1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (OpenOCD)
27 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
45 * About:: About OpenOCD.
46 * Developers:: OpenOCD developers
47 * Building:: Building OpenOCD
48 * Running:: Running OpenOCD
49 * Configuration:: OpenOCD Configuration.
50 * Target library:: Target library
51 * Commands:: OpenOCD Commands
52 * Sample Scripts:: Sample Target Scripts
53 * GDB and OpenOCD:: Using GDB and OpenOCD
54 * Upgrading:: Deprecated/Removed Commands
55 * FAQ:: Frequently Asked Questions
56 * License:: GNU Free Documentation License
64 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
65 and boundary-scan testing for embedded target devices. The targets are interfaced
66 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
67 connection types in the future.
69 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
70 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
71 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
72 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
74 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
75 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
76 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
82 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
83 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
84 Others interested in improving the state of free and open debug and testing technology
85 are welcome to participate.
87 Other developers have contributed support for additional targets and flashes as well
88 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
90 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
94 @cindex building OpenOCD
96 You can download the current SVN version with SVN client of your choice from the
97 following repositories:
99 (@uref{svn://svn.berlios.de/openocd/trunk})
103 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
105 Using the SVN command line client, you can use the following command to fetch the
106 latest version (make sure there is no (non-svn) directory called "openocd" in the
110 svn checkout svn://svn.berlios.de/openocd/trunk openocd
113 Building OpenOCD requires a recent version of the GNU autotools.
114 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
115 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
116 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
117 paths, resulting in obscure dependency errors (This is an observation I've gathered
118 from the logs of one user - correct me if I'm wrong).
120 You further need the appropriate driver files, if you want to build support for
121 a FTDI FT2232 based interface:
123 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
124 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
125 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
126 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
129 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
130 see contrib/libftdi for more details.
132 In general, the D2XX driver provides superior performance (several times as fast),
133 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
134 a kernel module, only a user space library.
136 To build OpenOCD (on both Linux and Cygwin), use the following commands:
140 Bootstrap generates the configure script, and prepares building on your system.
144 Configure generates the Makefiles used to build OpenOCD.
148 Make builds OpenOCD, and places the final executable in ./src/.
150 The configure script takes several options, specifying which JTAG interfaces
155 @option{--enable-parport}
157 @option{--enable-parport_ppdev}
159 @option{--enable-parport_giveio}
161 @option{--enable-amtjtagaccel}
163 @option{--enable-ft2232_ftd2xx}
164 @footnote{Using the latest D2XX drivers from FTDI and following their installation
165 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
168 @option{--enable-ft2232_libftdi}
170 @option{--with-ftd2xx=/path/to/d2xx/}
172 @option{--enable-gw16012}
174 @option{--enable-usbprog}
176 @option{--enable-presto_libftdi}
178 @option{--enable-presto_ftd2xx}
180 @option{--enable-jlink}
183 If you want to access the parallel port using the PPDEV interface you have to specify
184 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
185 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
186 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
188 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
189 absolute path containing no spaces.
191 Linux users should copy the various parts of the D2XX package to the appropriate
192 locations, i.e. /usr/include, /usr/lib.
196 @cindex running OpenOCD
198 @cindex --debug_level
201 OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
202 Run with @option{--help} or @option{-h} to view the available command line switches.
204 It reads its configuration by default from the file openocd.cfg located in the current
205 working directory. This may be overwritten with the @option{-f <configfile>} command line
206 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
207 are executed in order.
209 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
211 To enable debug output (when reporting problems or working on OpenOCD itself), use
212 the @option{-d} command line switch. This sets the debug_level to "3", outputting
213 the most information, including debug messages. The default setting is "2", outputting
214 only informational messages, warnings and errors. You can also change this setting
215 from within a telnet or gdb session (@option{debug_level <n>}).
217 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
219 Search paths for config/script files can be added to OpenOCD by using
220 the @option{-s <search>} switch. The current directory and the OpenOCD target library
221 is in the search path by default.
223 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
224 with the target. In general, it is possible for the JTAG controller to be unresponsive until
225 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
228 @chapter Configuration
229 @cindex configuration
230 OpenOCD runs as a daemon, and reads it current configuration
231 by default from the file openocd.cfg in the current directory. A different configuration
232 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
234 The configuration file is used to specify on which ports the daemon listens for new
235 connections, the JTAG interface used to connect to the target, the layout of the JTAG
236 chain, the targets that should be debugged, and connected flashes.
238 @section Daemon configuration
241 @item @b{init} This command terminates the configuration stage and enters the normal
242 command mode. This can be useful to add commands to the startup scripts and commands
243 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
244 add "init" and "reset" at the end of the config script or at the end of the
245 OpenOCD command line using the @option{-c} command line switch.
247 @item @b{telnet_port} <@var{number}>
249 Port on which to listen for incoming telnet connections
250 @item @b{gdb_port} <@var{number}>
252 First port on which to listen for incoming GDB connections. The GDB port for the
253 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
254 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
256 Configures what OpenOCD will do when gdb detaches from the daeman.
257 Default behaviour is <@var{resume}>
258 @item @b{gdb_memory_map} <@var{enable|disable}>
259 @cindex gdb_memory_map
260 Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
261 requested. gdb will then know when to set hardware breakpoints, and program flash
262 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
263 for flash programming to work.
264 Default behaviour is <@var{enable}>
265 @item @b{gdb_flash_program} <@var{enable|disable}>
266 @cindex gdb_flash_program
267 Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
268 vFlash packet is received.
269 Default behaviour is <@var{enable}>
270 @item @b{daemon_startup} <@var{mode}>
271 @cindex daemon_startup
272 @option{mode} can either @option{attach} or @option{reset}
273 This is equivalent to adding "init" and "reset" to the end of the config script.
275 It is available as a command mainly for backwards compatibility.
278 @section JTAG interface configuration
281 @item @b{interface} <@var{name}>
283 Use the interface driver <@var{name}> to connect to the target. Currently supported
287 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
290 @item @b{amt_jtagaccel}
291 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
296 FTDI FT2232 based devices using either the open-source libftdi or the binary only
297 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
298 platform. The libftdi uses libusb, and should be portable to all systems that provide
303 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
307 ASIX PRESTO USB JTAG programmer.
311 usbprog is a freely programmable USB adapter.
315 Gateworks GW16012 JTAG programmer.
319 Segger jlink usb adapter
324 @item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
326 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
327 speed. The actual effect of this option depends on the JTAG interface used. Reset
328 speed is used during reset and post reset speed after reset. post reset speed
329 is optional, in which case the reset speed is used.
332 @item wiggler: maximum speed / @var{number}
333 @item ft2232: 6MHz / (@var{number}+1)
334 @item amt jtagaccel: 8 / 2**@var{number}
335 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
338 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
339 especially true for synthesized cores (-S).
341 @item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
343 Same as jtag_speed, except that the speed is specified in maximum kHz. If
344 the device can not support the rate asked for, or can not translate from
345 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
346 is not supported, then an error is reported.
348 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
350 The configuration of the reset signals available on the JTAG interface AND the target.
351 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
352 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
353 @option{srst_only} or @option{trst_and_srst}.
355 [@var{combination}] is an optional value specifying broken reset signal implementations.
356 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
357 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
358 that the system is reset together with the test logic (only hypothetical, I haven't
359 seen hardware with such a bug, and can be worked around).
360 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
361 The default behaviour if no option given is @option{separate}.
363 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
364 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
365 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
366 (default) and @option{srst_push_pull} for the system reset. These values only affect
367 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
369 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
371 Describes the devices that form the JTAG daisy chain, with the first device being
372 the one closest to TDO. The parameters are the length of the instruction register
373 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
374 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
375 The IDCODE instruction will in future be used to query devices for their JTAG
376 identification code. This line is the same for all ARM7 and ARM9 devices.
377 Other devices, like CPLDs, require different parameters. An example configuration
378 line for a Xilinx XC9500 CPLD would look like this:
380 jtag_device 8 0x01 0x0e3 0xfe
382 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
383 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
384 The IDCODE instruction is 0xfe.
386 @item @b{jtag_nsrst_delay} <@var{ms}>
387 @cindex jtag_nsrst_delay
388 How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
389 starting new JTAG operations.
390 @item @b{jtag_ntrst_delay} <@var{ms}>
391 @cindex jtag_ntrst_delay
392 How long (in milliseconds) OpenOCD should wait after deasserting nTRST before
393 starting new JTAG operations.
395 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
396 or on-chip features) keep a reset line asserted for some time after the external reset
400 @section parport options
403 @item @b{parport_port} <@var{number}>
405 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
406 the @file{/dev/parport} device
408 When using PPDEV to access the parallel port, use the number of the parallel port:
409 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
410 you may encounter a problem.
411 @item @b{parport_cable} <@var{name}>
412 @cindex parport_cable
413 The layout of the parallel port cable used to connect to the target.
414 Currently supported cables are
418 The original Wiggler layout, also supported by several clones, such
419 as the Olimex ARM-JTAG
420 @item @b{old_amt_wiggler}
421 @cindex old_amt_wiggler
422 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
423 version available from the website uses the original Wiggler layout ('@var{wiggler}')
426 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.
429 The Xilinx Parallel cable III.
432 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
433 This is also the layout used by the HollyGates design
434 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
437 The ST Parallel cable.
439 @item @b{parport_write_on_exit} <@var{on|off}>
440 @cindex parport_write_on_exit
441 This will configure the parallel driver to write a known value to the parallel
442 interface on exiting OpenOCD
445 @section amt_jtagaccel options
447 @item @b{parport_port} <@var{number}>
449 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
450 @file{/dev/parport} device
452 @section ft2232 options
455 @item @b{ft2232_device_desc} <@var{description}>
456 @cindex ft2232_device_desc
457 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
458 default value is used. This setting is only valid if compiled with FTD2XX support.
459 @item @b{ft2232_layout} <@var{name}>
460 @cindex ft2232_layout
461 The layout of the FT2232 GPIO signals used to control output-enables and reset
462 signals. Valid layouts are
465 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
467 Amontec JTAGkey and JTAGkey-tiny
470 @item @b{olimex-jtag}
473 American Microsystems M5960
474 @item @b{evb_lm3s811}
475 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
476 SRST signals on external connector
480 Hitex STM32 Performance Stick
482 Tin Can Tools Flyswatter
483 @item @b{turtelizer2}
484 egnite Software turtelizer2
489 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
490 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
491 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
493 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
495 @item @b{ft2232_latency} <@var{ms}>
496 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
497 ft2232_read() fails to return the expected number of bytes. This can be caused by
498 USB communication delays and has proved hard to reproduce and debug. Setting the
499 FT2232 latency timer to a larger value increases delays for short USB packages but it
500 also reduces the risk of timeouts before receiving the expected number of bytes.
501 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
504 @section ep93xx options
505 @cindex ep93xx options
506 Currently, there are no options available for the ep93xx interface.
509 @section Target configuration
512 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
515 Defines a target that should be debugged. Currently supported types are:
529 If you want to use a target board that is not on this list, see Adding a new
532 Endianess may be @option{little} or @option{big}.
534 The reset_mode specifies what should happen to the target when a reset occurs:
538 Immediately request a target halt after reset. This allows targets to be debugged
539 from the very first instruction. This is only possible with targets and JTAG
540 interfaces that correctly implement the reset signals.
543 Similar to @option{reset_halt}, but executes the script file defined to handle the
544 'reset' event for the target. Like @option{reset_halt} this only works with
545 correct reset implementations.
548 Simply let the target run after a reset.
549 @item @b{run_and_halt}
551 Let the target run for some time (default: 1s), and then request halt.
552 @item @b{run_and_init}
554 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
555 to run for some time, then halted, and the @option{reset} event script is executed.
558 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
559 completely independent (like the LPC2000 series), or where the JTAG interface is
560 unavailable for some time during startup (like the STR7 series), you can't use
561 @option{reset_halt} or @option{reset_init}.
563 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
564 @cindex target_script
565 Event is one of the following:
566 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
567 @option{pre_resume} or @option{gdb_program_config}.
568 @option{post_reset} and @option{reset} will produce the same results.
570 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
571 @cindex run_and_halt_time
572 The amount of time the debugger should wait after releasing reset before it asserts
573 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
575 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
576 <@var{backup}|@var{nobackup}>
578 Specifies a working area for the debugger to use. This may be used to speed-up
579 downloads to target memory and flash operations, or to perform otherwise unavailable
580 operations (some coprocessor operations on ARM7/9 systems, for example). The last
581 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
582 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
585 @subsection arm7tdmi options
586 @cindex arm7tdmi options
587 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
588 The arm7tdmi target definition requires at least one additional argument, specifying
589 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
590 The optional [@var{variant}] parameter has been removed in recent versions.
591 The correct feature set is determined at runtime.
593 @subsection arm720t options
594 @cindex arm720t options
595 ARM720t options are similar to ARM7TDMI options.
597 @subsection arm9tdmi options
598 @cindex arm9tdmi options
599 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
600 @option{arm920t}, @option{arm922t} and @option{arm940t}.
601 This enables the hardware single-stepping support found on these cores.
603 @subsection arm920t options
604 @cindex arm920t options
605 ARM920t options are similar to ARM9TDMI options.
607 @subsection arm966e options
608 @cindex arm966e options
609 ARM966e options are similar to ARM9TDMI options.
611 @subsection cortex_m3 options
612 @cindex cortex_m3 options
613 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
614 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
615 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
616 be detected and the normal reset behaviour used.
618 @subsection xscale options
619 @cindex xscale options
620 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
621 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
623 @section Flash configuration
624 @cindex Flash configuration
627 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
628 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
630 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
631 and <@var{bus_width}> bytes using the selected flash <driver>.
634 @subsection lpc2000 options
635 @cindex lpc2000 options
637 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
638 <@var{clock}> [@var{calc_checksum}]
639 LPC flashes don't require the chip and bus width to be specified. Additional
640 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
641 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
642 of the target this flash belongs to (first is 0), the frequency at which the core
643 is currently running (in kHz - must be an integral number), and the optional keyword
644 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
647 @subsection cfi options
650 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
652 CFI flashes require the number of the target they're connected to as an additional
653 argument. The CFI driver makes use of a working area (specified for the target)
654 to significantly speed up operation.
656 @var{chip_width} and @var{bus_width} are specified in bytes.
658 @subsection at91sam7 options
659 @cindex at91sam7 options
661 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
662 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
663 reading the chip-id and type.
665 @subsection str7 options
668 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
669 variant can be either STR71x, STR73x or STR75x.
671 @subsection str9 options
674 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
675 The str9 needs the flash controller to be configured prior to Flash programming, eg.
677 str9x flash_config 0 4 2 0 0x80000
679 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
681 @subsection str9 options (str9xpec driver)
683 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
684 Before using the flash commands the turbo mode will need enabling using str9xpec
685 @option{enable_turbo} <@var{num>.}
687 Only use this driver for locking/unlocking the device or configuring the option bytes.
688 Use the standard str9 driver for programming.
690 @subsection stellaris (LM3Sxxx) options
691 @cindex stellaris (LM3Sxxx) options
693 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
694 stellaris flash plugin only require the @var{target#}.
696 @subsection stm32x options
697 @cindex stm32x options
699 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
700 stm32x flash plugin only require the @var{target#}.
703 @chapter Target library
704 @cindex Target library
706 OpenOCD comes with a target configuration script library. These scripts can be
707 used as-is or serve as a starting point.
709 The target library is published together with the openocd executable and
710 the path to the target library is in the OpenOCD script search path.
711 Similarly there are example scripts for configuring the JTAG interface.
713 The command line below uses the example parport configuration scripts
714 that ship with OpenOCD, then configures the str710.cfg target and
715 finally issues the init and reset command. The communication speed
716 is set to 10kHz for reset and 8MHz for post reset.
720 openocd -f interface/parport.cfg -c "jtag_khz 10 8000" -f target/str710.cfg -c "init" -c "reset"
724 To list the target scripts available:
727 $ ls /usr/local/lib/openocd/target
729 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
730 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
731 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
732 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
740 OpenOCD allows user interaction through a telnet interface
741 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
742 is available from both the telnet interface and a GDB session. To issue commands to the
743 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
744 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
750 @item @b{sleep} <@var{msec}>
752 Wait for n milliseconds before resuming. Useful in connection with script files
753 (@var{script} command and @var{target_script} configuration).
757 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
759 @item @b{debug_level} [@var{n}]
761 Display or adjust debug level to n<0-3>
763 @item @b{fast} [@var{enable/disable}]
765 Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
766 downloads and fast memory access will work if the JTAG interface isn't too fast and
767 the core doesn't run at a too low frequency. Note that this option only changes the default
768 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
771 The target specific "dangerous" optimisation tweaking options may come and go
772 as more robust and user friendly ways are found to ensure maximum throughput
773 and robustness with a minimum of configuration.
775 Typically the "fast enable" is specified first on the command line:
778 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
781 @item @b{log_output} <@var{file}>
783 Redirect logging to <file> (default: stderr)
785 @item @b{script} <@var{file}>
787 Execute commands from <file>
791 @subsection Target state handling
793 @item @b{poll} [@option{on}|@option{off}]
795 Poll the target for its current state. If the target is in debug mode, architecture
796 specific information about the current state is printed. An optional parameter
797 allows continuous polling to be enabled and disabled.
799 @item @b{halt} [@option{ms}]
801 Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
802 Default [@option{ms}] is 5 seconds if no arg given.
803 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
804 will stop OpenOCD from waiting.
806 @item @b{wait_halt} [@option{ms}]
808 Wait for the target to enter debug mode. Optional [@option{ms}] is
809 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
812 @item @b{resume} [@var{address}]
814 Resume the target at its current code position, or at an optional address.
815 OpenOCD will wait 5 seconds for the target to resume.
817 @item @b{step} [@var{address}]
819 Single-step the target at its current code position, or at an optional address.
821 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
822 |@option{run_and_init}]
824 Perform a hard-reset. The optional parameter specifies what should happen after the reset.
825 This optional parameter overrides the setting specified in the configuration file,
826 making the new behaviour the default for the @option{reset} command.
833 Immediately halt the target (works only with certain configurations).
836 Immediately halt the target, and execute the reset script (works only with certain
838 @item @b{run_and_halt}
839 @cindex reset run_and_halt
840 Let the target run for a certain amount of time, then request a halt.
841 @item @b{run_and_init}
842 @cindex reset run_and_init
843 Let the target run for a certain amount of time, then request a halt. Execute the
844 reset script once the target enters debug mode.
848 @subsection Memory access commands
849 These commands allow accesses of a specific size to the memory system:
851 @item @b{mdw} <@var{addr}> [@var{count}]
854 @item @b{mdh} <@var{addr}> [@var{count}]
856 display memory half-words
857 @item @b{mdb} <@var{addr}> [@var{count}]
860 @item @b{mww} <@var{addr}> <@var{value}>
863 @item @b{mwh} <@var{addr}> <@var{value}>
865 write memory half-word
866 @item @b{mwb} <@var{addr}> <@var{value}>
870 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
872 Load image <@var{file}> to target memory at <@var{address}>
873 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
875 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
876 (binary) <@var{file}>.
877 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
879 Verify <@var{file}> against target memory starting at <@var{address}>.
880 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
883 @subsection Flash commands
884 @cindex Flash commands
886 @item @b{flash banks}
888 List configured flash banks
889 @item @b{flash info} <@var{num}>
891 Print info about flash bank <@option{num}>
892 @item @b{flash probe} <@var{num}>
894 Identify the flash, or validate the parameters of the configured flash. Operation
895 depends on the flash type.
896 @item @b{flash erase_check} <@var{num}>
897 @cindex flash erase_check
898 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
899 updates the erase state information displayed by @option{flash info}. That means you have
900 to issue an @option{erase_check} command after erasing or programming the device to get
902 @item @b{flash protect_check} <@var{num}>
903 @cindex flash protect_check
904 Check protection state of sectors in flash bank <num>.
905 @option{flash erase_sector} using the same syntax.
906 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
907 @cindex flash erase_sector
908 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
909 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
910 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
912 @item @b{flash erase_address} <@var{address}> <@var{length}>
913 @cindex flash erase_address
914 Erase sectors starting at <@var{address}> for <@var{length}> bytes
915 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
916 @cindex flash write_bank
917 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
918 <@option{offset}> bytes from the beginning of the bank.
919 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
920 @cindex flash write_image
921 Write the image <@var{file}> to the current target's flash bank(s). A relocation
922 [@var{offset}] can be specified and the file [@var{type}] can be specified
923 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
924 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
925 if the @option{erase} parameter is given.
926 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
927 @cindex flash protect
928 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
929 <@var{last}> of @option{flash bank} <@var{num}>.
933 @section Target Specific Commands
934 @cindex Target Specific Commands
936 @subsection AT91SAM7 specific commands
937 @cindex AT91SAM7 specific commands
938 The flash configuration is deduced from the chip identification register. The flash
939 controller handles erases automatically on a page (128/265 byte) basis so erase is
940 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
941 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
942 that can be erased separatly. Only an EraseAll command is supported by the controller
943 for each flash plane and this is called with
945 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
946 bulk erase flash planes first_plane to last_plane.
947 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
948 @cindex at91sam7 gpnvm
949 set or clear a gpnvm bit for the processor
952 @subsection STR9 specific commands
953 @cindex STR9 specific commands
954 These are flash specific commands when using the str9xpec driver.
956 @item @b{str9xpec enable_turbo} <@var{num}>
957 @cindex str9xpec enable_turbo
958 enable turbo mode, simply this will remove the str9 from the chain and talk
959 directly to the embedded flash controller.
960 @item @b{str9xpec disable_turbo} <@var{num}>
961 @cindex str9xpec disable_turbo
962 restore the str9 into jtag chain.
963 @item @b{str9xpec lock} <@var{num}>
964 @cindex str9xpec lock
965 lock str9 device. The str9 will only respond to an unlock command that will
967 @item @b{str9xpec unlock} <@var{num}>
968 @cindex str9xpec unlock
970 @item @b{str9xpec options_read} <@var{num}>
971 @cindex str9xpec options_read
972 read str9 option bytes.
973 @item @b{str9xpec options_write} <@var{num}>
974 @cindex str9xpec options_write
975 write str9 option bytes.
978 @subsection STR9 configuration
979 @cindex STR9 configuration
981 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
982 <@var{BBADR}> <@var{NBBADR}>
983 @cindex str9x flash_config
984 Configure str9 flash controller.
986 eg. str9x flash_config 0 4 2 0 0x80000
988 BBSR - Boot Bank Size register
989 NBBSR - Non Boot Bank Size register
990 BBADR - Boot Bank Start Address register
991 NBBADR - Boot Bank Start Address register
995 @subsection STR9 option byte configuration
996 @cindex STR9 option byte configuration
998 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
999 @cindex str9xpec options_cmap
1000 configure str9 boot bank.
1001 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
1002 @cindex str9xpec options_lvdthd
1003 configure str9 lvd threshold.
1004 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
1005 @cindex str9xpec options_lvdsel
1006 configure str9 lvd source.
1007 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
1008 @cindex str9xpec options_lvdwarn
1009 configure str9 lvd reset warning source.
1012 @subsection STM32x specific commands
1013 @cindex STM32x specific commands
1015 These are flash specific commands when using the stm32x driver.
1017 @item @b{stm32x lock} <@var{num}>
1020 @item @b{stm32x unlock} <@var{num}>
1021 @cindex stm32x unlock
1022 unlock stm32 device.
1023 @item @b{stm32x options_read} <@var{num}>
1024 @cindex stm32x options_read
1025 read stm32 option bytes.
1026 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1027 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1028 @cindex stm32x options_write
1029 write stm32 option bytes.
1030 @item @b{stm32x mass_erase} <@var{num}>
1031 @cindex stm32x mass_erase
1032 mass erase flash memory.
1035 @subsection Stellaris specific commands
1036 @cindex Stellaris specific commands
1038 These are flash specific commands when using the Stellaris driver.
1040 @item @b{stellaris mass_erase} <@var{num}>
1041 @cindex stellaris mass_erase
1042 mass erase flash memory.
1046 @section Architecture Specific Commands
1047 @cindex Architecture Specific Commands
1049 @subsection ARMV4/5 specific commands
1050 @cindex ARMV4/5 specific commands
1052 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1053 or Intel XScale (XScale isn't supported yet).
1055 @item @b{armv4_5 reg}
1057 Display a list of all banked core registers, fetching the current value from every
1058 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1060 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1061 @cindex armv4_5 core_mode
1062 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1063 The target is resumed in the currently set @option{core_mode}.
1066 @subsection ARM7/9 specific commands
1067 @cindex ARM7/9 specific commands
1069 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1070 ARM920t or ARM926EJ-S.
1072 @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
1073 @cindex arm7_9 sw_bkpts
1074 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
1075 one of the watchpoint registers to implement software breakpoints. Disabling
1076 SW Bkpts frees that register again.
1077 @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
1078 @cindex arm7_9 force_hw_bkpts
1079 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
1080 breakpoints are turned into hardware breakpoints.
1081 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1082 @cindex arm7_9 dbgrq
1083 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1084 safe for all but ARM7TDMI--S cores (like Philips LPC).
1085 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1086 @cindex arm7_9 fast_memory_access
1087 Allow OpenOCD to read and write memory without checking completion of
1088 the operation. This provides a huge speed increase, especially with USB JTAG
1089 cables (FT2232), but might be unsafe if used with targets running at a very low
1090 speed, like the 32kHz startup clock of an AT91RM9200.
1091 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1092 @cindex arm7_9 dcc_downloads
1093 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1094 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1095 unsafe, especially with targets running at a very low speed. This command was introduced
1096 with OpenOCD rev. 60.
1099 @subsection ARM720T specific commands
1100 @cindex ARM720T specific commands
1103 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1104 @cindex arm720t cp15
1105 display/modify cp15 register <@option{num}> [@option{value}].
1106 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1107 @cindex arm720t md<bhw>_phys
1108 Display memory at physical address addr.
1109 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1110 @cindex arm720t mw<bhw>_phys
1111 Write memory at physical address addr.
1112 @item @b{arm720t virt2phys} <@var{va}>
1113 @cindex arm720t virt2phys
1114 Translate a virtual address to a physical address.
1117 @subsection ARM9TDMI specific commands
1118 @cindex ARM9TDMI specific commands
1121 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1122 @cindex arm9tdmi vector_catch
1123 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1124 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1125 @option{irq} @option{fiq}.
1127 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1130 @subsection ARM966E specific commands
1131 @cindex ARM966E specific commands
1134 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1135 @cindex arm966e cp15
1136 display/modify cp15 register <@option{num}> [@option{value}].
1139 @subsection ARM920T specific commands
1140 @cindex ARM920T specific commands
1143 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1144 @cindex arm920t cp15
1145 display/modify cp15 register <@option{num}> [@option{value}].
1146 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1147 @cindex arm920t cp15i
1148 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1149 @item @b{arm920t cache_info}
1150 @cindex arm920t cache_info
1151 Print information about the caches found. This allows you to see if your target
1152 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1153 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1154 @cindex arm920t md<bhw>_phys
1155 Display memory at physical address addr.
1156 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1157 @cindex arm920t mw<bhw>_phys
1158 Write memory at physical address addr.
1159 @item @b{arm920t read_cache} <@var{filename}>
1160 @cindex arm920t read_cache
1161 Dump the content of ICache and DCache to a file.
1162 @item @b{arm920t read_mmu} <@var{filename}>
1163 @cindex arm920t read_mmu
1164 Dump the content of the ITLB and DTLB to a file.
1165 @item @b{arm920t virt2phys} <@var{va}>
1166 @cindex arm920t virt2phys
1167 Translate a virtual address to a physical address.
1170 @subsection ARM926EJS specific commands
1171 @cindex ARM926EJS specific commands
1174 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1175 @cindex arm926ejs cp15
1176 display/modify cp15 register <@option{num}> [@option{value}].
1177 @item @b{arm926ejs cache_info}
1178 @cindex arm926ejs cache_info
1179 Print information about the caches found.
1180 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1181 @cindex arm926ejs md<bhw>_phys
1182 Display memory at physical address addr.
1183 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1184 @cindex arm926ejs mw<bhw>_phys
1185 Write memory at physical address addr.
1186 @item @b{arm926ejs virt2phys} <@var{va}>
1187 @cindex arm926ejs virt2phys
1188 Translate a virtual address to a physical address.
1192 @section Debug commands
1193 @cindex Debug commands
1194 The following commands give direct access to the core, and are most likely
1195 only useful while debugging OpenOCD.
1197 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1198 @cindex arm7_9 write_xpsr
1199 Immediately write either the current program status register (CPSR) or the saved
1200 program status register (SPSR), without changing the register cache (as displayed
1201 by the @option{reg} and @option{armv4_5 reg} commands).
1202 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1203 <@var{0=cpsr},@var{1=spsr}>
1204 @cindex arm7_9 write_xpsr_im8
1205 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1206 operation (similar to @option{write_xpsr}).
1207 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1208 @cindex arm7_9 write_core_reg
1209 Write a core register, without changing the register cache (as displayed by the
1210 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1211 encoding of the [M4:M0] bits of the PSR.
1215 @section JTAG commands
1216 @cindex JTAG commands
1218 @item @b{scan_chain}
1220 Print current scan chain configuration.
1221 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1224 @item @b{endstate} <@var{tap_state}>
1226 Finish JTAG operations in <@var{tap_state}>.
1227 @item @b{runtest} <@var{num_cycles}>
1229 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1230 @item @b{statemove} [@var{tap_state}]
1232 Move to current endstate or [@var{tap_state}]
1233 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1235 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1236 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1238 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1239 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1240 @cindex verify_ircapture
1241 Verify value captured during Capture-IR. Default is enabled.
1242 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1244 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1245 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1247 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1251 @section Target Requests
1252 @cindex Target Requests
1253 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1254 See libdcc in the contrib dir for more details.
1256 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1257 @cindex target_request debugmsgs
1258 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1261 @node Sample Scripts
1262 @chapter Sample Scripts
1265 This page shows how to use the target library.
1267 The configuration script can be divided in the following section:
1269 @item daemon configuration
1271 @item jtag scan chain
1272 @item target configuration
1273 @item flash configuration
1276 Detailed information about each section can be found at OpenOCD configuration.
1278 @section AT91R40008 example
1279 @cindex AT91R40008 example
1280 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1281 the CPU upon startup of the OpenOCD daemon.
1283 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1287 @node GDB and OpenOCD
1288 @chapter GDB and OpenOCD
1289 @cindex GDB and OpenOCD
1290 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1291 to debug remote targets.
1293 @section Connecting to gdb
1294 @cindex Connecting to gdb
1295 A connection is typically started as follows:
1297 target remote localhost:3333
1299 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1301 To see a list of available OpenOCD commands type @option{monitor help} on the
1304 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1305 to be sent by the gdb server (openocd) to gdb. Typical information includes
1306 packet size and device memory map.
1308 Previous versions of OpenOCD required the following gdb options to increase
1309 the packet size and speed up gdb communication.
1311 set remote memory-write-packet-size 1024
1312 set remote memory-write-packet-size fixed
1313 set remote memory-read-packet-size 1024
1314 set remote memory-read-packet-size fixed
1316 This is now handled in the @option{qSupported} PacketSize.
1318 @section Programming using gdb
1319 @cindex Programming using gdb
1321 By default the target memory map is sent to gdb, this can be disabled by
1322 the following OpenOCD config option:
1324 gdb_memory_map disable
1326 For this to function correctly a valid flash config must also be configured
1327 in OpenOCD. For faster performance you should also configure a valid
1330 Informing gdb of the memory map of the target will enable gdb to protect any
1331 flash area of the target and use hardware breakpoints by default. This means
1332 that the OpenOCD option @option{arm7_9 force_hw_bkpts} is not required when
1335 To view the configured memory map in gdb, use the gdb command @option{info mem}
1336 All other unasigned addresses within gdb are treated as RAM.
1338 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1339 this can be changed to the old behaviour by using the following gdb command.
1341 set mem inaccessible-by-default off
1344 If @option{gdb_flash_program enable} is also used, gdb will be able to
1345 program any flash memory using the vFlash interface.
1347 gdb will look at the target memory map when a load command is given, if any
1348 areas to be programmed lie within the target flash area the vFlash packets
1351 If the target needs configuring before gdb programming, a script can be executed.
1353 target_script 0 gdb_program_config config.script
1356 To verify any flash programming the gdb command @option{compare-sections}
1360 @chapter Deprecated/Removed Commands
1361 @cindex Deprecated/Removed Commands
1362 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1365 @item @b{load_binary}
1367 use @option{load_image} command with same args
1368 @item @b{dump_binary}
1370 use @option{dump_image} command with same args
1371 @item @b{flash erase}
1373 use @option{flash erase_sector} command with same args
1374 @item @b{flash write}
1376 use @option{flash write_bank} command with same args
1377 @item @b{flash write_binary}
1378 @cindex flash write_binary
1379 use @option{flash write_bank} command with same args
1380 @item @b{arm7_9 fast_writes}
1381 @cindex arm7_9 fast_writes
1382 use @option{arm7_9 fast_memory_access} command with same args
1383 @item @b{flash auto_erase}
1384 @cindex flash auto_erase
1385 use @option{flash write_image} command passing @option{erase} as the first parameter.
1392 @item OpenOCD complains about a missing cygwin1.dll.
1394 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1395 claims to come with all the necessary dlls. When using Cygwin, try launching
1396 OpenOCD from the Cygwin shell.
1398 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1399 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1400 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1402 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1403 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1404 software breakpoints consume one of the two available hardware breakpoints,
1405 and are therefore disabled by default. If your code is running from RAM, you
1406 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1407 your code resides in Flash, you can't use software breakpoints, but you can force
1408 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1410 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1411 and works sometimes fine.
1413 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1414 clock at the time you're programming the flash. If you've specified the crystal's
1415 frequency, make sure the PLL is disabled, if you've specified the full core speed
1416 (e.g. 60MHz), make sure the PLL is enabled.
1418 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1419 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1420 out while waiting for end of scan, rtck was disabled".
1422 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1423 settings in your PC BIOS (ECP, EPP, and different versions of those).
1425 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1426 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1427 memory read caused data abort".
1429 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1430 beyond the last valid frame. It might be possible to prevent this by setting up
1431 a proper "initial" stack frame, if you happen to know what exactly has to
1432 be done, feel free to add this here.
1434 @item I get the following message in the OpenOCD console (or log file):
1435 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1437 This warning doesn't indicate any serious problem, as long as you don't want to
1438 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1439 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
1440 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1441 independently. With this setup, it's not possible to halt the core right out of
1442 reset, everything else should work fine.
1444 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1445 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1446 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1447 quit with an error message. Is there a stability issue with OpenOCD?
1449 No, this is not a stability issue concerning OpenOCD. Most users have solved
1450 this issue by simply using a self-powered USB hub, which they connect their
1451 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1452 supply stable enough for the Amontec JTAGkey to be operated.
1454 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1455 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1456 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1457 What does that mean and what might be the reason for this?
1459 First of all, the reason might be the USB power supply. Try using a self-powered
1460 hub instead of a direct connection to your computer. Secondly, the error code 4
1461 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1462 chip ran into some sort of error - this points us to a USB problem.
1464 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1465 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1466 What does that mean and what might be the reason for this?
1468 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1469 has closed the connection to OpenOCD. This might be a GDB issue.
1471 @item In the configuration file in the section where flash device configurations
1472 are described, there is a parameter for specifying the clock frequency for
1473 LPC2000 internal flash devices (e.g.
1474 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1475 which must be specified in kilohertz. However, I do have a quartz crystal of a
1476 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1477 Is it possible to specify real numbers for the clock frequency?
1479 No. The clock frequency specified here must be given as an integral number.
1480 However, this clock frequency is used by the In-Application-Programming (IAP)
1481 routines of the LPC2000 family only, which seems to be very tolerant concerning
1482 the given clock frequency, so a slight difference between the specified clock
1483 frequency and the actual clock frequency will not cause any trouble.
1485 @item Do I have to keep a specific order for the commands in the configuration file?
1487 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1488 listed for the JTAG scan chain must be given in the right order (jtag_device),
1489 with the device closest to the TDO-Pin being listed first. In general,
1490 whenever objects of the same type exist which require an index number, then
1491 these objects must be given in the right order (jtag_devices, targets and flash
1492 banks - a target references a jtag_device and a flash bank references a target).
1494 @item Sometimes my debugging session terminates with an error. When I look into the
1495 log file, I can see these error messages: Error: arm7_9_common.c:561
1496 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP