1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
10 @title Open On-Chip Debugger (openocd)
11 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
12 @subtitle @value{UPDATED}
14 @vskip 0pt plus 1filll
19 @node Top, About, , (dir)
22 This is edition @value{EDITION} of the openocd manual for version
23 @value{VERSION}, @value{UPDATED}
26 * About:: About Openocd.
28 * Building:: Building Openocd
29 * Running:: Running Openocd
30 * Configuration:: Openocd Configuration.
31 * Commands:: Openocd Commands
32 * Sample Scripts:: Sample Target Scripts
33 * GDB and Openocd:: Using GDB and Openocd
34 * FAQ:: Frequently Asked Questions
35 * License:: GNU Free Documentation License
43 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
44 and boundary-scan testing for embedded target devices. The targets are interfaced
45 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
46 connection types in the future.
48 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
49 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
50 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
51 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
53 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
54 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
55 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
61 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
62 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
63 Others interested in improving the state of free and open debug and testing technology
64 are welcome to participate.
66 Other developers have contributed support for additional targets and flashes as well
67 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
71 @cindex building openocd
73 You can download the current SVN version with SVN client of your choice from the
74 following repositories:
76 (@uref{svn://svn.berlios.de/openocd/trunk})
80 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
82 Using the SVN command line client, you could use the following command to fetch the
83 latest version (make sure there is no (non-svn) directory called "openocd" in the
87 svn checkout svn://svn.berlios.de/openocd/trunk
90 Building the OpenOCD requires a recent version of the GNU autotools.
91 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
92 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
93 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
94 paths, resulting in obscure dependency errors (This is an observation I've gathered
95 from the logs of one user - correct me if I'm wrong).
97 You further need the appropriate driver files, if you want to build support for
98 a FTDI FT2232 based interface:
100 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
101 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
102 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
103 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
106 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
107 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
109 In general, the D2XX driver provides superior performance (several times as fast),
110 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
111 a kernel module, only a user space library.
113 To build OpenOCD (on both Linux and Cygwin), use the following commands:
117 Bootstrap generates the configure script, and prepares building on your system.
121 Configure generates the Makefiles used to build OpenOCD
125 Make builds the OpenOCD, and places the final executable in ./src/
127 The configure script takes several options, specifying which JTAG interfaces
134 --enable-parport_ppdev
136 --enable-amtjtagaccel
138 --enable-ft2232_ftd2xx
139 @footnote{Using the latest D2XX drivers from FTDI and following their installation
140 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
143 --enable-ft2232_libftdi
145 --with-ftd2xx=/path/to/d2xx/
148 If you want to access the parallel port using the PPDEV interface you have to specify
149 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
150 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
151 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
153 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
154 absolute path containing no spaces.
156 Linux users should copy the various parts of the D2XX package to the appropriate
157 locations, i.e. /usr/include, /usr/lib.
161 @cindex running openocd
163 @cindex --debug_level
166 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
167 Run with @option{--help} or @option{-h} to view the available command line arguments.
169 It reads its configuration by default from the file openocd.cfg located in the current
170 working directory. This may be overwritten with the @option{-f <configfile>} command line
173 To enable debug output (when reporting problems or working on OpenOCD itself), use
174 the @option{-d} command line switch. This sets the debug_level to "3", outputting
175 the most information, including debug messages. The default setting is "2", outputting
176 only informational messages, warnings and errors. You can also change this setting
177 from within a telnet or gdb session (@option{debug_level <n>}).
179 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
181 Search paths for config/script files can be added to openocd by using
182 the @option{-s <search>} switch.
185 @chapter Configuration
186 @cindex configuration
187 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
188 by default from the file openocd.cfg in the current directory. A different configuration
189 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
191 The configuration file is used to specify on which ports the daemon listens for new
192 connections, the JTAG interface used to connect to the target, the layout of the JTAG
193 chain, the targets that should be debugged, and connected flashes.
195 @section Daemon configuration
198 @item @b{telnet_port} <@var{number}>
200 Port on which to listen for incoming telnet connections
201 @item @b{gdb_port} <@var{number}>
203 First port on which to listen for incoming GDB connections. The GDB port for the
204 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
205 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
207 Configures what openocd will do when gdb detaches from the daeman.
208 Default behaviour is <@var{resume}>
209 @item @b{gdb_memory_map} <@var{enable|disable}>
210 @cindex gdb_memory_map
211 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
212 requested. gdb will then know when to set hardware breakpoints, and program flash
213 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
214 for flash programming to work.
215 Default behaviour is <@var{disable}>
216 @item @b{gdb_flash_program} <@var{enable|disable}>
217 @cindex gdb_flash_program
218 Set to <@var{enable}> so that openocd will program the flash memory when a
219 vFlash packet is received.
220 Default behaviour is <@var{disable}>
221 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
222 @cindex daemon_startup
223 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
224 if it should just attach to the target.
227 @section JTAG interface configuration
230 @item @b{interface} <@var{name}>
232 Use the interface driver <@var{name}> to connect to the target. Currently supported
236 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
240 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
245 FTDI FT2232 based devices using either the open-source libftdi or the binary only
246 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
247 platform. The libftdi uses libusb, and should be portable to all systems that provide
252 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
257 @item @b{jtag_speed} <@var{number}>
259 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
260 speed. The actual effect of this option depends on the JTAG interface used.
263 @item wiggler: maximum speed / @var{number}
264 @item ft2232: 6MHz / (@var{number}+1)
265 @item amt jtagaccel: 8 / 2**@var{number}
268 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
269 especially true for synthesized cores (-S).
271 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
273 The configuration of the reset signals available on the JTAG interface AND the target.
274 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
275 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
276 @samp{srst_only} or @samp{trst_and_srst}.
277 [@var{combination}] is an optional value specifying broken reset signal implementations.
278 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
279 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
280 that the system is reset together with the test logic (only hypothetical, I haven't
281 seen hardware with such a bug, and can be worked around).
283 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
284 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
285 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
286 (default) and @samp{srst_push_pull} for the system reset. These values only affect
287 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
289 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
291 Describes the devices that form the JTAG daisy chain, with the first device being
292 the one closest to TDO. The parameters are the length of the instruction register
293 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
294 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
295 The IDCODE instruction will in future be used to query devices for their JTAG
296 identification code. This line is the same for all ARM7 and ARM9 devices.
297 Other devices, like CPLDs, require different parameters. An example configuration
298 line for a Xilinx XC9500 CPLD would look like this:
300 jtag_device 8 0x01 0x0e3 0xfe
302 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
303 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
304 The IDCODE instruction is 0xfe.
306 @item @b{jtag_nsrst_delay} <@var{ms}>
307 @cindex jtag_nsrst_delay
308 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
309 starting new JTAG operations.
310 @item @b{jtag_ntrst_delay} <@var{ms}>
311 @cindex jtag_ntrst_delay
312 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
313 starting new JTAG operations.
315 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
316 or on-chip features) keep a reset line asserted for some time after the external reset
320 @section parport options
323 @item @b{parport_port} <@var{number}>
325 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
326 the @file{/dev/parport} device
328 When using PPDEV to access the parallel port, use the number of the parallel port:
329 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
330 you may encounter a problem.
331 @item @b{parport_cable} <@var{name}>
332 @cindex parport_cable
333 The layout of the parallel port cable used to connect to the target.
334 Currently supported cables are
338 Original Wiggler layout, also supported by several clones, such
339 as the Olimex ARM-JTAG
340 @item old_amt_wiggler
341 @cindex old_amt_wiggler
342 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
343 version available from the website uses the original Wiggler layout ('@var{wiggler}')
346 Describes the connection of the Amontec Chameleon's CPLD when operated in
347 configuration mode. This is only used to program the Chameleon itself, not
351 Xilinx Parallel cable III.
354 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
355 This is also the layout used by the HollyGates design
356 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
361 @item @b{parport_write_on_exit} <@var{on|off}>
362 @cindex parport_write_on_exit
363 This will configure the parallel driver to write a known value to the parallel
364 interface on exiting openocd
367 @section amt_jtagaccel options
369 @item @b{parport_port} <@var{number}>
371 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
372 @file{/dev/parport} device
374 @section ft2232 options
377 @item @b{ft2232_device_desc} <@var{description}>
378 @cindex ft2232_device_desc
379 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
380 default value is used. This setting is only valid if compiled with FTD2XX support.
381 @item @b{ft2232_layout} <@var{name}>
382 @cindex ft2232_layout
383 The layout of the FT2232 GPIO signals used to control output-enables and reset
384 signals. Valid layouts are
387 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
389 Amontec JTAGkey and JTAGkey-tiny
395 American Microsystems M5960
397 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
398 SRST signals on external connector
402 Hitex STM32 Performance Stick
404 Tin Can Tools Flyswatter
406 egnite Software turtelizer2
411 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
412 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
413 default values are used. This command is not available on Windows.
414 @item @b{ft2232_latency} <@var{ms}>
415 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
416 ft2232_read() fails to return the expected number of bytes. This can be caused by
417 USB communication delays and has proved hard to reproduce and debug. Setting the
418 FT2232 latency timer to a larger value increases delays for short USB packages but it
419 also reduces the risk of timeouts before receiving the expected number of bytes.
420 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
423 @section ep93xx options
424 @cindex ep93xx options
425 Currently, there are no options available for the ep93xx interface.
428 @section Target configuration
431 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
434 Defines a target that should be debugged. Currently supported types are:
447 If you want to use a target board that is not on this list, see Adding a new
450 Endianess may be @option{little} or @option{big}.
452 The reset_mode specifies what should happen to the target when a reset occurs:
456 Immediately request a target halt after reset. This allows targets to be debugged
457 from the very first instruction. This is only possible with targets and JTAG
458 interfaces that correctly implement the reset signals.
461 Similar to @option{reset_halt}, but executes the script file defined to handle the
462 'reset' event for the target. Like @option{reset_halt} this only works with
463 correct reset implementations.
466 Simply let the target run after a reset.
469 Let the target run for some time (default: 1s), and then request halt.
472 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
473 to run for some time, then halted, and the @option{reset} event script is executed.
476 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
477 completely independent (like the LPC2000 series), or where the JTAG interface is
478 unavailable for some time during startup (like the STR7 series), you can't use
479 @option{reset_halt} or @option{reset_init}.
481 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
482 @cindex target_script
483 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
485 TODO: describe exact semantic of events
486 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
487 @cindex run_and_halt_time
488 The amount of time the debugger should wait after releasing reset before it asserts
489 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
491 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
492 <@var{backup}|@var{nobackup}>
494 Specifies a working area for the debugger to use. This may be used to speed-up
495 downloads to target memory and flash operations, or to perform otherwise unavailable
496 operations (some coprocessor operations on ARM7/9 systems, for example). The last
497 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
498 a working_area that doesn't need to be backed up, as that slows down operation.
501 @subsection arm7tdmi options
502 @cindex arm7tdmi options
503 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
504 The arm7tdmi target definition requires at least one additional argument, specifying
505 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
506 The optional [@var{variant}] parameter has been removed in recent versions.
507 The correct feature set is determined at runtime.
509 @subsection arm720t options
510 @cindex arm720t options
511 ARM720t options are similar to ARM7TDMI options.
513 @subsection arm9tdmi options
514 @cindex arm9tdmi options
515 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
516 @option{arm920t}, @option{arm922t} and @option{arm940t}.
517 This enables the hardware single-stepping support found on these cores.
519 @subsection arm920t options
520 @cindex arm920t options
521 ARM920t options are similar to ARM9TDMI options.
523 @subsection arm966e options
524 @cindex arm966e options
525 ARM966e options are similar to ARM9TDMI options.
527 @subsection xscale options
528 @cindex xscale options
529 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
530 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
532 @section Flash configuration
533 @cindex Flash configuration
536 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
537 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
539 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
540 and <@var{bus_width}> bytes using the selected flash <driver>.
542 @item @b{flash auto_erase} <@option{on}|@option{off}>
543 @cindex flash auto_erase
544 auto erase flash banks prior to writing. Currently only works when using
545 @option{flash write_image} command. Default is @option{off}.
548 @subsection lpc2000 options
549 @cindex lpc2000 options
551 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
552 <@var{clock}> [@var{calc_checksum}]
553 LPC flashes don't require the chip and bus width to be specified. Additional
554 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
555 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
556 of the target this flash belongs to (first is 0), the frequency at which the core
557 is currently running (in kHz - must be an integral number), and the optional keyword
558 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
561 @subsection cfi options
564 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
566 CFI flashes require the number of the target they're connected to as an additional
567 argument. The CFI driver makes use of a working area (specified for the target)
568 to significantly speed up operation.
570 @var{chip_width} and @var{bus_width} are specified in bytes.
572 @subsection at91sam7 options
573 @cindex at91sam7 options
575 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
576 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
577 reading the chip-id and type.
579 @subsection str7 options
582 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
583 variant can be either STR71x, STR73x or STR75x.
585 @subsection str9 options
588 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
589 The str9 needs the flash controller to be configured prior to Flash programming, eg.
591 str9x flash_config 0 4 2 0 0x80000
593 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
595 @subsection str9 options (str9xpec driver)
597 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
598 Before using the flash commands the turbo mode will need enabling using str9xpec
599 @option{enable_turbo} <@var{num>.}
601 Only use this driver for locking/unlocking the device or configuring the option bytes.
602 Use the standard str9 driver for programming.
604 @subsection stellaris (LM3Sxxx) options
605 @cindex stellaris (LM3Sxxx) options
607 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
608 stellaris flash plugin only require the @var{target#}.
610 @subsection stm32x options
611 @cindex stm32x options
613 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
614 stm32x flash plugin only require the @var{target#}.
620 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
621 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
622 is available from both the telnet interface and a GDB session. To issue commands to the
623 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
624 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
630 @item @b{sleep} <@var{msec}>
632 Wait for n milliseconds before resuming. Useful in connection with script files
633 (@var{script} command and @var{target_script} configuration).
637 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
639 @item @b{debug_level} [@var{n}]
641 Display or adjust debug level to n<0-3>
643 @item @b{log_output} <@var{file}>
645 Redirect logging to <file> (default: stderr)
647 @item @b{script} <@var{file}>
649 Execute commands from <file>
653 @subsection Target state handling
655 @item @b{poll} [@option{on}|@option{off}]
657 Poll the target for its current state. If the target is in debug mode, architecture
658 specific information about the current state are printed. An optional parameter
659 allows continuous polling to be enabled and disabled.
661 @item @b{halt} [@option{ms}]
663 Send a halt request to the target and waits for it to halt for [@option{ms}].
664 Default [@option{ms}] is 5 seconds if no arg given.
665 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
666 will stop openocd from waiting.
668 @item @b{wait_halt} [@option{ms}]
670 Wait for the target to enter debug mode. Optional [@option{ms}] is
671 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
674 @item @b{resume} [@var{address}]
676 Resume the target at its current code position, or at an optional address.
677 Openocd will wait 5 seconds for the target to resume.
679 @item @b{step} [@var{address}]
681 Single-step the target at its current code position, or at an optional address.
683 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
684 |@option{run_and_init}]
686 Do a hard-reset. The optional parameter specifies what should happen after the reset.
687 This optional parameter overwrites the setting specified in the configuration file,
688 making the new behaviour the default for the @option{reset} command.
695 Immediately halt the target (works only with certain configurations).
698 Immediately halt the target, and execute the reset script (works only with certain
701 @cindex reset run_and_halt
702 Let the target run for a certain amount of time, then request a halt.
704 @cindex reset run_and_init
705 Let the target run for a certain amount of time, then request a halt. Execute the
706 reset script once the target entered debug mode.
710 @subsection Memory access commands
711 These commands allow accesses of a specific size to the memory system:
713 @item @b{mdw} <@var{addr}> [@var{count}]
716 @item @b{mdh} <@var{addr}> [@var{count}]
718 display memory half-words
719 @item @b{mdb} <@var{addr}> [@var{count}]
722 @item @b{mww} <@var{addr}> <@var{value}>
725 @item @b{mwh} <@var{addr}> <@var{value}>
727 write memory half-word
728 @item @b{mwb} <@var{addr}> <@var{value}>
732 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
734 Load image <@var{file}> to target memory at <@var{address}>
735 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
737 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
738 (binary) <@var{file}>.
739 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
741 Verify <@var{file}> to target memory starting at <@var{address}>.
742 This will first attempt using a crc checksum, if this fails it will try a binary compare.
743 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
745 Load binary <@var{file}> to target memory at <@var{address}>
746 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
748 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
749 (binary) <@var{file}>.
752 @subsection Flash commands
753 @cindex Flash commands
755 @item @b{flash banks}
757 List configured flash banks
758 @item @b{flash info} <@var{num}>
760 Print info about flash bank <@option{num}>
761 @item @b{flash probe} <@var{num}>
763 Identify the flash, or validate the parameters of the configured flash. Operation
764 depends on the flash type.
765 @item @b{flash erase_check} <@var{num}>
766 @cindex flash erase_check
767 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
768 updates the erase state information displayed by @option{flash info}. That means you have
769 to issue an @option{erase_check} command after erasing or programming the device to get
771 @item @b{flash protect_check} <@var{num}>
772 @cindex flash protect_check
773 Check protection state of sectors in flash bank <num>.
775 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
777 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
778 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
779 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
780 the CFI driver). This command was replaced by the new command
781 @option{flash erase_sector} using the same syntax.
782 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
783 @cindex flash erase_sector
784 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
785 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
786 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
788 @item @b{flash erase_address} <@var{address}> <@var{length}>
789 @cindex flash erase_address
790 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
791 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
793 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
794 bytes from the beginning of the bank. This command was replaced by the new command
795 @option{flash write_binary} using the same syntax.
796 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
797 @cindex flash write_binary
798 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
799 <@option{offset}> bytes from the beginning of the bank.
800 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
801 @cindex flash write_image
802 Write the image <@var{file}> to the current target's flash bank(s). A relocation
803 [@var{offset}] can be specified and the file [@var{type}] can be specified
804 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
805 (ELF file) or @option{s19} (Motorola s19).
806 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
807 @cindex flash protect
808 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
809 <@var{last}> of @option{flash bank} <@var{num}>.
810 @item @b{flash auto_erase} <@var{on}|@var{off}>
811 @cindex flash auto_erase
812 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
813 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
817 @section Target Specific Commands
818 @cindex Target Specific Commands
820 @subsection AT91SAM7 specific commands
821 @cindex AT91SAM7 specific commands
822 The flash configuration is deduced from the chip identification register. The flash
823 controller handles erases automatically on a page (128/265 byte) basis so erase is
824 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
825 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
826 that can be erased separatly.Only an EraseAll command is supported by the controller
827 for each flash plane and this is called with
829 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
830 bulk erase flash planes first_plane to last_plane.
831 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
832 @cindex at91sam7 gpnvm
833 set or clear a gpnvm bit for the processor
836 @subsection STR9 specific commands
837 @cindex STR9 specific commands
838 These are flash specific commands when using the str9xpec driver.
840 @item @b{str9xpec enable_turbo} <@var{num}>
841 @cindex str9xpec enable_turbo
842 enable turbo mode, simply this will remove the str9 from the chain and talk
843 directly to the embedded flash controller.
844 @item @b{str9xpec disable_turbo} <@var{num}>
845 @cindex str9xpec disable_turbo
846 restore the str9 into jtag chain.
847 @item @b{str9xpec lock} <@var{num}>
848 @cindex str9xpec lock
849 lock str9 device. The str9 will only respond to an unlock command that will
851 @item @b{str9xpec unlock} <@var{num}>
852 @cindex str9xpec unlock
854 @item @b{str9xpec options_read} <@var{num}>
855 @cindex str9xpec options_read
856 read str9 option bytes.
857 @item @b{str9xpec options_write} <@var{num}>
858 @cindex str9xpec options_write
859 write str9 option bytes.
862 @subsection STR9 configuration
863 @cindex STR9 configuration
865 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
866 <@var{BBADR}> <@var{NBBADR}>
867 @cindex str9x flash_config
868 Configure str9 flash controller.
870 eg. str9x flash_config 0 4 2 0 0x80000
872 BBSR - Boot Bank Size register
873 NBBSR - Non Boot Bank Size register
874 BBADR - Boot Bank Start Address register
875 NBBADR - Boot Bank Start Address register
879 @subsection STR9 option byte configuration
880 @cindex STR9 option byte configuration
882 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
883 @cindex str9xpec options_cmap
884 configure str9 boot bank.
885 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
886 @cindex str9xpec options_lvdthd
887 configure str9 lvd threshold.
888 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
889 @cindex str9xpec options_lvdsel
890 configure str9 lvd source.
891 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
892 @cindex str9xpec options_lvdwarn
893 configure str9 lvd reset warning source.
896 @subsection STM32x specific commands
897 @cindex STM32x specific commands
899 These are flash specific commands when using the stm32x driver.
901 @item @b{stm32x lock} <@var{num}>
904 @item @b{stm32x unlock} <@var{num}>
905 @cindex stm32x unlock
907 @item @b{stm32x options_read} <@var{num}>
908 @cindex stm32x options_read
909 read stm32 option bytes.
910 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
911 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
912 @cindex stm32x options_write
913 write stm32 option bytes.
914 @item @b{stm32x mass_erase} <@var{num}>
915 @cindex stm32x mass_erase
916 mass erase flash memory.
920 @section Architecture Specific Commands
921 @cindex Architecture Specific Commands
923 @subsection ARMV4/5 specific commands
924 @cindex ARMV4/5 specific commands
926 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
927 or Intel XScale (XScale isn't supported yet).
929 @item @b{armv4_5 reg}
931 Display a list of all banked core registers, fetching the current value from every
932 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
934 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
935 @cindex armv4_5 core_mode
936 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
937 The target is resumed in the currently set @option{core_mode}.
940 @subsection ARM7/9 specific commands
941 @cindex ARM7/9 specific commands
943 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
944 ARM920t or ARM926EJ-S.
946 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
947 @cindex arm7_9 sw_bkpts
948 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
949 one of the watchpoint registers to implement software breakpoints. Disabling
950 SW Bkpts frees that register again.
951 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
952 @cindex arm7_9 force_hw_bkpts
953 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
954 breakpoints are turned into hardware breakpoints.
955 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
957 Enable use of the DBGRQ bit to force entry into debug mode. This should be
958 safe for all but ARM7TDMI--S cores (like Philips LPC).
959 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
960 @cindex arm7_9 fast_writes [DEPRECATED]
961 See @option{arm7_9 fast_memory_access} instead.
962 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
963 @cindex arm7_9 fast_memory_access
964 Allow the OpenOCD to read and write memory without checking completion of
965 the operation. This provides a huge speed increase, especially with USB JTAG
966 cables (FT2232), but might be unsafe if used with targets running at a very low
967 speed, like the 32kHz startup clock of an AT91RM9200.
968 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
969 @cindex arm7_9 dcc_downloads
970 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
971 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
972 unsafe, especially with targets running at a very low speed. This command was introduced
973 with OpenOCD rev. 60.
976 @subsection ARM920T specific commands
977 @cindex ARM920T specific commands
980 @item @b{arm920t cache_info}
981 @cindex arm920t cache_info
982 Print information about the caches found. This allows you to see if your target
983 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
984 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
985 @cindex arm920t md<bhw>_phys
986 Display memory at physical address addr.
987 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
988 @cindex arm920t mw<bhw>_phys
989 Write memory at physical address addr.
990 @item @b{arm920t read_cache} <@var{filename}>
991 @cindex arm920t read_cache
992 Dump the content of ICache and DCache to a file.
993 @item @b{arm920t read_mmu} <@var{filename}>
994 @cindex arm920t read_mmu
995 Dump the content of the ITLB and DTLB to a file.
996 @item @b{arm920t virt2phys} <@var{VA}>
997 @cindex arm920t virt2phys
998 Translate a virtual address to a physical address.
1002 @section Debug commands
1003 @cindex Debug commands
1004 The following commands give direct access to the core, and are most likely
1005 only useful while debugging the OpenOCD.
1007 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1008 @cindex arm7_9 write_xpsr
1009 Immediately write either the current program status register (CPSR) or the saved
1010 program status register (SPSR), without changing the register cache (as displayed
1011 by the @option{reg} and @option{armv4_5 reg} commands).
1012 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1013 <@var{0=cpsr},@var{1=spsr}>
1014 @cindex arm7_9 write_xpsr_im8
1015 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1016 operation (similar to @option{write_xpsr}).
1017 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1018 @cindex arm7_9 write_core_reg
1019 Write a core register, without changing the register cache (as displayed by the
1020 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1021 encoding of the [M4:M0] bits of the PSR.
1025 @section JTAG commands
1026 @cindex JTAG commands
1028 @item @b{scan_chain}
1030 Print current scan chain configuration.
1031 @item @b{jtag_reset}
1033 Toggle reset lines <@var{trst}> <@var{srst}>.
1034 @item @b{endstate} <@var{tap_state}>
1036 Finish JTAG operations in <@var{tap_state}>.
1037 @item @b{runtest} <@var{num_cycles}>
1039 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1040 @item @b{statemove} [@var{tap_state}]
1042 Move to current endstate or [@var{tap_state}]
1045 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1048 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1049 @item @b{verify_ircapture}
1050 @cindex verify_ircapture
1051 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1054 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1057 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1060 @node Sample Scripts
1061 @chapter Sample Scripts
1064 This page will collect some script examples for different CPUs.
1066 The configuration script can be divided in the following section:
1068 @item daemon configuration
1070 @item jtag scan chain
1071 @item target configuration
1072 @item flash configuration
1075 Detailed information about each section can be found at OpenOCD configuration
1077 @section OMAP5912 Flash Debug
1078 @cindex OMAP5912 Flash Debug
1079 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1080 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1081 - (@uref{http://www.spectrumdigital.com}).
1082 @subsection Openocd config
1084 #daemon configuration
1091 parport_cable wiggler
1094 #use combined on interfaces or targets that can't set TRST/SRST separately
1095 reset_config trst_and_srst
1098 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1099 jtag_device 38 0x0 0x0 0x0
1100 jtag_device 4 0x1 0x0 0xe
1101 jtag_device 8 0x0 0x0 0x0
1103 #target configuration
1104 daemon_startup reset
1106 #target <type> <endianness> <reset mode> <chainpos> <variant>
1107 target arm926ejs little run_and_init 1 arm926ejs
1108 target_script 0 reset omap5912_osk.init
1109 run_and_halt_time 0 30
1111 # omap5912 lcd frame buffer as working area
1112 working_area 0 0x20000000 0x3e800 nobackup
1114 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1115 flash bank cfi 0x00000000 0x1000000 2 2 0
1118 @subsection Openocd init
1130 mww 0xfffec808 0x000000f5
1131 mww 0xfffec808 0x000000a0
1133 mww 0xfffeb048 0x0000aaaa
1135 mww 0xfffeb048 0x00005555
1144 @section STR71x Script
1145 @cindex STR71x Script
1146 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1148 #daemon configuration
1154 ft2232_device_desc "Amontec JTAGkey A"
1155 ft2232_layout jtagkey
1156 ft2232_vid_pid 0x0403 0xcff8
1159 #use combined on interfaces or targets that can't set TRST/SRST separately
1160 reset_config trst_and_srst srst_pulls_trst
1163 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1164 jtag_device 4 0x1 0xf 0xe
1166 #target configuration
1167 daemon_startup reset
1169 #target <type> <startup mode>
1170 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1171 target arm7tdmi little run_and_halt 0 arm7tdmi
1172 run_and_halt_time 0 30
1174 working_area 0 0x2000C000 0x4000 nobackup
1176 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1177 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1180 @section STR750 Script
1181 @cindex STR750 Script
1182 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1184 #daemon configuration
1190 ft2232_device_desc "Amontec JTAGkey A"
1191 ft2232_layout jtagkey
1192 ft2232_vid_pid 0x0403 0xcff8
1195 #use combined on interfaces or targets that can't set TRST/SRST separately
1196 #reset_config trst_and_srst srst_pulls_trst
1197 reset_config trst_and_srst srst_pulls_trst
1200 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1201 jtag_device 4 0x1 0xf 0xe
1203 #jtag nTRST and nSRST delay
1204 jtag_nsrst_delay 500
1205 jtag_ntrst_delay 500
1207 #target configuration
1208 daemon_startup reset
1210 #target <type> <startup mode>
1211 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1212 target arm7tdmi little run_and_halt 0 arm7tdmi
1213 run_and_halt_time 0 30
1215 working_area 0 0x40000000 0x4000 nobackup
1217 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1218 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1221 @section STR912 Script
1222 @cindex STR912 Script
1223 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1225 #daemon configuration
1231 ft2232_device_desc "Amontec JTAGkey A"
1232 ft2232_layout jtagkey
1235 #use combined on interfaces or targets that can't set TRST/SRST separately
1236 reset_config trst_and_srst
1239 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1240 jtag_device 8 0x1 0x1 0xfe
1241 jtag_device 4 0x1 0xf 0xe
1242 jtag_device 5 0x1 0x1 0x1e
1244 #target configuration
1245 daemon_startup reset
1247 #target <type> <startup mode>
1248 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1249 target arm966e little reset_halt 1 arm966e
1250 run_and_halt_time 0 30
1252 working_area 0 0x50000000 16384 nobackup
1254 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1255 flash bank str9x 0x00000000 0x00080000 0 0 0
1258 @section STR912 comstick
1259 @cindex STR912 comstick Script
1260 The following script was used with a Hitex STR9 Comstick:
1262 #daemon configuration
1268 ft2232_device_desc "STR9-comStick A"
1269 ft2232_layout comstick
1272 jtag_nsrst_delay 100
1273 jtag_ntrst_delay 100
1275 #use combined on interfaces or targets that can't set TRST/SRST separately
1276 reset_config trst_and_srst
1279 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1280 jtag_device 8 0x1 0x1 0xfe
1281 jtag_device 4 0x1 0xf 0xe
1282 jtag_device 5 0x1 0x1 0x1e
1284 #target configuration
1285 daemon_startup reset
1287 #target <type> <startup mode>
1288 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1289 target arm966e little reset_halt 1 arm966e
1290 run_and_halt_time 0 30
1292 working_area 0 0x50000000 16384 nobackup
1294 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1295 flash bank str9x 0x00000000 0x00080000 0 0 0
1298 @section STM32x Script
1299 @cindex STM32x Script
1300 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1302 #daemon configuration
1308 ft2232_device_desc "Amontec JTAGkey A"
1309 ft2232_layout jtagkey
1312 jtag_nsrst_delay 100
1313 jtag_ntrst_delay 100
1315 #use combined on interfaces or targets that can't set TRST/SRST separately
1316 reset_config trst_and_srst
1319 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1320 jtag_device 4 0x1 0xf 0xe
1321 jtag_device 5 0x1 0x1 0x1e
1323 #target configuration
1324 daemon_startup reset
1326 #target <type> <startup mode>
1327 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1328 target cortex_m3 little run_and_halt 0
1329 run_and_halt_time 0 30
1331 working_area 0 0x20000000 16384 nobackup
1333 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1334 flash bank stm32x 0x08000000 0x00020000 0 0 0
1337 @section STM32x Performance Stick
1338 @cindex STM32x Performance Stick Script
1339 The following script was used with the Hitex STM32 Performance Stick
1341 #daemon configuration
1347 ft2232_device_desc "STM32-PerformanceStick A"
1348 ft2232_layout stm32stick
1351 jtag_nsrst_delay 100
1352 jtag_ntrst_delay 100
1354 #use combined on interfaces or targets that can't set TRST/SRST separately
1355 reset_config trst_and_srst
1358 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1359 jtag_device 4 0x1 0xf 0xe
1360 jtag_device 5 0x1 0x1 0x1e
1361 jtag_device 4 0x1 0xf 0xe
1363 #target configuration
1364 daemon_startup reset
1366 #target <type> <startup mode>
1367 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1368 target cortex_m3 little run_and_halt 0
1369 run_and_halt_time 0 30
1371 working_area 0 0x20000000 16384 nobackup
1373 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1374 flash bank stm32x 0x08000000 0x00020000 0 0 0
1377 @section LPC2129 Script
1378 @cindex LPC2129 Script
1379 The following script was used with an wiggler PP and a LPC-2129 cpu:
1381 #daemon configuration
1388 parport_cable wiggler
1391 #use combined on interfaces or targets that can't set TRST/SRST separately
1392 reset_config trst_and_srst srst_pulls_trst
1395 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1396 jtag_device 4 0x1 0xf 0xe
1398 #target configuration
1399 daemon_startup reset
1401 #target <type> <startup mode>
1402 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1403 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1404 run_and_halt_time 0 30
1406 working_area 0 0x40000000 0x4000 nobackup
1408 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1409 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1412 @section LPC2148 Script
1413 @cindex LPC2148 Script
1414 The following script was used with an Amontec JTAGkey and a LPC2148 cpu:
1416 #daemon configuration
1422 ft2232_device_desc "Amontec JTAGkey A"
1423 ft2232_layout jtagkey
1424 ft2232_vid_pid 0x0403 0xcff8
1427 #use combined on interfaces or targets that can't set TRST/SRST separately
1428 reset_config trst_and_srst srst_pulls_trst
1431 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1432 jtag_device 4 0x1 0xf 0xe
1434 #target configuration
1435 daemon_startup reset
1437 #target <type> <startup mode>
1438 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1439 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1440 run_and_halt_time 0 30
1442 working_area 0 0x40000000 0x8000 nobackup
1444 #flash configuration
1445 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1448 @section LPC2294 Script
1449 @cindex LPC2294 Script
1450 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1452 #daemon configuration
1458 ft2232_device_desc "Amontec JTAGkey A"
1459 ft2232_layout jtagkey
1460 ft2232_vid_pid 0x0403 0xcff8
1463 #use combined on interfaces or targets that can't set TRST/SRST separately
1464 reset_config trst_and_srst srst_pulls_trst
1467 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1468 jtag_device 4 0x1 0xf 0xe
1470 #target configuration
1471 daemon_startup reset
1473 #target <type> <startup mode>
1474 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1475 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1476 run_and_halt_time 0 30
1478 working_area 0 0x40000000 0x4000 nobackup
1480 #flash configuration
1481 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1484 @section AT91R40008 Script
1485 @cindex AT91R40008 Script
1486 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1488 #daemon configuration
1494 ft2232_device_desc "Amontec JTAGkey A"
1495 ft2232_layout jtagkey
1496 ft2232_vid_pid 0x0403 0xcff8
1498 jtag_nsrst_delay 200
1499 jtag_ntrst_delay 200
1501 #use combined on interfaces or targets that can't set TRST/SRST separately
1502 reset_config srst_only srst_pulls_trst
1505 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1506 jtag_device 4 0x1 0xf 0xe
1508 #target configuration
1509 daemon_startup reset
1511 #target <type> <startup mode>
1512 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1513 target arm7tdmi little run_and_halt 0 arm7tdmi
1514 run_and_halt_time 0 30
1517 @section AT91SAM7s Script
1518 @cindex AT91SAM7s Script
1519 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1521 #daemon configuration
1527 ft2232_device_desc "Olimex OpenOCD JTAG A"
1528 ft2232_layout olimex-jtag
1529 ft2232_vid_pid 0x15BA 0x0003
1531 jtag_nsrst_delay 200
1532 jtag_ntrst_delay 200
1534 #use combined on interfaces or targets that can't set TRST/SRST separately
1535 reset_config srst_only srst_pulls_trst
1538 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1539 jtag_device 4 0x1 0xf 0xe
1541 #target configuration
1542 daemon_startup reset
1544 #target <type> <startup mode>
1545 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1546 target arm7tdmi little run_and_halt 0 arm7tdmi
1547 run_and_halt_time 0 30
1549 # flash-options AT91
1550 working_area 0 0x00200000 0x4000 nobackup
1551 flash bank at91sam7 0 0 0 0 0
1554 # erase command (telnet-interface) for complete flash:
1555 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1556 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1557 # set/clear NVM-Bits:
1558 # at91sam7 gpnvm <num> <bit> <set|clear>
1559 # disable locking from SAM-BA:
1560 # flash protect 0 0 1 off
1563 @section XSCALE IXP42x Script
1564 @cindex XSCALE IXP42x Script
1565 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1567 #daemon configuration
1573 ft2232_device_desc "Amontec JTAGkey A"
1574 ft2232_layout jtagkey
1575 ft2232_vid_pid 0x0403 0xcff8
1577 jtag_nsrst_delay 200
1578 jtag_ntrst_delay 200
1580 #use combined on interfaces or targets that can't set TRST/SRST separately
1581 reset_config srst_only srst_pulls_trst
1584 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1585 jtag_device 7 0x1 0x7f 0x7e
1587 #target configuration
1588 daemon_startup reset
1590 #target <type> <startup mode>
1591 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1592 target xscale big run_and_halt 0 IXP42x
1593 run_and_halt_time 0 30
1596 @section Cirrus Logic EP9301 Script
1597 @cindex Cirrus Logic EP9301 Script
1598 The following script was used with FT2232 based JTAG interfaces and a
1599 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1601 #daemon configuration
1609 #ft2232_device_desc "Olimex OpenOCD JTAG"
1610 #ft2232_layout olimex-jtag
1611 #ft2232_vid_pid 0x15ba 0x0003
1613 #Amontec JTAGkey (and JTAGkey-Tiny)
1614 #Serial is only necessary if more than one JTAGkey is connected
1615 ft2232_device_desc "Amontec JTAGkey A"
1616 #ft2232_serial AMTJKV31
1617 #ft2232_serial T1P3S2W8
1618 ft2232_layout jtagkey
1619 ft2232_vid_pid 0x0403 0xcff8
1621 #wiggler/parallel port interface
1624 #parport_cable wiggler
1627 reset_config trst_and_srst
1630 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1631 jtag_device 4 0x1 0xf 0xe
1633 jtag_nsrst_delay 100
1634 jtag_ntrst_delay 100
1636 #target configuration
1637 daemon_startup attach
1639 #target <type> <endianess> <reset mode>
1640 target arm920t little reset_halt 0
1641 working_area 0 0x80014000 0x1000 backup
1643 #flash configuration
1644 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1645 flash bank cfi 0x60000000 0x1000000 2 2 0
1648 @section Hilscher netX 100 / 500 Script
1649 @cindex Hilscher netX 100 / 500 Script
1650 The following script was used with an Amontec JTAGkey and a Hilscher
1653 #daemon configuration
1659 ft2232_device_desc "Amontec JTAGkey A"
1660 ft2232_layout jtagkey
1661 ft2232_vid_pid 0x0403 0xcff8
1664 #use combined on interfaces or targets that can't set TRST/SRST separately
1665 reset_config trst_and_srst
1668 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1669 jtag_device 4 0x1 0xf 0xe
1671 jtag_nsrst_delay 100
1672 jtag_ntrst_delay 100
1674 #target configuration
1675 daemon_startup reset
1677 #target <type> <endianness> <startup mode> <chainpos> <variant>
1678 target arm926ejs little run_and_halt 0 arm926ejs
1679 run_and_halt_time 0 500
1682 @section Marvell/Intel PXA270 Script
1683 @cindex Marvell/Intel PXA270 Script
1685 # config for Intel PXA270
1686 # not, as of 2007-06-22, openocd only works with the
1687 # libftd2xx library from ftdi. libftdi does not work.
1693 ft2232_layout olimex-jtag
1694 ft2232_vid_pid 0x15BA 0x0003
1695 ft2232_device_desc "Olimex OpenOCD JTAG"
1697 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1698 # the rest of the needed delays are built into the openocd program
1699 jtag_nsrst_delay 260
1700 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1701 # the rest of the needed delays are built into the openocd program
1704 #use combined on interfaces or targets that can't set TRST/SRST separately
1705 reset_config trst_and_srst separate
1708 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1709 jtag_device 7 0x1 0x7f 0x7e
1711 #target configuration
1712 daemon_startup reset
1714 target xscale little reset_halt 0 pxa27x
1716 # maps to PXA internal RAM. If you are using a PXA255
1717 # you must initialize SDRAM or leave this option off
1718 working_area 0 0x5c000000 0x10000 nobackup
1720 run_and_halt_time 0 30
1722 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1723 # works for P30 flash
1724 flash bank cfi 0x00000000 0x1000000 2 4 0
1727 @node GDB and Openocd
1728 @chapter GDB and Openocd
1729 @cindex GDB and Openocd
1730 Openocd complies with the remote gdbserver protocol, and as such can be used
1731 to debug remote targets.
1733 @section Connecting to gdb
1734 @cindex Connecting to gdb
1735 A connection is typically started as follows:
1737 target remote localhost:3333
1739 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1741 To see a list of available openocd commands type @option{monitor help} on the
1744 Openocd supports the gdb @option{qSupported} packet, this enables information
1745 to be sent by the gdb server (openocd) to gdb. Typical information includes
1746 packet size and device memory map.
1748 Previous versions of openocd required the following gdb options to increase
1749 the packet size and speed up gdb communication.
1751 set remote memory-write-packet-size 1024
1752 set remote memory-write-packet-size fixed
1753 set remote memory-read-packet-size 1024
1754 set remote memory-read-packet-size fixed
1756 This is now handled in the @option{qSupported} PacketSize.
1758 @section Programming using gdb
1759 @cindex Programming using gdb
1761 By default the target memory map is not sent to gdb, this can be enabled by
1762 the following openocd config option:
1764 gdb_memory_map enable
1766 For this to function correctly a valid flash config must also be configured
1767 in openocd. For speed also configure a valid working area.
1769 Informing gdb of the memory map of the target will enable gdb to protect any
1770 flash area of the target and use hardware breakpoints by default. This means
1771 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1774 To view the configured memory map in gdb, use the gdb command @option{info mem}
1775 All other unasigned addresses within gdb are treated as ram.
1777 If @option{gdb_flash_program enable} is also used, gdb will be able to
1778 program any flash memory using the vFlash interface.
1780 gdb will look at the target memory map when a load command is given, if any
1781 areas to be programmed lie within the target flash area the vFlash packets
1784 Incase the target needs configuring before gdb programming, a script can be executed.
1786 target_script 0 gdb_program_config config.script
1789 To verify any flash programming the gdb command @option{compare-sections}
1796 @item OpenOCD complains about a missing cygwin1.dll
1798 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1799 claims to come with all the necessary dlls. When using Cygwin, try launching
1800 the OpenOCD from the Cygwin shell.
1802 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1803 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1804 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1806 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1807 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1808 software breakpoints consume one of the two available hardware breakpoints,
1809 and are therefor disabled by default. If your code is running from RAM, you
1810 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1811 your code resides in Flash, you can't use software breakpoints, but you can force
1812 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1814 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1815 and works sometimes fine.
1817 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1818 clock at the time you're programming the flash. If you've specified the crystal's
1819 frequency, make sure the PLL is disabled, if you've specified the full core speed
1820 (e.g. 60MHz), make sure the PLL is enabled.
1822 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1823 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1824 out while waiting for end of scan, rtck was disabled".
1826 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1827 settings in your PC Bios (ECP, EPP, and different versions of those).
1829 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1830 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1831 memory read caused data abort".
1833 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1834 beyond the last valid frame. It might be possible to prevent this by setting up
1835 a proper "initial" stack frame, if you happen to know what exactly has to
1836 be done, feel free to add this here.
1838 @item I get the following message in the OpenOCD console (or log file):
1839 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1841 This warning doesn't indicate any serious problem, as long as you don't want to
1842 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1843 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1844 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1845 independently. With this setup, it's not possible to halt the core right out of
1846 reset, everything else should work fine.
1848 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1849 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1850 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1851 quit with an error message. Is there a stability issue with OpenOCD?
1853 No, this is not a stability issue concering OpenOCD. Most users have solved
1854 this issue by simply using a self-powered USB Hub, which they connect their
1855 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1856 supply stable enough for the Amontec JTAGkey to be operated.
1858 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1859 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1860 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1861 What does that mean and what might be the reason for this?
1863 First of all, the reason might be the USB power supply. Try using a self-powered
1864 hub instead of a direct connection to your computer. Secondly, the error code 4
1865 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1866 Chip ran into some sort of error - this points us to a USB problem.
1868 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1869 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1870 What does that mean and what might be the reason for this?
1872 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1873 has closed the connection to OpenOCD. This might be a GDB issue.
1875 @item In the configuration file in the section where flash device configurations
1876 are described, there is a parameter for specifying the clock frequency for
1877 LPC2000 internal flash devices (e.g.
1878 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1879 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1880 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1881 Is it possible to specify real numbers for the clock frequency?
1883 No. The clock frequency specified here must be given as an integral number.
1884 However, this clock frequency is used by the In-Application-Programming (IAP)
1885 routines of the LPC2000 family only, which seems to be very tolerant concerning
1886 the given clock frequency, so a slight difference between the specified clock
1887 frequency and the actual clock frequency will not cause any trouble.
1889 @item Do I have to keep a specific order for the commands in the configuration file?
1891 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1892 listed for the JTAG scan chain must be given in the right order (jtag_device),
1893 with the device closest to the TDO-Pin being listed first. In general,
1894 whenever objects of the same type exist which require an index number, then
1895 these objects must be given in the right order (jtag_devices, targets and flash
1896 banks - a target references a jtag_device and a flash bank references a target).
1898 @item Sometimes my debugging session terminates with an error. When I look into the
1899 log file, I can see these error messages: Error: arm7_9_common.c:561
1900 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP