1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.org/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.org/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
208 @chapter OpenOCD Developer Resources
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD Git Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
224 @uref{git://git.code.sf.net/p/openocd/code}
228 @uref{http://git.code.sf.net/p/openocd/code}
230 You may prefer to use a mirror and the HTTP protocol:
232 @uref{http://repo.or.cz/r/openocd.git}
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
240 @uref{http://repo.or.cz/w/openocd.git}
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
250 @section Doxygen Developer Manual
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
263 @section Gerrit Review System
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 @uref{https://review.openocd.org/}
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
282 @section OpenOCD Developer Mailing List
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289 @section OpenOCD Bug Tracker
291 The OpenOCD Bug Tracker is hosted on SourceForge:
293 @uref{http://bugs.openocd.org/}
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
312 @section Choosing a Dongle
314 There are several things you should keep in mind when choosing a dongle.
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
331 @section USB FT2232 Based
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
406 @section USB-JTAG / Altera USB-Blaster compatibles
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
522 @section IBM PC Parallel Printer Port Based
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
588 @* A JTAG driver acting as a client for the JTAG VPI server interface.
589 @* Link: @url{http://github.com/fjullien/jtag_vpi}
592 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
593 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
594 interface of a hardware model written in SystemVerilog, for example, on an
595 emulation model of target hardware.
597 @item @b{xlnx_pcie_xvc}
598 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
601 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
604 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
605 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
610 @chapter About Jim-Tcl
614 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
615 This programming language provides a simple and extensible
618 All commands presented in this Guide are extensions to Jim-Tcl.
619 You can use them as simple commands, without needing to learn
620 much of anything about Tcl.
621 Alternatively, you can write Tcl programs with them.
623 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
624 There is an active and responsive community, get on the mailing list
625 if you have any questions. Jim-Tcl maintainers also lurk on the
626 OpenOCD mailing list.
629 @item @b{Jim vs. Tcl}
630 @* Jim-Tcl is a stripped down version of the well known Tcl language,
631 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
632 fewer features. Jim-Tcl is several dozens of .C files and .H files and
633 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
634 4.2 MB .zip file containing 1540 files.
636 @item @b{Missing Features}
637 @* Our practice has been: Add/clone the real Tcl feature if/when
638 needed. We welcome Jim-Tcl improvements, not bloat. Also there
639 are a large number of optional Jim-Tcl features that are not
643 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
644 command interpreter today is a mixture of (newer)
645 Jim-Tcl commands, and the (older) original command interpreter.
648 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
649 can type a Tcl for() loop, set variables, etc.
650 Some of the commands documented in this guide are implemented
651 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
653 @item @b{Historical Note}
654 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
655 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
656 as a Git submodule, which greatly simplified upgrading Jim-Tcl
657 to benefit from new features and bugfixes in Jim-Tcl.
659 @item @b{Need a crash course in Tcl?}
660 @*@xref{Tcl Crash Course}.
665 @cindex command line options
667 @cindex directory search
669 Properly installing OpenOCD sets up your operating system to grant it access
670 to the debug adapters. On Linux, this usually involves installing a file
671 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
672 that works for many common adapters is shipped with OpenOCD in the
673 @file{contrib} directory. MS-Windows needs
674 complex and confusing driver configuration for every peripheral. Such issues
675 are unique to each operating system, and are not detailed in this User's Guide.
677 Then later you will invoke the OpenOCD server, with various options to
678 tell it how each debug session should work.
679 The @option{--help} option shows:
683 --help | -h display this help
684 --version | -v display OpenOCD version
685 --file | -f use configuration file <name>
686 --search | -s dir to search for config files and scripts
687 --debug | -d set debug level to 3
688 | -d<n> set debug level to <level>
689 --log_output | -l redirect log output to file <name>
690 --command | -c run <command>
693 If you don't give any @option{-f} or @option{-c} options,
694 OpenOCD tries to read the configuration file @file{openocd.cfg}.
695 To specify one or more different
696 configuration files, use @option{-f} options. For example:
699 openocd -f config1.cfg -f config2.cfg -f config3.cfg
702 Configuration files and scripts are searched for in
704 @item the current directory,
705 @item any search dir specified on the command line using the @option{-s} option,
706 @item any search dir specified using the @command{add_script_search_dir} command,
707 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
708 @item @file{%APPDATA%/OpenOCD} (only on Windows),
709 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
710 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
711 @item @file{$HOME/.openocd},
712 @item the site wide script library @file{$pkgdatadir/site} and
713 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
715 The first found file with a matching file name will be used.
718 Don't try to use configuration script names or paths which
719 include the "#" character. That character begins Tcl comments.
722 @section Simple setup, no customization
724 In the best case, you can use two scripts from one of the script
725 libraries, hook up your JTAG adapter, and start the server ... and
726 your JTAG setup will just work "out of the box". Always try to
727 start by reusing those scripts, but assume you'll need more
728 customization even if this works. @xref{OpenOCD Project Setup}.
730 If you find a script for your JTAG adapter, and for your board or
731 target, you may be able to hook up your JTAG adapter then start
732 the server with some variation of one of the following:
735 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
736 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
739 You might also need to configure which reset signals are present,
740 using @option{-c 'reset_config trst_and_srst'} or something similar.
741 If all goes well you'll see output something like
744 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
745 For bug reports, read
746 http://openocd.org/doc/doxygen/bugs.html
747 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
748 (mfg: 0x23b, part: 0xba00, ver: 0x3)
751 Seeing that "tap/device found" message, and no warnings, means
752 the JTAG communication is working. That's a key milestone, but
753 you'll probably need more project-specific setup.
755 @section What OpenOCD does as it starts
757 OpenOCD starts by processing the configuration commands provided
758 on the command line or, if there were no @option{-c command} or
759 @option{-f file.cfg} options given, in @file{openocd.cfg}.
760 @xref{configurationstage,,Configuration Stage}.
761 At the end of the configuration stage it verifies the JTAG scan
762 chain defined using those commands; your configuration should
763 ensure that this always succeeds.
764 Normally, OpenOCD then starts running as a server.
765 Alternatively, commands may be used to terminate the configuration
766 stage early, perform work (such as updating some flash memory),
767 and then shut down without acting as a server.
769 Once OpenOCD starts running as a server, it waits for connections from
770 clients (Telnet, GDB, RPC) and processes the commands issued through
773 If you are having problems, you can enable internal debug messages via
774 the @option{-d} option.
776 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
777 @option{-c} command line switch.
779 To enable debug output (when reporting problems or working on OpenOCD
780 itself), use the @option{-d} command line switch. This sets the
781 @option{debug_level} to "3", outputting the most information,
782 including debug messages. The default setting is "2", outputting only
783 informational messages, warnings and errors. You can also change this
784 setting from within a telnet or gdb session using @command{debug_level<n>}
785 (@pxref{debuglevel,,debug_level}).
787 You can redirect all output from the server to a file using the
788 @option{-l <logfile>} switch.
790 Note! OpenOCD will launch the GDB & telnet server even if it can not
791 establish a connection with the target. In general, it is possible for
792 the JTAG controller to be unresponsive until the target is set up
793 correctly via e.g. GDB monitor commands in a GDB init script.
795 @node OpenOCD Project Setup
796 @chapter OpenOCD Project Setup
798 To use OpenOCD with your development projects, you need to do more than
799 just connect the JTAG adapter hardware (dongle) to your development board
800 and start the OpenOCD server.
801 You also need to configure your OpenOCD server so that it knows
802 about your adapter and board, and helps your work.
803 You may also want to connect OpenOCD to GDB, possibly
804 using Eclipse or some other GUI.
806 @section Hooking up the JTAG Adapter
808 Today's most common case is a dongle with a JTAG cable on one side
809 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
810 and a USB cable on the other.
811 Instead of USB, some dongles use Ethernet;
812 older ones may use a PC parallel port, or even a serial port.
815 @item @emph{Start with power to your target board turned off},
816 and nothing connected to your JTAG adapter.
817 If you're particularly paranoid, unplug power to the board.
818 It's important to have the ground signal properly set up,
819 unless you are using a JTAG adapter which provides
820 galvanic isolation between the target board and the
823 @item @emph{Be sure it's the right kind of JTAG connector.}
824 If your dongle has a 20-pin ARM connector, you need some kind
825 of adapter (or octopus, see below) to hook it up to
826 boards using 14-pin or 10-pin connectors ... or to 20-pin
827 connectors which don't use ARM's pinout.
829 In the same vein, make sure the voltage levels are compatible.
830 Not all JTAG adapters have the level shifters needed to work
831 with 1.2 Volt boards.
833 @item @emph{Be certain the cable is properly oriented} or you might
834 damage your board. In most cases there are only two possible
835 ways to connect the cable.
836 Connect the JTAG cable from your adapter to the board.
837 Be sure it's firmly connected.
839 In the best case, the connector is keyed to physically
840 prevent you from inserting it wrong.
841 This is most often done using a slot on the board's male connector
842 housing, which must match a key on the JTAG cable's female connector.
843 If there's no housing, then you must look carefully and
844 make sure pin 1 on the cable hooks up to pin 1 on the board.
845 Ribbon cables are frequently all grey except for a wire on one
846 edge, which is red. The red wire is pin 1.
848 Sometimes dongles provide cables where one end is an ``octopus'' of
849 color coded single-wire connectors, instead of a connector block.
850 These are great when converting from one JTAG pinout to another,
851 but are tedious to set up.
852 Use these with connector pinout diagrams to help you match up the
853 adapter signals to the right board pins.
855 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
856 A USB, parallel, or serial port connector will go to the host which
857 you are using to run OpenOCD.
858 For Ethernet, consult the documentation and your network administrator.
860 For USB-based JTAG adapters you have an easy sanity check at this point:
861 does the host operating system see the JTAG adapter? If you're running
862 Linux, try the @command{lsusb} command. If that host is an
863 MS-Windows host, you'll need to install a driver before OpenOCD works.
865 @item @emph{Connect the adapter's power supply, if needed.}
866 This step is primarily for non-USB adapters,
867 but sometimes USB adapters need extra power.
869 @item @emph{Power up the target board.}
870 Unless you just let the magic smoke escape,
871 you're now ready to set up the OpenOCD server
872 so you can use JTAG to work with that board.
876 Talk with the OpenOCD server using
877 telnet (@code{telnet localhost 4444} on many systems) or GDB.
878 @xref{GDB and OpenOCD}.
880 @section Project Directory
882 There are many ways you can configure OpenOCD and start it up.
884 A simple way to organize them all involves keeping a
885 single directory for your work with a given board.
886 When you start OpenOCD from that directory,
887 it searches there first for configuration files, scripts,
888 files accessed through semihosting,
889 and for code you upload to the target board.
890 It is also the natural place to write files,
891 such as log files and data you download from the board.
893 @section Configuration Basics
895 There are two basic ways of configuring OpenOCD, and
896 a variety of ways you can mix them.
897 Think of the difference as just being how you start the server:
900 @item Many @option{-f file} or @option{-c command} options on the command line
901 @item No options, but a @dfn{user config file}
902 in the current directory named @file{openocd.cfg}
905 Here is an example @file{openocd.cfg} file for a setup
906 using a Signalyzer FT2232-based JTAG adapter to talk to
907 a board with an Atmel AT91SAM7X256 microcontroller:
910 source [find interface/ftdi/signalyzer.cfg]
912 # GDB can also flash my flash!
913 gdb_memory_map enable
914 gdb_flash_program enable
916 source [find target/sam7x256.cfg]
919 Here is the command line equivalent of that configuration:
922 openocd -f interface/ftdi/signalyzer.cfg \
923 -c "gdb_memory_map enable" \
924 -c "gdb_flash_program enable" \
925 -f target/sam7x256.cfg
928 You could wrap such long command lines in shell scripts,
929 each supporting a different development task.
930 One might re-flash the board with a specific firmware version.
931 Another might set up a particular debugging or run-time environment.
934 At this writing (October 2009) the command line method has
935 problems with how it treats variables.
936 For example, after @option{-c "set VAR value"}, or doing the
937 same in a script, the variable @var{VAR} will have no value
938 that can be tested in a later script.
941 Here we will focus on the simpler solution: one user config
942 file, including basic configuration plus any TCL procedures
943 to simplify your work.
945 @section User Config Files
946 @cindex config file, user
947 @cindex user config file
948 @cindex config file, overview
950 A user configuration file ties together all the parts of a project
952 One of the following will match your situation best:
955 @item Ideally almost everything comes from configuration files
956 provided by someone else.
957 For example, OpenOCD distributes a @file{scripts} directory
958 (probably in @file{/usr/share/openocd/scripts} on Linux).
959 Board and tool vendors can provide these too, as can individual
960 user sites; the @option{-s} command line option lets you say
961 where to find these files. (@xref{Running}.)
962 The AT91SAM7X256 example above works this way.
964 Three main types of non-user configuration file each have their
965 own subdirectory in the @file{scripts} directory:
968 @item @b{interface} -- one for each different debug adapter;
969 @item @b{board} -- one for each different board
970 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
973 Best case: include just two files, and they handle everything else.
974 The first is an interface config file.
975 The second is board-specific, and it sets up the JTAG TAPs and
976 their GDB targets (by deferring to some @file{target.cfg} file),
977 declares all flash memory, and leaves you nothing to do except
981 source [find interface/olimex-jtag-tiny.cfg]
982 source [find board/csb337.cfg]
985 Boards with a single microcontroller often won't need more
986 than the target config file, as in the AT91SAM7X256 example.
987 That's because there is no external memory (flash, DDR RAM), and
988 the board differences are encapsulated by application code.
990 @item Maybe you don't know yet what your board looks like to JTAG.
991 Once you know the @file{interface.cfg} file to use, you may
992 need help from OpenOCD to discover what's on the board.
993 Once you find the JTAG TAPs, you can just search for appropriate
995 configuration files ... or write your own, from the bottom up.
996 @xref{autoprobing,,Autoprobing}.
998 @item You can often reuse some standard config files but
999 need to write a few new ones, probably a @file{board.cfg} file.
1000 You will be using commands described later in this User's Guide,
1001 and working with the guidelines in the next chapter.
1003 For example, there may be configuration files for your JTAG adapter
1004 and target chip, but you need a new board-specific config file
1005 giving access to your particular flash chips.
1006 Or you might need to write another target chip configuration file
1007 for a new chip built around the Cortex-M3 core.
1010 When you write new configuration files, please submit
1011 them for inclusion in the next OpenOCD release.
1012 For example, a @file{board/newboard.cfg} file will help the
1013 next users of that board, and a @file{target/newcpu.cfg}
1014 will help support users of any board using that chip.
1018 You may need to write some C code.
1019 It may be as simple as supporting a new FT2232 or parport
1020 based adapter; a bit more involved, like a NAND or NOR flash
1021 controller driver; or a big piece of work like supporting
1022 a new chip architecture.
1025 Reuse the existing config files when you can.
1026 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1027 You may find a board configuration that's a good example to follow.
1029 When you write config files, separate the reusable parts
1030 (things every user of that interface, chip, or board needs)
1031 from ones specific to your environment and debugging approach.
1035 For example, a @code{gdb-attach} event handler that invokes
1036 the @command{reset init} command will interfere with debugging
1037 early boot code, which performs some of the same actions
1038 that the @code{reset-init} event handler does.
1041 Likewise, the @command{arm9 vector_catch} command (or
1042 @cindex vector_catch
1043 its siblings @command{xscale vector_catch}
1044 and @command{cortex_m vector_catch}) can be a time-saver
1045 during some debug sessions, but don't make everyone use that either.
1046 Keep those kinds of debugging aids in your user config file,
1047 along with messaging and tracing setup.
1048 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1051 You might need to override some defaults.
1052 For example, you might need to move, shrink, or back up the target's
1053 work area if your application needs much SRAM.
1056 TCP/IP port configuration is another example of something which
1057 is environment-specific, and should only appear in
1058 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1061 @section Project-Specific Utilities
1063 A few project-specific utility
1064 routines may well speed up your work.
1065 Write them, and keep them in your project's user config file.
1067 For example, if you are making a boot loader work on a
1068 board, it's nice to be able to debug the ``after it's
1069 loaded to RAM'' parts separately from the finicky early
1070 code which sets up the DDR RAM controller and clocks.
1071 A script like this one, or a more GDB-aware sibling,
1075 proc ramboot @{ @} @{
1076 # Reset, running the target's "reset-init" scripts
1077 # to initialize clocks and the DDR RAM controller.
1078 # Leave the CPU halted.
1081 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1082 load_image u-boot.bin 0x20000000
1089 Then once that code is working you will need to make it
1090 boot from NOR flash; a different utility would help.
1091 Alternatively, some developers write to flash using GDB.
1092 (You might use a similar script if you're working with a flash
1093 based microcontroller application instead of a boot loader.)
1096 proc newboot @{ @} @{
1097 # Reset, leaving the CPU halted. The "reset-init" event
1098 # proc gives faster access to the CPU and to NOR flash;
1099 # "reset halt" would be slower.
1102 # Write standard version of U-Boot into the first two
1103 # sectors of NOR flash ... the standard version should
1104 # do the same lowlevel init as "reset-init".
1105 flash protect 0 0 1 off
1106 flash erase_sector 0 0 1
1107 flash write_bank 0 u-boot.bin 0x0
1108 flash protect 0 0 1 on
1110 # Reboot from scratch using that new boot loader.
1115 You may need more complicated utility procedures when booting
1117 That often involves an extra bootloader stage,
1118 running from on-chip SRAM to perform DDR RAM setup so it can load
1119 the main bootloader code (which won't fit into that SRAM).
1121 Other helper scripts might be used to write production system images,
1122 involving considerably more than just a three stage bootloader.
1124 @section Target Software Changes
1126 Sometimes you may want to make some small changes to the software
1127 you're developing, to help make JTAG debugging work better.
1128 For example, in C or assembly language code you might
1129 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1130 handling issues like:
1134 @item @b{Watchdog Timers}...
1135 Watchdog timers are typically used to automatically reset systems if
1136 some application task doesn't periodically reset the timer. (The
1137 assumption is that the system has locked up if the task can't run.)
1138 When a JTAG debugger halts the system, that task won't be able to run
1139 and reset the timer ... potentially causing resets in the middle of
1140 your debug sessions.
1142 It's rarely a good idea to disable such watchdogs, since their usage
1143 needs to be debugged just like all other parts of your firmware.
1144 That might however be your only option.
1146 Look instead for chip-specific ways to stop the watchdog from counting
1147 while the system is in a debug halt state. It may be simplest to set
1148 that non-counting mode in your debugger startup scripts. You may however
1149 need a different approach when, for example, a motor could be physically
1150 damaged by firmware remaining inactive in a debug halt state. That might
1151 involve a type of firmware mode where that "non-counting" mode is disabled
1152 at the beginning then re-enabled at the end; a watchdog reset might fire
1153 and complicate the debug session, but hardware (or people) would be
1154 protected.@footnote{Note that many systems support a "monitor mode" debug
1155 that is a somewhat cleaner way to address such issues. You can think of
1156 it as only halting part of the system, maybe just one task,
1157 instead of the whole thing.
1158 At this writing, January 2010, OpenOCD based debugging does not support
1159 monitor mode debug, only "halt mode" debug.}
1161 @item @b{ARM Semihosting}...
1162 @cindex ARM semihosting
1163 When linked with a special runtime library provided with many
1164 toolchains@footnote{See chapter 8 "Semihosting" in
1165 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1166 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1167 The CodeSourcery EABI toolchain also includes a semihosting library.},
1168 your target code can use I/O facilities on the debug host. That library
1169 provides a small set of system calls which are handled by OpenOCD.
1170 It can let the debugger provide your system console and a file system,
1171 helping with early debugging or providing a more capable environment
1172 for sometimes-complex tasks like installing system firmware onto
1175 @item @b{ARM Wait-For-Interrupt}...
1176 Many ARM chips synchronize the JTAG clock using the core clock.
1177 Low power states which stop that core clock thus prevent JTAG access.
1178 Idle loops in tasking environments often enter those low power states
1179 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1181 You may want to @emph{disable that instruction} in source code,
1182 or otherwise prevent using that state,
1183 to ensure you can get JTAG access at any time.@footnote{As a more
1184 polite alternative, some processors have special debug-oriented
1185 registers which can be used to change various features including
1186 how the low power states are clocked while debugging.
1187 The STM32 DBGMCU_CR register is an example; at the cost of extra
1188 power consumption, JTAG can be used during low power states.}
1189 For example, the OpenOCD @command{halt} command may not
1190 work for an idle processor otherwise.
1192 @item @b{Delay after reset}...
1193 Not all chips have good support for debugger access
1194 right after reset; many LPC2xxx chips have issues here.
1195 Similarly, applications that reconfigure pins used for
1196 JTAG access as they start will also block debugger access.
1198 To work with boards like this, @emph{enable a short delay loop}
1199 the first thing after reset, before "real" startup activities.
1200 For example, one second's delay is usually more than enough
1201 time for a JTAG debugger to attach, so that
1202 early code execution can be debugged
1203 or firmware can be replaced.
1205 @item @b{Debug Communications Channel (DCC)}...
1206 Some processors include mechanisms to send messages over JTAG.
1207 Many ARM cores support these, as do some cores from other vendors.
1208 (OpenOCD may be able to use this DCC internally, speeding up some
1209 operations like writing to memory.)
1211 Your application may want to deliver various debugging messages
1212 over JTAG, by @emph{linking with a small library of code}
1213 provided with OpenOCD and using the utilities there to send
1214 various kinds of message.
1215 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1219 @section Target Hardware Setup
1221 Chip vendors often provide software development boards which
1222 are highly configurable, so that they can support all options
1223 that product boards may require. @emph{Make sure that any
1224 jumpers or switches match the system configuration you are
1227 Common issues include:
1231 @item @b{JTAG setup} ...
1232 Boards may support more than one JTAG configuration.
1233 Examples include jumpers controlling pullups versus pulldowns
1234 on the nTRST and/or nSRST signals, and choice of connectors
1235 (e.g. which of two headers on the base board,
1236 or one from a daughtercard).
1237 For some Texas Instruments boards, you may need to jumper the
1238 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1240 @item @b{Boot Modes} ...
1241 Complex chips often support multiple boot modes, controlled
1242 by external jumpers. Make sure this is set up correctly.
1243 For example many i.MX boards from NXP need to be jumpered
1244 to "ATX mode" to start booting using the on-chip ROM, when
1245 using second stage bootloader code stored in a NAND flash chip.
1247 Such explicit configuration is common, and not limited to
1248 booting from NAND. You might also need to set jumpers to
1249 start booting using code loaded from an MMC/SD card; external
1250 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1251 flash; some external host; or various other sources.
1254 @item @b{Memory Addressing} ...
1255 Boards which support multiple boot modes may also have jumpers
1256 to configure memory addressing. One board, for example, jumpers
1257 external chipselect 0 (used for booting) to address either
1258 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1259 or NAND flash. When it's jumpered to address NAND flash, that
1260 board must also be told to start booting from on-chip ROM.
1262 Your @file{board.cfg} file may also need to be told this jumper
1263 configuration, so that it can know whether to declare NOR flash
1264 using @command{flash bank} or instead declare NAND flash with
1265 @command{nand device}; and likewise which probe to perform in
1266 its @code{reset-init} handler.
1268 A closely related issue is bus width. Jumpers might need to
1269 distinguish between 8 bit or 16 bit bus access for the flash
1270 used to start booting.
1272 @item @b{Peripheral Access} ...
1273 Development boards generally provide access to every peripheral
1274 on the chip, sometimes in multiple modes (such as by providing
1275 multiple audio codec chips).
1276 This interacts with software
1277 configuration of pin multiplexing, where for example a
1278 given pin may be routed either to the MMC/SD controller
1279 or the GPIO controller. It also often interacts with
1280 configuration jumpers. One jumper may be used to route
1281 signals to an MMC/SD card slot or an expansion bus (which
1282 might in turn affect booting); others might control which
1283 audio or video codecs are used.
1287 Plus you should of course have @code{reset-init} event handlers
1288 which set up the hardware to match that jumper configuration.
1289 That includes in particular any oscillator or PLL used to clock
1290 the CPU, and any memory controllers needed to access external
1291 memory and peripherals. Without such handlers, you won't be
1292 able to access those resources without working target firmware
1293 which can do that setup ... this can be awkward when you're
1294 trying to debug that target firmware. Even if there's a ROM
1295 bootloader which handles a few issues, it rarely provides full
1296 access to all board-specific capabilities.
1299 @node Config File Guidelines
1300 @chapter Config File Guidelines
1302 This chapter is aimed at any user who needs to write a config file,
1303 including developers and integrators of OpenOCD and any user who
1304 needs to get a new board working smoothly.
1305 It provides guidelines for creating those files.
1307 You should find the following directories under
1308 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1309 them as-is where you can; or as models for new files.
1311 @item @file{interface} ...
1312 These are for debug adapters. Files that specify configuration to use
1313 specific JTAG, SWD and other adapters go here.
1314 @item @file{board} ...
1315 Think Circuit Board, PWA, PCB, they go by many names. Board files
1316 contain initialization items that are specific to a board.
1318 They reuse target configuration files, since the same
1319 microprocessor chips are used on many boards,
1320 but support for external parts varies widely. For
1321 example, the SDRAM initialization sequence for the board, or the type
1322 of external flash and what address it uses. Any initialization
1323 sequence to enable that external flash or SDRAM should be found in the
1324 board file. Boards may also contain multiple targets: two CPUs; or
1326 @item @file{target} ...
1327 Think chip. The ``target'' directory represents the JTAG TAPs
1329 which OpenOCD should control, not a board. Two common types of targets
1330 are ARM chips and FPGA or CPLD chips.
1331 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1332 the target config file defines all of them.
1333 @item @emph{more} ... browse for other library files which may be useful.
1334 For example, there are various generic and CPU-specific utilities.
1337 The @file{openocd.cfg} user config
1338 file may override features in any of the above files by
1339 setting variables before sourcing the target file, or by adding
1340 commands specific to their situation.
1342 @section Interface Config Files
1344 The user config file
1345 should be able to source one of these files with a command like this:
1348 source [find interface/FOOBAR.cfg]
1351 A preconfigured interface file should exist for every debug adapter
1352 in use today with OpenOCD.
1353 That said, perhaps some of these config files
1354 have only been used by the developer who created it.
1356 A separate chapter gives information about how to set these up.
1357 @xref{Debug Adapter Configuration}.
1358 Read the OpenOCD source code (and Developer's Guide)
1359 if you have a new kind of hardware interface
1360 and need to provide a driver for it.
1362 @deffn {Command} {find} 'filename'
1363 Prints full path to @var{filename} according to OpenOCD search rules.
1366 @deffn {Command} {ocd_find} 'filename'
1367 Prints full path to @var{filename} according to OpenOCD search rules. This
1368 is a low level function used by the @command{find}. Usually you want
1369 to use @command{find}, instead.
1372 @section Board Config Files
1373 @cindex config file, board
1374 @cindex board config file
1376 The user config file
1377 should be able to source one of these files with a command like this:
1380 source [find board/FOOBAR.cfg]
1383 The point of a board config file is to package everything
1384 about a given board that user config files need to know.
1385 In summary the board files should contain (if present)
1388 @item One or more @command{source [find target/...cfg]} statements
1389 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1390 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1391 @item Target @code{reset} handlers for SDRAM and I/O configuration
1392 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1393 @item All things that are not ``inside a chip''
1396 Generic things inside target chips belong in target config files,
1397 not board config files. So for example a @code{reset-init} event
1398 handler should know board-specific oscillator and PLL parameters,
1399 which it passes to target-specific utility code.
1401 The most complex task of a board config file is creating such a
1402 @code{reset-init} event handler.
1403 Define those handlers last, after you verify the rest of the board
1404 configuration works.
1406 @subsection Communication Between Config files
1408 In addition to target-specific utility code, another way that
1409 board and target config files communicate is by following a
1410 convention on how to use certain variables.
1412 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1413 Thus the rule we follow in OpenOCD is this: Variables that begin with
1414 a leading underscore are temporary in nature, and can be modified and
1415 used at will within a target configuration file.
1417 Complex board config files can do the things like this,
1418 for a board with three chips:
1421 # Chip #1: PXA270 for network side, big endian
1422 set CHIPNAME network
1424 source [find target/pxa270.cfg]
1425 # on return: _TARGETNAME = network.cpu
1426 # other commands can refer to the "network.cpu" target.
1427 $_TARGETNAME configure .... events for this CPU..
1429 # Chip #2: PXA270 for video side, little endian
1432 source [find target/pxa270.cfg]
1433 # on return: _TARGETNAME = video.cpu
1434 # other commands can refer to the "video.cpu" target.
1435 $_TARGETNAME configure .... events for this CPU..
1437 # Chip #3: Xilinx FPGA for glue logic
1440 source [find target/spartan3.cfg]
1443 That example is oversimplified because it doesn't show any flash memory,
1444 or the @code{reset-init} event handlers to initialize external DRAM
1445 or (assuming it needs it) load a configuration into the FPGA.
1446 Such features are usually needed for low-level work with many boards,
1447 where ``low level'' implies that the board initialization software may
1448 not be working. (That's a common reason to need JTAG tools. Another
1449 is to enable working with microcontroller-based systems, which often
1450 have no debugging support except a JTAG connector.)
1452 Target config files may also export utility functions to board and user
1453 config files. Such functions should use name prefixes, to help avoid
1456 Board files could also accept input variables from user config files.
1457 For example, there might be a @code{J4_JUMPER} setting used to identify
1458 what kind of flash memory a development board is using, or how to set
1459 up other clocks and peripherals.
1461 @subsection Variable Naming Convention
1462 @cindex variable names
1464 Most boards have only one instance of a chip.
1465 However, it should be easy to create a board with more than
1466 one such chip (as shown above).
1467 Accordingly, we encourage these conventions for naming
1468 variables associated with different @file{target.cfg} files,
1469 to promote consistency and
1470 so that board files can override target defaults.
1472 Inputs to target config files include:
1475 @item @code{CHIPNAME} ...
1476 This gives a name to the overall chip, and is used as part of
1477 tap identifier dotted names.
1478 While the default is normally provided by the chip manufacturer,
1479 board files may need to distinguish between instances of a chip.
1480 @item @code{ENDIAN} ...
1481 By default @option{little} - although chips may hard-wire @option{big}.
1482 Chips that can't change endianness don't need to use this variable.
1483 @item @code{CPUTAPID} ...
1484 When OpenOCD examines the JTAG chain, it can be told verify the
1485 chips against the JTAG IDCODE register.
1486 The target file will hold one or more defaults, but sometimes the
1487 chip in a board will use a different ID (perhaps a newer revision).
1490 Outputs from target config files include:
1493 @item @code{_TARGETNAME} ...
1494 By convention, this variable is created by the target configuration
1495 script. The board configuration file may make use of this variable to
1496 configure things like a ``reset init'' script, or other things
1497 specific to that board and that target.
1498 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1499 @code{_TARGETNAME1}, ... etc.
1502 @subsection The reset-init Event Handler
1503 @cindex event, reset-init
1504 @cindex reset-init handler
1506 Board config files run in the OpenOCD configuration stage;
1507 they can't use TAPs or targets, since they haven't been
1509 This means you can't write memory or access chip registers;
1510 you can't even verify that a flash chip is present.
1511 That's done later in event handlers, of which the target @code{reset-init}
1512 handler is one of the most important.
1514 Except on microcontrollers, the basic job of @code{reset-init} event
1515 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1516 Microcontrollers rarely use boot loaders; they run right out of their
1517 on-chip flash and SRAM memory. But they may want to use one of these
1518 handlers too, if just for developer convenience.
1521 Because this is so very board-specific, and chip-specific, no examples
1523 Instead, look at the board config files distributed with OpenOCD.
1524 If you have a boot loader, its source code will help; so will
1525 configuration files for other JTAG tools
1526 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1529 Some of this code could probably be shared between different boards.
1530 For example, setting up a DRAM controller often doesn't differ by
1531 much except the bus width (16 bits or 32?) and memory timings, so a
1532 reusable TCL procedure loaded by the @file{target.cfg} file might take
1533 those as parameters.
1534 Similarly with oscillator, PLL, and clock setup;
1535 and disabling the watchdog.
1536 Structure the code cleanly, and provide comments to help
1537 the next developer doing such work.
1538 (@emph{You might be that next person} trying to reuse init code!)
1540 The last thing normally done in a @code{reset-init} handler is probing
1541 whatever flash memory was configured. For most chips that needs to be
1542 done while the associated target is halted, either because JTAG memory
1543 access uses the CPU or to prevent conflicting CPU access.
1545 @subsection JTAG Clock Rate
1547 Before your @code{reset-init} handler has set up
1548 the PLLs and clocking, you may need to run with
1549 a low JTAG clock rate.
1550 @xref{jtagspeed,,JTAG Speed}.
1551 Then you'd increase that rate after your handler has
1552 made it possible to use the faster JTAG clock.
1553 When the initial low speed is board-specific, for example
1554 because it depends on a board-specific oscillator speed, then
1555 you should probably set it up in the board config file;
1556 if it's target-specific, it belongs in the target config file.
1558 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1559 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1560 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1561 Consult chip documentation to determine the peak JTAG clock rate,
1562 which might be less than that.
1565 On most ARMs, JTAG clock detection is coupled to the core clock, so
1566 software using a @option{wait for interrupt} operation blocks JTAG access.
1567 Adaptive clocking provides a partial workaround, but a more complete
1568 solution just avoids using that instruction with JTAG debuggers.
1571 If both the chip and the board support adaptive clocking,
1572 use the @command{jtag_rclk}
1573 command, in case your board is used with JTAG adapter which
1574 also supports it. Otherwise use @command{adapter speed}.
1575 Set the slow rate at the beginning of the reset sequence,
1576 and the faster rate as soon as the clocks are at full speed.
1578 @anchor{theinitboardprocedure}
1579 @subsection The init_board procedure
1580 @cindex init_board procedure
1582 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1583 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1584 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1585 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1586 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1587 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1588 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1589 Additionally ``linear'' board config file will most likely fail when target config file uses
1590 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1591 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1592 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1593 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1595 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1596 the original), allowing greater code reuse.
1599 ### board_file.cfg ###
1601 # source target file that does most of the config in init_targets
1602 source [find target/target.cfg]
1604 proc enable_fast_clock @{@} @{
1605 # enables fast on-board clock source
1606 # configures the chip to use it
1609 # initialize only board specifics - reset, clock, adapter frequency
1610 proc init_board @{@} @{
1611 reset_config trst_and_srst trst_pulls_srst
1613 $_TARGETNAME configure -event reset-start @{
1617 $_TARGETNAME configure -event reset-init @{
1624 @section Target Config Files
1625 @cindex config file, target
1626 @cindex target config file
1628 Board config files communicate with target config files using
1629 naming conventions as described above, and may source one or
1630 more target config files like this:
1633 source [find target/FOOBAR.cfg]
1636 The point of a target config file is to package everything
1637 about a given chip that board config files need to know.
1638 In summary the target files should contain
1642 @item Add TAPs to the scan chain
1643 @item Add CPU targets (includes GDB support)
1644 @item CPU/Chip/CPU-Core specific features
1648 As a rule of thumb, a target file sets up only one chip.
1649 For a microcontroller, that will often include a single TAP,
1650 which is a CPU needing a GDB target, and its on-chip flash.
1652 More complex chips may include multiple TAPs, and the target
1653 config file may need to define them all before OpenOCD
1654 can talk to the chip.
1655 For example, some phone chips have JTAG scan chains that include
1656 an ARM core for operating system use, a DSP,
1657 another ARM core embedded in an image processing engine,
1658 and other processing engines.
1660 @subsection Default Value Boiler Plate Code
1662 All target configuration files should start with code like this,
1663 letting board config files express environment-specific
1664 differences in how things should be set up.
1667 # Boards may override chip names, perhaps based on role,
1668 # but the default should match what the vendor uses
1669 if @{ [info exists CHIPNAME] @} @{
1670 set _CHIPNAME $CHIPNAME
1672 set _CHIPNAME sam7x256
1675 # ONLY use ENDIAN with targets that can change it.
1676 if @{ [info exists ENDIAN] @} @{
1682 # TAP identifiers may change as chips mature, for example with
1683 # new revision fields (the "3" here). Pick a good default; you
1684 # can pass several such identifiers to the "jtag newtap" command.
1685 if @{ [info exists CPUTAPID ] @} @{
1686 set _CPUTAPID $CPUTAPID
1688 set _CPUTAPID 0x3f0f0f0f
1691 @c but 0x3f0f0f0f is for an str73x part ...
1693 @emph{Remember:} Board config files may include multiple target
1694 config files, or the same target file multiple times
1695 (changing at least @code{CHIPNAME}).
1697 Likewise, the target configuration file should define
1698 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1699 use it later on when defining debug targets:
1702 set _TARGETNAME $_CHIPNAME.cpu
1703 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1706 @subsection Adding TAPs to the Scan Chain
1707 After the ``defaults'' are set up,
1708 add the TAPs on each chip to the JTAG scan chain.
1709 @xref{TAP Declaration}, and the naming convention
1712 In the simplest case the chip has only one TAP,
1713 probably for a CPU or FPGA.
1714 The config file for the Atmel AT91SAM7X256
1715 looks (in part) like this:
1718 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1721 A board with two such at91sam7 chips would be able
1722 to source such a config file twice, with different
1723 values for @code{CHIPNAME}, so
1724 it adds a different TAP each time.
1726 If there are nonzero @option{-expected-id} values,
1727 OpenOCD attempts to verify the actual tap id against those values.
1728 It will issue error messages if there is mismatch, which
1729 can help to pinpoint problems in OpenOCD configurations.
1732 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1733 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1734 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1735 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1736 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1739 There are more complex examples too, with chips that have
1740 multiple TAPs. Ones worth looking at include:
1743 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1744 plus a JRC to enable them
1745 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1746 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1747 is not currently used)
1750 @subsection Add CPU targets
1752 After adding a TAP for a CPU, you should set it up so that
1753 GDB and other commands can use it.
1754 @xref{CPU Configuration}.
1755 For the at91sam7 example above, the command can look like this;
1756 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1757 to little endian, and this chip doesn't support changing that.
1760 set _TARGETNAME $_CHIPNAME.cpu
1761 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1764 Work areas are small RAM areas associated with CPU targets.
1765 They are used by OpenOCD to speed up downloads,
1766 and to download small snippets of code to program flash chips.
1767 If the chip includes a form of ``on-chip-ram'' - and many do - define
1768 a work area if you can.
1769 Again using the at91sam7 as an example, this can look like:
1772 $_TARGETNAME configure -work-area-phys 0x00200000 \
1773 -work-area-size 0x4000 -work-area-backup 0
1776 @anchor{definecputargetsworkinginsmp}
1777 @subsection Define CPU targets working in SMP
1779 After setting targets, you can define a list of targets working in SMP.
1782 set _TARGETNAME_1 $_CHIPNAME.cpu1
1783 set _TARGETNAME_2 $_CHIPNAME.cpu2
1784 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1785 -coreid 0 -dbgbase $_DAP_DBG1
1786 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1787 -coreid 1 -dbgbase $_DAP_DBG2
1788 #define 2 targets working in smp.
1789 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1791 In the above example on cortex_a, 2 cpus are working in SMP.
1792 In SMP only one GDB instance is created and :
1794 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1795 @item halt command triggers the halt of all targets in the list.
1796 @item resume command triggers the write context and the restart of all targets in the list.
1797 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1798 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1799 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1802 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1803 command have been implemented.
1805 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1806 @item cortex_a smp off : disable SMP mode, the current target is the one
1807 displayed in the GDB session, only this target is now controlled by GDB
1808 session. This behaviour is useful during system boot up.
1809 @item cortex_a smp : display current SMP mode.
1810 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1817 #0 : coreid 0 is displayed to GDB ,
1818 #-> -1 : next resume triggers a real resume
1819 > cortex_a smp_gdb 1
1821 #0 :coreid 0 is displayed to GDB ,
1822 #->1 : next resume displays coreid 1 to GDB
1826 #1 :coreid 1 is displayed to GDB ,
1827 #->1 : next resume displays coreid 1 to GDB
1828 > cortex_a smp_gdb -1
1830 #1 :coreid 1 is displayed to GDB,
1831 #->-1 : next resume triggers a real resume
1835 @subsection Chip Reset Setup
1837 As a rule, you should put the @command{reset_config} command
1838 into the board file. Most things you think you know about a
1839 chip can be tweaked by the board.
1841 Some chips have specific ways the TRST and SRST signals are
1842 managed. In the unusual case that these are @emph{chip specific}
1843 and can never be changed by board wiring, they could go here.
1844 For example, some chips can't support JTAG debugging without
1847 Provide a @code{reset-assert} event handler if you can.
1848 Such a handler uses JTAG operations to reset the target,
1849 letting this target config be used in systems which don't
1850 provide the optional SRST signal, or on systems where you
1851 don't want to reset all targets at once.
1852 Such a handler might write to chip registers to force a reset,
1853 use a JRC to do that (preferable -- the target may be wedged!),
1854 or force a watchdog timer to trigger.
1855 (For Cortex-M targets, this is not necessary. The target
1856 driver knows how to use trigger an NVIC reset when SRST is
1859 Some chips need special attention during reset handling if
1860 they're going to be used with JTAG.
1861 An example might be needing to send some commands right
1862 after the target's TAP has been reset, providing a
1863 @code{reset-deassert-post} event handler that writes a chip
1864 register to report that JTAG debugging is being done.
1865 Another would be reconfiguring the watchdog so that it stops
1866 counting while the core is halted in the debugger.
1868 JTAG clocking constraints often change during reset, and in
1869 some cases target config files (rather than board config files)
1870 are the right places to handle some of those issues.
1871 For example, immediately after reset most chips run using a
1872 slower clock than they will use later.
1873 That means that after reset (and potentially, as OpenOCD
1874 first starts up) they must use a slower JTAG clock rate
1875 than they will use later.
1876 @xref{jtagspeed,,JTAG Speed}.
1878 @quotation Important
1879 When you are debugging code that runs right after chip
1880 reset, getting these issues right is critical.
1881 In particular, if you see intermittent failures when
1882 OpenOCD verifies the scan chain after reset,
1883 look at how you are setting up JTAG clocking.
1886 @anchor{theinittargetsprocedure}
1887 @subsection The init_targets procedure
1888 @cindex init_targets procedure
1890 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1891 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1892 procedure called @code{init_targets}, which will be executed when entering run stage
1893 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1894 Such procedure can be overridden by ``next level'' script (which sources the original).
1895 This concept facilitates code reuse when basic target config files provide generic configuration
1896 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1897 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1898 because sourcing them executes every initialization commands they provide.
1901 ### generic_file.cfg ###
1903 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1904 # basic initialization procedure ...
1907 proc init_targets @{@} @{
1908 # initializes generic chip with 4kB of flash and 1kB of RAM
1909 setup_my_chip MY_GENERIC_CHIP 4096 1024
1912 ### specific_file.cfg ###
1914 source [find target/generic_file.cfg]
1916 proc init_targets @{@} @{
1917 # initializes specific chip with 128kB of flash and 64kB of RAM
1918 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1922 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1923 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1925 For an example of this scheme see LPC2000 target config files.
1927 The @code{init_boards} procedure is a similar concept concerning board config files
1928 (@xref{theinitboardprocedure,,The init_board procedure}.)
1930 @anchor{theinittargeteventsprocedure}
1931 @subsection The init_target_events procedure
1932 @cindex init_target_events procedure
1934 A special procedure called @code{init_target_events} is run just after
1935 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1936 procedure}.) and before @code{init_board}
1937 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1938 to set up default target events for the targets that do not have those
1939 events already assigned.
1941 @subsection ARM Core Specific Hacks
1943 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1944 special high speed download features - enable it.
1946 If present, the MMU, the MPU and the CACHE should be disabled.
1948 Some ARM cores are equipped with trace support, which permits
1949 examination of the instruction and data bus activity. Trace
1950 activity is controlled through an ``Embedded Trace Module'' (ETM)
1951 on one of the core's scan chains. The ETM emits voluminous data
1952 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1953 If you are using an external trace port,
1954 configure it in your board config file.
1955 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1956 configure it in your target config file.
1959 etm config $_TARGETNAME 16 normal full etb
1960 etb config $_TARGETNAME $_CHIPNAME.etb
1963 @subsection Internal Flash Configuration
1965 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1967 @b{Never ever} in the ``target configuration file'' define any type of
1968 flash that is external to the chip. (For example a BOOT flash on
1969 Chip Select 0.) Such flash information goes in a board file - not
1970 the TARGET (chip) file.
1974 @item at91sam7x256 - has 256K flash YES enable it.
1975 @item str912 - has flash internal YES enable it.
1976 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1977 @item pxa270 - again - CS0 flash - it goes in the board file.
1980 @anchor{translatingconfigurationfiles}
1981 @section Translating Configuration Files
1983 If you have a configuration file for another hardware debugger
1984 or toolset (Abatron, BDI2000, BDI3000, CCS,
1985 Lauterbach, SEGGER, Macraigor, etc.), translating
1986 it into OpenOCD syntax is often quite straightforward. The most tricky
1987 part of creating a configuration script is oftentimes the reset init
1988 sequence where e.g. PLLs, DRAM and the like is set up.
1990 One trick that you can use when translating is to write small
1991 Tcl procedures to translate the syntax into OpenOCD syntax. This
1992 can avoid manual translation errors and make it easier to
1993 convert other scripts later on.
1995 Example of transforming quirky arguments to a simple search and
1999 # Lauterbach syntax(?)
2001 # Data.Set c15:0x042f %long 0x40000015
2003 # OpenOCD syntax when using procedure below.
2005 # setc15 0x01 0x00050078
2007 proc setc15 @{regs value@} @{
2010 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2012 arm mcr 15 [expr @{($regs >> 12) & 0x7@}] \
2013 [expr @{($regs >> 0) & 0xf@}] [expr @{($regs >> 4) & 0xf@}] \
2014 [expr @{($regs >> 8) & 0x7@}] $value
2020 @node Server Configuration
2021 @chapter Server Configuration
2022 @cindex initialization
2023 The commands here are commonly found in the openocd.cfg file and are
2024 used to specify what TCP/IP ports are used, and how GDB should be
2027 @anchor{configurationstage}
2028 @section Configuration Stage
2029 @cindex configuration stage
2030 @cindex config command
2032 When the OpenOCD server process starts up, it enters a
2033 @emph{configuration stage} which is the only time that
2034 certain commands, @emph{configuration commands}, may be issued.
2035 Normally, configuration commands are only available
2036 inside startup scripts.
2038 In this manual, the definition of a configuration command is
2039 presented as a @emph{Config Command}, not as a @emph{Command}
2040 which may be issued interactively.
2041 The runtime @command{help} command also highlights configuration
2042 commands, and those which may be issued at any time.
2044 Those configuration commands include declaration of TAPs,
2046 the interface used for JTAG communication,
2047 and other basic setup.
2048 The server must leave the configuration stage before it
2049 may access or activate TAPs.
2050 After it leaves this stage, configuration commands may no
2053 @deffn {Command} {command mode} [command_name]
2054 Returns the command modes allowed by a command: 'any', 'config', or
2055 'exec'. If no command is specified, returns the current command
2056 mode. Returns 'unknown' if an unknown command is given. Command can be
2057 multiple tokens. (command valid any time)
2059 In this document, the modes are described as stages, 'config' and
2060 'exec' mode correspond configuration stage and run stage. 'any' means
2061 the command can be executed in either
2062 stages. @xref{configurationstage,,Configuration Stage}, and
2063 @xref{enteringtherunstage,,Entering the Run Stage}.
2066 @anchor{enteringtherunstage}
2067 @section Entering the Run Stage
2069 The first thing OpenOCD does after leaving the configuration
2070 stage is to verify that it can talk to the scan chain
2071 (list of TAPs) which has been configured.
2072 It will warn if it doesn't find TAPs it expects to find,
2073 or finds TAPs that aren't supposed to be there.
2074 You should see no errors at this point.
2075 If you see errors, resolve them by correcting the
2076 commands you used to configure the server.
2077 Common errors include using an initial JTAG speed that's too
2078 fast, and not providing the right IDCODE values for the TAPs
2081 Once OpenOCD has entered the run stage, a number of commands
2083 A number of these relate to the debug targets you may have declared.
2084 For example, the @command{mww} command will not be available until
2085 a target has been successfully instantiated.
2086 If you want to use those commands, you may need to force
2087 entry to the run stage.
2089 @deffn {Config Command} {init}
2090 This command terminates the configuration stage and
2091 enters the run stage. This helps when you need to have
2092 the startup scripts manage tasks such as resetting the target,
2093 programming flash, etc. To reset the CPU upon startup, add "init" and
2094 "reset" at the end of the config script or at the end of the OpenOCD
2095 command line using the @option{-c} command line switch.
2097 If this command does not appear in any startup/configuration file
2098 OpenOCD executes the command for you after processing all
2099 configuration files and/or command line options.
2101 @b{NOTE:} This command normally occurs near the end of your
2102 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2103 targets ready. For example: If your openocd.cfg file needs to
2104 read/write memory on your target, @command{init} must occur before
2105 the memory read/write commands. This includes @command{nand probe}.
2107 @command{init} calls the following internal OpenOCD commands to initialize
2108 corresponding subsystems:
2109 @deffn {Config Command} {target init}
2110 @deffnx {Command} {transport init}
2111 @deffnx {Command} {dap init}
2112 @deffnx {Config Command} {flash init}
2113 @deffnx {Config Command} {nand init}
2114 @deffnx {Config Command} {pld init}
2115 @deffnx {Command} {tpiu init}
2119 @deffn {Config Command} {noinit}
2120 Prevent OpenOCD from implicit @command{init} call at the end of startup.
2121 Allows issuing configuration commands over telnet or Tcl connection.
2122 When you are done with configuration use @command{init} to enter
2126 @deffn {Overridable Procedure} {jtag_init}
2127 This is invoked at server startup to verify that it can talk
2128 to the scan chain (list of TAPs) which has been configured.
2130 The default implementation first tries @command{jtag arp_init},
2131 which uses only a lightweight JTAG reset before examining the
2133 If that fails, it tries again, using a harder reset
2134 from the overridable procedure @command{init_reset}.
2136 Implementations must have verified the JTAG scan chain before
2138 This is done by calling @command{jtag arp_init}
2139 (or @command{jtag arp_init-reset}).
2143 @section TCP/IP Ports
2148 The OpenOCD server accepts remote commands in several syntaxes.
2149 Each syntax uses a different TCP/IP port, which you may specify
2150 only during configuration (before those ports are opened).
2152 For reasons including security, you may wish to prevent remote
2153 access using one or more of these ports.
2154 In such cases, just specify the relevant port number as "disabled".
2155 If you disable all access through TCP/IP, you will need to
2156 use the command line @option{-pipe} option.
2159 @deffn {Config Command} {gdb_port} [number]
2161 Normally gdb listens to a TCP/IP port, but GDB can also
2162 communicate via pipes(stdin/out or named pipes). The name
2163 "gdb_port" stuck because it covers probably more than 90% of
2164 the normal use cases.
2166 No arguments reports GDB port. "pipe" means listen to stdin
2167 output to stdout, an integer is base port number, "disabled"
2168 disables the gdb server.
2170 When using "pipe", also use log_output to redirect the log
2171 output to a file so as not to flood the stdin/out pipes.
2173 Any other string is interpreted as named pipe to listen to.
2174 Output pipe is the same name as input pipe, but with 'o' appended,
2175 e.g. /var/gdb, /var/gdbo.
2177 The GDB port for the first target will be the base port, the
2178 second target will listen on gdb_port + 1, and so on.
2179 When not specified during the configuration stage,
2180 the port @var{number} defaults to 3333.
2181 When @var{number} is not a numeric value, incrementing it to compute
2182 the next port number does not work. In this case, specify the proper
2183 @var{number} for each target by using the option @code{-gdb-port} of the
2184 commands @command{target create} or @command{$target_name configure}.
2185 @xref{gdbportoverride,,option -gdb-port}.
2187 Note: when using "gdb_port pipe", increasing the default remote timeout in
2188 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2189 cause initialization to fail with "Unknown remote qXfer reply: OK".
2192 @deffn {Config Command} {tcl_port} [number]
2193 Specify or query the port used for a simplified RPC
2194 connection that can be used by clients to issue TCL commands and get the
2195 output from the Tcl engine.
2196 Intended as a machine interface.
2197 When not specified during the configuration stage,
2198 the port @var{number} defaults to 6666.
2199 When specified as "disabled", this service is not activated.
2202 @deffn {Config Command} {telnet_port} [number]
2203 Specify or query the
2204 port on which to listen for incoming telnet connections.
2205 This port is intended for interaction with one human through TCL commands.
2206 When not specified during the configuration stage,
2207 the port @var{number} defaults to 4444.
2208 When specified as "disabled", this service is not activated.
2211 @anchor{gdbconfiguration}
2212 @section GDB Configuration
2214 @cindex GDB configuration
2215 You can reconfigure some GDB behaviors if needed.
2216 The ones listed here are static and global.
2217 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2218 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2220 @anchor{gdbbreakpointoverride}
2221 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2222 Force breakpoint type for gdb @command{break} commands.
2223 This option supports GDB GUIs which don't
2224 distinguish hard versus soft breakpoints, if the default OpenOCD and
2225 GDB behaviour is not sufficient. GDB normally uses hardware
2226 breakpoints if the memory map has been set up for flash regions.
2229 @anchor{gdbflashprogram}
2230 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2231 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2232 vFlash packet is received.
2233 The default behaviour is @option{enable}.
2236 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2237 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2238 requested. GDB will then know when to set hardware breakpoints, and program flash
2239 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2240 for flash programming to work.
2241 Default behaviour is @option{enable}.
2242 @xref{gdbflashprogram,,gdb_flash_program}.
2245 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2246 Specifies whether data aborts cause an error to be reported
2247 by GDB memory read packets.
2248 The default behaviour is @option{disable};
2249 use @option{enable} see these errors reported.
2252 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2253 Specifies whether register accesses requested by GDB register read/write
2254 packets report errors or not.
2255 The default behaviour is @option{disable};
2256 use @option{enable} see these errors reported.
2259 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2260 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2261 The default behaviour is @option{enable}.
2264 @deffn {Command} {gdb_save_tdesc}
2265 Saves the target description file to the local file system.
2267 The file name is @i{target_name}.xml.
2270 @anchor{eventpolling}
2271 @section Event Polling
2273 Hardware debuggers are parts of asynchronous systems,
2274 where significant events can happen at any time.
2275 The OpenOCD server needs to detect some of these events,
2276 so it can report them to through TCL command line
2279 Examples of such events include:
2282 @item One of the targets can stop running ... maybe it triggers
2283 a code breakpoint or data watchpoint, or halts itself.
2284 @item Messages may be sent over ``debug message'' channels ... many
2285 targets support such messages sent over JTAG,
2286 for receipt by the person debugging or tools.
2287 @item Loss of power ... some adapters can detect these events.
2288 @item Resets not issued through JTAG ... such reset sources
2289 can include button presses or other system hardware, sometimes
2290 including the target itself (perhaps through a watchdog).
2291 @item Debug instrumentation sometimes supports event triggering
2292 such as ``trace buffer full'' (so it can quickly be emptied)
2293 or other signals (to correlate with code behavior).
2296 None of those events are signaled through standard JTAG signals.
2297 However, most conventions for JTAG connectors include voltage
2298 level and system reset (SRST) signal detection.
2299 Some connectors also include instrumentation signals, which
2300 can imply events when those signals are inputs.
2302 In general, OpenOCD needs to periodically check for those events,
2303 either by looking at the status of signals on the JTAG connector
2304 or by sending synchronous ``tell me your status'' JTAG requests
2305 to the various active targets.
2306 There is a command to manage and monitor that polling,
2307 which is normally done in the background.
2309 @deffn {Command} {poll} [@option{on}|@option{off}]
2310 Poll the current target for its current state.
2311 (Also, @pxref{targetcurstate,,target curstate}.)
2312 If that target is in debug mode, architecture
2313 specific information about the current state is printed.
2314 An optional parameter
2315 allows background polling to be enabled and disabled.
2317 You could use this from the TCL command shell, or
2318 from GDB using @command{monitor poll} command.
2319 Leave background polling enabled while you're using GDB.
2322 background polling: on
2323 target state: halted
2324 target halted in ARM state due to debug-request, \
2325 current mode: Supervisor
2326 cpsr: 0x800000d3 pc: 0x11081bfc
2327 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2332 @node Debug Adapter Configuration
2333 @chapter Debug Adapter Configuration
2334 @cindex config file, interface
2335 @cindex interface config file
2337 Correctly installing OpenOCD includes making your operating system give
2338 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2339 are used to select which one is used, and to configure how it is used.
2342 Because OpenOCD started out with a focus purely on JTAG, you may find
2343 places where it wrongly presumes JTAG is the only transport protocol
2344 in use. Be aware that recent versions of OpenOCD are removing that
2345 limitation. JTAG remains more functional than most other transports.
2346 Other transports do not support boundary scan operations, or may be
2347 specific to a given chip vendor. Some might be usable only for
2348 programming flash memory, instead of also for debugging.
2351 Debug Adapters/Interfaces/Dongles are normally configured
2352 through commands in an interface configuration
2353 file which is sourced by your @file{openocd.cfg} file, or
2354 through a command line @option{-f interface/....cfg} option.
2357 source [find interface/olimex-jtag-tiny.cfg]
2361 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2362 A few cases are so simple that you only need to say what driver to use:
2366 adapter driver jlink
2369 Most adapters need a bit more configuration than that.
2372 @section Adapter Configuration
2374 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2375 using. Depending on the type of adapter, you may need to use one or
2376 more additional commands to further identify or configure the adapter.
2378 @deffn {Config Command} {adapter driver} name
2379 Use the adapter driver @var{name} to connect to the
2383 @deffn {Command} {adapter list}
2384 List the debug adapter drivers that have been built into
2385 the running copy of OpenOCD.
2387 @deffn {Config Command} {adapter transports} transport_name+
2388 Specifies the transports supported by this debug adapter.
2389 The adapter driver builds-in similar knowledge; use this only
2390 when external configuration (such as jumpering) changes what
2391 the hardware can support.
2396 @deffn {Command} {adapter name}
2397 Returns the name of the debug adapter driver being used.
2400 @anchor{adapter_usb_location}
2401 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2402 Displays or specifies the physical USB port of the adapter to use. The path
2403 roots at @var{bus} and walks down the physical ports, with each
2404 @var{port} option specifying a deeper level in the bus topology, the last
2405 @var{port} denoting where the target adapter is actually plugged.
2406 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2408 This command is only available if your libusb1 is at least version 1.0.16.
2411 @deffn {Config Command} {adapter serial} serial_string
2412 Specifies the @var{serial_string} of the adapter to use.
2413 If this command is not specified, serial strings are not checked.
2414 Only the following adapter drivers use the serial string from this command:
2415 aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
2416 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
2419 @section Interface Drivers
2421 Each of the interface drivers listed here must be explicitly
2422 enabled when OpenOCD is configured, in order to be made
2423 available at run time.
2425 @deffn {Interface Driver} {amt_jtagaccel}
2426 Amontec Chameleon in its JTAG Accelerator configuration,
2427 connected to a PC's EPP mode parallel port.
2428 This defines some driver-specific commands:
2430 @deffn {Config Command} {parport port} number
2431 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2432 the number of the @file{/dev/parport} device.
2435 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2436 Displays status of RTCK option.
2437 Optionally sets that option first.
2441 @deffn {Interface Driver} {arm-jtag-ew}
2442 Olimex ARM-JTAG-EW USB adapter
2443 This has one driver-specific command:
2445 @deffn {Command} {armjtagew_info}
2450 @deffn {Interface Driver} {at91rm9200}
2451 Supports bitbanged JTAG from the local system,
2452 presuming that system is an Atmel AT91rm9200
2453 and a specific set of GPIOs is used.
2454 @c command: at91rm9200_device NAME
2455 @c chooses among list of bit configs ... only one option
2458 @deffn {Interface Driver} {cmsis-dap}
2459 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2462 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2463 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2464 the driver will attempt to auto detect the CMSIS-DAP device.
2465 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2467 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2471 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2472 Specifies how to communicate with the adapter:
2475 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2476 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2477 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2478 This is the default if @command{cmsis_dap_backend} is not specified.
2482 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2483 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2484 In most cases need not to be specified and interfaces are searched by
2485 interface string or for user class interface.
2488 @deffn {Command} {cmsis-dap info}
2489 Display various device information, like hardware version, firmware version, current bus status.
2492 @deffn {Command} {cmsis-dap cmd} number number ...
2493 Execute an arbitrary CMSIS-DAP command. Use for adapter testing or for handling
2494 of an adapter vendor specific command from a Tcl script.
2496 Take given numbers as bytes, assemble a CMSIS-DAP protocol command packet
2497 from them and send it to the adapter. The first 4 bytes of the adapter response
2499 See @url{https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Commands__gr.html}
2503 @deffn {Interface Driver} {dummy}
2504 A dummy software-only driver for debugging.
2507 @deffn {Interface Driver} {ep93xx}
2508 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2511 @deffn {Interface Driver} {ftdi}
2512 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2513 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2515 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2516 bypassing intermediate libraries like libftdi.
2518 Support for new FTDI based adapters can be added completely through
2519 configuration files, without the need to patch and rebuild OpenOCD.
2521 The driver uses a signal abstraction to enable Tcl configuration files to
2522 define outputs for one or several FTDI GPIO. These outputs can then be
2523 controlled using the @command{ftdi set_signal} command. Special signal names
2524 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2525 will be used for their customary purpose. Inputs can be read using the
2526 @command{ftdi get_signal} command.
2528 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2529 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2530 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2531 required by the protocol, to tell the adapter to drive the data output onto
2532 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2534 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2535 be controlled differently. In order to support tristateable signals such as
2536 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2537 signal. The following output buffer configurations are supported:
2540 @item Push-pull with one FTDI output as (non-)inverted data line
2541 @item Open drain with one FTDI output as (non-)inverted output-enable
2542 @item Tristate with one FTDI output as (non-)inverted data line and another
2543 FTDI output as (non-)inverted output-enable
2544 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2545 switching data and direction as necessary
2548 These interfaces have several commands, used to configure the driver
2549 before initializing the JTAG scan chain:
2551 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2552 The vendor ID and product ID of the adapter. Up to eight
2553 [@var{vid}, @var{pid}] pairs may be given, e.g.
2555 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2559 @deffn {Config Command} {ftdi device_desc} description
2560 Provides the USB device description (the @emph{iProduct string})
2561 of the adapter. If not specified, the device description is ignored
2562 during device selection.
2565 @deffn {Config Command} {ftdi channel} channel
2566 Selects the channel of the FTDI device to use for MPSSE operations. Most
2567 adapters use the default, channel 0, but there are exceptions.
2570 @deffn {Config Command} {ftdi layout_init} data direction
2571 Specifies the initial values of the FTDI GPIO data and direction registers.
2572 Each value is a 16-bit number corresponding to the concatenation of the high
2573 and low FTDI GPIO registers. The values should be selected based on the
2574 schematics of the adapter, such that all signals are set to safe levels with
2575 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2576 and initially asserted reset signals.
2579 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2580 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2581 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2582 register bitmasks to tell the driver the connection and type of the output
2583 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2584 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2585 used with inverting data inputs and @option{-data} with non-inverting inputs.
2586 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2587 not-output-enable) input to the output buffer is connected. The options
2588 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2589 with the method @command{ftdi get_signal}.
2591 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2592 simple open-collector transistor driver would be specified with @option{-oe}
2593 only. In that case the signal can only be set to drive low or to Hi-Z and the
2594 driver will complain if the signal is set to drive high. Which means that if
2595 it's a reset signal, @command{reset_config} must be specified as
2596 @option{srst_open_drain}, not @option{srst_push_pull}.
2598 A special case is provided when @option{-data} and @option{-oe} is set to the
2599 same bitmask. Then the FTDI pin is considered being connected straight to the
2600 target without any buffer. The FTDI pin is then switched between output and
2601 input as necessary to provide the full set of low, high and Hi-Z
2602 characteristics. In all other cases, the pins specified in a signal definition
2603 are always driven by the FTDI.
2605 If @option{-alias} or @option{-nalias} is used, the signal is created
2606 identical (or with data inverted) to an already specified signal
2610 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2611 Set a previously defined signal to the specified level.
2613 @item @option{0}, drive low
2614 @item @option{1}, drive high
2615 @item @option{z}, set to high-impedance
2619 @deffn {Command} {ftdi get_signal} name
2620 Get the value of a previously defined signal.
2623 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2624 Configure TCK edge at which the adapter samples the value of the TDO signal
2626 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2627 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2628 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2629 stability at higher JTAG clocks.
2631 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2632 @item @option{falling}, sample TDO on falling edge of TCK
2636 For example adapter definitions, see the configuration files shipped in the
2637 @file{interface/ftdi} directory.
2641 @deffn {Interface Driver} {ft232r}
2642 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2643 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2644 It currently doesn't support using CBUS pins as GPIO.
2646 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2653 @item DCD(10) - SRST
2656 User can change default pinout by supplying configuration
2657 commands with GPIO numbers or RS232 signal names.
2658 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2659 They differ from physical pin numbers.
2660 For details see actual FTDI chip datasheets.
2661 Every JTAG line must be configured to unique GPIO number
2662 different than any other JTAG line, even those lines
2663 that are sometimes not used like TRST or SRST.
2677 These interfaces have several commands, used to configure the driver
2678 before initializing the JTAG scan chain:
2680 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2681 The vendor ID and product ID of the adapter. If not specified, default
2682 0x0403:0x6001 is used.
2685 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2686 Set four JTAG GPIO numbers at once.
2687 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2690 @deffn {Config Command} {ft232r tck_num} @var{tck}
2691 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2694 @deffn {Config Command} {ft232r tms_num} @var{tms}
2695 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2698 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2699 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2702 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2703 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2706 @deffn {Config Command} {ft232r trst_num} @var{trst}
2707 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2710 @deffn {Config Command} {ft232r srst_num} @var{srst}
2711 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2714 @deffn {Config Command} {ft232r restore_serial} @var{word}
2715 Restore serial port after JTAG. This USB bitmode control word
2716 (16-bit) will be sent before quit. Lower byte should
2717 set GPIO direction register to a "sane" state:
2718 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2719 byte is usually 0 to disable bitbang mode.
2720 When kernel driver reattaches, serial port should continue to work.
2721 Value 0xFFFF disables sending control word and serial port,
2722 then kernel driver will not reattach.
2723 If not specified, default 0xFFFF is used.
2728 @deffn {Interface Driver} {remote_bitbang}
2729 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2730 with a remote process and sends ASCII encoded bitbang requests to that process
2731 instead of directly driving JTAG.
2733 The remote_bitbang driver is useful for debugging software running on
2734 processors which are being simulated.
2736 @deffn {Config Command} {remote_bitbang port} number
2737 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2738 sockets instead of TCP.
2741 @deffn {Config Command} {remote_bitbang host} hostname
2742 Specifies the hostname of the remote process to connect to using TCP, or the
2743 name of the UNIX socket to use if remote_bitbang port is 0.
2746 For example, to connect remotely via TCP to the host foobar you might have
2750 adapter driver remote_bitbang
2751 remote_bitbang port 3335
2752 remote_bitbang host foobar
2755 To connect to another process running locally via UNIX sockets with socket
2759 adapter driver remote_bitbang
2760 remote_bitbang port 0
2761 remote_bitbang host mysocket
2765 @deffn {Interface Driver} {usb_blaster}
2766 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2767 for FTDI chips. These interfaces have several commands, used to
2768 configure the driver before initializing the JTAG scan chain:
2770 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2771 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2772 default values are used.
2773 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2774 Altera USB-Blaster (default):
2776 usb_blaster vid_pid 0x09FB 0x6001
2778 The following VID/PID is for Kolja Waschk's USB JTAG:
2780 usb_blaster vid_pid 0x16C0 0x06AD
2784 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2785 Sets the state or function of the unused GPIO pins on USB-Blasters
2786 (pins 6 and 8 on the female JTAG header). These pins can be used as
2787 SRST and/or TRST provided the appropriate connections are made on the
2790 For example, to use pin 6 as SRST:
2792 usb_blaster pin pin6 s
2793 reset_config srst_only
2797 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2798 Chooses the low level access method for the adapter. If not specified,
2799 @option{ftdi} is selected unless it wasn't enabled during the
2800 configure stage. USB-Blaster II needs @option{ublast2}.
2803 @deffn {Config Command} {usb_blaster firmware} @var{path}
2804 This command specifies @var{path} to access USB-Blaster II firmware
2805 image. To be used with USB-Blaster II only.
2810 @deffn {Interface Driver} {gw16012}
2811 Gateworks GW16012 JTAG programmer.
2812 This has one driver-specific command:
2814 @deffn {Config Command} {parport port} [port_number]
2815 Display either the address of the I/O port
2816 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2817 If a parameter is provided, first switch to use that port.
2818 This is a write-once setting.
2822 @deffn {Interface Driver} {jlink}
2823 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2826 @quotation Compatibility Note
2827 SEGGER released many firmware versions for the many hardware versions they
2828 produced. OpenOCD was extensively tested and intended to run on all of them,
2829 but some combinations were reported as incompatible. As a general
2830 recommendation, it is advisable to use the latest firmware version
2831 available for each hardware version. However the current V8 is a moving
2832 target, and SEGGER firmware versions released after the OpenOCD was
2833 released may not be compatible. In such cases it is recommended to
2834 revert to the last known functional version. For 0.5.0, this is from
2835 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2836 version is from "May 3 2012 18:36:22", packed with 4.46f.
2839 @deffn {Command} {jlink hwstatus}
2840 Display various hardware related information, for example target voltage and pin
2843 @deffn {Command} {jlink freemem}
2844 Display free device internal memory.
2846 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2847 Set the JTAG command version to be used. Without argument, show the actual JTAG
2850 @deffn {Command} {jlink config}
2851 Display the device configuration.
2853 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2854 Set the target power state on JTAG-pin 19. Without argument, show the target
2857 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2858 Set the MAC address of the device. Without argument, show the MAC address.
2860 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2861 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2862 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2865 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2866 Set the USB address of the device. This will also change the USB Product ID
2867 (PID) of the device. Without argument, show the USB address.
2869 @deffn {Command} {jlink config reset}
2870 Reset the current configuration.
2872 @deffn {Command} {jlink config write}
2873 Write the current configuration to the internal persistent storage.
2875 @deffn {Command} {jlink emucom write} <channel> <data>
2876 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2879 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2880 the EMUCOM channel 0x10:
2882 > jlink emucom write 0x10 aa0b23
2885 @deffn {Command} {jlink emucom read} <channel> <length>
2886 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2889 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2891 > jlink emucom read 0x0 4
2895 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2896 Set the USB address of the interface, in case more than one adapter is connected
2897 to the host. If not specified, USB addresses are not considered. Device
2898 selection via USB address is not always unambiguous. It is recommended to use
2899 the serial number instead, if possible.
2901 As a configuration command, it can be used only before 'init'.
2905 @deffn {Interface Driver} {kitprog}
2906 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2907 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2908 families, but it is possible to use it with some other devices. If you are using
2909 this adapter with a PSoC or a PRoC, you may need to add
2910 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2911 configuration script.
2913 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2914 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2915 be used with this driver, and must either be used with the cmsis-dap driver or
2916 switched back to KitProg mode. See the Cypress KitProg User Guide for
2917 instructions on how to switch KitProg modes.
2921 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2923 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2924 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2925 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2926 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2927 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2928 SWD sequence must be sent after every target reset in order to re-establish
2929 communications with the target.
2930 @item Due in part to the limitation above, KitProg devices with firmware below
2931 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2932 communicate with PSoC 5LP devices. This is because, assuming debug is not
2933 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2934 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2935 could only be sent with an acquisition sequence.
2938 @deffn {Config Command} {kitprog_init_acquire_psoc}
2939 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2940 Please be aware that the acquisition sequence hard-resets the target.
2943 @deffn {Command} {kitprog acquire_psoc}
2944 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2945 outside of the target-specific configuration scripts since it hard-resets the
2946 target as a side-effect.
2947 This is necessary for "reset halt" on some PSoC 4 series devices.
2950 @deffn {Command} {kitprog info}
2951 Display various adapter information, such as the hardware version, firmware
2952 version, and target voltage.
2956 @deffn {Interface Driver} {parport}
2957 Supports PC parallel port bit-banging cables:
2958 Wigglers, PLD download cable, and more.
2959 These interfaces have several commands, used to configure the driver
2960 before initializing the JTAG scan chain:
2962 @deffn {Config Command} {parport cable} name
2963 Set the layout of the parallel port cable used to connect to the target.
2964 This is a write-once setting.
2965 Currently valid cable @var{name} values include:
2968 @item @b{altium} Altium Universal JTAG cable.
2969 @item @b{arm-jtag} Same as original wiggler except SRST and
2970 TRST connections reversed and TRST is also inverted.
2971 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2972 in configuration mode. This is only used to
2973 program the Chameleon itself, not a connected target.
2974 @item @b{dlc5} The Xilinx Parallel cable III.
2975 @item @b{flashlink} The ST Parallel cable.
2976 @item @b{lattice} Lattice ispDOWNLOAD Cable
2977 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2979 Amontec's Chameleon Programmer. The new version available from
2980 the website uses the original Wiggler layout ('@var{wiggler}')
2981 @item @b{triton} The parallel port adapter found on the
2982 ``Karo Triton 1 Development Board''.
2983 This is also the layout used by the HollyGates design
2984 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2985 @item @b{wiggler} The original Wiggler layout, also supported by
2986 several clones, such as the Olimex ARM-JTAG
2987 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2988 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2992 @deffn {Config Command} {parport port} [port_number]
2993 Display either the address of the I/O port
2994 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2995 If a parameter is provided, first switch to use that port.
2996 This is a write-once setting.
2998 When using PPDEV to access the parallel port, use the number of the parallel port:
2999 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
3000 you may encounter a problem.
3003 @deffn {Config Command} {parport toggling_time} [nanoseconds]
3004 Displays how many nanoseconds the hardware needs to toggle TCK;
3005 the parport driver uses this value to obey the
3006 @command{adapter speed} configuration.
3007 When the optional @var{nanoseconds} parameter is given,
3008 that setting is changed before displaying the current value.
3010 The default setting should work reasonably well on commodity PC hardware.
3011 However, you may want to calibrate for your specific hardware.
3013 To measure the toggling time with a logic analyzer or a digital storage
3014 oscilloscope, follow the procedure below:
3016 > parport toggling_time 1000
3019 This sets the maximum JTAG clock speed of the hardware, but
3020 the actual speed probably deviates from the requested 500 kHz.
3021 Now, measure the time between the two closest spaced TCK transitions.
3022 You can use @command{runtest 1000} or something similar to generate a
3023 large set of samples.
3024 Update the setting to match your measurement:
3026 > parport toggling_time <measured nanoseconds>
3028 Now the clock speed will be a better match for @command{adapter speed}
3029 command given in OpenOCD scripts and event handlers.
3031 You can do something similar with many digital multimeters, but note
3032 that you'll probably need to run the clock continuously for several
3033 seconds before it decides what clock rate to show. Adjust the
3034 toggling time up or down until the measured clock rate is a good
3035 match with the rate you specified in the @command{adapter speed} command;
3040 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3041 This will configure the parallel driver to write a known
3042 cable-specific value to the parallel interface on exiting OpenOCD.
3045 For example, the interface configuration file for a
3046 classic ``Wiggler'' cable on LPT2 might look something like this:
3049 adapter driver parport
3051 parport cable wiggler
3055 @deffn {Interface Driver} {presto}
3056 ASIX PRESTO USB JTAG programmer.
3059 @deffn {Interface Driver} {rlink}
3060 Raisonance RLink USB adapter
3063 @deffn {Interface Driver} {usbprog}
3064 usbprog is a freely programmable USB adapter.
3067 @deffn {Interface Driver} {vsllink}
3068 vsllink is part of Versaloon which is a versatile USB programmer.
3071 This defines quite a few driver-specific commands,
3072 which are not currently documented here.
3076 @anchor{hla_interface}
3077 @deffn {Interface Driver} {hla}
3078 This is a driver that supports multiple High Level Adapters.
3079 This type of adapter does not expose some of the lower level api's
3080 that OpenOCD would normally use to access the target.
3082 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3083 and Nuvoton Nu-Link.
3084 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3085 versions of firmware where serial number is reset after first use. Suggest
3086 using ST firmware update utility to upgrade ST-LINK firmware even if current
3087 version reported is V2.J21.S4.
3089 @deffn {Config Command} {hla_device_desc} description
3090 Currently Not Supported.
3093 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3094 Specifies the adapter layout to use.
3097 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3098 Pairs of vendor IDs and product IDs of the device.
3101 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3102 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3103 'shared' mode using ST-Link TCP server (the default port is 7184).
3105 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3106 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3107 ST-LINK server software module}.
3110 @deffn {Command} {hla_command} command
3111 Execute a custom adapter-specific command. The @var{command} string is
3112 passed as is to the underlying adapter layout handler.
3116 @anchor{st_link_dap_interface}
3117 @deffn {Interface Driver} {st-link}
3118 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3119 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3120 directly access the arm ADIv5 DAP.
3122 The new API provide access to multiple AP on the same DAP, but the
3123 maximum number of the AP port is limited by the specific firmware version
3124 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3125 An error is returned for any AP number above the maximum allowed value.
3127 @emph{Note:} Either these same adapters and their older versions are
3128 also supported by @ref{hla_interface, the hla interface driver}.
3130 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3131 Choose between 'exclusive' USB communication (the default backend) or
3132 'shared' mode using ST-Link TCP server (the default port is 7184).
3134 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3135 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3136 ST-LINK server software module}.
3138 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3141 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3142 Pairs of vendor IDs and product IDs of the device.
3145 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3146 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3147 and receives @var{rx_n} bytes.
3149 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3150 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3151 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3152 the target's supply voltage.
3154 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3155 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3157 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3159 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3160 > set n [expr @{[lindex $a 4] + 256 * [lindex $a 5]@}]
3161 > set d [expr @{[lindex $a 0] + 256 * [lindex $a 1]@}]
3162 > echo [expr @{2 * 1.2 * $n / $d@}]
3168 @deffn {Interface Driver} {opendous}
3169 opendous-jtag is a freely programmable USB adapter.
3172 @deffn {Interface Driver} {ulink}
3173 This is the Keil ULINK v1 JTAG debugger.
3176 @deffn {Interface Driver} {xds110}
3177 The XDS110 is included as the embedded debug probe on many Texas Instruments
3178 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3179 debug probe with the added capability to supply power to the target board. The
3180 following commands are supported by the XDS110 driver:
3182 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3183 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3184 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3185 can be set to any value in the range 1800 to 3600 millivolts.
3188 @deffn {Command} {xds110 info}
3189 Displays information about the connected XDS110 debug probe (e.g. firmware
3194 @deffn {Interface Driver} {xlnx_pcie_xvc}
3195 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3196 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3197 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3198 exposed via extended capability registers in the PCI Express configuration space.
3200 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3202 @deffn {Config Command} {xlnx_pcie_xvc config} device
3203 Specifies the PCI Express device via parameter @var{device} to use.
3205 The correct value for @var{device} can be obtained by looking at the output
3206 of lscpi -D (first column) for the corresponding device.
3208 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3213 @deffn {Interface Driver} {bcm2835gpio}
3214 This SoC is present in Raspberry Pi which is a cheap single-board computer
3215 exposing some GPIOs on its expansion header.
3217 The driver accesses memory-mapped GPIO peripheral registers directly
3218 for maximum performance, but the only possible race condition is for
3219 the pins' modes/muxing (which is highly unlikely), so it should be
3220 able to coexist nicely with both sysfs bitbanging and various
3221 peripherals' kernel drivers. The driver restores the previous
3222 configuration on exit.
3224 GPIO numbers >= 32 can't be used for performance reasons.
3226 See @file{interface/raspberrypi-native.cfg} for a sample config and
3229 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3230 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3231 Must be specified to enable JTAG transport. These pins can also be specified
3235 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3236 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3237 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3240 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3241 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3242 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3245 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3246 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3247 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3250 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3251 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3252 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3255 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3256 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3257 specified to enable SWD transport. These pins can also be specified individually.
3260 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3261 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3262 specified using the configuration command @command{bcm2835gpio swd_nums}.
3265 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3266 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3267 specified using the configuration command @command{bcm2835gpio swd_nums}.
3270 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3271 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3272 to control the direction of an external buffer on the SWDIO pin (set=output
3273 mode, clear=input mode). If not specified, this feature is disabled.
3276 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3277 Set SRST GPIO number. Must be specified to enable SRST.
3280 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3281 Set TRST GPIO number. Must be specified to enable TRST.
3284 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3285 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3286 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3289 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3290 Set the peripheral base register address to access GPIOs. For the RPi1, use
3291 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3292 list can be found in the
3293 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3298 @deffn {Interface Driver} {imx_gpio}
3299 i.MX SoC is present in many community boards. Wandboard is an example
3300 of the one which is most popular.
3302 This driver is mostly the same as bcm2835gpio.
3304 See @file{interface/imx-native.cfg} for a sample config and
3310 @deffn {Interface Driver} {linuxgpiod}
3311 Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
3312 The driver emulates either JTAG and SWD transport through bitbanging.
3314 See @file{interface/dln-2-gpiod.cfg} for a sample config.
3318 @deffn {Interface Driver} {sysfsgpio}
3319 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3320 Prefer using @b{linuxgpiod}, instead.
3322 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3326 @deffn {Interface Driver} {openjtag}
3327 OpenJTAG compatible USB adapter.
3328 This defines some driver-specific commands:
3330 @deffn {Config Command} {openjtag variant} variant
3331 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3332 Currently valid @var{variant} values include:
3335 @item @b{standard} Standard variant (default).
3336 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3337 (see @uref{http://www.cypress.com/?rID=82870}).
3341 @deffn {Config Command} {openjtag device_desc} string
3342 The USB device description string of the adapter.
3343 This value is only used with the standard variant.
3348 @deffn {Interface Driver} {jtag_dpi}
3349 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3350 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3351 DPI server interface.
3353 @deffn {Config Command} {jtag_dpi set_port} port
3354 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3357 @deffn {Config Command} {jtag_dpi set_address} address
3358 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3363 @deffn {Interface Driver} {buspirate}
3365 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3366 It uses a simple data protocol over a serial port connection.
3368 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3369 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3371 @deffn {Config Command} {buspirate port} serial_port
3372 Specify the serial port's filename. For example:
3374 buspirate port /dev/ttyUSB0
3378 @deffn {Config Command} {buspirate speed} (normal|fast)
3379 Set the communication speed to 115k (normal) or 1M (fast). For example:
3381 buspirate speed normal
3385 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3386 Set the Bus Pirate output mode.
3388 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3389 @item In open drain mode, you will then need to enable the pull-ups.
3393 buspirate mode normal
3397 @deffn {Config Command} {buspirate pullup} (0|1)
3398 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3399 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3406 @deffn {Config Command} {buspirate vreg} (0|1)
3407 Whether to enable (1) or disable (0) the built-in voltage regulator,
3408 which can be used to supply power to a test circuit through
3409 I/O header pins +3V3 and +5V. For example:
3415 @deffn {Command} {buspirate led} (0|1)
3416 Turns the Bus Pirate's LED on (1) or off (0). For example:
3425 @section Transport Configuration
3427 As noted earlier, depending on the version of OpenOCD you use,
3428 and the debug adapter you are using,
3429 several transports may be available to
3430 communicate with debug targets (or perhaps to program flash memory).
3431 @deffn {Command} {transport list}
3432 displays the names of the transports supported by this
3436 @deffn {Command} {transport select} @option{transport_name}
3437 Select which of the supported transports to use in this OpenOCD session.
3439 When invoked with @option{transport_name}, attempts to select the named
3440 transport. The transport must be supported by the debug adapter
3441 hardware and by the version of OpenOCD you are using (including the
3444 If no transport has been selected and no @option{transport_name} is
3445 provided, @command{transport select} auto-selects the first transport
3446 supported by the debug adapter.
3448 @command{transport select} always returns the name of the session's selected
3452 @subsection JTAG Transport
3454 JTAG is the original transport supported by OpenOCD, and most
3455 of the OpenOCD commands support it.
3456 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3457 each of which must be explicitly declared.
3458 JTAG supports both debugging and boundary scan testing.
3459 Flash programming support is built on top of debug support.
3461 JTAG transport is selected with the command @command{transport select
3462 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3463 driver} (in which case the command is @command{transport select hla_jtag})
3464 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3465 the command is @command{transport select dapdirect_jtag}).
3467 @subsection SWD Transport
3469 @cindex Serial Wire Debug
3470 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3471 Debug Access Point (DAP, which must be explicitly declared.
3472 (SWD uses fewer signal wires than JTAG.)
3473 SWD is debug-oriented, and does not support boundary scan testing.
3474 Flash programming support is built on top of debug support.
3475 (Some processors support both JTAG and SWD.)
3477 SWD transport is selected with the command @command{transport select
3478 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3479 driver} (in which case the command is @command{transport select hla_swd})
3480 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3481 the command is @command{transport select dapdirect_swd}).
3483 @deffn {Config Command} {swd newdap} ...
3484 Declares a single DAP which uses SWD transport.
3485 Parameters are currently the same as "jtag newtap" but this is
3489 @cindex SWD multi-drop
3490 The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop extension
3491 of SWD protocol: two or more devices can be connected to one SWD adapter.
3492 SWD transport works in multi-drop mode if @ref{dap_create,DAP} is configured
3493 with both @code{-dp-id} and @code{-instance-id} parameters regardless how many
3496 Not all adapters and adapter drivers support SWD multi-drop. Only the following
3497 adapter drivers are SWD multi-drop capable:
3498 cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
3500 @subsection SPI Transport
3502 @cindex Serial Peripheral Interface
3503 The Serial Peripheral Interface (SPI) is a general purpose transport
3504 which uses four wire signaling. Some processors use it as part of a
3505 solution for flash programming.
3507 @anchor{swimtransport}
3508 @subsection SWIM Transport
3510 @cindex Single Wire Interface Module
3511 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3512 by the STMicroelectronics MCU family STM8 and documented in the
3513 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3515 SWIM does not support boundary scan testing nor multiple cores.
3517 The SWIM transport is selected with the command @command{transport select swim}.
3519 The concept of TAPs does not fit in the protocol since SWIM does not implement
3520 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3521 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3522 The TAP definition must precede the target definition command
3523 @command{target create target_name stm8 -chain-position basename.tap_type}.
3527 JTAG clock setup is part of system setup.
3528 It @emph{does not belong with interface setup} since any interface
3529 only knows a few of the constraints for the JTAG clock speed.
3530 Sometimes the JTAG speed is
3531 changed during the target initialization process: (1) slow at
3532 reset, (2) program the CPU clocks, (3) run fast.
3533 Both the "slow" and "fast" clock rates are functions of the
3534 oscillators used, the chip, the board design, and sometimes
3535 power management software that may be active.
3537 The speed used during reset, and the scan chain verification which
3538 follows reset, can be adjusted using a @code{reset-start}
3539 target event handler.
3540 It can then be reconfigured to a faster speed by a
3541 @code{reset-init} target event handler after it reprograms those
3542 CPU clocks, or manually (if something else, such as a boot loader,
3543 sets up those clocks).
3544 @xref{targetevents,,Target Events}.
3545 When the initial low JTAG speed is a chip characteristic, perhaps
3546 because of a required oscillator speed, provide such a handler
3547 in the target config file.
3548 When that speed is a function of a board-specific characteristic
3549 such as which speed oscillator is used, it belongs in the board
3550 config file instead.
3551 In both cases it's safest to also set the initial JTAG clock rate
3552 to that same slow speed, so that OpenOCD never starts up using a
3553 clock speed that's faster than the scan chain can support.
3557 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3560 If your system supports adaptive clocking (RTCK), configuring
3561 JTAG to use that is probably the most robust approach.
3562 However, it introduces delays to synchronize clocks; so it
3563 may not be the fastest solution.
3565 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3566 instead of @command{adapter speed}, but only for (ARM) cores and boards
3567 which support adaptive clocking.
3569 @deffn {Command} {adapter speed} max_speed_kHz
3570 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3571 JTAG interfaces usually support a limited number of
3572 speeds. The speed actually used won't be faster
3573 than the speed specified.
3575 Chip data sheets generally include a top JTAG clock rate.
3576 The actual rate is often a function of a CPU core clock,
3577 and is normally less than that peak rate.
3578 For example, most ARM cores accept at most one sixth of the CPU clock.
3580 Speed 0 (khz) selects RTCK method.
3581 @xref{faqrtck,,FAQ RTCK}.
3582 If your system uses RTCK, you won't need to change the
3583 JTAG clocking after setup.
3584 Not all interfaces, boards, or targets support ``rtck''.
3585 If the interface device can not
3586 support it, an error is returned when you try to use RTCK.
3589 @defun jtag_rclk fallback_speed_kHz
3590 @cindex adaptive clocking
3592 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3593 If that fails (maybe the interface, board, or target doesn't
3594 support it), falls back to the specified frequency.
3596 # Fall back to 3mhz if RTCK is not supported
3601 @node Reset Configuration
3602 @chapter Reset Configuration
3603 @cindex Reset Configuration
3605 Every system configuration may require a different reset
3606 configuration. This can also be quite confusing.
3607 Resets also interact with @var{reset-init} event handlers,
3608 which do things like setting up clocks and DRAM, and
3609 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3610 They can also interact with JTAG routers.
3611 Please see the various board files for examples.
3614 To maintainers and integrators:
3615 Reset configuration touches several things at once.
3616 Normally the board configuration file
3617 should define it and assume that the JTAG adapter supports
3618 everything that's wired up to the board's JTAG connector.
3620 However, the target configuration file could also make note
3621 of something the silicon vendor has done inside the chip,
3622 which will be true for most (or all) boards using that chip.
3623 And when the JTAG adapter doesn't support everything, the
3624 user configuration file will need to override parts of
3625 the reset configuration provided by other files.
3628 @section Types of Reset
3630 There are many kinds of reset possible through JTAG, but
3631 they may not all work with a given board and adapter.
3632 That's part of why reset configuration can be error prone.
3636 @emph{System Reset} ... the @emph{SRST} hardware signal
3637 resets all chips connected to the JTAG adapter, such as processors,
3638 power management chips, and I/O controllers. Normally resets triggered
3639 with this signal behave exactly like pressing a RESET button.
3641 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3642 just the TAP controllers connected to the JTAG adapter.
3643 Such resets should not be visible to the rest of the system; resetting a
3644 device's TAP controller just puts that controller into a known state.
3646 @emph{Emulation Reset} ... many devices can be reset through JTAG
3647 commands. These resets are often distinguishable from system
3648 resets, either explicitly (a "reset reason" register says so)
3649 or implicitly (not all parts of the chip get reset).
3651 @emph{Other Resets} ... system-on-chip devices often support
3652 several other types of reset.
3653 You may need to arrange that a watchdog timer stops
3654 while debugging, preventing a watchdog reset.
3655 There may be individual module resets.
3658 In the best case, OpenOCD can hold SRST, then reset
3659 the TAPs via TRST and send commands through JTAG to halt the
3660 CPU at the reset vector before the 1st instruction is executed.
3661 Then when it finally releases the SRST signal, the system is
3662 halted under debugger control before any code has executed.
3663 This is the behavior required to support the @command{reset halt}
3664 and @command{reset init} commands; after @command{reset init} a
3665 board-specific script might do things like setting up DRAM.
3666 (@xref{resetcommand,,Reset Command}.)
3668 @anchor{srstandtrstissues}
3669 @section SRST and TRST Issues
3671 Because SRST and TRST are hardware signals, they can have a
3672 variety of system-specific constraints. Some of the most
3677 @item @emph{Signal not available} ... Some boards don't wire
3678 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3679 support such signals even if they are wired up.
3680 Use the @command{reset_config} @var{signals} options to say
3681 when either of those signals is not connected.
3682 When SRST is not available, your code might not be able to rely
3683 on controllers having been fully reset during code startup.
3684 Missing TRST is not a problem, since JTAG-level resets can
3685 be triggered using with TMS signaling.
3687 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3688 adapter will connect SRST to TRST, instead of keeping them separate.
3689 Use the @command{reset_config} @var{combination} options to say
3690 when those signals aren't properly independent.
3692 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3693 delay circuit, reset supervisor, or on-chip features can extend
3694 the effect of a JTAG adapter's reset for some time after the adapter
3695 stops issuing the reset. For example, there may be chip or board
3696 requirements that all reset pulses last for at least a
3697 certain amount of time; and reset buttons commonly have
3698 hardware debouncing.
3699 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3700 commands to say when extra delays are needed.
3702 @item @emph{Drive type} ... Reset lines often have a pullup
3703 resistor, letting the JTAG interface treat them as open-drain
3704 signals. But that's not a requirement, so the adapter may need
3705 to use push/pull output drivers.
3706 Also, with weak pullups it may be advisable to drive
3707 signals to both levels (push/pull) to minimize rise times.
3708 Use the @command{reset_config} @var{trst_type} and
3709 @var{srst_type} parameters to say how to drive reset signals.
3711 @item @emph{Special initialization} ... Targets sometimes need
3712 special JTAG initialization sequences to handle chip-specific
3713 issues (not limited to errata).
3714 For example, certain JTAG commands might need to be issued while
3715 the system as a whole is in a reset state (SRST active)
3716 but the JTAG scan chain is usable (TRST inactive).
3717 Many systems treat combined assertion of SRST and TRST as a
3718 trigger for a harder reset than SRST alone.
3719 Such custom reset handling is discussed later in this chapter.
3722 There can also be other issues.
3723 Some devices don't fully conform to the JTAG specifications.
3724 Trivial system-specific differences are common, such as
3725 SRST and TRST using slightly different names.
3726 There are also vendors who distribute key JTAG documentation for
3727 their chips only to developers who have signed a Non-Disclosure
3730 Sometimes there are chip-specific extensions like a requirement to use
3731 the normally-optional TRST signal (precluding use of JTAG adapters which
3732 don't pass TRST through), or needing extra steps to complete a TAP reset.
3734 In short, SRST and especially TRST handling may be very finicky,
3735 needing to cope with both architecture and board specific constraints.
3737 @section Commands for Handling Resets
3739 @deffn {Command} {adapter srst pulse_width} milliseconds
3740 Minimum amount of time (in milliseconds) OpenOCD should wait
3741 after asserting nSRST (active-low system reset) before
3742 allowing it to be deasserted.
3745 @deffn {Command} {adapter srst delay} milliseconds
3746 How long (in milliseconds) OpenOCD should wait after deasserting
3747 nSRST (active-low system reset) before starting new JTAG operations.
3748 When a board has a reset button connected to SRST line it will
3749 probably have hardware debouncing, implying you should use this.
3752 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
3753 Minimum amount of time (in milliseconds) OpenOCD should wait
3754 after asserting nTRST (active-low JTAG TAP reset) before
3755 allowing it to be deasserted.
3758 @deffn {Command} {jtag_ntrst_delay} milliseconds
3759 How long (in milliseconds) OpenOCD should wait after deasserting
3760 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3763 @anchor{reset_config}
3764 @deffn {Command} {reset_config} mode_flag ...
3765 This command displays or modifies the reset configuration
3766 of your combination of JTAG board and target in target
3767 configuration scripts.
3769 Information earlier in this section describes the kind of problems
3770 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3771 As a rule this command belongs only in board config files,
3772 describing issues like @emph{board doesn't connect TRST};
3773 or in user config files, addressing limitations derived
3774 from a particular combination of interface and board.
3775 (An unlikely example would be using a TRST-only adapter
3776 with a board that only wires up SRST.)
3778 The @var{mode_flag} options can be specified in any order, but only one
3779 of each type -- @var{signals}, @var{combination}, @var{gates},
3780 @var{trst_type}, @var{srst_type} and @var{connect_type}
3781 -- may be specified at a time.
3782 If you don't provide a new value for a given type, its previous
3783 value (perhaps the default) is unchanged.
3784 For example, this means that you don't need to say anything at all about
3785 TRST just to declare that if the JTAG adapter should want to drive SRST,
3786 it must explicitly be driven high (@option{srst_push_pull}).
3790 @var{signals} can specify which of the reset signals are connected.
3791 For example, If the JTAG interface provides SRST, but the board doesn't
3792 connect that signal properly, then OpenOCD can't use it.
3793 Possible values are @option{none} (the default), @option{trst_only},
3794 @option{srst_only} and @option{trst_and_srst}.
3797 If your board provides SRST and/or TRST through the JTAG connector,
3798 you must declare that so those signals can be used.
3802 The @var{combination} is an optional value specifying broken reset
3803 signal implementations.
3804 The default behaviour if no option given is @option{separate},
3805 indicating everything behaves normally.
3806 @option{srst_pulls_trst} states that the
3807 test logic is reset together with the reset of the system (e.g. NXP
3808 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3809 the system is reset together with the test logic (only hypothetical, I
3810 haven't seen hardware with such a bug, and can be worked around).
3811 @option{combined} implies both @option{srst_pulls_trst} and
3812 @option{trst_pulls_srst}.
3815 The @var{gates} tokens control flags that describe some cases where
3816 JTAG may be unavailable during reset.
3817 @option{srst_gates_jtag} (default)
3818 indicates that asserting SRST gates the
3819 JTAG clock. This means that no communication can happen on JTAG
3820 while SRST is asserted.
3821 Its converse is @option{srst_nogate}, indicating that JTAG commands
3822 can safely be issued while SRST is active.
3825 The @var{connect_type} tokens control flags that describe some cases where
3826 SRST is asserted while connecting to the target. @option{srst_nogate}
3827 is required to use this option.
3828 @option{connect_deassert_srst} (default)
3829 indicates that SRST will not be asserted while connecting to the target.
3830 Its converse is @option{connect_assert_srst}, indicating that SRST will
3831 be asserted before any target connection.
3832 Only some targets support this feature, STM32 and STR9 are examples.
3833 This feature is useful if you are unable to connect to your target due
3834 to incorrect options byte config or illegal program execution.
3837 The optional @var{trst_type} and @var{srst_type} parameters allow the
3838 driver mode of each reset line to be specified. These values only affect
3839 JTAG interfaces with support for different driver modes, like the Amontec
3840 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3841 relevant signal (TRST or SRST) is not connected.
3845 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3846 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3847 Most boards connect this signal to a pulldown, so the JTAG TAPs
3848 never leave reset unless they are hooked up to a JTAG adapter.
3851 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3852 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3853 Most boards connect this signal to a pullup, and allow the
3854 signal to be pulled low by various events including system
3855 power-up and pressing a reset button.
3859 @section Custom Reset Handling
3862 OpenOCD has several ways to help support the various reset
3863 mechanisms provided by chip and board vendors.
3864 The commands shown in the previous section give standard parameters.
3865 There are also @emph{event handlers} associated with TAPs or Targets.
3866 Those handlers are Tcl procedures you can provide, which are invoked
3867 at particular points in the reset sequence.
3869 @emph{When SRST is not an option} you must set
3870 up a @code{reset-assert} event handler for your target.
3871 For example, some JTAG adapters don't include the SRST signal;
3872 and some boards have multiple targets, and you won't always
3873 want to reset everything at once.
3875 After configuring those mechanisms, you might still
3876 find your board doesn't start up or reset correctly.
3877 For example, maybe it needs a slightly different sequence
3878 of SRST and/or TRST manipulations, because of quirks that
3879 the @command{reset_config} mechanism doesn't address;
3880 or asserting both might trigger a stronger reset, which
3881 needs special attention.
3883 Experiment with lower level operations, such as
3884 @command{adapter assert}, @command{adapter deassert}
3885 and the @command{jtag arp_*} operations shown here,
3886 to find a sequence of operations that works.
3887 @xref{JTAG Commands}.
3888 When you find a working sequence, it can be used to override
3889 @command{jtag_init}, which fires during OpenOCD startup
3890 (@pxref{configurationstage,,Configuration Stage});
3891 or @command{init_reset}, which fires during reset processing.
3893 You might also want to provide some project-specific reset
3894 schemes. For example, on a multi-target board the standard
3895 @command{reset} command would reset all targets, but you
3896 may need the ability to reset only one target at time and
3897 thus want to avoid using the board-wide SRST signal.
3899 @deffn {Overridable Procedure} {init_reset} mode
3900 This is invoked near the beginning of the @command{reset} command,
3901 usually to provide as much of a cold (power-up) reset as practical.
3902 By default it is also invoked from @command{jtag_init} if
3903 the scan chain does not respond to pure JTAG operations.
3904 The @var{mode} parameter is the parameter given to the
3905 low level reset command (@option{halt},
3906 @option{init}, or @option{run}), @option{setup},
3907 or potentially some other value.
3909 The default implementation just invokes @command{jtag arp_init-reset}.
3910 Replacements will normally build on low level JTAG
3911 operations such as @command{adapter assert} and @command{adapter deassert}.
3912 Operations here must not address individual TAPs
3913 (or their associated targets)
3914 until the JTAG scan chain has first been verified to work.
3916 Implementations must have verified the JTAG scan chain before
3918 This is done by calling @command{jtag arp_init}
3919 (or @command{jtag arp_init-reset}).
3922 @deffn {Command} {jtag arp_init}
3923 This validates the scan chain using just the four
3924 standard JTAG signals (TMS, TCK, TDI, TDO).
3925 It starts by issuing a JTAG-only reset.
3926 Then it performs checks to verify that the scan chain configuration
3927 matches the TAPs it can observe.
3928 Those checks include checking IDCODE values for each active TAP,
3929 and verifying the length of their instruction registers using
3930 TAP @code{-ircapture} and @code{-irmask} values.
3931 If these tests all pass, TAP @code{setup} events are
3932 issued to all TAPs with handlers for that event.
3935 @deffn {Command} {jtag arp_init-reset}
3936 This uses TRST and SRST to try resetting
3937 everything on the JTAG scan chain
3938 (and anything else connected to SRST).
3939 It then invokes the logic of @command{jtag arp_init}.
3943 @node TAP Declaration
3944 @chapter TAP Declaration
3945 @cindex TAP declaration
3946 @cindex TAP configuration
3948 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3949 TAPs serve many roles, including:
3952 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3953 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3954 Others do it indirectly, making a CPU do it.
3955 @item @b{Program Download} Using the same CPU support GDB uses,
3956 you can initialize a DRAM controller, download code to DRAM, and then
3957 start running that code.
3958 @item @b{Boundary Scan} Most chips support boundary scan, which
3959 helps test for board assembly problems like solder bridges
3960 and missing connections.
3963 OpenOCD must know about the active TAPs on your board(s).
3964 Setting up the TAPs is the core task of your configuration files.
3965 Once those TAPs are set up, you can pass their names to code
3966 which sets up CPUs and exports them as GDB targets,
3967 probes flash memory, performs low-level JTAG operations, and more.
3969 @section Scan Chains
3972 TAPs are part of a hardware @dfn{scan chain},
3973 which is a daisy chain of TAPs.
3974 They also need to be added to
3975 OpenOCD's software mirror of that hardware list,
3976 giving each member a name and associating other data with it.
3977 Simple scan chains, with a single TAP, are common in
3978 systems with a single microcontroller or microprocessor.
3979 More complex chips may have several TAPs internally.
3980 Very complex scan chains might have a dozen or more TAPs:
3981 several in one chip, more in the next, and connecting
3982 to other boards with their own chips and TAPs.
3984 You can display the list with the @command{scan_chain} command.
3985 (Don't confuse this with the list displayed by the @command{targets}
3986 command, presented in the next chapter.
3987 That only displays TAPs for CPUs which are configured as
3989 Here's what the scan chain might look like for a chip more than one TAP:
3992 TapName Enabled IdCode Expected IrLen IrCap IrMask
3993 -- ------------------ ------- ---------- ---------- ----- ----- ------
3994 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3995 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3996 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3999 OpenOCD can detect some of that information, but not all
4000 of it. @xref{autoprobing,,Autoprobing}.
4001 Unfortunately, those TAPs can't always be autoconfigured,
4002 because not all devices provide good support for that.
4003 JTAG doesn't require supporting IDCODE instructions, and
4004 chips with JTAG routers may not link TAPs into the chain
4005 until they are told to do so.
4007 The configuration mechanism currently supported by OpenOCD
4008 requires explicit configuration of all TAP devices using
4009 @command{jtag newtap} commands, as detailed later in this chapter.
4010 A command like this would declare one tap and name it @code{chip1.cpu}:
4013 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
4016 Each target configuration file lists the TAPs provided
4018 Board configuration files combine all the targets on a board,
4020 Note that @emph{the order in which TAPs are declared is very important.}
4021 That declaration order must match the order in the JTAG scan chain,
4022 both inside a single chip and between them.
4023 @xref{faqtaporder,,FAQ TAP Order}.
4025 For example, the STMicroelectronics STR912 chip has
4026 three separate TAPs@footnote{See the ST
4027 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
4028 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
4029 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
4030 To configure those taps, @file{target/str912.cfg}
4031 includes commands something like this:
4034 jtag newtap str912 flash ... params ...
4035 jtag newtap str912 cpu ... params ...
4036 jtag newtap str912 bs ... params ...
4039 Actual config files typically use a variable such as @code{$_CHIPNAME}
4040 instead of literals like @option{str912}, to support more than one chip
4041 of each type. @xref{Config File Guidelines}.
4043 @deffn {Command} {jtag names}
4044 Returns the names of all current TAPs in the scan chain.
4045 Use @command{jtag cget} or @command{jtag tapisenabled}
4046 to examine attributes and state of each TAP.
4048 foreach t [jtag names] @{
4049 puts [format "TAP: %s\n" $t]
4054 @deffn {Command} {scan_chain}
4055 Displays the TAPs in the scan chain configuration,
4057 The set of TAPs listed by this command is fixed by
4058 exiting the OpenOCD configuration stage,
4059 but systems with a JTAG router can
4060 enable or disable TAPs dynamically.
4063 @c FIXME! "jtag cget" should be able to return all TAP
4064 @c attributes, like "$target_name cget" does for targets.
4066 @c Probably want "jtag eventlist", and a "tap-reset" event
4067 @c (on entry to RESET state).
4072 When TAP objects are declared with @command{jtag newtap},
4073 a @dfn{dotted.name} is created for the TAP, combining the
4074 name of a module (usually a chip) and a label for the TAP.
4075 For example: @code{xilinx.tap}, @code{str912.flash},
4076 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4077 Many other commands use that dotted.name to manipulate or
4078 refer to the TAP. For example, CPU configuration uses the
4079 name, as does declaration of NAND or NOR flash banks.
4081 The components of a dotted name should follow ``C'' symbol
4082 name rules: start with an alphabetic character, then numbers
4083 and underscores are OK; while others (including dots!) are not.
4085 @section TAP Declaration Commands
4087 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4088 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4089 and configured according to the various @var{configparams}.
4091 The @var{chipname} is a symbolic name for the chip.
4092 Conventionally target config files use @code{$_CHIPNAME},
4093 defaulting to the model name given by the chip vendor but
4096 @cindex TAP naming convention
4097 The @var{tapname} reflects the role of that TAP,
4098 and should follow this convention:
4101 @item @code{bs} -- For boundary scan if this is a separate TAP;
4102 @item @code{cpu} -- The main CPU of the chip, alternatively
4103 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4104 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4105 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4106 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4107 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4108 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4109 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4111 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4112 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4113 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4114 a JTAG TAP; that TAP should be named @code{sdma}.
4117 Every TAP requires at least the following @var{configparams}:
4120 @item @code{-irlen} @var{NUMBER}
4121 @*The length in bits of the
4122 instruction register, such as 4 or 5 bits.
4125 A TAP may also provide optional @var{configparams}:
4128 @item @code{-disable} (or @code{-enable})
4129 @*Use the @code{-disable} parameter to flag a TAP which is not
4130 linked into the scan chain after a reset using either TRST
4131 or the JTAG state machine's @sc{reset} state.
4132 You may use @code{-enable} to highlight the default state
4133 (the TAP is linked in).
4134 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4135 @item @code{-expected-id} @var{NUMBER}
4136 @*A non-zero @var{number} represents a 32-bit IDCODE
4137 which you expect to find when the scan chain is examined.
4138 These codes are not required by all JTAG devices.
4139 @emph{Repeat the option} as many times as required if more than one
4140 ID code could appear (for example, multiple versions).
4141 Specify @var{number} as zero to suppress warnings about IDCODE
4142 values that were found but not included in the list.
4144 Provide this value if at all possible, since it lets OpenOCD
4145 tell when the scan chain it sees isn't right. These values
4146 are provided in vendors' chip documentation, usually a technical
4147 reference manual. Sometimes you may need to probe the JTAG
4148 hardware to find these values.
4149 @xref{autoprobing,,Autoprobing}.
4150 @item @code{-ignore-version}
4151 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4152 option. When vendors put out multiple versions of a chip, or use the same
4153 JTAG-level ID for several largely-compatible chips, it may be more practical
4154 to ignore the version field than to update config files to handle all of
4155 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4156 @item @code{-ircapture} @var{NUMBER}
4157 @*The bit pattern loaded by the TAP into the JTAG shift register
4158 on entry to the @sc{ircapture} state, such as 0x01.
4159 JTAG requires the two LSBs of this value to be 01.
4160 By default, @code{-ircapture} and @code{-irmask} are set
4161 up to verify that two-bit value. You may provide
4162 additional bits if you know them, or indicate that
4163 a TAP doesn't conform to the JTAG specification.
4164 @item @code{-irmask} @var{NUMBER}
4165 @*A mask used with @code{-ircapture}
4166 to verify that instruction scans work correctly.
4167 Such scans are not used by OpenOCD except to verify that
4168 there seems to be no problems with JTAG scan chain operations.
4169 @item @code{-ignore-syspwrupack}
4170 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4171 register during initial examination and when checking the sticky error bit.
4172 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4173 devices do not set the ack bit until sometime later.
4177 @section Other TAP commands
4179 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4180 Get the value of the IDCODE found in hardware.
4183 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4184 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4185 At this writing this TAP attribute
4186 mechanism is limited and used mostly for event handling.
4187 (It is not a direct analogue of the @code{cget}/@code{configure}
4188 mechanism for debugger targets.)
4189 See the next section for information about the available events.
4191 The @code{configure} subcommand assigns an event handler,
4192 a TCL string which is evaluated when the event is triggered.
4193 The @code{cget} subcommand returns that handler.
4200 OpenOCD includes two event mechanisms.
4201 The one presented here applies to all JTAG TAPs.
4202 The other applies to debugger targets,
4203 which are associated with certain TAPs.
4205 The TAP events currently defined are:
4208 @item @b{post-reset}
4209 @* The TAP has just completed a JTAG reset.
4210 The tap may still be in the JTAG @sc{reset} state.
4211 Handlers for these events might perform initialization sequences
4212 such as issuing TCK cycles, TMS sequences to ensure
4213 exit from the ARM SWD mode, and more.
4215 Because the scan chain has not yet been verified, handlers for these events
4216 @emph{should not issue commands which scan the JTAG IR or DR registers}
4217 of any particular target.
4218 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4220 @* The scan chain has been reset and verified.
4221 This handler may enable TAPs as needed.
4222 @item @b{tap-disable}
4223 @* The TAP needs to be disabled. This handler should
4224 implement @command{jtag tapdisable}
4225 by issuing the relevant JTAG commands.
4226 @item @b{tap-enable}
4227 @* The TAP needs to be enabled. This handler should
4228 implement @command{jtag tapenable}
4229 by issuing the relevant JTAG commands.
4232 If you need some action after each JTAG reset which isn't actually
4233 specific to any TAP (since you can't yet trust the scan chain's
4234 contents to be accurate), you might:
4237 jtag configure CHIP.jrc -event post-reset @{
4238 echo "JTAG Reset done"
4239 ... non-scan jtag operations to be done after reset
4244 @anchor{enablinganddisablingtaps}
4245 @section Enabling and Disabling TAPs
4246 @cindex JTAG Route Controller
4249 In some systems, a @dfn{JTAG Route Controller} (JRC)
4250 is used to enable and/or disable specific JTAG TAPs.
4251 Many ARM-based chips from Texas Instruments include
4252 an ``ICEPick'' module, which is a JRC.
4253 Such chips include DaVinci and OMAP3 processors.
4255 A given TAP may not be visible until the JRC has been
4256 told to link it into the scan chain; and if the JRC
4257 has been told to unlink that TAP, it will no longer
4259 Such routers address problems that JTAG ``bypass mode''
4263 @item The scan chain can only go as fast as its slowest TAP.
4264 @item Having many TAPs slows instruction scans, since all
4265 TAPs receive new instructions.
4266 @item TAPs in the scan chain must be powered up, which wastes
4267 power and prevents debugging some power management mechanisms.
4270 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4271 as implied by the existence of JTAG routers.
4272 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4273 does include a kind of JTAG router functionality.
4275 @c (a) currently the event handlers don't seem to be able to
4276 @c fail in a way that could lead to no-change-of-state.
4278 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4279 shown below, and is implemented using TAP event handlers.
4280 So for example, when defining a TAP for a CPU connected to
4281 a JTAG router, your @file{target.cfg} file
4282 should define TAP event handlers using
4283 code that looks something like this:
4286 jtag configure CHIP.cpu -event tap-enable @{
4287 ... jtag operations using CHIP.jrc
4289 jtag configure CHIP.cpu -event tap-disable @{
4290 ... jtag operations using CHIP.jrc
4294 Then you might want that CPU's TAP enabled almost all the time:
4297 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4300 Note how that particular setup event handler declaration
4301 uses quotes to evaluate @code{$CHIP} when the event is configured.
4302 Using brackets @{ @} would cause it to be evaluated later,
4303 at runtime, when it might have a different value.
4305 @deffn {Command} {jtag tapdisable} dotted.name
4306 If necessary, disables the tap
4307 by sending it a @option{tap-disable} event.
4308 Returns the string "1" if the tap
4309 specified by @var{dotted.name} is enabled,
4310 and "0" if it is disabled.
4313 @deffn {Command} {jtag tapenable} dotted.name
4314 If necessary, enables the tap
4315 by sending it a @option{tap-enable} event.
4316 Returns the string "1" if the tap
4317 specified by @var{dotted.name} is enabled,
4318 and "0" if it is disabled.
4321 @deffn {Command} {jtag tapisenabled} dotted.name
4322 Returns the string "1" if the tap
4323 specified by @var{dotted.name} is enabled,
4324 and "0" if it is disabled.
4327 Humans will find the @command{scan_chain} command more helpful
4328 for querying the state of the JTAG taps.
4332 @anchor{autoprobing}
4333 @section Autoprobing
4335 @cindex JTAG autoprobe
4337 TAP configuration is the first thing that needs to be done
4338 after interface and reset configuration. Sometimes it's
4339 hard finding out what TAPs exist, or how they are identified.
4340 Vendor documentation is not always easy to find and use.
4342 To help you get past such problems, OpenOCD has a limited
4343 @emph{autoprobing} ability to look at the scan chain, doing
4344 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4345 To use this mechanism, start the OpenOCD server with only data
4346 that configures your JTAG interface, and arranges to come up
4347 with a slow clock (many devices don't support fast JTAG clocks
4348 right when they come out of reset).
4350 For example, your @file{openocd.cfg} file might have:
4353 source [find interface/olimex-arm-usb-tiny-h.cfg]
4354 reset_config trst_and_srst
4358 When you start the server without any TAPs configured, it will
4359 attempt to autoconfigure the TAPs. There are two parts to this:
4362 @item @emph{TAP discovery} ...
4363 After a JTAG reset (sometimes a system reset may be needed too),
4364 each TAP's data registers will hold the contents of either the
4365 IDCODE or BYPASS register.
4366 If JTAG communication is working, OpenOCD will see each TAP,
4367 and report what @option{-expected-id} to use with it.
4368 @item @emph{IR Length discovery} ...
4369 Unfortunately JTAG does not provide a reliable way to find out
4370 the value of the @option{-irlen} parameter to use with a TAP
4372 If OpenOCD can discover the length of a TAP's instruction
4373 register, it will report it.
4374 Otherwise you may need to consult vendor documentation, such
4375 as chip data sheets or BSDL files.
4378 In many cases your board will have a simple scan chain with just
4379 a single device. Here's what OpenOCD reported with one board
4380 that's a bit more complex:
4384 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4385 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4386 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4387 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4388 AUTO auto0.tap - use "... -irlen 4"
4389 AUTO auto1.tap - use "... -irlen 4"
4390 AUTO auto2.tap - use "... -irlen 6"
4391 no gdb ports allocated as no target has been specified
4394 Given that information, you should be able to either find some existing
4395 config files to use, or create your own. If you create your own, you
4396 would configure from the bottom up: first a @file{target.cfg} file
4397 with these TAPs, any targets associated with them, and any on-chip
4398 resources; then a @file{board.cfg} with off-chip resources, clocking,
4401 @anchor{dapdeclaration}
4402 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4403 @cindex DAP declaration
4405 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4406 no longer implicitly created together with the target. It must be
4407 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4408 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4409 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4411 The @command{dap} command group supports the following sub-commands:
4414 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4415 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4416 @var{dotted.name}. This also creates a new command (@command{dap_name})
4417 which is used for various purposes including additional configuration.
4418 There can only be one DAP for each JTAG tap in the system.
4420 A DAP may also provide optional @var{configparams}:
4423 @item @code{-ignore-syspwrupack}
4424 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4425 register during initial examination and when checking the sticky error bit.
4426 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4427 devices do not set the ack bit until sometime later.
4429 @item @code{-dp-id} @var{number}
4430 @*Debug port identification number for SWD DPv2 multidrop.
4431 The @var{number} is written to bits 0..27 of DP TARGETSEL during DP selection.
4432 To find the id number of a single connected device read DP TARGETID:
4433 @code{device.dap dpreg 0x24}
4434 Use bits 0..27 of TARGETID.
4436 @item @code{-instance-id} @var{number}
4437 @*Instance identification number for SWD DPv2 multidrop.
4438 The @var{number} is written to bits 28..31 of DP TARGETSEL during DP selection.
4439 To find the instance number of a single connected device read DP DLPIDR:
4440 @code{device.dap dpreg 0x34}
4441 The instance number is in bits 28..31 of DLPIDR value.
4445 @deffn {Command} {dap names}
4446 This command returns a list of all registered DAP objects. It it useful mainly
4450 @deffn {Command} {dap info} [num]
4451 Displays the ROM table for MEM-AP @var{num},
4452 defaulting to the currently selected AP of the currently selected target.
4455 @deffn {Command} {dap init}
4456 Initialize all registered DAPs. This command is used internally
4457 during initialization. It can be issued at any time after the
4458 initialization, too.
4461 The following commands exist as subcommands of DAP instances:
4463 @deffn {Command} {$dap_name info} [num]
4464 Displays the ROM table for MEM-AP @var{num},
4465 defaulting to the currently selected AP.
4468 @deffn {Command} {$dap_name apid} [num]
4469 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4472 @anchor{DAP subcommand apreg}
4473 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4474 Displays content of a register @var{reg} from AP @var{ap_num}
4475 or set a new value @var{value}.
4476 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4479 @deffn {Command} {$dap_name apsel} [num]
4480 Select AP @var{num}, defaulting to 0.
4483 @deffn {Command} {$dap_name dpreg} reg [value]
4484 Displays the content of DP register at address @var{reg}, or set it to a new
4487 In case of SWD, @var{reg} is a value in packed format
4488 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4489 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4491 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4492 background activity by OpenOCD while you are operating at such low-level.
4495 @deffn {Command} {$dap_name baseaddr} [num]
4496 Displays debug base address from MEM-AP @var{num},
4497 defaulting to the currently selected AP.
4500 @deffn {Command} {$dap_name memaccess} [value]
4501 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4502 memory bus access [0-255], giving additional time to respond to reads.
4503 If @var{value} is defined, first assigns that.
4506 @deffn {Command} {$dap_name apcsw} [value [mask]]
4507 Displays or changes CSW bit pattern for MEM-AP transfers.
4509 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4510 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4511 and the result is written to the real CSW register. All bits except dynamically
4512 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4513 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4516 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4517 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4520 kx.dap apcsw 0x2000000
4523 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4524 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4525 and leaves the rest of the pattern intact. It configures memory access through
4526 DCache on Cortex-M7.
4528 set CSW_HPROT3_CACHEABLE [expr @{1 << 27@}]
4529 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4532 Another example clears SPROT bit and leaves the rest of pattern intact:
4534 set CSW_SPROT [expr @{1 << 30@}]
4535 samv.dap apcsw 0 $CSW_SPROT
4538 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4539 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4541 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4542 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4543 example with a proper dap name:
4545 xxx.dap apcsw default
4549 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4550 Set/get quirks mode for TI TMS450/TMS570 processors
4555 @node CPU Configuration
4556 @chapter CPU Configuration
4559 This chapter discusses how to set up GDB debug targets for CPUs.
4560 You can also access these targets without GDB
4561 (@pxref{Architecture and Core Commands},
4562 and @ref{targetstatehandling,,Target State handling}) and
4563 through various kinds of NAND and NOR flash commands.
4564 If you have multiple CPUs you can have multiple such targets.
4566 We'll start by looking at how to examine the targets you have,
4567 then look at how to add one more target and how to configure it.
4569 @section Target List
4570 @cindex target, current
4571 @cindex target, list
4573 All targets that have been set up are part of a list,
4574 where each member has a name.
4575 That name should normally be the same as the TAP name.
4576 You can display the list with the @command{targets}
4578 This display often has only one CPU; here's what it might
4579 look like with more than one:
4581 TargetName Type Endian TapName State
4582 -- ------------------ ---------- ------ ------------------ ------------
4583 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4584 1 MyTarget cortex_m little mychip.foo tap-disabled
4587 One member of that list is the @dfn{current target}, which
4588 is implicitly referenced by many commands.
4589 It's the one marked with a @code{*} near the target name.
4590 In particular, memory addresses often refer to the address
4591 space seen by that current target.
4592 Commands like @command{mdw} (memory display words)
4593 and @command{flash erase_address} (erase NOR flash blocks)
4594 are examples; and there are many more.
4596 Several commands let you examine the list of targets:
4598 @deffn {Command} {target current}
4599 Returns the name of the current target.
4602 @deffn {Command} {target names}
4603 Lists the names of all current targets in the list.
4605 foreach t [target names] @{
4606 puts [format "Target: %s\n" $t]
4611 @c yep, "target list" would have been better.
4612 @c plus maybe "target setdefault".
4614 @deffn {Command} {targets} [name]
4615 @emph{Note: the name of this command is plural. Other target
4616 command names are singular.}
4618 With no parameter, this command displays a table of all known
4619 targets in a user friendly form.
4621 With a parameter, this command sets the current target to
4622 the given target with the given @var{name}; this is
4623 only relevant on boards which have more than one target.
4626 @section Target CPU Types
4630 Each target has a @dfn{CPU type}, as shown in the output of
4631 the @command{targets} command. You need to specify that type
4632 when calling @command{target create}.
4633 The CPU type indicates more than just the instruction set.
4634 It also indicates how that instruction set is implemented,
4635 what kind of debug support it integrates,
4636 whether it has an MMU (and if so, what kind),
4637 what core-specific commands may be available
4638 (@pxref{Architecture and Core Commands}),
4641 It's easy to see what target types are supported,
4642 since there's a command to list them.
4644 @anchor{targettypes}
4645 @deffn {Command} {target types}
4646 Lists all supported target types.
4647 At this writing, the supported CPU types are:
4650 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4651 @item @code{arm11} -- this is a generation of ARMv6 cores.
4652 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4653 @item @code{arm7tdmi} -- this is an ARMv4 core.
4654 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4655 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4656 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4657 @item @code{arm966e} -- this is an ARMv5 core.
4658 @item @code{arm9tdmi} -- this is an ARMv4 core.
4659 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4660 (Support for this is preliminary and incomplete.)
4661 @item @code{avr32_ap7k} -- this an AVR32 core.
4662 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4663 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4664 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4665 @item @code{cortex_r4} -- this is an ARMv7-R core.
4666 @item @code{dragonite} -- resembles arm966e.
4667 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4668 (Support for this is still incomplete.)
4669 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4670 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4671 The current implementation supports eSi-32xx cores.
4672 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4673 @item @code{feroceon} -- resembles arm926.
4674 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4675 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4676 allowing access to physical memory addresses independently of CPU cores.
4677 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4678 a CPU, through which bus read and write cycles can be generated; it may be
4679 useful for working with non-CPU hardware behind an AP or during development of
4680 support for new CPUs.
4681 It's possible to connect a GDB client to this target (the GDB port has to be
4682 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4683 be emulated to comply to GDB remote protocol.
4684 @item @code{mips_m4k} -- a MIPS core.
4685 @item @code{mips_mips64} -- a MIPS64 core.
4686 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core.
4687 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core.
4688 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core.
4689 @item @code{or1k} -- this is an OpenRISC 1000 core.
4690 The current implementation supports three JTAG TAP cores:
4692 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4693 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4694 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4696 And two debug interfaces cores:
4698 @item @code{Advanced debug interface}
4699 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4700 @item @code{SoC Debug Interface}
4701 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4703 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4704 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4705 @item @code{riscv} -- a RISC-V core.
4706 @item @code{stm8} -- implements an STM8 core.
4707 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4708 @item @code{xscale} -- this is actually an architecture,
4709 not a CPU type. It is based on the ARMv5 architecture.
4713 To avoid being confused by the variety of ARM based cores, remember
4714 this key point: @emph{ARM is a technology licencing company}.
4715 (See: @url{http://www.arm.com}.)
4716 The CPU name used by OpenOCD will reflect the CPU design that was
4717 licensed, not a vendor brand which incorporates that design.
4718 Name prefixes like arm7, arm9, arm11, and cortex
4719 reflect design generations;
4720 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4721 reflect an architecture version implemented by a CPU design.
4723 @anchor{targetconfiguration}
4724 @section Target Configuration
4726 Before creating a ``target'', you must have added its TAP to the scan chain.
4727 When you've added that TAP, you will have a @code{dotted.name}
4728 which is used to set up the CPU support.
4729 The chip-specific configuration file will normally configure its CPU(s)
4730 right after it adds all of the chip's TAPs to the scan chain.
4732 Although you can set up a target in one step, it's often clearer if you
4733 use shorter commands and do it in two steps: create it, then configure
4735 All operations on the target after it's created will use a new
4736 command, created as part of target creation.
4738 The two main things to configure after target creation are
4739 a work area, which usually has target-specific defaults even
4740 if the board setup code overrides them later;
4741 and event handlers (@pxref{targetevents,,Target Events}), which tend
4742 to be much more board-specific.
4743 The key steps you use might look something like this
4746 dap create mychip.dap -chain-position mychip.cpu
4747 target create MyTarget cortex_m -dap mychip.dap
4748 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4749 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4750 MyTarget configure -event reset-init @{ myboard_reinit @}
4753 You should specify a working area if you can; typically it uses some
4755 Such a working area can speed up many things, including bulk
4756 writes to target memory;
4757 flash operations like checking to see if memory needs to be erased;
4758 GDB memory checksumming;
4762 On more complex chips, the work area can become
4763 inaccessible when application code
4764 (such as an operating system)
4765 enables or disables the MMU.
4766 For example, the particular MMU context used to access the virtual
4767 address will probably matter ... and that context might not have
4768 easy access to other addresses needed.
4769 At this writing, OpenOCD doesn't have much MMU intelligence.
4772 It's often very useful to define a @code{reset-init} event handler.
4773 For systems that are normally used with a boot loader,
4774 common tasks include updating clocks and initializing memory
4776 That may be needed to let you write the boot loader into flash,
4777 in order to ``de-brick'' your board; or to load programs into
4778 external DDR memory without having run the boot loader.
4780 @deffn {Config Command} {target create} target_name type configparams...
4781 This command creates a GDB debug target that refers to a specific JTAG tap.
4782 It enters that target into a list, and creates a new
4783 command (@command{@var{target_name}}) which is used for various
4784 purposes including additional configuration.
4787 @item @var{target_name} ... is the name of the debug target.
4788 By convention this should be the same as the @emph{dotted.name}
4789 of the TAP associated with this target, which must be specified here
4790 using the @code{-chain-position @var{dotted.name}} configparam.
4792 This name is also used to create the target object command,
4793 referred to here as @command{$target_name},
4794 and in other places the target needs to be identified.
4795 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4796 @item @var{configparams} ... all parameters accepted by
4797 @command{$target_name configure} are permitted.
4798 If the target is big-endian, set it here with @code{-endian big}.
4800 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4801 @code{-dap @var{dap_name}} here.
4805 @deffn {Command} {$target_name configure} configparams...
4806 The options accepted by this command may also be
4807 specified as parameters to @command{target create}.
4808 Their values can later be queried one at a time by
4809 using the @command{$target_name cget} command.
4811 @emph{Warning:} changing some of these after setup is dangerous.
4812 For example, moving a target from one TAP to another;
4813 and changing its endianness.
4817 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4818 used to access this target.
4820 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4821 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4822 create and manage DAP instances.
4824 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4825 whether the CPU uses big or little endian conventions
4827 @item @code{-event} @var{event_name} @var{event_body} --
4828 @xref{targetevents,,Target Events}.
4829 Note that this updates a list of named event handlers.
4830 Calling this twice with two different event names assigns
4831 two different handlers, but calling it twice with the
4832 same event name assigns only one handler.
4834 Current target is temporarily overridden to the event issuing target
4835 before handler code starts and switched back after handler is done.
4837 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4838 whether the work area gets backed up; by default,
4839 @emph{it is not backed up.}
4840 When possible, use a working_area that doesn't need to be backed up,
4841 since performing a backup slows down operations.
4842 For example, the beginning of an SRAM block is likely to
4843 be used by most build systems, but the end is often unused.
4845 @item @code{-work-area-size} @var{size} -- specify work are size,
4846 in bytes. The same size applies regardless of whether its physical
4847 or virtual address is being used.
4849 @item @code{-work-area-phys} @var{address} -- set the work area
4850 base @var{address} to be used when no MMU is active.
4852 @item @code{-work-area-virt} @var{address} -- set the work area
4853 base @var{address} to be used when an MMU is active.
4854 @emph{Do not specify a value for this except on targets with an MMU.}
4855 The value should normally correspond to a static mapping for the
4856 @code{-work-area-phys} address, set up by the current operating system.
4859 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4860 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4861 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4862 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
4863 @option{RIOT}, @option{Zephyr}
4864 @xref{gdbrtossupport,,RTOS Support}.
4866 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4867 scan and after a reset. A manual call to arp_examine is required to
4868 access the target for debugging.
4870 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4871 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4872 Use this option with systems where multiple, independent cores are connected
4873 to separate access ports of the same DAP.
4875 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4876 to the target. Currently, only the @code{aarch64} target makes use of this option,
4877 where it is a mandatory configuration for the target run control.
4878 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4879 for instruction on how to declare and control a CTI instance.
4881 @anchor{gdbportoverride}
4882 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4883 possible values of the parameter @var{number}, which are not only numeric values.
4884 Use this option to override, for this target only, the global parameter set with
4885 command @command{gdb_port}.
4886 @xref{gdb_port,,command gdb_port}.
4888 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
4889 number of GDB connections that are allowed for the target. Default is 1.
4890 A negative value for @var{number} means unlimited connections.
4891 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
4895 @section Other $target_name Commands
4896 @cindex object command
4898 The Tcl/Tk language has the concept of object commands,
4899 and OpenOCD adopts that same model for targets.
4901 A good Tk example is a on screen button.
4902 Once a button is created a button
4903 has a name (a path in Tk terms) and that name is useable as a first
4904 class command. For example in Tk, one can create a button and later
4905 configure it like this:
4909 button .foobar -background red -command @{ foo @}
4911 .foobar configure -foreground blue
4913 set x [.foobar cget -background]
4915 puts [format "The button is %s" $x]
4918 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4919 button, and its object commands are invoked the same way.
4922 str912.cpu mww 0x1234 0x42
4923 omap3530.cpu mww 0x5555 123
4926 The commands supported by OpenOCD target objects are:
4928 @deffn {Command} {$target_name arp_examine} @option{allow-defer}
4929 @deffnx {Command} {$target_name arp_halt}
4930 @deffnx {Command} {$target_name arp_poll}
4931 @deffnx {Command} {$target_name arp_reset}
4932 @deffnx {Command} {$target_name arp_waitstate}
4933 Internal OpenOCD scripts (most notably @file{startup.tcl})
4934 use these to deal with specific reset cases.
4935 They are not otherwise documented here.
4938 @deffn {Command} {$target_name array2mem} arrayname width address count
4939 @deffnx {Command} {$target_name mem2array} arrayname width address count
4940 These provide an efficient script-oriented interface to memory.
4941 The @code{array2mem} primitive writes bytes, halfwords, words
4942 or double-words; while @code{mem2array} reads them.
4943 In both cases, the TCL side uses an array, and
4944 the target side uses raw memory.
4946 The efficiency comes from enabling the use of
4947 bulk JTAG data transfer operations.
4948 The script orientation comes from working with data
4949 values that are packaged for use by TCL scripts;
4950 @command{mdw} type primitives only print data they retrieve,
4951 and neither store nor return those values.
4954 @item @var{arrayname} ... is the name of an array variable
4955 @item @var{width} ... is 8/16/32/64 - indicating the memory access size
4956 @item @var{address} ... is the target memory address
4957 @item @var{count} ... is the number of elements to process
4961 @deffn {Command} {$target_name cget} queryparm
4962 Each configuration parameter accepted by
4963 @command{$target_name configure}
4964 can be individually queried, to return its current value.
4965 The @var{queryparm} is a parameter name
4966 accepted by that command, such as @code{-work-area-phys}.
4967 There are a few special cases:
4970 @item @code{-event} @var{event_name} -- returns the handler for the
4971 event named @var{event_name}.
4972 This is a special case because setting a handler requires
4974 @item @code{-type} -- returns the target type.
4975 This is a special case because this is set using
4976 @command{target create} and can't be changed
4977 using @command{$target_name configure}.
4980 For example, if you wanted to summarize information about
4981 all the targets you might use something like this:
4984 foreach name [target names] @{
4985 set y [$name cget -endian]
4986 set z [$name cget -type]
4987 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4993 @anchor{targetcurstate}
4994 @deffn {Command} {$target_name curstate}
4995 Displays the current target state:
4996 @code{debug-running},
4999 @code{running}, or @code{unknown}.
5000 (Also, @pxref{eventpolling,,Event Polling}.)
5003 @deffn {Command} {$target_name eventlist}
5004 Displays a table listing all event handlers
5005 currently associated with this target.
5006 @xref{targetevents,,Target Events}.
5009 @deffn {Command} {$target_name invoke-event} event_name
5010 Invokes the handler for the event named @var{event_name}.
5011 (This is primarily intended for use by OpenOCD framework
5012 code, for example by the reset code in @file{startup.tcl}.)
5015 @deffn {Command} {$target_name mdd} [phys] addr [count]
5016 @deffnx {Command} {$target_name mdw} [phys] addr [count]
5017 @deffnx {Command} {$target_name mdh} [phys] addr [count]
5018 @deffnx {Command} {$target_name mdb} [phys] addr [count]
5019 Display contents of address @var{addr}, as
5020 64-bit doublewords (@command{mdd}),
5021 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5022 or 8-bit bytes (@command{mdb}).
5023 When the current target has an MMU which is present and active,
5024 @var{addr} is interpreted as a virtual address.
5025 Otherwise, or if the optional @var{phys} flag is specified,
5026 @var{addr} is interpreted as a physical address.
5027 If @var{count} is specified, displays that many units.
5028 (If you want to manipulate the data instead of displaying it,
5029 see the @code{mem2array} primitives.)
5032 @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
5033 @deffnx {Command} {$target_name mww} [phys] addr word [count]
5034 @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
5035 @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
5036 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
5037 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
5038 at the specified address @var{addr}.
5039 When the current target has an MMU which is present and active,
5040 @var{addr} is interpreted as a virtual address.
5041 Otherwise, or if the optional @var{phys} flag is specified,
5042 @var{addr} is interpreted as a physical address.
5043 If @var{count} is specified, fills that many units of consecutive address.
5046 @anchor{targetevents}
5047 @section Target Events
5048 @cindex target events
5050 At various times, certain things can happen, or you want them to happen.
5053 @item What should happen when GDB connects? Should your target reset?
5054 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
5055 @item Is using SRST appropriate (and possible) on your system?
5056 Or instead of that, do you need to issue JTAG commands to trigger reset?
5057 SRST usually resets everything on the scan chain, which can be inappropriate.
5058 @item During reset, do you need to write to certain memory locations
5059 to set up system clocks or
5060 to reconfigure the SDRAM?
5061 How about configuring the watchdog timer, or other peripherals,
5062 to stop running while you hold the core stopped for debugging?
5065 All of the above items can be addressed by target event handlers.
5066 These are set up by @command{$target_name configure -event} or
5067 @command{target create ... -event}.
5069 The programmer's model matches the @code{-command} option used in Tcl/Tk
5070 buttons and events. The two examples below act the same, but one creates
5071 and invokes a small procedure while the other inlines it.
5074 proc my_init_proc @{ @} @{
5075 echo "Disabling watchdog..."
5076 mww 0xfffffd44 0x00008000
5078 mychip.cpu configure -event reset-init my_init_proc
5079 mychip.cpu configure -event reset-init @{
5080 echo "Disabling watchdog..."
5081 mww 0xfffffd44 0x00008000
5085 The following target events are defined:
5088 @item @b{debug-halted}
5089 @* The target has halted for debug reasons (i.e.: breakpoint)
5090 @item @b{debug-resumed}
5091 @* The target has resumed (i.e.: GDB said run)
5092 @item @b{early-halted}
5093 @* Occurs early in the halt process
5094 @item @b{examine-start}
5095 @* Before target examine is called.
5096 @item @b{examine-end}
5097 @* After target examine is called with no errors.
5098 @item @b{examine-fail}
5099 @* After target examine fails.
5100 @item @b{gdb-attach}
5101 @* When GDB connects. Issued before any GDB communication with the target
5102 starts. GDB expects the target is halted during attachment.
5103 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
5104 connect GDB to running target.
5105 The event can be also used to set up the target so it is possible to probe flash.
5106 Probing flash is necessary during GDB connect if you want to use
5107 @pxref{programmingusinggdb,,programming using GDB}.
5108 Another use of the flash memory map is for GDB to automatically choose
5109 hardware or software breakpoints depending on whether the breakpoint
5110 is in RAM or read only memory.
5111 Default is @code{halt}
5112 @item @b{gdb-detach}
5113 @* When GDB disconnects
5115 @* When the target has halted and GDB is not doing anything (see early halt)
5116 @item @b{gdb-flash-erase-start}
5117 @* Before the GDB flash process tries to erase the flash (default is
5119 @item @b{gdb-flash-erase-end}
5120 @* After the GDB flash process has finished erasing the flash
5121 @item @b{gdb-flash-write-start}
5122 @* Before GDB writes to the flash
5123 @item @b{gdb-flash-write-end}
5124 @* After GDB writes to the flash (default is @code{reset halt})
5126 @* Before the target steps, GDB is trying to start/resume the target
5128 @* The target has halted
5129 @item @b{reset-assert-pre}
5130 @* Issued as part of @command{reset} processing
5131 after @command{reset-start} was triggered
5132 but before either SRST alone is asserted on the scan chain,
5133 or @code{reset-assert} is triggered.
5134 @item @b{reset-assert}
5135 @* Issued as part of @command{reset} processing
5136 after @command{reset-assert-pre} was triggered.
5137 When such a handler is present, cores which support this event will use
5138 it instead of asserting SRST.
5139 This support is essential for debugging with JTAG interfaces which
5140 don't include an SRST line (JTAG doesn't require SRST), and for
5141 selective reset on scan chains that have multiple targets.
5142 @item @b{reset-assert-post}
5143 @* Issued as part of @command{reset} processing
5144 after @code{reset-assert} has been triggered.
5145 or the target asserted SRST on the entire scan chain.
5146 @item @b{reset-deassert-pre}
5147 @* Issued as part of @command{reset} processing
5148 after @code{reset-assert-post} has been triggered.
5149 @item @b{reset-deassert-post}
5150 @* Issued as part of @command{reset} processing
5151 after @code{reset-deassert-pre} has been triggered
5152 and (if the target is using it) after SRST has been
5153 released on the scan chain.
5155 @* Issued as the final step in @command{reset} processing.
5156 @item @b{reset-init}
5157 @* Used by @b{reset init} command for board-specific initialization.
5158 This event fires after @emph{reset-deassert-post}.
5160 This is where you would configure PLLs and clocking, set up DRAM so
5161 you can download programs that don't fit in on-chip SRAM, set up pin
5162 multiplexing, and so on.
5163 (You may be able to switch to a fast JTAG clock rate here, after
5164 the target clocks are fully set up.)
5165 @item @b{reset-start}
5166 @* Issued as the first step in @command{reset} processing
5167 before @command{reset-assert-pre} is called.
5169 This is the most robust place to use @command{jtag_rclk}
5170 or @command{adapter speed} to switch to a low JTAG clock rate,
5171 when reset disables PLLs needed to use a fast clock.
5172 @item @b{resume-start}
5173 @* Before any target is resumed
5174 @item @b{resume-end}
5175 @* After all targets have resumed
5177 @* Target has resumed
5178 @item @b{step-start}
5179 @* Before a target is single-stepped
5181 @* After single-step has completed
5182 @item @b{trace-config}
5183 @* After target hardware trace configuration was changed
5187 OpenOCD events are not supposed to be preempt by another event, but this
5188 is not enforced in current code. Only the target event @b{resumed} is
5189 executed with polling disabled; this avoids polling to trigger the event
5190 @b{halted}, reversing the logical order of execution of their handlers.
5191 Future versions of OpenOCD will prevent the event preemption and will
5192 disable the schedule of polling during the event execution. Do not rely
5193 on polling in any event handler; this means, don't expect the status of
5194 a core to change during the execution of the handler. The event handler
5195 will have to enable polling or use @command{$target_name arp_poll} to
5196 check if the core has changed status.
5199 @node Flash Commands
5200 @chapter Flash Commands
5202 OpenOCD has different commands for NOR and NAND flash;
5203 the ``flash'' command works with NOR flash, while
5204 the ``nand'' command works with NAND flash.
5205 This partially reflects different hardware technologies:
5206 NOR flash usually supports direct CPU instruction and data bus access,
5207 while data from a NAND flash must be copied to memory before it can be
5208 used. (SPI flash must also be copied to memory before use.)
5209 However, the documentation also uses ``flash'' as a generic term;
5210 for example, ``Put flash configuration in board-specific files''.
5214 @item Configure via the command @command{flash bank}
5215 @* Do this in a board-specific configuration file,
5216 passing parameters as needed by the driver.
5217 @item Operate on the flash via @command{flash subcommand}
5218 @* Often commands to manipulate the flash are typed by a human, or run
5219 via a script in some automated way. Common tasks include writing a
5220 boot loader, operating system, or other data.
5222 @* Flashing via GDB requires the flash be configured via ``flash
5223 bank'', and the GDB flash features be enabled.
5224 @xref{gdbconfiguration,,GDB Configuration}.
5227 Many CPUs have the ability to ``boot'' from the first flash bank.
5228 This means that misprogramming that bank can ``brick'' a system,
5229 so that it can't boot.
5230 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5231 board by (re)installing working boot firmware.
5233 @anchor{norconfiguration}
5234 @section Flash Configuration Commands
5235 @cindex flash configuration
5237 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5238 Configures a flash bank which provides persistent storage
5239 for addresses from @math{base} to @math{base + size - 1}.
5240 These banks will often be visible to GDB through the target's memory map.
5241 In some cases, configuring a flash bank will activate extra commands;
5242 see the driver-specific documentation.
5245 @item @var{name} ... may be used to reference the flash bank
5246 in other flash commands. A number is also available.
5247 @item @var{driver} ... identifies the controller driver
5248 associated with the flash bank being declared.
5249 This is usually @code{cfi} for external flash, or else
5250 the name of a microcontroller with embedded flash memory.
5251 @xref{flashdriverlist,,Flash Driver List}.
5252 @item @var{base} ... Base address of the flash chip.
5253 @item @var{size} ... Size of the chip, in bytes.
5254 For some drivers, this value is detected from the hardware.
5255 @item @var{chip_width} ... Width of the flash chip, in bytes;
5256 ignored for most microcontroller drivers.
5257 @item @var{bus_width} ... Width of the data bus used to access the
5258 chip, in bytes; ignored for most microcontroller drivers.
5259 @item @var{target} ... Names the target used to issue
5260 commands to the flash controller.
5261 @comment Actually, it's currently a controller-specific parameter...
5262 @item @var{driver_options} ... drivers may support, or require,
5263 additional parameters. See the driver-specific documentation
5264 for more information.
5267 This command is not available after OpenOCD initialization has completed.
5268 Use it in board specific configuration files, not interactively.
5272 @comment less confusing would be: "flash list" (like "nand list")
5273 @deffn {Command} {flash banks}
5274 Prints a one-line summary of each device that was
5275 declared using @command{flash bank}, numbered from zero.
5276 Note that this is the @emph{plural} form;
5277 the @emph{singular} form is a very different command.
5280 @deffn {Command} {flash list}
5281 Retrieves a list of associative arrays for each device that was
5282 declared using @command{flash bank}, numbered from zero.
5283 This returned list can be manipulated easily from within scripts.
5286 @deffn {Command} {flash probe} num
5287 Identify the flash, or validate the parameters of the configured flash. Operation
5288 depends on the flash type.
5289 The @var{num} parameter is a value shown by @command{flash banks}.
5290 Most flash commands will implicitly @emph{autoprobe} the bank;
5291 flash drivers can distinguish between probing and autoprobing,
5292 but most don't bother.
5295 @section Preparing a Target before Flash Programming
5297 The target device should be in well defined state before the flash programming
5300 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5301 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5302 until the programming session is finished.
5304 If you use @ref{programmingusinggdb,,Programming using GDB},
5305 the target is prepared automatically in the event gdb-flash-erase-start
5307 The jimtcl script @command{program} calls @command{reset init} explicitly.
5309 @section Erasing, Reading, Writing to Flash
5310 @cindex flash erasing
5311 @cindex flash reading
5312 @cindex flash writing
5313 @cindex flash programming
5314 @anchor{flashprogrammingcommands}
5316 One feature distinguishing NOR flash from NAND or serial flash technologies
5317 is that for read access, it acts exactly like any other addressable memory.
5318 This means you can use normal memory read commands like @command{mdw} or
5319 @command{dump_image} with it, with no special @command{flash} subcommands.
5320 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5322 Write access works differently. Flash memory normally needs to be erased
5323 before it's written. Erasing a sector turns all of its bits to ones, and
5324 writing can turn ones into zeroes. This is why there are special commands
5325 for interactive erasing and writing, and why GDB needs to know which parts
5326 of the address space hold NOR flash memory.
5329 Most of these erase and write commands leverage the fact that NOR flash
5330 chips consume target address space. They implicitly refer to the current
5331 JTAG target, and map from an address in that target's address space
5332 back to a flash bank.
5333 @comment In May 2009, those mappings may fail if any bank associated
5334 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5335 A few commands use abstract addressing based on bank and sector numbers,
5336 and don't depend on searching the current target and its address space.
5337 Avoid confusing the two command models.
5340 Some flash chips implement software protection against accidental writes,
5341 since such buggy writes could in some cases ``brick'' a system.
5342 For such systems, erasing and writing may require sector protection to be
5344 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5345 and AT91SAM7 on-chip flash.
5346 @xref{flashprotect,,flash protect}.
5348 @deffn {Command} {flash erase_sector} num first last
5349 Erase sectors in bank @var{num}, starting at sector @var{first}
5350 up to and including @var{last}.
5351 Sector numbering starts at 0.
5352 Providing a @var{last} sector of @option{last}
5353 specifies "to the end of the flash bank".
5354 The @var{num} parameter is a value shown by @command{flash banks}.
5357 @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
5358 Erase sectors starting at @var{address} for @var{length} bytes.
5359 Unless @option{pad} is specified, @math{address} must begin a
5360 flash sector, and @math{address + length - 1} must end a sector.
5361 Specifying @option{pad} erases extra data at the beginning and/or
5362 end of the specified region, as needed to erase only full sectors.
5363 The flash bank to use is inferred from the @var{address}, and
5364 the specified length must stay within that bank.
5365 As a special case, when @var{length} is zero and @var{address} is
5366 the start of the bank, the whole flash is erased.
5367 If @option{unlock} is specified, then the flash is unprotected
5368 before erase starts.
5371 @deffn {Command} {flash filld} address double-word length
5372 @deffnx {Command} {flash fillw} address word length
5373 @deffnx {Command} {flash fillh} address halfword length
5374 @deffnx {Command} {flash fillb} address byte length
5375 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5376 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5377 starting at @var{address} and continuing
5378 for @var{length} units (word/halfword/byte).
5379 No erasure is done before writing; when needed, that must be done
5380 before issuing this command.
5381 Writes are done in blocks of up to 1024 bytes, and each write is
5382 verified by reading back the data and comparing it to what was written.
5383 The flash bank to use is inferred from the @var{address} of
5384 each block, and the specified length must stay within that bank.
5386 @comment no current checks for errors if fill blocks touch multiple banks!
5388 @deffn {Command} {flash mdw} addr [count]
5389 @deffnx {Command} {flash mdh} addr [count]
5390 @deffnx {Command} {flash mdb} addr [count]
5391 Display contents of address @var{addr}, as
5392 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5393 or 8-bit bytes (@command{mdb}).
5394 If @var{count} is specified, displays that many units.
5395 Reads from flash using the flash driver, therefore it enables reading
5396 from a bank not mapped in target address space.
5397 The flash bank to use is inferred from the @var{address} of
5398 each block, and the specified length must stay within that bank.
5401 @deffn {Command} {flash write_bank} num filename [offset]
5402 Write the binary @file{filename} to flash bank @var{num},
5403 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5404 is omitted, start at the beginning of the flash bank.
5405 The @var{num} parameter is a value shown by @command{flash banks}.
5408 @deffn {Command} {flash read_bank} num filename [offset [length]]
5409 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5410 and write the contents to the binary @file{filename}. If @var{offset} is
5411 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5412 read the remaining bytes from the flash bank.
5413 The @var{num} parameter is a value shown by @command{flash banks}.
5416 @deffn {Command} {flash verify_bank} num filename [offset]
5417 Compare the contents of the binary file @var{filename} with the contents of the
5418 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5419 start at the beginning of the flash bank. Fail if the contents do not match.
5420 The @var{num} parameter is a value shown by @command{flash banks}.
5423 @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
5424 Write the image @file{filename} to the current target's flash bank(s).
5425 Only loadable sections from the image are written.
5426 A relocation @var{offset} may be specified, in which case it is added
5427 to the base address for each section in the image.
5428 The file [@var{type}] can be specified
5429 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5430 @option{elf} (ELF file), @option{s19} (Motorola s19).
5431 @option{mem}, or @option{builder}.
5432 The relevant flash sectors will be erased prior to programming
5433 if the @option{erase} parameter is given. If @option{unlock} is
5434 provided, then the flash banks are unlocked before erase and
5435 program. The flash bank to use is inferred from the address of
5439 Be careful using the @option{erase} flag when the flash is holding
5440 data you want to preserve.
5441 Portions of the flash outside those described in the image's
5442 sections might be erased with no notice.
5445 When a section of the image being written does not fill out all the
5446 sectors it uses, the unwritten parts of those sectors are necessarily
5447 also erased, because sectors can't be partially erased.
5449 Data stored in sector "holes" between image sections are also affected.
5450 For example, "@command{flash write_image erase ...}" of an image with
5451 one byte at the beginning of a flash bank and one byte at the end
5452 erases the entire bank -- not just the two sectors being written.
5454 Also, when flash protection is important, you must re-apply it after
5455 it has been removed by the @option{unlock} flag.
5460 @deffn {Command} {flash verify_image} filename [offset] [type]
5461 Verify the image @file{filename} to the current target's flash bank(s).
5462 Parameters follow the description of 'flash write_image'.
5463 In contrast to the 'verify_image' command, for banks with specific
5464 verify method, that one is used instead of the usual target's read
5465 memory methods. This is necessary for flash banks not readable by
5466 ordinary memory reads.
5467 This command gives only an overall good/bad result for each bank, not
5468 addresses of individual failed bytes as it's intended only as quick
5469 check for successful programming.
5472 @section Other Flash commands
5473 @cindex flash protection
5475 @deffn {Command} {flash erase_check} num
5476 Check erase state of sectors in flash bank @var{num},
5477 and display that status.
5478 The @var{num} parameter is a value shown by @command{flash banks}.
5481 @deffn {Command} {flash info} num [sectors]
5482 Print info about flash bank @var{num}, a list of protection blocks
5483 and their status. Use @option{sectors} to show a list of sectors instead.
5485 The @var{num} parameter is a value shown by @command{flash banks}.
5486 This command will first query the hardware, it does not print cached
5487 and possibly stale information.
5490 @anchor{flashprotect}
5491 @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
5492 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5493 in flash bank @var{num}, starting at protection block @var{first}
5494 and continuing up to and including @var{last}.
5495 Providing a @var{last} block of @option{last}
5496 specifies "to the end of the flash bank".
5497 The @var{num} parameter is a value shown by @command{flash banks}.
5498 The protection block is usually identical to a flash sector.
5499 Some devices may utilize a protection block distinct from flash sector.
5500 See @command{flash info} for a list of protection blocks.
5503 @deffn {Command} {flash padded_value} num value
5504 Sets the default value used for padding any image sections, This should
5505 normally match the flash bank erased value. If not specified by this
5506 command or the flash driver then it defaults to 0xff.
5510 @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
5511 This is a helper script that simplifies using OpenOCD as a standalone
5512 programmer. The only required parameter is @option{filename}, the others are optional.
5513 @xref{Flash Programming}.
5516 @anchor{flashdriverlist}
5517 @section Flash Driver List
5518 As noted above, the @command{flash bank} command requires a driver name,
5519 and allows driver-specific options and behaviors.
5520 Some drivers also activate driver-specific commands.
5522 @deffn {Flash Driver} {virtual}
5523 This is a special driver that maps a previously defined bank to another
5524 address. All bank settings will be copied from the master physical bank.
5526 The @var{virtual} driver defines one mandatory parameters,
5529 @item @var{master_bank} The bank that this virtual address refers to.
5532 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5533 the flash bank defined at address 0x1fc00000. Any command executed on
5534 the virtual banks is actually performed on the physical banks.
5536 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5537 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5538 $_TARGETNAME $_FLASHNAME
5539 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5540 $_TARGETNAME $_FLASHNAME
5544 @subsection External Flash
5546 @deffn {Flash Driver} {cfi}
5547 @cindex Common Flash Interface
5549 The ``Common Flash Interface'' (CFI) is the main standard for
5550 external NOR flash chips, each of which connects to a
5551 specific external chip select on the CPU.
5552 Frequently the first such chip is used to boot the system.
5553 Your board's @code{reset-init} handler might need to
5554 configure additional chip selects using other commands (like: @command{mww} to
5555 configure a bus and its timings), or
5556 perhaps configure a GPIO pin that controls the ``write protect'' pin
5558 The CFI driver can use a target-specific working area to significantly
5561 The CFI driver can accept the following optional parameters, in any order:
5564 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5565 like AM29LV010 and similar types.
5566 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5567 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5568 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5569 swapped when writing data values (i.e. not CFI commands).
5572 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5573 wide on a sixteen bit bus:
5576 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5577 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5580 To configure one bank of 32 MBytes
5581 built from two sixteen bit (two byte) wide parts wired in parallel
5582 to create a thirty-two bit (four byte) bus with doubled throughput:
5585 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5588 @c "cfi part_id" disabled
5591 @deffn {Flash Driver} {jtagspi}
5592 @cindex Generic JTAG2SPI driver
5596 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5597 SPI flash connected to them. To access this flash from the host, the device
5598 is first programmed with a special proxy bitstream that
5599 exposes the SPI flash on the device's JTAG interface. The flash can then be
5600 accessed through JTAG.
5602 Since signaling between JTAG and SPI is compatible, all that is required for
5603 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5604 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5605 a bitstream for several Xilinx FPGAs can be found in
5606 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5607 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5609 This flash bank driver requires a target on a JTAG tap and will access that
5610 tap directly. Since no support from the target is needed, the target can be a
5611 "testee" dummy. Since the target does not expose the flash memory
5612 mapping, target commands that would otherwise be expected to access the flash
5613 will not work. These include all @command{*_image} and
5614 @command{$target_name m*} commands as well as @command{program}. Equivalent
5615 functionality is available through the @command{flash write_bank},
5616 @command{flash read_bank}, and @command{flash verify_bank} commands.
5618 According to device size, 1- to 4-byte addresses are sent. However, some
5619 flash chips additionally have to be switched to 4-byte addresses by an extra
5623 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5624 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5625 @var{USER1} instruction.
5629 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5630 set _XILINX_USER1 0x02
5631 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5632 $_TARGETNAME $_XILINX_USER1
5635 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5636 Sets flash parameters: @var{name} human readable string, @var{total_size}
5637 size in bytes, @var{page_size} is write page size. @var{read_cmd} and @var{pprg_cmd}
5638 are commands for read and page program, respectively. @var{mass_erase_cmd},
5639 @var{sector_size} and @var{sector_erase_cmd} are optional.
5641 jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
5645 @deffn Command {jtagspi cmd} bank_id resp_num cmd_byte ...
5646 Sends command @var{cmd_byte} and at most 20 following bytes and reads
5647 @var{resp_num} bytes afterwards. E.g. for 'Enter 4-byte address mode'
5649 jtagspi cmd 0 0 0xB7
5653 @deffn Command {jtagspi always_4byte} bank_id [ on | off ]
5654 Some devices use 4-byte addresses for all commands except the legacy 0x03 read
5655 regardless of device size. This command controls the corresponding hack.
5659 @deffn {Flash Driver} {xcf}
5660 @cindex Xilinx Platform flash driver
5662 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5663 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5664 only difference is special registers controlling its FPGA specific behavior.
5665 They must be properly configured for successful FPGA loading using
5666 additional @var{xcf} driver command:
5668 @deffn {Command} {xcf ccb} <bank_id>
5669 command accepts additional parameters:
5671 @item @var{external|internal} ... selects clock source.
5672 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5673 @item @var{slave|master} ... selects slave of master mode for flash device.
5674 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5678 xcf ccb 0 external parallel slave 40
5680 All of them must be specified even if clock frequency is pointless
5681 in slave mode. If only bank id specified than command prints current
5682 CCB register value. Note: there is no need to write this register
5683 every time you erase/program data sectors because it stores in
5687 @deffn {Command} {xcf configure} <bank_id>
5688 Initiates FPGA loading procedure. Useful if your board has no "configure"
5695 Additional driver notes:
5697 @item Only single revision supported.
5698 @item Driver automatically detects need of bit reverse, but
5699 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5700 (Intel hex) file types supported.
5701 @item For additional info check xapp972.pdf and ug380.pdf.
5705 @deffn {Flash Driver} {lpcspifi}
5706 @cindex NXP SPI Flash Interface
5709 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5710 Flash Interface (SPIFI) peripheral that can drive and provide
5711 memory mapped access to external SPI flash devices.
5713 The lpcspifi driver initializes this interface and provides
5714 program and erase functionality for these serial flash devices.
5715 Use of this driver @b{requires} a working area of at least 1kB
5716 to be configured on the target device; more than this will
5717 significantly reduce flash programming times.
5719 The setup command only requires the @var{base} parameter. All
5720 other parameters are ignored, and the flash size and layout
5721 are configured by the driver.
5724 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5729 @deffn {Flash Driver} {stmsmi}
5730 @cindex STMicroelectronics Serial Memory Interface
5733 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5734 SPEAr MPU family) include a proprietary
5735 ``Serial Memory Interface'' (SMI) controller able to drive external
5737 Depending on specific device and board configuration, up to 4 external
5738 flash devices can be connected.
5740 SMI makes the flash content directly accessible in the CPU address
5741 space; each external device is mapped in a memory bank.
5742 CPU can directly read data, execute code and boot from SMI banks.
5743 Normal OpenOCD commands like @command{mdw} can be used to display
5746 The setup command only requires the @var{base} parameter in order
5747 to identify the memory bank.
5748 All other parameters are ignored. Additional information, like
5749 flash size, are detected automatically.
5752 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5757 @deffn {Flash Driver} {stmqspi}
5758 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
5762 Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
5763 (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
5764 controller able to drive one or even two (dual mode) external SPI flash devices.
5765 The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
5766 Currently only the regular command mode is supported, whereas the HyperFlash
5769 QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
5770 space; in case of dual mode both devices must be of the same type and are
5771 mapped in the same memory bank (even and odd addresses interleaved).
5772 CPU can directly read data, execute code (but not boot) from QuadSPI bank.
5774 The 'flash bank' command only requires the @var{base} parameter and the extra
5775 parameter @var{io_base} in order to identify the memory bank. Both are fixed
5776 by hardware, see datasheet or RM. All other parameters are ignored.
5778 The controller must be initialized after each reset and properly configured
5779 for memory-mapped read operation for the particular flash chip(s), for the full
5780 list of available register settings cf. the controller's RM. This setup is quite
5781 board specific (that's why booting from this memory is not possible). The
5782 flash driver infers all parameters from current controller register values when
5783 'flash probe @var{bank_id}' is executed.
5785 Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
5786 but only after proper controller initialization as described above. However,
5787 due to a silicon bug in some devices, attempting to access the very last word
5790 It is possible to use two (even different) flash chips alternatingly, if individual
5791 bank chip selects are available. For some package variants, this is not the case
5792 due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
5793 and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
5794 change, so the address spaces of both devices will overlap. In dual flash mode
5795 both chips must be identical regarding size and most other properties.
5797 Block or sector protection internal to the flash chip is not handled by this
5798 driver at all, but can be dealt with manually by the 'cmd' command, see below.
5799 The sector protection via 'flash protect' command etc. is completely internal to
5800 openocd, intended only to prevent accidental erase or overwrite and it does not
5801 persist across openocd invocations.
5803 OpenOCD contains a hardcoded list of flash devices with their properties,
5804 these are auto-detected. If a device is not included in this list, SFDP discovery
5805 is attempted. If this fails or gives inappropriate results, manual setting is
5806 required (see 'set' command).
5809 flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
5810 $_TARGETNAME 0xA0001000
5811 flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
5812 $_TARGETNAME 0xA0001400
5815 There are three specific commands
5816 @deffn {Command} {stmqspi mass_erase} bank_id
5817 Clears sector protections and performs a mass erase. Works only if there is no
5818 chip specific write protection engaged.
5821 @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5822 Set flash parameters: @var{name} human readable string, @var{total_size} size
5823 in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
5824 are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
5825 @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
5826 and @var{sector_erase_cmd} are optional.
5828 This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
5829 which don't support an id command.
5831 In dual mode parameters of both chips are set identically. The parameters refer to
5832 a single chip, so the whole bank gets twice the specified capacity etc.
5835 @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
5836 If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
5837 bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
5838 sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
5839 i.e. the total number of bytes (including cmd_byte) must be odd.
5841 If @var{resp_num} is not zero, cmd and at most four following data bytes are
5842 sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
5843 are read interleaved from both chips starting with chip 1. In this case
5844 @var{resp_num} must be even.
5846 Note the hardware dictated subtle difference of those two cases in dual-flash mode.
5848 To check basic communication settings, issue
5850 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
5851 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
5853 for single flash mode or
5855 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
5856 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
5858 for dual flash mode. This should return the status register contents.
5860 In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
5861 complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
5862 need a dummy address, e.g.
5864 stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
5866 should return the status register contents.
5872 @deffn {Flash Driver} {mrvlqspi}
5873 This driver supports QSPI flash controller of Marvell's Wireless
5874 Microcontroller platform.
5876 The flash size is autodetected based on the table of known JEDEC IDs
5877 hardcoded in the OpenOCD sources.
5880 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5885 @deffn {Flash Driver} {ath79}
5886 @cindex Atheros ath79 SPI driver
5888 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5890 On reset a SPI flash connected to the first chip select (CS0) is made
5891 directly read-accessible in the CPU address space (up to 16MBytes)
5892 and is usually used to store the bootloader and operating system.
5893 Normal OpenOCD commands like @command{mdw} can be used to display
5894 the flash content while it is in memory-mapped mode (only the first
5895 4MBytes are accessible without additional configuration on reset).
5897 The setup command only requires the @var{base} parameter in order
5898 to identify the memory bank. The actual value for the base address
5899 is not otherwise used by the driver. However the mapping is passed
5900 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5901 address should be the actual memory mapped base address. For unmapped
5902 chipselects (CS1 and CS2) care should be taken to use a base address
5903 that does not overlap with real memory regions.
5904 Additional information, like flash size, are detected automatically.
5905 An optional additional parameter sets the chipselect for the bank,
5906 with the default CS0.
5907 CS1 and CS2 require additional GPIO setup before they can be used
5908 since the alternate function must be enabled on the GPIO pin
5909 CS1/CS2 is routed to on the given SoC.
5912 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
5914 # When using multiple chipselects the base should be different
5915 # for each, otherwise the write_image command is not able to
5916 # distinguish the banks.
5917 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
5918 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5919 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5924 @deffn {Flash Driver} {fespi}
5925 @cindex Freedom E SPI
5928 SiFive's Freedom E SPI controller, used in HiFive and other boards.
5931 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
5935 @subsection Internal Flash (Microcontrollers)
5937 @deffn {Flash Driver} {aduc702x}
5938 The ADUC702x analog microcontrollers from Analog Devices
5939 include internal flash and use ARM7TDMI cores.
5940 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5941 The setup command only requires the @var{target} argument
5942 since all devices in this family have the same memory layout.
5945 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5949 @deffn {Flash Driver} {ambiqmicro}
5952 All members of the Apollo microcontroller family from
5953 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5954 The host connects over USB to an FTDI interface that communicates
5955 with the target using SWD.
5957 The @var{ambiqmicro} driver reads the Chip Information Register detect
5958 the device class of the MCU.
5959 The Flash and SRAM sizes directly follow device class, and are used
5960 to set up the flash banks.
5961 If this fails, the driver will use default values set to the minimum
5962 sizes of an Apollo chip.
5964 All Apollo chips have two flash banks of the same size.
5965 In all cases the first flash bank starts at location 0,
5966 and the second bank starts after the first.
5970 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5971 # Flash bank 1 - same size as bank0, starts after bank 0.
5972 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5976 Flash is programmed using custom entry points into the bootloader.
5977 This is the only way to program the flash as no flash control registers
5978 are available to the user.
5980 The @var{ambiqmicro} driver adds some additional commands:
5982 @deffn {Command} {ambiqmicro mass_erase} <bank>
5985 @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
5988 @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
5989 Program OTP is a one time operation to create write protected flash.
5990 The user writes sectors to SRAM starting at 0x10000010.
5991 Program OTP will write these sectors from SRAM to flash, and write protect
5997 @deffn {Flash Driver} {at91samd}
5999 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
6000 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
6002 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
6004 The devices have one flash bank:
6007 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
6010 @deffn {Command} {at91samd chip-erase}
6011 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6012 used to erase a chip back to its factory state and does not require the
6013 processor to be halted.
6016 @deffn {Command} {at91samd set-security}
6017 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
6018 to the Flash and can only be undone by using the chip-erase command which
6019 erases the Flash contents and turns off the security bit. Warning: at this
6020 time, openocd will not be able to communicate with a secured chip and it is
6021 therefore not possible to chip-erase it without using another tool.
6024 at91samd set-security enable
6028 @deffn {Command} {at91samd eeprom}
6029 Shows or sets the EEPROM emulation size configuration, stored in the User Row
6030 of the Flash. When setting, the EEPROM size must be specified in bytes and it
6031 must be one of the permitted sizes according to the datasheet. Settings are
6032 written immediately but only take effect on MCU reset. EEPROM emulation
6033 requires additional firmware support and the minimum EEPROM size may not be
6034 the same as the minimum that the hardware supports. Set the EEPROM size to 0
6035 in order to disable this feature.
6039 at91samd eeprom 1024
6043 @deffn {Command} {at91samd bootloader}
6044 Shows or sets the bootloader size configuration, stored in the User Row of the
6045 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6046 must be specified in bytes and it must be one of the permitted sizes according
6047 to the datasheet. Settings are written immediately but only take effect on
6048 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
6052 at91samd bootloader 16384
6056 @deffn {Command} {at91samd dsu_reset_deassert}
6057 This command releases internal reset held by DSU
6058 and prepares reset vector catch in case of reset halt.
6059 Command is used internally in event reset-deassert-post.
6062 @deffn {Command} {at91samd nvmuserrow}
6063 Writes or reads the entire 64 bit wide NVM user row register which is located at
6064 0x804000. This register includes various fuses lock-bits and factory calibration
6065 data. Reading the register is done by invoking this command without any
6066 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
6067 is the register value to be written and the second one is an optional changemask.
6068 Every bit which value in changemask is 0 will stay unchanged. The lock- and
6069 reserved-bits are masked out and cannot be changed.
6073 >at91samd nvmuserrow
6074 NVMUSERROW: 0xFFFFFC5DD8E0C788
6075 # Write 0xFFFFFC5DD8E0C788 to user row
6076 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
6077 # Write 0x12300 to user row but leave other bits and low
6079 >at91samd nvmuserrow 0x12345 0xFFF00
6086 @deffn {Flash Driver} {at91sam3}
6088 All members of the AT91SAM3 microcontroller family from
6089 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
6090 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
6091 that the driver was orginaly developed and tested using the
6092 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
6093 the family was cribbed from the data sheet. @emph{Note to future
6094 readers/updaters: Please remove this worrisome comment after other
6095 chips are confirmed.}
6097 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
6098 have one flash bank. In all cases the flash banks are at
6099 the following fixed locations:
6102 # Flash bank 0 - all chips
6103 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
6104 # Flash bank 1 - only 256K chips
6105 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
6108 Internally, the AT91SAM3 flash memory is organized as follows.
6109 Unlike the AT91SAM7 chips, these are not used as parameters
6110 to the @command{flash bank} command:
6113 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
6114 @item @emph{Bank Size:} 128K/64K Per flash bank
6115 @item @emph{Sectors:} 16 or 8 per bank
6116 @item @emph{SectorSize:} 8K Per Sector
6117 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
6120 The AT91SAM3 driver adds some additional commands:
6122 @deffn {Command} {at91sam3 gpnvm}
6123 @deffnx {Command} {at91sam3 gpnvm clear} number
6124 @deffnx {Command} {at91sam3 gpnvm set} number
6125 @deffnx {Command} {at91sam3 gpnvm show} [@option{all}|number]
6126 With no parameters, @command{show} or @command{show all},
6127 shows the status of all GPNVM bits.
6128 With @command{show} @var{number}, displays that bit.
6130 With @command{set} @var{number} or @command{clear} @var{number},
6131 modifies that GPNVM bit.
6134 @deffn {Command} {at91sam3 info}
6135 This command attempts to display information about the AT91SAM3
6136 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
6137 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
6138 document id: doc6430A] and decodes the values. @emph{Second} it reads the
6139 various clock configuration registers and attempts to display how it
6140 believes the chip is configured. By default, the SLOWCLK is assumed to
6141 be 32768 Hz, see the command @command{at91sam3 slowclk}.
6144 @deffn {Command} {at91sam3 slowclk} [value]
6145 This command shows/sets the slow clock frequency used in the
6146 @command{at91sam3 info} command calculations above.
6150 @deffn {Flash Driver} {at91sam4}
6152 All members of the AT91SAM4 microcontroller family from
6153 Atmel include internal flash and use ARM's Cortex-M4 core.
6154 This driver uses the same command names/syntax as @xref{at91sam3}.
6157 @deffn {Flash Driver} {at91sam4l}
6159 All members of the AT91SAM4L microcontroller family from
6160 Atmel include internal flash and use ARM's Cortex-M4 core.
6161 This driver uses the same command names/syntax as @xref{at91sam3}.
6163 The AT91SAM4L driver adds some additional commands:
6164 @deffn {Command} {at91sam4l smap_reset_deassert}
6165 This command releases internal reset held by SMAP
6166 and prepares reset vector catch in case of reset halt.
6167 Command is used internally in event reset-deassert-post.
6172 @deffn {Flash Driver} {atsame5}
6174 All members of the SAM E54, E53, E51 and D51 microcontroller
6175 families from Microchip (former Atmel) include internal flash
6176 and use ARM's Cortex-M4 core.
6178 The devices have two ECC flash banks with a swapping feature.
6179 This driver handles both banks together as it were one.
6180 Bank swapping is not supported yet.
6183 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
6186 @deffn {Command} {atsame5 bootloader}
6187 Shows or sets the bootloader size configuration, stored in the User Page of the
6188 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6189 must be specified in bytes. The nearest bigger protection size is used.
6190 Settings are written immediately but only take effect on MCU reset.
6191 Setting the bootloader size to 0 disables bootloader protection.
6195 atsame5 bootloader 16384
6199 @deffn {Command} {atsame5 chip-erase}
6200 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6201 used to erase a chip back to its factory state and does not require the
6202 processor to be halted.
6205 @deffn {Command} {atsame5 dsu_reset_deassert}
6206 This command releases internal reset held by DSU
6207 and prepares reset vector catch in case of reset halt.
6208 Command is used internally in event reset-deassert-post.
6211 @deffn {Command} {atsame5 userpage}
6212 Writes or reads the first 64 bits of NVM User Page which is located at
6213 0x804000. This field includes various fuses.
6214 Reading is done by invoking this command without any arguments.
6215 Writing is possible by giving 1 or 2 hex values. The first argument
6216 is the value to be written and the second one is an optional bit mask
6217 (a zero bit in the mask means the bit stays unchanged).
6218 The reserved fields are always masked out and cannot be changed.
6223 USER PAGE: 0xAEECFF80FE9A9239
6225 >atsame5 userpage 0xAEECFF80FE9A9239
6226 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
6227 # bits unchanged (setup SmartEEPROM of virtual size 8192
6229 >atsame5 userpage 0x4200000000 0x7f00000000
6235 @deffn {Flash Driver} {atsamv}
6237 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
6238 Atmel include internal flash and use ARM's Cortex-M7 core.
6239 This driver uses the same command names/syntax as @xref{at91sam3}.
6242 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
6245 @deffn {Command} {atsamv gpnvm} [@option{show} [@option{all}|number]]
6246 @deffnx {Command} {atsamv gpnvm} (@option{clr}|@option{set}) number
6247 With no parameters, @option{show} or @option{show all},
6248 shows the status of all GPNVM bits.
6249 With @option{show} @var{number}, displays that bit.
6251 With @option{set} @var{number} or @option{clear} @var{number},
6252 modifies that GPNVM bit.
6257 @deffn {Flash Driver} {at91sam7}
6258 All members of the AT91SAM7 microcontroller family from Atmel include
6259 internal flash and use ARM7TDMI cores. The driver automatically
6260 recognizes a number of these chips using the chip identification
6261 register, and autoconfigures itself.
6264 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
6267 For chips which are not recognized by the controller driver, you must
6268 provide additional parameters in the following order:
6271 @item @var{chip_model} ... label used with @command{flash info}
6273 @item @var{sectors_per_bank}
6274 @item @var{pages_per_sector}
6275 @item @var{pages_size}
6276 @item @var{num_nvm_bits}
6277 @item @var{freq_khz} ... required if an external clock is provided,
6278 optional (but recommended) when the oscillator frequency is known
6281 It is recommended that you provide zeroes for all of those values
6282 except the clock frequency, so that everything except that frequency
6283 will be autoconfigured.
6284 Knowing the frequency helps ensure correct timings for flash access.
6286 The flash controller handles erases automatically on a page (128/256 byte)
6287 basis, so explicit erase commands are not necessary for flash programming.
6288 However, there is an ``EraseAll`` command that can erase an entire flash
6289 plane (of up to 256KB), and it will be used automatically when you issue
6290 @command{flash erase_sector} or @command{flash erase_address} commands.
6292 @deffn {Command} {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
6293 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
6294 bit for the processor. Each processor has a number of such bits,
6295 used for controlling features such as brownout detection (so they
6296 are not truly general purpose).
6298 This assumes that the first flash bank (number 0) is associated with
6299 the appropriate at91sam7 target.
6304 @deffn {Flash Driver} {avr}
6305 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
6306 @emph{The current implementation is incomplete.}
6307 @comment - defines mass_erase ... pointless given flash_erase_address
6310 @deffn {Flash Driver} {bluenrg-x}
6311 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
6312 The driver automatically recognizes these chips using
6313 the chip identification registers, and autoconfigures itself.
6316 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
6319 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
6320 each single sector one by one.
6323 flash erase_sector 0 0 last # It will perform a mass erase
6326 Triggering a mass erase is also useful when users want to disable readout protection.
6329 @deffn {Flash Driver} {cc26xx}
6330 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
6331 Instruments include internal flash. The cc26xx flash driver supports both the
6332 CC13xx and CC26xx family of devices. The driver automatically recognizes the
6333 specific version's flash parameters and autoconfigures itself. The flash bank
6334 starts at address 0.
6337 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
6341 @deffn {Flash Driver} {cc3220sf}
6342 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
6343 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
6344 supports the internal flash. The serial flash on SimpleLink boards is
6345 programmed via the bootloader over a UART connection. Security features of
6346 the CC3220SF may erase the internal flash during power on reset. Refer to
6347 documentation at @url{www.ti.com/cc3220sf} for details on security features
6348 and programming the serial flash.
6351 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
6355 @deffn {Flash Driver} {efm32}
6356 All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs)
6357 include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically
6358 recognizes a number of these chips using the chip identification register, and
6359 autoconfigures itself.
6361 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
6363 It supports writing to the user data page, as well as the portion of the lockbits page
6364 past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs
6365 bootloader/AppLoader system for encryption keys. Setting protection on these pages is
6366 currently not supported.
6368 flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
6369 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
6372 A special feature of efm32 controllers is that it is possible to completely disable the
6373 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
6374 this via the following command:
6378 The @var{num} parameter is a value shown by @command{flash banks}.
6379 Note that in order for this command to take effect, the target needs to be reset.
6380 @emph{The current implementation is incomplete. Unprotecting flash pages is not
6384 @deffn {Flash Driver} {esirisc}
6385 Members of the eSi-RISC family may optionally include internal flash programmed
6386 via the eSi-TSMC Flash interface. Additional parameters are required to
6387 configure the driver: @option{cfg_address} is the base address of the
6388 configuration register interface, @option{clock_hz} is the expected clock
6389 frequency, and @option{wait_states} is the number of configured read wait states.
6392 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6393 $_TARGETNAME cfg_address clock_hz wait_states
6396 @deffn {Command} {esirisc flash mass_erase} bank_id
6397 Erase all pages in data memory for the bank identified by @option{bank_id}.
6400 @deffn {Command} {esirisc flash ref_erase} bank_id
6401 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6402 is an uncommon operation.}
6406 @deffn {Flash Driver} {fm3}
6407 All members of the FM3 microcontroller family from Fujitsu
6408 include internal flash and use ARM Cortex-M3 cores.
6409 The @var{fm3} driver uses the @var{target} parameter to select the
6410 correct bank config, it can currently be one of the following:
6411 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6412 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6415 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6419 @deffn {Flash Driver} {fm4}
6420 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6421 include internal flash and use ARM Cortex-M4 cores.
6422 The @var{fm4} driver uses a @var{family} parameter to select the
6423 correct bank config, it can currently be one of the following:
6424 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6425 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6426 with @code{x} treated as wildcard and otherwise case (and any trailing
6427 characters) ignored.
6430 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6431 $_TARGETNAME S6E2CCAJ0A
6432 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6433 $_TARGETNAME S6E2CCAJ0A
6435 @emph{The current implementation is incomplete. Protection is not supported,
6436 nor is Chip Erase (only Sector Erase is implemented).}
6439 @deffn {Flash Driver} {kinetis}
6441 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
6442 from NXP (former Freescale) include
6443 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
6444 recognizes flash size and a number of flash banks (1-4) using the chip
6445 identification register, and autoconfigures itself.
6446 Use kinetis_ke driver for KE0x and KEAx devices.
6448 The @var{kinetis} driver defines option:
6450 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
6454 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6457 @deffn {Config Command} {kinetis create_banks}
6458 Configuration command enables automatic creation of additional flash banks
6459 based on real flash layout of device. Banks are created during device probe.
6460 Use 'flash probe 0' to force probe.
6463 @deffn {Command} {kinetis fcf_source} [protection|write]
6464 Select what source is used when writing to a Flash Configuration Field.
6465 @option{protection} mode builds FCF content from protection bits previously
6466 set by 'flash protect' command.
6467 This mode is default. MCU is protected from unwanted locking by immediate
6468 writing FCF after erase of relevant sector.
6469 @option{write} mode enables direct write to FCF.
6470 Protection cannot be set by 'flash protect' command. FCF is written along
6471 with the rest of a flash image.
6472 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6475 @deffn {Command} {kinetis fopt} [num]
6476 Set value to write to FOPT byte of Flash Configuration Field.
6477 Used in kinetis 'fcf_source protection' mode only.
6480 @deffn {Command} {kinetis mdm check_security}
6481 Checks status of device security lock. Used internally in examine-end
6482 and examine-fail event.
6485 @deffn {Command} {kinetis mdm halt}
6486 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6487 loop when connecting to an unsecured target.
6490 @deffn {Command} {kinetis mdm mass_erase}
6491 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6492 back to its factory state, removing security. It does not require the processor
6493 to be halted, however the target will remain in a halted state after this
6497 @deffn {Command} {kinetis nvm_partition}
6498 For FlexNVM devices only (KxxDX and KxxFX).
6499 Command shows or sets data flash or EEPROM backup size in kilobytes,
6500 sets two EEPROM blocks sizes in bytes and enables/disables loading
6501 of EEPROM contents to FlexRAM during reset.
6503 For details see device reference manual, Flash Memory Module,
6504 Program Partition command.
6506 Setting is possible only once after mass_erase.
6507 Reset the device after partition setting.
6509 Show partition size:
6511 kinetis nvm_partition info
6514 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6515 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6517 kinetis nvm_partition dataflash 32 512 1536 on
6520 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6521 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6523 kinetis nvm_partition eebkp 16 1024 1024 off
6527 @deffn {Command} {kinetis mdm reset}
6528 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6529 RESET pin, which can be used to reset other hardware on board.
6532 @deffn {Command} {kinetis disable_wdog}
6533 For Kx devices only (KLx has different COP watchdog, it is not supported).
6534 Command disables watchdog timer.
6538 @deffn {Flash Driver} {kinetis_ke}
6540 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6541 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6542 the KE0x sub-family using the chip identification register, and
6543 autoconfigures itself.
6544 Use kinetis (not kinetis_ke) driver for KE1x devices.
6547 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6550 @deffn {Command} {kinetis_ke mdm check_security}
6551 Checks status of device security lock. Used internally in examine-end event.
6554 @deffn {Command} {kinetis_ke mdm mass_erase}
6555 Issues a complete Flash erase via the MDM-AP.
6556 This can be used to erase a chip back to its factory state.
6557 Command removes security lock from a device (use of SRST highly recommended).
6558 It does not require the processor to be halted.
6561 @deffn {Command} {kinetis_ke disable_wdog}
6562 Command disables watchdog timer.
6566 @deffn {Flash Driver} {lpc2000}
6567 This is the driver to support internal flash of all members of the
6568 LPC11(x)00 and LPC1300 microcontroller families and most members of
6569 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6570 LPC8Nxx and NHS31xx microcontroller families from NXP.
6573 There are LPC2000 devices which are not supported by the @var{lpc2000}
6575 The LPC2888 is supported by the @var{lpc288x} driver.
6576 The LPC29xx family is supported by the @var{lpc2900} driver.
6579 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6580 which must appear in the following order:
6583 @item @var{variant} ... required, may be
6584 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6585 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6586 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6587 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6589 @option{lpc800} (LPC8xx)
6590 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6591 @option{lpc1500} (LPC15xx)
6592 @option{lpc54100} (LPC541xx)
6593 @option{lpc4000} (LPC40xx)
6594 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6595 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6596 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6597 at which the core is running
6598 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6599 telling the driver to calculate a valid checksum for the exception vector table.
6601 If you don't provide @option{calc_checksum} when you're writing the vector
6602 table, the boot ROM will almost certainly ignore your flash image.
6603 However, if you do provide it,
6604 with most tool chains @command{verify_image} will fail.
6606 @item @option{iap_entry} ... optional telling the driver to use a different
6607 ROM IAP entry point.
6610 LPC flashes don't require the chip and bus width to be specified.
6613 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6614 lpc2000_v2 14765 calc_checksum
6617 @deffn {Command} {lpc2000 part_id} bank
6618 Displays the four byte part identifier associated with
6619 the specified flash @var{bank}.
6623 @deffn {Flash Driver} {lpc288x}
6624 The LPC2888 microcontroller from NXP needs slightly different flash
6625 support from its lpc2000 siblings.
6626 The @var{lpc288x} driver defines one mandatory parameter,
6627 the programming clock rate in Hz.
6628 LPC flashes don't require the chip and bus width to be specified.
6631 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6635 @deffn {Flash Driver} {lpc2900}
6636 This driver supports the LPC29xx ARM968E based microcontroller family
6639 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6640 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6641 sector layout are auto-configured by the driver.
6642 The driver has one additional mandatory parameter: The CPU clock rate
6643 (in kHz) at the time the flash operations will take place. Most of the time this
6644 will not be the crystal frequency, but a higher PLL frequency. The
6645 @code{reset-init} event handler in the board script is usually the place where
6648 The driver rejects flashless devices (currently the LPC2930).
6650 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6651 It must be handled much more like NAND flash memory, and will therefore be
6652 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6654 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6655 sector needs to be erased or programmed, it is automatically unprotected.
6656 What is shown as protection status in the @code{flash info} command, is
6657 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6658 sector from ever being erased or programmed again. As this is an irreversible
6659 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6660 and not by the standard @code{flash protect} command.
6662 Example for a 125 MHz clock frequency:
6664 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6667 Some @code{lpc2900}-specific commands are defined. In the following command list,
6668 the @var{bank} parameter is the bank number as obtained by the
6669 @code{flash banks} command.
6671 @deffn {Command} {lpc2900 signature} bank
6672 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6673 content. This is a hardware feature of the flash block, hence the calculation is
6674 very fast. You may use this to verify the content of a programmed device against
6679 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6683 @deffn {Command} {lpc2900 read_custom} bank filename
6684 Reads the 912 bytes of customer information from the flash index sector, and
6685 saves it to a file in binary format.
6688 lpc2900 read_custom 0 /path_to/customer_info.bin
6692 The index sector of the flash is a @emph{write-only} sector. It cannot be
6693 erased! In order to guard against unintentional write access, all following
6694 commands need to be preceded by a successful call to the @code{password}
6697 @deffn {Command} {lpc2900 password} bank password
6698 You need to use this command right before each of the following commands:
6699 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6700 @code{lpc2900 secure_jtag}.
6702 The password string is fixed to "I_know_what_I_am_doing".
6705 lpc2900 password 0 I_know_what_I_am_doing
6706 Potentially dangerous operation allowed in next command!
6710 @deffn {Command} {lpc2900 write_custom} bank filename type
6711 Writes the content of the file into the customer info space of the flash index
6712 sector. The filetype can be specified with the @var{type} field. Possible values
6713 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6714 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6715 contain a single section, and the contained data length must be exactly
6717 @quotation Attention
6718 This cannot be reverted! Be careful!
6722 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6726 @deffn {Command} {lpc2900 secure_sector} bank first last
6727 Secures the sector range from @var{first} to @var{last} (including) against
6728 further program and erase operations. The sector security will be effective
6729 after the next power cycle.
6730 @quotation Attention
6731 This cannot be reverted! Be careful!
6733 Secured sectors appear as @emph{protected} in the @code{flash info} command.
6736 lpc2900 secure_sector 0 1 1
6738 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
6739 # 0: 0x00000000 (0x2000 8kB) not protected
6740 # 1: 0x00002000 (0x2000 8kB) protected
6741 # 2: 0x00004000 (0x2000 8kB) not protected
6745 @deffn {Command} {lpc2900 secure_jtag} bank
6746 Irreversibly disable the JTAG port. The new JTAG security setting will be
6747 effective after the next power cycle.
6748 @quotation Attention
6749 This cannot be reverted! Be careful!
6753 lpc2900 secure_jtag 0
6758 @deffn {Flash Driver} {mdr}
6759 This drivers handles the integrated NOR flash on Milandr Cortex-M
6760 based controllers. A known limitation is that the Info memory can't be
6761 read or verified as it's not memory mapped.
6764 flash bank <name> mdr <base> <size> \
6765 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
6769 @item @var{type} - 0 for main memory, 1 for info memory
6770 @item @var{page_count} - total number of pages
6771 @item @var{sec_count} - number of sector per page count
6776 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
6777 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
6778 0 0 $_TARGETNAME 1 1 4
6780 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
6781 0 0 $_TARGETNAME 0 32 4
6786 @deffn {Flash Driver} {msp432}
6787 All versions of the SimpleLink MSP432 microcontrollers from Texas
6788 Instruments include internal flash. The msp432 flash driver automatically
6789 recognizes the specific version's flash parameters and autoconfigures itself.
6790 Main program flash starts at address 0. The information flash region on
6791 MSP432P4 versions starts at address 0x200000.
6794 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
6797 @deffn {Command} {msp432 mass_erase} bank_id [main|all]
6798 Performs a complete erase of flash. By default, @command{mass_erase} will erase
6799 only the main program flash.
6801 On MSP432P4 versions, using @command{mass_erase all} will erase both the
6802 main program and information flash regions. To also erase the BSL in information
6803 flash, the user must first use the @command{bsl} command.
6806 @deffn {Command} {msp432 bsl} bank_id [unlock|lock]
6807 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
6808 region in information flash so that flash commands can erase or write the BSL.
6809 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
6811 To erase and program the BSL:
6814 flash erase_address 0x202000 0x2000
6815 flash write_image bsl.bin 0x202000
6821 @deffn {Flash Driver} {niietcm4}
6822 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6823 based controllers. Flash size and sector layout are auto-configured by the driver.
6824 Main flash memory is called "Bootflash" and has main region and info region.
6825 Info region is NOT memory mapped by default,
6826 but it can replace first part of main region if needed.
6827 Full erase, single and block writes are supported for both main and info regions.
6828 There is additional not memory mapped flash called "Userflash", which
6829 also have division into regions: main and info.
6830 Purpose of userflash - to store system and user settings.
6831 Driver has special commands to perform operations with this memory.
6834 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6837 Some niietcm4-specific commands are defined:
6839 @deffn {Command} {niietcm4 uflash_read_byte} bank ('main'|'info') address
6840 Read byte from main or info userflash region.
6843 @deffn {Command} {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6844 Write byte to main or info userflash region.
6847 @deffn {Command} {niietcm4 uflash_full_erase} bank
6848 Erase all userflash including info region.
6851 @deffn {Command} {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6852 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6855 @deffn {Command} {niietcm4 uflash_protect_check} bank ('main'|'info')
6856 Check sectors protect.
6859 @deffn {Command} {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6860 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6863 @deffn {Command} {niietcm4 bflash_info_remap} bank ('on'|'off')
6864 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6867 @deffn {Command} {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6868 Configure external memory interface for boot.
6871 @deffn {Command} {niietcm4 service_mode_erase} bank
6872 Perform emergency erase of all flash (bootflash and userflash).
6875 @deffn {Command} {niietcm4 driver_info} bank
6876 Show information about flash driver.
6881 @deffn {Flash Driver} {npcx}
6882 All versions of the NPCX microcontroller families from Nuvoton include internal
6883 flash. The NPCX flash driver supports the NPCX family of devices. The driver
6884 automatically recognizes the specific version's flash parameters and
6885 autoconfigures itself. The flash bank starts at address 0x64000000.
6888 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
6892 @deffn {Flash Driver} {nrf5}
6893 All members of the nRF51 microcontroller families from Nordic Semiconductor
6894 include internal flash and use ARM Cortex-M0 core. nRF52 family powered
6895 by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported
6896 including BPROT flash protection scheme. nRF52833 and nRF52840 devices are
6897 supported with the exception of security extensions (flash access control list
6901 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6904 Some nrf5-specific commands are defined:
6906 @deffn {Command} {nrf5 mass_erase}
6907 Erases the contents of the code memory and user information
6908 configuration registers as well. It must be noted that this command
6909 works only for chips that do not have factory pre-programmed region 0
6913 @deffn {Command} {nrf5 info}
6914 Decodes and shows information from FICR and UICR registers.
6919 @deffn {Flash Driver} {ocl}
6920 This driver is an implementation of the ``on chip flash loader''
6921 protocol proposed by Pavel Chromy.
6923 It is a minimalistic command-response protocol intended to be used
6924 over a DCC when communicating with an internal or external flash
6925 loader running from RAM. An example implementation for AT91SAM7x is
6926 available in @file{contrib/loaders/flash/at91sam7x/}.
6929 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
6933 @deffn {Flash Driver} {pic32mx}
6934 The PIC32MX microcontrollers are based on the MIPS 4K cores,
6935 and integrate flash memory.
6938 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
6939 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
6942 @comment numerous *disabled* commands are defined:
6943 @comment - chip_erase ... pointless given flash_erase_address
6944 @comment - lock, unlock ... pointless given protect on/off (yes?)
6945 @comment - pgm_word ... shouldn't bank be deduced from address??
6946 Some pic32mx-specific commands are defined:
6947 @deffn {Command} {pic32mx pgm_word} address value bank
6948 Programs the specified 32-bit @var{value} at the given @var{address}
6949 in the specified chip @var{bank}.
6951 @deffn {Command} {pic32mx unlock} bank
6952 Unlock and erase specified chip @var{bank}.
6953 This will remove any Code Protection.
6957 @deffn {Flash Driver} {psoc4}
6958 All members of the PSoC 41xx/42xx microcontroller family from Cypress
6959 include internal flash and use ARM Cortex-M0 cores.
6960 The driver automatically recognizes a number of these chips using
6961 the chip identification register, and autoconfigures itself.
6963 Note: Erased internal flash reads as 00.
6964 System ROM of PSoC 4 does not implement erase of a flash sector.
6967 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
6970 psoc4-specific commands
6971 @deffn {Command} {psoc4 flash_autoerase} num (on|off)
6972 Enables or disables autoerase mode for a flash bank.
6974 If flash_autoerase is off, use mass_erase before flash programming.
6975 Flash erase command fails if region to erase is not whole flash memory.
6977 If flash_autoerase is on, a sector is both erased and programmed in one
6978 system ROM call. Flash erase command is ignored.
6979 This mode is suitable for gdb load.
6981 The @var{num} parameter is a value shown by @command{flash banks}.
6984 @deffn {Command} {psoc4 mass_erase} num
6985 Erases the contents of the flash memory, protection and security lock.
6987 The @var{num} parameter is a value shown by @command{flash banks}.
6991 @deffn {Flash Driver} {psoc5lp}
6992 All members of the PSoC 5LP microcontroller family from Cypress
6993 include internal program flash and use ARM Cortex-M3 cores.
6994 The driver probes for a number of these chips and autoconfigures itself,
6995 apart from the base address.
6998 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
7001 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
7002 @quotation Attention
7003 If flash operations are performed in ECC-disabled mode, they will also affect
7004 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
7005 then also erase the corresponding 2k data bytes in the 0x48000000 area.
7006 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
7009 Commands defined in the @var{psoc5lp} driver:
7011 @deffn {Command} {psoc5lp mass_erase}
7012 Erases all flash data and ECC/configuration bytes, all flash protection rows,
7013 and all row latches in all flash arrays on the device.
7017 @deffn {Flash Driver} {psoc5lp_eeprom}
7018 All members of the PSoC 5LP microcontroller family from Cypress
7019 include internal EEPROM and use ARM Cortex-M3 cores.
7020 The driver probes for a number of these chips and autoconfigures itself,
7021 apart from the base address.
7024 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
7029 @deffn {Flash Driver} {psoc5lp_nvl}
7030 All members of the PSoC 5LP microcontroller family from Cypress
7031 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
7032 The driver probes for a number of these chips and autoconfigures itself.
7035 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
7038 PSoC 5LP chips have multiple NV Latches:
7041 @item Device Configuration NV Latch - 4 bytes
7042 @item Write Once (WO) NV Latch - 4 bytes
7045 @b{Note:} This driver only implements the Device Configuration NVL.
7047 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
7048 @quotation Attention
7049 Switching ECC mode via write to Device Configuration NVL will require a reset
7050 after successful write.
7054 @deffn {Flash Driver} {psoc6}
7055 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
7056 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
7057 the same Flash/RAM/MMIO address space.
7059 Flash in PSoC6 is split into three regions:
7061 @item Main Flash - this is the main storage for user application.
7062 Total size varies among devices, sector size: 256 kBytes, row size:
7063 512 bytes. Supports erase operation on individual rows.
7064 @item Work Flash - intended to be used as storage for user data
7065 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
7066 row size: 512 bytes.
7067 @item Supervisory Flash - special region which contains device-specific
7068 service data. This region does not support erase operation. Only few rows can
7069 be programmed by the user, most of the rows are read only. Programming
7070 operation will erase row automatically.
7073 All three flash regions are supported by the driver. Flash geometry is detected
7074 automatically by parsing data in SPCIF_GEOMETRY register.
7076 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
7079 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
7081 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
7083 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
7085 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
7087 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
7089 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
7092 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
7094 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
7096 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
7098 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
7100 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
7102 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
7106 psoc6-specific commands
7107 @deffn {Command} {psoc6 reset_halt}
7108 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
7109 When invoked for CM0+ target, it will set break point at application entry point
7110 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
7111 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
7112 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
7115 @deffn {Command} {psoc6 mass_erase} num
7116 Erases the contents given flash bank. The @var{num} parameter is a value shown
7117 by @command{flash banks}.
7118 Note: only Main and Work flash regions support Erase operation.
7122 @deffn {Flash Driver} {rp2040}
7123 Supports RP2040 "Raspberry Pi Pico" microcontroller.
7124 RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
7125 Flash/RAM/MMIO address space. Non-volatile storage is achieved with an
7126 external QSPI flash; a Boot ROM provides helper functions.
7129 flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
7133 @deffn {Flash Driver} {sim3x}
7134 All members of the SiM3 microcontroller family from Silicon Laboratories
7135 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
7137 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
7138 If this fails, it will use the @var{size} parameter as the size of flash bank.
7141 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
7144 There are 2 commands defined in the @var{sim3x} driver:
7146 @deffn {Command} {sim3x mass_erase}
7147 Erases the complete flash. This is used to unlock the flash.
7148 And this command is only possible when using the SWD interface.
7151 @deffn {Command} {sim3x lock}
7152 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
7156 @deffn {Flash Driver} {stellaris}
7157 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
7158 families from Texas Instruments include internal flash. The driver
7159 automatically recognizes a number of these chips using the chip
7160 identification register, and autoconfigures itself.
7163 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
7166 @deffn {Command} {stellaris recover}
7167 Performs the @emph{Recovering a "Locked" Device} procedure to restore
7168 the flash and its associated nonvolatile registers to their factory
7169 default values (erased). This is the only way to remove flash
7170 protection or re-enable debugging if that capability has been
7173 Note that the final "power cycle the chip" step in this procedure
7174 must be performed by hand, since OpenOCD can't do it.
7176 if more than one Stellaris chip is connected, the procedure is
7177 applied to all of them.
7182 @deffn {Flash Driver} {stm32f1x}
7183 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
7184 from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
7185 families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
7186 The driver automatically recognizes a number of these chips using
7187 the chip identification register, and autoconfigures itself.
7190 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
7193 Note that some devices have been found that have a flash size register that contains
7194 an invalid value, to workaround this issue you can override the probed value used by
7198 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
7201 If you have a target with dual flash banks then define the second bank
7202 as per the following example.
7204 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
7207 Some stm32f1x-specific commands are defined:
7209 @deffn {Command} {stm32f1x lock} num
7210 Locks the entire stm32 device against reading.
7211 The @var{num} parameter is a value shown by @command{flash banks}.
7214 @deffn {Command} {stm32f1x unlock} num
7215 Unlocks the entire stm32 device for reading. This command will cause
7216 a mass erase of the entire stm32 device if previously locked.
7217 The @var{num} parameter is a value shown by @command{flash banks}.
7220 @deffn {Command} {stm32f1x mass_erase} num
7221 Mass erases the entire stm32 device.
7222 The @var{num} parameter is a value shown by @command{flash banks}.
7225 @deffn {Command} {stm32f1x options_read} num
7226 Reads and displays active stm32 option bytes loaded during POR
7227 or upon executing the @command{stm32f1x options_load} command.
7228 The @var{num} parameter is a value shown by @command{flash banks}.
7231 @deffn {Command} {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
7232 Writes the stm32 option byte with the specified values.
7233 The @var{num} parameter is a value shown by @command{flash banks}.
7234 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
7237 @deffn {Command} {stm32f1x options_load} num
7238 Generates a special kind of reset to re-load the stm32 option bytes written
7239 by the @command{stm32f1x options_write} or @command{flash protect} commands
7240 without having to power cycle the target. Not applicable to stm32f1x devices.
7241 The @var{num} parameter is a value shown by @command{flash banks}.
7245 @deffn {Flash Driver} {stm32f2x}
7246 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
7247 include internal flash and use ARM Cortex-M3/M4/M7 cores.
7248 The driver automatically recognizes a number of these chips using
7249 the chip identification register, and autoconfigures itself.
7252 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
7255 If you use OTP (One-Time Programmable) memory define it as a second bank
7256 as per the following example.
7258 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
7261 @deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
7262 Enables or disables OTP write commands for bank @var{num}.
7263 The @var{num} parameter is a value shown by @command{flash banks}.
7266 Note that some devices have been found that have a flash size register that contains
7267 an invalid value, to workaround this issue you can override the probed value used by
7271 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
7274 Some stm32f2x-specific commands are defined:
7276 @deffn {Command} {stm32f2x lock} num
7277 Locks the entire stm32 device.
7278 The @var{num} parameter is a value shown by @command{flash banks}.
7281 @deffn {Command} {stm32f2x unlock} num
7282 Unlocks the entire stm32 device.
7283 The @var{num} parameter is a value shown by @command{flash banks}.
7286 @deffn {Command} {stm32f2x mass_erase} num
7287 Mass erases the entire stm32f2x device.
7288 The @var{num} parameter is a value shown by @command{flash banks}.
7291 @deffn {Command} {stm32f2x options_read} num
7292 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
7293 The @var{num} parameter is a value shown by @command{flash banks}.
7296 @deffn {Command} {stm32f2x options_write} num user_options boot_addr0 boot_addr1
7297 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
7298 Warning: The meaning of the various bits depends on the device, always check datasheet!
7299 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
7300 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
7301 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
7304 @deffn {Command} {stm32f2x optcr2_write} num optcr2
7305 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
7306 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
7310 @deffn {Flash Driver} {stm32h7x}
7311 All members of the STM32H7 microcontroller families from STMicroelectronics
7312 include internal flash and use ARM Cortex-M7 core.
7313 The driver automatically recognizes a number of these chips using
7314 the chip identification register, and autoconfigures itself.
7317 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
7320 Note that some devices have been found that have a flash size register that contains
7321 an invalid value, to workaround this issue you can override the probed value used by
7325 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
7328 Some stm32h7x-specific commands are defined:
7330 @deffn {Command} {stm32h7x lock} num
7331 Locks the entire stm32 device.
7332 The @var{num} parameter is a value shown by @command{flash banks}.
7335 @deffn {Command} {stm32h7x unlock} num
7336 Unlocks the entire stm32 device.
7337 The @var{num} parameter is a value shown by @command{flash banks}.
7340 @deffn {Command} {stm32h7x mass_erase} num
7341 Mass erases the entire stm32h7x device.
7342 The @var{num} parameter is a value shown by @command{flash banks}.
7345 @deffn {Command} {stm32h7x option_read} num reg_offset
7346 Reads an option byte register from the stm32h7x device.
7347 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7348 is the register offset of the option byte to read from the used bank registers' base.
7349 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
7354 stm32h7x option_read 0 0x1c
7356 stm32h7x option_read 0 0x38
7358 stm32h7x option_read 1 0x38
7362 @deffn {Command} {stm32h7x option_write} num reg_offset value [reg_mask]
7363 Writes an option byte register of the stm32h7x device.
7364 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7365 is the register offset of the option byte to write from the used bank register base,
7366 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
7371 # swap bank 1 and bank 2 in dual bank devices
7372 # by setting SWAP_BANK_OPT bit in OPTSR_PRG
7373 stm32h7x option_write 0 0x20 0x8000000 0x8000000
7378 @deffn {Flash Driver} {stm32lx}
7379 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
7380 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
7381 The driver automatically recognizes a number of these chips using
7382 the chip identification register, and autoconfigures itself.
7385 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
7388 Note that some devices have been found that have a flash size register that contains
7389 an invalid value, to workaround this issue you can override the probed value used by
7390 the flash driver. If you use 0 as the bank base address, it tells the
7391 driver to autodetect the bank location assuming you're configuring the
7395 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
7398 Some stm32lx-specific commands are defined:
7400 @deffn {Command} {stm32lx lock} num
7401 Locks the entire stm32 device.
7402 The @var{num} parameter is a value shown by @command{flash banks}.
7405 @deffn {Command} {stm32lx unlock} num
7406 Unlocks the entire stm32 device.
7407 The @var{num} parameter is a value shown by @command{flash banks}.
7410 @deffn {Command} {stm32lx mass_erase} num
7411 Mass erases the entire stm32lx device (all flash banks and EEPROM
7412 data). This is the only way to unlock a protected flash (unless RDP
7413 Level is 2 which can't be unlocked at all).
7414 The @var{num} parameter is a value shown by @command{flash banks}.
7418 @deffn {Flash Driver} {stm32l4x}
7419 All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
7420 microcontroller families from STMicroelectronics include internal flash
7421 and use ARM Cortex-M0+, M4 and M33 cores.
7422 The driver automatically recognizes a number of these chips using
7423 the chip identification register, and autoconfigures itself.
7426 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7429 If you use OTP (One-Time Programmable) memory define it as a second bank
7430 as per the following example.
7432 flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
7435 @deffn {Command} {stm32l4x otp} num (@option{enable}|@option{disable}|@option{show})
7436 Enables or disables OTP write commands for bank @var{num}.
7437 The @var{num} parameter is a value shown by @command{flash banks}.
7440 Note that some devices have been found that have a flash size register that contains
7441 an invalid value, to workaround this issue you can override the probed value used by
7442 the flash driver. However, specifying a wrong value might lead to a completely
7443 wrong flash layout, so this feature must be used carefully.
7446 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7449 Some stm32l4x-specific commands are defined:
7451 @deffn {Command} {stm32l4x lock} num
7452 Locks the entire stm32 device.
7453 The @var{num} parameter is a value shown by @command{flash banks}.
7455 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7458 @deffn {Command} {stm32l4x unlock} num
7459 Unlocks the entire stm32 device.
7460 The @var{num} parameter is a value shown by @command{flash banks}.
7462 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7465 @deffn {Command} {stm32l4x mass_erase} num
7466 Mass erases the entire stm32l4x device.
7467 The @var{num} parameter is a value shown by @command{flash banks}.
7470 @deffn {Command} {stm32l4x option_read} num reg_offset
7471 Reads an option byte register from the stm32l4x device.
7472 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7473 is the register offset of the Option byte to read.
7475 For example to read the FLASH_OPTR register:
7477 stm32l4x option_read 0 0x20
7478 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
7479 # Option Register (for STM32WBx): <0x58004020> = ...
7480 # The correct flash base address will be used automatically
7483 The above example will read out the FLASH_OPTR register which contains the RDP
7484 option byte, Watchdog configuration, BOR level etc.
7487 @deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
7488 Write an option byte register of the stm32l4x device.
7489 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7490 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
7491 to apply when writing the register (only bits with a '1' will be touched).
7493 @emph{Note:} To apply the option bytes change immediately, use @command{stm32l4x option_load}.
7495 For example to write the WRP1AR option bytes:
7497 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
7500 The above example will write the WRP1AR option register configuring the Write protection
7501 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
7502 This will effectively write protect all sectors in flash bank 1.
7505 @deffn {Command} {stm32l4x wrp_info} num [device_bank]
7506 List the protected areas using WRP.
7507 The @var{num} parameter is a value shown by @command{flash banks}.
7508 @var{device_bank} parameter is optional, possible values 'bank1' or 'bank2',
7509 if not specified, the command will display the whole flash protected areas.
7511 @b{Note:} @var{device_bank} is different from banks created using @code{flash bank}.
7512 Devices supported in this flash driver, can have main flash memory organized
7513 in single or dual-banks mode.
7514 Thus the usage of @var{device_bank} is meaningful only in dual-bank mode, to get
7515 write protected areas in a specific @var{device_bank}
7519 @deffn {Command} {stm32l4x option_load} num
7520 Forces a re-load of the option byte registers. Will cause a system reset of the device.
7521 The @var{num} parameter is a value shown by @command{flash banks}.
7524 @deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
7525 Enables or disables Global TrustZone Security, using the TZEN option bit.
7526 If neither @option{enabled} nor @option{disable} are specified, the command will display
7527 the TrustZone status.
7528 @emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
7529 @emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
7533 @deffn {Flash Driver} {str7x}
7534 All members of the STR7 microcontroller family from STMicroelectronics
7535 include internal flash and use ARM7TDMI cores.
7536 The @var{str7x} driver defines one mandatory parameter, @var{variant},
7537 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
7540 flash bank $_FLASHNAME str7x \
7541 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
7544 @deffn {Command} {str7x disable_jtag} bank
7545 Activate the Debug/Readout protection mechanism
7546 for the specified flash bank.
7550 @deffn {Flash Driver} {str9x}
7551 Most members of the STR9 microcontroller family from STMicroelectronics
7552 include internal flash and use ARM966E cores.
7553 The str9 needs the flash controller to be configured using
7554 the @command{str9x flash_config} command prior to Flash programming.
7557 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
7558 str9x flash_config 0 4 2 0 0x80000
7561 @deffn {Command} {str9x flash_config} num bbsr nbbsr bbadr nbbadr
7562 Configures the str9 flash controller.
7563 The @var{num} parameter is a value shown by @command{flash banks}.
7566 @item @var{bbsr} - Boot Bank Size register
7567 @item @var{nbbsr} - Non Boot Bank Size register
7568 @item @var{bbadr} - Boot Bank Start Address register
7569 @item @var{nbbadr} - Boot Bank Start Address register
7575 @deffn {Flash Driver} {str9xpec}
7578 Only use this driver for locking/unlocking the device or configuring the option bytes.
7579 Use the standard str9 driver for programming.
7580 Before using the flash commands the turbo mode must be enabled using the
7581 @command{str9xpec enable_turbo} command.
7583 Here is some background info to help
7584 you better understand how this driver works. OpenOCD has two flash drivers for
7588 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7589 flash programming as it is faster than the @option{str9xpec} driver.
7591 Direct programming @option{str9xpec} using the flash controller. This is an
7592 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7593 core does not need to be running to program using this flash driver. Typical use
7594 for this driver is locking/unlocking the target and programming the option bytes.
7597 Before we run any commands using the @option{str9xpec} driver we must first disable
7598 the str9 core. This example assumes the @option{str9xpec} driver has been
7599 configured for flash bank 0.
7601 # assert srst, we do not want core running
7602 # while accessing str9xpec flash driver
7604 # turn off target polling
7607 str9xpec enable_turbo 0
7609 str9xpec options_read 0
7610 # re-enable str9 core
7611 str9xpec disable_turbo 0
7615 The above example will read the str9 option bytes.
7616 When performing a unlock remember that you will not be able to halt the str9 - it
7617 has been locked. Halting the core is not required for the @option{str9xpec} driver
7618 as mentioned above, just issue the commands above manually or from a telnet prompt.
7620 Several str9xpec-specific commands are defined:
7622 @deffn {Command} {str9xpec disable_turbo} num
7623 Restore the str9 into JTAG chain.
7626 @deffn {Command} {str9xpec enable_turbo} num
7627 Enable turbo mode, will simply remove the str9 from the chain and talk
7628 directly to the embedded flash controller.
7631 @deffn {Command} {str9xpec lock} num
7632 Lock str9 device. The str9 will only respond to an unlock command that will
7636 @deffn {Command} {str9xpec part_id} num
7637 Prints the part identifier for bank @var{num}.
7640 @deffn {Command} {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7641 Configure str9 boot bank.
7644 @deffn {Command} {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
7645 Configure str9 lvd source.
7648 @deffn {Command} {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
7649 Configure str9 lvd threshold.
7652 @deffn {Command} {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
7653 Configure str9 lvd reset warning source.
7656 @deffn {Command} {str9xpec options_read} num
7657 Read str9 option bytes.
7660 @deffn {Command} {str9xpec options_write} num
7661 Write str9 option bytes.
7664 @deffn {Command} {str9xpec unlock} num
7670 @deffn {Flash Driver} {swm050}
7672 All members of the swm050 microcontroller family from Foshan Synwit Tech.
7675 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
7678 One swm050-specific command is defined:
7680 @deffn {Command} {swm050 mass_erase} bank_id
7681 Erases the entire flash bank.
7687 @deffn {Flash Driver} {tms470}
7688 Most members of the TMS470 microcontroller family from Texas Instruments
7689 include internal flash and use ARM7TDMI cores.
7690 This driver doesn't require the chip and bus width to be specified.
7692 Some tms470-specific commands are defined:
7694 @deffn {Command} {tms470 flash_keyset} key0 key1 key2 key3
7695 Saves programming keys in a register, to enable flash erase and write commands.
7698 @deffn {Command} {tms470 osc_megahertz} clock_mhz
7699 Reports the clock speed, which is used to calculate timings.
7702 @deffn {Command} {tms470 plldis} (0|1)
7703 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
7708 @deffn {Flash Driver} {w600}
7709 W60x series Wi-Fi SoC from WinnerMicro
7710 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
7711 The @var{w600} driver uses the @var{target} parameter to select the
7712 correct bank config.
7715 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
7719 @deffn {Flash Driver} {xmc1xxx}
7720 All members of the XMC1xxx microcontroller family from Infineon.
7721 This driver does not require the chip and bus width to be specified.
7724 @deffn {Flash Driver} {xmc4xxx}
7725 All members of the XMC4xxx microcontroller family from Infineon.
7726 This driver does not require the chip and bus width to be specified.
7728 Some xmc4xxx-specific commands are defined:
7730 @deffn {Command} {xmc4xxx flash_password} bank_id passwd1 passwd2
7731 Saves flash protection passwords which are used to lock the user flash
7734 @deffn {Command} {xmc4xxx flash_unprotect} bank_id user_level[0-1]
7735 Removes Flash write protection from the selected user bank
7740 @section NAND Flash Commands
7743 Compared to NOR or SPI flash, NAND devices are inexpensive
7744 and high density. Today's NAND chips, and multi-chip modules,
7745 commonly hold multiple GigaBytes of data.
7747 NAND chips consist of a number of ``erase blocks'' of a given
7748 size (such as 128 KBytes), each of which is divided into a
7749 number of pages (of perhaps 512 or 2048 bytes each). Each
7750 page of a NAND flash has an ``out of band'' (OOB) area to hold
7751 Error Correcting Code (ECC) and other metadata, usually 16 bytes
7752 of OOB for every 512 bytes of page data.
7754 One key characteristic of NAND flash is that its error rate
7755 is higher than that of NOR flash. In normal operation, that
7756 ECC is used to correct and detect errors. However, NAND
7757 blocks can also wear out and become unusable; those blocks
7758 are then marked "bad". NAND chips are even shipped from the
7759 manufacturer with a few bad blocks. The highest density chips
7760 use a technology (MLC) that wears out more quickly, so ECC
7761 support is increasingly important as a way to detect blocks
7762 that have begun to fail, and help to preserve data integrity
7763 with techniques such as wear leveling.
7765 Software is used to manage the ECC. Some controllers don't
7766 support ECC directly; in those cases, software ECC is used.
7767 Other controllers speed up the ECC calculations with hardware.
7768 Single-bit error correction hardware is routine. Controllers
7769 geared for newer MLC chips may correct 4 or more errors for
7770 every 512 bytes of data.
7772 You will need to make sure that any data you write using
7773 OpenOCD includes the appropriate kind of ECC. For example,
7774 that may mean passing the @code{oob_softecc} flag when
7775 writing NAND data, or ensuring that the correct hardware
7778 The basic steps for using NAND devices include:
7780 @item Declare via the command @command{nand device}
7781 @* Do this in a board-specific configuration file,
7782 passing parameters as needed by the controller.
7783 @item Configure each device using @command{nand probe}.
7784 @* Do this only after the associated target is set up,
7785 such as in its reset-init script or in procures defined
7786 to access that device.
7787 @item Operate on the flash via @command{nand subcommand}
7788 @* Often commands to manipulate the flash are typed by a human, or run
7789 via a script in some automated way. Common task include writing a
7790 boot loader, operating system, or other data needed to initialize or
7794 @b{NOTE:} At the time this text was written, the largest NAND
7795 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
7796 This is because the variables used to hold offsets and lengths
7797 are only 32 bits wide.
7798 (Larger chips may work in some cases, unless an offset or length
7799 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
7800 Some larger devices will work, since they are actually multi-chip
7801 modules with two smaller chips and individual chipselect lines.
7803 @anchor{nandconfiguration}
7804 @subsection NAND Configuration Commands
7805 @cindex NAND configuration
7807 NAND chips must be declared in configuration scripts,
7808 plus some additional configuration that's done after
7809 OpenOCD has initialized.
7811 @deffn {Config Command} {nand device} name driver target [configparams...]
7812 Declares a NAND device, which can be read and written to
7813 after it has been configured through @command{nand probe}.
7814 In OpenOCD, devices are single chips; this is unlike some
7815 operating systems, which may manage multiple chips as if
7816 they were a single (larger) device.
7817 In some cases, configuring a device will activate extra
7818 commands; see the controller-specific documentation.
7820 @b{NOTE:} This command is not available after OpenOCD
7821 initialization has completed. Use it in board specific
7822 configuration files, not interactively.
7825 @item @var{name} ... may be used to reference the NAND bank
7826 in most other NAND commands. A number is also available.
7827 @item @var{driver} ... identifies the NAND controller driver
7828 associated with the NAND device being declared.
7829 @xref{nanddriverlist,,NAND Driver List}.
7830 @item @var{target} ... names the target used when issuing
7831 commands to the NAND controller.
7832 @comment Actually, it's currently a controller-specific parameter...
7833 @item @var{configparams} ... controllers may support, or require,
7834 additional parameters. See the controller-specific documentation
7835 for more information.
7839 @deffn {Command} {nand list}
7840 Prints a summary of each device declared
7841 using @command{nand device}, numbered from zero.
7842 Note that un-probed devices show no details.
7845 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7846 blocksize: 131072, blocks: 8192
7847 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7848 blocksize: 131072, blocks: 8192
7853 @deffn {Command} {nand probe} num
7854 Probes the specified device to determine key characteristics
7855 like its page and block sizes, and how many blocks it has.
7856 The @var{num} parameter is the value shown by @command{nand list}.
7857 You must (successfully) probe a device before you can use
7858 it with most other NAND commands.
7861 @subsection Erasing, Reading, Writing to NAND Flash
7863 @deffn {Command} {nand dump} num filename offset length [oob_option]
7864 @cindex NAND reading
7865 Reads binary data from the NAND device and writes it to the file,
7866 starting at the specified offset.
7867 The @var{num} parameter is the value shown by @command{nand list}.
7869 Use a complete path name for @var{filename}, so you don't depend
7870 on the directory used to start the OpenOCD server.
7872 The @var{offset} and @var{length} must be exact multiples of the
7873 device's page size. They describe a data region; the OOB data
7874 associated with each such page may also be accessed.
7876 @b{NOTE:} At the time this text was written, no error correction
7877 was done on the data that's read, unless raw access was disabled
7878 and the underlying NAND controller driver had a @code{read_page}
7879 method which handled that error correction.
7881 By default, only page data is saved to the specified file.
7882 Use an @var{oob_option} parameter to save OOB data:
7884 @item no oob_* parameter
7885 @*Output file holds only page data; OOB is discarded.
7886 @item @code{oob_raw}
7887 @*Output file interleaves page data and OOB data;
7888 the file will be longer than "length" by the size of the
7889 spare areas associated with each data page.
7890 Note that this kind of "raw" access is different from
7891 what's implied by @command{nand raw_access}, which just
7892 controls whether a hardware-aware access method is used.
7893 @item @code{oob_only}
7894 @*Output file has only raw OOB data, and will
7895 be smaller than "length" since it will contain only the
7896 spare areas associated with each data page.
7900 @deffn {Command} {nand erase} num [offset length]
7901 @cindex NAND erasing
7902 @cindex NAND programming
7903 Erases blocks on the specified NAND device, starting at the
7904 specified @var{offset} and continuing for @var{length} bytes.
7905 Both of those values must be exact multiples of the device's
7906 block size, and the region they specify must fit entirely in the chip.
7907 If those parameters are not specified,
7908 the whole NAND chip will be erased.
7909 The @var{num} parameter is the value shown by @command{nand list}.
7911 @b{NOTE:} This command will try to erase bad blocks, when told
7912 to do so, which will probably invalidate the manufacturer's bad
7914 For the remainder of the current server session, @command{nand info}
7915 will still report that the block ``is'' bad.
7918 @deffn {Command} {nand write} num filename offset [option...]
7919 @cindex NAND writing
7920 @cindex NAND programming
7921 Writes binary data from the file into the specified NAND device,
7922 starting at the specified offset. Those pages should already
7923 have been erased; you can't change zero bits to one bits.
7924 The @var{num} parameter is the value shown by @command{nand list}.
7926 Use a complete path name for @var{filename}, so you don't depend
7927 on the directory used to start the OpenOCD server.
7929 The @var{offset} must be an exact multiple of the device's page size.
7930 All data in the file will be written, assuming it doesn't run
7931 past the end of the device.
7932 Only full pages are written, and any extra space in the last
7933 page will be filled with 0xff bytes. (That includes OOB data,
7934 if that's being written.)
7936 @b{NOTE:} At the time this text was written, bad blocks are
7937 ignored. That is, this routine will not skip bad blocks,
7938 but will instead try to write them. This can cause problems.
7940 Provide at most one @var{option} parameter. With some
7941 NAND drivers, the meanings of these parameters may change
7942 if @command{nand raw_access} was used to disable hardware ECC.
7944 @item no oob_* parameter
7945 @*File has only page data, which is written.
7946 If raw access is in use, the OOB area will not be written.
7947 Otherwise, if the underlying NAND controller driver has
7948 a @code{write_page} routine, that routine may write the OOB
7949 with hardware-computed ECC data.
7950 @item @code{oob_only}
7951 @*File has only raw OOB data, which is written to the OOB area.
7952 Each page's data area stays untouched. @i{This can be a dangerous
7953 option}, since it can invalidate the ECC data.
7954 You may need to force raw access to use this mode.
7955 @item @code{oob_raw}
7956 @*File interleaves data and OOB data, both of which are written
7957 If raw access is enabled, the data is written first, then the
7959 Otherwise, if the underlying NAND controller driver has
7960 a @code{write_page} routine, that routine may modify the OOB
7961 before it's written, to include hardware-computed ECC data.
7962 @item @code{oob_softecc}
7963 @*File has only page data, which is written.
7964 The OOB area is filled with 0xff, except for a standard 1-bit
7965 software ECC code stored in conventional locations.
7966 You might need to force raw access to use this mode, to prevent
7967 the underlying driver from applying hardware ECC.
7968 @item @code{oob_softecc_kw}
7969 @*File has only page data, which is written.
7970 The OOB area is filled with 0xff, except for a 4-bit software ECC
7971 specific to the boot ROM in Marvell Kirkwood SoCs.
7972 You might need to force raw access to use this mode, to prevent
7973 the underlying driver from applying hardware ECC.
7977 @deffn {Command} {nand verify} num filename offset [option...]
7978 @cindex NAND verification
7979 @cindex NAND programming
7980 Verify the binary data in the file has been programmed to the
7981 specified NAND device, starting at the specified offset.
7982 The @var{num} parameter is the value shown by @command{nand list}.
7984 Use a complete path name for @var{filename}, so you don't depend
7985 on the directory used to start the OpenOCD server.
7987 The @var{offset} must be an exact multiple of the device's page size.
7988 All data in the file will be read and compared to the contents of the
7989 flash, assuming it doesn't run past the end of the device.
7990 As with @command{nand write}, only full pages are verified, so any extra
7991 space in the last page will be filled with 0xff bytes.
7993 The same @var{options} accepted by @command{nand write},
7994 and the file will be processed similarly to produce the buffers that
7995 can be compared against the contents produced from @command{nand dump}.
7997 @b{NOTE:} This will not work when the underlying NAND controller
7998 driver's @code{write_page} routine must update the OOB with a
7999 hardware-computed ECC before the data is written. This limitation may
8000 be removed in a future release.
8003 @subsection Other NAND commands
8004 @cindex NAND other commands
8006 @deffn {Command} {nand check_bad_blocks} num [offset length]
8007 Checks for manufacturer bad block markers on the specified NAND
8008 device. If no parameters are provided, checks the whole
8009 device; otherwise, starts at the specified @var{offset} and
8010 continues for @var{length} bytes.
8011 Both of those values must be exact multiples of the device's
8012 block size, and the region they specify must fit entirely in the chip.
8013 The @var{num} parameter is the value shown by @command{nand list}.
8015 @b{NOTE:} Before using this command you should force raw access
8016 with @command{nand raw_access enable} to ensure that the underlying
8017 driver will not try to apply hardware ECC.
8020 @deffn {Command} {nand info} num
8021 The @var{num} parameter is the value shown by @command{nand list}.
8022 This prints the one-line summary from "nand list", plus for
8023 devices which have been probed this also prints any known
8024 status for each block.
8027 @deffn {Command} {nand raw_access} num (@option{enable}|@option{disable})
8028 Sets or clears an flag affecting how page I/O is done.
8029 The @var{num} parameter is the value shown by @command{nand list}.
8031 This flag is cleared (disabled) by default, but changing that
8032 value won't affect all NAND devices. The key factor is whether
8033 the underlying driver provides @code{read_page} or @code{write_page}
8034 methods. If it doesn't provide those methods, the setting of
8035 this flag is irrelevant; all access is effectively ``raw''.
8037 When those methods exist, they are normally used when reading
8038 data (@command{nand dump} or reading bad block markers) or
8039 writing it (@command{nand write}). However, enabling
8040 raw access (setting the flag) prevents use of those methods,
8041 bypassing hardware ECC logic.
8042 @i{This can be a dangerous option}, since writing blocks
8043 with the wrong ECC data can cause them to be marked as bad.
8046 @anchor{nanddriverlist}
8047 @subsection NAND Driver List
8048 As noted above, the @command{nand device} command allows
8049 driver-specific options and behaviors.
8050 Some controllers also activate controller-specific commands.
8052 @deffn {NAND Driver} {at91sam9}
8053 This driver handles the NAND controllers found on AT91SAM9 family chips from
8054 Atmel. It takes two extra parameters: address of the NAND chip;
8055 address of the ECC controller.
8057 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
8059 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
8060 @code{read_page} methods are used to utilize the ECC hardware unless they are
8061 disabled by using the @command{nand raw_access} command. There are four
8062 additional commands that are needed to fully configure the AT91SAM9 NAND
8063 controller. Two are optional; most boards use the same wiring for ALE/CLE:
8064 @deffn {Config Command} {at91sam9 cle} num addr_line
8065 Configure the address line used for latching commands. The @var{num}
8066 parameter is the value shown by @command{nand list}.
8068 @deffn {Config Command} {at91sam9 ale} num addr_line
8069 Configure the address line used for latching addresses. The @var{num}
8070 parameter is the value shown by @command{nand list}.
8073 For the next two commands, it is assumed that the pins have already been
8074 properly configured for input or output.
8075 @deffn {Config Command} {at91sam9 rdy_busy} num pio_base_addr pin
8076 Configure the RDY/nBUSY input from the NAND device. The @var{num}
8077 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8078 is the base address of the PIO controller and @var{pin} is the pin number.
8080 @deffn {Config Command} {at91sam9 ce} num pio_base_addr pin
8081 Configure the chip enable input to the NAND device. The @var{num}
8082 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8083 is the base address of the PIO controller and @var{pin} is the pin number.
8087 @deffn {NAND Driver} {davinci}
8088 This driver handles the NAND controllers found on DaVinci family
8089 chips from Texas Instruments.
8090 It takes three extra parameters:
8091 address of the NAND chip;
8092 hardware ECC mode to use (@option{hwecc1},
8093 @option{hwecc4}, @option{hwecc4_infix});
8094 address of the AEMIF controller on this processor.
8096 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
8098 All DaVinci processors support the single-bit ECC hardware,
8099 and newer ones also support the four-bit ECC hardware.
8100 The @code{write_page} and @code{read_page} methods are used
8101 to implement those ECC modes, unless they are disabled using
8102 the @command{nand raw_access} command.
8105 @deffn {NAND Driver} {lpc3180}
8106 These controllers require an extra @command{nand device}
8107 parameter: the clock rate used by the controller.
8108 @deffn {Command} {lpc3180 select} num [mlc|slc]
8109 Configures use of the MLC or SLC controller mode.
8110 MLC implies use of hardware ECC.
8111 The @var{num} parameter is the value shown by @command{nand list}.
8114 At this writing, this driver includes @code{write_page}
8115 and @code{read_page} methods. Using @command{nand raw_access}
8116 to disable those methods will prevent use of hardware ECC
8117 in the MLC controller mode, but won't change SLC behavior.
8119 @comment current lpc3180 code won't issue 5-byte address cycles
8121 @deffn {NAND Driver} {mx3}
8122 This driver handles the NAND controller in i.MX31. The mxc driver
8123 should work for this chip as well.
8126 @deffn {NAND Driver} {mxc}
8127 This driver handles the NAND controller found in Freescale i.MX
8128 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
8129 The driver takes 3 extra arguments, chip (@option{mx27},
8130 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
8131 and optionally if bad block information should be swapped between
8132 main area and spare area (@option{biswap}), defaults to off.
8134 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
8136 @deffn {Command} {mxc biswap} bank_num [enable|disable]
8137 Turns on/off bad block information swapping from main area,
8138 without parameter query status.
8142 @deffn {NAND Driver} {orion}
8143 These controllers require an extra @command{nand device}
8144 parameter: the address of the controller.
8146 nand device orion 0xd8000000
8148 These controllers don't define any specialized commands.
8149 At this writing, their drivers don't include @code{write_page}
8150 or @code{read_page} methods, so @command{nand raw_access} won't
8151 change any behavior.
8154 @deffn {NAND Driver} {s3c2410}
8155 @deffnx {NAND Driver} {s3c2412}
8156 @deffnx {NAND Driver} {s3c2440}
8157 @deffnx {NAND Driver} {s3c2443}
8158 @deffnx {NAND Driver} {s3c6400}
8159 These S3C family controllers don't have any special
8160 @command{nand device} options, and don't define any
8161 specialized commands.
8162 At this writing, their drivers don't include @code{write_page}
8163 or @code{read_page} methods, so @command{nand raw_access} won't
8164 change any behavior.
8167 @node Flash Programming
8168 @chapter Flash Programming
8170 OpenOCD implements numerous ways to program the target flash, whether internal or external.
8171 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
8172 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
8174 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
8175 OpenOCD will program/verify/reset the target and optionally shutdown.
8177 The script is executed as follows and by default the following actions will be performed.
8179 @item 'init' is executed.
8180 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
8181 @item @code{flash write_image} is called to erase and write any flash using the filename given.
8182 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
8183 @item @code{verify_image} is called if @option{verify} parameter is given.
8184 @item @code{reset run} is called if @option{reset} parameter is given.
8185 @item OpenOCD is shutdown if @option{exit} parameter is given.
8188 An example of usage is given below. @xref{program}.
8191 # program and verify using elf/hex/s19. verify and reset
8192 # are optional parameters
8193 openocd -f board/stm32f3discovery.cfg \
8194 -c "program filename.elf verify reset exit"
8196 # binary files need the flash address passing
8197 openocd -f board/stm32f3discovery.cfg \
8198 -c "program filename.bin exit 0x08000000"
8201 @node PLD/FPGA Commands
8202 @chapter PLD/FPGA Commands
8206 Programmable Logic Devices (PLDs) and the more flexible
8207 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
8208 OpenOCD can support programming them.
8209 Although PLDs are generally restrictive (cells are less functional, and
8210 there are no special purpose cells for memory or computational tasks),
8211 they share the same OpenOCD infrastructure.
8212 Accordingly, both are called PLDs here.
8214 @section PLD/FPGA Configuration and Commands
8216 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
8217 OpenOCD maintains a list of PLDs available for use in various commands.
8218 Also, each such PLD requires a driver.
8220 They are referenced by the number shown by the @command{pld devices} command,
8221 and new PLDs are defined by @command{pld device driver_name}.
8223 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
8224 Defines a new PLD device, supported by driver @var{driver_name},
8225 using the TAP named @var{tap_name}.
8226 The driver may make use of any @var{driver_options} to configure its
8230 @deffn {Command} {pld devices}
8231 Lists the PLDs and their numbers.
8234 @deffn {Command} {pld load} num filename
8235 Loads the file @file{filename} into the PLD identified by @var{num}.
8236 The file format must be inferred by the driver.
8239 @section PLD/FPGA Drivers, Options, and Commands
8241 Drivers may support PLD-specific options to the @command{pld device}
8242 definition command, and may also define commands usable only with
8243 that particular type of PLD.
8245 @deffn {FPGA Driver} {virtex2} [no_jstart]
8246 Virtex-II is a family of FPGAs sold by Xilinx.
8247 It supports the IEEE 1532 standard for In-System Configuration (ISC).
8249 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
8250 loading the bitstream. While required for Series2, Series3, and Series6, it
8251 breaks bitstream loading on Series7.
8253 @deffn {Command} {virtex2 read_stat} num
8254 Reads and displays the Virtex-II status register (STAT)
8259 @node General Commands
8260 @chapter General Commands
8263 The commands documented in this chapter here are common commands that
8264 you, as a human, may want to type and see the output of. Configuration type
8265 commands are documented elsewhere.
8269 @item @b{Source Of Commands}
8270 @* OpenOCD commands can occur in a configuration script (discussed
8271 elsewhere) or typed manually by a human or supplied programmatically,
8272 or via one of several TCP/IP Ports.
8274 @item @b{From the human}
8275 @* A human should interact with the telnet interface (default port: 4444)
8276 or via GDB (default port 3333).
8278 To issue commands from within a GDB session, use the @option{monitor}
8279 command, e.g. use @option{monitor poll} to issue the @option{poll}
8280 command. All output is relayed through the GDB session.
8282 @item @b{Machine Interface}
8283 The Tcl interface's intent is to be a machine interface. The default Tcl
8288 @section Server Commands
8290 @deffn {Command} {exit}
8291 Exits the current telnet session.
8294 @deffn {Command} {help} [string]
8295 With no parameters, prints help text for all commands.
8296 Otherwise, prints each helptext containing @var{string}.
8297 Not every command provides helptext.
8299 Configuration commands, and commands valid at any time, are
8300 explicitly noted in parenthesis.
8301 In most cases, no such restriction is listed; this indicates commands
8302 which are only available after the configuration stage has completed.
8305 @deffn {Command} {usage} [string]
8306 With no parameters, prints usage text for all commands. Otherwise,
8307 prints all usage text of which command, help text, and usage text
8308 containing @var{string}.
8309 Not every command provides helptext.
8312 @deffn {Command} {sleep} msec [@option{busy}]
8313 Wait for at least @var{msec} milliseconds before resuming.
8314 If @option{busy} is passed, busy-wait instead of sleeping.
8315 (This option is strongly discouraged.)
8316 Useful in connection with script files
8317 (@command{script} command and @command{target_name} configuration).
8320 @deffn {Command} {shutdown} [@option{error}]
8321 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
8322 other). If option @option{error} is used, OpenOCD will return a
8323 non-zero exit code to the parent process.
8325 Like any TCL commands, also @command{shutdown} can be redefined, e.g.:
8328 rename shutdown original_shutdown
8329 proc shutdown @{@} @{
8330 puts "This is my implementation of shutdown"
8331 # my own stuff before exit OpenOCD
8335 If user types CTRL-C or kills OpenOCD, either the command @command{shutdown}
8336 or its replacement will be automatically executed before OpenOCD exits.
8340 @deffn {Command} {debug_level} [n]
8341 @cindex message level
8342 Display debug level.
8343 If @var{n} (from 0..4) is provided, then set it to that level.
8344 This affects the kind of messages sent to the server log.
8345 Level 0 is error messages only;
8346 level 1 adds warnings;
8347 level 2 adds informational messages;
8348 level 3 adds debugging messages;
8349 and level 4 adds verbose low-level debug messages.
8350 The default is level 2, but that can be overridden on
8351 the command line along with the location of that log
8352 file (which is normally the server's standard output).
8356 @deffn {Command} {echo} [-n] message
8357 Logs a message at "user" priority.
8358 Option "-n" suppresses trailing newline.
8360 echo "Downloading kernel -- please wait"
8364 @deffn {Command} {log_output} [filename | "default"]
8365 Redirect logging to @var{filename} or set it back to default output;
8366 the default log output channel is stderr.
8369 @deffn {Command} {add_script_search_dir} [directory]
8370 Add @var{directory} to the file/script search path.
8373 @deffn {Config Command} {bindto} [@var{name}]
8374 Specify hostname or IPv4 address on which to listen for incoming
8375 TCP/IP connections. By default, OpenOCD will listen on the loopback
8376 interface only. If your network environment is safe, @code{bindto
8377 0.0.0.0} can be used to cover all available interfaces.
8380 @anchor{targetstatehandling}
8381 @section Target State handling
8384 @cindex target initialization
8386 In this section ``target'' refers to a CPU configured as
8387 shown earlier (@pxref{CPU Configuration}).
8388 These commands, like many, implicitly refer to
8389 a current target which is used to perform the
8390 various operations. The current target may be changed
8391 by using @command{targets} command with the name of the
8392 target which should become current.
8394 @deffn {Command} {reg} [(number|name) [(value|'force')]]
8395 Access a single register by @var{number} or by its @var{name}.
8396 The target must generally be halted before access to CPU core
8397 registers is allowed. Depending on the hardware, some other
8398 registers may be accessible while the target is running.
8400 @emph{With no arguments}:
8401 list all available registers for the current target,
8402 showing number, name, size, value, and cache status.
8403 For valid entries, a value is shown; valid entries
8404 which are also dirty (and will be written back later)
8405 are flagged as such.
8407 @emph{With number/name}: display that register's value.
8408 Use @var{force} argument to read directly from the target,
8409 bypassing any internal cache.
8411 @emph{With both number/name and value}: set register's value.
8412 Writes may be held in a writeback cache internal to OpenOCD,
8413 so that setting the value marks the register as dirty instead
8414 of immediately flushing that value. Resuming CPU execution
8415 (including by single stepping) or otherwise activating the
8416 relevant module will flush such values.
8418 Cores may have surprisingly many registers in their
8419 Debug and trace infrastructure:
8424 (0) r0 (/32): 0x0000D3C2 (dirty)
8425 (1) r1 (/32): 0xFD61F31C
8428 (164) ETM_contextid_comparator_mask (/32)
8433 @deffn {Command} {halt} [ms]
8434 @deffnx {Command} {wait_halt} [ms]
8435 The @command{halt} command first sends a halt request to the target,
8436 which @command{wait_halt} doesn't.
8437 Otherwise these behave the same: wait up to @var{ms} milliseconds,
8438 or 5 seconds if there is no parameter, for the target to halt
8439 (and enter debug mode).
8440 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
8443 On ARM cores, software using the @emph{wait for interrupt} operation
8444 often blocks the JTAG access needed by a @command{halt} command.
8445 This is because that operation also puts the core into a low
8446 power mode by gating the core clock;
8447 but the core clock is needed to detect JTAG clock transitions.
8449 One partial workaround uses adaptive clocking: when the core is
8450 interrupted the operation completes, then JTAG clocks are accepted
8451 at least until the interrupt handler completes.
8452 However, this workaround is often unusable since the processor, board,
8453 and JTAG adapter must all support adaptive JTAG clocking.
8454 Also, it can't work until an interrupt is issued.
8456 A more complete workaround is to not use that operation while you
8457 work with a JTAG debugger.
8458 Tasking environments generally have idle loops where the body is the
8459 @emph{wait for interrupt} operation.
8460 (On older cores, it is a coprocessor action;
8461 newer cores have a @option{wfi} instruction.)
8462 Such loops can just remove that operation, at the cost of higher
8463 power consumption (because the CPU is needlessly clocked).
8468 @deffn {Command} {resume} [address]
8469 Resume the target at its current code position,
8470 or the optional @var{address} if it is provided.
8471 OpenOCD will wait 5 seconds for the target to resume.
8474 @deffn {Command} {step} [address]
8475 Single-step the target at its current code position,
8476 or the optional @var{address} if it is provided.
8479 @anchor{resetcommand}
8480 @deffn {Command} {reset}
8481 @deffnx {Command} {reset run}
8482 @deffnx {Command} {reset halt}
8483 @deffnx {Command} {reset init}
8484 Perform as hard a reset as possible, using SRST if possible.
8485 @emph{All defined targets will be reset, and target
8486 events will fire during the reset sequence.}
8488 The optional parameter specifies what should
8489 happen after the reset.
8490 If there is no parameter, a @command{reset run} is executed.
8491 The other options will not work on all systems.
8492 @xref{Reset Configuration}.
8495 @item @b{run} Let the target run
8496 @item @b{halt} Immediately halt the target
8497 @item @b{init} Immediately halt the target, and execute the reset-init script
8501 @deffn {Command} {soft_reset_halt}
8502 Requesting target halt and executing a soft reset. This is often used
8503 when a target cannot be reset and halted. The target, after reset is
8504 released begins to execute code. OpenOCD attempts to stop the CPU and
8505 then sets the program counter back to the reset vector. Unfortunately
8506 the code that was executed may have left the hardware in an unknown
8510 @deffn {Command} {adapter assert} [signal [assert|deassert signal]]
8511 @deffnx {Command} {adapter deassert} [signal [assert|deassert signal]]
8512 Set values of reset signals.
8513 Without parameters returns current status of the signals.
8514 The @var{signal} parameter values may be
8515 @option{srst}, indicating that srst signal is to be asserted or deasserted,
8516 @option{trst}, indicating that trst signal is to be asserted or deasserted.
8518 The @command{reset_config} command should already have been used
8519 to configure how the board and the adapter treat these two
8520 signals, and to say if either signal is even present.
8521 @xref{Reset Configuration}.
8522 Trying to assert a signal that is not present triggers an error.
8523 If a signal is present on the adapter and not specified in the command,
8524 the signal will not be modified.
8527 TRST is specially handled.
8528 It actually signifies JTAG's @sc{reset} state.
8529 So if the board doesn't support the optional TRST signal,
8530 or it doesn't support it along with the specified SRST value,
8531 JTAG reset is triggered with TMS and TCK signals
8532 instead of the TRST signal.
8533 And no matter how that JTAG reset is triggered, once
8534 the scan chain enters @sc{reset} with TRST inactive,
8535 TAP @code{post-reset} events are delivered to all TAPs
8536 with handlers for that event.
8540 @anchor{memoryaccess}
8541 @section Memory access commands
8542 @cindex memory access
8544 These commands allow accesses of a specific size to the memory
8545 system. Often these are used to configure the current target in some
8546 special way. For example - one may need to write certain values to the
8547 SDRAM controller to enable SDRAM.
8550 @item Use the @command{targets} (plural) command
8551 to change the current target.
8552 @item In system level scripts these commands are deprecated.
8553 Please use their TARGET object siblings to avoid making assumptions
8554 about what TAP is the current target, or about MMU configuration.
8557 @deffn {Command} {mdd} [phys] addr [count]
8558 @deffnx {Command} {mdw} [phys] addr [count]
8559 @deffnx {Command} {mdh} [phys] addr [count]
8560 @deffnx {Command} {mdb} [phys] addr [count]
8561 Display contents of address @var{addr}, as
8562 64-bit doublewords (@command{mdd}),
8563 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8564 or 8-bit bytes (@command{mdb}).
8565 When the current target has an MMU which is present and active,
8566 @var{addr} is interpreted as a virtual address.
8567 Otherwise, or if the optional @var{phys} flag is specified,
8568 @var{addr} is interpreted as a physical address.
8569 If @var{count} is specified, displays that many units.
8570 (If you want to manipulate the data instead of displaying it,
8571 see the @code{mem2array} primitives.)
8574 @deffn {Command} {mwd} [phys] addr doubleword [count]
8575 @deffnx {Command} {mww} [phys] addr word [count]
8576 @deffnx {Command} {mwh} [phys] addr halfword [count]
8577 @deffnx {Command} {mwb} [phys] addr byte [count]
8578 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
8579 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
8580 at the specified address @var{addr}.
8581 When the current target has an MMU which is present and active,
8582 @var{addr} is interpreted as a virtual address.
8583 Otherwise, or if the optional @var{phys} flag is specified,
8584 @var{addr} is interpreted as a physical address.
8585 If @var{count} is specified, fills that many units of consecutive address.
8588 @anchor{imageaccess}
8589 @section Image loading commands
8590 @cindex image loading
8591 @cindex image dumping
8593 @deffn {Command} {dump_image} filename address size
8594 Dump @var{size} bytes of target memory starting at @var{address} to the
8595 binary file named @var{filename}.
8598 @deffn {Command} {fast_load}
8599 Loads an image stored in memory by @command{fast_load_image} to the
8600 current target. Must be preceded by fast_load_image.
8603 @deffn {Command} {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
8604 Normally you should be using @command{load_image} or GDB load. However, for
8605 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
8606 host), storing the image in memory and uploading the image to the target
8607 can be a way to upload e.g. multiple debug sessions when the binary does not change.
8608 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
8609 memory, i.e. does not affect target. This approach is also useful when profiling
8610 target programming performance as I/O and target programming can easily be profiled
8614 @deffn {Command} {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
8615 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
8616 The file format may optionally be specified
8617 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
8618 In addition the following arguments may be specified:
8619 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
8620 @var{max_length} - maximum number of bytes to load.
8622 proc load_image_bin @{fname foffset address length @} @{
8623 # Load data from fname filename at foffset offset to
8624 # target at address. Load at most length bytes.
8625 load_image $fname [expr @{$address - $foffset@}] bin \
8631 @deffn {Command} {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
8632 Displays image section sizes and addresses
8633 as if @var{filename} were loaded into target memory
8634 starting at @var{address} (defaults to zero).
8635 The file format may optionally be specified
8636 (@option{bin}, @option{ihex}, or @option{elf})
8639 @deffn {Command} {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
8640 Verify @var{filename} against target memory starting at @var{address}.
8641 The file format may optionally be specified
8642 (@option{bin}, @option{ihex}, or @option{elf})
8643 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
8646 @deffn {Command} {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
8647 Verify @var{filename} against target memory starting at @var{address}.
8648 The file format may optionally be specified
8649 (@option{bin}, @option{ihex}, or @option{elf})
8650 This perform a comparison using a CRC checksum only
8654 @section Breakpoint and Watchpoint commands
8658 CPUs often make debug modules accessible through JTAG, with
8659 hardware support for a handful of code breakpoints and data
8661 In addition, CPUs almost always support software breakpoints.
8663 @deffn {Command} {bp} [address len [@option{hw}]]
8664 With no parameters, lists all active breakpoints.
8665 Else sets a breakpoint on code execution starting
8666 at @var{address} for @var{length} bytes.
8667 This is a software breakpoint, unless @option{hw} is specified
8668 in which case it will be a hardware breakpoint.
8670 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
8671 for similar mechanisms that do not consume hardware breakpoints.)
8674 @deffn {Command} {rbp} @option{all} | address
8675 Remove the breakpoint at @var{address} or all breakpoints.
8678 @deffn {Command} {rwp} address
8679 Remove data watchpoint on @var{address}
8682 @deffn {Command} {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
8683 With no parameters, lists all active watchpoints.
8684 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
8685 The watch point is an "access" watchpoint unless
8686 the @option{r} or @option{w} parameter is provided,
8687 defining it as respectively a read or write watchpoint.
8688 If a @var{value} is provided, that value is used when determining if
8689 the watchpoint should trigger. The value may be first be masked
8690 using @var{mask} to mark ``don't care'' fields.
8694 @section Real Time Transfer (RTT)
8696 Real Time Transfer (RTT) is an interface specified by SEGGER based on basic
8697 memory reads and writes to transfer data bidirectionally between target and host.
8698 The specification is independent of the target architecture.
8699 Every target that supports so called "background memory access", which means
8700 that the target memory can be accessed by the debugger while the target is
8701 running, can be used.
8702 This interface is especially of interest for targets without
8703 Serial Wire Output (SWO), such as ARM Cortex-M0, or where semihosting is not
8704 applicable because of real-time constraints.
8707 The current implementation supports only single target devices.
8710 The data transfer between host and target device is organized through
8711 unidirectional up/down-channels for target-to-host and host-to-target
8712 communication, respectively.
8715 The current implementation does not respect channel buffer flags.
8716 They are used to determine what happens when writing to a full buffer, for
8720 Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
8721 assigned to each channel to make them accessible to an unlimited number
8722 of TCP/IP connections.
8724 @deffn {Command} {rtt setup} address size ID
8725 Configure RTT for the currently selected target.
8726 Once RTT is started, OpenOCD searches for a control block with the
8727 identifier @var{ID} starting at the memory address @var{address} within the next
8731 @deffn {Command} {rtt start}
8733 If the control block location is not known, OpenOCD starts searching for it.
8736 @deffn {Command} {rtt stop}
8740 @deffn {Command} {rtt polling_interval} [interval]
8741 Display the polling interval.
8742 If @var{interval} is provided, set the polling interval.
8743 The polling interval determines (in milliseconds) how often the up-channels are
8744 checked for new data.
8747 @deffn {Command} {rtt channels}
8748 Display a list of all channels and their properties.
8751 @deffn {Command} {rtt channellist}
8752 Return a list of all channels and their properties as Tcl list.
8753 The list can be manipulated easily from within scripts.
8756 @deffn {Command} {rtt server start} port channel
8757 Start a TCP server on @var{port} for the channel @var{channel}.
8760 @deffn {Command} {rtt server stop} port
8761 Stop the TCP sever with port @var{port}.
8764 The following example shows how to setup RTT using the SEGGER RTT implementation
8765 on the target device.
8770 rtt setup 0x20000000 2048 "SEGGER RTT"
8773 rtt server start 9090 0
8776 In this example, OpenOCD searches the control block with the ID "SEGGER RTT"
8777 starting at 0x20000000 for 2048 bytes. The RTT channel 0 is exposed through the
8781 @section Misc Commands
8784 @deffn {Command} {profile} seconds filename [start end]
8785 Profiling samples the CPU's program counter as quickly as possible,
8786 which is useful for non-intrusive stochastic profiling.
8787 Saves up to 10000 samples in @file{filename} using ``gmon.out''
8788 format. Optional @option{start} and @option{end} parameters allow to
8789 limit the address range.
8792 @deffn {Command} {version}
8793 Displays a string identifying the version of this OpenOCD server.
8796 @deffn {Command} {virt2phys} virtual_address
8797 Requests the current target to map the specified @var{virtual_address}
8798 to its corresponding physical address, and displays the result.
8801 @deffn {Command} {add_help_text} 'command_name' 'help-string'
8802 Add or replace help text on the given @var{command_name}.
8805 @deffn {Command} {add_usage_text} 'command_name' 'help-string'
8806 Add or replace usage text on the given @var{command_name}.
8809 @node Architecture and Core Commands
8810 @chapter Architecture and Core Commands
8811 @cindex Architecture Specific Commands
8812 @cindex Core Specific Commands
8814 Most CPUs have specialized JTAG operations to support debugging.
8815 OpenOCD packages most such operations in its standard command framework.
8816 Some of those operations don't fit well in that framework, so they are
8817 exposed here as architecture or implementation (core) specific commands.
8819 @anchor{armhardwaretracing}
8820 @section ARM Hardware Tracing
8825 CPUs based on ARM cores may include standard tracing interfaces,
8826 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
8827 address and data bus trace records to a ``Trace Port''.
8831 Development-oriented boards will sometimes provide a high speed
8832 trace connector for collecting that data, when the particular CPU
8833 supports such an interface.
8834 (The standard connector is a 38-pin Mictor, with both JTAG
8835 and trace port support.)
8836 Those trace connectors are supported by higher end JTAG adapters
8837 and some logic analyzer modules; frequently those modules can
8838 buffer several megabytes of trace data.
8839 Configuring an ETM coupled to such an external trace port belongs
8840 in the board-specific configuration file.
8842 If the CPU doesn't provide an external interface, it probably
8843 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
8844 dedicated SRAM. 4KBytes is one common ETB size.
8845 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
8846 (target) configuration file, since it works the same on all boards.
8849 ETM support in OpenOCD doesn't seem to be widely used yet.
8852 ETM support may be buggy, and at least some @command{etm config}
8853 parameters should be detected by asking the ETM for them.
8855 ETM trigger events could also implement a kind of complex
8856 hardware breakpoint, much more powerful than the simple
8857 watchpoint hardware exported by EmbeddedICE modules.
8858 @emph{Such breakpoints can be triggered even when using the
8859 dummy trace port driver}.
8861 It seems like a GDB hookup should be possible,
8862 as well as tracing only during specific states
8863 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
8865 There should be GUI tools to manipulate saved trace data and help
8866 analyse it in conjunction with the source code.
8867 It's unclear how much of a common interface is shared
8868 with the current XScale trace support, or should be
8869 shared with eventual Nexus-style trace module support.
8871 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
8872 for ETM modules is available. The code should be able to
8873 work with some newer cores; but not all of them support
8874 this original style of JTAG access.
8877 @subsection ETM Configuration
8878 ETM setup is coupled with the trace port driver configuration.
8880 @deffn {Config Command} {etm config} target width mode clocking driver
8881 Declares the ETM associated with @var{target}, and associates it
8882 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
8884 Several of the parameters must reflect the trace port capabilities,
8885 which are a function of silicon capabilities (exposed later
8886 using @command{etm info}) and of what hardware is connected to
8887 that port (such as an external pod, or ETB).
8888 The @var{width} must be either 4, 8, or 16,
8889 except with ETMv3.0 and newer modules which may also
8890 support 1, 2, 24, 32, 48, and 64 bit widths.
8891 (With those versions, @command{etm info} also shows whether
8892 the selected port width and mode are supported.)
8894 The @var{mode} must be @option{normal}, @option{multiplexed},
8895 or @option{demultiplexed}.
8896 The @var{clocking} must be @option{half} or @option{full}.
8899 With ETMv3.0 and newer, the bits set with the @var{mode} and
8900 @var{clocking} parameters both control the mode.
8901 This modified mode does not map to the values supported by
8902 previous ETM modules, so this syntax is subject to change.
8906 You can see the ETM registers using the @command{reg} command.
8907 Not all possible registers are present in every ETM.
8908 Most of the registers are write-only, and are used to configure
8909 what CPU activities are traced.
8913 @deffn {Command} {etm info}
8914 Displays information about the current target's ETM.
8915 This includes resource counts from the @code{ETM_CONFIG} register,
8916 as well as silicon capabilities (except on rather old modules).
8917 from the @code{ETM_SYS_CONFIG} register.
8920 @deffn {Command} {etm status}
8921 Displays status of the current target's ETM and trace port driver:
8922 is the ETM idle, or is it collecting data?
8923 Did trace data overflow?
8927 @deffn {Command} {etm tracemode} [type context_id_bits cycle_accurate branch_output]
8928 Displays what data that ETM will collect.
8929 If arguments are provided, first configures that data.
8930 When the configuration changes, tracing is stopped
8931 and any buffered trace data is invalidated.
8934 @item @var{type} ... describing how data accesses are traced,
8935 when they pass any ViewData filtering that was set up.
8937 @option{none} (save nothing),
8938 @option{data} (save data),
8939 @option{address} (save addresses),
8940 @option{all} (save data and addresses)
8941 @item @var{context_id_bits} ... 0, 8, 16, or 32
8942 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
8943 cycle-accurate instruction tracing.
8944 Before ETMv3, enabling this causes much extra data to be recorded.
8945 @item @var{branch_output} ... @option{enable} or @option{disable}.
8946 Disable this unless you need to try reconstructing the instruction
8947 trace stream without an image of the code.
8951 @deffn {Command} {etm trigger_debug} (@option{enable}|@option{disable})
8952 Displays whether ETM triggering debug entry (like a breakpoint) is
8953 enabled or disabled, after optionally modifying that configuration.
8954 The default behaviour is @option{disable}.
8955 Any change takes effect after the next @command{etm start}.
8957 By using script commands to configure ETM registers, you can make the
8958 processor enter debug state automatically when certain conditions,
8959 more complex than supported by the breakpoint hardware, happen.
8962 @subsection ETM Trace Operation
8964 After setting up the ETM, you can use it to collect data.
8965 That data can be exported to files for later analysis.
8966 It can also be parsed with OpenOCD, for basic sanity checking.
8968 To configure what is being traced, you will need to write
8969 various trace registers using @command{reg ETM_*} commands.
8970 For the definitions of these registers, read ARM publication
8971 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
8972 Be aware that most of the relevant registers are write-only,
8973 and that ETM resources are limited. There are only a handful
8974 of address comparators, data comparators, counters, and so on.
8976 Examples of scenarios you might arrange to trace include:
8979 @item Code flow within a function, @emph{excluding} subroutines
8980 it calls. Use address range comparators to enable tracing
8981 for instruction access within that function's body.
8982 @item Code flow within a function, @emph{including} subroutines
8983 it calls. Use the sequencer and address comparators to activate
8984 tracing on an ``entered function'' state, then deactivate it by
8985 exiting that state when the function's exit code is invoked.
8986 @item Code flow starting at the fifth invocation of a function,
8987 combining one of the above models with a counter.
8988 @item CPU data accesses to the registers for a particular device,
8989 using address range comparators and the ViewData logic.
8990 @item Such data accesses only during IRQ handling, combining the above
8991 model with sequencer triggers which on entry and exit to the IRQ handler.
8992 @item @emph{... more}
8995 At this writing, September 2009, there are no Tcl utility
8996 procedures to help set up any common tracing scenarios.
8998 @deffn {Command} {etm analyze}
8999 Reads trace data into memory, if it wasn't already present.
9000 Decodes and prints the data that was collected.
9003 @deffn {Command} {etm dump} filename
9004 Stores the captured trace data in @file{filename}.
9007 @deffn {Command} {etm image} filename [base_address] [type]
9008 Opens an image file.
9011 @deffn {Command} {etm load} filename
9012 Loads captured trace data from @file{filename}.
9015 @deffn {Command} {etm start}
9016 Starts trace data collection.
9019 @deffn {Command} {etm stop}
9020 Stops trace data collection.
9023 @anchor{traceportdrivers}
9024 @subsection Trace Port Drivers
9026 To use an ETM trace port it must be associated with a driver.
9028 @deffn {Trace Port Driver} {dummy}
9029 Use the @option{dummy} driver if you are configuring an ETM that's
9030 not connected to anything (on-chip ETB or off-chip trace connector).
9031 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
9032 any trace data collection.}
9033 @deffn {Config Command} {etm_dummy config} target
9034 Associates the ETM for @var{target} with a dummy driver.
9038 @deffn {Trace Port Driver} {etb}
9039 Use the @option{etb} driver if you are configuring an ETM
9040 to use on-chip ETB memory.
9041 @deffn {Config Command} {etb config} target etb_tap
9042 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
9043 You can see the ETB registers using the @command{reg} command.
9045 @deffn {Command} {etb trigger_percent} [percent]
9046 This displays, or optionally changes, ETB behavior after the
9047 ETM's configured @emph{trigger} event fires.
9048 It controls how much more trace data is saved after the (single)
9049 trace trigger becomes active.
9052 @item The default corresponds to @emph{trace around} usage,
9053 recording 50 percent data before the event and the rest
9055 @item The minimum value of @var{percent} is 2 percent,
9056 recording almost exclusively data before the trigger.
9057 Such extreme @emph{trace before} usage can help figure out
9058 what caused that event to happen.
9059 @item The maximum value of @var{percent} is 100 percent,
9060 recording data almost exclusively after the event.
9061 This extreme @emph{trace after} usage might help sort out
9062 how the event caused trouble.
9064 @c REVISIT allow "break" too -- enter debug mode.
9069 @anchor{armcrosstrigger}
9070 @section ARM Cross-Trigger Interface
9073 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
9074 that connects event sources like tracing components or CPU cores with each
9075 other through a common trigger matrix (CTM). For ARMv8 architecture, a
9076 CTI is mandatory for core run control and each core has an individual
9077 CTI instance attached to it. OpenOCD has limited support for CTI using
9078 the @emph{cti} group of commands.
9080 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
9081 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
9082 @var{apn}. The @var{base_address} must match the base address of the CTI
9083 on the respective MEM-AP. All arguments are mandatory. This creates a
9084 new command @command{$cti_name} which is used for various purposes
9085 including additional configuration.
9088 @deffn {Command} {$cti_name enable} @option{on|off}
9089 Enable (@option{on}) or disable (@option{off}) the CTI.
9092 @deffn {Command} {$cti_name dump}
9093 Displays a register dump of the CTI.
9096 @deffn {Command} {$cti_name write} @var{reg_name} @var{value}
9097 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
9100 @deffn {Command} {$cti_name read} @var{reg_name}
9101 Print the value read from the CTI register with the symbolic name @var{reg_name}.
9104 @deffn {Command} {$cti_name ack} @var{event}
9105 Acknowledge a CTI @var{event}.
9108 @deffn {Command} {$cti_name channel} @var{channel_number} @var{operation}
9109 Perform a specific channel operation, the possible operations are:
9110 gate, ungate, set, clear and pulse
9113 @deffn {Command} {$cti_name testmode} @option{on|off}
9114 Enable (@option{on}) or disable (@option{off}) the integration test mode
9118 @deffn {Command} {cti names}
9119 Prints a list of names of all CTI objects created. This command is mainly
9120 useful in TCL scripting.
9123 @section Generic ARM
9126 These commands should be available on all ARM processors.
9127 They are available in addition to other core-specific
9128 commands that may be available.
9130 @deffn {Command} {arm core_state} [@option{arm}|@option{thumb}]
9131 Displays the core_state, optionally changing it to process
9132 either @option{arm} or @option{thumb} instructions.
9133 The target may later be resumed in the currently set core_state.
9134 (Processors may also support the Jazelle state, but
9135 that is not currently supported in OpenOCD.)
9138 @deffn {Command} {arm disassemble} address [count [@option{thumb}]]
9140 Disassembles @var{count} instructions starting at @var{address}.
9141 If @var{count} is not specified, a single instruction is disassembled.
9142 If @option{thumb} is specified, or the low bit of the address is set,
9143 Thumb2 (mixed 16/32-bit) instructions are used;
9144 else ARM (32-bit) instructions are used.
9145 (Processors may also support the Jazelle state, but
9146 those instructions are not currently understood by OpenOCD.)
9148 Note that all Thumb instructions are Thumb2 instructions,
9149 so older processors (without Thumb2 support) will still
9150 see correct disassembly of Thumb code.
9151 Also, ThumbEE opcodes are the same as Thumb2,
9152 with a handful of exceptions.
9153 ThumbEE disassembly currently has no explicit support.
9156 @deffn {Command} {arm mcr} pX op1 CRn CRm op2 value
9157 Write @var{value} to a coprocessor @var{pX} register
9158 passing parameters @var{CRn},
9159 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9160 and using the MCR instruction.
9161 (Parameter sequence matches the ARM instruction, but omits
9165 @deffn {Command} {arm mrc} pX coproc op1 CRn CRm op2
9166 Read a coprocessor @var{pX} register passing parameters @var{CRn},
9167 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9168 and the MRC instruction.
9169 Returns the result so it can be manipulated by Jim scripts.
9170 (Parameter sequence matches the ARM instruction, but omits
9174 @deffn {Command} {arm reg}
9175 Display a table of all banked core registers, fetching the current value from every
9176 core mode if necessary.
9179 @deffn {Command} {arm semihosting} [@option{enable}|@option{disable}]
9180 @cindex ARM semihosting
9181 Display status of semihosting, after optionally changing that status.
9183 Semihosting allows for code executing on an ARM target to use the
9184 I/O facilities on the host computer i.e. the system where OpenOCD
9185 is running. The target application must be linked against a library
9186 implementing the ARM semihosting convention that forwards operation
9187 requests by using a special SVC instruction that is trapped at the
9188 Supervisor Call vector by OpenOCD.
9191 @deffn {Command} {arm semihosting_cmdline} [@option{enable}|@option{disable}]
9192 @cindex ARM semihosting
9193 Set the command line to be passed to the debugger.
9196 arm semihosting_cmdline argv0 argv1 argv2 ...
9199 This option lets one set the command line arguments to be passed to
9200 the program. The first argument (argv0) is the program name in a
9201 standard C environment (argv[0]). Depending on the program (not much
9202 programs look at argv[0]), argv0 is ignored and can be any string.
9205 @deffn {Command} {arm semihosting_fileio} [@option{enable}|@option{disable}]
9206 @cindex ARM semihosting
9207 Display status of semihosting fileio, after optionally changing that
9210 Enabling this option forwards semihosting I/O to GDB process using the
9211 File-I/O remote protocol extension. This is especially useful for
9212 interacting with remote files or displaying console messages in the
9216 @deffn {Command} {arm semihosting_resexit} [@option{enable}|@option{disable}]
9217 @cindex ARM semihosting
9218 Enable resumable SEMIHOSTING_SYS_EXIT.
9220 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
9221 things are simple, the openocd process calls exit() and passes
9222 the value returned by the target.
9224 When SEMIHOSTING_SYS_EXIT is called during a debug session,
9225 by default execution returns to the debugger, leaving the
9226 debugger in a HALT state, similar to the state entered when
9227 encountering a break.
9229 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
9230 return normally, as any semihosting call, and do not break
9232 The standard allows this to happen, but the condition
9233 to trigger it is a bit obscure ("by performing an RDI_Execute
9234 request or equivalent").
9236 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
9237 this option (default: disabled).
9240 @section ARMv4 and ARMv5 Architecture
9244 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
9245 and introduced core parts of the instruction set in use today.
9246 That includes the Thumb instruction set, introduced in the ARMv4T
9249 @subsection ARM7 and ARM9 specific commands
9253 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
9254 ARM9TDMI, ARM920T or ARM926EJ-S.
9255 They are available in addition to the ARM commands,
9256 and any other core-specific commands that may be available.
9258 @deffn {Command} {arm7_9 dbgrq} [@option{enable}|@option{disable}]
9259 Displays the value of the flag controlling use of the
9260 EmbeddedIce DBGRQ signal to force entry into debug mode,
9261 instead of breakpoints.
9262 If a boolean parameter is provided, first assigns that flag.
9265 safe for all but ARM7TDMI-S cores (like NXP LPC).
9266 This feature is enabled by default on most ARM9 cores,
9267 including ARM9TDMI, ARM920T, and ARM926EJ-S.
9270 @deffn {Command} {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
9272 Displays the value of the flag controlling use of the debug communications
9273 channel (DCC) to write larger (>128 byte) amounts of memory.
9274 If a boolean parameter is provided, first assigns that flag.
9276 DCC downloads offer a huge speed increase, but might be
9277 unsafe, especially with targets running at very low speeds. This command was introduced
9278 with OpenOCD rev. 60, and requires a few bytes of working area.
9281 @deffn {Command} {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
9282 Displays the value of the flag controlling use of memory writes and reads
9283 that don't check completion of the operation.
9284 If a boolean parameter is provided, first assigns that flag.
9286 This provides a huge speed increase, especially with USB JTAG
9287 cables (FT2232), but might be unsafe if used with targets running at very low
9288 speeds, like the 32kHz startup clock of an AT91RM9200.
9291 @subsection ARM9 specific commands
9294 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
9296 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
9298 @c 9-june-2009: tried this on arm920t, it didn't work.
9299 @c no-params always lists nothing caught, and that's how it acts.
9300 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
9301 @c versions have different rules about when they commit writes.
9303 @anchor{arm9vectorcatch}
9304 @deffn {Command} {arm9 vector_catch} [@option{all}|@option{none}|list]
9305 @cindex vector_catch
9306 Vector Catch hardware provides a sort of dedicated breakpoint
9307 for hardware events such as reset, interrupt, and abort.
9308 You can use this to conserve normal breakpoint resources,
9309 so long as you're not concerned with code that branches directly
9310 to those hardware vectors.
9312 This always finishes by listing the current configuration.
9313 If parameters are provided, it first reconfigures the
9314 vector catch hardware to intercept
9315 @option{all} of the hardware vectors,
9316 @option{none} of them,
9317 or a list with one or more of the following:
9318 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
9319 @option{irq} @option{fiq}.
9322 @subsection ARM920T specific commands
9325 These commands are available to ARM920T based CPUs,
9326 which are implementations of the ARMv4T architecture
9327 built using the ARM9TDMI integer core.
9328 They are available in addition to the ARM, ARM7/ARM9,
9331 @deffn {Command} {arm920t cache_info}
9332 Print information about the caches found. This allows to see whether your target
9333 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
9336 @deffn {Command} {arm920t cp15} regnum [value]
9337 Display cp15 register @var{regnum};
9338 else if a @var{value} is provided, that value is written to that register.
9339 This uses "physical access" and the register number is as
9340 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
9341 (Not all registers can be written.)
9344 @deffn {Command} {arm920t read_cache} filename
9345 Dump the content of ICache and DCache to a file named @file{filename}.
9348 @deffn {Command} {arm920t read_mmu} filename
9349 Dump the content of the ITLB and DTLB to a file named @file{filename}.
9352 @subsection ARM926ej-s specific commands
9355 These commands are available to ARM926ej-s based CPUs,
9356 which are implementations of the ARMv5TEJ architecture
9357 based on the ARM9EJ-S integer core.
9358 They are available in addition to the ARM, ARM7/ARM9,
9361 The Feroceon cores also support these commands, although
9362 they are not built from ARM926ej-s designs.
9364 @deffn {Command} {arm926ejs cache_info}
9365 Print information about the caches found.
9368 @subsection ARM966E specific commands
9371 These commands are available to ARM966 based CPUs,
9372 which are implementations of the ARMv5TE architecture.
9373 They are available in addition to the ARM, ARM7/ARM9,
9376 @deffn {Command} {arm966e cp15} regnum [value]
9377 Display cp15 register @var{regnum};
9378 else if a @var{value} is provided, that value is written to that register.
9379 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
9381 There is no current control over bits 31..30 from that table,
9382 as required for BIST support.
9385 @subsection XScale specific commands
9388 Some notes about the debug implementation on the XScale CPUs:
9390 The XScale CPU provides a special debug-only mini-instruction cache
9391 (mini-IC) in which exception vectors and target-resident debug handler
9392 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
9393 must point vector 0 (the reset vector) to the entry of the debug
9394 handler. However, this means that the complete first cacheline in the
9395 mini-IC is marked valid, which makes the CPU fetch all exception
9396 handlers from the mini-IC, ignoring the code in RAM.
9398 To address this situation, OpenOCD provides the @code{xscale
9399 vector_table} command, which allows the user to explicitly write
9400 individual entries to either the high or low vector table stored in
9403 It is recommended to place a pc-relative indirect branch in the vector
9404 table, and put the branch destination somewhere in memory. Doing so
9405 makes sure the code in the vector table stays constant regardless of
9406 code layout in memory:
9409 ldr pc,[pc,#0x100-8]
9410 ldr pc,[pc,#0x100-8]
9411 ldr pc,[pc,#0x100-8]
9412 ldr pc,[pc,#0x100-8]
9413 ldr pc,[pc,#0x100-8]
9414 ldr pc,[pc,#0x100-8]
9415 ldr pc,[pc,#0x100-8]
9416 ldr pc,[pc,#0x100-8]
9418 .long real_reset_vector
9419 .long real_ui_handler
9420 .long real_swi_handler
9422 .long real_data_abort
9423 .long 0 /* unused */
9424 .long real_irq_handler
9425 .long real_fiq_handler
9428 Alternatively, you may choose to keep some or all of the mini-IC
9429 vector table entries synced with those written to memory by your
9430 system software. The mini-IC can not be modified while the processor
9431 is executing, but for each vector table entry not previously defined
9432 using the @code{xscale vector_table} command, OpenOCD will copy the
9433 value from memory to the mini-IC every time execution resumes from a
9434 halt. This is done for both high and low vector tables (although the
9435 table not in use may not be mapped to valid memory, and in this case
9436 that copy operation will silently fail). This means that you will
9437 need to briefly halt execution at some strategic point during system
9438 start-up; e.g., after the software has initialized the vector table,
9439 but before exceptions are enabled. A breakpoint can be used to
9440 accomplish this once the appropriate location in the start-up code has
9441 been identified. A watchpoint over the vector table region is helpful
9442 in finding the location if you're not sure. Note that the same
9443 situation exists any time the vector table is modified by the system
9446 The debug handler must be placed somewhere in the address space using
9447 the @code{xscale debug_handler} command. The allowed locations for the
9448 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
9449 0xfffff800). The default value is 0xfe000800.
9451 XScale has resources to support two hardware breakpoints and two
9452 watchpoints. However, the following restrictions on watchpoint
9453 functionality apply: (1) the value and mask arguments to the @code{wp}
9454 command are not supported, (2) the watchpoint length must be a
9455 power of two and not less than four, and can not be greater than the
9456 watchpoint address, and (3) a watchpoint with a length greater than
9457 four consumes all the watchpoint hardware resources. This means that
9458 at any one time, you can have enabled either two watchpoints with a
9459 length of four, or one watchpoint with a length greater than four.
9461 These commands are available to XScale based CPUs,
9462 which are implementations of the ARMv5TE architecture.
9464 @deffn {Command} {xscale analyze_trace}
9465 Displays the contents of the trace buffer.
9468 @deffn {Command} {xscale cache_clean_address} address
9469 Changes the address used when cleaning the data cache.
9472 @deffn {Command} {xscale cache_info}
9473 Displays information about the CPU caches.
9476 @deffn {Command} {xscale cp15} regnum [value]
9477 Display cp15 register @var{regnum};
9478 else if a @var{value} is provided, that value is written to that register.
9481 @deffn {Command} {xscale debug_handler} target address
9482 Changes the address used for the specified target's debug handler.
9485 @deffn {Command} {xscale dcache} [@option{enable}|@option{disable}]
9486 Enables or disable the CPU's data cache.
9489 @deffn {Command} {xscale dump_trace} filename
9490 Dumps the raw contents of the trace buffer to @file{filename}.
9493 @deffn {Command} {xscale icache} [@option{enable}|@option{disable}]
9494 Enables or disable the CPU's instruction cache.
9497 @deffn {Command} {xscale mmu} [@option{enable}|@option{disable}]
9498 Enables or disable the CPU's memory management unit.
9501 @deffn {Command} {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
9502 Displays the trace buffer status, after optionally
9503 enabling or disabling the trace buffer
9504 and modifying how it is emptied.
9507 @deffn {Command} {xscale trace_image} filename [offset [type]]
9508 Opens a trace image from @file{filename}, optionally rebasing
9509 its segment addresses by @var{offset}.
9510 The image @var{type} may be one of
9511 @option{bin} (binary), @option{ihex} (Intel hex),
9512 @option{elf} (ELF file), @option{s19} (Motorola s19),
9513 @option{mem}, or @option{builder}.
9516 @anchor{xscalevectorcatch}
9517 @deffn {Command} {xscale vector_catch} [mask]
9518 @cindex vector_catch
9519 Display a bitmask showing the hardware vectors to catch.
9520 If the optional parameter is provided, first set the bitmask to that value.
9522 The mask bits correspond with bit 16..23 in the DCSR:
9525 0x02 Trap Undefined Instructions
9526 0x04 Trap Software Interrupt
9527 0x08 Trap Prefetch Abort
9528 0x10 Trap Data Abort
9535 @deffn {Command} {xscale vector_table} [(@option{low}|@option{high}) index value]
9536 @cindex vector_table
9538 Set an entry in the mini-IC vector table. There are two tables: one for
9539 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
9540 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
9541 points to the debug handler entry and can not be overwritten.
9542 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
9544 Without arguments, the current settings are displayed.
9548 @section ARMv6 Architecture
9551 @subsection ARM11 specific commands
9554 @deffn {Command} {arm11 memwrite burst} [@option{enable}|@option{disable}]
9555 Displays the value of the memwrite burst-enable flag,
9556 which is enabled by default.
9557 If a boolean parameter is provided, first assigns that flag.
9558 Burst writes are only used for memory writes larger than 1 word.
9559 They improve performance by assuming that the CPU has read each data
9560 word over JTAG and completed its write before the next word arrives,
9561 instead of polling for a status flag to verify that completion.
9562 This is usually safe, because JTAG runs much slower than the CPU.
9565 @deffn {Command} {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
9566 Displays the value of the memwrite error_fatal flag,
9567 which is enabled by default.
9568 If a boolean parameter is provided, first assigns that flag.
9569 When set, certain memory write errors cause earlier transfer termination.
9572 @deffn {Command} {arm11 step_irq_enable} [@option{enable}|@option{disable}]
9573 Displays the value of the flag controlling whether
9574 IRQs are enabled during single stepping;
9575 they are disabled by default.
9576 If a boolean parameter is provided, first assigns that.
9579 @deffn {Command} {arm11 vcr} [value]
9580 @cindex vector_catch
9581 Displays the value of the @emph{Vector Catch Register (VCR)},
9582 coprocessor 14 register 7.
9583 If @var{value} is defined, first assigns that.
9585 Vector Catch hardware provides dedicated breakpoints
9586 for certain hardware events.
9587 The specific bit values are core-specific (as in fact is using
9588 coprocessor 14 register 7 itself) but all current ARM11
9589 cores @emph{except the ARM1176} use the same six bits.
9592 @section ARMv7 and ARMv8 Architecture
9596 @subsection ARMv7-A specific commands
9599 @deffn {Command} {cortex_a cache_info}
9600 display information about target caches
9603 @deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
9604 Work around issues with software breakpoints when the program text is
9605 mapped read-only by the operating system. This option sets the CP15 DACR
9606 to "all-manager" to bypass MMU permission checks on memory access.
9610 @deffn {Command} {cortex_a dbginit}
9611 Initialize core debug
9612 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9615 @deffn {Command} {cortex_a smp} [on|off]
9616 Display/set the current SMP mode
9619 @deffn {Command} {cortex_a smp_gdb} [core_id]
9620 Display/set the current core displayed in GDB
9623 @deffn {Command} {cortex_a maskisr} [@option{on}|@option{off}]
9624 Selects whether interrupts will be processed when single stepping
9627 @deffn {Command} {cache_config l2x} [base way]
9631 @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
9632 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
9633 memory location @var{address}. When dumping the table from @var{address}, print at most
9634 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
9635 possible (4096) entries are printed.
9638 @subsection ARMv7-R specific commands
9641 @deffn {Command} {cortex_r4 dbginit}
9642 Initialize core debug
9643 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9646 @deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
9647 Selects whether interrupts will be processed when single stepping
9651 @subsection ARM CoreSight TPIU and SWO specific commands
9657 ARM CoreSight provides several modules to generate debugging
9658 information internally (ITM, DWT and ETM). Their output is directed
9659 through TPIU or SWO modules to be captured externally either on an SWO pin (this
9660 configuration is called SWV) or on a synchronous parallel trace port.
9662 ARM CoreSight provides independent HW blocks named TPIU and SWO each with its
9663 own functionality. Embedded in Cortex-M3 and M4, ARM provides an optional HW
9664 block that includes both TPIU and SWO functionalities and is again named TPIU,
9665 which causes quite some confusion.
9666 The registers map of all the TPIU and SWO implementations allows using a single
9667 driver that detects at runtime the features available.
9669 The @command{tpiu} is used for either TPIU or SWO.
9670 A convenient alias @command{swo} is available to help distinguish, in scripts,
9671 the commands for SWO from the commands for TPIU.
9673 @deffn {Command} {swo} ...
9674 Alias of @command{tpiu ...}. Can be used in scripts to distinguish the commands
9675 for SWO from the commands for TPIU.
9678 @deffn {Command} {tpiu create} tpiu_name configparams...
9679 Creates a TPIU or a SWO object. The two commands are equivalent.
9680 Add the object in a list and add new commands (@command{@var{tpiu_name}})
9681 which are used for various purposes including additional configuration.
9684 @item @var{tpiu_name} -- the name of the TPIU or SWO object.
9685 This name is also used to create the object's command, referred to here
9686 as @command{$tpiu_name}, and in other places where the TPIU or SWO needs to be identified.
9687 @item @var{configparams} -- all parameters accepted by @command{$tpiu_name configure} are permitted.
9689 You @emph{must} set here the AP and MEM_AP base_address through @code{-dap @var{dap_name}},
9690 @code{-ap-num @var{ap_number}} and @code{-baseaddr @var{base_address}}.
9694 @deffn {Command} {tpiu names}
9695 Lists all the TPIU or SWO objects created so far. The two commands are equivalent.
9698 @deffn {Command} {tpiu init}
9699 Initialize all registered TPIU and SWO. The two commands are equivalent.
9700 These commands are used internally during initialization. They can be issued
9701 at any time after the initialization, too.
9704 @deffn {Command} {$tpiu_name cget} queryparm
9705 Each configuration parameter accepted by @command{$tpiu_name configure} can be
9706 individually queried, to return its current value.
9707 The @var{queryparm} is a parameter name accepted by that command, such as @code{-dap}.
9710 @deffn {Command} {$tpiu_name configure} configparams...
9711 The options accepted by this command may also be specified as parameters
9712 to @command{tpiu create}. Their values can later be queried one at a time by
9713 using the @command{$tpiu_name cget} command.
9716 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
9717 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
9719 @item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU,
9720 @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
9722 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
9723 to access the TPIU in the DAP AP memory space.
9725 @item @code{-protocol} (@option{sync}|@option{uart}|@option{manchester}) -- sets the
9726 protocol used for trace data:
9728 @item @option{sync} -- synchronous parallel trace output mode, using @var{port_width}
9729 data bits (default);
9730 @item @option{uart} -- use asynchronous SWO mode with NRZ (same as regular UART 8N1) coding;
9731 @item @option{manchester} -- use asynchronous SWO mode with Manchester coding.
9734 @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler,
9735 a TCL string which is evaluated when the event is triggered. The events
9736 @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable}
9737 are defined for TPIU/SWO.
9738 A typical use case for the event @code{pre-enable} is to enable the trace clock
9741 @item @code{-output} (@option{external}|@option{:}@var{port}|@var{filename}|@option{-}) -- specifies
9742 the destination of the trace data:
9744 @item @option{external} -- configure TPIU/SWO to let user capture trace
9745 output externally, either with an additional UART or with a logic analyzer (default);
9746 @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data
9747 and forward it to @command{tcl_trace} command;
9748 @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather
9749 trace data, open a TCP server at port @var{port} and send the trace data to
9750 each connected client;
9751 @item @var{filename} -- configure TPIU/SWO and debug adapter to
9752 gather trace data and append it to @var{filename}, which can be
9753 either a regular file or a named pipe.
9756 @item @code{-traceclk} @var{TRACECLKIN_freq} -- mandatory parameter.
9757 Specifies the frequency in Hz of the trace clock. For the TPIU embedded in
9758 Cortex-M3 or M4, this is usually the same frequency as HCLK. For protocol
9759 @option{sync} this is twice the frequency of the pin data rate.
9761 @item @code{-pin-freq} @var{trace_freq} -- specifies the expected data rate
9762 in Hz of the SWO pin. Parameter used only on protocols @option{uart} and
9763 @option{manchester}. Can be omitted to let the adapter driver select the
9764 maximum supported rate automatically.
9766 @item @code{-port-width} @var{port_width} -- sets to @var{port_width} the width
9767 of the synchronous parallel port used for trace output. Parameter used only on
9768 protocol @option{sync}. If not specified, default value is @var{1}.
9770 @item @code{-formatter} (@option{0}|@option{1}) -- specifies if the formatter
9771 should be enabled. Parameter used only on protocol @option{sync}. If not specified,
9772 default value is @var{0}.
9776 @deffn {Command} {$tpiu_name enable}
9777 Uses the parameters specified by the previous @command{$tpiu_name configure}
9778 to configure and enable the TPIU or the SWO.
9779 If required, the adapter is also configured and enabled to receive the trace
9781 This command can be used before @command{init}, but it will take effect only
9782 after the @command{init}.
9785 @deffn {Command} {$tpiu_name disable}
9786 Disable the TPIU or the SWO, terminating the receiving of the trace data.
9793 @item STM32L152 board is programmed with an application that configures
9794 PLL to provide core clock with 24MHz frequency; to use ITM output it's
9797 #include <libopencm3/cm3/itm.h>
9802 (the most obvious way is to use the first stimulus port for printf,
9803 for that this ITM_STIM8 assignment can be used inside _write(); to make it
9804 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
9805 ITM_STIM_FIFOREADY));});
9806 @item An FT2232H UART is connected to the SWO pin of the board;
9807 @item Commands to configure UART for 12MHz baud rate:
9809 $ setserial /dev/ttyUSB1 spd_cust divisor 5
9810 $ stty -F /dev/ttyUSB1 38400
9812 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
9813 baud with our custom divisor to get 12MHz)
9814 @item @code{itmdump -f /dev/ttyUSB1 -d1}
9815 @item OpenOCD invocation line:
9817 openocd -f interface/stlink.cfg \
9818 -c "transport select hla_swd" \
9819 -f target/stm32l1.cfg \
9820 -c "stm32l1.tpiu configure -protocol uart" \
9821 -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
9822 -c "stm32l1.tpiu enable"
9826 @subsection ARMv7-M specific commands
9833 @deffn {Command} {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
9834 Enable or disable trace output for ITM stimulus @var{port} (counting
9835 from 0). Port 0 is enabled on target creation automatically.
9838 @deffn {Command} {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
9839 Enable or disable trace output for all ITM stimulus ports.
9842 @subsection Cortex-M specific commands
9845 @deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
9846 Control masking (disabling) interrupts during target step/resume.
9848 The @option{auto} option handles interrupts during stepping in a way that they
9849 get served but don't disturb the program flow. The step command first allows
9850 pending interrupt handlers to execute, then disables interrupts and steps over
9851 the next instruction where the core was halted. After the step interrupts
9852 are enabled again. If the interrupt handlers don't complete within 500ms,
9853 the step command leaves with the core running.
9855 The @option{steponly} option disables interrupts during single-stepping but
9856 enables them during normal execution. This can be used as a partial workaround
9857 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
9858 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
9860 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
9861 option. If no breakpoint is available at the time of the step, then the step
9862 is taken with interrupts enabled, i.e. the same way the @option{off} option
9865 Default is @option{auto}.
9868 @deffn {Command} {cortex_m vector_catch} [@option{all}|@option{none}|list]
9869 @cindex vector_catch
9870 Vector Catch hardware provides dedicated breakpoints
9871 for certain hardware events.
9873 Parameters request interception of
9874 @option{all} of these hardware event vectors,
9875 @option{none} of them,
9876 or one or more of the following:
9877 @option{hard_err} for a HardFault exception;
9878 @option{mm_err} for a MemManage exception;
9879 @option{bus_err} for a BusFault exception;
9882 @option{chk_err}, or
9883 @option{nocp_err} for various UsageFault exceptions; or
9885 If NVIC setup code does not enable them,
9886 MemManage, BusFault, and UsageFault exceptions
9887 are mapped to HardFault.
9888 UsageFault checks for
9889 divide-by-zero and unaligned access
9890 must also be explicitly enabled.
9892 This finishes by listing the current vector catch configuration.
9895 @deffn {Command} {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
9896 Control reset handling if hardware srst is not fitted
9897 @xref{reset_config,,reset_config}.
9900 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
9901 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
9904 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
9905 This however has the disadvantage of only resetting the core, all peripherals
9906 are unaffected. A solution would be to use a @code{reset-init} event handler
9907 to manually reset the peripherals.
9908 @xref{targetevents,,Target Events}.
9910 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
9914 @subsection ARMv8-A specific commands
9918 @deffn {Command} {aarch64 cache_info}
9919 Display information about target caches
9922 @deffn {Command} {aarch64 dbginit}
9923 This command enables debugging by clearing the OS Lock and sticky power-down and reset
9924 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
9925 target code relies on. In a configuration file, the command would typically be called from a
9926 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
9927 However, normally it is not necessary to use the command at all.
9930 @deffn {Command} {aarch64 disassemble} address [count]
9932 Disassembles @var{count} instructions starting at @var{address}.
9933 If @var{count} is not specified, a single instruction is disassembled.
9936 @deffn {Command} {aarch64 smp} [on|off]
9937 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
9938 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
9939 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
9940 group. With SMP handling disabled, all targets need to be treated individually.
9943 @deffn {Command} {aarch64 maskisr} [@option{on}|@option{off}]
9944 Selects whether interrupts will be processed when single stepping. The default configuration is
9948 @deffn {Command} {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
9949 Cause @command{$target_name} to halt when an exception is taken. Any combination of
9950 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
9951 @command{$target_name} will halt before taking the exception. In order to resume
9952 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
9953 Issuing the command without options prints the current configuration.
9956 @section EnSilica eSi-RISC Architecture
9958 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
9959 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
9961 @subsection eSi-RISC Configuration
9963 @deffn {Command} {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
9964 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
9965 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
9968 @deffn {Command} {esirisc hwdc} (@option{all}|@option{none}|mask ...)
9969 Configure hardware debug control. The HWDC register controls which exceptions return
9970 control back to the debugger. Possible masks are @option{all}, @option{none},
9971 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
9972 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
9975 @subsection eSi-RISC Operation
9977 @deffn {Command} {esirisc flush_caches}
9978 Flush instruction and data caches. This command requires that the target is halted
9979 when the command is issued and configured with an instruction or data cache.
9982 @subsection eSi-Trace Configuration
9984 eSi-RISC targets may be configured with support for instruction tracing. Trace
9985 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
9986 is typically employed to move trace data off-device using a high-speed
9987 peripheral (eg. SPI). Collected trace data is encoded in one of three different
9988 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
9989 fifo} must be issued along with @command{esirisc trace format} before trace data
9992 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
9993 needed, collected trace data can be dumped to a file and processed by external
9997 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
9998 for this issue is to configure DMA to copy trace data to an in-memory buffer,
9999 which can then be passed to the @command{esirisc trace analyze} and
10000 @command{esirisc trace dump} commands.
10002 It is possible to corrupt trace data when using a FIFO if the peripheral
10003 responsible for draining data from the FIFO is not fast enough. This can be
10004 managed by enabling flow control, however this can impact timing-sensitive
10005 software operation on the CPU.
10008 @deffn {Command} {esirisc trace buffer} address size [@option{wrap}]
10009 Configure trace buffer using the provided address and size. If the @option{wrap}
10010 option is specified, trace collection will continue once the end of the buffer
10011 is reached. By default, wrap is disabled.
10014 @deffn {Command} {esirisc trace fifo} address
10015 Configure trace FIFO using the provided address.
10018 @deffn {Command} {esirisc trace flow_control} (@option{enable}|@option{disable})
10019 Enable or disable stalling the CPU to collect trace data. By default, flow
10020 control is disabled.
10023 @deffn {Command} {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
10024 Configure trace format and number of PC bits to be captured. @option{pc_bits}
10025 must be within 1 and 31 as the LSB is not collected. If external tooling is used
10026 to analyze collected trace data, these values must match.
10028 Supported trace formats:
10030 @item @option{full} capture full trace data, allowing execution history and
10031 timing to be determined.
10032 @item @option{branch} capture taken branch instructions and branch target
10034 @item @option{icache} capture instruction cache misses.
10038 @deffn {Command} {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
10039 Configure trigger start condition using the provided start data and mask. A
10040 brief description of each condition is provided below; for more detail on how
10041 these values are used, see the eSi-RISC Architecture Manual.
10043 Supported conditions:
10045 @item @option{none} manual tracing (see @command{esirisc trace start}).
10046 @item @option{pc} start tracing if the PC matches start data and mask.
10047 @item @option{load} start tracing if the effective address of a load
10048 instruction matches start data and mask.
10049 @item @option{store} start tracing if the effective address of a store
10050 instruction matches start data and mask.
10051 @item @option{exception} start tracing if the EID of an exception matches start
10053 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
10054 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
10055 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
10056 @item @option{high} start tracing when an external signal is a logical high.
10057 @item @option{low} start tracing when an external signal is a logical low.
10061 @deffn {Command} {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
10062 Configure trigger stop condition using the provided stop data and mask. A brief
10063 description of each condition is provided below; for more detail on how these
10064 values are used, see the eSi-RISC Architecture Manual.
10066 Supported conditions:
10068 @item @option{none} manual tracing (see @command{esirisc trace stop}).
10069 @item @option{pc} stop tracing if the PC matches stop data and mask.
10070 @item @option{load} stop tracing if the effective address of a load
10071 instruction matches stop data and mask.
10072 @item @option{store} stop tracing if the effective address of a store
10073 instruction matches stop data and mask.
10074 @item @option{exception} stop tracing if the EID of an exception matches stop
10076 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
10077 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
10078 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
10082 @deffn {Command} {esirisc trace trigger delay} (@option{trigger}) [cycles]
10083 Configure trigger start/stop delay in clock cycles.
10085 Supported triggers:
10087 @item @option{none} no delay to start or stop collection.
10088 @item @option{start} delay @option{cycles} after trigger to start collection.
10089 @item @option{stop} delay @option{cycles} after trigger to stop collection.
10090 @item @option{both} delay @option{cycles} after both triggers to start or stop
10095 @subsection eSi-Trace Operation
10097 @deffn {Command} {esirisc trace init}
10098 Initialize trace collection. This command must be called any time the
10099 configuration changes. If a trace buffer has been configured, the contents will
10100 be overwritten when trace collection starts.
10103 @deffn {Command} {esirisc trace info}
10104 Display trace configuration.
10107 @deffn {Command} {esirisc trace status}
10108 Display trace collection status.
10111 @deffn {Command} {esirisc trace start}
10112 Start manual trace collection.
10115 @deffn {Command} {esirisc trace stop}
10116 Stop manual trace collection.
10119 @deffn {Command} {esirisc trace analyze} [address size]
10120 Analyze collected trace data. This command may only be used if a trace buffer
10121 has been configured. If a trace FIFO has been configured, trace data must be
10122 copied to an in-memory buffer identified by the @option{address} and
10123 @option{size} options using DMA.
10126 @deffn {Command} {esirisc trace dump} [address size] @file{filename}
10127 Dump collected trace data to file. This command may only be used if a trace
10128 buffer has been configured. If a trace FIFO has been configured, trace data must
10129 be copied to an in-memory buffer identified by the @option{address} and
10130 @option{size} options using DMA.
10133 @section Intel Architecture
10135 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
10136 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
10137 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
10138 software debug and the CLTAP is used for SoC level operations.
10139 Useful docs are here: https://communities.intel.com/community/makers/documentation
10141 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
10142 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
10143 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
10146 @subsection x86 32-bit specific commands
10147 The three main address spaces for x86 are memory, I/O and configuration space.
10148 These commands allow a user to read and write to the 64Kbyte I/O address space.
10150 @deffn {Command} {x86_32 idw} address
10151 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
10154 @deffn {Command} {x86_32 idh} address
10155 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
10158 @deffn {Command} {x86_32 idb} address
10159 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
10162 @deffn {Command} {x86_32 iww} address
10163 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
10166 @deffn {Command} {x86_32 iwh} address
10167 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
10170 @deffn {Command} {x86_32 iwb} address
10171 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
10174 @section OpenRISC Architecture
10176 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
10177 configured with any of the TAP / Debug Unit available.
10179 @subsection TAP and Debug Unit selection commands
10180 @deffn {Command} {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
10181 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
10183 @deffn {Command} {du_select} (@option{adv}|@option{mohor}) [option]
10184 Select between the Advanced Debug Interface and the classic one.
10186 An option can be passed as a second argument to the debug unit.
10188 When using the Advanced Debug Interface, option = 1 means the RTL core is
10189 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
10190 between bytes while doing read or write bursts.
10193 @subsection Registers commands
10194 @deffn {Command} {addreg} [name] [address] [feature] [reg_group]
10195 Add a new register in the cpu register list. This register will be
10196 included in the generated target descriptor file.
10198 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
10200 @strong{[reg_group]} can be anything. The default register list defines "system",
10201 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
10202 and "timer" groups.
10206 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
10211 @section RISC-V Architecture
10213 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
10214 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
10215 harts. (It's possible to increase this limit to 1024 by changing
10216 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
10217 Debug Specification, but there is also support for legacy targets that
10218 implement version 0.11.
10220 @subsection RISC-V Terminology
10222 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
10223 another hart, or may be a separate core. RISC-V treats those the same, and
10224 OpenOCD exposes each hart as a separate core.
10226 @subsection Vector Registers
10228 For harts that implement the vector extension, OpenOCD provides access to the
10229 relevant CSRs, as well as the vector registers (v0-v31). The size of each
10230 vector register is dependent on the value of vlenb. RISC-V allows each vector
10231 register to be divided into selected-width elements, and this division can be
10232 changed at run-time. Because OpenOCD cannot update register definitions at
10233 run-time, it exposes each vector register to gdb as a union of fields of
10234 vectors so that users can easily access individual bytes, shorts, words,
10235 longs, and quads inside each vector register. It is left to gdb or
10236 higher-level debuggers to present this data in a more intuitive format.
10238 In the XML register description, the vector registers (when vlenb=16) look as
10242 <feature name="org.gnu.gdb.riscv.vector">
10243 <vector id="bytes" type="uint8" count="16"/>
10244 <vector id="shorts" type="uint16" count="8"/>
10245 <vector id="words" type="uint32" count="4"/>
10246 <vector id="longs" type="uint64" count="2"/>
10247 <vector id="quads" type="uint128" count="1"/>
10248 <union id="riscv_vector">
10249 <field name="b" type="bytes"/>
10250 <field name="s" type="shorts"/>
10251 <field name="w" type="words"/>
10252 <field name="l" type="longs"/>
10253 <field name="q" type="quads"/>
10255 <reg name="v0" bitsize="128" regnum="4162" save-restore="no"
10256 type="riscv_vector" group="vector"/>
10258 <reg name="v31" bitsize="128" regnum="4193" save-restore="no"
10259 type="riscv_vector" group="vector"/>
10263 @subsection RISC-V Debug Configuration Commands
10265 @deffn {Config Command} {riscv expose_csrs} n[-m|=name] [...]
10266 Configure which CSRs to expose in addition to the standard ones. The CSRs to expose
10267 can be specified as individual register numbers or register ranges (inclusive). For the
10268 individually listed CSRs, a human-readable name can optionally be set using the @code{n=name}
10269 syntax, which will get @code{csr_} prepended to it. If no name is provided, the register will be
10270 named @code{csr<n>}.
10272 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
10273 and then only if the corresponding extension appears to be implemented. This
10274 command can be used if OpenOCD gets this wrong, or if the target implements custom
10278 # Expose a single RISC-V CSR number 128 under the name "csr128":
10279 $_TARGETNAME expose_csrs 128
10281 # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
10282 $_TARGETNAME expose_csrs 128-132
10284 # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
10285 $_TARGETNAME expose_csrs 1996=myregister
10289 @deffn {Config Command} {riscv expose_custom} n[-m|=name] [...]
10290 The RISC-V Debug Specification allows targets to expose custom registers
10291 through abstract commands. (See Section 3.5.1.1 in that document.) This command
10292 configures individual registers or register ranges (inclusive) that shall be exposed.
10293 Number 0 indicates the first custom register, whose abstract command number is 0xc000.
10294 For individually listed registers, a human-readable name can be optionally provided
10295 using the @code{n=name} syntax, which will get @code{custom_} prepended to it. If no
10296 name is provided, the register will be named @code{custom<n>}.
10299 # Expose one RISC-V custom register with number 0xc010 (0xc000 + 16)
10300 # under the name "custom16":
10301 $_TARGETNAME expose_custom 16
10303 # Expose a range of RISC-V custom registers with numbers 0xc010 .. 0xc018
10304 # (0xc000+16 .. 0xc000+24) under the names "custom16" through "custom24":
10305 $_TARGETNAME expose_custom 16-24
10307 # Expose one RISC-V custom register with number 0xc020 (0xc000 + 32) under
10308 # user-defined name "custom_myregister":
10309 $_TARGETNAME expose_custom 32=myregister
10313 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
10314 Set the wall-clock timeout (in seconds) for individual commands. The default
10315 should work fine for all but the slowest targets (eg. simulators).
10318 @deffn {Command} {riscv set_reset_timeout_sec} [seconds]
10319 Set the maximum time to wait for a hart to come out of reset after reset is
10323 @deffn {Command} {riscv set_scratch_ram} none|[address]
10324 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
10325 This is used to access 64-bit floating point registers on 32-bit targets.
10328 @deffn Command {riscv set_mem_access} method1 [method2] [method3]
10329 Specify which RISC-V memory access method(s) shall be used, and in which order
10330 of priority. At least one method must be specified.
10332 Available methods are:
10334 @item @code{progbuf} - Use RISC-V Debug Program Buffer to access memory.
10335 @item @code{sysbus} - Access memory via RISC-V Debug System Bus interface.
10336 @item @code{abstract} - Access memory via RISC-V Debug abstract commands.
10339 By default, all memory access methods are enabled in the following order:
10340 @code{progbuf sysbus abstract}.
10342 This command can be used to change the memory access methods if the default
10343 behavior is not suitable for a particular target.
10346 @deffn {Command} {riscv set_enable_virtual} on|off
10347 When on, memory accesses are performed on physical or virtual memory depending
10348 on the current system configuration. When off (default), all memory accessses are performed
10349 on physical memory.
10352 @deffn {Command} {riscv set_enable_virt2phys} on|off
10353 When on (default), memory accesses are performed on physical or virtual memory
10354 depending on the current satp configuration. When off, all memory accessses are
10355 performed on physical memory.
10358 @deffn {Command} {riscv resume_order} normal|reversed
10359 Some software assumes all harts are executing nearly continuously. Such
10360 software may be sensitive to the order that harts are resumed in. On harts
10361 that don't support hasel, this option allows the user to choose the order the
10362 harts are resumed in. If you are using this option, it's probably masking a
10363 race condition problem in your code.
10365 Normal order is from lowest hart index to highest. This is the default
10366 behavior. Reversed order is from highest hart index to lowest.
10369 @deffn {Command} {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
10370 Set the IR value for the specified JTAG register. This is useful, for
10371 example, when using the existing JTAG interface on a Xilinx FPGA by
10372 way of BSCANE2 primitives that only permit a limited selection of IR
10375 When utilizing version 0.11 of the RISC-V Debug Specification,
10376 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
10377 and DBUS registers, respectively.
10380 @deffn {Command} {riscv use_bscan_tunnel} value
10381 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
10382 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
10385 @deffn {Command} {riscv set_ebreakm} on|off
10386 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
10387 OpenOCD. When off, they generate a breakpoint exception handled internally.
10390 @deffn {Command} {riscv set_ebreaks} on|off
10391 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
10392 OpenOCD. When off, they generate a breakpoint exception handled internally.
10395 @deffn {Command} {riscv set_ebreaku} on|off
10396 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
10397 OpenOCD. When off, they generate a breakpoint exception handled internally.
10400 @subsection RISC-V Authentication Commands
10402 The following commands can be used to authenticate to a RISC-V system. Eg. a
10403 trivial challenge-response protocol could be implemented as follows in a
10404 configuration file, immediately following @command{init}:
10406 set challenge [riscv authdata_read]
10407 riscv authdata_write [expr @{$challenge + 1@}]
10410 @deffn {Command} {riscv authdata_read}
10411 Return the 32-bit value read from authdata.
10414 @deffn {Command} {riscv authdata_write} value
10415 Write the 32-bit value to authdata.
10418 @subsection RISC-V DMI Commands
10420 The following commands allow direct access to the Debug Module Interface, which
10421 can be used to interact with custom debug features.
10423 @deffn {Command} {riscv dmi_read} address
10424 Perform a 32-bit DMI read at address, returning the value.
10427 @deffn {Command} {riscv dmi_write} address value
10428 Perform a 32-bit DMI write of value at address.
10431 @section ARC Architecture
10434 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
10435 designers can optimize for a wide range of uses, from deeply embedded to
10436 high-performance host applications in a variety of market segments. See more
10437 at: @url{http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx}.
10438 OpenOCD currently supports ARC EM processors.
10439 There is a set ARC-specific OpenOCD commands that allow low-level
10440 access to the core and provide necessary support for ARC extensibility and
10441 configurability capabilities. ARC processors has much more configuration
10442 capabilities than most of the other processors and in addition there is an
10443 extension interface that allows SoC designers to add custom registers and
10444 instructions. For the OpenOCD that mostly means that set of core and AUX
10445 registers in target will vary and is not fixed for a particular processor
10446 model. To enable extensibility several TCL commands are provided that allow to
10447 describe those optional registers in OpenOCD configuration files. Moreover
10448 those commands allow for a dynamic target features discovery.
10451 @subsection General ARC commands
10453 @deffn {Config Command} {arc add-reg} configparams
10455 Add a new register to processor target. By default newly created register is
10456 marked as not existing. @var{configparams} must have following required
10461 @item @code{-name} name
10462 @*Name of a register.
10464 @item @code{-num} number
10465 @*Architectural register number: core register number or AUX register number.
10467 @item @code{-feature} XML_feature
10468 @*Name of GDB XML target description feature.
10472 @var{configparams} may have following optional arguments:
10476 @item @code{-gdbnum} number
10477 @*GDB register number. It is recommended to not assign GDB register number
10478 manually, because there would be a risk that two register will have same
10479 number. When register GDB number is not set with this option, then register
10480 will get a previous register number + 1. This option is required only for those
10481 registers that must be at particular address expected by GDB.
10484 @*This option specifies that register is a core registers. If not - this is an
10485 AUX register. AUX registers and core registers reside in different address
10489 @*This options specifies that register is a BCR register. BCR means Build
10490 Configuration Registers - this is a special type of AUX registers that are read
10491 only and non-volatile, that is - they never change their value. Therefore OpenOCD
10492 never invalidates values of those registers in internal caches. Because BCR is a
10493 type of AUX registers, this option cannot be used with @code{-core}.
10495 @item @code{-type} type_name
10496 @*Name of type of this register. This can be either one of the basic GDB types,
10497 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
10500 @* If specified then this is a "general" register. General registers are always
10501 read by OpenOCD on context save (when core has just been halted) and is always
10502 transferred to GDB client in a response to g-packet. Contrary to this,
10503 non-general registers are read and sent to GDB client on-demand. In general it
10504 is not recommended to apply this option to custom registers.
10510 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
10511 Adds new register type of ``flags'' class. ``Flags'' types can contain only
10512 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
10515 @anchor{add-reg-type-struct}
10516 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
10517 Adds new register type of ``struct'' class. ``Struct'' types can contain either
10518 bit-fields or fields of other types, however at the moment only bit fields are
10519 supported. Structure bit field definition looks like @code{-bitfield name
10523 @deffn {Command} {arc get-reg-field} reg-name field-name
10524 Returns value of bit-field in a register. Register must be ``struct'' register
10525 type, @xref{add-reg-type-struct}. command definition.
10528 @deffn {Command} {arc set-reg-exists} reg-names...
10529 Specify that some register exists. Any amount of names can be passed
10530 as an argument for a single command invocation.
10533 @subsection ARC JTAG commands
10535 @deffn {Command} {arc jtag set-aux-reg} regnum value
10536 This command writes value to AUX register via its number. This command access
10537 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10538 therefore it is unsafe to use if that register can be operated by other means.
10542 @deffn {Command} {arc jtag set-core-reg} regnum value
10543 This command is similar to @command{arc jtag set-aux-reg} but is for core
10547 @deffn {Command} {arc jtag get-aux-reg} regnum
10548 This command returns the value storded in AUX register via its number. This commands access
10549 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10550 therefore it is unsafe to use if that register can be operated by other means.
10554 @deffn {Command} {arc jtag get-core-reg} regnum
10555 This command is similar to @command{arc jtag get-aux-reg} but is for core
10559 @section STM8 Architecture
10560 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
10561 STMicroelectronics, based on a proprietary 8-bit core architecture.
10563 OpenOCD supports debugging STM8 through the STMicroelectronics debug
10564 protocol SWIM, @pxref{swimtransport,,SWIM}.
10566 @anchor{softwaredebugmessagesandtracing}
10567 @section Software Debug Messages and Tracing
10568 @cindex Linux-ARM DCC support
10572 OpenOCD can process certain requests from target software, when
10573 the target uses appropriate libraries.
10574 The most powerful mechanism is semihosting, but there is also
10575 a lighter weight mechanism using only the DCC channel.
10577 Currently @command{target_request debugmsgs}
10578 is supported only for @option{arm7_9} and @option{cortex_m} cores.
10579 These messages are received as part of target polling, so
10580 you need to have @command{poll on} active to receive them.
10581 They are intrusive in that they will affect program execution
10582 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
10584 See @file{libdcc} in the contrib dir for more details.
10585 In addition to sending strings, characters, and
10586 arrays of various size integers from the target,
10587 @file{libdcc} also exports a software trace point mechanism.
10588 The target being debugged may
10589 issue trace messages which include a 24-bit @dfn{trace point} number.
10590 Trace point support includes two distinct mechanisms,
10591 each supported by a command:
10594 @item @emph{History} ... A circular buffer of trace points
10595 can be set up, and then displayed at any time.
10596 This tracks where code has been, which can be invaluable in
10597 finding out how some fault was triggered.
10599 The buffer may overflow, since it collects records continuously.
10600 It may be useful to use some of the 24 bits to represent a
10601 particular event, and other bits to hold data.
10603 @item @emph{Counting} ... An array of counters can be set up,
10604 and then displayed at any time.
10605 This can help establish code coverage and identify hot spots.
10607 The array of counters is directly indexed by the trace point
10608 number, so trace points with higher numbers are not counted.
10611 Linux-ARM kernels have a ``Kernel low-level debugging
10612 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
10613 depends on CONFIG_DEBUG_LL) which uses this mechanism to
10614 deliver messages before a serial console can be activated.
10615 This is not the same format used by @file{libdcc}.
10616 Other software, such as the U-Boot boot loader, sometimes
10617 does the same thing.
10619 @deffn {Command} {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
10620 Displays current handling of target DCC message requests.
10621 These messages may be sent to the debugger while the target is running.
10622 The optional @option{enable} and @option{charmsg} parameters
10623 both enable the messages, while @option{disable} disables them.
10625 With @option{charmsg} the DCC words each contain one character,
10626 as used by Linux with CONFIG_DEBUG_ICEDCC;
10627 otherwise the libdcc format is used.
10630 @deffn {Command} {trace history} [@option{clear}|count]
10631 With no parameter, displays all the trace points that have triggered
10632 in the order they triggered.
10633 With the parameter @option{clear}, erases all current trace history records.
10634 With a @var{count} parameter, allocates space for that many
10638 @deffn {Command} {trace point} [@option{clear}|identifier]
10639 With no parameter, displays all trace point identifiers and how many times
10640 they have been triggered.
10641 With the parameter @option{clear}, erases all current trace point counters.
10642 With a numeric @var{identifier} parameter, creates a new a trace point counter
10643 and associates it with that identifier.
10645 @emph{Important:} The identifier and the trace point number
10646 are not related except by this command.
10647 These trace point numbers always start at zero (from server startup,
10648 or after @command{trace point clear}) and count up from there.
10652 @node JTAG Commands
10653 @chapter JTAG Commands
10654 @cindex JTAG Commands
10655 Most general purpose JTAG commands have been presented earlier.
10656 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
10657 Lower level JTAG commands, as presented here,
10658 may be needed to work with targets which require special
10659 attention during operations such as reset or initialization.
10661 To use these commands you will need to understand some
10662 of the basics of JTAG, including:
10665 @item A JTAG scan chain consists of a sequence of individual TAP
10666 devices such as a CPUs.
10667 @item Control operations involve moving each TAP through the same
10668 standard state machine (in parallel)
10669 using their shared TMS and clock signals.
10670 @item Data transfer involves shifting data through the chain of
10671 instruction or data registers of each TAP, writing new register values
10672 while the reading previous ones.
10673 @item Data register sizes are a function of the instruction active in
10674 a given TAP, while instruction register sizes are fixed for each TAP.
10675 All TAPs support a BYPASS instruction with a single bit data register.
10676 @item The way OpenOCD differentiates between TAP devices is by
10677 shifting different instructions into (and out of) their instruction
10681 @section Low Level JTAG Commands
10683 These commands are used by developers who need to access
10684 JTAG instruction or data registers, possibly controlling
10685 the order of TAP state transitions.
10686 If you're not debugging OpenOCD internals, or bringing up a
10687 new JTAG adapter or a new type of TAP device (like a CPU or
10688 JTAG router), you probably won't need to use these commands.
10689 In a debug session that doesn't use JTAG for its transport protocol,
10690 these commands are not available.
10692 @deffn {Command} {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
10693 Loads the data register of @var{tap} with a series of bit fields
10694 that specify the entire register.
10695 Each field is @var{numbits} bits long with
10696 a numeric @var{value} (hexadecimal encouraged).
10697 The return value holds the original value of each
10700 For example, a 38 bit number might be specified as one
10701 field of 32 bits then one of 6 bits.
10702 @emph{For portability, never pass fields which are more
10703 than 32 bits long. Many OpenOCD implementations do not
10704 support 64-bit (or larger) integer values.}
10706 All TAPs other than @var{tap} must be in BYPASS mode.
10707 The single bit in their data registers does not matter.
10709 When @var{tap_state} is specified, the JTAG state machine is left
10711 For example @sc{drpause} might be specified, so that more
10712 instructions can be issued before re-entering the @sc{run/idle} state.
10713 If the end state is not specified, the @sc{run/idle} state is entered.
10716 OpenOCD does not record information about data register lengths,
10717 so @emph{it is important that you get the bit field lengths right}.
10718 Remember that different JTAG instructions refer to different
10719 data registers, which may have different lengths.
10720 Moreover, those lengths may not be fixed;
10721 the SCAN_N instruction can change the length of
10722 the register accessed by the INTEST instruction
10723 (by connecting a different scan chain).
10727 @deffn {Command} {flush_count}
10728 Returns the number of times the JTAG queue has been flushed.
10729 This may be used for performance tuning.
10731 For example, flushing a queue over USB involves a
10732 minimum latency, often several milliseconds, which does
10733 not change with the amount of data which is written.
10734 You may be able to identify performance problems by finding
10735 tasks which waste bandwidth by flushing small transfers too often,
10736 instead of batching them into larger operations.
10739 @deffn {Command} {irscan} [tap instruction]+ [@option{-endstate} tap_state]
10740 For each @var{tap} listed, loads the instruction register
10741 with its associated numeric @var{instruction}.
10742 (The number of bits in that instruction may be displayed
10743 using the @command{scan_chain} command.)
10744 For other TAPs, a BYPASS instruction is loaded.
10746 When @var{tap_state} is specified, the JTAG state machine is left
10748 For example @sc{irpause} might be specified, so the data register
10749 can be loaded before re-entering the @sc{run/idle} state.
10750 If the end state is not specified, the @sc{run/idle} state is entered.
10753 OpenOCD currently supports only a single field for instruction
10754 register values, unlike data register values.
10755 For TAPs where the instruction register length is more than 32 bits,
10756 portable scripts currently must issue only BYPASS instructions.
10760 @deffn {Command} {pathmove} start_state [next_state ...]
10761 Start by moving to @var{start_state}, which
10762 must be one of the @emph{stable} states.
10763 Unless it is the only state given, this will often be the
10764 current state, so that no TCK transitions are needed.
10765 Then, in a series of single state transitions
10766 (conforming to the JTAG state machine) shift to
10767 each @var{next_state} in sequence, one per TCK cycle.
10768 The final state must also be stable.
10771 @deffn {Command} {runtest} @var{num_cycles}
10772 Move to the @sc{run/idle} state, and execute at least
10773 @var{num_cycles} of the JTAG clock (TCK).
10774 Instructions often need some time
10775 to execute before they take effect.
10778 @c tms_sequence (short|long)
10779 @c ... temporary, debug-only, other than USBprog bug workaround...
10781 @deffn {Command} {verify_ircapture} (@option{enable}|@option{disable})
10782 Verify values captured during @sc{ircapture} and returned
10783 during IR scans. Default is enabled, but this can be
10784 overridden by @command{verify_jtag}.
10785 This flag is ignored when validating JTAG chain configuration.
10788 @deffn {Command} {verify_jtag} (@option{enable}|@option{disable})
10789 Enables verification of DR and IR scans, to help detect
10790 programming errors. For IR scans, @command{verify_ircapture}
10791 must also be enabled.
10792 Default is enabled.
10795 @section TAP state names
10796 @cindex TAP state names
10798 The @var{tap_state} names used by OpenOCD in the @command{drscan},
10799 @command{irscan}, and @command{pathmove} commands are the same
10800 as those used in SVF boundary scan documents, except that
10801 SVF uses @sc{idle} instead of @sc{run/idle}.
10804 @item @b{RESET} ... @emph{stable} (with TMS high);
10805 acts as if TRST were pulsed
10806 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
10808 @item @b{DRCAPTURE}
10809 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
10810 through the data register
10812 @item @b{DRPAUSE} ... @emph{stable}; data register ready
10813 for update or more shifting
10817 @item @b{IRCAPTURE}
10818 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
10819 through the instruction register
10821 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
10822 for update or more shifting
10827 Note that only six of those states are fully ``stable'' in the
10828 face of TMS fixed (low except for @sc{reset})
10829 and a free-running JTAG clock. For all the
10830 others, the next TCK transition changes to a new state.
10833 @item From @sc{drshift} and @sc{irshift}, clock transitions will
10834 produce side effects by changing register contents. The values
10835 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
10836 may not be as expected.
10837 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
10838 choices after @command{drscan} or @command{irscan} commands,
10839 since they are free of JTAG side effects.
10840 @item @sc{run/idle} may have side effects that appear at non-JTAG
10841 levels, such as advancing the ARM9E-S instruction pipeline.
10842 Consult the documentation for the TAP(s) you are working with.
10845 @node Boundary Scan Commands
10846 @chapter Boundary Scan Commands
10848 One of the original purposes of JTAG was to support
10849 boundary scan based hardware testing.
10850 Although its primary focus is to support On-Chip Debugging,
10851 OpenOCD also includes some boundary scan commands.
10853 @section SVF: Serial Vector Format
10854 @cindex Serial Vector Format
10857 The Serial Vector Format, better known as @dfn{SVF}, is a
10858 way to represent JTAG test patterns in text files.
10859 In a debug session using JTAG for its transport protocol,
10860 OpenOCD supports running such test files.
10862 @deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
10863 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
10864 This issues a JTAG reset (Test-Logic-Reset) and then
10865 runs the SVF script from @file{filename}.
10867 Arguments can be specified in any order; the optional dash doesn't
10868 affect their semantics.
10872 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
10873 specified by the SVF file with HIR, TIR, HDR and TDR commands;
10874 instead, calculate them automatically according to the current JTAG
10875 chain configuration, targeting @var{tapname};
10876 @item @option{[-]quiet} do not log every command before execution;
10877 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
10878 on the real interface;
10879 @item @option{[-]progress} enable progress indication;
10880 @item @option{[-]ignore_error} continue execution despite TDO check
10885 @section XSVF: Xilinx Serial Vector Format
10886 @cindex Xilinx Serial Vector Format
10889 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
10890 binary representation of SVF which is optimized for use with
10892 In a debug session using JTAG for its transport protocol,
10893 OpenOCD supports running such test files.
10895 @quotation Important
10896 Not all XSVF commands are supported.
10899 @deffn {Command} {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
10900 This issues a JTAG reset (Test-Logic-Reset) and then
10901 runs the XSVF script from @file{filename}.
10902 When a @var{tapname} is specified, the commands are directed at
10904 When @option{virt2} is specified, the @sc{xruntest} command counts
10905 are interpreted as TCK cycles instead of microseconds.
10906 Unless the @option{quiet} option is specified,
10907 messages are logged for comments and some retries.
10910 The OpenOCD sources also include two utility scripts
10911 for working with XSVF; they are not currently installed
10912 after building the software.
10913 You may find them useful:
10916 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
10917 syntax understood by the @command{xsvf} command; see notes below.
10918 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
10919 understands the OpenOCD extensions.
10922 The input format accepts a handful of non-standard extensions.
10923 These include three opcodes corresponding to SVF extensions
10924 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
10925 two opcodes supporting a more accurate translation of SVF
10926 (XTRST, XWAITSTATE).
10927 If @emph{xsvfdump} shows a file is using those opcodes, it
10928 probably will not be usable with other XSVF tools.
10931 @section IPDBG: JTAG-Host server
10932 @cindex IPDBG JTAG-Host server
10935 IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary
10936 waveform generator. These are synthesize-able hardware descriptions of
10937 logic circuits in addition to software for control, visualization and further analysis.
10938 In a session using JTAG for its transport protocol, OpenOCD supports the function
10939 of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the
10940 control-software. For more details see @url{http://ipdbg.org}.
10942 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}]
10943 Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order.
10947 @item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start).
10948 @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}.
10949 @item @option{-hub @var{ir_value}} states that the JTAG hub is
10950 reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}.
10951 @item @option{-port @var{number}} tcp port number where the JTAG-Host is listening.
10952 @item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub.
10953 @item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a
10954 specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an
10955 access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second
10956 parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to
10957 shift data through vir can be configured.
10963 ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4
10965 Starts a server listening on tcp-port 4242 which connects to tool 4.
10966 The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board).
10969 ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1
10971 Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1).
10972 The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5).
10974 @node Utility Commands
10975 @chapter Utility Commands
10976 @cindex Utility Commands
10978 @section RAM testing
10979 @cindex RAM testing
10981 There is often a need to stress-test random access memory (RAM) for
10982 errors. OpenOCD comes with a Tcl implementation of well-known memory
10983 testing procedures allowing the detection of all sorts of issues with
10984 electrical wiring, defective chips, PCB layout and other common
10987 To use them, you usually need to initialise your RAM controller first;
10988 consult your SoC's documentation to get the recommended list of
10989 register operations and translate them to the corresponding
10990 @command{mww}/@command{mwb} commands.
10992 Load the memory testing functions with
10995 source [find tools/memtest.tcl]
10998 to get access to the following facilities:
11000 @deffn {Command} {memTestDataBus} address
11001 Test the data bus wiring in a memory region by performing a walking
11002 1's test at a fixed address within that region.
11005 @deffn {Command} {memTestAddressBus} baseaddress size
11006 Perform a walking 1's test on the relevant bits of the address and
11007 check for aliasing. This test will find single-bit address failures
11008 such as stuck-high, stuck-low, and shorted pins.
11011 @deffn {Command} {memTestDevice} baseaddress size
11012 Test the integrity of a physical memory device by performing an
11013 increment/decrement test over the entire region. In the process every
11014 storage bit in the device is tested as zero and as one.
11017 @deffn {Command} {runAllMemTests} baseaddress size
11018 Run all of the above tests over a specified memory region.
11021 @section Firmware recovery helpers
11022 @cindex Firmware recovery
11024 OpenOCD includes an easy-to-use script to facilitate mass-market
11025 devices recovery with JTAG.
11027 For quickstart instructions run:
11029 openocd -f tools/firmware-recovery.tcl -c firmware_help
11032 @node GDB and OpenOCD
11033 @chapter GDB and OpenOCD
11035 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
11036 to debug remote targets.
11037 Setting up GDB to work with OpenOCD can involve several components:
11040 @item The OpenOCD server support for GDB may need to be configured.
11041 @xref{gdbconfiguration,,GDB Configuration}.
11042 @item GDB's support for OpenOCD may need configuration,
11043 as shown in this chapter.
11044 @item If you have a GUI environment like Eclipse,
11045 that also will probably need to be configured.
11048 Of course, the version of GDB you use will need to be one which has
11049 been built to know about the target CPU you're using. It's probably
11050 part of the tool chain you're using. For example, if you are doing
11051 cross-development for ARM on an x86 PC, instead of using the native
11052 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
11053 if that's the tool chain used to compile your code.
11055 @section Connecting to GDB
11056 @cindex Connecting to GDB
11057 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
11058 instance GDB 6.3 has a known bug that produces bogus memory access
11059 errors, which has since been fixed; see
11060 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
11062 OpenOCD can communicate with GDB in two ways:
11066 A socket (TCP/IP) connection is typically started as follows:
11068 target extended-remote localhost:3333
11070 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
11072 The extended remote protocol is a super-set of the remote protocol and should
11073 be the preferred choice. More details are available in GDB documentation
11074 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
11076 To speed-up typing, any GDB command can be abbreviated, including the extended
11077 remote command above that becomes:
11082 @b{Note:} If any backward compatibility issue requires using the old remote
11083 protocol in place of the extended remote one, the former protocol is still
11084 available through the command:
11086 target remote localhost:3333
11090 A pipe connection is typically started as follows:
11092 target extended-remote | \
11093 openocd -c "gdb_port pipe; log_output openocd.log"
11095 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
11096 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
11097 session. log_output sends the log output to a file to ensure that the pipe is
11098 not saturated when using higher debug level outputs.
11101 To list the available OpenOCD commands type @command{monitor help} on the
11104 @section Sample GDB session startup
11106 With the remote protocol, GDB sessions start a little differently
11107 than they do when you're debugging locally.
11108 Here's an example showing how to start a debug session with a
11110 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
11111 Most programs would be written into flash (address 0) and run from there.
11114 $ arm-none-eabi-gdb example.elf
11115 (gdb) target extended-remote localhost:3333
11116 Remote debugging using localhost:3333
11118 (gdb) monitor reset halt
11121 Loading section .vectors, size 0x100 lma 0x20000000
11122 Loading section .text, size 0x5a0 lma 0x20000100
11123 Loading section .data, size 0x18 lma 0x200006a0
11124 Start address 0x2000061c, load size 1720
11125 Transfer rate: 22 KB/sec, 573 bytes/write.
11131 You could then interrupt the GDB session to make the program break,
11132 type @command{where} to show the stack, @command{list} to show the
11133 code around the program counter, @command{step} through code,
11134 set breakpoints or watchpoints, and so on.
11136 @section Configuring GDB for OpenOCD
11138 OpenOCD supports the gdb @option{qSupported} packet, this enables information
11139 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
11140 packet size and the device's memory map.
11141 You do not need to configure the packet size by hand,
11142 and the relevant parts of the memory map should be automatically
11143 set up when you declare (NOR) flash banks.
11145 However, there are other things which GDB can't currently query.
11146 You may need to set those up by hand.
11147 As OpenOCD starts up, you will often see a line reporting
11151 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
11154 You can pass that information to GDB with these commands:
11157 set remote hardware-breakpoint-limit 6
11158 set remote hardware-watchpoint-limit 4
11161 With that particular hardware (Cortex-M3) the hardware breakpoints
11162 only work for code running from flash memory. Most other ARM systems
11163 do not have such restrictions.
11165 Rather than typing such commands interactively, you may prefer to
11166 save them in a file and have GDB execute them as it starts, perhaps
11167 using a @file{.gdbinit} in your project directory or starting GDB
11168 using @command{gdb -x filename}.
11170 @section Programming using GDB
11171 @cindex Programming using GDB
11172 @anchor{programmingusinggdb}
11174 By default the target memory map is sent to GDB. This can be disabled by
11175 the following OpenOCD configuration option:
11177 gdb_memory_map disable
11179 For this to function correctly a valid flash configuration must also be set
11180 in OpenOCD. For faster performance you should also configure a valid
11183 Informing GDB of the memory map of the target will enable GDB to protect any
11184 flash areas of the target and use hardware breakpoints by default. This means
11185 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
11186 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
11188 To view the configured memory map in GDB, use the GDB command @option{info mem}.
11189 All other unassigned addresses within GDB are treated as RAM.
11191 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
11192 This can be changed to the old behaviour by using the following GDB command
11194 set mem inaccessible-by-default off
11197 If @command{gdb_flash_program enable} is also used, GDB will be able to
11198 program any flash memory using the vFlash interface.
11200 GDB will look at the target memory map when a load command is given, if any
11201 areas to be programmed lie within the target flash area the vFlash packets
11204 If the target needs configuring before GDB programming, set target
11205 event gdb-flash-erase-start:
11207 $_TARGETNAME configure -event gdb-flash-erase-start BODY
11209 @xref{targetevents,,Target Events}, for other GDB programming related events.
11211 To verify any flash programming the GDB command @option{compare-sections}
11214 @section Using GDB as a non-intrusive memory inspector
11215 @cindex Using GDB as a non-intrusive memory inspector
11216 @anchor{gdbmeminspect}
11218 If your project controls more than a blinking LED, let's say a heavy industrial
11219 robot or an experimental nuclear reactor, stopping the controlling process
11220 just because you want to attach GDB is not a good option.
11222 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
11223 Though there is a possible setup where the target does not get stopped
11224 and GDB treats it as it were running.
11225 If the target supports background access to memory while it is running,
11226 you can use GDB in this mode to inspect memory (mainly global variables)
11227 without any intrusion of the target process.
11229 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
11230 Place following command after target configuration:
11232 $_TARGETNAME configure -event gdb-attach @{@}
11235 If any of installed flash banks does not support probe on running target,
11236 switch off gdb_memory_map:
11238 gdb_memory_map disable
11241 Ensure GDB is configured without interrupt-on-connect.
11242 Some GDB versions set it by default, some does not.
11244 set remote interrupt-on-connect off
11247 If you switched gdb_memory_map off, you may want to setup GDB memory map
11248 manually or issue @command{set mem inaccessible-by-default off}
11250 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
11251 of a running target. Do not use GDB commands @command{continue},
11252 @command{step} or @command{next} as they synchronize GDB with your target
11253 and GDB would require stopping the target to get the prompt back.
11255 Do not use this mode under an IDE like Eclipse as it caches values of
11256 previously shown variables.
11258 It's also possible to connect more than one GDB to the same target by the
11259 target's configuration option @code{-gdb-max-connections}. This allows, for
11260 example, one GDB to run a script that continuously polls a set of variables
11261 while other GDB can be used interactively. Be extremely careful in this case,
11262 because the two GDB can easily get out-of-sync.
11264 @section RTOS Support
11265 @cindex RTOS Support
11266 @anchor{gdbrtossupport}
11268 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
11269 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
11271 @xref{Threads, Debugging Programs with Multiple Threads,
11272 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
11275 @* An example setup is below:
11278 $_TARGETNAME configure -rtos auto
11281 This will attempt to auto detect the RTOS within your application.
11283 Currently supported rtos's include:
11285 @item @option{eCos}
11286 @item @option{ThreadX}
11287 @item @option{FreeRTOS}
11288 @item @option{linux}
11289 @item @option{ChibiOS}
11290 @item @option{embKernel}
11292 @item @option{uCOS-III}
11293 @item @option{nuttx}
11294 @item @option{RIOT}
11295 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
11296 @item @option{Zephyr}
11299 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
11300 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
11304 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
11305 @item ThreadX symbols
11306 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
11307 @item FreeRTOS symbols
11309 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
11310 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
11311 uxCurrentNumberOfTasks, uxTopUsedPriority.
11313 @item linux symbols
11315 @item ChibiOS symbols
11316 rlist, ch_debug, chSysInit.
11317 @item embKernel symbols
11318 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
11319 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
11321 _mqx_kernel_data, MQX_init_struct.
11322 @item uC/OS-III symbols
11323 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
11324 @item nuttx symbols
11325 g_readytorun, g_tasklisttable.
11328 sched_threads, sched_num_threads, sched_active_pid, max_threads,
11331 @item Zephyr symbols
11332 _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
11335 For most RTOS supported the above symbols will be exported by default. However for
11336 some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken.
11338 Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols
11339 with information needed in order to build the list of threads.
11341 FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked
11342 along with the project:
11346 contrib/rtos-helpers/FreeRTOS-openocd.c
11348 contrib/rtos-helpers/uCOS-III-openocd.c
11351 @anchor{usingopenocdsmpwithgdb}
11352 @section Using OpenOCD SMP with GDB
11356 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
11357 ("hardware threads") in an SMP system as threads to GDB. With this extension,
11358 GDB can be used to inspect the state of an SMP system in a natural way.
11359 After halting the system, using the GDB command @command{info threads} will
11360 list the context of each active CPU core in the system. GDB's @command{thread}
11361 command can be used to switch the view to a different CPU core.
11362 The @command{step} and @command{stepi} commands can be used to step a specific core
11363 while other cores are free-running or remain halted, depending on the
11364 scheduler-locking mode configured in GDB.
11366 @section Legacy SMP core switching support
11368 This method is deprecated in favor of the @emph{hwthread} pseudo RTOS.
11371 For SMP support following GDB serial protocol packet have been defined :
11373 @item j - smp status request
11374 @item J - smp set request
11377 OpenOCD implements :
11379 @item @option{jc} packet for reading core id displayed by
11380 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
11381 @option{E01} for target not smp.
11382 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
11383 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
11384 for target not smp or @option{OK} on success.
11387 Handling of this packet within GDB can be done :
11389 @item by the creation of an internal variable (i.e @option{_core}) by mean
11390 of function allocate_computed_value allowing following GDB command.
11393 #Jc01 packet is sent
11395 #jc packet is sent and result is affected in $
11398 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
11399 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
11402 # toggle0 : force display of coreid 0
11408 # toggle1 : force display of coreid 1
11417 @node Tcl Scripting API
11418 @chapter Tcl Scripting API
11419 @cindex Tcl Scripting API
11420 @cindex Tcl scripts
11423 Tcl commands are stateless; e.g. the @command{telnet} command has
11424 a concept of currently active target, the Tcl API proc's take this sort
11425 of state information as an argument to each proc.
11427 There are three main types of return values: single value, name value
11428 pair list and lists.
11430 Name value pair. The proc 'foo' below returns a name/value pair
11434 > set foo(me) Duane
11435 > set foo(you) Oyvind
11436 > set foo(mouse) Micky
11437 > set foo(duck) Donald
11449 me Duane you Oyvind mouse Micky duck Donald
11452 Thus, to get the names of the associative array is easy:
11455 foreach { name value } [set foo] {
11456 puts "Name: $name, Value: $value"
11460 Lists returned should be relatively small. Otherwise, a range
11461 should be passed in to the proc in question.
11463 @section Internal low-level Commands
11465 By "low-level", we mean commands that a human would typically not
11469 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
11471 Read memory and return as a Tcl array for script processing
11472 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
11474 Convert a Tcl array to memory locations and write the values
11475 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
11477 Return information about the flash banks
11479 @item @b{capture} <@var{command}>
11481 Run <@var{command}> and return full log output that was produced during
11482 its execution. Example:
11485 > capture "reset init"
11490 OpenOCD commands can consist of two words, e.g. "flash banks". The
11491 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
11492 called "flash_banks".
11494 @section Tcl RPC server
11497 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
11498 commands and receive the results.
11500 To access it, your application needs to connect to a configured TCP port
11501 (see @command{tcl_port}). Then it can pass any string to the
11502 interpreter terminating it with @code{0x1a} and wait for the return
11503 value (it will be terminated with @code{0x1a} as well). This can be
11504 repeated as many times as desired without reopening the connection.
11506 It is not needed anymore to prefix the OpenOCD commands with
11507 @code{ocd_} to get the results back. But sometimes you might need the
11508 @command{capture} command.
11510 See @file{contrib/rpc_examples/} for specific client implementations.
11512 @section Tcl RPC server notifications
11513 @cindex RPC Notifications
11515 Notifications are sent asynchronously to other commands being executed over
11516 the RPC server, so the port must be polled continuously.
11518 Target event, state and reset notifications are emitted as Tcl associative arrays
11519 in the following format.
11522 type target_event event [event-name]
11523 type target_state state [state-name]
11524 type target_reset mode [reset-mode]
11527 @deffn {Command} {tcl_notifications} [on/off]
11528 Toggle output of target notifications to the current Tcl RPC server.
11529 Only available from the Tcl RPC server.
11534 @section Tcl RPC server trace output
11535 @cindex RPC trace output
11537 Trace data is sent asynchronously to other commands being executed over
11538 the RPC server, so the port must be polled continuously.
11540 Target trace data is emitted as a Tcl associative array in the following format.
11543 type target_trace data [trace-data-hex-encoded]
11546 @deffn {Command} {tcl_trace} [on/off]
11547 Toggle output of target trace data to the current Tcl RPC server.
11548 Only available from the Tcl RPC server.
11551 See an example application here:
11552 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
11561 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
11563 @cindex adaptive clocking
11566 In digital circuit design it is often referred to as ``clock
11567 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
11568 operating at some speed, your CPU target is operating at another.
11569 The two clocks are not synchronised, they are ``asynchronous''
11571 In order for the two to work together they must be synchronised
11572 well enough to work; JTAG can't go ten times faster than the CPU,
11573 for example. There are 2 basic options:
11576 Use a special "adaptive clocking" circuit to change the JTAG
11577 clock rate to match what the CPU currently supports.
11579 The JTAG clock must be fixed at some speed that's enough slower than
11580 the CPU clock that all TMS and TDI transitions can be detected.
11583 @b{Does this really matter?} For some chips and some situations, this
11584 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
11585 the CPU has no difficulty keeping up with JTAG.
11586 Startup sequences are often problematic though, as are other
11587 situations where the CPU clock rate changes (perhaps to save
11590 For example, Atmel AT91SAM chips start operation from reset with
11591 a 32kHz system clock. Boot firmware may activate the main oscillator
11592 and PLL before switching to a faster clock (perhaps that 500 MHz
11594 If you're using JTAG to debug that startup sequence, you must slow
11595 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
11596 JTAG can use a faster clock.
11598 Consider also debugging a 500MHz ARM926 hand held battery powered
11599 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
11600 clock, between keystrokes unless it has work to do. When would
11601 that 5 MHz JTAG clock be usable?
11603 @b{Solution #1 - A special circuit}
11605 In order to make use of this,
11606 your CPU, board, and JTAG adapter must all support the RTCK
11607 feature. Not all of them support this; keep reading!
11609 The RTCK ("Return TCK") signal in some ARM chips is used to help with
11610 this problem. ARM has a good description of the problem described at
11611 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
11612 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
11613 work? / how does adaptive clocking work?''.
11615 The nice thing about adaptive clocking is that ``battery powered hand
11616 held device example'' - the adaptiveness works perfectly all the
11617 time. One can set a break point or halt the system in the deep power
11618 down code, slow step out until the system speeds up.
11620 Note that adaptive clocking may also need to work at the board level,
11621 when a board-level scan chain has multiple chips.
11622 Parallel clock voting schemes are good way to implement this,
11623 both within and between chips, and can easily be implemented
11625 It's not difficult to have logic fan a module's input TCK signal out
11626 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
11627 back with the right polarity before changing the output RTCK signal.
11628 Texas Instruments makes some clock voting logic available
11629 for free (with no support) in VHDL form; see
11630 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
11632 @b{Solution #2 - Always works - but may be slower}
11634 Often this is a perfectly acceptable solution.
11636 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
11637 the target clock speed. But what that ``magic division'' is varies
11638 depending on the chips on your board.
11639 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
11640 ARM11 cores use an 8:1 division.
11641 @b{Xilinx rule of thumb} is 1/12 the clock speed.
11643 Note: most full speed FT2232 based JTAG adapters are limited to a
11644 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
11645 often support faster clock rates (and adaptive clocking).
11647 You can still debug the 'low power' situations - you just need to
11648 either use a fixed and very slow JTAG clock rate ... or else
11649 manually adjust the clock speed at every step. (Adjusting is painful
11650 and tedious, and is not always practical.)
11652 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
11653 have a special debug mode in your application that does a ``high power
11654 sleep''. If you are careful - 98% of your problems can be debugged
11657 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
11658 operation in your idle loops even if you don't otherwise change the CPU
11660 That operation gates the CPU clock, and thus the JTAG clock; which
11661 prevents JTAG access. One consequence is not being able to @command{halt}
11662 cores which are executing that @emph{wait for interrupt} operation.
11664 To set the JTAG frequency use the command:
11667 # Example: 1.234MHz
11672 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
11674 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
11675 around Windows filenames.
11688 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
11690 Make sure you have Cygwin installed, or at least a version of OpenOCD that
11691 claims to come with all the necessary DLLs. When using Cygwin, try launching
11692 OpenOCD from the Cygwin shell.
11694 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
11695 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
11696 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
11698 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
11699 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
11700 software breakpoints consume one of the two available hardware breakpoints.
11702 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
11704 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
11705 clock at the time you're programming the flash. If you've specified the crystal's
11706 frequency, make sure the PLL is disabled. If you've specified the full core speed
11707 (e.g. 60MHz), make sure the PLL is enabled.
11709 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
11710 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
11711 out while waiting for end of scan, rtck was disabled".
11713 Make sure your PC's parallel port operates in EPP mode. You might have to try several
11714 settings in your PC BIOS (ECP, EPP, and different versions of those).
11716 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
11717 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
11718 memory read caused data abort".
11720 The errors are non-fatal, and are the result of GDB trying to trace stack frames
11721 beyond the last valid frame. It might be possible to prevent this by setting up
11722 a proper "initial" stack frame, if you happen to know what exactly has to
11723 be done, feel free to add this here.
11725 @b{Simple:} In your startup code - push 8 registers of zeros onto the
11726 stack before calling main(). What GDB is doing is ``climbing'' the run
11727 time stack by reading various values on the stack using the standard
11728 call frame for the target. GDB keeps going - until one of 2 things
11729 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
11730 stackframes have been processed. By pushing zeros on the stack, GDB
11733 @b{Debugging Interrupt Service Routines} - In your ISR before you call
11734 your C code, do the same - artificially push some zeros onto the stack,
11735 remember to pop them off when the ISR is done.
11737 @b{Also note:} If you have a multi-threaded operating system, they
11738 often do not @b{in the interest of saving memory} waste these few
11742 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
11743 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
11745 This warning doesn't indicate any serious problem, as long as you don't want to
11746 debug your core right out of reset. Your .cfg file specified @option{reset_config
11747 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
11748 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
11749 independently. With this setup, it's not possible to halt the core right out of
11750 reset, everything else should work fine.
11752 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
11753 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
11754 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
11755 quit with an error message. Is there a stability issue with OpenOCD?
11757 No, this is not a stability issue concerning OpenOCD. Most users have solved
11758 this issue by simply using a self-powered USB hub, which they connect their
11759 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
11760 supply stable enough for the Amontec JTAGkey to be operated.
11762 @b{Laptops running on battery have this problem too...}
11764 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
11765 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
11766 What does that mean and what might be the reason for this?
11768 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
11769 has closed the connection to OpenOCD. This might be a GDB issue.
11771 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
11772 are described, there is a parameter for specifying the clock frequency
11773 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
11774 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
11775 specified in kilohertz. However, I do have a quartz crystal of a
11776 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
11777 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
11780 No. The clock frequency specified here must be given as an integral number.
11781 However, this clock frequency is used by the In-Application-Programming (IAP)
11782 routines of the LPC2000 family only, which seems to be very tolerant concerning
11783 the given clock frequency, so a slight difference between the specified clock
11784 frequency and the actual clock frequency will not cause any trouble.
11786 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
11788 Well, yes and no. Commands can be given in arbitrary order, yet the
11789 devices listed for the JTAG scan chain must be given in the right
11790 order (jtag newdevice), with the device closest to the TDO-Pin being
11791 listed first. In general, whenever objects of the same type exist
11792 which require an index number, then these objects must be given in the
11793 right order (jtag newtap, targets and flash banks - a target
11794 references a jtag newtap and a flash bank references a target).
11796 You can use the ``scan_chain'' command to verify and display the tap order.
11798 Also, some commands can't execute until after @command{init} has been
11799 processed. Such commands include @command{nand probe} and everything
11800 else that needs to write to controller registers, perhaps for setting
11801 up DRAM and loading it with code.
11803 @anchor{faqtaporder}
11804 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
11807 Yes; whenever you have more than one, you must declare them in
11808 the same order used by the hardware.
11810 Many newer devices have multiple JTAG TAPs. For example:
11811 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
11812 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
11813 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
11814 connected to the boundary scan TAP, which then connects to the
11815 Cortex-M3 TAP, which then connects to the TDO pin.
11817 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
11818 (2) The boundary scan TAP. If your board includes an additional JTAG
11819 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
11820 place it before or after the STM32 chip in the chain. For example:
11823 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
11824 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
11825 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
11826 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
11827 @item Xilinx TDO Pin -> OpenOCD TDO (input)
11830 The ``jtag device'' commands would thus be in the order shown below. Note:
11833 @item jtag newtap Xilinx tap -irlen ...
11834 @item jtag newtap stm32 cpu -irlen ...
11835 @item jtag newtap stm32 bs -irlen ...
11836 @item # Create the debug target and say where it is
11837 @item target create stm32.cpu -chain-position stm32.cpu ...
11841 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
11842 log file, I can see these error messages: Error: arm7_9_common.c:561
11843 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
11849 @node Tcl Crash Course
11850 @chapter Tcl Crash Course
11853 Not everyone knows Tcl - this is not intended to be a replacement for
11854 learning Tcl, the intent of this chapter is to give you some idea of
11855 how the Tcl scripts work.
11857 This chapter is written with two audiences in mind. (1) OpenOCD users
11858 who need to understand a bit more of how Jim-Tcl works so they can do
11859 something useful, and (2) those that want to add a new command to
11862 @section Tcl Rule #1
11863 There is a famous joke, it goes like this:
11865 @item Rule #1: The wife is always correct
11866 @item Rule #2: If you think otherwise, See Rule #1
11869 The Tcl equal is this:
11872 @item Rule #1: Everything is a string
11873 @item Rule #2: If you think otherwise, See Rule #1
11876 As in the famous joke, the consequences of Rule #1 are profound. Once
11877 you understand Rule #1, you will understand Tcl.
11879 @section Tcl Rule #1b
11880 There is a second pair of rules.
11882 @item Rule #1: Control flow does not exist. Only commands
11883 @* For example: the classic FOR loop or IF statement is not a control
11884 flow item, they are commands, there is no such thing as control flow
11886 @item Rule #2: If you think otherwise, See Rule #1
11887 @* Actually what happens is this: There are commands that by
11888 convention, act like control flow key words in other languages. One of
11889 those commands is the word ``for'', another command is ``if''.
11892 @section Per Rule #1 - All Results are strings
11893 Every Tcl command results in a string. The word ``result'' is used
11894 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
11895 Everything is a string}
11897 @section Tcl Quoting Operators
11898 In life of a Tcl script, there are two important periods of time, the
11899 difference is subtle.
11902 @item Evaluation Time
11905 The two key items here are how ``quoted things'' work in Tcl. Tcl has
11906 three primary quoting constructs, the [square-brackets] the
11907 @{curly-braces@} and ``double-quotes''
11909 By now you should know $VARIABLES always start with a $DOLLAR
11910 sign. BTW: To set a variable, you actually use the command ``set'', as
11911 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
11912 = 1'' statement, but without the equal sign.
11915 @item @b{[square-brackets]}
11916 @* @b{[square-brackets]} are command substitutions. It operates much
11917 like Unix Shell `back-ticks`. The result of a [square-bracket]
11918 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
11919 string}. These two statements are roughly identical:
11923 echo "The Date is: $X"
11926 puts "The Date is: $X"
11928 @item @b{``double-quoted-things''}
11929 @* @b{``double-quoted-things''} are just simply quoted
11930 text. $VARIABLES and [square-brackets] are expanded in place - the
11931 result however is exactly 1 string. @i{Remember Rule #1 - Everything
11935 puts "It is now \"[date]\", $x is in 1 hour"
11937 @item @b{@{Curly-Braces@}}
11938 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
11939 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
11940 'single-quote' operators in BASH shell scripts, with the added
11941 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
11942 nested 3 times@}@}@} NOTE: [date] is a bad example;
11943 at this writing, Jim/OpenOCD does not have a date command.
11946 @section Consequences of Rule 1/2/3/4
11948 The consequences of Rule 1 are profound.
11950 @subsection Tokenisation & Execution.
11952 Of course, whitespace, blank lines and #comment lines are handled in
11955 As a script is parsed, each (multi) line in the script file is
11956 tokenised and according to the quoting rules. After tokenisation, that
11957 line is immediately executed.
11959 Multi line statements end with one or more ``still-open''
11960 @{curly-braces@} which - eventually - closes a few lines later.
11962 @subsection Command Execution
11964 Remember earlier: There are no ``control flow''
11965 statements in Tcl. Instead there are COMMANDS that simply act like
11966 control flow operators.
11968 Commands are executed like this:
11971 @item Parse the next line into (argc) and (argv[]).
11972 @item Look up (argv[0]) in a table and call its function.
11973 @item Repeat until End Of File.
11976 It sort of works like this:
11979 ReadAndParse( &argc, &argv );
11981 cmdPtr = LookupCommand( argv[0] );
11983 (*cmdPtr->Execute)( argc, argv );
11987 When the command ``proc'' is parsed (which creates a procedure
11988 function) it gets 3 parameters on the command line. @b{1} the name of
11989 the proc (function), @b{2} the list of parameters, and @b{3} the body
11990 of the function. Not the choice of words: LIST and BODY. The PROC
11991 command stores these items in a table somewhere so it can be found by
11992 ``LookupCommand()''
11994 @subsection The FOR command
11996 The most interesting command to look at is the FOR command. In Tcl,
11997 the FOR command is normally implemented in C. Remember, FOR is a
11998 command just like any other command.
12000 When the ascii text containing the FOR command is parsed, the parser
12001 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
12005 @item The ascii text 'for'
12006 @item The start text
12007 @item The test expression
12008 @item The next text
12009 @item The body text
12012 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
12013 Remember @i{Rule #1 - Everything is a string.} The key point is this:
12014 Often many of those parameters are in @{curly-braces@} - thus the
12015 variables inside are not expanded or replaced until later.
12017 Remember that every Tcl command looks like the classic ``main( argc,
12018 argv )'' function in C. In JimTCL - they actually look like this:
12022 MyCommand( Jim_Interp *interp,
12024 Jim_Obj * const *argvs );
12027 Real Tcl is nearly identical. Although the newer versions have
12028 introduced a byte-code parser and interpreter, but at the core, it
12029 still operates in the same basic way.
12031 @subsection FOR command implementation
12033 To understand Tcl it is perhaps most helpful to see the FOR
12034 command. Remember, it is a COMMAND not a control flow structure.
12036 In Tcl there are two underlying C helper functions.
12038 Remember Rule #1 - You are a string.
12040 The @b{first} helper parses and executes commands found in an ascii
12041 string. Commands can be separated by semicolons, or newlines. While
12042 parsing, variables are expanded via the quoting rules.
12044 The @b{second} helper evaluates an ascii string as a numerical
12045 expression and returns a value.
12047 Here is an example of how the @b{FOR} command could be
12048 implemented. The pseudo code below does not show error handling.
12050 void Execute_AsciiString( void *interp, const char *string );
12052 int Evaluate_AsciiExpression( void *interp, const char *string );
12055 MyForCommand( void *interp,
12060 SetResult( interp, "WRONG number of parameters");
12064 // argv[0] = the ascii string just like C
12066 // Execute the start statement.
12067 Execute_AsciiString( interp, argv[1] );
12069 // Top of loop test
12071 i = Evaluate_AsciiExpression(interp, argv[2]);
12075 // Execute the body
12076 Execute_AsciiString( interp, argv[3] );
12078 // Execute the LOOP part
12079 Execute_AsciiString( interp, argv[4] );
12083 SetResult( interp, "" );
12088 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
12089 in the same basic way.
12091 @section OpenOCD Tcl Usage
12093 @subsection source and find commands
12094 @b{Where:} In many configuration files
12095 @* Example: @b{ source [find FILENAME] }
12096 @*Remember the parsing rules
12098 @item The @command{find} command is in square brackets,
12099 and is executed with the parameter FILENAME. It should find and return
12100 the full path to a file with that name; it uses an internal search path.
12101 The RESULT is a string, which is substituted into the command line in
12102 place of the bracketed @command{find} command.
12103 (Don't try to use a FILENAME which includes the "#" character.
12104 That character begins Tcl comments.)
12105 @item The @command{source} command is executed with the resulting filename;
12106 it reads a file and executes as a script.
12108 @subsection format command
12109 @b{Where:} Generally occurs in numerous places.
12110 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
12116 puts [format "The answer: %d" [expr @{$x * $y@}]]
12119 @item The SET command creates 2 variables, X and Y.
12120 @item The double [nested] EXPR command performs math
12121 @* The EXPR command produces numerical result as a string.
12122 @* Refer to Rule #1
12123 @item The format command is executed, producing a single string
12124 @* Refer to Rule #1.
12125 @item The PUTS command outputs the text.
12127 @subsection Body or Inlined Text
12128 @b{Where:} Various TARGET scripts.
12131 proc someproc @{@} @{
12132 ... multiple lines of stuff ...
12134 $_TARGETNAME configure -event FOO someproc
12135 #2 Good - no variables
12136 $_TARGETNAME configure -event foo "this ; that;"
12137 #3 Good Curly Braces
12138 $_TARGETNAME configure -event FOO @{
12139 puts "Time: [date]"
12141 #4 DANGER DANGER DANGER
12142 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
12145 @item The $_TARGETNAME is an OpenOCD variable convention.
12146 @*@b{$_TARGETNAME} represents the last target created, the value changes
12147 each time a new target is created. Remember the parsing rules. When
12148 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
12149 the name of the target which happens to be a TARGET (object)
12151 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
12152 @*There are 4 examples:
12154 @item The TCLBODY is a simple string that happens to be a proc name
12155 @item The TCLBODY is several simple commands separated by semicolons
12156 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
12157 @item The TCLBODY is a string with variables that get expanded.
12160 In the end, when the target event FOO occurs the TCLBODY is
12161 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
12162 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
12164 Remember the parsing rules. In case #3, @{curly-braces@} mean the
12165 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
12166 and the text is evaluated. In case #4, they are replaced before the
12167 ``Target Object Command'' is executed. This occurs at the same time
12168 $_TARGETNAME is replaced. In case #4 the date will never
12169 change. @{BTW: [date] is a bad example; at this writing,
12170 Jim/OpenOCD does not have a date command@}
12172 @subsection Global Variables
12173 @b{Where:} You might discover this when writing your own procs @* In
12174 simple terms: Inside a PROC, if you need to access a global variable
12175 you must say so. See also ``upvar''. Example:
12177 proc myproc @{ @} @{
12178 set y 0 #Local variable Y
12179 global x #Global variable X
12180 puts [format "X=%d, Y=%d" $x $y]
12183 @section Other Tcl Hacks
12184 @b{Dynamic variable creation}
12186 # Dynamically create a bunch of variables.
12187 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr @{$x + 1@}]@} @{
12189 set vn [format "BIT%d" $x]
12193 set $vn [expr @{1 << $x@}]
12196 @b{Dynamic proc/command creation}
12198 # One "X" function - 5 uart functions.
12199 foreach who @{A B C D E@}
12200 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
12205 @appendix The GNU Free Documentation License.
12208 @node OpenOCD Concept Index
12209 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
12210 @comment case issue with ``Index.html'' and ``index.html''
12211 @comment Occurs when creating ``--html --no-split'' output
12212 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
12213 @unnumbered OpenOCD Concept Index
12217 @node Command and Driver Index
12218 @unnumbered Command and Driver Index