1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
160 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 STMicroelectronics has an adapter called @b{ST-LINK}.
481 They only work with STMicroelectronics chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
491 @* This is available standalone and as part of some kits.
492 @* Link: @url{http://www.st.com/stlink-v3}
495 For info the original ST-LINK enumerates using the mass storage usb class; however,
496 its implementation is completely broken. The result is this causes issues under Linux.
497 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
499 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
500 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
503 @section USB TI/Stellaris ICDI based
504 Texas Instruments has an adapter called @b{ICDI}.
505 It is not to be confused with the FTDI based adapters that were originally fitted to their
506 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
508 @section USB Nuvoton Nu-Link
509 Nuvoton has an adapter called @b{Nu-Link}.
510 It is available either as stand-alone dongle and embedded on development boards.
511 It supports SWD, serial port bridge and mass storage for firmware update.
512 Both Nu-Link v1 and v2 are supported.
514 @section USB CMSIS-DAP based
515 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
516 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
521 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
523 @item @b{USB - Presto}
524 @* Link: @url{http://tools.asix.net/prg_presto.htm}
526 @item @b{Versaloon-Link}
527 @* Link: @url{http://www.versaloon.com}
529 @item @b{ARM-JTAG-EW}
530 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
533 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
536 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
539 @* Link: @url{http://code.google.com/p/estick-jtag/}
541 @item @b{Keil ULINK v1}
542 @* Link: @url{http://www.keil.com/ulink1/}
544 @item @b{TI XDS110 Debug Probe}
545 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
546 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
549 @section IBM PC Parallel Printer Port Based
551 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
552 and the Macraigor Wiggler. There are many clones and variations of
555 Note that parallel ports are becoming much less common, so if you
556 have the choice you should probably avoid these adapters in favor
561 @item @b{Wiggler} - There are many clones of this.
562 @* Link: @url{http://www.macraigor.com/wiggler.htm}
564 @item @b{DLC5} - From XILINX - There are many clones of this
565 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
566 produced, PDF schematics are easily found and it is easy to make.
568 @item @b{Amontec - JTAG Accelerator}
569 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
572 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
574 @item @b{Wiggler_ntrst_inverted}
575 @* Yet another variation - See the source code, src/jtag/parport.c
577 @item @b{old_amt_wiggler}
578 @* Unknown - probably not on the market today
581 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
584 @* Link: @url{http://www.amontec.com/chameleon.shtml}
590 @* ispDownload from Lattice Semiconductor
591 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
594 @* From STMicroelectronics;
595 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
603 @* An EP93xx based Linux machine using the GPIO pins directly.
606 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
608 @item @b{bcm2835gpio}
609 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
612 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
615 @* A JTAG driver acting as a client for the JTAG VPI server interface.
616 @* Link: @url{http://github.com/fjullien/jtag_vpi}
619 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
620 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
621 interface of a hardware model written in SystemVerilog, for example, on an
622 emulation model of target hardware.
624 @item @b{xlnx_pcie_xvc}
625 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
630 @chapter About Jim-Tcl
634 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
635 This programming language provides a simple and extensible
638 All commands presented in this Guide are extensions to Jim-Tcl.
639 You can use them as simple commands, without needing to learn
640 much of anything about Tcl.
641 Alternatively, you can write Tcl programs with them.
643 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
644 There is an active and responsive community, get on the mailing list
645 if you have any questions. Jim-Tcl maintainers also lurk on the
646 OpenOCD mailing list.
649 @item @b{Jim vs. Tcl}
650 @* Jim-Tcl is a stripped down version of the well known Tcl language,
651 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
652 fewer features. Jim-Tcl is several dozens of .C files and .H files and
653 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
654 4.2 MB .zip file containing 1540 files.
656 @item @b{Missing Features}
657 @* Our practice has been: Add/clone the real Tcl feature if/when
658 needed. We welcome Jim-Tcl improvements, not bloat. Also there
659 are a large number of optional Jim-Tcl features that are not
663 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
664 command interpreter today is a mixture of (newer)
665 Jim-Tcl commands, and the (older) original command interpreter.
668 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
669 can type a Tcl for() loop, set variables, etc.
670 Some of the commands documented in this guide are implemented
671 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
673 @item @b{Historical Note}
674 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
675 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
676 as a Git submodule, which greatly simplified upgrading Jim-Tcl
677 to benefit from new features and bugfixes in Jim-Tcl.
679 @item @b{Need a crash course in Tcl?}
680 @*@xref{Tcl Crash Course}.
685 @cindex command line options
687 @cindex directory search
689 Properly installing OpenOCD sets up your operating system to grant it access
690 to the debug adapters. On Linux, this usually involves installing a file
691 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
692 that works for many common adapters is shipped with OpenOCD in the
693 @file{contrib} directory. MS-Windows needs
694 complex and confusing driver configuration for every peripheral. Such issues
695 are unique to each operating system, and are not detailed in this User's Guide.
697 Then later you will invoke the OpenOCD server, with various options to
698 tell it how each debug session should work.
699 The @option{--help} option shows:
703 --help | -h display this help
704 --version | -v display OpenOCD version
705 --file | -f use configuration file <name>
706 --search | -s dir to search for config files and scripts
707 --debug | -d set debug level to 3
708 | -d<n> set debug level to <level>
709 --log_output | -l redirect log output to file <name>
710 --command | -c run <command>
713 If you don't give any @option{-f} or @option{-c} options,
714 OpenOCD tries to read the configuration file @file{openocd.cfg}.
715 To specify one or more different
716 configuration files, use @option{-f} options. For example:
719 openocd -f config1.cfg -f config2.cfg -f config3.cfg
722 Configuration files and scripts are searched for in
724 @item the current directory,
725 @item any search dir specified on the command line using the @option{-s} option,
726 @item any search dir specified using the @command{add_script_search_dir} command,
727 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
728 @item @file{%APPDATA%/OpenOCD} (only on Windows),
729 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
730 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
731 @item @file{$HOME/.openocd},
732 @item the site wide script library @file{$pkgdatadir/site} and
733 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
735 The first found file with a matching file name will be used.
738 Don't try to use configuration script names or paths which
739 include the "#" character. That character begins Tcl comments.
742 @section Simple setup, no customization
744 In the best case, you can use two scripts from one of the script
745 libraries, hook up your JTAG adapter, and start the server ... and
746 your JTAG setup will just work "out of the box". Always try to
747 start by reusing those scripts, but assume you'll need more
748 customization even if this works. @xref{OpenOCD Project Setup}.
750 If you find a script for your JTAG adapter, and for your board or
751 target, you may be able to hook up your JTAG adapter then start
752 the server with some variation of one of the following:
755 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
756 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
759 You might also need to configure which reset signals are present,
760 using @option{-c 'reset_config trst_and_srst'} or something similar.
761 If all goes well you'll see output something like
764 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
765 For bug reports, read
766 http://openocd.org/doc/doxygen/bugs.html
767 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
768 (mfg: 0x23b, part: 0xba00, ver: 0x3)
771 Seeing that "tap/device found" message, and no warnings, means
772 the JTAG communication is working. That's a key milestone, but
773 you'll probably need more project-specific setup.
775 @section What OpenOCD does as it starts
777 OpenOCD starts by processing the configuration commands provided
778 on the command line or, if there were no @option{-c command} or
779 @option{-f file.cfg} options given, in @file{openocd.cfg}.
780 @xref{configurationstage,,Configuration Stage}.
781 At the end of the configuration stage it verifies the JTAG scan
782 chain defined using those commands; your configuration should
783 ensure that this always succeeds.
784 Normally, OpenOCD then starts running as a server.
785 Alternatively, commands may be used to terminate the configuration
786 stage early, perform work (such as updating some flash memory),
787 and then shut down without acting as a server.
789 Once OpenOCD starts running as a server, it waits for connections from
790 clients (Telnet, GDB, RPC) and processes the commands issued through
793 If you are having problems, you can enable internal debug messages via
794 the @option{-d} option.
796 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
797 @option{-c} command line switch.
799 To enable debug output (when reporting problems or working on OpenOCD
800 itself), use the @option{-d} command line switch. This sets the
801 @option{debug_level} to "3", outputting the most information,
802 including debug messages. The default setting is "2", outputting only
803 informational messages, warnings and errors. You can also change this
804 setting from within a telnet or gdb session using @command{debug_level<n>}
805 (@pxref{debuglevel,,debug_level}).
807 You can redirect all output from the server to a file using the
808 @option{-l <logfile>} switch.
810 Note! OpenOCD will launch the GDB & telnet server even if it can not
811 establish a connection with the target. In general, it is possible for
812 the JTAG controller to be unresponsive until the target is set up
813 correctly via e.g. GDB monitor commands in a GDB init script.
815 @node OpenOCD Project Setup
816 @chapter OpenOCD Project Setup
818 To use OpenOCD with your development projects, you need to do more than
819 just connect the JTAG adapter hardware (dongle) to your development board
820 and start the OpenOCD server.
821 You also need to configure your OpenOCD server so that it knows
822 about your adapter and board, and helps your work.
823 You may also want to connect OpenOCD to GDB, possibly
824 using Eclipse or some other GUI.
826 @section Hooking up the JTAG Adapter
828 Today's most common case is a dongle with a JTAG cable on one side
829 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
830 and a USB cable on the other.
831 Instead of USB, some cables use Ethernet;
832 older ones may use a PC parallel port, or even a serial port.
835 @item @emph{Start with power to your target board turned off},
836 and nothing connected to your JTAG adapter.
837 If you're particularly paranoid, unplug power to the board.
838 It's important to have the ground signal properly set up,
839 unless you are using a JTAG adapter which provides
840 galvanic isolation between the target board and the
843 @item @emph{Be sure it's the right kind of JTAG connector.}
844 If your dongle has a 20-pin ARM connector, you need some kind
845 of adapter (or octopus, see below) to hook it up to
846 boards using 14-pin or 10-pin connectors ... or to 20-pin
847 connectors which don't use ARM's pinout.
849 In the same vein, make sure the voltage levels are compatible.
850 Not all JTAG adapters have the level shifters needed to work
851 with 1.2 Volt boards.
853 @item @emph{Be certain the cable is properly oriented} or you might
854 damage your board. In most cases there are only two possible
855 ways to connect the cable.
856 Connect the JTAG cable from your adapter to the board.
857 Be sure it's firmly connected.
859 In the best case, the connector is keyed to physically
860 prevent you from inserting it wrong.
861 This is most often done using a slot on the board's male connector
862 housing, which must match a key on the JTAG cable's female connector.
863 If there's no housing, then you must look carefully and
864 make sure pin 1 on the cable hooks up to pin 1 on the board.
865 Ribbon cables are frequently all grey except for a wire on one
866 edge, which is red. The red wire is pin 1.
868 Sometimes dongles provide cables where one end is an ``octopus'' of
869 color coded single-wire connectors, instead of a connector block.
870 These are great when converting from one JTAG pinout to another,
871 but are tedious to set up.
872 Use these with connector pinout diagrams to help you match up the
873 adapter signals to the right board pins.
875 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
876 A USB, parallel, or serial port connector will go to the host which
877 you are using to run OpenOCD.
878 For Ethernet, consult the documentation and your network administrator.
880 For USB-based JTAG adapters you have an easy sanity check at this point:
881 does the host operating system see the JTAG adapter? If you're running
882 Linux, try the @command{lsusb} command. If that host is an
883 MS-Windows host, you'll need to install a driver before OpenOCD works.
885 @item @emph{Connect the adapter's power supply, if needed.}
886 This step is primarily for non-USB adapters,
887 but sometimes USB adapters need extra power.
889 @item @emph{Power up the target board.}
890 Unless you just let the magic smoke escape,
891 you're now ready to set up the OpenOCD server
892 so you can use JTAG to work with that board.
896 Talk with the OpenOCD server using
897 telnet (@code{telnet localhost 4444} on many systems) or GDB.
898 @xref{GDB and OpenOCD}.
900 @section Project Directory
902 There are many ways you can configure OpenOCD and start it up.
904 A simple way to organize them all involves keeping a
905 single directory for your work with a given board.
906 When you start OpenOCD from that directory,
907 it searches there first for configuration files, scripts,
908 files accessed through semihosting,
909 and for code you upload to the target board.
910 It is also the natural place to write files,
911 such as log files and data you download from the board.
913 @section Configuration Basics
915 There are two basic ways of configuring OpenOCD, and
916 a variety of ways you can mix them.
917 Think of the difference as just being how you start the server:
920 @item Many @option{-f file} or @option{-c command} options on the command line
921 @item No options, but a @dfn{user config file}
922 in the current directory named @file{openocd.cfg}
925 Here is an example @file{openocd.cfg} file for a setup
926 using a Signalyzer FT2232-based JTAG adapter to talk to
927 a board with an Atmel AT91SAM7X256 microcontroller:
930 source [find interface/ftdi/signalyzer.cfg]
932 # GDB can also flash my flash!
933 gdb_memory_map enable
934 gdb_flash_program enable
936 source [find target/sam7x256.cfg]
939 Here is the command line equivalent of that configuration:
942 openocd -f interface/ftdi/signalyzer.cfg \
943 -c "gdb_memory_map enable" \
944 -c "gdb_flash_program enable" \
945 -f target/sam7x256.cfg
948 You could wrap such long command lines in shell scripts,
949 each supporting a different development task.
950 One might re-flash the board with a specific firmware version.
951 Another might set up a particular debugging or run-time environment.
954 At this writing (October 2009) the command line method has
955 problems with how it treats variables.
956 For example, after @option{-c "set VAR value"}, or doing the
957 same in a script, the variable @var{VAR} will have no value
958 that can be tested in a later script.
961 Here we will focus on the simpler solution: one user config
962 file, including basic configuration plus any TCL procedures
963 to simplify your work.
965 @section User Config Files
966 @cindex config file, user
967 @cindex user config file
968 @cindex config file, overview
970 A user configuration file ties together all the parts of a project
972 One of the following will match your situation best:
975 @item Ideally almost everything comes from configuration files
976 provided by someone else.
977 For example, OpenOCD distributes a @file{scripts} directory
978 (probably in @file{/usr/share/openocd/scripts} on Linux).
979 Board and tool vendors can provide these too, as can individual
980 user sites; the @option{-s} command line option lets you say
981 where to find these files. (@xref{Running}.)
982 The AT91SAM7X256 example above works this way.
984 Three main types of non-user configuration file each have their
985 own subdirectory in the @file{scripts} directory:
988 @item @b{interface} -- one for each different debug adapter;
989 @item @b{board} -- one for each different board
990 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
993 Best case: include just two files, and they handle everything else.
994 The first is an interface config file.
995 The second is board-specific, and it sets up the JTAG TAPs and
996 their GDB targets (by deferring to some @file{target.cfg} file),
997 declares all flash memory, and leaves you nothing to do except
1001 source [find interface/olimex-jtag-tiny.cfg]
1002 source [find board/csb337.cfg]
1005 Boards with a single microcontroller often won't need more
1006 than the target config file, as in the AT91SAM7X256 example.
1007 That's because there is no external memory (flash, DDR RAM), and
1008 the board differences are encapsulated by application code.
1010 @item Maybe you don't know yet what your board looks like to JTAG.
1011 Once you know the @file{interface.cfg} file to use, you may
1012 need help from OpenOCD to discover what's on the board.
1013 Once you find the JTAG TAPs, you can just search for appropriate
1015 configuration files ... or write your own, from the bottom up.
1016 @xref{autoprobing,,Autoprobing}.
1018 @item You can often reuse some standard config files but
1019 need to write a few new ones, probably a @file{board.cfg} file.
1020 You will be using commands described later in this User's Guide,
1021 and working with the guidelines in the next chapter.
1023 For example, there may be configuration files for your JTAG adapter
1024 and target chip, but you need a new board-specific config file
1025 giving access to your particular flash chips.
1026 Or you might need to write another target chip configuration file
1027 for a new chip built around the Cortex-M3 core.
1030 When you write new configuration files, please submit
1031 them for inclusion in the next OpenOCD release.
1032 For example, a @file{board/newboard.cfg} file will help the
1033 next users of that board, and a @file{target/newcpu.cfg}
1034 will help support users of any board using that chip.
1038 You may need to write some C code.
1039 It may be as simple as supporting a new FT2232 or parport
1040 based adapter; a bit more involved, like a NAND or NOR flash
1041 controller driver; or a big piece of work like supporting
1042 a new chip architecture.
1045 Reuse the existing config files when you can.
1046 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1047 You may find a board configuration that's a good example to follow.
1049 When you write config files, separate the reusable parts
1050 (things every user of that interface, chip, or board needs)
1051 from ones specific to your environment and debugging approach.
1055 For example, a @code{gdb-attach} event handler that invokes
1056 the @command{reset init} command will interfere with debugging
1057 early boot code, which performs some of the same actions
1058 that the @code{reset-init} event handler does.
1061 Likewise, the @command{arm9 vector_catch} command (or
1062 @cindex vector_catch
1063 its siblings @command{xscale vector_catch}
1064 and @command{cortex_m vector_catch}) can be a time-saver
1065 during some debug sessions, but don't make everyone use that either.
1066 Keep those kinds of debugging aids in your user config file,
1067 along with messaging and tracing setup.
1068 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1071 You might need to override some defaults.
1072 For example, you might need to move, shrink, or back up the target's
1073 work area if your application needs much SRAM.
1076 TCP/IP port configuration is another example of something which
1077 is environment-specific, and should only appear in
1078 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1081 @section Project-Specific Utilities
1083 A few project-specific utility
1084 routines may well speed up your work.
1085 Write them, and keep them in your project's user config file.
1087 For example, if you are making a boot loader work on a
1088 board, it's nice to be able to debug the ``after it's
1089 loaded to RAM'' parts separately from the finicky early
1090 code which sets up the DDR RAM controller and clocks.
1091 A script like this one, or a more GDB-aware sibling,
1095 proc ramboot @{ @} @{
1096 # Reset, running the target's "reset-init" scripts
1097 # to initialize clocks and the DDR RAM controller.
1098 # Leave the CPU halted.
1101 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1102 load_image u-boot.bin 0x20000000
1109 Then once that code is working you will need to make it
1110 boot from NOR flash; a different utility would help.
1111 Alternatively, some developers write to flash using GDB.
1112 (You might use a similar script if you're working with a flash
1113 based microcontroller application instead of a boot loader.)
1116 proc newboot @{ @} @{
1117 # Reset, leaving the CPU halted. The "reset-init" event
1118 # proc gives faster access to the CPU and to NOR flash;
1119 # "reset halt" would be slower.
1122 # Write standard version of U-Boot into the first two
1123 # sectors of NOR flash ... the standard version should
1124 # do the same lowlevel init as "reset-init".
1125 flash protect 0 0 1 off
1126 flash erase_sector 0 0 1
1127 flash write_bank 0 u-boot.bin 0x0
1128 flash protect 0 0 1 on
1130 # Reboot from scratch using that new boot loader.
1135 You may need more complicated utility procedures when booting
1137 That often involves an extra bootloader stage,
1138 running from on-chip SRAM to perform DDR RAM setup so it can load
1139 the main bootloader code (which won't fit into that SRAM).
1141 Other helper scripts might be used to write production system images,
1142 involving considerably more than just a three stage bootloader.
1144 @section Target Software Changes
1146 Sometimes you may want to make some small changes to the software
1147 you're developing, to help make JTAG debugging work better.
1148 For example, in C or assembly language code you might
1149 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1150 handling issues like:
1154 @item @b{Watchdog Timers}...
1155 Watchdog timers are typically used to automatically reset systems if
1156 some application task doesn't periodically reset the timer. (The
1157 assumption is that the system has locked up if the task can't run.)
1158 When a JTAG debugger halts the system, that task won't be able to run
1159 and reset the timer ... potentially causing resets in the middle of
1160 your debug sessions.
1162 It's rarely a good idea to disable such watchdogs, since their usage
1163 needs to be debugged just like all other parts of your firmware.
1164 That might however be your only option.
1166 Look instead for chip-specific ways to stop the watchdog from counting
1167 while the system is in a debug halt state. It may be simplest to set
1168 that non-counting mode in your debugger startup scripts. You may however
1169 need a different approach when, for example, a motor could be physically
1170 damaged by firmware remaining inactive in a debug halt state. That might
1171 involve a type of firmware mode where that "non-counting" mode is disabled
1172 at the beginning then re-enabled at the end; a watchdog reset might fire
1173 and complicate the debug session, but hardware (or people) would be
1174 protected.@footnote{Note that many systems support a "monitor mode" debug
1175 that is a somewhat cleaner way to address such issues. You can think of
1176 it as only halting part of the system, maybe just one task,
1177 instead of the whole thing.
1178 At this writing, January 2010, OpenOCD based debugging does not support
1179 monitor mode debug, only "halt mode" debug.}
1181 @item @b{ARM Semihosting}...
1182 @cindex ARM semihosting
1183 When linked with a special runtime library provided with many
1184 toolchains@footnote{See chapter 8 "Semihosting" in
1185 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1186 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1187 The CodeSourcery EABI toolchain also includes a semihosting library.},
1188 your target code can use I/O facilities on the debug host. That library
1189 provides a small set of system calls which are handled by OpenOCD.
1190 It can let the debugger provide your system console and a file system,
1191 helping with early debugging or providing a more capable environment
1192 for sometimes-complex tasks like installing system firmware onto
1195 @item @b{ARM Wait-For-Interrupt}...
1196 Many ARM chips synchronize the JTAG clock using the core clock.
1197 Low power states which stop that core clock thus prevent JTAG access.
1198 Idle loops in tasking environments often enter those low power states
1199 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1201 You may want to @emph{disable that instruction} in source code,
1202 or otherwise prevent using that state,
1203 to ensure you can get JTAG access at any time.@footnote{As a more
1204 polite alternative, some processors have special debug-oriented
1205 registers which can be used to change various features including
1206 how the low power states are clocked while debugging.
1207 The STM32 DBGMCU_CR register is an example; at the cost of extra
1208 power consumption, JTAG can be used during low power states.}
1209 For example, the OpenOCD @command{halt} command may not
1210 work for an idle processor otherwise.
1212 @item @b{Delay after reset}...
1213 Not all chips have good support for debugger access
1214 right after reset; many LPC2xxx chips have issues here.
1215 Similarly, applications that reconfigure pins used for
1216 JTAG access as they start will also block debugger access.
1218 To work with boards like this, @emph{enable a short delay loop}
1219 the first thing after reset, before "real" startup activities.
1220 For example, one second's delay is usually more than enough
1221 time for a JTAG debugger to attach, so that
1222 early code execution can be debugged
1223 or firmware can be replaced.
1225 @item @b{Debug Communications Channel (DCC)}...
1226 Some processors include mechanisms to send messages over JTAG.
1227 Many ARM cores support these, as do some cores from other vendors.
1228 (OpenOCD may be able to use this DCC internally, speeding up some
1229 operations like writing to memory.)
1231 Your application may want to deliver various debugging messages
1232 over JTAG, by @emph{linking with a small library of code}
1233 provided with OpenOCD and using the utilities there to send
1234 various kinds of message.
1235 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1239 @section Target Hardware Setup
1241 Chip vendors often provide software development boards which
1242 are highly configurable, so that they can support all options
1243 that product boards may require. @emph{Make sure that any
1244 jumpers or switches match the system configuration you are
1247 Common issues include:
1251 @item @b{JTAG setup} ...
1252 Boards may support more than one JTAG configuration.
1253 Examples include jumpers controlling pullups versus pulldowns
1254 on the nTRST and/or nSRST signals, and choice of connectors
1255 (e.g. which of two headers on the base board,
1256 or one from a daughtercard).
1257 For some Texas Instruments boards, you may need to jumper the
1258 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1260 @item @b{Boot Modes} ...
1261 Complex chips often support multiple boot modes, controlled
1262 by external jumpers. Make sure this is set up correctly.
1263 For example many i.MX boards from NXP need to be jumpered
1264 to "ATX mode" to start booting using the on-chip ROM, when
1265 using second stage bootloader code stored in a NAND flash chip.
1267 Such explicit configuration is common, and not limited to
1268 booting from NAND. You might also need to set jumpers to
1269 start booting using code loaded from an MMC/SD card; external
1270 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1271 flash; some external host; or various other sources.
1274 @item @b{Memory Addressing} ...
1275 Boards which support multiple boot modes may also have jumpers
1276 to configure memory addressing. One board, for example, jumpers
1277 external chipselect 0 (used for booting) to address either
1278 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1279 or NAND flash. When it's jumpered to address NAND flash, that
1280 board must also be told to start booting from on-chip ROM.
1282 Your @file{board.cfg} file may also need to be told this jumper
1283 configuration, so that it can know whether to declare NOR flash
1284 using @command{flash bank} or instead declare NAND flash with
1285 @command{nand device}; and likewise which probe to perform in
1286 its @code{reset-init} handler.
1288 A closely related issue is bus width. Jumpers might need to
1289 distinguish between 8 bit or 16 bit bus access for the flash
1290 used to start booting.
1292 @item @b{Peripheral Access} ...
1293 Development boards generally provide access to every peripheral
1294 on the chip, sometimes in multiple modes (such as by providing
1295 multiple audio codec chips).
1296 This interacts with software
1297 configuration of pin multiplexing, where for example a
1298 given pin may be routed either to the MMC/SD controller
1299 or the GPIO controller. It also often interacts with
1300 configuration jumpers. One jumper may be used to route
1301 signals to an MMC/SD card slot or an expansion bus (which
1302 might in turn affect booting); others might control which
1303 audio or video codecs are used.
1307 Plus you should of course have @code{reset-init} event handlers
1308 which set up the hardware to match that jumper configuration.
1309 That includes in particular any oscillator or PLL used to clock
1310 the CPU, and any memory controllers needed to access external
1311 memory and peripherals. Without such handlers, you won't be
1312 able to access those resources without working target firmware
1313 which can do that setup ... this can be awkward when you're
1314 trying to debug that target firmware. Even if there's a ROM
1315 bootloader which handles a few issues, it rarely provides full
1316 access to all board-specific capabilities.
1319 @node Config File Guidelines
1320 @chapter Config File Guidelines
1322 This chapter is aimed at any user who needs to write a config file,
1323 including developers and integrators of OpenOCD and any user who
1324 needs to get a new board working smoothly.
1325 It provides guidelines for creating those files.
1327 You should find the following directories under
1328 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1329 them as-is where you can; or as models for new files.
1331 @item @file{interface} ...
1332 These are for debug adapters. Files that specify configuration to use
1333 specific JTAG, SWD and other adapters go here.
1334 @item @file{board} ...
1335 Think Circuit Board, PWA, PCB, they go by many names. Board files
1336 contain initialization items that are specific to a board.
1338 They reuse target configuration files, since the same
1339 microprocessor chips are used on many boards,
1340 but support for external parts varies widely. For
1341 example, the SDRAM initialization sequence for the board, or the type
1342 of external flash and what address it uses. Any initialization
1343 sequence to enable that external flash or SDRAM should be found in the
1344 board file. Boards may also contain multiple targets: two CPUs; or
1346 @item @file{target} ...
1347 Think chip. The ``target'' directory represents the JTAG TAPs
1349 which OpenOCD should control, not a board. Two common types of targets
1350 are ARM chips and FPGA or CPLD chips.
1351 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1352 the target config file defines all of them.
1353 @item @emph{more} ... browse for other library files which may be useful.
1354 For example, there are various generic and CPU-specific utilities.
1357 The @file{openocd.cfg} user config
1358 file may override features in any of the above files by
1359 setting variables before sourcing the target file, or by adding
1360 commands specific to their situation.
1362 @section Interface Config Files
1364 The user config file
1365 should be able to source one of these files with a command like this:
1368 source [find interface/FOOBAR.cfg]
1371 A preconfigured interface file should exist for every debug adapter
1372 in use today with OpenOCD.
1373 That said, perhaps some of these config files
1374 have only been used by the developer who created it.
1376 A separate chapter gives information about how to set these up.
1377 @xref{Debug Adapter Configuration}.
1378 Read the OpenOCD source code (and Developer's Guide)
1379 if you have a new kind of hardware interface
1380 and need to provide a driver for it.
1382 @section Board Config Files
1383 @cindex config file, board
1384 @cindex board config file
1386 The user config file
1387 should be able to source one of these files with a command like this:
1390 source [find board/FOOBAR.cfg]
1393 The point of a board config file is to package everything
1394 about a given board that user config files need to know.
1395 In summary the board files should contain (if present)
1398 @item One or more @command{source [find target/...cfg]} statements
1399 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1400 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1401 @item Target @code{reset} handlers for SDRAM and I/O configuration
1402 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1403 @item All things that are not ``inside a chip''
1406 Generic things inside target chips belong in target config files,
1407 not board config files. So for example a @code{reset-init} event
1408 handler should know board-specific oscillator and PLL parameters,
1409 which it passes to target-specific utility code.
1411 The most complex task of a board config file is creating such a
1412 @code{reset-init} event handler.
1413 Define those handlers last, after you verify the rest of the board
1414 configuration works.
1416 @subsection Communication Between Config files
1418 In addition to target-specific utility code, another way that
1419 board and target config files communicate is by following a
1420 convention on how to use certain variables.
1422 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1423 Thus the rule we follow in OpenOCD is this: Variables that begin with
1424 a leading underscore are temporary in nature, and can be modified and
1425 used at will within a target configuration file.
1427 Complex board config files can do the things like this,
1428 for a board with three chips:
1431 # Chip #1: PXA270 for network side, big endian
1432 set CHIPNAME network
1434 source [find target/pxa270.cfg]
1435 # on return: _TARGETNAME = network.cpu
1436 # other commands can refer to the "network.cpu" target.
1437 $_TARGETNAME configure .... events for this CPU..
1439 # Chip #2: PXA270 for video side, little endian
1442 source [find target/pxa270.cfg]
1443 # on return: _TARGETNAME = video.cpu
1444 # other commands can refer to the "video.cpu" target.
1445 $_TARGETNAME configure .... events for this CPU..
1447 # Chip #3: Xilinx FPGA for glue logic
1450 source [find target/spartan3.cfg]
1453 That example is oversimplified because it doesn't show any flash memory,
1454 or the @code{reset-init} event handlers to initialize external DRAM
1455 or (assuming it needs it) load a configuration into the FPGA.
1456 Such features are usually needed for low-level work with many boards,
1457 where ``low level'' implies that the board initialization software may
1458 not be working. (That's a common reason to need JTAG tools. Another
1459 is to enable working with microcontroller-based systems, which often
1460 have no debugging support except a JTAG connector.)
1462 Target config files may also export utility functions to board and user
1463 config files. Such functions should use name prefixes, to help avoid
1466 Board files could also accept input variables from user config files.
1467 For example, there might be a @code{J4_JUMPER} setting used to identify
1468 what kind of flash memory a development board is using, or how to set
1469 up other clocks and peripherals.
1471 @subsection Variable Naming Convention
1472 @cindex variable names
1474 Most boards have only one instance of a chip.
1475 However, it should be easy to create a board with more than
1476 one such chip (as shown above).
1477 Accordingly, we encourage these conventions for naming
1478 variables associated with different @file{target.cfg} files,
1479 to promote consistency and
1480 so that board files can override target defaults.
1482 Inputs to target config files include:
1485 @item @code{CHIPNAME} ...
1486 This gives a name to the overall chip, and is used as part of
1487 tap identifier dotted names.
1488 While the default is normally provided by the chip manufacturer,
1489 board files may need to distinguish between instances of a chip.
1490 @item @code{ENDIAN} ...
1491 By default @option{little} - although chips may hard-wire @option{big}.
1492 Chips that can't change endianness don't need to use this variable.
1493 @item @code{CPUTAPID} ...
1494 When OpenOCD examines the JTAG chain, it can be told verify the
1495 chips against the JTAG IDCODE register.
1496 The target file will hold one or more defaults, but sometimes the
1497 chip in a board will use a different ID (perhaps a newer revision).
1500 Outputs from target config files include:
1503 @item @code{_TARGETNAME} ...
1504 By convention, this variable is created by the target configuration
1505 script. The board configuration file may make use of this variable to
1506 configure things like a ``reset init'' script, or other things
1507 specific to that board and that target.
1508 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1509 @code{_TARGETNAME1}, ... etc.
1512 @subsection The reset-init Event Handler
1513 @cindex event, reset-init
1514 @cindex reset-init handler
1516 Board config files run in the OpenOCD configuration stage;
1517 they can't use TAPs or targets, since they haven't been
1519 This means you can't write memory or access chip registers;
1520 you can't even verify that a flash chip is present.
1521 That's done later in event handlers, of which the target @code{reset-init}
1522 handler is one of the most important.
1524 Except on microcontrollers, the basic job of @code{reset-init} event
1525 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1526 Microcontrollers rarely use boot loaders; they run right out of their
1527 on-chip flash and SRAM memory. But they may want to use one of these
1528 handlers too, if just for developer convenience.
1531 Because this is so very board-specific, and chip-specific, no examples
1533 Instead, look at the board config files distributed with OpenOCD.
1534 If you have a boot loader, its source code will help; so will
1535 configuration files for other JTAG tools
1536 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1539 Some of this code could probably be shared between different boards.
1540 For example, setting up a DRAM controller often doesn't differ by
1541 much except the bus width (16 bits or 32?) and memory timings, so a
1542 reusable TCL procedure loaded by the @file{target.cfg} file might take
1543 those as parameters.
1544 Similarly with oscillator, PLL, and clock setup;
1545 and disabling the watchdog.
1546 Structure the code cleanly, and provide comments to help
1547 the next developer doing such work.
1548 (@emph{You might be that next person} trying to reuse init code!)
1550 The last thing normally done in a @code{reset-init} handler is probing
1551 whatever flash memory was configured. For most chips that needs to be
1552 done while the associated target is halted, either because JTAG memory
1553 access uses the CPU or to prevent conflicting CPU access.
1555 @subsection JTAG Clock Rate
1557 Before your @code{reset-init} handler has set up
1558 the PLLs and clocking, you may need to run with
1559 a low JTAG clock rate.
1560 @xref{jtagspeed,,JTAG Speed}.
1561 Then you'd increase that rate after your handler has
1562 made it possible to use the faster JTAG clock.
1563 When the initial low speed is board-specific, for example
1564 because it depends on a board-specific oscillator speed, then
1565 you should probably set it up in the board config file;
1566 if it's target-specific, it belongs in the target config file.
1568 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1569 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1570 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1571 Consult chip documentation to determine the peak JTAG clock rate,
1572 which might be less than that.
1575 On most ARMs, JTAG clock detection is coupled to the core clock, so
1576 software using a @option{wait for interrupt} operation blocks JTAG access.
1577 Adaptive clocking provides a partial workaround, but a more complete
1578 solution just avoids using that instruction with JTAG debuggers.
1581 If both the chip and the board support adaptive clocking,
1582 use the @command{jtag_rclk}
1583 command, in case your board is used with JTAG adapter which
1584 also supports it. Otherwise use @command{adapter speed}.
1585 Set the slow rate at the beginning of the reset sequence,
1586 and the faster rate as soon as the clocks are at full speed.
1588 @anchor{theinitboardprocedure}
1589 @subsection The init_board procedure
1590 @cindex init_board procedure
1592 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1593 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1594 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1595 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1596 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1597 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1598 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1599 Additionally ``linear'' board config file will most likely fail when target config file uses
1600 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1601 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1602 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1603 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1605 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1606 the original), allowing greater code reuse.
1609 ### board_file.cfg ###
1611 # source target file that does most of the config in init_targets
1612 source [find target/target.cfg]
1614 proc enable_fast_clock @{@} @{
1615 # enables fast on-board clock source
1616 # configures the chip to use it
1619 # initialize only board specifics - reset, clock, adapter frequency
1620 proc init_board @{@} @{
1621 reset_config trst_and_srst trst_pulls_srst
1623 $_TARGETNAME configure -event reset-start @{
1627 $_TARGETNAME configure -event reset-init @{
1634 @section Target Config Files
1635 @cindex config file, target
1636 @cindex target config file
1638 Board config files communicate with target config files using
1639 naming conventions as described above, and may source one or
1640 more target config files like this:
1643 source [find target/FOOBAR.cfg]
1646 The point of a target config file is to package everything
1647 about a given chip that board config files need to know.
1648 In summary the target files should contain
1652 @item Add TAPs to the scan chain
1653 @item Add CPU targets (includes GDB support)
1654 @item CPU/Chip/CPU-Core specific features
1658 As a rule of thumb, a target file sets up only one chip.
1659 For a microcontroller, that will often include a single TAP,
1660 which is a CPU needing a GDB target, and its on-chip flash.
1662 More complex chips may include multiple TAPs, and the target
1663 config file may need to define them all before OpenOCD
1664 can talk to the chip.
1665 For example, some phone chips have JTAG scan chains that include
1666 an ARM core for operating system use, a DSP,
1667 another ARM core embedded in an image processing engine,
1668 and other processing engines.
1670 @subsection Default Value Boiler Plate Code
1672 All target configuration files should start with code like this,
1673 letting board config files express environment-specific
1674 differences in how things should be set up.
1677 # Boards may override chip names, perhaps based on role,
1678 # but the default should match what the vendor uses
1679 if @{ [info exists CHIPNAME] @} @{
1680 set _CHIPNAME $CHIPNAME
1682 set _CHIPNAME sam7x256
1685 # ONLY use ENDIAN with targets that can change it.
1686 if @{ [info exists ENDIAN] @} @{
1692 # TAP identifiers may change as chips mature, for example with
1693 # new revision fields (the "3" here). Pick a good default; you
1694 # can pass several such identifiers to the "jtag newtap" command.
1695 if @{ [info exists CPUTAPID ] @} @{
1696 set _CPUTAPID $CPUTAPID
1698 set _CPUTAPID 0x3f0f0f0f
1701 @c but 0x3f0f0f0f is for an str73x part ...
1703 @emph{Remember:} Board config files may include multiple target
1704 config files, or the same target file multiple times
1705 (changing at least @code{CHIPNAME}).
1707 Likewise, the target configuration file should define
1708 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1709 use it later on when defining debug targets:
1712 set _TARGETNAME $_CHIPNAME.cpu
1713 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1716 @subsection Adding TAPs to the Scan Chain
1717 After the ``defaults'' are set up,
1718 add the TAPs on each chip to the JTAG scan chain.
1719 @xref{TAP Declaration}, and the naming convention
1722 In the simplest case the chip has only one TAP,
1723 probably for a CPU or FPGA.
1724 The config file for the Atmel AT91SAM7X256
1725 looks (in part) like this:
1728 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1731 A board with two such at91sam7 chips would be able
1732 to source such a config file twice, with different
1733 values for @code{CHIPNAME}, so
1734 it adds a different TAP each time.
1736 If there are nonzero @option{-expected-id} values,
1737 OpenOCD attempts to verify the actual tap id against those values.
1738 It will issue error messages if there is mismatch, which
1739 can help to pinpoint problems in OpenOCD configurations.
1742 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1743 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1744 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1745 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1746 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1749 There are more complex examples too, with chips that have
1750 multiple TAPs. Ones worth looking at include:
1753 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1754 plus a JRC to enable them
1755 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1756 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1757 is not currently used)
1760 @subsection Add CPU targets
1762 After adding a TAP for a CPU, you should set it up so that
1763 GDB and other commands can use it.
1764 @xref{CPU Configuration}.
1765 For the at91sam7 example above, the command can look like this;
1766 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1767 to little endian, and this chip doesn't support changing that.
1770 set _TARGETNAME $_CHIPNAME.cpu
1771 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1774 Work areas are small RAM areas associated with CPU targets.
1775 They are used by OpenOCD to speed up downloads,
1776 and to download small snippets of code to program flash chips.
1777 If the chip includes a form of ``on-chip-ram'' - and many do - define
1778 a work area if you can.
1779 Again using the at91sam7 as an example, this can look like:
1782 $_TARGETNAME configure -work-area-phys 0x00200000 \
1783 -work-area-size 0x4000 -work-area-backup 0
1786 @anchor{definecputargetsworkinginsmp}
1787 @subsection Define CPU targets working in SMP
1789 After setting targets, you can define a list of targets working in SMP.
1792 set _TARGETNAME_1 $_CHIPNAME.cpu1
1793 set _TARGETNAME_2 $_CHIPNAME.cpu2
1794 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1795 -coreid 0 -dbgbase $_DAP_DBG1
1796 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1797 -coreid 1 -dbgbase $_DAP_DBG2
1798 #define 2 targets working in smp.
1799 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1801 In the above example on cortex_a, 2 cpus are working in SMP.
1802 In SMP only one GDB instance is created and :
1804 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1805 @item halt command triggers the halt of all targets in the list.
1806 @item resume command triggers the write context and the restart of all targets in the list.
1807 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1808 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1809 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1812 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1813 command have been implemented.
1815 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1816 @item cortex_a smp off : disable SMP mode, the current target is the one
1817 displayed in the GDB session, only this target is now controlled by GDB
1818 session. This behaviour is useful during system boot up.
1819 @item cortex_a smp : display current SMP mode.
1820 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1827 #0 : coreid 0 is displayed to GDB ,
1828 #-> -1 : next resume triggers a real resume
1829 > cortex_a smp_gdb 1
1831 #0 :coreid 0 is displayed to GDB ,
1832 #->1 : next resume displays coreid 1 to GDB
1836 #1 :coreid 1 is displayed to GDB ,
1837 #->1 : next resume displays coreid 1 to GDB
1838 > cortex_a smp_gdb -1
1840 #1 :coreid 1 is displayed to GDB,
1841 #->-1 : next resume triggers a real resume
1845 @subsection Chip Reset Setup
1847 As a rule, you should put the @command{reset_config} command
1848 into the board file. Most things you think you know about a
1849 chip can be tweaked by the board.
1851 Some chips have specific ways the TRST and SRST signals are
1852 managed. In the unusual case that these are @emph{chip specific}
1853 and can never be changed by board wiring, they could go here.
1854 For example, some chips can't support JTAG debugging without
1857 Provide a @code{reset-assert} event handler if you can.
1858 Such a handler uses JTAG operations to reset the target,
1859 letting this target config be used in systems which don't
1860 provide the optional SRST signal, or on systems where you
1861 don't want to reset all targets at once.
1862 Such a handler might write to chip registers to force a reset,
1863 use a JRC to do that (preferable -- the target may be wedged!),
1864 or force a watchdog timer to trigger.
1865 (For Cortex-M targets, this is not necessary. The target
1866 driver knows how to use trigger an NVIC reset when SRST is
1869 Some chips need special attention during reset handling if
1870 they're going to be used with JTAG.
1871 An example might be needing to send some commands right
1872 after the target's TAP has been reset, providing a
1873 @code{reset-deassert-post} event handler that writes a chip
1874 register to report that JTAG debugging is being done.
1875 Another would be reconfiguring the watchdog so that it stops
1876 counting while the core is halted in the debugger.
1878 JTAG clocking constraints often change during reset, and in
1879 some cases target config files (rather than board config files)
1880 are the right places to handle some of those issues.
1881 For example, immediately after reset most chips run using a
1882 slower clock than they will use later.
1883 That means that after reset (and potentially, as OpenOCD
1884 first starts up) they must use a slower JTAG clock rate
1885 than they will use later.
1886 @xref{jtagspeed,,JTAG Speed}.
1888 @quotation Important
1889 When you are debugging code that runs right after chip
1890 reset, getting these issues right is critical.
1891 In particular, if you see intermittent failures when
1892 OpenOCD verifies the scan chain after reset,
1893 look at how you are setting up JTAG clocking.
1896 @anchor{theinittargetsprocedure}
1897 @subsection The init_targets procedure
1898 @cindex init_targets procedure
1900 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1901 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1902 procedure called @code{init_targets}, which will be executed when entering run stage
1903 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1904 Such procedure can be overridden by ``next level'' script (which sources the original).
1905 This concept facilitates code reuse when basic target config files provide generic configuration
1906 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1907 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1908 because sourcing them executes every initialization commands they provide.
1911 ### generic_file.cfg ###
1913 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1914 # basic initialization procedure ...
1917 proc init_targets @{@} @{
1918 # initializes generic chip with 4kB of flash and 1kB of RAM
1919 setup_my_chip MY_GENERIC_CHIP 4096 1024
1922 ### specific_file.cfg ###
1924 source [find target/generic_file.cfg]
1926 proc init_targets @{@} @{
1927 # initializes specific chip with 128kB of flash and 64kB of RAM
1928 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1932 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1933 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1935 For an example of this scheme see LPC2000 target config files.
1937 The @code{init_boards} procedure is a similar concept concerning board config files
1938 (@xref{theinitboardprocedure,,The init_board procedure}.)
1940 @anchor{theinittargeteventsprocedure}
1941 @subsection The init_target_events procedure
1942 @cindex init_target_events procedure
1944 A special procedure called @code{init_target_events} is run just after
1945 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1946 procedure}.) and before @code{init_board}
1947 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1948 to set up default target events for the targets that do not have those
1949 events already assigned.
1951 @subsection ARM Core Specific Hacks
1953 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1954 special high speed download features - enable it.
1956 If present, the MMU, the MPU and the CACHE should be disabled.
1958 Some ARM cores are equipped with trace support, which permits
1959 examination of the instruction and data bus activity. Trace
1960 activity is controlled through an ``Embedded Trace Module'' (ETM)
1961 on one of the core's scan chains. The ETM emits voluminous data
1962 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1963 If you are using an external trace port,
1964 configure it in your board config file.
1965 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1966 configure it in your target config file.
1969 etm config $_TARGETNAME 16 normal full etb
1970 etb config $_TARGETNAME $_CHIPNAME.etb
1973 @subsection Internal Flash Configuration
1975 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1977 @b{Never ever} in the ``target configuration file'' define any type of
1978 flash that is external to the chip. (For example a BOOT flash on
1979 Chip Select 0.) Such flash information goes in a board file - not
1980 the TARGET (chip) file.
1984 @item at91sam7x256 - has 256K flash YES enable it.
1985 @item str912 - has flash internal YES enable it.
1986 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1987 @item pxa270 - again - CS0 flash - it goes in the board file.
1990 @anchor{translatingconfigurationfiles}
1991 @section Translating Configuration Files
1993 If you have a configuration file for another hardware debugger
1994 or toolset (Abatron, BDI2000, BDI3000, CCS,
1995 Lauterbach, SEGGER, Macraigor, etc.), translating
1996 it into OpenOCD syntax is often quite straightforward. The most tricky
1997 part of creating a configuration script is oftentimes the reset init
1998 sequence where e.g. PLLs, DRAM and the like is set up.
2000 One trick that you can use when translating is to write small
2001 Tcl procedures to translate the syntax into OpenOCD syntax. This
2002 can avoid manual translation errors and make it easier to
2003 convert other scripts later on.
2005 Example of transforming quirky arguments to a simple search and
2009 # Lauterbach syntax(?)
2011 # Data.Set c15:0x042f %long 0x40000015
2013 # OpenOCD syntax when using procedure below.
2015 # setc15 0x01 0x00050078
2017 proc setc15 @{regs value@} @{
2020 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2022 arm mcr 15 [expr ($regs>>12)&0x7] \
2023 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2024 [expr ($regs>>8)&0x7] $value
2030 @node Server Configuration
2031 @chapter Server Configuration
2032 @cindex initialization
2033 The commands here are commonly found in the openocd.cfg file and are
2034 used to specify what TCP/IP ports are used, and how GDB should be
2037 @anchor{configurationstage}
2038 @section Configuration Stage
2039 @cindex configuration stage
2040 @cindex config command
2042 When the OpenOCD server process starts up, it enters a
2043 @emph{configuration stage} which is the only time that
2044 certain commands, @emph{configuration commands}, may be issued.
2045 Normally, configuration commands are only available
2046 inside startup scripts.
2048 In this manual, the definition of a configuration command is
2049 presented as a @emph{Config Command}, not as a @emph{Command}
2050 which may be issued interactively.
2051 The runtime @command{help} command also highlights configuration
2052 commands, and those which may be issued at any time.
2054 Those configuration commands include declaration of TAPs,
2056 the interface used for JTAG communication,
2057 and other basic setup.
2058 The server must leave the configuration stage before it
2059 may access or activate TAPs.
2060 After it leaves this stage, configuration commands may no
2063 @anchor{enteringtherunstage}
2064 @section Entering the Run Stage
2066 The first thing OpenOCD does after leaving the configuration
2067 stage is to verify that it can talk to the scan chain
2068 (list of TAPs) which has been configured.
2069 It will warn if it doesn't find TAPs it expects to find,
2070 or finds TAPs that aren't supposed to be there.
2071 You should see no errors at this point.
2072 If you see errors, resolve them by correcting the
2073 commands you used to configure the server.
2074 Common errors include using an initial JTAG speed that's too
2075 fast, and not providing the right IDCODE values for the TAPs
2078 Once OpenOCD has entered the run stage, a number of commands
2080 A number of these relate to the debug targets you may have declared.
2081 For example, the @command{mww} command will not be available until
2082 a target has been successfully instantiated.
2083 If you want to use those commands, you may need to force
2084 entry to the run stage.
2086 @deffn {Config Command} init
2087 This command terminates the configuration stage and
2088 enters the run stage. This helps when you need to have
2089 the startup scripts manage tasks such as resetting the target,
2090 programming flash, etc. To reset the CPU upon startup, add "init" and
2091 "reset" at the end of the config script or at the end of the OpenOCD
2092 command line using the @option{-c} command line switch.
2094 If this command does not appear in any startup/configuration file
2095 OpenOCD executes the command for you after processing all
2096 configuration files and/or command line options.
2098 @b{NOTE:} This command normally occurs at or near the end of your
2099 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2100 targets ready. For example: If your openocd.cfg file needs to
2101 read/write memory on your target, @command{init} must occur before
2102 the memory read/write commands. This includes @command{nand probe}.
2105 @deffn {Overridable Procedure} jtag_init
2106 This is invoked at server startup to verify that it can talk
2107 to the scan chain (list of TAPs) which has been configured.
2109 The default implementation first tries @command{jtag arp_init},
2110 which uses only a lightweight JTAG reset before examining the
2112 If that fails, it tries again, using a harder reset
2113 from the overridable procedure @command{init_reset}.
2115 Implementations must have verified the JTAG scan chain before
2117 This is done by calling @command{jtag arp_init}
2118 (or @command{jtag arp_init-reset}).
2122 @section TCP/IP Ports
2127 The OpenOCD server accepts remote commands in several syntaxes.
2128 Each syntax uses a different TCP/IP port, which you may specify
2129 only during configuration (before those ports are opened).
2131 For reasons including security, you may wish to prevent remote
2132 access using one or more of these ports.
2133 In such cases, just specify the relevant port number as "disabled".
2134 If you disable all access through TCP/IP, you will need to
2135 use the command line @option{-pipe} option.
2138 @deffn {Command} gdb_port [number]
2140 Normally gdb listens to a TCP/IP port, but GDB can also
2141 communicate via pipes(stdin/out or named pipes). The name
2142 "gdb_port" stuck because it covers probably more than 90% of
2143 the normal use cases.
2145 No arguments reports GDB port. "pipe" means listen to stdin
2146 output to stdout, an integer is base port number, "disabled"
2147 disables the gdb server.
2149 When using "pipe", also use log_output to redirect the log
2150 output to a file so as not to flood the stdin/out pipes.
2152 The -p/--pipe option is deprecated and a warning is printed
2153 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2155 Any other string is interpreted as named pipe to listen to.
2156 Output pipe is the same name as input pipe, but with 'o' appended,
2157 e.g. /var/gdb, /var/gdbo.
2159 The GDB port for the first target will be the base port, the
2160 second target will listen on gdb_port + 1, and so on.
2161 When not specified during the configuration stage,
2162 the port @var{number} defaults to 3333.
2163 When @var{number} is not a numeric value, incrementing it to compute
2164 the next port number does not work. In this case, specify the proper
2165 @var{number} for each target by using the option @code{-gdb-port} of the
2166 commands @command{target create} or @command{$target_name configure}.
2167 @xref{gdbportoverride,,option -gdb-port}.
2169 Note: when using "gdb_port pipe", increasing the default remote timeout in
2170 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2171 cause initialization to fail with "Unknown remote qXfer reply: OK".
2174 @deffn {Command} tcl_port [number]
2175 Specify or query the port used for a simplified RPC
2176 connection that can be used by clients to issue TCL commands and get the
2177 output from the Tcl engine.
2178 Intended as a machine interface.
2179 When not specified during the configuration stage,
2180 the port @var{number} defaults to 6666.
2181 When specified as "disabled", this service is not activated.
2184 @deffn {Command} telnet_port [number]
2185 Specify or query the
2186 port on which to listen for incoming telnet connections.
2187 This port is intended for interaction with one human through TCL commands.
2188 When not specified during the configuration stage,
2189 the port @var{number} defaults to 4444.
2190 When specified as "disabled", this service is not activated.
2193 @anchor{gdbconfiguration}
2194 @section GDB Configuration
2196 @cindex GDB configuration
2197 You can reconfigure some GDB behaviors if needed.
2198 The ones listed here are static and global.
2199 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2200 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2202 @anchor{gdbbreakpointoverride}
2203 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2204 Force breakpoint type for gdb @command{break} commands.
2205 This option supports GDB GUIs which don't
2206 distinguish hard versus soft breakpoints, if the default OpenOCD and
2207 GDB behaviour is not sufficient. GDB normally uses hardware
2208 breakpoints if the memory map has been set up for flash regions.
2211 @anchor{gdbflashprogram}
2212 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2213 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2214 vFlash packet is received.
2215 The default behaviour is @option{enable}.
2218 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2219 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2220 requested. GDB will then know when to set hardware breakpoints, and program flash
2221 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2222 for flash programming to work.
2223 Default behaviour is @option{enable}.
2224 @xref{gdbflashprogram,,gdb_flash_program}.
2227 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2228 Specifies whether data aborts cause an error to be reported
2229 by GDB memory read packets.
2230 The default behaviour is @option{disable};
2231 use @option{enable} see these errors reported.
2234 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2235 Specifies whether register accesses requested by GDB register read/write
2236 packets report errors or not.
2237 The default behaviour is @option{disable};
2238 use @option{enable} see these errors reported.
2241 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2242 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2243 The default behaviour is @option{enable}.
2246 @deffn {Command} gdb_save_tdesc
2247 Saves the target description file to the local file system.
2249 The file name is @i{target_name}.xml.
2252 @anchor{eventpolling}
2253 @section Event Polling
2255 Hardware debuggers are parts of asynchronous systems,
2256 where significant events can happen at any time.
2257 The OpenOCD server needs to detect some of these events,
2258 so it can report them to through TCL command line
2261 Examples of such events include:
2264 @item One of the targets can stop running ... maybe it triggers
2265 a code breakpoint or data watchpoint, or halts itself.
2266 @item Messages may be sent over ``debug message'' channels ... many
2267 targets support such messages sent over JTAG,
2268 for receipt by the person debugging or tools.
2269 @item Loss of power ... some adapters can detect these events.
2270 @item Resets not issued through JTAG ... such reset sources
2271 can include button presses or other system hardware, sometimes
2272 including the target itself (perhaps through a watchdog).
2273 @item Debug instrumentation sometimes supports event triggering
2274 such as ``trace buffer full'' (so it can quickly be emptied)
2275 or other signals (to correlate with code behavior).
2278 None of those events are signaled through standard JTAG signals.
2279 However, most conventions for JTAG connectors include voltage
2280 level and system reset (SRST) signal detection.
2281 Some connectors also include instrumentation signals, which
2282 can imply events when those signals are inputs.
2284 In general, OpenOCD needs to periodically check for those events,
2285 either by looking at the status of signals on the JTAG connector
2286 or by sending synchronous ``tell me your status'' JTAG requests
2287 to the various active targets.
2288 There is a command to manage and monitor that polling,
2289 which is normally done in the background.
2291 @deffn Command poll [@option{on}|@option{off}]
2292 Poll the current target for its current state.
2293 (Also, @pxref{targetcurstate,,target curstate}.)
2294 If that target is in debug mode, architecture
2295 specific information about the current state is printed.
2296 An optional parameter
2297 allows background polling to be enabled and disabled.
2299 You could use this from the TCL command shell, or
2300 from GDB using @command{monitor poll} command.
2301 Leave background polling enabled while you're using GDB.
2304 background polling: on
2305 target state: halted
2306 target halted in ARM state due to debug-request, \
2307 current mode: Supervisor
2308 cpsr: 0x800000d3 pc: 0x11081bfc
2309 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2314 @node Debug Adapter Configuration
2315 @chapter Debug Adapter Configuration
2316 @cindex config file, interface
2317 @cindex interface config file
2319 Correctly installing OpenOCD includes making your operating system give
2320 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2321 are used to select which one is used, and to configure how it is used.
2324 Because OpenOCD started out with a focus purely on JTAG, you may find
2325 places where it wrongly presumes JTAG is the only transport protocol
2326 in use. Be aware that recent versions of OpenOCD are removing that
2327 limitation. JTAG remains more functional than most other transports.
2328 Other transports do not support boundary scan operations, or may be
2329 specific to a given chip vendor. Some might be usable only for
2330 programming flash memory, instead of also for debugging.
2333 Debug Adapters/Interfaces/Dongles are normally configured
2334 through commands in an interface configuration
2335 file which is sourced by your @file{openocd.cfg} file, or
2336 through a command line @option{-f interface/....cfg} option.
2339 source [find interface/olimex-jtag-tiny.cfg]
2343 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2344 A few cases are so simple that you only need to say what driver to use:
2348 adapter driver jlink
2351 Most adapters need a bit more configuration than that.
2354 @section Adapter Configuration
2356 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2357 using. Depending on the type of adapter, you may need to use one or
2358 more additional commands to further identify or configure the adapter.
2360 @deffn {Config Command} {adapter driver} name
2361 Use the adapter driver @var{name} to connect to the
2365 @deffn Command {adapter list}
2366 List the debug adapter drivers that have been built into
2367 the running copy of OpenOCD.
2369 @deffn Command {adapter transports} transport_name+
2370 Specifies the transports supported by this debug adapter.
2371 The adapter driver builds-in similar knowledge; use this only
2372 when external configuration (such as jumpering) changes what
2373 the hardware can support.
2378 @deffn Command {adapter name}
2379 Returns the name of the debug adapter driver being used.
2382 @anchor{adapter_usb_location}
2383 @deffn Command {adapter usb location} [<bus>-<port>[.<port>]...]
2384 Displays or specifies the physical USB port of the adapter to use. The path
2385 roots at @var{bus} and walks down the physical ports, with each
2386 @var{port} option specifying a deeper level in the bus topology, the last
2387 @var{port} denoting where the target adapter is actually plugged.
2388 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2390 This command is only available if your libusb1 is at least version 1.0.16.
2393 @section Interface Drivers
2395 Each of the interface drivers listed here must be explicitly
2396 enabled when OpenOCD is configured, in order to be made
2397 available at run time.
2399 @deffn {Interface Driver} {amt_jtagaccel}
2400 Amontec Chameleon in its JTAG Accelerator configuration,
2401 connected to a PC's EPP mode parallel port.
2402 This defines some driver-specific commands:
2404 @deffn {Config Command} {parport_port} number
2405 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2406 the number of the @file{/dev/parport} device.
2409 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2410 Displays status of RTCK option.
2411 Optionally sets that option first.
2415 @deffn {Interface Driver} {arm-jtag-ew}
2416 Olimex ARM-JTAG-EW USB adapter
2417 This has one driver-specific command:
2419 @deffn Command {armjtagew_info}
2424 @deffn {Interface Driver} {at91rm9200}
2425 Supports bitbanged JTAG from the local system,
2426 presuming that system is an Atmel AT91rm9200
2427 and a specific set of GPIOs is used.
2428 @c command: at91rm9200_device NAME
2429 @c chooses among list of bit configs ... only one option
2432 @deffn {Interface Driver} {cmsis-dap}
2433 ARM CMSIS-DAP compliant based adapter.
2435 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2436 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2437 the driver will attempt to auto detect the CMSIS-DAP device.
2438 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2440 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2444 @deffn {Config Command} {cmsis_dap_serial} [serial]
2445 Specifies the @var{serial} of the CMSIS-DAP device to use.
2446 If not specified, serial numbers are not considered.
2449 @deffn {Command} {cmsis-dap info}
2450 Display various device information, like hardware version, firmware version, current bus status.
2454 @deffn {Interface Driver} {dummy}
2455 A dummy software-only driver for debugging.
2458 @deffn {Interface Driver} {ep93xx}
2459 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2462 @deffn {Interface Driver} {ftdi}
2463 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2464 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2466 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2467 bypassing intermediate libraries like libftdi or D2XX.
2469 Support for new FTDI based adapters can be added completely through
2470 configuration files, without the need to patch and rebuild OpenOCD.
2472 The driver uses a signal abstraction to enable Tcl configuration files to
2473 define outputs for one or several FTDI GPIO. These outputs can then be
2474 controlled using the @command{ftdi_set_signal} command. Special signal names
2475 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2476 will be used for their customary purpose. Inputs can be read using the
2477 @command{ftdi_get_signal} command.
2479 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2480 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2481 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2482 required by the protocol, to tell the adapter to drive the data output onto
2483 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2485 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2486 be controlled differently. In order to support tristateable signals such as
2487 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2488 signal. The following output buffer configurations are supported:
2491 @item Push-pull with one FTDI output as (non-)inverted data line
2492 @item Open drain with one FTDI output as (non-)inverted output-enable
2493 @item Tristate with one FTDI output as (non-)inverted data line and another
2494 FTDI output as (non-)inverted output-enable
2495 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2496 switching data and direction as necessary
2499 These interfaces have several commands, used to configure the driver
2500 before initializing the JTAG scan chain:
2502 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2503 The vendor ID and product ID of the adapter. Up to eight
2504 [@var{vid}, @var{pid}] pairs may be given, e.g.
2506 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2510 @deffn {Config Command} {ftdi_device_desc} description
2511 Provides the USB device description (the @emph{iProduct string})
2512 of the adapter. If not specified, the device description is ignored
2513 during device selection.
2516 @deffn {Config Command} {ftdi_serial} serial-number
2517 Specifies the @var{serial-number} of the adapter to use,
2518 in case the vendor provides unique IDs and more than one adapter
2519 is connected to the host.
2520 If not specified, serial numbers are not considered.
2521 (Note that USB serial numbers can be arbitrary Unicode strings,
2522 and are not restricted to containing only decimal digits.)
2525 @deffn {Config Command} {ftdi_location} <bus>-<port>[.<port>]...
2526 @emph{DEPRECATED -- avoid using this.
2527 Use the command @ref{adapter_usb_location,,adapter usb location} instead.}
2529 Specifies the physical USB port of the adapter to use. The path
2530 roots at @var{bus} and walks down the physical ports, with each
2531 @var{port} option specifying a deeper level in the bus topology, the last
2532 @var{port} denoting where the target adapter is actually plugged.
2533 The USB bus topology can be queried with the command @emph{lsusb -t}.
2535 This command is only available if your libusb1 is at least version 1.0.16.
2538 @deffn {Config Command} {ftdi_channel} channel
2539 Selects the channel of the FTDI device to use for MPSSE operations. Most
2540 adapters use the default, channel 0, but there are exceptions.
2543 @deffn {Config Command} {ftdi_layout_init} data direction
2544 Specifies the initial values of the FTDI GPIO data and direction registers.
2545 Each value is a 16-bit number corresponding to the concatenation of the high
2546 and low FTDI GPIO registers. The values should be selected based on the
2547 schematics of the adapter, such that all signals are set to safe levels with
2548 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2549 and initially asserted reset signals.
2552 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2553 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2554 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2555 register bitmasks to tell the driver the connection and type of the output
2556 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2557 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2558 used with inverting data inputs and @option{-data} with non-inverting inputs.
2559 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2560 not-output-enable) input to the output buffer is connected. The options
2561 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2562 with the method @command{ftdi_get_signal}.
2564 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2565 simple open-collector transistor driver would be specified with @option{-oe}
2566 only. In that case the signal can only be set to drive low or to Hi-Z and the
2567 driver will complain if the signal is set to drive high. Which means that if
2568 it's a reset signal, @command{reset_config} must be specified as
2569 @option{srst_open_drain}, not @option{srst_push_pull}.
2571 A special case is provided when @option{-data} and @option{-oe} is set to the
2572 same bitmask. Then the FTDI pin is considered being connected straight to the
2573 target without any buffer. The FTDI pin is then switched between output and
2574 input as necessary to provide the full set of low, high and Hi-Z
2575 characteristics. In all other cases, the pins specified in a signal definition
2576 are always driven by the FTDI.
2578 If @option{-alias} or @option{-nalias} is used, the signal is created
2579 identical (or with data inverted) to an already specified signal
2583 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2584 Set a previously defined signal to the specified level.
2586 @item @option{0}, drive low
2587 @item @option{1}, drive high
2588 @item @option{z}, set to high-impedance
2592 @deffn {Command} {ftdi_get_signal} name
2593 Get the value of a previously defined signal.
2596 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2597 Configure TCK edge at which the adapter samples the value of the TDO signal
2599 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2600 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2601 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2602 stability at higher JTAG clocks.
2604 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2605 @item @option{falling}, sample TDO on falling edge of TCK
2609 For example adapter definitions, see the configuration files shipped in the
2610 @file{interface/ftdi} directory.
2614 @deffn {Interface Driver} {ft232r}
2615 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2616 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2617 It currently doesn't support using CBUS pins as GPIO.
2619 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2626 @item DCD(10) - SRST
2629 User can change default pinout by supplying configuration
2630 commands with GPIO numbers or RS232 signal names.
2631 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2632 They differ from physical pin numbers.
2633 For details see actual FTDI chip datasheets.
2634 Every JTAG line must be configured to unique GPIO number
2635 different than any other JTAG line, even those lines
2636 that are sometimes not used like TRST or SRST.
2650 These interfaces have several commands, used to configure the driver
2651 before initializing the JTAG scan chain:
2653 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2654 The vendor ID and product ID of the adapter. If not specified, default
2655 0x0403:0x6001 is used.
2658 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2659 Specifies the @var{serial} of the adapter to use, in case the
2660 vendor provides unique IDs and more than one adapter is connected to
2661 the host. If not specified, serial numbers are not considered.
2664 @deffn {Config Command} {ft232r_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2665 Set four JTAG GPIO numbers at once.
2666 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2669 @deffn {Config Command} {ft232r_tck_num} @var{tck}
2670 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2673 @deffn {Config Command} {ft232r_tms_num} @var{tms}
2674 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2677 @deffn {Config Command} {ft232r_tdi_num} @var{tdi}
2678 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2681 @deffn {Config Command} {ft232r_tdo_num} @var{tdo}
2682 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2685 @deffn {Config Command} {ft232r_trst_num} @var{trst}
2686 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2689 @deffn {Config Command} {ft232r_srst_num} @var{srst}
2690 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2693 @deffn {Config Command} {ft232r_restore_serial} @var{word}
2694 Restore serial port after JTAG. This USB bitmode control word
2695 (16-bit) will be sent before quit. Lower byte should
2696 set GPIO direction register to a "sane" state:
2697 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2698 byte is usually 0 to disable bitbang mode.
2699 When kernel driver reattaches, serial port should continue to work.
2700 Value 0xFFFF disables sending control word and serial port,
2701 then kernel driver will not reattach.
2702 If not specified, default 0xFFFF is used.
2707 @deffn {Interface Driver} {remote_bitbang}
2708 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2709 with a remote process and sends ASCII encoded bitbang requests to that process
2710 instead of directly driving JTAG.
2712 The remote_bitbang driver is useful for debugging software running on
2713 processors which are being simulated.
2715 @deffn {Config Command} {remote_bitbang_port} number
2716 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2717 sockets instead of TCP.
2720 @deffn {Config Command} {remote_bitbang_host} hostname
2721 Specifies the hostname of the remote process to connect to using TCP, or the
2722 name of the UNIX socket to use if remote_bitbang_port is 0.
2725 For example, to connect remotely via TCP to the host foobar you might have
2729 adapter driver remote_bitbang
2730 remote_bitbang_port 3335
2731 remote_bitbang_host foobar
2734 To connect to another process running locally via UNIX sockets with socket
2738 adapter driver remote_bitbang
2739 remote_bitbang_port 0
2740 remote_bitbang_host mysocket
2744 @deffn {Interface Driver} {usb_blaster}
2745 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2746 for FTDI chips. These interfaces have several commands, used to
2747 configure the driver before initializing the JTAG scan chain:
2749 @deffn {Config Command} {usb_blaster_device_desc} description
2750 Provides the USB device description (the @emph{iProduct string})
2751 of the FTDI FT245 device. If not
2752 specified, the FTDI default value is used. This setting is only valid
2753 if compiled with FTD2XX support.
2756 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2757 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2758 default values are used.
2759 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2760 Altera USB-Blaster (default):
2762 usb_blaster_vid_pid 0x09FB 0x6001
2764 The following VID/PID is for Kolja Waschk's USB JTAG:
2766 usb_blaster_vid_pid 0x16C0 0x06AD
2770 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2771 Sets the state or function of the unused GPIO pins on USB-Blasters
2772 (pins 6 and 8 on the female JTAG header). These pins can be used as
2773 SRST and/or TRST provided the appropriate connections are made on the
2776 For example, to use pin 6 as SRST:
2778 usb_blaster_pin pin6 s
2779 reset_config srst_only
2783 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2784 Chooses the low level access method for the adapter. If not specified,
2785 @option{ftdi} is selected unless it wasn't enabled during the
2786 configure stage. USB-Blaster II needs @option{ublast2}.
2789 @deffn {Command} {usb_blaster_firmware} @var{path}
2790 This command specifies @var{path} to access USB-Blaster II firmware
2791 image. To be used with USB-Blaster II only.
2796 @deffn {Interface Driver} {gw16012}
2797 Gateworks GW16012 JTAG programmer.
2798 This has one driver-specific command:
2800 @deffn {Config Command} {parport_port} [port_number]
2801 Display either the address of the I/O port
2802 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2803 If a parameter is provided, first switch to use that port.
2804 This is a write-once setting.
2808 @deffn {Interface Driver} {jlink}
2809 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2812 @quotation Compatibility Note
2813 SEGGER released many firmware versions for the many hardware versions they
2814 produced. OpenOCD was extensively tested and intended to run on all of them,
2815 but some combinations were reported as incompatible. As a general
2816 recommendation, it is advisable to use the latest firmware version
2817 available for each hardware version. However the current V8 is a moving
2818 target, and SEGGER firmware versions released after the OpenOCD was
2819 released may not be compatible. In such cases it is recommended to
2820 revert to the last known functional version. For 0.5.0, this is from
2821 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2822 version is from "May 3 2012 18:36:22", packed with 4.46f.
2825 @deffn {Command} {jlink hwstatus}
2826 Display various hardware related information, for example target voltage and pin
2829 @deffn {Command} {jlink freemem}
2830 Display free device internal memory.
2832 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2833 Set the JTAG command version to be used. Without argument, show the actual JTAG
2836 @deffn {Command} {jlink config}
2837 Display the device configuration.
2839 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2840 Set the target power state on JTAG-pin 19. Without argument, show the target
2843 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2844 Set the MAC address of the device. Without argument, show the MAC address.
2846 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2847 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2848 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2851 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2852 Set the USB address of the device. This will also change the USB Product ID
2853 (PID) of the device. Without argument, show the USB address.
2855 @deffn {Command} {jlink config reset}
2856 Reset the current configuration.
2858 @deffn {Command} {jlink config write}
2859 Write the current configuration to the internal persistent storage.
2861 @deffn {Command} {jlink emucom write <channel> <data>}
2862 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2865 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2866 the EMUCOM channel 0x10:
2868 > jlink emucom write 0x10 aa0b23
2871 @deffn {Command} {jlink emucom read <channel> <length>}
2872 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2875 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2877 > jlink emucom read 0x0 4
2881 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2882 Set the USB address of the interface, in case more than one adapter is connected
2883 to the host. If not specified, USB addresses are not considered. Device
2884 selection via USB address is deprecated and the serial number should be used
2887 As a configuration command, it can be used only before 'init'.
2889 @deffn {Config} {jlink serial} <serial number>
2890 Set the serial number of the interface, in case more than one adapter is
2891 connected to the host. If not specified, serial numbers are not considered.
2893 As a configuration command, it can be used only before 'init'.
2897 @deffn {Interface Driver} {kitprog}
2898 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2899 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2900 families, but it is possible to use it with some other devices. If you are using
2901 this adapter with a PSoC or a PRoC, you may need to add
2902 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2903 configuration script.
2905 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2906 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2907 be used with this driver, and must either be used with the cmsis-dap driver or
2908 switched back to KitProg mode. See the Cypress KitProg User Guide for
2909 instructions on how to switch KitProg modes.
2913 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2915 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2916 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2917 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2918 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2919 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2920 SWD sequence must be sent after every target reset in order to re-establish
2921 communications with the target.
2922 @item Due in part to the limitation above, KitProg devices with firmware below
2923 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2924 communicate with PSoC 5LP devices. This is because, assuming debug is not
2925 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2926 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2927 could only be sent with an acquisition sequence.
2930 @deffn {Config Command} {kitprog_init_acquire_psoc}
2931 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2932 Please be aware that the acquisition sequence hard-resets the target.
2935 @deffn {Config Command} {kitprog_serial} serial
2936 Select a KitProg device by its @var{serial}. If left unspecified, the first
2937 device detected by OpenOCD will be used.
2940 @deffn {Command} {kitprog acquire_psoc}
2941 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2942 outside of the target-specific configuration scripts since it hard-resets the
2943 target as a side-effect.
2944 This is necessary for "reset halt" on some PSoC 4 series devices.
2947 @deffn {Command} {kitprog info}
2948 Display various adapter information, such as the hardware version, firmware
2949 version, and target voltage.
2953 @deffn {Interface Driver} {parport}
2954 Supports PC parallel port bit-banging cables:
2955 Wigglers, PLD download cable, and more.
2956 These interfaces have several commands, used to configure the driver
2957 before initializing the JTAG scan chain:
2959 @deffn {Config Command} {parport_cable} name
2960 Set the layout of the parallel port cable used to connect to the target.
2961 This is a write-once setting.
2962 Currently valid cable @var{name} values include:
2965 @item @b{altium} Altium Universal JTAG cable.
2966 @item @b{arm-jtag} Same as original wiggler except SRST and
2967 TRST connections reversed and TRST is also inverted.
2968 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2969 in configuration mode. This is only used to
2970 program the Chameleon itself, not a connected target.
2971 @item @b{dlc5} The Xilinx Parallel cable III.
2972 @item @b{flashlink} The ST Parallel cable.
2973 @item @b{lattice} Lattice ispDOWNLOAD Cable
2974 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2976 Amontec's Chameleon Programmer. The new version available from
2977 the website uses the original Wiggler layout ('@var{wiggler}')
2978 @item @b{triton} The parallel port adapter found on the
2979 ``Karo Triton 1 Development Board''.
2980 This is also the layout used by the HollyGates design
2981 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2982 @item @b{wiggler} The original Wiggler layout, also supported by
2983 several clones, such as the Olimex ARM-JTAG
2984 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2985 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2989 @deffn {Config Command} {parport_port} [port_number]
2990 Display either the address of the I/O port
2991 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2992 If a parameter is provided, first switch to use that port.
2993 This is a write-once setting.
2995 When using PPDEV to access the parallel port, use the number of the parallel port:
2996 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2997 you may encounter a problem.
3000 @deffn Command {parport_toggling_time} [nanoseconds]
3001 Displays how many nanoseconds the hardware needs to toggle TCK;
3002 the parport driver uses this value to obey the
3003 @command{adapter speed} configuration.
3004 When the optional @var{nanoseconds} parameter is given,
3005 that setting is changed before displaying the current value.
3007 The default setting should work reasonably well on commodity PC hardware.
3008 However, you may want to calibrate for your specific hardware.
3010 To measure the toggling time with a logic analyzer or a digital storage
3011 oscilloscope, follow the procedure below:
3013 > parport_toggling_time 1000
3016 This sets the maximum JTAG clock speed of the hardware, but
3017 the actual speed probably deviates from the requested 500 kHz.
3018 Now, measure the time between the two closest spaced TCK transitions.
3019 You can use @command{runtest 1000} or something similar to generate a
3020 large set of samples.
3021 Update the setting to match your measurement:
3023 > parport_toggling_time <measured nanoseconds>
3025 Now the clock speed will be a better match for @command{adapter speed}
3026 command given in OpenOCD scripts and event handlers.
3028 You can do something similar with many digital multimeters, but note
3029 that you'll probably need to run the clock continuously for several
3030 seconds before it decides what clock rate to show. Adjust the
3031 toggling time up or down until the measured clock rate is a good
3032 match with the rate you specified in the @command{adapter speed} command;
3037 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3038 This will configure the parallel driver to write a known
3039 cable-specific value to the parallel interface on exiting OpenOCD.
3042 For example, the interface configuration file for a
3043 classic ``Wiggler'' cable on LPT2 might look something like this:
3046 adapter driver parport
3048 parport_cable wiggler
3052 @deffn {Interface Driver} {presto}
3053 ASIX PRESTO USB JTAG programmer.
3054 @deffn {Config Command} {presto_serial} serial_string
3055 Configures the USB serial number of the Presto device to use.
3059 @deffn {Interface Driver} {rlink}
3060 Raisonance RLink USB adapter
3063 @deffn {Interface Driver} {usbprog}
3064 usbprog is a freely programmable USB adapter.
3067 @deffn {Interface Driver} {vsllink}
3068 vsllink is part of Versaloon which is a versatile USB programmer.
3071 This defines quite a few driver-specific commands,
3072 which are not currently documented here.
3076 @anchor{hla_interface}
3077 @deffn {Interface Driver} {hla}
3078 This is a driver that supports multiple High Level Adapters.
3079 This type of adapter does not expose some of the lower level api's
3080 that OpenOCD would normally use to access the target.
3082 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3083 and Nuvoton Nu-Link.
3084 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3085 versions of firmware where serial number is reset after first use. Suggest
3086 using ST firmware update utility to upgrade ST-LINK firmware even if current
3087 version reported is V2.J21.S4.
3089 @deffn {Config Command} {hla_device_desc} description
3090 Currently Not Supported.
3093 @deffn {Config Command} {hla_serial} serial
3094 Specifies the serial number of the adapter.
3097 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3098 Specifies the adapter layout to use.
3101 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3102 Pairs of vendor IDs and product IDs of the device.
3105 @deffn {Command} {hla_command} command
3106 Execute a custom adapter-specific command. The @var{command} string is
3107 passed as is to the underlying adapter layout handler.
3111 @anchor{st_link_dap_interface}
3112 @deffn {Interface Driver} {st-link}
3113 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3114 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3115 directly access the arm ADIv5 DAP.
3117 The new API provide access to multiple AP on the same DAP, but the
3118 maximum number of the AP port is limited by the specific firmware version
3119 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3120 An error is returned for any AP number above the maximum allowed value.
3122 @emph{Note:} Either these same adapters and their older versions are
3123 also supported by @ref{hla_interface, the hla interface driver}.
3125 @deffn {Config Command} {st-link serial} serial
3126 Specifies the serial number of the adapter.
3129 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3130 Pairs of vendor IDs and product IDs of the device.
3134 @deffn {Interface Driver} {opendous}
3135 opendous-jtag is a freely programmable USB adapter.
3138 @deffn {Interface Driver} {ulink}
3139 This is the Keil ULINK v1 JTAG debugger.
3142 @deffn {Interface Driver} {xds110}
3143 The XDS110 is included as the embedded debug probe on many Texas Instruments
3144 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3145 debug probe with the added capability to supply power to the target board. The
3146 following commands are supported by the XDS110 driver:
3148 @deffn {Config Command} {xds110 serial} serial_string
3149 Specifies the serial number of which XDS110 probe to use. Otherwise, the first
3150 XDS110 found will be used.
3153 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3154 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3155 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3156 can be set to any value in the range 1800 to 3600 millivolts.
3159 @deffn {Command} {xds110 info}
3160 Displays information about the connected XDS110 debug probe (e.g. firmware
3165 @deffn {Interface Driver} {xlnx_pcie_xvc}
3166 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3167 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3168 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3169 exposed via extended capability registers in the PCI Express configuration space.
3171 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3173 @deffn {Config Command} {xlnx_pcie_xvc_config} device
3174 Specifies the PCI Express device via parameter @var{device} to use.
3176 The correct value for @var{device} can be obtained by looking at the output
3177 of lscpi -D (first column) for the corresponding device.
3179 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3184 @deffn {Interface Driver} {ZY1000}
3185 This is the Zylin ZY1000 JTAG debugger.
3189 This defines some driver-specific commands,
3190 which are not currently documented here.
3193 @deffn Command power [@option{on}|@option{off}]
3194 Turn power switch to target on/off.
3195 No arguments: print status.
3198 @deffn {Interface Driver} {bcm2835gpio}
3199 This SoC is present in Raspberry Pi which is a cheap single-board computer
3200 exposing some GPIOs on its expansion header.
3202 The driver accesses memory-mapped GPIO peripheral registers directly
3203 for maximum performance, but the only possible race condition is for
3204 the pins' modes/muxing (which is highly unlikely), so it should be
3205 able to coexist nicely with both sysfs bitbanging and various
3206 peripherals' kernel drivers. The driver restores the previous
3207 configuration on exit.
3209 See @file{interface/raspberrypi-native.cfg} for a sample config and
3214 @deffn {Interface Driver} {imx_gpio}
3215 i.MX SoC is present in many community boards. Wandboard is an example
3216 of the one which is most popular.
3218 This driver is mostly the same as bcm2835gpio.
3220 See @file{interface/imx-native.cfg} for a sample config and
3226 @deffn {Interface Driver} {openjtag}
3227 OpenJTAG compatible USB adapter.
3228 This defines some driver-specific commands:
3230 @deffn {Config Command} {openjtag_variant} variant
3231 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3232 Currently valid @var{variant} values include:
3235 @item @b{standard} Standard variant (default).
3236 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3237 (see @uref{http://www.cypress.com/?rID=82870}).
3241 @deffn {Config Command} {openjtag_device_desc} string
3242 The USB device description string of the adapter.
3243 This value is only used with the standard variant.
3248 @deffn {Interface Driver} {jtag_dpi}
3249 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3250 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3251 DPI server interface.
3253 @deffn {Config Command} {jtag_dpi_set_port} port
3254 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3257 @deffn {Config Command} {jtag_dpi_set_address} address
3258 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3263 @section Transport Configuration
3265 As noted earlier, depending on the version of OpenOCD you use,
3266 and the debug adapter you are using,
3267 several transports may be available to
3268 communicate with debug targets (or perhaps to program flash memory).
3269 @deffn Command {transport list}
3270 displays the names of the transports supported by this
3274 @deffn Command {transport select} @option{transport_name}
3275 Select which of the supported transports to use in this OpenOCD session.
3277 When invoked with @option{transport_name}, attempts to select the named
3278 transport. The transport must be supported by the debug adapter
3279 hardware and by the version of OpenOCD you are using (including the
3282 If no transport has been selected and no @option{transport_name} is
3283 provided, @command{transport select} auto-selects the first transport
3284 supported by the debug adapter.
3286 @command{transport select} always returns the name of the session's selected
3290 @subsection JTAG Transport
3292 JTAG is the original transport supported by OpenOCD, and most
3293 of the OpenOCD commands support it.
3294 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3295 each of which must be explicitly declared.
3296 JTAG supports both debugging and boundary scan testing.
3297 Flash programming support is built on top of debug support.
3299 JTAG transport is selected with the command @command{transport select
3300 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3301 driver} (in which case the command is @command{transport select hla_jtag})
3302 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3303 the command is @command{transport select dapdirect_jtag}).
3305 @subsection SWD Transport
3307 @cindex Serial Wire Debug
3308 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3309 Debug Access Point (DAP, which must be explicitly declared.
3310 (SWD uses fewer signal wires than JTAG.)
3311 SWD is debug-oriented, and does not support boundary scan testing.
3312 Flash programming support is built on top of debug support.
3313 (Some processors support both JTAG and SWD.)
3315 SWD transport is selected with the command @command{transport select
3316 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3317 driver} (in which case the command is @command{transport select hla_swd})
3318 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3319 the command is @command{transport select dapdirect_swd}).
3321 @deffn Command {swd newdap} ...
3322 Declares a single DAP which uses SWD transport.
3323 Parameters are currently the same as "jtag newtap" but this is
3326 @deffn Command {swd wcr trn prescale}
3327 Updates TRN (turnaround delay) and prescaling.fields of the
3328 Wire Control Register (WCR).
3329 No parameters: displays current settings.
3332 @subsection SPI Transport
3334 @cindex Serial Peripheral Interface
3335 The Serial Peripheral Interface (SPI) is a general purpose transport
3336 which uses four wire signaling. Some processors use it as part of a
3337 solution for flash programming.
3339 @anchor{swimtransport}
3340 @subsection SWIM Transport
3342 @cindex Single Wire Interface Module
3343 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3344 by the STMicroelectronics MCU family STM8 and documented in the
3345 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3347 SWIM does not support boundary scan testing nor multiple cores.
3349 The SWIM transport is selected with the command @command{transport select swim}.
3351 The concept of TAPs does not fit in the protocol since SWIM does not implement
3352 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3353 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3354 The TAP definition must precede the target definition command
3355 @command{target create target_name stm8 -chain-position basename.tap_type}.
3359 JTAG clock setup is part of system setup.
3360 It @emph{does not belong with interface setup} since any interface
3361 only knows a few of the constraints for the JTAG clock speed.
3362 Sometimes the JTAG speed is
3363 changed during the target initialization process: (1) slow at
3364 reset, (2) program the CPU clocks, (3) run fast.
3365 Both the "slow" and "fast" clock rates are functions of the
3366 oscillators used, the chip, the board design, and sometimes
3367 power management software that may be active.
3369 The speed used during reset, and the scan chain verification which
3370 follows reset, can be adjusted using a @code{reset-start}
3371 target event handler.
3372 It can then be reconfigured to a faster speed by a
3373 @code{reset-init} target event handler after it reprograms those
3374 CPU clocks, or manually (if something else, such as a boot loader,
3375 sets up those clocks).
3376 @xref{targetevents,,Target Events}.
3377 When the initial low JTAG speed is a chip characteristic, perhaps
3378 because of a required oscillator speed, provide such a handler
3379 in the target config file.
3380 When that speed is a function of a board-specific characteristic
3381 such as which speed oscillator is used, it belongs in the board
3382 config file instead.
3383 In both cases it's safest to also set the initial JTAG clock rate
3384 to that same slow speed, so that OpenOCD never starts up using a
3385 clock speed that's faster than the scan chain can support.
3389 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3392 If your system supports adaptive clocking (RTCK), configuring
3393 JTAG to use that is probably the most robust approach.
3394 However, it introduces delays to synchronize clocks; so it
3395 may not be the fastest solution.
3397 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3398 instead of @command{adapter speed}, but only for (ARM) cores and boards
3399 which support adaptive clocking.
3401 @deffn {Command} adapter speed max_speed_kHz
3402 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3403 JTAG interfaces usually support a limited number of
3404 speeds. The speed actually used won't be faster
3405 than the speed specified.
3407 Chip data sheets generally include a top JTAG clock rate.
3408 The actual rate is often a function of a CPU core clock,
3409 and is normally less than that peak rate.
3410 For example, most ARM cores accept at most one sixth of the CPU clock.
3412 Speed 0 (khz) selects RTCK method.
3413 @xref{faqrtck,,FAQ RTCK}.
3414 If your system uses RTCK, you won't need to change the
3415 JTAG clocking after setup.
3416 Not all interfaces, boards, or targets support ``rtck''.
3417 If the interface device can not
3418 support it, an error is returned when you try to use RTCK.
3421 @defun jtag_rclk fallback_speed_kHz
3422 @cindex adaptive clocking
3424 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3425 If that fails (maybe the interface, board, or target doesn't
3426 support it), falls back to the specified frequency.
3428 # Fall back to 3mhz if RTCK is not supported
3433 @node Reset Configuration
3434 @chapter Reset Configuration
3435 @cindex Reset Configuration
3437 Every system configuration may require a different reset
3438 configuration. This can also be quite confusing.
3439 Resets also interact with @var{reset-init} event handlers,
3440 which do things like setting up clocks and DRAM, and
3441 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3442 They can also interact with JTAG routers.
3443 Please see the various board files for examples.
3446 To maintainers and integrators:
3447 Reset configuration touches several things at once.
3448 Normally the board configuration file
3449 should define it and assume that the JTAG adapter supports
3450 everything that's wired up to the board's JTAG connector.
3452 However, the target configuration file could also make note
3453 of something the silicon vendor has done inside the chip,
3454 which will be true for most (or all) boards using that chip.
3455 And when the JTAG adapter doesn't support everything, the
3456 user configuration file will need to override parts of
3457 the reset configuration provided by other files.
3460 @section Types of Reset
3462 There are many kinds of reset possible through JTAG, but
3463 they may not all work with a given board and adapter.
3464 That's part of why reset configuration can be error prone.
3468 @emph{System Reset} ... the @emph{SRST} hardware signal
3469 resets all chips connected to the JTAG adapter, such as processors,
3470 power management chips, and I/O controllers. Normally resets triggered
3471 with this signal behave exactly like pressing a RESET button.
3473 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3474 just the TAP controllers connected to the JTAG adapter.
3475 Such resets should not be visible to the rest of the system; resetting a
3476 device's TAP controller just puts that controller into a known state.
3478 @emph{Emulation Reset} ... many devices can be reset through JTAG
3479 commands. These resets are often distinguishable from system
3480 resets, either explicitly (a "reset reason" register says so)
3481 or implicitly (not all parts of the chip get reset).
3483 @emph{Other Resets} ... system-on-chip devices often support
3484 several other types of reset.
3485 You may need to arrange that a watchdog timer stops
3486 while debugging, preventing a watchdog reset.
3487 There may be individual module resets.
3490 In the best case, OpenOCD can hold SRST, then reset
3491 the TAPs via TRST and send commands through JTAG to halt the
3492 CPU at the reset vector before the 1st instruction is executed.
3493 Then when it finally releases the SRST signal, the system is
3494 halted under debugger control before any code has executed.
3495 This is the behavior required to support the @command{reset halt}
3496 and @command{reset init} commands; after @command{reset init} a
3497 board-specific script might do things like setting up DRAM.
3498 (@xref{resetcommand,,Reset Command}.)
3500 @anchor{srstandtrstissues}
3501 @section SRST and TRST Issues
3503 Because SRST and TRST are hardware signals, they can have a
3504 variety of system-specific constraints. Some of the most
3509 @item @emph{Signal not available} ... Some boards don't wire
3510 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3511 support such signals even if they are wired up.
3512 Use the @command{reset_config} @var{signals} options to say
3513 when either of those signals is not connected.
3514 When SRST is not available, your code might not be able to rely
3515 on controllers having been fully reset during code startup.
3516 Missing TRST is not a problem, since JTAG-level resets can
3517 be triggered using with TMS signaling.
3519 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3520 adapter will connect SRST to TRST, instead of keeping them separate.
3521 Use the @command{reset_config} @var{combination} options to say
3522 when those signals aren't properly independent.
3524 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3525 delay circuit, reset supervisor, or on-chip features can extend
3526 the effect of a JTAG adapter's reset for some time after the adapter
3527 stops issuing the reset. For example, there may be chip or board
3528 requirements that all reset pulses last for at least a
3529 certain amount of time; and reset buttons commonly have
3530 hardware debouncing.
3531 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3532 commands to say when extra delays are needed.
3534 @item @emph{Drive type} ... Reset lines often have a pullup
3535 resistor, letting the JTAG interface treat them as open-drain
3536 signals. But that's not a requirement, so the adapter may need
3537 to use push/pull output drivers.
3538 Also, with weak pullups it may be advisable to drive
3539 signals to both levels (push/pull) to minimize rise times.
3540 Use the @command{reset_config} @var{trst_type} and
3541 @var{srst_type} parameters to say how to drive reset signals.
3543 @item @emph{Special initialization} ... Targets sometimes need
3544 special JTAG initialization sequences to handle chip-specific
3545 issues (not limited to errata).
3546 For example, certain JTAG commands might need to be issued while
3547 the system as a whole is in a reset state (SRST active)
3548 but the JTAG scan chain is usable (TRST inactive).
3549 Many systems treat combined assertion of SRST and TRST as a
3550 trigger for a harder reset than SRST alone.
3551 Such custom reset handling is discussed later in this chapter.
3554 There can also be other issues.
3555 Some devices don't fully conform to the JTAG specifications.
3556 Trivial system-specific differences are common, such as
3557 SRST and TRST using slightly different names.
3558 There are also vendors who distribute key JTAG documentation for
3559 their chips only to developers who have signed a Non-Disclosure
3562 Sometimes there are chip-specific extensions like a requirement to use
3563 the normally-optional TRST signal (precluding use of JTAG adapters which
3564 don't pass TRST through), or needing extra steps to complete a TAP reset.
3566 In short, SRST and especially TRST handling may be very finicky,
3567 needing to cope with both architecture and board specific constraints.
3569 @section Commands for Handling Resets
3571 @deffn {Command} adapter srst pulse_width milliseconds
3572 Minimum amount of time (in milliseconds) OpenOCD should wait
3573 after asserting nSRST (active-low system reset) before
3574 allowing it to be deasserted.
3577 @deffn {Command} adapter srst delay milliseconds
3578 How long (in milliseconds) OpenOCD should wait after deasserting
3579 nSRST (active-low system reset) before starting new JTAG operations.
3580 When a board has a reset button connected to SRST line it will
3581 probably have hardware debouncing, implying you should use this.
3584 @deffn {Command} jtag_ntrst_assert_width milliseconds
3585 Minimum amount of time (in milliseconds) OpenOCD should wait
3586 after asserting nTRST (active-low JTAG TAP reset) before
3587 allowing it to be deasserted.
3590 @deffn {Command} jtag_ntrst_delay milliseconds
3591 How long (in milliseconds) OpenOCD should wait after deasserting
3592 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3595 @anchor{reset_config}
3596 @deffn {Command} reset_config mode_flag ...
3597 This command displays or modifies the reset configuration
3598 of your combination of JTAG board and target in target
3599 configuration scripts.
3601 Information earlier in this section describes the kind of problems
3602 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3603 As a rule this command belongs only in board config files,
3604 describing issues like @emph{board doesn't connect TRST};
3605 or in user config files, addressing limitations derived
3606 from a particular combination of interface and board.
3607 (An unlikely example would be using a TRST-only adapter
3608 with a board that only wires up SRST.)
3610 The @var{mode_flag} options can be specified in any order, but only one
3611 of each type -- @var{signals}, @var{combination}, @var{gates},
3612 @var{trst_type}, @var{srst_type} and @var{connect_type}
3613 -- may be specified at a time.
3614 If you don't provide a new value for a given type, its previous
3615 value (perhaps the default) is unchanged.
3616 For example, this means that you don't need to say anything at all about
3617 TRST just to declare that if the JTAG adapter should want to drive SRST,
3618 it must explicitly be driven high (@option{srst_push_pull}).
3622 @var{signals} can specify which of the reset signals are connected.
3623 For example, If the JTAG interface provides SRST, but the board doesn't
3624 connect that signal properly, then OpenOCD can't use it.
3625 Possible values are @option{none} (the default), @option{trst_only},
3626 @option{srst_only} and @option{trst_and_srst}.
3629 If your board provides SRST and/or TRST through the JTAG connector,
3630 you must declare that so those signals can be used.
3634 The @var{combination} is an optional value specifying broken reset
3635 signal implementations.
3636 The default behaviour if no option given is @option{separate},
3637 indicating everything behaves normally.
3638 @option{srst_pulls_trst} states that the
3639 test logic is reset together with the reset of the system (e.g. NXP
3640 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3641 the system is reset together with the test logic (only hypothetical, I
3642 haven't seen hardware with such a bug, and can be worked around).
3643 @option{combined} implies both @option{srst_pulls_trst} and
3644 @option{trst_pulls_srst}.
3647 The @var{gates} tokens control flags that describe some cases where
3648 JTAG may be unavailable during reset.
3649 @option{srst_gates_jtag} (default)
3650 indicates that asserting SRST gates the
3651 JTAG clock. This means that no communication can happen on JTAG
3652 while SRST is asserted.
3653 Its converse is @option{srst_nogate}, indicating that JTAG commands
3654 can safely be issued while SRST is active.
3657 The @var{connect_type} tokens control flags that describe some cases where
3658 SRST is asserted while connecting to the target. @option{srst_nogate}
3659 is required to use this option.
3660 @option{connect_deassert_srst} (default)
3661 indicates that SRST will not be asserted while connecting to the target.
3662 Its converse is @option{connect_assert_srst}, indicating that SRST will
3663 be asserted before any target connection.
3664 Only some targets support this feature, STM32 and STR9 are examples.
3665 This feature is useful if you are unable to connect to your target due
3666 to incorrect options byte config or illegal program execution.
3669 The optional @var{trst_type} and @var{srst_type} parameters allow the
3670 driver mode of each reset line to be specified. These values only affect
3671 JTAG interfaces with support for different driver modes, like the Amontec
3672 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3673 relevant signal (TRST or SRST) is not connected.
3677 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3678 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3679 Most boards connect this signal to a pulldown, so the JTAG TAPs
3680 never leave reset unless they are hooked up to a JTAG adapter.
3683 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3684 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3685 Most boards connect this signal to a pullup, and allow the
3686 signal to be pulled low by various events including system
3687 power-up and pressing a reset button.
3691 @section Custom Reset Handling
3694 OpenOCD has several ways to help support the various reset
3695 mechanisms provided by chip and board vendors.
3696 The commands shown in the previous section give standard parameters.
3697 There are also @emph{event handlers} associated with TAPs or Targets.
3698 Those handlers are Tcl procedures you can provide, which are invoked
3699 at particular points in the reset sequence.
3701 @emph{When SRST is not an option} you must set
3702 up a @code{reset-assert} event handler for your target.
3703 For example, some JTAG adapters don't include the SRST signal;
3704 and some boards have multiple targets, and you won't always
3705 want to reset everything at once.
3707 After configuring those mechanisms, you might still
3708 find your board doesn't start up or reset correctly.
3709 For example, maybe it needs a slightly different sequence
3710 of SRST and/or TRST manipulations, because of quirks that
3711 the @command{reset_config} mechanism doesn't address;
3712 or asserting both might trigger a stronger reset, which
3713 needs special attention.
3715 Experiment with lower level operations, such as
3716 @command{adapter assert}, @command{adapter deassert}
3717 and the @command{jtag arp_*} operations shown here,
3718 to find a sequence of operations that works.
3719 @xref{JTAG Commands}.
3720 When you find a working sequence, it can be used to override
3721 @command{jtag_init}, which fires during OpenOCD startup
3722 (@pxref{configurationstage,,Configuration Stage});
3723 or @command{init_reset}, which fires during reset processing.
3725 You might also want to provide some project-specific reset
3726 schemes. For example, on a multi-target board the standard
3727 @command{reset} command would reset all targets, but you
3728 may need the ability to reset only one target at time and
3729 thus want to avoid using the board-wide SRST signal.
3731 @deffn {Overridable Procedure} init_reset mode
3732 This is invoked near the beginning of the @command{reset} command,
3733 usually to provide as much of a cold (power-up) reset as practical.
3734 By default it is also invoked from @command{jtag_init} if
3735 the scan chain does not respond to pure JTAG operations.
3736 The @var{mode} parameter is the parameter given to the
3737 low level reset command (@option{halt},
3738 @option{init}, or @option{run}), @option{setup},
3739 or potentially some other value.
3741 The default implementation just invokes @command{jtag arp_init-reset}.
3742 Replacements will normally build on low level JTAG
3743 operations such as @command{adapter assert} and @command{adapter deassert}.
3744 Operations here must not address individual TAPs
3745 (or their associated targets)
3746 until the JTAG scan chain has first been verified to work.
3748 Implementations must have verified the JTAG scan chain before
3750 This is done by calling @command{jtag arp_init}
3751 (or @command{jtag arp_init-reset}).
3754 @deffn Command {jtag arp_init}
3755 This validates the scan chain using just the four
3756 standard JTAG signals (TMS, TCK, TDI, TDO).
3757 It starts by issuing a JTAG-only reset.
3758 Then it performs checks to verify that the scan chain configuration
3759 matches the TAPs it can observe.
3760 Those checks include checking IDCODE values for each active TAP,
3761 and verifying the length of their instruction registers using
3762 TAP @code{-ircapture} and @code{-irmask} values.
3763 If these tests all pass, TAP @code{setup} events are
3764 issued to all TAPs with handlers for that event.
3767 @deffn Command {jtag arp_init-reset}
3768 This uses TRST and SRST to try resetting
3769 everything on the JTAG scan chain
3770 (and anything else connected to SRST).
3771 It then invokes the logic of @command{jtag arp_init}.
3775 @node TAP Declaration
3776 @chapter TAP Declaration
3777 @cindex TAP declaration
3778 @cindex TAP configuration
3780 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3781 TAPs serve many roles, including:
3784 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3785 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3786 Others do it indirectly, making a CPU do it.
3787 @item @b{Program Download} Using the same CPU support GDB uses,
3788 you can initialize a DRAM controller, download code to DRAM, and then
3789 start running that code.
3790 @item @b{Boundary Scan} Most chips support boundary scan, which
3791 helps test for board assembly problems like solder bridges
3792 and missing connections.
3795 OpenOCD must know about the active TAPs on your board(s).
3796 Setting up the TAPs is the core task of your configuration files.
3797 Once those TAPs are set up, you can pass their names to code
3798 which sets up CPUs and exports them as GDB targets,
3799 probes flash memory, performs low-level JTAG operations, and more.
3801 @section Scan Chains
3804 TAPs are part of a hardware @dfn{scan chain},
3805 which is a daisy chain of TAPs.
3806 They also need to be added to
3807 OpenOCD's software mirror of that hardware list,
3808 giving each member a name and associating other data with it.
3809 Simple scan chains, with a single TAP, are common in
3810 systems with a single microcontroller or microprocessor.
3811 More complex chips may have several TAPs internally.
3812 Very complex scan chains might have a dozen or more TAPs:
3813 several in one chip, more in the next, and connecting
3814 to other boards with their own chips and TAPs.
3816 You can display the list with the @command{scan_chain} command.
3817 (Don't confuse this with the list displayed by the @command{targets}
3818 command, presented in the next chapter.
3819 That only displays TAPs for CPUs which are configured as
3821 Here's what the scan chain might look like for a chip more than one TAP:
3824 TapName Enabled IdCode Expected IrLen IrCap IrMask
3825 -- ------------------ ------- ---------- ---------- ----- ----- ------
3826 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3827 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3828 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3831 OpenOCD can detect some of that information, but not all
3832 of it. @xref{autoprobing,,Autoprobing}.
3833 Unfortunately, those TAPs can't always be autoconfigured,
3834 because not all devices provide good support for that.
3835 JTAG doesn't require supporting IDCODE instructions, and
3836 chips with JTAG routers may not link TAPs into the chain
3837 until they are told to do so.
3839 The configuration mechanism currently supported by OpenOCD
3840 requires explicit configuration of all TAP devices using
3841 @command{jtag newtap} commands, as detailed later in this chapter.
3842 A command like this would declare one tap and name it @code{chip1.cpu}:
3845 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3848 Each target configuration file lists the TAPs provided
3850 Board configuration files combine all the targets on a board,
3852 Note that @emph{the order in which TAPs are declared is very important.}
3853 That declaration order must match the order in the JTAG scan chain,
3854 both inside a single chip and between them.
3855 @xref{faqtaporder,,FAQ TAP Order}.
3857 For example, the STMicroelectronics STR912 chip has
3858 three separate TAPs@footnote{See the ST
3859 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3860 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3861 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3862 To configure those taps, @file{target/str912.cfg}
3863 includes commands something like this:
3866 jtag newtap str912 flash ... params ...
3867 jtag newtap str912 cpu ... params ...
3868 jtag newtap str912 bs ... params ...
3871 Actual config files typically use a variable such as @code{$_CHIPNAME}
3872 instead of literals like @option{str912}, to support more than one chip
3873 of each type. @xref{Config File Guidelines}.
3875 @deffn Command {jtag names}
3876 Returns the names of all current TAPs in the scan chain.
3877 Use @command{jtag cget} or @command{jtag tapisenabled}
3878 to examine attributes and state of each TAP.
3880 foreach t [jtag names] @{
3881 puts [format "TAP: %s\n" $t]
3886 @deffn Command {scan_chain}
3887 Displays the TAPs in the scan chain configuration,
3889 The set of TAPs listed by this command is fixed by
3890 exiting the OpenOCD configuration stage,
3891 but systems with a JTAG router can
3892 enable or disable TAPs dynamically.
3895 @c FIXME! "jtag cget" should be able to return all TAP
3896 @c attributes, like "$target_name cget" does for targets.
3898 @c Probably want "jtag eventlist", and a "tap-reset" event
3899 @c (on entry to RESET state).
3904 When TAP objects are declared with @command{jtag newtap},
3905 a @dfn{dotted.name} is created for the TAP, combining the
3906 name of a module (usually a chip) and a label for the TAP.
3907 For example: @code{xilinx.tap}, @code{str912.flash},
3908 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3909 Many other commands use that dotted.name to manipulate or
3910 refer to the TAP. For example, CPU configuration uses the
3911 name, as does declaration of NAND or NOR flash banks.
3913 The components of a dotted name should follow ``C'' symbol
3914 name rules: start with an alphabetic character, then numbers
3915 and underscores are OK; while others (including dots!) are not.
3917 @section TAP Declaration Commands
3919 @c shouldn't this be(come) a {Config Command}?
3920 @deffn Command {jtag newtap} chipname tapname configparams...
3921 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3922 and configured according to the various @var{configparams}.
3924 The @var{chipname} is a symbolic name for the chip.
3925 Conventionally target config files use @code{$_CHIPNAME},
3926 defaulting to the model name given by the chip vendor but
3929 @cindex TAP naming convention
3930 The @var{tapname} reflects the role of that TAP,
3931 and should follow this convention:
3934 @item @code{bs} -- For boundary scan if this is a separate TAP;
3935 @item @code{cpu} -- The main CPU of the chip, alternatively
3936 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3937 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3938 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3939 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3940 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3941 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3942 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3944 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3945 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3946 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3947 a JTAG TAP; that TAP should be named @code{sdma}.
3950 Every TAP requires at least the following @var{configparams}:
3953 @item @code{-irlen} @var{NUMBER}
3954 @*The length in bits of the
3955 instruction register, such as 4 or 5 bits.
3958 A TAP may also provide optional @var{configparams}:
3961 @item @code{-disable} (or @code{-enable})
3962 @*Use the @code{-disable} parameter to flag a TAP which is not
3963 linked into the scan chain after a reset using either TRST
3964 or the JTAG state machine's @sc{reset} state.
3965 You may use @code{-enable} to highlight the default state
3966 (the TAP is linked in).
3967 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3968 @item @code{-expected-id} @var{NUMBER}
3969 @*A non-zero @var{number} represents a 32-bit IDCODE
3970 which you expect to find when the scan chain is examined.
3971 These codes are not required by all JTAG devices.
3972 @emph{Repeat the option} as many times as required if more than one
3973 ID code could appear (for example, multiple versions).
3974 Specify @var{number} as zero to suppress warnings about IDCODE
3975 values that were found but not included in the list.
3977 Provide this value if at all possible, since it lets OpenOCD
3978 tell when the scan chain it sees isn't right. These values
3979 are provided in vendors' chip documentation, usually a technical
3980 reference manual. Sometimes you may need to probe the JTAG
3981 hardware to find these values.
3982 @xref{autoprobing,,Autoprobing}.
3983 @item @code{-ignore-version}
3984 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3985 option. When vendors put out multiple versions of a chip, or use the same
3986 JTAG-level ID for several largely-compatible chips, it may be more practical
3987 to ignore the version field than to update config files to handle all of
3988 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3989 @item @code{-ircapture} @var{NUMBER}
3990 @*The bit pattern loaded by the TAP into the JTAG shift register
3991 on entry to the @sc{ircapture} state, such as 0x01.
3992 JTAG requires the two LSBs of this value to be 01.
3993 By default, @code{-ircapture} and @code{-irmask} are set
3994 up to verify that two-bit value. You may provide
3995 additional bits if you know them, or indicate that
3996 a TAP doesn't conform to the JTAG specification.
3997 @item @code{-irmask} @var{NUMBER}
3998 @*A mask used with @code{-ircapture}
3999 to verify that instruction scans work correctly.
4000 Such scans are not used by OpenOCD except to verify that
4001 there seems to be no problems with JTAG scan chain operations.
4002 @item @code{-ignore-syspwrupack}
4003 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4004 register during initial examination and when checking the sticky error bit.
4005 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4006 devices do not set the ack bit until sometime later.
4010 @section Other TAP commands
4012 @deffn Command {jtag cget} dotted.name @option{-idcode}
4013 Get the value of the IDCODE found in hardware.
4016 @deffn Command {jtag cget} dotted.name @option{-event} event_name
4017 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
4018 At this writing this TAP attribute
4019 mechanism is limited and used mostly for event handling.
4020 (It is not a direct analogue of the @code{cget}/@code{configure}
4021 mechanism for debugger targets.)
4022 See the next section for information about the available events.
4024 The @code{configure} subcommand assigns an event handler,
4025 a TCL string which is evaluated when the event is triggered.
4026 The @code{cget} subcommand returns that handler.
4033 OpenOCD includes two event mechanisms.
4034 The one presented here applies to all JTAG TAPs.
4035 The other applies to debugger targets,
4036 which are associated with certain TAPs.
4038 The TAP events currently defined are:
4041 @item @b{post-reset}
4042 @* The TAP has just completed a JTAG reset.
4043 The tap may still be in the JTAG @sc{reset} state.
4044 Handlers for these events might perform initialization sequences
4045 such as issuing TCK cycles, TMS sequences to ensure
4046 exit from the ARM SWD mode, and more.
4048 Because the scan chain has not yet been verified, handlers for these events
4049 @emph{should not issue commands which scan the JTAG IR or DR registers}
4050 of any particular target.
4051 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4053 @* The scan chain has been reset and verified.
4054 This handler may enable TAPs as needed.
4055 @item @b{tap-disable}
4056 @* The TAP needs to be disabled. This handler should
4057 implement @command{jtag tapdisable}
4058 by issuing the relevant JTAG commands.
4059 @item @b{tap-enable}
4060 @* The TAP needs to be enabled. This handler should
4061 implement @command{jtag tapenable}
4062 by issuing the relevant JTAG commands.
4065 If you need some action after each JTAG reset which isn't actually
4066 specific to any TAP (since you can't yet trust the scan chain's
4067 contents to be accurate), you might:
4070 jtag configure CHIP.jrc -event post-reset @{
4071 echo "JTAG Reset done"
4072 ... non-scan jtag operations to be done after reset
4077 @anchor{enablinganddisablingtaps}
4078 @section Enabling and Disabling TAPs
4079 @cindex JTAG Route Controller
4082 In some systems, a @dfn{JTAG Route Controller} (JRC)
4083 is used to enable and/or disable specific JTAG TAPs.
4084 Many ARM-based chips from Texas Instruments include
4085 an ``ICEPick'' module, which is a JRC.
4086 Such chips include DaVinci and OMAP3 processors.
4088 A given TAP may not be visible until the JRC has been
4089 told to link it into the scan chain; and if the JRC
4090 has been told to unlink that TAP, it will no longer
4092 Such routers address problems that JTAG ``bypass mode''
4096 @item The scan chain can only go as fast as its slowest TAP.
4097 @item Having many TAPs slows instruction scans, since all
4098 TAPs receive new instructions.
4099 @item TAPs in the scan chain must be powered up, which wastes
4100 power and prevents debugging some power management mechanisms.
4103 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4104 as implied by the existence of JTAG routers.
4105 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4106 does include a kind of JTAG router functionality.
4108 @c (a) currently the event handlers don't seem to be able to
4109 @c fail in a way that could lead to no-change-of-state.
4111 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4112 shown below, and is implemented using TAP event handlers.
4113 So for example, when defining a TAP for a CPU connected to
4114 a JTAG router, your @file{target.cfg} file
4115 should define TAP event handlers using
4116 code that looks something like this:
4119 jtag configure CHIP.cpu -event tap-enable @{
4120 ... jtag operations using CHIP.jrc
4122 jtag configure CHIP.cpu -event tap-disable @{
4123 ... jtag operations using CHIP.jrc
4127 Then you might want that CPU's TAP enabled almost all the time:
4130 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4133 Note how that particular setup event handler declaration
4134 uses quotes to evaluate @code{$CHIP} when the event is configured.
4135 Using brackets @{ @} would cause it to be evaluated later,
4136 at runtime, when it might have a different value.
4138 @deffn Command {jtag tapdisable} dotted.name
4139 If necessary, disables the tap
4140 by sending it a @option{tap-disable} event.
4141 Returns the string "1" if the tap
4142 specified by @var{dotted.name} is enabled,
4143 and "0" if it is disabled.
4146 @deffn Command {jtag tapenable} dotted.name
4147 If necessary, enables the tap
4148 by sending it a @option{tap-enable} event.
4149 Returns the string "1" if the tap
4150 specified by @var{dotted.name} is enabled,
4151 and "0" if it is disabled.
4154 @deffn Command {jtag tapisenabled} dotted.name
4155 Returns the string "1" if the tap
4156 specified by @var{dotted.name} is enabled,
4157 and "0" if it is disabled.
4160 Humans will find the @command{scan_chain} command more helpful
4161 for querying the state of the JTAG taps.
4165 @anchor{autoprobing}
4166 @section Autoprobing
4168 @cindex JTAG autoprobe
4170 TAP configuration is the first thing that needs to be done
4171 after interface and reset configuration. Sometimes it's
4172 hard finding out what TAPs exist, or how they are identified.
4173 Vendor documentation is not always easy to find and use.
4175 To help you get past such problems, OpenOCD has a limited
4176 @emph{autoprobing} ability to look at the scan chain, doing
4177 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4178 To use this mechanism, start the OpenOCD server with only data
4179 that configures your JTAG interface, and arranges to come up
4180 with a slow clock (many devices don't support fast JTAG clocks
4181 right when they come out of reset).
4183 For example, your @file{openocd.cfg} file might have:
4186 source [find interface/olimex-arm-usb-tiny-h.cfg]
4187 reset_config trst_and_srst
4191 When you start the server without any TAPs configured, it will
4192 attempt to autoconfigure the TAPs. There are two parts to this:
4195 @item @emph{TAP discovery} ...
4196 After a JTAG reset (sometimes a system reset may be needed too),
4197 each TAP's data registers will hold the contents of either the
4198 IDCODE or BYPASS register.
4199 If JTAG communication is working, OpenOCD will see each TAP,
4200 and report what @option{-expected-id} to use with it.
4201 @item @emph{IR Length discovery} ...
4202 Unfortunately JTAG does not provide a reliable way to find out
4203 the value of the @option{-irlen} parameter to use with a TAP
4205 If OpenOCD can discover the length of a TAP's instruction
4206 register, it will report it.
4207 Otherwise you may need to consult vendor documentation, such
4208 as chip data sheets or BSDL files.
4211 In many cases your board will have a simple scan chain with just
4212 a single device. Here's what OpenOCD reported with one board
4213 that's a bit more complex:
4217 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4218 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4219 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4220 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4221 AUTO auto0.tap - use "... -irlen 4"
4222 AUTO auto1.tap - use "... -irlen 4"
4223 AUTO auto2.tap - use "... -irlen 6"
4224 no gdb ports allocated as no target has been specified
4227 Given that information, you should be able to either find some existing
4228 config files to use, or create your own. If you create your own, you
4229 would configure from the bottom up: first a @file{target.cfg} file
4230 with these TAPs, any targets associated with them, and any on-chip
4231 resources; then a @file{board.cfg} with off-chip resources, clocking,
4234 @anchor{dapdeclaration}
4235 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4236 @cindex DAP declaration
4238 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4239 no longer implicitly created together with the target. It must be
4240 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4241 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4242 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4244 The @command{dap} command group supports the following sub-commands:
4246 @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
4247 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4248 @var{dotted.name}. This also creates a new command (@command{dap_name})
4249 which is used for various purposes including additional configuration.
4250 There can only be one DAP for each JTAG tap in the system.
4252 A DAP may also provide optional @var{configparams}:
4255 @item @code{-ignore-syspwrupack}
4256 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4257 register during initial examination and when checking the sticky error bit.
4258 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4259 devices do not set the ack bit until sometime later.
4263 @deffn Command {dap names}
4264 This command returns a list of all registered DAP objects. It it useful mainly
4268 @deffn Command {dap info} [num]
4269 Displays the ROM table for MEM-AP @var{num},
4270 defaulting to the currently selected AP of the currently selected target.
4273 @deffn Command {dap init}
4274 Initialize all registered DAPs. This command is used internally
4275 during initialization. It can be issued at any time after the
4276 initialization, too.
4279 The following commands exist as subcommands of DAP instances:
4281 @deffn Command {$dap_name info} [num]
4282 Displays the ROM table for MEM-AP @var{num},
4283 defaulting to the currently selected AP.
4286 @deffn Command {$dap_name apid} [num]
4287 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4290 @anchor{DAP subcommand apreg}
4291 @deffn Command {$dap_name apreg} ap_num reg [value]
4292 Displays content of a register @var{reg} from AP @var{ap_num}
4293 or set a new value @var{value}.
4294 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4297 @deffn Command {$dap_name apsel} [num]
4298 Select AP @var{num}, defaulting to 0.
4301 @deffn Command {$dap_name dpreg} reg [value]
4302 Displays the content of DP register at address @var{reg}, or set it to a new
4305 In case of SWD, @var{reg} is a value in packed format
4306 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4307 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4309 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4310 background activity by OpenOCD while you are operating at such low-level.
4313 @deffn Command {$dap_name baseaddr} [num]
4314 Displays debug base address from MEM-AP @var{num},
4315 defaulting to the currently selected AP.
4318 @deffn Command {$dap_name memaccess} [value]
4319 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4320 memory bus access [0-255], giving additional time to respond to reads.
4321 If @var{value} is defined, first assigns that.
4324 @deffn Command {$dap_name apcsw} [value [mask]]
4325 Displays or changes CSW bit pattern for MEM-AP transfers.
4327 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4328 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4329 and the result is written to the real CSW register. All bits except dynamically
4330 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4331 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4334 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4335 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4338 kx.dap apcsw 0x2000000
4341 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4342 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4343 and leaves the rest of the pattern intact. It configures memory access through
4344 DCache on Cortex-M7.
4346 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4347 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4350 Another example clears SPROT bit and leaves the rest of pattern intact:
4352 set CSW_SPROT [expr 1 << 30]
4353 samv.dap apcsw 0 $CSW_SPROT
4356 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4357 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4359 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4360 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4361 example with a proper dap name:
4363 xxx.dap apcsw default
4367 @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
4368 Set/get quirks mode for TI TMS450/TMS570 processors
4373 @node CPU Configuration
4374 @chapter CPU Configuration
4377 This chapter discusses how to set up GDB debug targets for CPUs.
4378 You can also access these targets without GDB
4379 (@pxref{Architecture and Core Commands},
4380 and @ref{targetstatehandling,,Target State handling}) and
4381 through various kinds of NAND and NOR flash commands.
4382 If you have multiple CPUs you can have multiple such targets.
4384 We'll start by looking at how to examine the targets you have,
4385 then look at how to add one more target and how to configure it.
4387 @section Target List
4388 @cindex target, current
4389 @cindex target, list
4391 All targets that have been set up are part of a list,
4392 where each member has a name.
4393 That name should normally be the same as the TAP name.
4394 You can display the list with the @command{targets}
4396 This display often has only one CPU; here's what it might
4397 look like with more than one:
4399 TargetName Type Endian TapName State
4400 -- ------------------ ---------- ------ ------------------ ------------
4401 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4402 1 MyTarget cortex_m little mychip.foo tap-disabled
4405 One member of that list is the @dfn{current target}, which
4406 is implicitly referenced by many commands.
4407 It's the one marked with a @code{*} near the target name.
4408 In particular, memory addresses often refer to the address
4409 space seen by that current target.
4410 Commands like @command{mdw} (memory display words)
4411 and @command{flash erase_address} (erase NOR flash blocks)
4412 are examples; and there are many more.
4414 Several commands let you examine the list of targets:
4416 @deffn Command {target current}
4417 Returns the name of the current target.
4420 @deffn Command {target names}
4421 Lists the names of all current targets in the list.
4423 foreach t [target names] @{
4424 puts [format "Target: %s\n" $t]
4429 @c yep, "target list" would have been better.
4430 @c plus maybe "target setdefault".
4432 @deffn Command targets [name]
4433 @emph{Note: the name of this command is plural. Other target
4434 command names are singular.}
4436 With no parameter, this command displays a table of all known
4437 targets in a user friendly form.
4439 With a parameter, this command sets the current target to
4440 the given target with the given @var{name}; this is
4441 only relevant on boards which have more than one target.
4444 @section Target CPU Types
4448 Each target has a @dfn{CPU type}, as shown in the output of
4449 the @command{targets} command. You need to specify that type
4450 when calling @command{target create}.
4451 The CPU type indicates more than just the instruction set.
4452 It also indicates how that instruction set is implemented,
4453 what kind of debug support it integrates,
4454 whether it has an MMU (and if so, what kind),
4455 what core-specific commands may be available
4456 (@pxref{Architecture and Core Commands}),
4459 It's easy to see what target types are supported,
4460 since there's a command to list them.
4462 @anchor{targettypes}
4463 @deffn Command {target types}
4464 Lists all supported target types.
4465 At this writing, the supported CPU types are:
4468 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4469 @item @code{arm11} -- this is a generation of ARMv6 cores.
4470 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4471 @item @code{arm7tdmi} -- this is an ARMv4 core.
4472 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4473 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4474 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4475 @item @code{arm966e} -- this is an ARMv5 core.
4476 @item @code{arm9tdmi} -- this is an ARMv4 core.
4477 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4478 (Support for this is preliminary and incomplete.)
4479 @item @code{avr32_ap7k} -- this an AVR32 core.
4480 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4481 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4482 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4483 @item @code{cortex_r4} -- this is an ARMv7-R core.
4484 @item @code{dragonite} -- resembles arm966e.
4485 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4486 (Support for this is still incomplete.)
4487 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4488 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4489 The current implementation supports eSi-32xx cores.
4490 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4491 @item @code{feroceon} -- resembles arm926.
4492 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4493 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4494 allowing access to physical memory addresses independently of CPU cores.
4495 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs.
4496 @item @code{mips_m4k} -- a MIPS core.
4497 @item @code{mips_mips64} -- a MIPS64 core.
4498 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core.
4499 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core.
4500 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core.
4501 @item @code{or1k} -- this is an OpenRISC 1000 core.
4502 The current implementation supports three JTAG TAP cores:
4504 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4505 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4506 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4508 And two debug interfaces cores:
4510 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4511 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project@comma{}dbg_interface})
4513 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4514 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4515 @item @code{riscv} -- a RISC-V core.
4516 @item @code{stm8} -- implements an STM8 core.
4517 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4518 @item @code{xscale} -- this is actually an architecture,
4519 not a CPU type. It is based on the ARMv5 architecture.
4523 To avoid being confused by the variety of ARM based cores, remember
4524 this key point: @emph{ARM is a technology licencing company}.
4525 (See: @url{http://www.arm.com}.)
4526 The CPU name used by OpenOCD will reflect the CPU design that was
4527 licensed, not a vendor brand which incorporates that design.
4528 Name prefixes like arm7, arm9, arm11, and cortex
4529 reflect design generations;
4530 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4531 reflect an architecture version implemented by a CPU design.
4533 @anchor{targetconfiguration}
4534 @section Target Configuration
4536 Before creating a ``target'', you must have added its TAP to the scan chain.
4537 When you've added that TAP, you will have a @code{dotted.name}
4538 which is used to set up the CPU support.
4539 The chip-specific configuration file will normally configure its CPU(s)
4540 right after it adds all of the chip's TAPs to the scan chain.
4542 Although you can set up a target in one step, it's often clearer if you
4543 use shorter commands and do it in two steps: create it, then configure
4545 All operations on the target after it's created will use a new
4546 command, created as part of target creation.
4548 The two main things to configure after target creation are
4549 a work area, which usually has target-specific defaults even
4550 if the board setup code overrides them later;
4551 and event handlers (@pxref{targetevents,,Target Events}), which tend
4552 to be much more board-specific.
4553 The key steps you use might look something like this
4556 dap create mychip.dap -chain-position mychip.cpu
4557 target create MyTarget cortex_m -dap mychip.dap
4558 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4559 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4560 MyTarget configure -event reset-init @{ myboard_reinit @}
4563 You should specify a working area if you can; typically it uses some
4565 Such a working area can speed up many things, including bulk
4566 writes to target memory;
4567 flash operations like checking to see if memory needs to be erased;
4568 GDB memory checksumming;
4572 On more complex chips, the work area can become
4573 inaccessible when application code
4574 (such as an operating system)
4575 enables or disables the MMU.
4576 For example, the particular MMU context used to access the virtual
4577 address will probably matter ... and that context might not have
4578 easy access to other addresses needed.
4579 At this writing, OpenOCD doesn't have much MMU intelligence.
4582 It's often very useful to define a @code{reset-init} event handler.
4583 For systems that are normally used with a boot loader,
4584 common tasks include updating clocks and initializing memory
4586 That may be needed to let you write the boot loader into flash,
4587 in order to ``de-brick'' your board; or to load programs into
4588 external DDR memory without having run the boot loader.
4590 @deffn Command {target create} target_name type configparams...
4591 This command creates a GDB debug target that refers to a specific JTAG tap.
4592 It enters that target into a list, and creates a new
4593 command (@command{@var{target_name}}) which is used for various
4594 purposes including additional configuration.
4597 @item @var{target_name} ... is the name of the debug target.
4598 By convention this should be the same as the @emph{dotted.name}
4599 of the TAP associated with this target, which must be specified here
4600 using the @code{-chain-position @var{dotted.name}} configparam.
4602 This name is also used to create the target object command,
4603 referred to here as @command{$target_name},
4604 and in other places the target needs to be identified.
4605 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4606 @item @var{configparams} ... all parameters accepted by
4607 @command{$target_name configure} are permitted.
4608 If the target is big-endian, set it here with @code{-endian big}.
4610 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4611 @code{-dap @var{dap_name}} here.
4615 @deffn Command {$target_name configure} configparams...
4616 The options accepted by this command may also be
4617 specified as parameters to @command{target create}.
4618 Their values can later be queried one at a time by
4619 using the @command{$target_name cget} command.
4621 @emph{Warning:} changing some of these after setup is dangerous.
4622 For example, moving a target from one TAP to another;
4623 and changing its endianness.
4627 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4628 used to access this target.
4630 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4631 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4632 create and manage DAP instances.
4634 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4635 whether the CPU uses big or little endian conventions
4637 @item @code{-event} @var{event_name} @var{event_body} --
4638 @xref{targetevents,,Target Events}.
4639 Note that this updates a list of named event handlers.
4640 Calling this twice with two different event names assigns
4641 two different handlers, but calling it twice with the
4642 same event name assigns only one handler.
4644 Current target is temporarily overridden to the event issuing target
4645 before handler code starts and switched back after handler is done.
4647 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4648 whether the work area gets backed up; by default,
4649 @emph{it is not backed up.}
4650 When possible, use a working_area that doesn't need to be backed up,
4651 since performing a backup slows down operations.
4652 For example, the beginning of an SRAM block is likely to
4653 be used by most build systems, but the end is often unused.
4655 @item @code{-work-area-size} @var{size} -- specify work are size,
4656 in bytes. The same size applies regardless of whether its physical
4657 or virtual address is being used.
4659 @item @code{-work-area-phys} @var{address} -- set the work area
4660 base @var{address} to be used when no MMU is active.
4662 @item @code{-work-area-virt} @var{address} -- set the work area
4663 base @var{address} to be used when an MMU is active.
4664 @emph{Do not specify a value for this except on targets with an MMU.}
4665 The value should normally correspond to a static mapping for the
4666 @code{-work-area-phys} address, set up by the current operating system.
4669 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4670 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4671 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4672 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
4674 @xref{gdbrtossupport,,RTOS Support}.
4676 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4677 scan and after a reset. A manual call to arp_examine is required to
4678 access the target for debugging.
4680 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4681 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4682 Use this option with systems where multiple, independent cores are connected
4683 to separate access ports of the same DAP.
4685 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4686 to the target. Currently, only the @code{aarch64} target makes use of this option,
4687 where it is a mandatory configuration for the target run control.
4688 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4689 for instruction on how to declare and control a CTI instance.
4691 @anchor{gdbportoverride}
4692 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4693 possible values of the parameter @var{number}, which are not only numeric values.
4694 Use this option to override, for this target only, the global parameter set with
4695 command @command{gdb_port}.
4696 @xref{gdb_port,,command gdb_port}.
4700 @section Other $target_name Commands
4701 @cindex object command
4703 The Tcl/Tk language has the concept of object commands,
4704 and OpenOCD adopts that same model for targets.
4706 A good Tk example is a on screen button.
4707 Once a button is created a button
4708 has a name (a path in Tk terms) and that name is useable as a first
4709 class command. For example in Tk, one can create a button and later
4710 configure it like this:
4714 button .foobar -background red -command @{ foo @}
4716 .foobar configure -foreground blue
4718 set x [.foobar cget -background]
4720 puts [format "The button is %s" $x]
4723 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4724 button, and its object commands are invoked the same way.
4727 str912.cpu mww 0x1234 0x42
4728 omap3530.cpu mww 0x5555 123
4731 The commands supported by OpenOCD target objects are:
4733 @deffn Command {$target_name arp_examine} @option{allow-defer}
4734 @deffnx Command {$target_name arp_halt}
4735 @deffnx Command {$target_name arp_poll}
4736 @deffnx Command {$target_name arp_reset}
4737 @deffnx Command {$target_name arp_waitstate}
4738 Internal OpenOCD scripts (most notably @file{startup.tcl})
4739 use these to deal with specific reset cases.
4740 They are not otherwise documented here.
4743 @deffn Command {$target_name array2mem} arrayname width address count
4744 @deffnx Command {$target_name mem2array} arrayname width address count
4745 These provide an efficient script-oriented interface to memory.
4746 The @code{array2mem} primitive writes bytes, halfwords, or words;
4747 while @code{mem2array} reads them.
4748 In both cases, the TCL side uses an array, and
4749 the target side uses raw memory.
4751 The efficiency comes from enabling the use of
4752 bulk JTAG data transfer operations.
4753 The script orientation comes from working with data
4754 values that are packaged for use by TCL scripts;
4755 @command{mdw} type primitives only print data they retrieve,
4756 and neither store nor return those values.
4759 @item @var{arrayname} ... is the name of an array variable
4760 @item @var{width} ... is 8/16/32 - indicating the memory access size
4761 @item @var{address} ... is the target memory address
4762 @item @var{count} ... is the number of elements to process
4766 @deffn Command {$target_name cget} queryparm
4767 Each configuration parameter accepted by
4768 @command{$target_name configure}
4769 can be individually queried, to return its current value.
4770 The @var{queryparm} is a parameter name
4771 accepted by that command, such as @code{-work-area-phys}.
4772 There are a few special cases:
4775 @item @code{-event} @var{event_name} -- returns the handler for the
4776 event named @var{event_name}.
4777 This is a special case because setting a handler requires
4779 @item @code{-type} -- returns the target type.
4780 This is a special case because this is set using
4781 @command{target create} and can't be changed
4782 using @command{$target_name configure}.
4785 For example, if you wanted to summarize information about
4786 all the targets you might use something like this:
4789 foreach name [target names] @{
4790 set y [$name cget -endian]
4791 set z [$name cget -type]
4792 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4798 @anchor{targetcurstate}
4799 @deffn Command {$target_name curstate}
4800 Displays the current target state:
4801 @code{debug-running},
4804 @code{running}, or @code{unknown}.
4805 (Also, @pxref{eventpolling,,Event Polling}.)
4808 @deffn Command {$target_name eventlist}
4809 Displays a table listing all event handlers
4810 currently associated with this target.
4811 @xref{targetevents,,Target Events}.
4814 @deffn Command {$target_name invoke-event} event_name
4815 Invokes the handler for the event named @var{event_name}.
4816 (This is primarily intended for use by OpenOCD framework
4817 code, for example by the reset code in @file{startup.tcl}.)
4820 @deffn Command {$target_name mdd} [phys] addr [count]
4821 @deffnx Command {$target_name mdw} [phys] addr [count]
4822 @deffnx Command {$target_name mdh} [phys] addr [count]
4823 @deffnx Command {$target_name mdb} [phys] addr [count]
4824 Display contents of address @var{addr}, as
4825 64-bit doublewords (@command{mdd}),
4826 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4827 or 8-bit bytes (@command{mdb}).
4828 When the current target has an MMU which is present and active,
4829 @var{addr} is interpreted as a virtual address.
4830 Otherwise, or if the optional @var{phys} flag is specified,
4831 @var{addr} is interpreted as a physical address.
4832 If @var{count} is specified, displays that many units.
4833 (If you want to manipulate the data instead of displaying it,
4834 see the @code{mem2array} primitives.)
4837 @deffn Command {$target_name mwd} [phys] addr doubleword [count]
4838 @deffnx Command {$target_name mww} [phys] addr word [count]
4839 @deffnx Command {$target_name mwh} [phys] addr halfword [count]
4840 @deffnx Command {$target_name mwb} [phys] addr byte [count]
4841 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
4842 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
4843 at the specified address @var{addr}.
4844 When the current target has an MMU which is present and active,
4845 @var{addr} is interpreted as a virtual address.
4846 Otherwise, or if the optional @var{phys} flag is specified,
4847 @var{addr} is interpreted as a physical address.
4848 If @var{count} is specified, fills that many units of consecutive address.
4851 @anchor{targetevents}
4852 @section Target Events
4853 @cindex target events
4855 At various times, certain things can happen, or you want them to happen.
4858 @item What should happen when GDB connects? Should your target reset?
4859 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4860 @item Is using SRST appropriate (and possible) on your system?
4861 Or instead of that, do you need to issue JTAG commands to trigger reset?
4862 SRST usually resets everything on the scan chain, which can be inappropriate.
4863 @item During reset, do you need to write to certain memory locations
4864 to set up system clocks or
4865 to reconfigure the SDRAM?
4866 How about configuring the watchdog timer, or other peripherals,
4867 to stop running while you hold the core stopped for debugging?
4870 All of the above items can be addressed by target event handlers.
4871 These are set up by @command{$target_name configure -event} or
4872 @command{target create ... -event}.
4874 The programmer's model matches the @code{-command} option used in Tcl/Tk
4875 buttons and events. The two examples below act the same, but one creates
4876 and invokes a small procedure while the other inlines it.
4879 proc my_init_proc @{ @} @{
4880 echo "Disabling watchdog..."
4881 mww 0xfffffd44 0x00008000
4883 mychip.cpu configure -event reset-init my_init_proc
4884 mychip.cpu configure -event reset-init @{
4885 echo "Disabling watchdog..."
4886 mww 0xfffffd44 0x00008000
4890 The following target events are defined:
4893 @item @b{debug-halted}
4894 @* The target has halted for debug reasons (i.e.: breakpoint)
4895 @item @b{debug-resumed}
4896 @* The target has resumed (i.e.: GDB said run)
4897 @item @b{early-halted}
4898 @* Occurs early in the halt process
4899 @item @b{examine-start}
4900 @* Before target examine is called.
4901 @item @b{examine-end}
4902 @* After target examine is called with no errors.
4903 @item @b{examine-fail}
4904 @* After target examine fails.
4905 @item @b{gdb-attach}
4906 @* When GDB connects. Issued before any GDB communication with the target
4907 starts. GDB expects the target is halted during attachment.
4908 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
4909 connect GDB to running target.
4910 The event can be also used to set up the target so it is possible to probe flash.
4911 Probing flash is necessary during GDB connect if you want to use
4912 @pxref{programmingusinggdb,,programming using GDB}.
4913 Another use of the flash memory map is for GDB to automatically choose
4914 hardware or software breakpoints depending on whether the breakpoint
4915 is in RAM or read only memory.
4916 Default is @code{halt}
4917 @item @b{gdb-detach}
4918 @* When GDB disconnects
4920 @* When the target has halted and GDB is not doing anything (see early halt)
4921 @item @b{gdb-flash-erase-start}
4922 @* Before the GDB flash process tries to erase the flash (default is
4924 @item @b{gdb-flash-erase-end}
4925 @* After the GDB flash process has finished erasing the flash
4926 @item @b{gdb-flash-write-start}
4927 @* Before GDB writes to the flash
4928 @item @b{gdb-flash-write-end}
4929 @* After GDB writes to the flash (default is @code{reset halt})
4931 @* Before the target steps, GDB is trying to start/resume the target
4933 @* The target has halted
4934 @item @b{reset-assert-pre}
4935 @* Issued as part of @command{reset} processing
4936 after @command{reset-start} was triggered
4937 but before either SRST alone is asserted on the scan chain,
4938 or @code{reset-assert} is triggered.
4939 @item @b{reset-assert}
4940 @* Issued as part of @command{reset} processing
4941 after @command{reset-assert-pre} was triggered.
4942 When such a handler is present, cores which support this event will use
4943 it instead of asserting SRST.
4944 This support is essential for debugging with JTAG interfaces which
4945 don't include an SRST line (JTAG doesn't require SRST), and for
4946 selective reset on scan chains that have multiple targets.
4947 @item @b{reset-assert-post}
4948 @* Issued as part of @command{reset} processing
4949 after @code{reset-assert} has been triggered.
4950 or the target asserted SRST on the entire scan chain.
4951 @item @b{reset-deassert-pre}
4952 @* Issued as part of @command{reset} processing
4953 after @code{reset-assert-post} has been triggered.
4954 @item @b{reset-deassert-post}
4955 @* Issued as part of @command{reset} processing
4956 after @code{reset-deassert-pre} has been triggered
4957 and (if the target is using it) after SRST has been
4958 released on the scan chain.
4960 @* Issued as the final step in @command{reset} processing.
4961 @item @b{reset-init}
4962 @* Used by @b{reset init} command for board-specific initialization.
4963 This event fires after @emph{reset-deassert-post}.
4965 This is where you would configure PLLs and clocking, set up DRAM so
4966 you can download programs that don't fit in on-chip SRAM, set up pin
4967 multiplexing, and so on.
4968 (You may be able to switch to a fast JTAG clock rate here, after
4969 the target clocks are fully set up.)
4970 @item @b{reset-start}
4971 @* Issued as the first step in @command{reset} processing
4972 before @command{reset-assert-pre} is called.
4974 This is the most robust place to use @command{jtag_rclk}
4975 or @command{adapter speed} to switch to a low JTAG clock rate,
4976 when reset disables PLLs needed to use a fast clock.
4977 @item @b{resume-start}
4978 @* Before any target is resumed
4979 @item @b{resume-end}
4980 @* After all targets have resumed
4982 @* Target has resumed
4983 @item @b{step-start}
4984 @* Before a target is single-stepped
4986 @* After single-step has completed
4987 @item @b{trace-config}
4988 @* After target hardware trace configuration was changed
4991 @node Flash Commands
4992 @chapter Flash Commands
4994 OpenOCD has different commands for NOR and NAND flash;
4995 the ``flash'' command works with NOR flash, while
4996 the ``nand'' command works with NAND flash.
4997 This partially reflects different hardware technologies:
4998 NOR flash usually supports direct CPU instruction and data bus access,
4999 while data from a NAND flash must be copied to memory before it can be
5000 used. (SPI flash must also be copied to memory before use.)
5001 However, the documentation also uses ``flash'' as a generic term;
5002 for example, ``Put flash configuration in board-specific files''.
5006 @item Configure via the command @command{flash bank}
5007 @* Do this in a board-specific configuration file,
5008 passing parameters as needed by the driver.
5009 @item Operate on the flash via @command{flash subcommand}
5010 @* Often commands to manipulate the flash are typed by a human, or run
5011 via a script in some automated way. Common tasks include writing a
5012 boot loader, operating system, or other data.
5014 @* Flashing via GDB requires the flash be configured via ``flash
5015 bank'', and the GDB flash features be enabled.
5016 @xref{gdbconfiguration,,GDB Configuration}.
5019 Many CPUs have the ability to ``boot'' from the first flash bank.
5020 This means that misprogramming that bank can ``brick'' a system,
5021 so that it can't boot.
5022 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5023 board by (re)installing working boot firmware.
5025 @anchor{norconfiguration}
5026 @section Flash Configuration Commands
5027 @cindex flash configuration
5029 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5030 Configures a flash bank which provides persistent storage
5031 for addresses from @math{base} to @math{base + size - 1}.
5032 These banks will often be visible to GDB through the target's memory map.
5033 In some cases, configuring a flash bank will activate extra commands;
5034 see the driver-specific documentation.
5037 @item @var{name} ... may be used to reference the flash bank
5038 in other flash commands. A number is also available.
5039 @item @var{driver} ... identifies the controller driver
5040 associated with the flash bank being declared.
5041 This is usually @code{cfi} for external flash, or else
5042 the name of a microcontroller with embedded flash memory.
5043 @xref{flashdriverlist,,Flash Driver List}.
5044 @item @var{base} ... Base address of the flash chip.
5045 @item @var{size} ... Size of the chip, in bytes.
5046 For some drivers, this value is detected from the hardware.
5047 @item @var{chip_width} ... Width of the flash chip, in bytes;
5048 ignored for most microcontroller drivers.
5049 @item @var{bus_width} ... Width of the data bus used to access the
5050 chip, in bytes; ignored for most microcontroller drivers.
5051 @item @var{target} ... Names the target used to issue
5052 commands to the flash controller.
5053 @comment Actually, it's currently a controller-specific parameter...
5054 @item @var{driver_options} ... drivers may support, or require,
5055 additional parameters. See the driver-specific documentation
5056 for more information.
5059 This command is not available after OpenOCD initialization has completed.
5060 Use it in board specific configuration files, not interactively.
5064 @comment less confusing would be: "flash list" (like "nand list")
5065 @deffn Command {flash banks}
5066 Prints a one-line summary of each device that was
5067 declared using @command{flash bank}, numbered from zero.
5068 Note that this is the @emph{plural} form;
5069 the @emph{singular} form is a very different command.
5072 @deffn Command {flash list}
5073 Retrieves a list of associative arrays for each device that was
5074 declared using @command{flash bank}, numbered from zero.
5075 This returned list can be manipulated easily from within scripts.
5078 @deffn Command {flash probe} num
5079 Identify the flash, or validate the parameters of the configured flash. Operation
5080 depends on the flash type.
5081 The @var{num} parameter is a value shown by @command{flash banks}.
5082 Most flash commands will implicitly @emph{autoprobe} the bank;
5083 flash drivers can distinguish between probing and autoprobing,
5084 but most don't bother.
5087 @section Preparing a Target before Flash Programming
5089 The target device should be in well defined state before the flash programming
5092 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5093 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5094 until the programming session is finished.
5096 If you use @ref{programmingusinggdb,,Programming using GDB},
5097 the target is prepared automatically in the event gdb-flash-erase-start
5099 The jimtcl script @command{program} calls @command{reset init} explicitly.
5101 @section Erasing, Reading, Writing to Flash
5102 @cindex flash erasing
5103 @cindex flash reading
5104 @cindex flash writing
5105 @cindex flash programming
5106 @anchor{flashprogrammingcommands}
5108 One feature distinguishing NOR flash from NAND or serial flash technologies
5109 is that for read access, it acts exactly like any other addressable memory.
5110 This means you can use normal memory read commands like @command{mdw} or
5111 @command{dump_image} with it, with no special @command{flash} subcommands.
5112 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5114 Write access works differently. Flash memory normally needs to be erased
5115 before it's written. Erasing a sector turns all of its bits to ones, and
5116 writing can turn ones into zeroes. This is why there are special commands
5117 for interactive erasing and writing, and why GDB needs to know which parts
5118 of the address space hold NOR flash memory.
5121 Most of these erase and write commands leverage the fact that NOR flash
5122 chips consume target address space. They implicitly refer to the current
5123 JTAG target, and map from an address in that target's address space
5124 back to a flash bank.
5125 @comment In May 2009, those mappings may fail if any bank associated
5126 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5127 A few commands use abstract addressing based on bank and sector numbers,
5128 and don't depend on searching the current target and its address space.
5129 Avoid confusing the two command models.
5132 Some flash chips implement software protection against accidental writes,
5133 since such buggy writes could in some cases ``brick'' a system.
5134 For such systems, erasing and writing may require sector protection to be
5136 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5137 and AT91SAM7 on-chip flash.
5138 @xref{flashprotect,,flash protect}.
5140 @deffn Command {flash erase_sector} num first last
5141 Erase sectors in bank @var{num}, starting at sector @var{first}
5142 up to and including @var{last}.
5143 Sector numbering starts at 0.
5144 Providing a @var{last} sector of @option{last}
5145 specifies "to the end of the flash bank".
5146 The @var{num} parameter is a value shown by @command{flash banks}.
5149 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
5150 Erase sectors starting at @var{address} for @var{length} bytes.
5151 Unless @option{pad} is specified, @math{address} must begin a
5152 flash sector, and @math{address + length - 1} must end a sector.
5153 Specifying @option{pad} erases extra data at the beginning and/or
5154 end of the specified region, as needed to erase only full sectors.
5155 The flash bank to use is inferred from the @var{address}, and
5156 the specified length must stay within that bank.
5157 As a special case, when @var{length} is zero and @var{address} is
5158 the start of the bank, the whole flash is erased.
5159 If @option{unlock} is specified, then the flash is unprotected
5160 before erase starts.
5163 @deffn Command {flash filld} address double-word length
5164 @deffnx Command {flash fillw} address word length
5165 @deffnx Command {flash fillh} address halfword length
5166 @deffnx Command {flash fillb} address byte length
5167 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5168 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5169 starting at @var{address} and continuing
5170 for @var{length} units (word/halfword/byte).
5171 No erasure is done before writing; when needed, that must be done
5172 before issuing this command.
5173 Writes are done in blocks of up to 1024 bytes, and each write is
5174 verified by reading back the data and comparing it to what was written.
5175 The flash bank to use is inferred from the @var{address} of
5176 each block, and the specified length must stay within that bank.
5178 @comment no current checks for errors if fill blocks touch multiple banks!
5180 @deffn Command {flash mdw} addr [count]
5181 @deffnx Command {flash mdh} addr [count]
5182 @deffnx Command {flash mdb} addr [count]
5183 Display contents of address @var{addr}, as
5184 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5185 or 8-bit bytes (@command{mdb}).
5186 If @var{count} is specified, displays that many units.
5187 Reads from flash using the flash driver, therefore it enables reading
5188 from a bank not mapped in target address space.
5189 The flash bank to use is inferred from the @var{address} of
5190 each block, and the specified length must stay within that bank.
5193 @deffn Command {flash write_bank} num filename [offset]
5194 Write the binary @file{filename} to flash bank @var{num},
5195 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5196 is omitted, start at the beginning of the flash bank.
5197 The @var{num} parameter is a value shown by @command{flash banks}.
5200 @deffn Command {flash read_bank} num filename [offset [length]]
5201 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5202 and write the contents to the binary @file{filename}. If @var{offset} is
5203 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5204 read the remaining bytes from the flash bank.
5205 The @var{num} parameter is a value shown by @command{flash banks}.
5208 @deffn Command {flash verify_bank} num filename [offset]
5209 Compare the contents of the binary file @var{filename} with the contents of the
5210 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5211 start at the beginning of the flash bank. Fail if the contents do not match.
5212 The @var{num} parameter is a value shown by @command{flash banks}.
5215 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
5216 Write the image @file{filename} to the current target's flash bank(s).
5217 Only loadable sections from the image are written.
5218 A relocation @var{offset} may be specified, in which case it is added
5219 to the base address for each section in the image.
5220 The file [@var{type}] can be specified
5221 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5222 @option{elf} (ELF file), @option{s19} (Motorola s19).
5223 @option{mem}, or @option{builder}.
5224 The relevant flash sectors will be erased prior to programming
5225 if the @option{erase} parameter is given. If @option{unlock} is
5226 provided, then the flash banks are unlocked before erase and
5227 program. The flash bank to use is inferred from the address of
5231 Be careful using the @option{erase} flag when the flash is holding
5232 data you want to preserve.
5233 Portions of the flash outside those described in the image's
5234 sections might be erased with no notice.
5237 When a section of the image being written does not fill out all the
5238 sectors it uses, the unwritten parts of those sectors are necessarily
5239 also erased, because sectors can't be partially erased.
5241 Data stored in sector "holes" between image sections are also affected.
5242 For example, "@command{flash write_image erase ...}" of an image with
5243 one byte at the beginning of a flash bank and one byte at the end
5244 erases the entire bank -- not just the two sectors being written.
5246 Also, when flash protection is important, you must re-apply it after
5247 it has been removed by the @option{unlock} flag.
5252 @section Other Flash commands
5253 @cindex flash protection
5255 @deffn Command {flash erase_check} num
5256 Check erase state of sectors in flash bank @var{num},
5257 and display that status.
5258 The @var{num} parameter is a value shown by @command{flash banks}.
5261 @deffn Command {flash info} num [sectors]
5262 Print info about flash bank @var{num}, a list of protection blocks
5263 and their status. Use @option{sectors} to show a list of sectors instead.
5265 The @var{num} parameter is a value shown by @command{flash banks}.
5266 This command will first query the hardware, it does not print cached
5267 and possibly stale information.
5270 @anchor{flashprotect}
5271 @deffn Command {flash protect} num first last (@option{on}|@option{off})
5272 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5273 in flash bank @var{num}, starting at protection block @var{first}
5274 and continuing up to and including @var{last}.
5275 Providing a @var{last} block of @option{last}
5276 specifies "to the end of the flash bank".
5277 The @var{num} parameter is a value shown by @command{flash banks}.
5278 The protection block is usually identical to a flash sector.
5279 Some devices may utilize a protection block distinct from flash sector.
5280 See @command{flash info} for a list of protection blocks.
5283 @deffn Command {flash padded_value} num value
5284 Sets the default value used for padding any image sections, This should
5285 normally match the flash bank erased value. If not specified by this
5286 command or the flash driver then it defaults to 0xff.
5290 @deffn Command {program} filename [preverify] [verify] [reset] [exit] [offset]
5291 This is a helper script that simplifies using OpenOCD as a standalone
5292 programmer. The only required parameter is @option{filename}, the others are optional.
5293 @xref{Flash Programming}.
5296 @anchor{flashdriverlist}
5297 @section Flash Driver List
5298 As noted above, the @command{flash bank} command requires a driver name,
5299 and allows driver-specific options and behaviors.
5300 Some drivers also activate driver-specific commands.
5302 @deffn {Flash Driver} virtual
5303 This is a special driver that maps a previously defined bank to another
5304 address. All bank settings will be copied from the master physical bank.
5306 The @var{virtual} driver defines one mandatory parameters,
5309 @item @var{master_bank} The bank that this virtual address refers to.
5312 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5313 the flash bank defined at address 0x1fc00000. Any command executed on
5314 the virtual banks is actually performed on the physical banks.
5316 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5317 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5318 $_TARGETNAME $_FLASHNAME
5319 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5320 $_TARGETNAME $_FLASHNAME
5324 @subsection External Flash
5326 @deffn {Flash Driver} cfi
5327 @cindex Common Flash Interface
5329 The ``Common Flash Interface'' (CFI) is the main standard for
5330 external NOR flash chips, each of which connects to a
5331 specific external chip select on the CPU.
5332 Frequently the first such chip is used to boot the system.
5333 Your board's @code{reset-init} handler might need to
5334 configure additional chip selects using other commands (like: @command{mww} to
5335 configure a bus and its timings), or
5336 perhaps configure a GPIO pin that controls the ``write protect'' pin
5338 The CFI driver can use a target-specific working area to significantly
5341 The CFI driver can accept the following optional parameters, in any order:
5344 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5345 like AM29LV010 and similar types.
5346 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5347 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5348 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5349 swapped when writing data values (i.e. not CFI commands).
5352 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5353 wide on a sixteen bit bus:
5356 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5357 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5360 To configure one bank of 32 MBytes
5361 built from two sixteen bit (two byte) wide parts wired in parallel
5362 to create a thirty-two bit (four byte) bus with doubled throughput:
5365 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5368 @c "cfi part_id" disabled
5371 @deffn {Flash Driver} jtagspi
5372 @cindex Generic JTAG2SPI driver
5376 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5377 SPI flash connected to them. To access this flash from the host, the device
5378 is first programmed with a special proxy bitstream that
5379 exposes the SPI flash on the device's JTAG interface. The flash can then be
5380 accessed through JTAG.
5382 Since signaling between JTAG and SPI is compatible, all that is required for
5383 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5384 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5385 a bitstream for several Xilinx FPGAs can be found in
5386 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5387 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5389 This flash bank driver requires a target on a JTAG tap and will access that
5390 tap directly. Since no support from the target is needed, the target can be a
5391 "testee" dummy. Since the target does not expose the flash memory
5392 mapping, target commands that would otherwise be expected to access the flash
5393 will not work. These include all @command{*_image} and
5394 @command{$target_name m*} commands as well as @command{program}. Equivalent
5395 functionality is available through the @command{flash write_bank},
5396 @command{flash read_bank}, and @command{flash verify_bank} commands.
5399 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5400 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5401 @var{USER1} instruction.
5405 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5406 set _XILINX_USER1 0x02
5407 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5408 $_TARGETNAME $_XILINX_USER1
5412 @deffn {Flash Driver} xcf
5413 @cindex Xilinx Platform flash driver
5415 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5416 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5417 only difference is special registers controlling its FPGA specific behavior.
5418 They must be properly configured for successful FPGA loading using
5419 additional @var{xcf} driver command:
5421 @deffn Command {xcf ccb} <bank_id>
5422 command accepts additional parameters:
5424 @item @var{external|internal} ... selects clock source.
5425 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5426 @item @var{slave|master} ... selects slave of master mode for flash device.
5427 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5431 xcf ccb 0 external parallel slave 40
5433 All of them must be specified even if clock frequency is pointless
5434 in slave mode. If only bank id specified than command prints current
5435 CCB register value. Note: there is no need to write this register
5436 every time you erase/program data sectors because it stores in
5440 @deffn Command {xcf configure} <bank_id>
5441 Initiates FPGA loading procedure. Useful if your board has no "configure"
5448 Additional driver notes:
5450 @item Only single revision supported.
5451 @item Driver automatically detects need of bit reverse, but
5452 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5453 (Intel hex) file types supported.
5454 @item For additional info check xapp972.pdf and ug380.pdf.
5458 @deffn {Flash Driver} lpcspifi
5459 @cindex NXP SPI Flash Interface
5462 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5463 Flash Interface (SPIFI) peripheral that can drive and provide
5464 memory mapped access to external SPI flash devices.
5466 The lpcspifi driver initializes this interface and provides
5467 program and erase functionality for these serial flash devices.
5468 Use of this driver @b{requires} a working area of at least 1kB
5469 to be configured on the target device; more than this will
5470 significantly reduce flash programming times.
5472 The setup command only requires the @var{base} parameter. All
5473 other parameters are ignored, and the flash size and layout
5474 are configured by the driver.
5477 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5482 @deffn {Flash Driver} stmsmi
5483 @cindex STMicroelectronics Serial Memory Interface
5486 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5487 SPEAr MPU family) include a proprietary
5488 ``Serial Memory Interface'' (SMI) controller able to drive external
5490 Depending on specific device and board configuration, up to 4 external
5491 flash devices can be connected.
5493 SMI makes the flash content directly accessible in the CPU address
5494 space; each external device is mapped in a memory bank.
5495 CPU can directly read data, execute code and boot from SMI banks.
5496 Normal OpenOCD commands like @command{mdw} can be used to display
5499 The setup command only requires the @var{base} parameter in order
5500 to identify the memory bank.
5501 All other parameters are ignored. Additional information, like
5502 flash size, are detected automatically.
5505 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5510 @deffn {Flash Driver} mrvlqspi
5511 This driver supports QSPI flash controller of Marvell's Wireless
5512 Microcontroller platform.
5514 The flash size is autodetected based on the table of known JEDEC IDs
5515 hardcoded in the OpenOCD sources.
5518 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5523 @deffn {Flash Driver} ath79
5524 @cindex Atheros ath79 SPI driver
5526 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5528 On reset a SPI flash connected to the first chip select (CS0) is made
5529 directly read-accessible in the CPU address space (up to 16MBytes)
5530 and is usually used to store the bootloader and operating system.
5531 Normal OpenOCD commands like @command{mdw} can be used to display
5532 the flash content while it is in memory-mapped mode (only the first
5533 4MBytes are accessible without additional configuration on reset).
5535 The setup command only requires the @var{base} parameter in order
5536 to identify the memory bank. The actual value for the base address
5537 is not otherwise used by the driver. However the mapping is passed
5538 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5539 address should be the actual memory mapped base address. For unmapped
5540 chipselects (CS1 and CS2) care should be taken to use a base address
5541 that does not overlap with real memory regions.
5542 Additional information, like flash size, are detected automatically.
5543 An optional additional parameter sets the chipselect for the bank,
5544 with the default CS0.
5545 CS1 and CS2 require additional GPIO setup before they can be used
5546 since the alternate function must be enabled on the GPIO pin
5547 CS1/CS2 is routed to on the given SoC.
5550 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
5552 # When using multiple chipselects the base should be different for each,
5553 # otherwise the write_image command is not able to distinguish the
5555 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
5556 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5557 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5562 @deffn {Flash Driver} fespi
5563 @cindex Freedom E SPI
5566 SiFive's Freedom E SPI controller, used in HiFive and other boards.
5569 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
5573 @subsection Internal Flash (Microcontrollers)
5575 @deffn {Flash Driver} aduc702x
5576 The ADUC702x analog microcontrollers from Analog Devices
5577 include internal flash and use ARM7TDMI cores.
5578 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5579 The setup command only requires the @var{target} argument
5580 since all devices in this family have the same memory layout.
5583 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5587 @deffn {Flash Driver} ambiqmicro
5590 All members of the Apollo microcontroller family from
5591 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5592 The host connects over USB to an FTDI interface that communicates
5593 with the target using SWD.
5595 The @var{ambiqmicro} driver reads the Chip Information Register detect
5596 the device class of the MCU.
5597 The Flash and SRAM sizes directly follow device class, and are used
5598 to set up the flash banks.
5599 If this fails, the driver will use default values set to the minimum
5600 sizes of an Apollo chip.
5602 All Apollo chips have two flash banks of the same size.
5603 In all cases the first flash bank starts at location 0,
5604 and the second bank starts after the first.
5608 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5609 # Flash bank 1 - same size as bank0, starts after bank 0.
5610 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5614 Flash is programmed using custom entry points into the bootloader.
5615 This is the only way to program the flash as no flash control registers
5616 are available to the user.
5618 The @var{ambiqmicro} driver adds some additional commands:
5620 @deffn Command {ambiqmicro mass_erase} <bank>
5623 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
5626 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
5627 Program OTP is a one time operation to create write protected flash.
5628 The user writes sectors to SRAM starting at 0x10000010.
5629 Program OTP will write these sectors from SRAM to flash, and write protect
5635 @deffn {Flash Driver} at91samd
5637 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
5638 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5640 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
5642 The devices have one flash bank:
5645 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
5648 @deffn Command {at91samd chip-erase}
5649 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5650 used to erase a chip back to its factory state and does not require the
5651 processor to be halted.
5654 @deffn Command {at91samd set-security}
5655 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5656 to the Flash and can only be undone by using the chip-erase command which
5657 erases the Flash contents and turns off the security bit. Warning: at this
5658 time, openocd will not be able to communicate with a secured chip and it is
5659 therefore not possible to chip-erase it without using another tool.
5662 at91samd set-security enable
5666 @deffn Command {at91samd eeprom}
5667 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5668 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5669 must be one of the permitted sizes according to the datasheet. Settings are
5670 written immediately but only take effect on MCU reset. EEPROM emulation
5671 requires additional firmware support and the minimum EEPROM size may not be
5672 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5673 in order to disable this feature.
5677 at91samd eeprom 1024
5681 @deffn Command {at91samd bootloader}
5682 Shows or sets the bootloader size configuration, stored in the User Row of the
5683 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5684 must be specified in bytes and it must be one of the permitted sizes according
5685 to the datasheet. Settings are written immediately but only take effect on
5686 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5690 at91samd bootloader 16384
5694 @deffn Command {at91samd dsu_reset_deassert}
5695 This command releases internal reset held by DSU
5696 and prepares reset vector catch in case of reset halt.
5697 Command is used internally in event reset-deassert-post.
5700 @deffn Command {at91samd nvmuserrow}
5701 Writes or reads the entire 64 bit wide NVM user row register which is located at
5702 0x804000. This register includes various fuses lock-bits and factory calibration
5703 data. Reading the register is done by invoking this command without any
5704 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
5705 is the register value to be written and the second one is an optional changemask.
5706 Every bit which value in changemask is 0 will stay unchanged. The lock- and
5707 reserved-bits are masked out and cannot be changed.
5711 >at91samd nvmuserrow
5712 NVMUSERROW: 0xFFFFFC5DD8E0C788
5713 # Write 0xFFFFFC5DD8E0C788 to user row
5714 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
5715 # Write 0x12300 to user row but leave other bits and low byte unchanged
5716 >at91samd nvmuserrow 0x12345 0xFFF00
5723 @deffn {Flash Driver} at91sam3
5725 All members of the AT91SAM3 microcontroller family from
5726 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5727 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5728 that the driver was orginaly developed and tested using the
5729 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5730 the family was cribbed from the data sheet. @emph{Note to future
5731 readers/updaters: Please remove this worrisome comment after other
5732 chips are confirmed.}
5734 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5735 have one flash bank. In all cases the flash banks are at
5736 the following fixed locations:
5739 # Flash bank 0 - all chips
5740 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5741 # Flash bank 1 - only 256K chips
5742 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5745 Internally, the AT91SAM3 flash memory is organized as follows.
5746 Unlike the AT91SAM7 chips, these are not used as parameters
5747 to the @command{flash bank} command:
5750 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5751 @item @emph{Bank Size:} 128K/64K Per flash bank
5752 @item @emph{Sectors:} 16 or 8 per bank
5753 @item @emph{SectorSize:} 8K Per Sector
5754 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5757 The AT91SAM3 driver adds some additional commands:
5759 @deffn Command {at91sam3 gpnvm}
5760 @deffnx Command {at91sam3 gpnvm clear} number
5761 @deffnx Command {at91sam3 gpnvm set} number
5762 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5763 With no parameters, @command{show} or @command{show all},
5764 shows the status of all GPNVM bits.
5765 With @command{show} @var{number}, displays that bit.
5767 With @command{set} @var{number} or @command{clear} @var{number},
5768 modifies that GPNVM bit.
5771 @deffn Command {at91sam3 info}
5772 This command attempts to display information about the AT91SAM3
5773 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5774 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5775 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5776 various clock configuration registers and attempts to display how it
5777 believes the chip is configured. By default, the SLOWCLK is assumed to
5778 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5781 @deffn Command {at91sam3 slowclk} [value]
5782 This command shows/sets the slow clock frequency used in the
5783 @command{at91sam3 info} command calculations above.
5787 @deffn {Flash Driver} at91sam4
5789 All members of the AT91SAM4 microcontroller family from
5790 Atmel include internal flash and use ARM's Cortex-M4 core.
5791 This driver uses the same command names/syntax as @xref{at91sam3}.
5794 @deffn {Flash Driver} at91sam4l
5796 All members of the AT91SAM4L microcontroller family from
5797 Atmel include internal flash and use ARM's Cortex-M4 core.
5798 This driver uses the same command names/syntax as @xref{at91sam3}.
5800 The AT91SAM4L driver adds some additional commands:
5801 @deffn Command {at91sam4l smap_reset_deassert}
5802 This command releases internal reset held by SMAP
5803 and prepares reset vector catch in case of reset halt.
5804 Command is used internally in event reset-deassert-post.
5809 @deffn {Flash Driver} atsame5
5811 All members of the SAM E54, E53, E51 and D51 microcontroller
5812 families from Microchip (former Atmel) include internal flash
5813 and use ARM's Cortex-M4 core.
5815 The devices have two ECC flash banks with a swapping feature.
5816 This driver handles both banks together as it were one.
5817 Bank swapping is not supported yet.
5820 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
5823 @deffn Command {atsame5 bootloader}
5824 Shows or sets the bootloader size configuration, stored in the User Page of the
5825 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5826 must be specified in bytes. The nearest bigger protection size is used.
5827 Settings are written immediately but only take effect on MCU reset.
5828 Setting the bootloader size to 0 disables bootloader protection.
5832 atsame5 bootloader 16384
5836 @deffn Command {atsame5 chip-erase}
5837 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5838 used to erase a chip back to its factory state and does not require the
5839 processor to be halted.
5842 @deffn Command {atsame5 dsu_reset_deassert}
5843 This command releases internal reset held by DSU
5844 and prepares reset vector catch in case of reset halt.
5845 Command is used internally in event reset-deassert-post.
5848 @deffn Command {atsame5 userpage}
5849 Writes or reads the first 64 bits of NVM User Page which is located at
5850 0x804000. This field includes various fuses.
5851 Reading is done by invoking this command without any arguments.
5852 Writing is possible by giving 1 or 2 hex values. The first argument
5853 is the value to be written and the second one is an optional bit mask
5854 (a zero bit in the mask means the bit stays unchanged).
5855 The reserved fields are always masked out and cannot be changed.
5860 USER PAGE: 0xAEECFF80FE9A9239
5862 >atsame5 userpage 0xAEECFF80FE9A9239
5863 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other bits unchanged
5864 # (setup SmartEEPROM of virtual size 8192 bytes)
5865 >atsame5 userpage 0x4200000000 0x7f00000000
5871 @deffn {Flash Driver} atsamv
5873 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
5874 Atmel include internal flash and use ARM's Cortex-M7 core.
5875 This driver uses the same command names/syntax as @xref{at91sam3}.
5878 @deffn {Flash Driver} at91sam7
5879 All members of the AT91SAM7 microcontroller family from Atmel include
5880 internal flash and use ARM7TDMI cores. The driver automatically
5881 recognizes a number of these chips using the chip identification
5882 register, and autoconfigures itself.
5885 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5888 For chips which are not recognized by the controller driver, you must
5889 provide additional parameters in the following order:
5892 @item @var{chip_model} ... label used with @command{flash info}
5894 @item @var{sectors_per_bank}
5895 @item @var{pages_per_sector}
5896 @item @var{pages_size}
5897 @item @var{num_nvm_bits}
5898 @item @var{freq_khz} ... required if an external clock is provided,
5899 optional (but recommended) when the oscillator frequency is known
5902 It is recommended that you provide zeroes for all of those values
5903 except the clock frequency, so that everything except that frequency
5904 will be autoconfigured.
5905 Knowing the frequency helps ensure correct timings for flash access.
5907 The flash controller handles erases automatically on a page (128/256 byte)
5908 basis, so explicit erase commands are not necessary for flash programming.
5909 However, there is an ``EraseAll`` command that can erase an entire flash
5910 plane (of up to 256KB), and it will be used automatically when you issue
5911 @command{flash erase_sector} or @command{flash erase_address} commands.
5913 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5914 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5915 bit for the processor. Each processor has a number of such bits,
5916 used for controlling features such as brownout detection (so they
5917 are not truly general purpose).
5919 This assumes that the first flash bank (number 0) is associated with
5920 the appropriate at91sam7 target.
5925 @deffn {Flash Driver} avr
5926 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5927 @emph{The current implementation is incomplete.}
5928 @comment - defines mass_erase ... pointless given flash_erase_address
5931 @deffn {Flash Driver} bluenrg-x
5932 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
5933 The driver automatically recognizes these chips using
5934 the chip identification registers, and autoconfigures itself.
5937 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
5940 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
5941 each single sector one by one.
5944 flash erase_sector 0 0 last # It will perform a mass erase
5947 Triggering a mass erase is also useful when users want to disable readout protection.
5950 @deffn {Flash Driver} cc26xx
5951 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
5952 Instruments include internal flash. The cc26xx flash driver supports both the
5953 CC13xx and CC26xx family of devices. The driver automatically recognizes the
5954 specific version's flash parameters and autoconfigures itself. The flash bank
5955 starts at address 0.
5958 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
5962 @deffn {Flash Driver} cc3220sf
5963 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
5964 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
5965 supports the internal flash. The serial flash on SimpleLink boards is
5966 programmed via the bootloader over a UART connection. Security features of
5967 the CC3220SF may erase the internal flash during power on reset. Refer to
5968 documentation at @url{www.ti.com/cc3220sf} for details on security features
5969 and programming the serial flash.
5972 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
5976 @deffn {Flash Driver} efm32
5977 All members of the EFM32 microcontroller family from Energy Micro include
5978 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
5979 a number of these chips using the chip identification register, and
5980 autoconfigures itself.
5982 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5984 A special feature of efm32 controllers is that it is possible to completely disable the
5985 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
5986 this via the following command:
5990 The @var{num} parameter is a value shown by @command{flash banks}.
5991 Note that in order for this command to take effect, the target needs to be reset.
5992 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5996 @deffn {Flash Driver} esirisc
5997 Members of the eSi-RISC family may optionally include internal flash programmed
5998 via the eSi-TSMC Flash interface. Additional parameters are required to
5999 configure the driver: @option{cfg_address} is the base address of the
6000 configuration register interface, @option{clock_hz} is the expected clock
6001 frequency, and @option{wait_states} is the number of configured read wait states.
6004 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6005 $_TARGETNAME cfg_address clock_hz wait_states
6008 @deffn Command {esirisc flash mass_erase} bank_id
6009 Erase all pages in data memory for the bank identified by @option{bank_id}.
6012 @deffn Command {esirisc flash ref_erase} bank_id
6013 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6014 is an uncommon operation.}
6018 @deffn {Flash Driver} fm3
6019 All members of the FM3 microcontroller family from Fujitsu
6020 include internal flash and use ARM Cortex-M3 cores.
6021 The @var{fm3} driver uses the @var{target} parameter to select the
6022 correct bank config, it can currently be one of the following:
6023 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6024 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6027 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6031 @deffn {Flash Driver} fm4
6032 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6033 include internal flash and use ARM Cortex-M4 cores.
6034 The @var{fm4} driver uses a @var{family} parameter to select the
6035 correct bank config, it can currently be one of the following:
6036 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6037 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6038 with @code{x} treated as wildcard and otherwise case (and any trailing
6039 characters) ignored.
6042 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6043 $_TARGETNAME S6E2CCAJ0A
6044 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6045 $_TARGETNAME S6E2CCAJ0A
6047 @emph{The current implementation is incomplete. Protection is not supported,
6048 nor is Chip Erase (only Sector Erase is implemented).}
6051 @deffn {Flash Driver} kinetis
6053 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
6054 from NXP (former Freescale) include
6055 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
6056 recognizes flash size and a number of flash banks (1-4) using the chip
6057 identification register, and autoconfigures itself.
6058 Use kinetis_ke driver for KE0x and KEAx devices.
6060 The @var{kinetis} driver defines option:
6062 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
6066 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6069 @deffn Command {kinetis create_banks}
6070 Configuration command enables automatic creation of additional flash banks
6071 based on real flash layout of device. Banks are created during device probe.
6072 Use 'flash probe 0' to force probe.
6075 @deffn Command {kinetis fcf_source} [protection|write]
6076 Select what source is used when writing to a Flash Configuration Field.
6077 @option{protection} mode builds FCF content from protection bits previously
6078 set by 'flash protect' command.
6079 This mode is default. MCU is protected from unwanted locking by immediate
6080 writing FCF after erase of relevant sector.
6081 @option{write} mode enables direct write to FCF.
6082 Protection cannot be set by 'flash protect' command. FCF is written along
6083 with the rest of a flash image.
6084 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6087 @deffn Command {kinetis fopt} [num]
6088 Set value to write to FOPT byte of Flash Configuration Field.
6089 Used in kinetis 'fcf_source protection' mode only.
6092 @deffn Command {kinetis mdm check_security}
6093 Checks status of device security lock. Used internally in examine-end
6094 and examine-fail event.
6097 @deffn Command {kinetis mdm halt}
6098 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6099 loop when connecting to an unsecured target.
6102 @deffn Command {kinetis mdm mass_erase}
6103 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6104 back to its factory state, removing security. It does not require the processor
6105 to be halted, however the target will remain in a halted state after this
6109 @deffn Command {kinetis nvm_partition}
6110 For FlexNVM devices only (KxxDX and KxxFX).
6111 Command shows or sets data flash or EEPROM backup size in kilobytes,
6112 sets two EEPROM blocks sizes in bytes and enables/disables loading
6113 of EEPROM contents to FlexRAM during reset.
6115 For details see device reference manual, Flash Memory Module,
6116 Program Partition command.
6118 Setting is possible only once after mass_erase.
6119 Reset the device after partition setting.
6121 Show partition size:
6123 kinetis nvm_partition info
6126 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6127 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6129 kinetis nvm_partition dataflash 32 512 1536 on
6132 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6133 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6135 kinetis nvm_partition eebkp 16 1024 1024 off
6139 @deffn Command {kinetis mdm reset}
6140 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6141 RESET pin, which can be used to reset other hardware on board.
6144 @deffn Command {kinetis disable_wdog}
6145 For Kx devices only (KLx has different COP watchdog, it is not supported).
6146 Command disables watchdog timer.
6150 @deffn {Flash Driver} kinetis_ke
6152 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6153 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6154 the KE0x sub-family using the chip identification register, and
6155 autoconfigures itself.
6156 Use kinetis (not kinetis_ke) driver for KE1x devices.
6159 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6162 @deffn Command {kinetis_ke mdm check_security}
6163 Checks status of device security lock. Used internally in examine-end event.
6166 @deffn Command {kinetis_ke mdm mass_erase}
6167 Issues a complete Flash erase via the MDM-AP.
6168 This can be used to erase a chip back to its factory state.
6169 Command removes security lock from a device (use of SRST highly recommended).
6170 It does not require the processor to be halted.
6173 @deffn Command {kinetis_ke disable_wdog}
6174 Command disables watchdog timer.
6178 @deffn {Flash Driver} lpc2000
6179 This is the driver to support internal flash of all members of the
6180 LPC11(x)00 and LPC1300 microcontroller families and most members of
6181 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6182 LPC8Nxx and NHS31xx microcontroller families from NXP.
6185 There are LPC2000 devices which are not supported by the @var{lpc2000}
6187 The LPC2888 is supported by the @var{lpc288x} driver.
6188 The LPC29xx family is supported by the @var{lpc2900} driver.
6191 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6192 which must appear in the following order:
6195 @item @var{variant} ... required, may be
6196 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6197 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6198 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6199 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6201 @option{lpc800} (LPC8xx)
6202 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6203 @option{lpc1500} (LPC15xx)
6204 @option{lpc54100} (LPC541xx)
6205 @option{lpc4000} (LPC40xx)
6206 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6207 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6208 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6209 at which the core is running
6210 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6211 telling the driver to calculate a valid checksum for the exception vector table.
6213 If you don't provide @option{calc_checksum} when you're writing the vector
6214 table, the boot ROM will almost certainly ignore your flash image.
6215 However, if you do provide it,
6216 with most tool chains @command{verify_image} will fail.
6218 @item @option{iap_entry} ... optional telling the driver to use a different
6219 ROM IAP entry point.
6222 LPC flashes don't require the chip and bus width to be specified.
6225 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6226 lpc2000_v2 14765 calc_checksum
6229 @deffn {Command} {lpc2000 part_id} bank
6230 Displays the four byte part identifier associated with
6231 the specified flash @var{bank}.
6235 @deffn {Flash Driver} lpc288x
6236 The LPC2888 microcontroller from NXP needs slightly different flash
6237 support from its lpc2000 siblings.
6238 The @var{lpc288x} driver defines one mandatory parameter,
6239 the programming clock rate in Hz.
6240 LPC flashes don't require the chip and bus width to be specified.
6243 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6247 @deffn {Flash Driver} lpc2900
6248 This driver supports the LPC29xx ARM968E based microcontroller family
6251 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6252 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6253 sector layout are auto-configured by the driver.
6254 The driver has one additional mandatory parameter: The CPU clock rate
6255 (in kHz) at the time the flash operations will take place. Most of the time this
6256 will not be the crystal frequency, but a higher PLL frequency. The
6257 @code{reset-init} event handler in the board script is usually the place where
6260 The driver rejects flashless devices (currently the LPC2930).
6262 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6263 It must be handled much more like NAND flash memory, and will therefore be
6264 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6266 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6267 sector needs to be erased or programmed, it is automatically unprotected.
6268 What is shown as protection status in the @code{flash info} command, is
6269 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6270 sector from ever being erased or programmed again. As this is an irreversible
6271 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6272 and not by the standard @code{flash protect} command.
6274 Example for a 125 MHz clock frequency:
6276 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6279 Some @code{lpc2900}-specific commands are defined. In the following command list,
6280 the @var{bank} parameter is the bank number as obtained by the
6281 @code{flash banks} command.
6283 @deffn Command {lpc2900 signature} bank
6284 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6285 content. This is a hardware feature of the flash block, hence the calculation is
6286 very fast. You may use this to verify the content of a programmed device against
6291 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6295 @deffn Command {lpc2900 read_custom} bank filename
6296 Reads the 912 bytes of customer information from the flash index sector, and
6297 saves it to a file in binary format.
6300 lpc2900 read_custom 0 /path_to/customer_info.bin
6304 The index sector of the flash is a @emph{write-only} sector. It cannot be
6305 erased! In order to guard against unintentional write access, all following
6306 commands need to be preceded by a successful call to the @code{password}
6309 @deffn Command {lpc2900 password} bank password
6310 You need to use this command right before each of the following commands:
6311 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6312 @code{lpc2900 secure_jtag}.
6314 The password string is fixed to "I_know_what_I_am_doing".
6317 lpc2900 password 0 I_know_what_I_am_doing
6318 Potentially dangerous operation allowed in next command!
6322 @deffn Command {lpc2900 write_custom} bank filename type
6323 Writes the content of the file into the customer info space of the flash index
6324 sector. The filetype can be specified with the @var{type} field. Possible values
6325 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6326 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6327 contain a single section, and the contained data length must be exactly
6329 @quotation Attention
6330 This cannot be reverted! Be careful!
6334 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6338 @deffn Command {lpc2900 secure_sector} bank first last
6339 Secures the sector range from @var{first} to @var{last} (including) against
6340 further program and erase operations. The sector security will be effective
6341 after the next power cycle.
6342 @quotation Attention
6343 This cannot be reverted! Be careful!
6345 Secured sectors appear as @emph{protected} in the @code{flash info} command.
6348 lpc2900 secure_sector 0 1 1
6350 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
6351 # 0: 0x00000000 (0x2000 8kB) not protected
6352 # 1: 0x00002000 (0x2000 8kB) protected
6353 # 2: 0x00004000 (0x2000 8kB) not protected
6357 @deffn Command {lpc2900 secure_jtag} bank
6358 Irreversibly disable the JTAG port. The new JTAG security setting will be
6359 effective after the next power cycle.
6360 @quotation Attention
6361 This cannot be reverted! Be careful!
6365 lpc2900 secure_jtag 0
6370 @deffn {Flash Driver} mdr
6371 This drivers handles the integrated NOR flash on Milandr Cortex-M
6372 based controllers. A known limitation is that the Info memory can't be
6373 read or verified as it's not memory mapped.
6376 flash bank <name> mdr <base> <size> \
6377 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
6381 @item @var{type} - 0 for main memory, 1 for info memory
6382 @item @var{page_count} - total number of pages
6383 @item @var{sec_count} - number of sector per page count
6388 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
6389 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
6390 0 0 $_TARGETNAME 1 1 4
6392 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
6393 0 0 $_TARGETNAME 0 32 4
6398 @deffn {Flash Driver} msp432
6399 All versions of the SimpleLink MSP432 microcontrollers from Texas
6400 Instruments include internal flash. The msp432 flash driver automatically
6401 recognizes the specific version's flash parameters and autoconfigures itself.
6402 Main program flash starts at address 0. The information flash region on
6403 MSP432P4 versions starts at address 0x200000.
6406 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
6409 @deffn Command {msp432 mass_erase} bank_id [main|all]
6410 Performs a complete erase of flash. By default, @command{mass_erase} will erase
6411 only the main program flash.
6413 On MSP432P4 versions, using @command{mass_erase all} will erase both the
6414 main program and information flash regions. To also erase the BSL in information
6415 flash, the user must first use the @command{bsl} command.
6418 @deffn Command {msp432 bsl} bank_id [unlock|lock]
6419 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
6420 region in information flash so that flash commands can erase or write the BSL.
6421 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
6423 To erase and program the BSL:
6426 flash erase_address 0x202000 0x2000
6427 flash write_image bsl.bin 0x202000
6433 @deffn {Flash Driver} niietcm4
6434 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6435 based controllers. Flash size and sector layout are auto-configured by the driver.
6436 Main flash memory is called "Bootflash" and has main region and info region.
6437 Info region is NOT memory mapped by default,
6438 but it can replace first part of main region if needed.
6439 Full erase, single and block writes are supported for both main and info regions.
6440 There is additional not memory mapped flash called "Userflash", which
6441 also have division into regions: main and info.
6442 Purpose of userflash - to store system and user settings.
6443 Driver has special commands to perform operations with this memory.
6446 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6449 Some niietcm4-specific commands are defined:
6451 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
6452 Read byte from main or info userflash region.
6455 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6456 Write byte to main or info userflash region.
6459 @deffn Command {niietcm4 uflash_full_erase} bank
6460 Erase all userflash including info region.
6463 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6464 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6467 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
6468 Check sectors protect.
6471 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6472 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6475 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
6476 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6479 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6480 Configure external memory interface for boot.
6483 @deffn Command {niietcm4 service_mode_erase} bank
6484 Perform emergency erase of all flash (bootflash and userflash).
6487 @deffn Command {niietcm4 driver_info} bank
6488 Show information about flash driver.
6493 @deffn {Flash Driver} nrf5
6494 All members of the nRF51 microcontroller families from Nordic Semiconductor
6495 include internal flash and use ARM Cortex-M0 core.
6496 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
6497 internal flash and use an ARM Cortex-M4F core.
6500 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6503 Some nrf5-specific commands are defined:
6505 @deffn Command {nrf5 mass_erase}
6506 Erases the contents of the code memory and user information
6507 configuration registers as well. It must be noted that this command
6508 works only for chips that do not have factory pre-programmed region 0
6512 @deffn Command {nrf5 info}
6513 Decodes and shows information from FICR and UICR registers.
6518 @deffn {Flash Driver} ocl
6519 This driver is an implementation of the ``on chip flash loader''
6520 protocol proposed by Pavel Chromy.
6522 It is a minimalistic command-response protocol intended to be used
6523 over a DCC when communicating with an internal or external flash
6524 loader running from RAM. An example implementation for AT91SAM7x is
6525 available in @file{contrib/loaders/flash/at91sam7x/}.
6528 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
6532 @deffn {Flash Driver} pic32mx
6533 The PIC32MX microcontrollers are based on the MIPS 4K cores,
6534 and integrate flash memory.
6537 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
6538 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
6541 @comment numerous *disabled* commands are defined:
6542 @comment - chip_erase ... pointless given flash_erase_address
6543 @comment - lock, unlock ... pointless given protect on/off (yes?)
6544 @comment - pgm_word ... shouldn't bank be deduced from address??
6545 Some pic32mx-specific commands are defined:
6546 @deffn Command {pic32mx pgm_word} address value bank
6547 Programs the specified 32-bit @var{value} at the given @var{address}
6548 in the specified chip @var{bank}.
6550 @deffn Command {pic32mx unlock} bank
6551 Unlock and erase specified chip @var{bank}.
6552 This will remove any Code Protection.
6556 @deffn {Flash Driver} psoc4
6557 All members of the PSoC 41xx/42xx microcontroller family from Cypress
6558 include internal flash and use ARM Cortex-M0 cores.
6559 The driver automatically recognizes a number of these chips using
6560 the chip identification register, and autoconfigures itself.
6562 Note: Erased internal flash reads as 00.
6563 System ROM of PSoC 4 does not implement erase of a flash sector.
6566 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
6569 psoc4-specific commands
6570 @deffn Command {psoc4 flash_autoerase} num (on|off)
6571 Enables or disables autoerase mode for a flash bank.
6573 If flash_autoerase is off, use mass_erase before flash programming.
6574 Flash erase command fails if region to erase is not whole flash memory.
6576 If flash_autoerase is on, a sector is both erased and programmed in one
6577 system ROM call. Flash erase command is ignored.
6578 This mode is suitable for gdb load.
6580 The @var{num} parameter is a value shown by @command{flash banks}.
6583 @deffn Command {psoc4 mass_erase} num
6584 Erases the contents of the flash memory, protection and security lock.
6586 The @var{num} parameter is a value shown by @command{flash banks}.
6590 @deffn {Flash Driver} psoc5lp
6591 All members of the PSoC 5LP microcontroller family from Cypress
6592 include internal program flash and use ARM Cortex-M3 cores.
6593 The driver probes for a number of these chips and autoconfigures itself,
6594 apart from the base address.
6597 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
6600 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
6601 @quotation Attention
6602 If flash operations are performed in ECC-disabled mode, they will also affect
6603 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
6604 then also erase the corresponding 2k data bytes in the 0x48000000 area.
6605 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
6608 Commands defined in the @var{psoc5lp} driver:
6610 @deffn Command {psoc5lp mass_erase}
6611 Erases all flash data and ECC/configuration bytes, all flash protection rows,
6612 and all row latches in all flash arrays on the device.
6616 @deffn {Flash Driver} psoc5lp_eeprom
6617 All members of the PSoC 5LP microcontroller family from Cypress
6618 include internal EEPROM and use ARM Cortex-M3 cores.
6619 The driver probes for a number of these chips and autoconfigures itself,
6620 apart from the base address.
6623 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
6627 @deffn {Flash Driver} psoc5lp_nvl
6628 All members of the PSoC 5LP microcontroller family from Cypress
6629 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
6630 The driver probes for a number of these chips and autoconfigures itself.
6633 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
6636 PSoC 5LP chips have multiple NV Latches:
6639 @item Device Configuration NV Latch - 4 bytes
6640 @item Write Once (WO) NV Latch - 4 bytes
6643 @b{Note:} This driver only implements the Device Configuration NVL.
6645 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
6646 @quotation Attention
6647 Switching ECC mode via write to Device Configuration NVL will require a reset
6648 after successful write.
6652 @deffn {Flash Driver} psoc6
6653 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
6654 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
6655 the same Flash/RAM/MMIO address space.
6657 Flash in PSoC6 is split into three regions:
6659 @item Main Flash - this is the main storage for user application.
6660 Total size varies among devices, sector size: 256 kBytes, row size:
6661 512 bytes. Supports erase operation on individual rows.
6662 @item Work Flash - intended to be used as storage for user data
6663 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
6664 row size: 512 bytes.
6665 @item Supervisory Flash - special region which contains device-specific
6666 service data. This region does not support erase operation. Only few rows can
6667 be programmed by the user, most of the rows are read only. Programming
6668 operation will erase row automatically.
6671 All three flash regions are supported by the driver. Flash geometry is detected
6672 automatically by parsing data in SPCIF_GEOMETRY register.
6674 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
6677 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm0
6678 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm0
6679 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm0
6680 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm0
6681 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm0
6682 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm0
6684 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm4
6685 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm4
6686 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm4
6687 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm4
6688 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm4
6689 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm4
6692 psoc6-specific commands
6693 @deffn Command {psoc6 reset_halt}
6694 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
6695 When invoked for CM0+ target, it will set break point at application entry point
6696 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
6697 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
6698 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
6701 @deffn Command {psoc6 mass_erase} num
6702 Erases the contents given flash bank. The @var{num} parameter is a value shown
6703 by @command{flash banks}.
6704 Note: only Main and Work flash regions support Erase operation.
6708 @deffn {Flash Driver} sim3x
6709 All members of the SiM3 microcontroller family from Silicon Laboratories
6710 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
6712 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
6713 If this fails, it will use the @var{size} parameter as the size of flash bank.
6716 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
6719 There are 2 commands defined in the @var{sim3x} driver:
6721 @deffn Command {sim3x mass_erase}
6722 Erases the complete flash. This is used to unlock the flash.
6723 And this command is only possible when using the SWD interface.
6726 @deffn Command {sim3x lock}
6727 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
6731 @deffn {Flash Driver} stellaris
6732 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
6733 families from Texas Instruments include internal flash. The driver
6734 automatically recognizes a number of these chips using the chip
6735 identification register, and autoconfigures itself.
6738 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
6741 @deffn Command {stellaris recover}
6742 Performs the @emph{Recovering a "Locked" Device} procedure to restore
6743 the flash and its associated nonvolatile registers to their factory
6744 default values (erased). This is the only way to remove flash
6745 protection or re-enable debugging if that capability has been
6748 Note that the final "power cycle the chip" step in this procedure
6749 must be performed by hand, since OpenOCD can't do it.
6751 if more than one Stellaris chip is connected, the procedure is
6752 applied to all of them.
6757 @deffn {Flash Driver} stm32f1x
6758 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
6759 from STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
6760 The driver automatically recognizes a number of these chips using
6761 the chip identification register, and autoconfigures itself.
6764 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
6767 Note that some devices have been found that have a flash size register that contains
6768 an invalid value, to workaround this issue you can override the probed value used by
6772 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
6775 If you have a target with dual flash banks then define the second bank
6776 as per the following example.
6778 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
6781 Some stm32f1x-specific commands are defined:
6783 @deffn Command {stm32f1x lock} num
6784 Locks the entire stm32 device against reading.
6785 The @var{num} parameter is a value shown by @command{flash banks}.
6788 @deffn Command {stm32f1x unlock} num
6789 Unlocks the entire stm32 device for reading. This command will cause
6790 a mass erase of the entire stm32 device if previously locked.
6791 The @var{num} parameter is a value shown by @command{flash banks}.
6794 @deffn Command {stm32f1x mass_erase} num
6795 Mass erases the entire stm32 device.
6796 The @var{num} parameter is a value shown by @command{flash banks}.
6799 @deffn Command {stm32f1x options_read} num
6800 Reads and displays active stm32 option bytes loaded during POR
6801 or upon executing the @command{stm32f1x options_load} command.
6802 The @var{num} parameter is a value shown by @command{flash banks}.
6805 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
6806 Writes the stm32 option byte with the specified values.
6807 The @var{num} parameter is a value shown by @command{flash banks}.
6808 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
6811 @deffn Command {stm32f1x options_load} num
6812 Generates a special kind of reset to re-load the stm32 option bytes written
6813 by the @command{stm32f1x options_write} or @command{flash protect} commands
6814 without having to power cycle the target. Not applicable to stm32f1x devices.
6815 The @var{num} parameter is a value shown by @command{flash banks}.
6819 @deffn {Flash Driver} stm32f2x
6820 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
6821 include internal flash and use ARM Cortex-M3/M4/M7 cores.
6822 The driver automatically recognizes a number of these chips using
6823 the chip identification register, and autoconfigures itself.
6826 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
6829 If you use OTP (One-Time Programmable) memory define it as a second bank
6830 as per the following example.
6832 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
6835 @deffn Command {stm32f2x otp } num (@option{enable}|@option{disable}|@option{show})
6836 Enables or disables OTP write commands for bank @var{num}.
6837 The @var{num} parameter is a value shown by @command{flash banks}.
6840 Note that some devices have been found that have a flash size register that contains
6841 an invalid value, to workaround this issue you can override the probed value used by
6845 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
6848 Some stm32f2x-specific commands are defined:
6850 @deffn Command {stm32f2x lock} num
6851 Locks the entire stm32 device.
6852 The @var{num} parameter is a value shown by @command{flash banks}.
6855 @deffn Command {stm32f2x unlock} num
6856 Unlocks the entire stm32 device.
6857 The @var{num} parameter is a value shown by @command{flash banks}.
6860 @deffn Command {stm32f2x mass_erase} num
6861 Mass erases the entire stm32f2x device.
6862 The @var{num} parameter is a value shown by @command{flash banks}.
6865 @deffn Command {stm32f2x options_read} num
6866 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
6867 The @var{num} parameter is a value shown by @command{flash banks}.
6870 @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
6871 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
6872 Warning: The meaning of the various bits depends on the device, always check datasheet!
6873 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
6874 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
6875 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
6878 @deffn Command {stm32f2x optcr2_write} num optcr2
6879 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
6880 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
6884 @deffn {Flash Driver} stm32h7x
6885 All members of the STM32H7 microcontroller families from STMicroelectronics
6886 include internal flash and use ARM Cortex-M7 core.
6887 The driver automatically recognizes a number of these chips using
6888 the chip identification register, and autoconfigures itself.
6891 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
6894 Note that some devices have been found that have a flash size register that contains
6895 an invalid value, to workaround this issue you can override the probed value used by
6899 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
6902 Some stm32h7x-specific commands are defined:
6904 @deffn Command {stm32h7x lock} num
6905 Locks the entire stm32 device.
6906 The @var{num} parameter is a value shown by @command{flash banks}.
6909 @deffn Command {stm32h7x unlock} num
6910 Unlocks the entire stm32 device.
6911 The @var{num} parameter is a value shown by @command{flash banks}.
6914 @deffn Command {stm32h7x mass_erase} num
6915 Mass erases the entire stm32h7x device.
6916 The @var{num} parameter is a value shown by @command{flash banks}.
6919 @deffn Command {stm32h7x option_read} num reg_offset
6920 Reads an option byte register from the stm32h7x device.
6921 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6922 is the register offset of the option byte to read from the used bank registers' base.
6923 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
6928 stm32h7x option_read 0 0x1c
6930 stm32h7x option_read 0 0x38
6932 stm32h7x option_read 1 0x38
6936 @deffn Command {stm32h7x option_write} num reg_offset value [reg_mask]
6937 Writes an option byte register of the stm32h7x device.
6938 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6939 is the register offset of the option byte to write from the used bank register base,
6940 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
6945 # swap bank 1 and bank 2 in dual bank devices, by setting SWAP_BANK_OPT bit in OPTSR_PRG
6946 stm32h7x option_write 0 0x20 0x8000000 0x8000000
6951 @deffn {Flash Driver} stm32lx
6952 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
6953 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
6954 The driver automatically recognizes a number of these chips using
6955 the chip identification register, and autoconfigures itself.
6958 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
6961 Note that some devices have been found that have a flash size register that contains
6962 an invalid value, to workaround this issue you can override the probed value used by
6963 the flash driver. If you use 0 as the bank base address, it tells the
6964 driver to autodetect the bank location assuming you're configuring the
6968 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
6971 Some stm32lx-specific commands are defined:
6973 @deffn Command {stm32lx lock} num
6974 Locks the entire stm32 device.
6975 The @var{num} parameter is a value shown by @command{flash banks}.
6978 @deffn Command {stm32lx unlock} num
6979 Unlocks the entire stm32 device.
6980 The @var{num} parameter is a value shown by @command{flash banks}.
6983 @deffn Command {stm32lx mass_erase} num
6984 Mass erases the entire stm32lx device (all flash banks and EEPROM
6985 data). This is the only way to unlock a protected flash (unless RDP
6986 Level is 2 which can't be unlocked at all).
6987 The @var{num} parameter is a value shown by @command{flash banks}.
6991 @deffn {Flash Driver} stm32l4x
6992 All members of the STM32L4, STM32L4+, STM32WB, STM32WL and STM32G4
6993 microcontroller families from STMicroelectronics include internal flash
6994 and use ARM Cortex-M4 cores.
6995 Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core.
6996 The driver automatically recognizes a number of these chips using
6997 the chip identification register, and autoconfigures itself.
7000 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7003 Note that some devices have been found that have a flash size register that contains
7004 an invalid value, to workaround this issue you can override the probed value used by
7005 the flash driver. However, specifying a wrong value might lead to a completely
7006 wrong flash layout, so this feature must be used carefully.
7009 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7012 Some stm32l4x-specific commands are defined:
7014 @deffn Command {stm32l4x lock} num
7015 Locks the entire stm32 device.
7016 The @var{num} parameter is a value shown by @command{flash banks}.
7019 @deffn Command {stm32l4x unlock} num
7020 Unlocks the entire stm32 device.
7021 The @var{num} parameter is a value shown by @command{flash banks}.
7024 @deffn Command {stm32l4x mass_erase} num
7025 Mass erases the entire stm32l4x device.
7026 The @var{num} parameter is a value shown by @command{flash banks}.
7029 @deffn Command {stm32l4x option_read} num reg_offset
7030 Reads an option byte register from the stm32l4x device.
7031 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7032 is the register offset of the Option byte to read.
7034 For example to read the FLASH_OPTR register:
7036 stm32l4x option_read 0 0x20
7037 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
7038 # Option Register (for STM32WBx): <0x58004020> = ...
7039 # The correct flash base address will be used automatically
7042 The above example will read out the FLASH_OPTR register which contains the RDP
7043 option byte, Watchdog configuration, BOR level etc.
7046 @deffn Command {stm32l4x option_write} num reg_offset reg_mask
7047 Write an option byte register of the stm32l4x device.
7048 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7049 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
7050 to apply when writing the register (only bits with a '1' will be touched).
7052 For example to write the WRP1AR option bytes:
7054 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
7057 The above example will write the WRP1AR option register configuring the Write protection
7058 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
7059 This will effectively write protect all sectors in flash bank 1.
7062 @deffn Command {stm32l4x option_load} num
7063 Forces a re-load of the option byte registers. Will cause a system reset of the device.
7064 The @var{num} parameter is a value shown by @command{flash banks}.
7068 @deffn {Flash Driver} str7x
7069 All members of the STR7 microcontroller family from STMicroelectronics
7070 include internal flash and use ARM7TDMI cores.
7071 The @var{str7x} driver defines one mandatory parameter, @var{variant},
7072 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
7075 flash bank $_FLASHNAME str7x \
7076 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
7079 @deffn Command {str7x disable_jtag} bank
7080 Activate the Debug/Readout protection mechanism
7081 for the specified flash bank.
7085 @deffn {Flash Driver} str9x
7086 Most members of the STR9 microcontroller family from STMicroelectronics
7087 include internal flash and use ARM966E cores.
7088 The str9 needs the flash controller to be configured using
7089 the @command{str9x flash_config} command prior to Flash programming.
7092 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
7093 str9x flash_config 0 4 2 0 0x80000
7096 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
7097 Configures the str9 flash controller.
7098 The @var{num} parameter is a value shown by @command{flash banks}.
7101 @item @var{bbsr} - Boot Bank Size register
7102 @item @var{nbbsr} - Non Boot Bank Size register
7103 @item @var{bbadr} - Boot Bank Start Address register
7104 @item @var{nbbadr} - Boot Bank Start Address register
7110 @deffn {Flash Driver} str9xpec
7113 Only use this driver for locking/unlocking the device or configuring the option bytes.
7114 Use the standard str9 driver for programming.
7115 Before using the flash commands the turbo mode must be enabled using the
7116 @command{str9xpec enable_turbo} command.
7118 Here is some background info to help
7119 you better understand how this driver works. OpenOCD has two flash drivers for
7123 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7124 flash programming as it is faster than the @option{str9xpec} driver.
7126 Direct programming @option{str9xpec} using the flash controller. This is an
7127 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7128 core does not need to be running to program using this flash driver. Typical use
7129 for this driver is locking/unlocking the target and programming the option bytes.
7132 Before we run any commands using the @option{str9xpec} driver we must first disable
7133 the str9 core. This example assumes the @option{str9xpec} driver has been
7134 configured for flash bank 0.
7136 # assert srst, we do not want core running
7137 # while accessing str9xpec flash driver
7139 # turn off target polling
7142 str9xpec enable_turbo 0
7144 str9xpec options_read 0
7145 # re-enable str9 core
7146 str9xpec disable_turbo 0
7150 The above example will read the str9 option bytes.
7151 When performing a unlock remember that you will not be able to halt the str9 - it
7152 has been locked. Halting the core is not required for the @option{str9xpec} driver
7153 as mentioned above, just issue the commands above manually or from a telnet prompt.
7155 Several str9xpec-specific commands are defined:
7157 @deffn Command {str9xpec disable_turbo} num
7158 Restore the str9 into JTAG chain.
7161 @deffn Command {str9xpec enable_turbo} num
7162 Enable turbo mode, will simply remove the str9 from the chain and talk
7163 directly to the embedded flash controller.
7166 @deffn Command {str9xpec lock} num
7167 Lock str9 device. The str9 will only respond to an unlock command that will
7171 @deffn Command {str9xpec part_id} num
7172 Prints the part identifier for bank @var{num}.
7175 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7176 Configure str9 boot bank.
7179 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
7180 Configure str9 lvd source.
7183 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
7184 Configure str9 lvd threshold.
7187 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
7188 Configure str9 lvd reset warning source.
7191 @deffn Command {str9xpec options_read} num
7192 Read str9 option bytes.
7195 @deffn Command {str9xpec options_write} num
7196 Write str9 option bytes.
7199 @deffn Command {str9xpec unlock} num
7205 @deffn {Flash Driver} swm050
7207 All members of the swm050 microcontroller family from Foshan Synwit Tech.
7210 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
7213 One swm050-specific command is defined:
7215 @deffn Command {swm050 mass_erase} bank_id
7216 Erases the entire flash bank.
7222 @deffn {Flash Driver} tms470
7223 Most members of the TMS470 microcontroller family from Texas Instruments
7224 include internal flash and use ARM7TDMI cores.
7225 This driver doesn't require the chip and bus width to be specified.
7227 Some tms470-specific commands are defined:
7229 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
7230 Saves programming keys in a register, to enable flash erase and write commands.
7233 @deffn Command {tms470 osc_mhz} clock_mhz
7234 Reports the clock speed, which is used to calculate timings.
7237 @deffn Command {tms470 plldis} (0|1)
7238 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
7243 @deffn {Flash Driver} w600
7244 W60x series Wi-Fi SoC from WinnerMicro
7245 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
7246 The @var{w600} driver uses the @var{target} parameter to select the
7247 correct bank config.
7250 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
7254 @deffn {Flash Driver} xmc1xxx
7255 All members of the XMC1xxx microcontroller family from Infineon.
7256 This driver does not require the chip and bus width to be specified.
7259 @deffn {Flash Driver} xmc4xxx
7260 All members of the XMC4xxx microcontroller family from Infineon.
7261 This driver does not require the chip and bus width to be specified.
7263 Some xmc4xxx-specific commands are defined:
7265 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
7266 Saves flash protection passwords which are used to lock the user flash
7269 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
7270 Removes Flash write protection from the selected user bank
7275 @section NAND Flash Commands
7278 Compared to NOR or SPI flash, NAND devices are inexpensive
7279 and high density. Today's NAND chips, and multi-chip modules,
7280 commonly hold multiple GigaBytes of data.
7282 NAND chips consist of a number of ``erase blocks'' of a given
7283 size (such as 128 KBytes), each of which is divided into a
7284 number of pages (of perhaps 512 or 2048 bytes each). Each
7285 page of a NAND flash has an ``out of band'' (OOB) area to hold
7286 Error Correcting Code (ECC) and other metadata, usually 16 bytes
7287 of OOB for every 512 bytes of page data.
7289 One key characteristic of NAND flash is that its error rate
7290 is higher than that of NOR flash. In normal operation, that
7291 ECC is used to correct and detect errors. However, NAND
7292 blocks can also wear out and become unusable; those blocks
7293 are then marked "bad". NAND chips are even shipped from the
7294 manufacturer with a few bad blocks. The highest density chips
7295 use a technology (MLC) that wears out more quickly, so ECC
7296 support is increasingly important as a way to detect blocks
7297 that have begun to fail, and help to preserve data integrity
7298 with techniques such as wear leveling.
7300 Software is used to manage the ECC. Some controllers don't
7301 support ECC directly; in those cases, software ECC is used.
7302 Other controllers speed up the ECC calculations with hardware.
7303 Single-bit error correction hardware is routine. Controllers
7304 geared for newer MLC chips may correct 4 or more errors for
7305 every 512 bytes of data.
7307 You will need to make sure that any data you write using
7308 OpenOCD includes the appropriate kind of ECC. For example,
7309 that may mean passing the @code{oob_softecc} flag when
7310 writing NAND data, or ensuring that the correct hardware
7313 The basic steps for using NAND devices include:
7315 @item Declare via the command @command{nand device}
7316 @* Do this in a board-specific configuration file,
7317 passing parameters as needed by the controller.
7318 @item Configure each device using @command{nand probe}.
7319 @* Do this only after the associated target is set up,
7320 such as in its reset-init script or in procures defined
7321 to access that device.
7322 @item Operate on the flash via @command{nand subcommand}
7323 @* Often commands to manipulate the flash are typed by a human, or run
7324 via a script in some automated way. Common task include writing a
7325 boot loader, operating system, or other data needed to initialize or
7329 @b{NOTE:} At the time this text was written, the largest NAND
7330 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
7331 This is because the variables used to hold offsets and lengths
7332 are only 32 bits wide.
7333 (Larger chips may work in some cases, unless an offset or length
7334 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
7335 Some larger devices will work, since they are actually multi-chip
7336 modules with two smaller chips and individual chipselect lines.
7338 @anchor{nandconfiguration}
7339 @subsection NAND Configuration Commands
7340 @cindex NAND configuration
7342 NAND chips must be declared in configuration scripts,
7343 plus some additional configuration that's done after
7344 OpenOCD has initialized.
7346 @deffn {Config Command} {nand device} name driver target [configparams...]
7347 Declares a NAND device, which can be read and written to
7348 after it has been configured through @command{nand probe}.
7349 In OpenOCD, devices are single chips; this is unlike some
7350 operating systems, which may manage multiple chips as if
7351 they were a single (larger) device.
7352 In some cases, configuring a device will activate extra
7353 commands; see the controller-specific documentation.
7355 @b{NOTE:} This command is not available after OpenOCD
7356 initialization has completed. Use it in board specific
7357 configuration files, not interactively.
7360 @item @var{name} ... may be used to reference the NAND bank
7361 in most other NAND commands. A number is also available.
7362 @item @var{driver} ... identifies the NAND controller driver
7363 associated with the NAND device being declared.
7364 @xref{nanddriverlist,,NAND Driver List}.
7365 @item @var{target} ... names the target used when issuing
7366 commands to the NAND controller.
7367 @comment Actually, it's currently a controller-specific parameter...
7368 @item @var{configparams} ... controllers may support, or require,
7369 additional parameters. See the controller-specific documentation
7370 for more information.
7374 @deffn Command {nand list}
7375 Prints a summary of each device declared
7376 using @command{nand device}, numbered from zero.
7377 Note that un-probed devices show no details.
7380 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7381 blocksize: 131072, blocks: 8192
7382 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7383 blocksize: 131072, blocks: 8192
7388 @deffn Command {nand probe} num
7389 Probes the specified device to determine key characteristics
7390 like its page and block sizes, and how many blocks it has.
7391 The @var{num} parameter is the value shown by @command{nand list}.
7392 You must (successfully) probe a device before you can use
7393 it with most other NAND commands.
7396 @subsection Erasing, Reading, Writing to NAND Flash
7398 @deffn Command {nand dump} num filename offset length [oob_option]
7399 @cindex NAND reading
7400 Reads binary data from the NAND device and writes it to the file,
7401 starting at the specified offset.
7402 The @var{num} parameter is the value shown by @command{nand list}.
7404 Use a complete path name for @var{filename}, so you don't depend
7405 on the directory used to start the OpenOCD server.
7407 The @var{offset} and @var{length} must be exact multiples of the
7408 device's page size. They describe a data region; the OOB data
7409 associated with each such page may also be accessed.
7411 @b{NOTE:} At the time this text was written, no error correction
7412 was done on the data that's read, unless raw access was disabled
7413 and the underlying NAND controller driver had a @code{read_page}
7414 method which handled that error correction.
7416 By default, only page data is saved to the specified file.
7417 Use an @var{oob_option} parameter to save OOB data:
7419 @item no oob_* parameter
7420 @*Output file holds only page data; OOB is discarded.
7421 @item @code{oob_raw}
7422 @*Output file interleaves page data and OOB data;
7423 the file will be longer than "length" by the size of the
7424 spare areas associated with each data page.
7425 Note that this kind of "raw" access is different from
7426 what's implied by @command{nand raw_access}, which just
7427 controls whether a hardware-aware access method is used.
7428 @item @code{oob_only}
7429 @*Output file has only raw OOB data, and will
7430 be smaller than "length" since it will contain only the
7431 spare areas associated with each data page.
7435 @deffn Command {nand erase} num [offset length]
7436 @cindex NAND erasing
7437 @cindex NAND programming
7438 Erases blocks on the specified NAND device, starting at the
7439 specified @var{offset} and continuing for @var{length} bytes.
7440 Both of those values must be exact multiples of the device's
7441 block size, and the region they specify must fit entirely in the chip.
7442 If those parameters are not specified,
7443 the whole NAND chip will be erased.
7444 The @var{num} parameter is the value shown by @command{nand list}.
7446 @b{NOTE:} This command will try to erase bad blocks, when told
7447 to do so, which will probably invalidate the manufacturer's bad
7449 For the remainder of the current server session, @command{nand info}
7450 will still report that the block ``is'' bad.
7453 @deffn Command {nand write} num filename offset [option...]
7454 @cindex NAND writing
7455 @cindex NAND programming
7456 Writes binary data from the file into the specified NAND device,
7457 starting at the specified offset. Those pages should already
7458 have been erased; you can't change zero bits to one bits.
7459 The @var{num} parameter is the value shown by @command{nand list}.
7461 Use a complete path name for @var{filename}, so you don't depend
7462 on the directory used to start the OpenOCD server.
7464 The @var{offset} must be an exact multiple of the device's page size.
7465 All data in the file will be written, assuming it doesn't run
7466 past the end of the device.
7467 Only full pages are written, and any extra space in the last
7468 page will be filled with 0xff bytes. (That includes OOB data,
7469 if that's being written.)
7471 @b{NOTE:} At the time this text was written, bad blocks are
7472 ignored. That is, this routine will not skip bad blocks,
7473 but will instead try to write them. This can cause problems.
7475 Provide at most one @var{option} parameter. With some
7476 NAND drivers, the meanings of these parameters may change
7477 if @command{nand raw_access} was used to disable hardware ECC.
7479 @item no oob_* parameter
7480 @*File has only page data, which is written.
7481 If raw access is in use, the OOB area will not be written.
7482 Otherwise, if the underlying NAND controller driver has
7483 a @code{write_page} routine, that routine may write the OOB
7484 with hardware-computed ECC data.
7485 @item @code{oob_only}
7486 @*File has only raw OOB data, which is written to the OOB area.
7487 Each page's data area stays untouched. @i{This can be a dangerous
7488 option}, since it can invalidate the ECC data.
7489 You may need to force raw access to use this mode.
7490 @item @code{oob_raw}
7491 @*File interleaves data and OOB data, both of which are written
7492 If raw access is enabled, the data is written first, then the
7494 Otherwise, if the underlying NAND controller driver has
7495 a @code{write_page} routine, that routine may modify the OOB
7496 before it's written, to include hardware-computed ECC data.
7497 @item @code{oob_softecc}
7498 @*File has only page data, which is written.
7499 The OOB area is filled with 0xff, except for a standard 1-bit
7500 software ECC code stored in conventional locations.
7501 You might need to force raw access to use this mode, to prevent
7502 the underlying driver from applying hardware ECC.
7503 @item @code{oob_softecc_kw}
7504 @*File has only page data, which is written.
7505 The OOB area is filled with 0xff, except for a 4-bit software ECC
7506 specific to the boot ROM in Marvell Kirkwood SoCs.
7507 You might need to force raw access to use this mode, to prevent
7508 the underlying driver from applying hardware ECC.
7512 @deffn Command {nand verify} num filename offset [option...]
7513 @cindex NAND verification
7514 @cindex NAND programming
7515 Verify the binary data in the file has been programmed to the
7516 specified NAND device, starting at the specified offset.
7517 The @var{num} parameter is the value shown by @command{nand list}.
7519 Use a complete path name for @var{filename}, so you don't depend
7520 on the directory used to start the OpenOCD server.
7522 The @var{offset} must be an exact multiple of the device's page size.
7523 All data in the file will be read and compared to the contents of the
7524 flash, assuming it doesn't run past the end of the device.
7525 As with @command{nand write}, only full pages are verified, so any extra
7526 space in the last page will be filled with 0xff bytes.
7528 The same @var{options} accepted by @command{nand write},
7529 and the file will be processed similarly to produce the buffers that
7530 can be compared against the contents produced from @command{nand dump}.
7532 @b{NOTE:} This will not work when the underlying NAND controller
7533 driver's @code{write_page} routine must update the OOB with a
7534 hardware-computed ECC before the data is written. This limitation may
7535 be removed in a future release.
7538 @subsection Other NAND commands
7539 @cindex NAND other commands
7541 @deffn Command {nand check_bad_blocks} num [offset length]
7542 Checks for manufacturer bad block markers on the specified NAND
7543 device. If no parameters are provided, checks the whole
7544 device; otherwise, starts at the specified @var{offset} and
7545 continues for @var{length} bytes.
7546 Both of those values must be exact multiples of the device's
7547 block size, and the region they specify must fit entirely in the chip.
7548 The @var{num} parameter is the value shown by @command{nand list}.
7550 @b{NOTE:} Before using this command you should force raw access
7551 with @command{nand raw_access enable} to ensure that the underlying
7552 driver will not try to apply hardware ECC.
7555 @deffn Command {nand info} num
7556 The @var{num} parameter is the value shown by @command{nand list}.
7557 This prints the one-line summary from "nand list", plus for
7558 devices which have been probed this also prints any known
7559 status for each block.
7562 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
7563 Sets or clears an flag affecting how page I/O is done.
7564 The @var{num} parameter is the value shown by @command{nand list}.
7566 This flag is cleared (disabled) by default, but changing that
7567 value won't affect all NAND devices. The key factor is whether
7568 the underlying driver provides @code{read_page} or @code{write_page}
7569 methods. If it doesn't provide those methods, the setting of
7570 this flag is irrelevant; all access is effectively ``raw''.
7572 When those methods exist, they are normally used when reading
7573 data (@command{nand dump} or reading bad block markers) or
7574 writing it (@command{nand write}). However, enabling
7575 raw access (setting the flag) prevents use of those methods,
7576 bypassing hardware ECC logic.
7577 @i{This can be a dangerous option}, since writing blocks
7578 with the wrong ECC data can cause them to be marked as bad.
7581 @anchor{nanddriverlist}
7582 @subsection NAND Driver List
7583 As noted above, the @command{nand device} command allows
7584 driver-specific options and behaviors.
7585 Some controllers also activate controller-specific commands.
7587 @deffn {NAND Driver} at91sam9
7588 This driver handles the NAND controllers found on AT91SAM9 family chips from
7589 Atmel. It takes two extra parameters: address of the NAND chip;
7590 address of the ECC controller.
7592 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
7594 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
7595 @code{read_page} methods are used to utilize the ECC hardware unless they are
7596 disabled by using the @command{nand raw_access} command. There are four
7597 additional commands that are needed to fully configure the AT91SAM9 NAND
7598 controller. Two are optional; most boards use the same wiring for ALE/CLE:
7599 @deffn Command {at91sam9 cle} num addr_line
7600 Configure the address line used for latching commands. The @var{num}
7601 parameter is the value shown by @command{nand list}.
7603 @deffn Command {at91sam9 ale} num addr_line
7604 Configure the address line used for latching addresses. The @var{num}
7605 parameter is the value shown by @command{nand list}.
7608 For the next two commands, it is assumed that the pins have already been
7609 properly configured for input or output.
7610 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
7611 Configure the RDY/nBUSY input from the NAND device. The @var{num}
7612 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7613 is the base address of the PIO controller and @var{pin} is the pin number.
7615 @deffn Command {at91sam9 ce} num pio_base_addr pin
7616 Configure the chip enable input to the NAND device. The @var{num}
7617 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7618 is the base address of the PIO controller and @var{pin} is the pin number.
7622 @deffn {NAND Driver} davinci
7623 This driver handles the NAND controllers found on DaVinci family
7624 chips from Texas Instruments.
7625 It takes three extra parameters:
7626 address of the NAND chip;
7627 hardware ECC mode to use (@option{hwecc1},
7628 @option{hwecc4}, @option{hwecc4_infix});
7629 address of the AEMIF controller on this processor.
7631 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
7633 All DaVinci processors support the single-bit ECC hardware,
7634 and newer ones also support the four-bit ECC hardware.
7635 The @code{write_page} and @code{read_page} methods are used
7636 to implement those ECC modes, unless they are disabled using
7637 the @command{nand raw_access} command.
7640 @deffn {NAND Driver} lpc3180
7641 These controllers require an extra @command{nand device}
7642 parameter: the clock rate used by the controller.
7643 @deffn Command {lpc3180 select} num [mlc|slc]
7644 Configures use of the MLC or SLC controller mode.
7645 MLC implies use of hardware ECC.
7646 The @var{num} parameter is the value shown by @command{nand list}.
7649 At this writing, this driver includes @code{write_page}
7650 and @code{read_page} methods. Using @command{nand raw_access}
7651 to disable those methods will prevent use of hardware ECC
7652 in the MLC controller mode, but won't change SLC behavior.
7654 @comment current lpc3180 code won't issue 5-byte address cycles
7656 @deffn {NAND Driver} mx3
7657 This driver handles the NAND controller in i.MX31. The mxc driver
7658 should work for this chip as well.
7661 @deffn {NAND Driver} mxc
7662 This driver handles the NAND controller found in Freescale i.MX
7663 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
7664 The driver takes 3 extra arguments, chip (@option{mx27},
7665 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
7666 and optionally if bad block information should be swapped between
7667 main area and spare area (@option{biswap}), defaults to off.
7669 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
7671 @deffn Command {mxc biswap} bank_num [enable|disable]
7672 Turns on/off bad block information swapping from main area,
7673 without parameter query status.
7677 @deffn {NAND Driver} orion
7678 These controllers require an extra @command{nand device}
7679 parameter: the address of the controller.
7681 nand device orion 0xd8000000
7683 These controllers don't define any specialized commands.
7684 At this writing, their drivers don't include @code{write_page}
7685 or @code{read_page} methods, so @command{nand raw_access} won't
7686 change any behavior.
7689 @deffn {NAND Driver} s3c2410
7690 @deffnx {NAND Driver} s3c2412
7691 @deffnx {NAND Driver} s3c2440
7692 @deffnx {NAND Driver} s3c2443
7693 @deffnx {NAND Driver} s3c6400
7694 These S3C family controllers don't have any special
7695 @command{nand device} options, and don't define any
7696 specialized commands.
7697 At this writing, their drivers don't include @code{write_page}
7698 or @code{read_page} methods, so @command{nand raw_access} won't
7699 change any behavior.
7702 @node Flash Programming
7703 @chapter Flash Programming
7705 OpenOCD implements numerous ways to program the target flash, whether internal or external.
7706 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
7707 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
7709 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
7710 OpenOCD will program/verify/reset the target and optionally shutdown.
7712 The script is executed as follows and by default the following actions will be performed.
7714 @item 'init' is executed.
7715 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
7716 @item @code{flash write_image} is called to erase and write any flash using the filename given.
7717 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
7718 @item @code{verify_image} is called if @option{verify} parameter is given.
7719 @item @code{reset run} is called if @option{reset} parameter is given.
7720 @item OpenOCD is shutdown if @option{exit} parameter is given.
7723 An example of usage is given below. @xref{program}.
7726 # program and verify using elf/hex/s19. verify and reset
7727 # are optional parameters
7728 openocd -f board/stm32f3discovery.cfg \
7729 -c "program filename.elf verify reset exit"
7731 # binary files need the flash address passing
7732 openocd -f board/stm32f3discovery.cfg \
7733 -c "program filename.bin exit 0x08000000"
7736 @node PLD/FPGA Commands
7737 @chapter PLD/FPGA Commands
7741 Programmable Logic Devices (PLDs) and the more flexible
7742 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
7743 OpenOCD can support programming them.
7744 Although PLDs are generally restrictive (cells are less functional, and
7745 there are no special purpose cells for memory or computational tasks),
7746 they share the same OpenOCD infrastructure.
7747 Accordingly, both are called PLDs here.
7749 @section PLD/FPGA Configuration and Commands
7751 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
7752 OpenOCD maintains a list of PLDs available for use in various commands.
7753 Also, each such PLD requires a driver.
7755 They are referenced by the number shown by the @command{pld devices} command,
7756 and new PLDs are defined by @command{pld device driver_name}.
7758 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
7759 Defines a new PLD device, supported by driver @var{driver_name},
7760 using the TAP named @var{tap_name}.
7761 The driver may make use of any @var{driver_options} to configure its
7765 @deffn {Command} {pld devices}
7766 Lists the PLDs and their numbers.
7769 @deffn {Command} {pld load} num filename
7770 Loads the file @file{filename} into the PLD identified by @var{num}.
7771 The file format must be inferred by the driver.
7774 @section PLD/FPGA Drivers, Options, and Commands
7776 Drivers may support PLD-specific options to the @command{pld device}
7777 definition command, and may also define commands usable only with
7778 that particular type of PLD.
7780 @deffn {FPGA Driver} virtex2 [no_jstart]
7781 Virtex-II is a family of FPGAs sold by Xilinx.
7782 It supports the IEEE 1532 standard for In-System Configuration (ISC).
7784 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
7785 loading the bitstream. While required for Series2, Series3, and Series6, it
7786 breaks bitstream loading on Series7.
7788 @deffn {Command} {virtex2 read_stat} num
7789 Reads and displays the Virtex-II status register (STAT)
7794 @node General Commands
7795 @chapter General Commands
7798 The commands documented in this chapter here are common commands that
7799 you, as a human, may want to type and see the output of. Configuration type
7800 commands are documented elsewhere.
7804 @item @b{Source Of Commands}
7805 @* OpenOCD commands can occur in a configuration script (discussed
7806 elsewhere) or typed manually by a human or supplied programmatically,
7807 or via one of several TCP/IP Ports.
7809 @item @b{From the human}
7810 @* A human should interact with the telnet interface (default port: 4444)
7811 or via GDB (default port 3333).
7813 To issue commands from within a GDB session, use the @option{monitor}
7814 command, e.g. use @option{monitor poll} to issue the @option{poll}
7815 command. All output is relayed through the GDB session.
7817 @item @b{Machine Interface}
7818 The Tcl interface's intent is to be a machine interface. The default Tcl
7823 @section Server Commands
7825 @deffn {Command} exit
7826 Exits the current telnet session.
7829 @deffn {Command} help [string]
7830 With no parameters, prints help text for all commands.
7831 Otherwise, prints each helptext containing @var{string}.
7832 Not every command provides helptext.
7834 Configuration commands, and commands valid at any time, are
7835 explicitly noted in parenthesis.
7836 In most cases, no such restriction is listed; this indicates commands
7837 which are only available after the configuration stage has completed.
7840 @deffn Command sleep msec [@option{busy}]
7841 Wait for at least @var{msec} milliseconds before resuming.
7842 If @option{busy} is passed, busy-wait instead of sleeping.
7843 (This option is strongly discouraged.)
7844 Useful in connection with script files
7845 (@command{script} command and @command{target_name} configuration).
7848 @deffn Command shutdown [@option{error}]
7849 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
7850 other). If option @option{error} is used, OpenOCD will return a
7851 non-zero exit code to the parent process.
7853 Like any TCL commands, also @command{shutdown} can be redefined, e.g.:
7856 rename shutdown original_shutdown
7857 proc shutdown @{@} @{
7858 puts "This is my implementation of shutdown"
7859 # my own stuff before exit OpenOCD
7863 If user types CTRL-C or kills OpenOCD, either the command @command{shutdown}
7864 or its replacement will be automatically executed before OpenOCD exits.
7868 @deffn Command debug_level [n]
7869 @cindex message level
7870 Display debug level.
7871 If @var{n} (from 0..4) is provided, then set it to that level.
7872 This affects the kind of messages sent to the server log.
7873 Level 0 is error messages only;
7874 level 1 adds warnings;
7875 level 2 adds informational messages;
7876 level 3 adds debugging messages;
7877 and level 4 adds verbose low-level debug messages.
7878 The default is level 2, but that can be overridden on
7879 the command line along with the location of that log
7880 file (which is normally the server's standard output).
7884 @deffn Command echo [-n] message
7885 Logs a message at "user" priority.
7886 Output @var{message} to stdout.
7887 Option "-n" suppresses trailing newline.
7889 echo "Downloading kernel -- please wait"
7893 @deffn Command log_output [filename | "default"]
7894 Redirect logging to @var{filename} or set it back to default output;
7895 the default log output channel is stderr.
7898 @deffn Command add_script_search_dir [directory]
7899 Add @var{directory} to the file/script search path.
7902 @deffn Command bindto [@var{name}]
7903 Specify hostname or IPv4 address on which to listen for incoming
7904 TCP/IP connections. By default, OpenOCD will listen on the loopback
7905 interface only. If your network environment is safe, @code{bindto
7906 0.0.0.0} can be used to cover all available interfaces.
7909 @anchor{targetstatehandling}
7910 @section Target State handling
7913 @cindex target initialization
7915 In this section ``target'' refers to a CPU configured as
7916 shown earlier (@pxref{CPU Configuration}).
7917 These commands, like many, implicitly refer to
7918 a current target which is used to perform the
7919 various operations. The current target may be changed
7920 by using @command{targets} command with the name of the
7921 target which should become current.
7923 @deffn Command reg [(number|name) [(value|'force')]]
7924 Access a single register by @var{number} or by its @var{name}.
7925 The target must generally be halted before access to CPU core
7926 registers is allowed. Depending on the hardware, some other
7927 registers may be accessible while the target is running.
7929 @emph{With no arguments}:
7930 list all available registers for the current target,
7931 showing number, name, size, value, and cache status.
7932 For valid entries, a value is shown; valid entries
7933 which are also dirty (and will be written back later)
7934 are flagged as such.
7936 @emph{With number/name}: display that register's value.
7937 Use @var{force} argument to read directly from the target,
7938 bypassing any internal cache.
7940 @emph{With both number/name and value}: set register's value.
7941 Writes may be held in a writeback cache internal to OpenOCD,
7942 so that setting the value marks the register as dirty instead
7943 of immediately flushing that value. Resuming CPU execution
7944 (including by single stepping) or otherwise activating the
7945 relevant module will flush such values.
7947 Cores may have surprisingly many registers in their
7948 Debug and trace infrastructure:
7953 (0) r0 (/32): 0x0000D3C2 (dirty)
7954 (1) r1 (/32): 0xFD61F31C
7957 (164) ETM_contextid_comparator_mask (/32)
7962 @deffn Command halt [ms]
7963 @deffnx Command wait_halt [ms]
7964 The @command{halt} command first sends a halt request to the target,
7965 which @command{wait_halt} doesn't.
7966 Otherwise these behave the same: wait up to @var{ms} milliseconds,
7967 or 5 seconds if there is no parameter, for the target to halt
7968 (and enter debug mode).
7969 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
7972 On ARM cores, software using the @emph{wait for interrupt} operation
7973 often blocks the JTAG access needed by a @command{halt} command.
7974 This is because that operation also puts the core into a low
7975 power mode by gating the core clock;
7976 but the core clock is needed to detect JTAG clock transitions.
7978 One partial workaround uses adaptive clocking: when the core is
7979 interrupted the operation completes, then JTAG clocks are accepted
7980 at least until the interrupt handler completes.
7981 However, this workaround is often unusable since the processor, board,
7982 and JTAG adapter must all support adaptive JTAG clocking.
7983 Also, it can't work until an interrupt is issued.
7985 A more complete workaround is to not use that operation while you
7986 work with a JTAG debugger.
7987 Tasking environments generally have idle loops where the body is the
7988 @emph{wait for interrupt} operation.
7989 (On older cores, it is a coprocessor action;
7990 newer cores have a @option{wfi} instruction.)
7991 Such loops can just remove that operation, at the cost of higher
7992 power consumption (because the CPU is needlessly clocked).
7997 @deffn Command resume [address]
7998 Resume the target at its current code position,
7999 or the optional @var{address} if it is provided.
8000 OpenOCD will wait 5 seconds for the target to resume.
8003 @deffn Command step [address]
8004 Single-step the target at its current code position,
8005 or the optional @var{address} if it is provided.
8008 @anchor{resetcommand}
8009 @deffn Command reset
8010 @deffnx Command {reset run}
8011 @deffnx Command {reset halt}
8012 @deffnx Command {reset init}
8013 Perform as hard a reset as possible, using SRST if possible.
8014 @emph{All defined targets will be reset, and target
8015 events will fire during the reset sequence.}
8017 The optional parameter specifies what should
8018 happen after the reset.
8019 If there is no parameter, a @command{reset run} is executed.
8020 The other options will not work on all systems.
8021 @xref{Reset Configuration}.
8024 @item @b{run} Let the target run
8025 @item @b{halt} Immediately halt the target
8026 @item @b{init} Immediately halt the target, and execute the reset-init script
8030 @deffn Command soft_reset_halt
8031 Requesting target halt and executing a soft reset. This is often used
8032 when a target cannot be reset and halted. The target, after reset is
8033 released begins to execute code. OpenOCD attempts to stop the CPU and
8034 then sets the program counter back to the reset vector. Unfortunately
8035 the code that was executed may have left the hardware in an unknown
8039 @deffn Command {adapter assert} [signal [assert|deassert signal]]
8040 @deffnx Command {adapter deassert} [signal [assert|deassert signal]]
8041 Set values of reset signals.
8042 Without parameters returns current status of the signals.
8043 The @var{signal} parameter values may be
8044 @option{srst}, indicating that srst signal is to be asserted or deasserted,
8045 @option{trst}, indicating that trst signal is to be asserted or deasserted.
8047 The @command{reset_config} command should already have been used
8048 to configure how the board and the adapter treat these two
8049 signals, and to say if either signal is even present.
8050 @xref{Reset Configuration}.
8051 Trying to assert a signal that is not present triggers an error.
8052 If a signal is present on the adapter and not specified in the command,
8053 the signal will not be modified.
8056 TRST is specially handled.
8057 It actually signifies JTAG's @sc{reset} state.
8058 So if the board doesn't support the optional TRST signal,
8059 or it doesn't support it along with the specified SRST value,
8060 JTAG reset is triggered with TMS and TCK signals
8061 instead of the TRST signal.
8062 And no matter how that JTAG reset is triggered, once
8063 the scan chain enters @sc{reset} with TRST inactive,
8064 TAP @code{post-reset} events are delivered to all TAPs
8065 with handlers for that event.
8069 @section I/O Utilities
8071 These commands are available when
8072 OpenOCD is built with @option{--enable-ioutil}.
8073 They are mainly useful on embedded targets,
8075 Hosts with operating systems have complementary tools.
8077 @emph{Note:} there are several more such commands.
8079 @deffn Command append_file filename [string]*
8080 Appends the @var{string} parameters to
8081 the text file @file{filename}.
8082 Each string except the last one is followed by one space.
8083 The last string is followed by a newline.
8086 @deffn Command cat filename
8087 Reads and displays the text file @file{filename}.
8090 @deffn Command cp src_filename dest_filename
8091 Copies contents from the file @file{src_filename}
8092 into @file{dest_filename}.
8096 @emph{No description provided.}
8100 @emph{No description provided.}
8104 @emph{No description provided.}
8107 @deffn Command meminfo
8108 Display available RAM memory on OpenOCD host.
8109 Used in OpenOCD regression testing scripts.
8113 @emph{No description provided.}
8117 @emph{No description provided.}
8120 @deffn Command rm filename
8121 @c "rm" has both normal and Jim-level versions??
8122 Unlinks the file @file{filename}.
8125 @deffn Command trunc filename
8126 Removes all data in the file @file{filename}.
8129 @anchor{memoryaccess}
8130 @section Memory access commands
8131 @cindex memory access
8133 These commands allow accesses of a specific size to the memory
8134 system. Often these are used to configure the current target in some
8135 special way. For example - one may need to write certain values to the
8136 SDRAM controller to enable SDRAM.
8139 @item Use the @command{targets} (plural) command
8140 to change the current target.
8141 @item In system level scripts these commands are deprecated.
8142 Please use their TARGET object siblings to avoid making assumptions
8143 about what TAP is the current target, or about MMU configuration.
8146 @deffn Command mdd [phys] addr [count]
8147 @deffnx Command mdw [phys] addr [count]
8148 @deffnx Command mdh [phys] addr [count]
8149 @deffnx Command mdb [phys] addr [count]
8150 Display contents of address @var{addr}, as
8151 64-bit doublewords (@command{mdd}),
8152 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8153 or 8-bit bytes (@command{mdb}).
8154 When the current target has an MMU which is present and active,
8155 @var{addr} is interpreted as a virtual address.
8156 Otherwise, or if the optional @var{phys} flag is specified,
8157 @var{addr} is interpreted as a physical address.
8158 If @var{count} is specified, displays that many units.
8159 (If you want to manipulate the data instead of displaying it,
8160 see the @code{mem2array} primitives.)
8163 @deffn Command mwd [phys] addr doubleword [count]
8164 @deffnx Command mww [phys] addr word [count]
8165 @deffnx Command mwh [phys] addr halfword [count]
8166 @deffnx Command mwb [phys] addr byte [count]
8167 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
8168 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
8169 at the specified address @var{addr}.
8170 When the current target has an MMU which is present and active,
8171 @var{addr} is interpreted as a virtual address.
8172 Otherwise, or if the optional @var{phys} flag is specified,
8173 @var{addr} is interpreted as a physical address.
8174 If @var{count} is specified, fills that many units of consecutive address.
8177 @anchor{imageaccess}
8178 @section Image loading commands
8179 @cindex image loading
8180 @cindex image dumping
8182 @deffn Command {dump_image} filename address size
8183 Dump @var{size} bytes of target memory starting at @var{address} to the
8184 binary file named @var{filename}.
8187 @deffn Command {fast_load}
8188 Loads an image stored in memory by @command{fast_load_image} to the
8189 current target. Must be preceded by fast_load_image.
8192 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
8193 Normally you should be using @command{load_image} or GDB load. However, for
8194 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
8195 host), storing the image in memory and uploading the image to the target
8196 can be a way to upload e.g. multiple debug sessions when the binary does not change.
8197 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
8198 memory, i.e. does not affect target. This approach is also useful when profiling
8199 target programming performance as I/O and target programming can easily be profiled
8203 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
8204 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
8205 The file format may optionally be specified
8206 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
8207 In addition the following arguments may be specified:
8208 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
8209 @var{max_length} - maximum number of bytes to load.
8211 proc load_image_bin @{fname foffset address length @} @{
8212 # Load data from fname filename at foffset offset to
8213 # target at address. Load at most length bytes.
8214 load_image $fname [expr $address - $foffset] bin \
8220 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
8221 Displays image section sizes and addresses
8222 as if @var{filename} were loaded into target memory
8223 starting at @var{address} (defaults to zero).
8224 The file format may optionally be specified
8225 (@option{bin}, @option{ihex}, or @option{elf})
8228 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
8229 Verify @var{filename} against target memory starting at @var{address}.
8230 The file format may optionally be specified
8231 (@option{bin}, @option{ihex}, or @option{elf})
8232 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
8235 @deffn Command {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
8236 Verify @var{filename} against target memory starting at @var{address}.
8237 The file format may optionally be specified
8238 (@option{bin}, @option{ihex}, or @option{elf})
8239 This perform a comparison using a CRC checksum only
8243 @section Breakpoint and Watchpoint commands
8247 CPUs often make debug modules accessible through JTAG, with
8248 hardware support for a handful of code breakpoints and data
8250 In addition, CPUs almost always support software breakpoints.
8252 @deffn Command {bp} [address len [@option{hw}]]
8253 With no parameters, lists all active breakpoints.
8254 Else sets a breakpoint on code execution starting
8255 at @var{address} for @var{length} bytes.
8256 This is a software breakpoint, unless @option{hw} is specified
8257 in which case it will be a hardware breakpoint.
8259 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
8260 for similar mechanisms that do not consume hardware breakpoints.)
8263 @deffn Command {rbp} @option{all} | address
8264 Remove the breakpoint at @var{address} or all breakpoints.
8267 @deffn Command {rwp} address
8268 Remove data watchpoint on @var{address}
8271 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
8272 With no parameters, lists all active watchpoints.
8273 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
8274 The watch point is an "access" watchpoint unless
8275 the @option{r} or @option{w} parameter is provided,
8276 defining it as respectively a read or write watchpoint.
8277 If a @var{value} is provided, that value is used when determining if
8278 the watchpoint should trigger. The value may be first be masked
8279 using @var{mask} to mark ``don't care'' fields.
8282 @section Misc Commands
8285 @deffn Command {profile} seconds filename [start end]
8286 Profiling samples the CPU's program counter as quickly as possible,
8287 which is useful for non-intrusive stochastic profiling.
8288 Saves up to 10000 samples in @file{filename} using ``gmon.out''
8289 format. Optional @option{start} and @option{end} parameters allow to
8290 limit the address range.
8293 @deffn Command {version}
8294 Displays a string identifying the version of this OpenOCD server.
8297 @deffn Command {virt2phys} virtual_address
8298 Requests the current target to map the specified @var{virtual_address}
8299 to its corresponding physical address, and displays the result.
8302 @node Architecture and Core Commands
8303 @chapter Architecture and Core Commands
8304 @cindex Architecture Specific Commands
8305 @cindex Core Specific Commands
8307 Most CPUs have specialized JTAG operations to support debugging.
8308 OpenOCD packages most such operations in its standard command framework.
8309 Some of those operations don't fit well in that framework, so they are
8310 exposed here as architecture or implementation (core) specific commands.
8312 @anchor{armhardwaretracing}
8313 @section ARM Hardware Tracing
8318 CPUs based on ARM cores may include standard tracing interfaces,
8319 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
8320 address and data bus trace records to a ``Trace Port''.
8324 Development-oriented boards will sometimes provide a high speed
8325 trace connector for collecting that data, when the particular CPU
8326 supports such an interface.
8327 (The standard connector is a 38-pin Mictor, with both JTAG
8328 and trace port support.)
8329 Those trace connectors are supported by higher end JTAG adapters
8330 and some logic analyzer modules; frequently those modules can
8331 buffer several megabytes of trace data.
8332 Configuring an ETM coupled to such an external trace port belongs
8333 in the board-specific configuration file.
8335 If the CPU doesn't provide an external interface, it probably
8336 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
8337 dedicated SRAM. 4KBytes is one common ETB size.
8338 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
8339 (target) configuration file, since it works the same on all boards.
8342 ETM support in OpenOCD doesn't seem to be widely used yet.
8345 ETM support may be buggy, and at least some @command{etm config}
8346 parameters should be detected by asking the ETM for them.
8348 ETM trigger events could also implement a kind of complex
8349 hardware breakpoint, much more powerful than the simple
8350 watchpoint hardware exported by EmbeddedICE modules.
8351 @emph{Such breakpoints can be triggered even when using the
8352 dummy trace port driver}.
8354 It seems like a GDB hookup should be possible,
8355 as well as tracing only during specific states
8356 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
8358 There should be GUI tools to manipulate saved trace data and help
8359 analyse it in conjunction with the source code.
8360 It's unclear how much of a common interface is shared
8361 with the current XScale trace support, or should be
8362 shared with eventual Nexus-style trace module support.
8364 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
8365 for ETM modules is available. The code should be able to
8366 work with some newer cores; but not all of them support
8367 this original style of JTAG access.
8370 @subsection ETM Configuration
8371 ETM setup is coupled with the trace port driver configuration.
8373 @deffn {Config Command} {etm config} target width mode clocking driver
8374 Declares the ETM associated with @var{target}, and associates it
8375 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
8377 Several of the parameters must reflect the trace port capabilities,
8378 which are a function of silicon capabilities (exposed later
8379 using @command{etm info}) and of what hardware is connected to
8380 that port (such as an external pod, or ETB).
8381 The @var{width} must be either 4, 8, or 16,
8382 except with ETMv3.0 and newer modules which may also
8383 support 1, 2, 24, 32, 48, and 64 bit widths.
8384 (With those versions, @command{etm info} also shows whether
8385 the selected port width and mode are supported.)
8387 The @var{mode} must be @option{normal}, @option{multiplexed},
8388 or @option{demultiplexed}.
8389 The @var{clocking} must be @option{half} or @option{full}.
8392 With ETMv3.0 and newer, the bits set with the @var{mode} and
8393 @var{clocking} parameters both control the mode.
8394 This modified mode does not map to the values supported by
8395 previous ETM modules, so this syntax is subject to change.
8399 You can see the ETM registers using the @command{reg} command.
8400 Not all possible registers are present in every ETM.
8401 Most of the registers are write-only, and are used to configure
8402 what CPU activities are traced.
8406 @deffn Command {etm info}
8407 Displays information about the current target's ETM.
8408 This includes resource counts from the @code{ETM_CONFIG} register,
8409 as well as silicon capabilities (except on rather old modules).
8410 from the @code{ETM_SYS_CONFIG} register.
8413 @deffn Command {etm status}
8414 Displays status of the current target's ETM and trace port driver:
8415 is the ETM idle, or is it collecting data?
8416 Did trace data overflow?
8420 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
8421 Displays what data that ETM will collect.
8422 If arguments are provided, first configures that data.
8423 When the configuration changes, tracing is stopped
8424 and any buffered trace data is invalidated.
8427 @item @var{type} ... describing how data accesses are traced,
8428 when they pass any ViewData filtering that was set up.
8430 @option{none} (save nothing),
8431 @option{data} (save data),
8432 @option{address} (save addresses),
8433 @option{all} (save data and addresses)
8434 @item @var{context_id_bits} ... 0, 8, 16, or 32
8435 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
8436 cycle-accurate instruction tracing.
8437 Before ETMv3, enabling this causes much extra data to be recorded.
8438 @item @var{branch_output} ... @option{enable} or @option{disable}.
8439 Disable this unless you need to try reconstructing the instruction
8440 trace stream without an image of the code.
8444 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
8445 Displays whether ETM triggering debug entry (like a breakpoint) is
8446 enabled or disabled, after optionally modifying that configuration.
8447 The default behaviour is @option{disable}.
8448 Any change takes effect after the next @command{etm start}.
8450 By using script commands to configure ETM registers, you can make the
8451 processor enter debug state automatically when certain conditions,
8452 more complex than supported by the breakpoint hardware, happen.
8455 @subsection ETM Trace Operation
8457 After setting up the ETM, you can use it to collect data.
8458 That data can be exported to files for later analysis.
8459 It can also be parsed with OpenOCD, for basic sanity checking.
8461 To configure what is being traced, you will need to write
8462 various trace registers using @command{reg ETM_*} commands.
8463 For the definitions of these registers, read ARM publication
8464 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
8465 Be aware that most of the relevant registers are write-only,
8466 and that ETM resources are limited. There are only a handful
8467 of address comparators, data comparators, counters, and so on.
8469 Examples of scenarios you might arrange to trace include:
8472 @item Code flow within a function, @emph{excluding} subroutines
8473 it calls. Use address range comparators to enable tracing
8474 for instruction access within that function's body.
8475 @item Code flow within a function, @emph{including} subroutines
8476 it calls. Use the sequencer and address comparators to activate
8477 tracing on an ``entered function'' state, then deactivate it by
8478 exiting that state when the function's exit code is invoked.
8479 @item Code flow starting at the fifth invocation of a function,
8480 combining one of the above models with a counter.
8481 @item CPU data accesses to the registers for a particular device,
8482 using address range comparators and the ViewData logic.
8483 @item Such data accesses only during IRQ handling, combining the above
8484 model with sequencer triggers which on entry and exit to the IRQ handler.
8485 @item @emph{... more}
8488 At this writing, September 2009, there are no Tcl utility
8489 procedures to help set up any common tracing scenarios.
8491 @deffn Command {etm analyze}
8492 Reads trace data into memory, if it wasn't already present.
8493 Decodes and prints the data that was collected.
8496 @deffn Command {etm dump} filename
8497 Stores the captured trace data in @file{filename}.
8500 @deffn Command {etm image} filename [base_address] [type]
8501 Opens an image file.
8504 @deffn Command {etm load} filename
8505 Loads captured trace data from @file{filename}.
8508 @deffn Command {etm start}
8509 Starts trace data collection.
8512 @deffn Command {etm stop}
8513 Stops trace data collection.
8516 @anchor{traceportdrivers}
8517 @subsection Trace Port Drivers
8519 To use an ETM trace port it must be associated with a driver.
8521 @deffn {Trace Port Driver} dummy
8522 Use the @option{dummy} driver if you are configuring an ETM that's
8523 not connected to anything (on-chip ETB or off-chip trace connector).
8524 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
8525 any trace data collection.}
8526 @deffn {Config Command} {etm_dummy config} target
8527 Associates the ETM for @var{target} with a dummy driver.
8531 @deffn {Trace Port Driver} etb
8532 Use the @option{etb} driver if you are configuring an ETM
8533 to use on-chip ETB memory.
8534 @deffn {Config Command} {etb config} target etb_tap
8535 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
8536 You can see the ETB registers using the @command{reg} command.
8538 @deffn Command {etb trigger_percent} [percent]
8539 This displays, or optionally changes, ETB behavior after the
8540 ETM's configured @emph{trigger} event fires.
8541 It controls how much more trace data is saved after the (single)
8542 trace trigger becomes active.
8545 @item The default corresponds to @emph{trace around} usage,
8546 recording 50 percent data before the event and the rest
8548 @item The minimum value of @var{percent} is 2 percent,
8549 recording almost exclusively data before the trigger.
8550 Such extreme @emph{trace before} usage can help figure out
8551 what caused that event to happen.
8552 @item The maximum value of @var{percent} is 100 percent,
8553 recording data almost exclusively after the event.
8554 This extreme @emph{trace after} usage might help sort out
8555 how the event caused trouble.
8557 @c REVISIT allow "break" too -- enter debug mode.
8562 @deffn {Trace Port Driver} oocd_trace
8563 This driver isn't available unless OpenOCD was explicitly configured
8564 with the @option{--enable-oocd_trace} option. You probably don't want
8565 to configure it unless you've built the appropriate prototype hardware;
8566 it's @emph{proof-of-concept} software.
8568 Use the @option{oocd_trace} driver if you are configuring an ETM that's
8569 connected to an off-chip trace connector.
8571 @deffn {Config Command} {oocd_trace config} target tty
8572 Associates the ETM for @var{target} with a trace driver which
8573 collects data through the serial port @var{tty}.
8576 @deffn Command {oocd_trace resync}
8577 Re-synchronizes with the capture clock.
8580 @deffn Command {oocd_trace status}
8581 Reports whether the capture clock is locked or not.
8585 @anchor{armcrosstrigger}
8586 @section ARM Cross-Trigger Interface
8589 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
8590 that connects event sources like tracing components or CPU cores with each
8591 other through a common trigger matrix (CTM). For ARMv8 architecture, a
8592 CTI is mandatory for core run control and each core has an individual
8593 CTI instance attached to it. OpenOCD has limited support for CTI using
8594 the @emph{cti} group of commands.
8596 @deffn Command {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
8597 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
8598 @var{apn}. The @var{base_address} must match the base address of the CTI
8599 on the respective MEM-AP. All arguments are mandatory. This creates a
8600 new command @command{$cti_name} which is used for various purposes
8601 including additional configuration.
8604 @deffn Command {$cti_name enable} @option{on|off}
8605 Enable (@option{on}) or disable (@option{off}) the CTI.
8608 @deffn Command {$cti_name dump}
8609 Displays a register dump of the CTI.
8612 @deffn Command {$cti_name write } @var{reg_name} @var{value}
8613 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
8616 @deffn Command {$cti_name read} @var{reg_name}
8617 Print the value read from the CTI register with the symbolic name @var{reg_name}.
8620 @deffn Command {$cti_name ack} @var{event}
8621 Acknowledge a CTI @var{event}.
8624 @deffn Command {$cti_name channel} @var{channel_number} @var{operation}
8625 Perform a specific channel operation, the possible operations are:
8626 gate, ungate, set, clear and pulse
8629 @deffn Command {$cti_name testmode} @option{on|off}
8630 Enable (@option{on}) or disable (@option{off}) the integration test mode
8634 @deffn Command {cti names}
8635 Prints a list of names of all CTI objects created. This command is mainly
8636 useful in TCL scripting.
8639 @section Generic ARM
8642 These commands should be available on all ARM processors.
8643 They are available in addition to other core-specific
8644 commands that may be available.
8646 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
8647 Displays the core_state, optionally changing it to process
8648 either @option{arm} or @option{thumb} instructions.
8649 The target may later be resumed in the currently set core_state.
8650 (Processors may also support the Jazelle state, but
8651 that is not currently supported in OpenOCD.)
8654 @deffn Command {arm disassemble} address [count [@option{thumb}]]
8656 Disassembles @var{count} instructions starting at @var{address}.
8657 If @var{count} is not specified, a single instruction is disassembled.
8658 If @option{thumb} is specified, or the low bit of the address is set,
8659 Thumb2 (mixed 16/32-bit) instructions are used;
8660 else ARM (32-bit) instructions are used.
8661 (Processors may also support the Jazelle state, but
8662 those instructions are not currently understood by OpenOCD.)
8664 Note that all Thumb instructions are Thumb2 instructions,
8665 so older processors (without Thumb2 support) will still
8666 see correct disassembly of Thumb code.
8667 Also, ThumbEE opcodes are the same as Thumb2,
8668 with a handful of exceptions.
8669 ThumbEE disassembly currently has no explicit support.
8672 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
8673 Write @var{value} to a coprocessor @var{pX} register
8674 passing parameters @var{CRn},
8675 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8676 and using the MCR instruction.
8677 (Parameter sequence matches the ARM instruction, but omits
8681 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
8682 Read a coprocessor @var{pX} register passing parameters @var{CRn},
8683 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8684 and the MRC instruction.
8685 Returns the result so it can be manipulated by Jim scripts.
8686 (Parameter sequence matches the ARM instruction, but omits
8690 @deffn Command {arm reg}
8691 Display a table of all banked core registers, fetching the current value from every
8692 core mode if necessary.
8695 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
8696 @cindex ARM semihosting
8697 Display status of semihosting, after optionally changing that status.
8699 Semihosting allows for code executing on an ARM target to use the
8700 I/O facilities on the host computer i.e. the system where OpenOCD
8701 is running. The target application must be linked against a library
8702 implementing the ARM semihosting convention that forwards operation
8703 requests by using a special SVC instruction that is trapped at the
8704 Supervisor Call vector by OpenOCD.
8707 @deffn Command {arm semihosting_cmdline} [@option{enable}|@option{disable}]
8708 @cindex ARM semihosting
8709 Set the command line to be passed to the debugger.
8712 arm semihosting_cmdline argv0 argv1 argv2 ...
8715 This option lets one set the command line arguments to be passed to
8716 the program. The first argument (argv0) is the program name in a
8717 standard C environment (argv[0]). Depending on the program (not much
8718 programs look at argv[0]), argv0 is ignored and can be any string.
8721 @deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
8722 @cindex ARM semihosting
8723 Display status of semihosting fileio, after optionally changing that
8726 Enabling this option forwards semihosting I/O to GDB process using the
8727 File-I/O remote protocol extension. This is especially useful for
8728 interacting with remote files or displaying console messages in the
8732 @deffn Command {arm semihosting_resexit} [@option{enable}|@option{disable}]
8733 @cindex ARM semihosting
8734 Enable resumable SEMIHOSTING_SYS_EXIT.
8736 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
8737 things are simple, the openocd process calls exit() and passes
8738 the value returned by the target.
8740 When SEMIHOSTING_SYS_EXIT is called during a debug session,
8741 by default execution returns to the debugger, leaving the
8742 debugger in a HALT state, similar to the state entered when
8743 encountering a break.
8745 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
8746 return normally, as any semihosting call, and do not break
8748 The standard allows this to happen, but the condition
8749 to trigger it is a bit obscure ("by performing an RDI_Execute
8750 request or equivalent").
8752 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
8753 this option (default: disabled).
8756 @section ARMv4 and ARMv5 Architecture
8760 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
8761 and introduced core parts of the instruction set in use today.
8762 That includes the Thumb instruction set, introduced in the ARMv4T
8765 @subsection ARM7 and ARM9 specific commands
8769 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
8770 ARM9TDMI, ARM920T or ARM926EJ-S.
8771 They are available in addition to the ARM commands,
8772 and any other core-specific commands that may be available.
8774 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
8775 Displays the value of the flag controlling use of the
8776 EmbeddedIce DBGRQ signal to force entry into debug mode,
8777 instead of breakpoints.
8778 If a boolean parameter is provided, first assigns that flag.
8781 safe for all but ARM7TDMI-S cores (like NXP LPC).
8782 This feature is enabled by default on most ARM9 cores,
8783 including ARM9TDMI, ARM920T, and ARM926EJ-S.
8786 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
8788 Displays the value of the flag controlling use of the debug communications
8789 channel (DCC) to write larger (>128 byte) amounts of memory.
8790 If a boolean parameter is provided, first assigns that flag.
8792 DCC downloads offer a huge speed increase, but might be
8793 unsafe, especially with targets running at very low speeds. This command was introduced
8794 with OpenOCD rev. 60, and requires a few bytes of working area.
8797 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
8798 Displays the value of the flag controlling use of memory writes and reads
8799 that don't check completion of the operation.
8800 If a boolean parameter is provided, first assigns that flag.
8802 This provides a huge speed increase, especially with USB JTAG
8803 cables (FT2232), but might be unsafe if used with targets running at very low
8804 speeds, like the 32kHz startup clock of an AT91RM9200.
8807 @subsection ARM720T specific commands
8810 These commands are available to ARM720T based CPUs,
8811 which are implementations of the ARMv4T architecture
8812 based on the ARM7TDMI-S integer core.
8813 They are available in addition to the ARM and ARM7/ARM9 commands.
8815 @deffn Command {arm720t cp15} opcode [value]
8816 @emph{DEPRECATED -- avoid using this.
8817 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8819 Display cp15 register returned by the ARM instruction @var{opcode};
8820 else if a @var{value} is provided, that value is written to that register.
8821 The @var{opcode} should be the value of either an MRC or MCR instruction.
8824 @subsection ARM9 specific commands
8827 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
8829 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
8831 @c 9-june-2009: tried this on arm920t, it didn't work.
8832 @c no-params always lists nothing caught, and that's how it acts.
8833 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
8834 @c versions have different rules about when they commit writes.
8836 @anchor{arm9vectorcatch}
8837 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
8838 @cindex vector_catch
8839 Vector Catch hardware provides a sort of dedicated breakpoint
8840 for hardware events such as reset, interrupt, and abort.
8841 You can use this to conserve normal breakpoint resources,
8842 so long as you're not concerned with code that branches directly
8843 to those hardware vectors.
8845 This always finishes by listing the current configuration.
8846 If parameters are provided, it first reconfigures the
8847 vector catch hardware to intercept
8848 @option{all} of the hardware vectors,
8849 @option{none} of them,
8850 or a list with one or more of the following:
8851 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
8852 @option{irq} @option{fiq}.
8855 @subsection ARM920T specific commands
8858 These commands are available to ARM920T based CPUs,
8859 which are implementations of the ARMv4T architecture
8860 built using the ARM9TDMI integer core.
8861 They are available in addition to the ARM, ARM7/ARM9,
8864 @deffn Command {arm920t cache_info}
8865 Print information about the caches found. This allows to see whether your target
8866 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
8869 @deffn Command {arm920t cp15} regnum [value]
8870 Display cp15 register @var{regnum};
8871 else if a @var{value} is provided, that value is written to that register.
8872 This uses "physical access" and the register number is as
8873 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
8874 (Not all registers can be written.)
8877 @deffn Command {arm920t cp15i} opcode [value [address]]
8878 @emph{DEPRECATED -- avoid using this.
8879 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8881 Interpreted access using ARM instruction @var{opcode}, which should
8882 be the value of either an MRC or MCR instruction
8883 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
8884 If no @var{value} is provided, the result is displayed.
8885 Else if that value is written using the specified @var{address},
8886 or using zero if no other address is provided.
8889 @deffn Command {arm920t read_cache} filename
8890 Dump the content of ICache and DCache to a file named @file{filename}.
8893 @deffn Command {arm920t read_mmu} filename
8894 Dump the content of the ITLB and DTLB to a file named @file{filename}.
8897 @subsection ARM926ej-s specific commands
8900 These commands are available to ARM926ej-s based CPUs,
8901 which are implementations of the ARMv5TEJ architecture
8902 based on the ARM9EJ-S integer core.
8903 They are available in addition to the ARM, ARM7/ARM9,
8906 The Feroceon cores also support these commands, although
8907 they are not built from ARM926ej-s designs.
8909 @deffn Command {arm926ejs cache_info}
8910 Print information about the caches found.
8913 @subsection ARM966E specific commands
8916 These commands are available to ARM966 based CPUs,
8917 which are implementations of the ARMv5TE architecture.
8918 They are available in addition to the ARM, ARM7/ARM9,
8921 @deffn Command {arm966e cp15} regnum [value]
8922 Display cp15 register @var{regnum};
8923 else if a @var{value} is provided, that value is written to that register.
8924 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
8926 There is no current control over bits 31..30 from that table,
8927 as required for BIST support.
8930 @subsection XScale specific commands
8933 Some notes about the debug implementation on the XScale CPUs:
8935 The XScale CPU provides a special debug-only mini-instruction cache
8936 (mini-IC) in which exception vectors and target-resident debug handler
8937 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
8938 must point vector 0 (the reset vector) to the entry of the debug
8939 handler. However, this means that the complete first cacheline in the
8940 mini-IC is marked valid, which makes the CPU fetch all exception
8941 handlers from the mini-IC, ignoring the code in RAM.
8943 To address this situation, OpenOCD provides the @code{xscale
8944 vector_table} command, which allows the user to explicitly write
8945 individual entries to either the high or low vector table stored in
8948 It is recommended to place a pc-relative indirect branch in the vector
8949 table, and put the branch destination somewhere in memory. Doing so
8950 makes sure the code in the vector table stays constant regardless of
8951 code layout in memory:
8954 ldr pc,[pc,#0x100-8]
8955 ldr pc,[pc,#0x100-8]
8956 ldr pc,[pc,#0x100-8]
8957 ldr pc,[pc,#0x100-8]
8958 ldr pc,[pc,#0x100-8]
8959 ldr pc,[pc,#0x100-8]
8960 ldr pc,[pc,#0x100-8]
8961 ldr pc,[pc,#0x100-8]
8963 .long real_reset_vector
8964 .long real_ui_handler
8965 .long real_swi_handler
8967 .long real_data_abort
8968 .long 0 /* unused */
8969 .long real_irq_handler
8970 .long real_fiq_handler
8973 Alternatively, you may choose to keep some or all of the mini-IC
8974 vector table entries synced with those written to memory by your
8975 system software. The mini-IC can not be modified while the processor
8976 is executing, but for each vector table entry not previously defined
8977 using the @code{xscale vector_table} command, OpenOCD will copy the
8978 value from memory to the mini-IC every time execution resumes from a
8979 halt. This is done for both high and low vector tables (although the
8980 table not in use may not be mapped to valid memory, and in this case
8981 that copy operation will silently fail). This means that you will
8982 need to briefly halt execution at some strategic point during system
8983 start-up; e.g., after the software has initialized the vector table,
8984 but before exceptions are enabled. A breakpoint can be used to
8985 accomplish this once the appropriate location in the start-up code has
8986 been identified. A watchpoint over the vector table region is helpful
8987 in finding the location if you're not sure. Note that the same
8988 situation exists any time the vector table is modified by the system
8991 The debug handler must be placed somewhere in the address space using
8992 the @code{xscale debug_handler} command. The allowed locations for the
8993 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
8994 0xfffff800). The default value is 0xfe000800.
8996 XScale has resources to support two hardware breakpoints and two
8997 watchpoints. However, the following restrictions on watchpoint
8998 functionality apply: (1) the value and mask arguments to the @code{wp}
8999 command are not supported, (2) the watchpoint length must be a
9000 power of two and not less than four, and can not be greater than the
9001 watchpoint address, and (3) a watchpoint with a length greater than
9002 four consumes all the watchpoint hardware resources. This means that
9003 at any one time, you can have enabled either two watchpoints with a
9004 length of four, or one watchpoint with a length greater than four.
9006 These commands are available to XScale based CPUs,
9007 which are implementations of the ARMv5TE architecture.
9009 @deffn Command {xscale analyze_trace}
9010 Displays the contents of the trace buffer.
9013 @deffn Command {xscale cache_clean_address} address
9014 Changes the address used when cleaning the data cache.
9017 @deffn Command {xscale cache_info}
9018 Displays information about the CPU caches.
9021 @deffn Command {xscale cp15} regnum [value]
9022 Display cp15 register @var{regnum};
9023 else if a @var{value} is provided, that value is written to that register.
9026 @deffn Command {xscale debug_handler} target address
9027 Changes the address used for the specified target's debug handler.
9030 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
9031 Enables or disable the CPU's data cache.
9034 @deffn Command {xscale dump_trace} filename
9035 Dumps the raw contents of the trace buffer to @file{filename}.
9038 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
9039 Enables or disable the CPU's instruction cache.
9042 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
9043 Enables or disable the CPU's memory management unit.
9046 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
9047 Displays the trace buffer status, after optionally
9048 enabling or disabling the trace buffer
9049 and modifying how it is emptied.
9052 @deffn Command {xscale trace_image} filename [offset [type]]
9053 Opens a trace image from @file{filename}, optionally rebasing
9054 its segment addresses by @var{offset}.
9055 The image @var{type} may be one of
9056 @option{bin} (binary), @option{ihex} (Intel hex),
9057 @option{elf} (ELF file), @option{s19} (Motorola s19),
9058 @option{mem}, or @option{builder}.
9061 @anchor{xscalevectorcatch}
9062 @deffn Command {xscale vector_catch} [mask]
9063 @cindex vector_catch
9064 Display a bitmask showing the hardware vectors to catch.
9065 If the optional parameter is provided, first set the bitmask to that value.
9067 The mask bits correspond with bit 16..23 in the DCSR:
9070 0x02 Trap Undefined Instructions
9071 0x04 Trap Software Interrupt
9072 0x08 Trap Prefetch Abort
9073 0x10 Trap Data Abort
9080 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
9081 @cindex vector_table
9083 Set an entry in the mini-IC vector table. There are two tables: one for
9084 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
9085 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
9086 points to the debug handler entry and can not be overwritten.
9087 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
9089 Without arguments, the current settings are displayed.
9093 @section ARMv6 Architecture
9096 @subsection ARM11 specific commands
9099 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
9100 Displays the value of the memwrite burst-enable flag,
9101 which is enabled by default.
9102 If a boolean parameter is provided, first assigns that flag.
9103 Burst writes are only used for memory writes larger than 1 word.
9104 They improve performance by assuming that the CPU has read each data
9105 word over JTAG and completed its write before the next word arrives,
9106 instead of polling for a status flag to verify that completion.
9107 This is usually safe, because JTAG runs much slower than the CPU.
9110 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
9111 Displays the value of the memwrite error_fatal flag,
9112 which is enabled by default.
9113 If a boolean parameter is provided, first assigns that flag.
9114 When set, certain memory write errors cause earlier transfer termination.
9117 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
9118 Displays the value of the flag controlling whether
9119 IRQs are enabled during single stepping;
9120 they are disabled by default.
9121 If a boolean parameter is provided, first assigns that.
9124 @deffn Command {arm11 vcr} [value]
9125 @cindex vector_catch
9126 Displays the value of the @emph{Vector Catch Register (VCR)},
9127 coprocessor 14 register 7.
9128 If @var{value} is defined, first assigns that.
9130 Vector Catch hardware provides dedicated breakpoints
9131 for certain hardware events.
9132 The specific bit values are core-specific (as in fact is using
9133 coprocessor 14 register 7 itself) but all current ARM11
9134 cores @emph{except the ARM1176} use the same six bits.
9137 @section ARMv7 and ARMv8 Architecture
9141 @subsection ARMv7-A specific commands
9144 @deffn Command {cortex_a cache_info}
9145 display information about target caches
9148 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
9149 Work around issues with software breakpoints when the program text is
9150 mapped read-only by the operating system. This option sets the CP15 DACR
9151 to "all-manager" to bypass MMU permission checks on memory access.
9155 @deffn Command {cortex_a dbginit}
9156 Initialize core debug
9157 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9160 @deffn Command {cortex_a smp} [on|off]
9161 Display/set the current SMP mode
9164 @deffn Command {cortex_a smp_gdb} [core_id]
9165 Display/set the current core displayed in GDB
9168 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
9169 Selects whether interrupts will be processed when single stepping
9172 @deffn Command {cache_config l2x} [base way]
9176 @deffn Command {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
9177 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
9178 memory location @var{address}. When dumping the table from @var{address}, print at most
9179 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
9180 possible (4096) entries are printed.
9183 @subsection ARMv7-R specific commands
9186 @deffn Command {cortex_r dbginit}
9187 Initialize core debug
9188 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9191 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
9192 Selects whether interrupts will be processed when single stepping
9196 @subsection ARMv7-M specific commands
9204 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
9205 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
9206 @var{TRACECLKIN_freq} [@var{trace_freq}]))
9208 ARMv7-M architecture provides several modules to generate debugging
9209 information internally (ITM, DWT and ETM). Their output is directed
9210 through TPIU to be captured externally either on an SWO pin (this
9211 configuration is called SWV) or on a synchronous parallel trace port.
9213 This command configures the TPIU module of the target and, if internal
9214 capture mode is selected, starts to capture trace output by using the
9215 debugger adapter features.
9217 Some targets require additional actions to be performed in the
9218 @b{trace-config} handler for trace port to be activated.
9222 @item @option{disable} disable TPIU handling;
9223 @item @option{external} configure TPIU to let user capture trace
9224 output externally (with an additional UART or logic analyzer hardware);
9225 @item @option{internal @var{filename}} configure TPIU and debug adapter to
9226 gather trace data and append it to @var{filename} (which can be
9227 either a regular file or a named pipe);
9228 @item @option{internal -} configure TPIU and debug adapter to
9229 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
9230 @item @option{sync @var{port_width}} use synchronous parallel trace output
9231 mode, and set port width to @var{port_width};
9232 @item @option{manchester} use asynchronous SWO mode with Manchester
9234 @item @option{uart} use asynchronous SWO mode with NRZ (same as
9235 regular UART 8N1) coding;
9236 @item @var{formatter_enable} is @option{on} or @option{off} to enable
9237 or disable TPIU formatter which needs to be used when both ITM and ETM
9238 data is to be output via SWO;
9239 @item @var{TRACECLKIN_freq} this should be specified to match target's
9240 current TRACECLKIN frequency (usually the same as HCLK);
9241 @item @var{trace_freq} trace port frequency. Can be omitted in
9242 internal mode to let the adapter driver select the maximum supported
9248 @item STM32L152 board is programmed with an application that configures
9249 PLL to provide core clock with 24MHz frequency; to use ITM output it's
9252 #include <libopencm3/cm3/itm.h>
9257 (the most obvious way is to use the first stimulus port for printf,
9258 for that this ITM_STIM8 assignment can be used inside _write(); to make it
9259 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
9260 ITM_STIM_FIFOREADY));});
9261 @item An FT2232H UART is connected to the SWO pin of the board;
9262 @item Commands to configure UART for 12MHz baud rate:
9264 $ setserial /dev/ttyUSB1 spd_cust divisor 5
9265 $ stty -F /dev/ttyUSB1 38400
9267 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
9268 baud with our custom divisor to get 12MHz)
9269 @item @code{itmdump -f /dev/ttyUSB1 -d1}
9270 @item OpenOCD invocation line:
9272 openocd -f interface/stlink.cfg \
9273 -c "transport select hla_swd" \
9274 -f target/stm32l1.cfg \
9275 -c "tpiu config external uart off 24000000 12000000"
9280 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
9281 Enable or disable trace output for ITM stimulus @var{port} (counting
9282 from 0). Port 0 is enabled on target creation automatically.
9285 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
9286 Enable or disable trace output for all ITM stimulus ports.
9289 @subsection Cortex-M specific commands
9292 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
9293 Control masking (disabling) interrupts during target step/resume.
9295 The @option{auto} option handles interrupts during stepping in a way that they
9296 get served but don't disturb the program flow. The step command first allows
9297 pending interrupt handlers to execute, then disables interrupts and steps over
9298 the next instruction where the core was halted. After the step interrupts
9299 are enabled again. If the interrupt handlers don't complete within 500ms,
9300 the step command leaves with the core running.
9302 The @option{steponly} option disables interrupts during single-stepping but
9303 enables them during normal execution. This can be used as a partial workaround
9304 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
9305 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
9307 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
9308 option. If no breakpoint is available at the time of the step, then the step
9309 is taken with interrupts enabled, i.e. the same way the @option{off} option
9312 Default is @option{auto}.
9315 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
9316 @cindex vector_catch
9317 Vector Catch hardware provides dedicated breakpoints
9318 for certain hardware events.
9320 Parameters request interception of
9321 @option{all} of these hardware event vectors,
9322 @option{none} of them,
9323 or one or more of the following:
9324 @option{hard_err} for a HardFault exception;
9325 @option{mm_err} for a MemManage exception;
9326 @option{bus_err} for a BusFault exception;
9329 @option{chk_err}, or
9330 @option{nocp_err} for various UsageFault exceptions; or
9332 If NVIC setup code does not enable them,
9333 MemManage, BusFault, and UsageFault exceptions
9334 are mapped to HardFault.
9335 UsageFault checks for
9336 divide-by-zero and unaligned access
9337 must also be explicitly enabled.
9339 This finishes by listing the current vector catch configuration.
9342 @deffn Command {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
9343 Control reset handling if hardware srst is not fitted
9344 @xref{reset_config,,reset_config}.
9347 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
9348 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
9351 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
9352 This however has the disadvantage of only resetting the core, all peripherals
9353 are unaffected. A solution would be to use a @code{reset-init} event handler
9354 to manually reset the peripherals.
9355 @xref{targetevents,,Target Events}.
9357 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
9361 @subsection ARMv8-A specific commands
9365 @deffn Command {aarch64 cache_info}
9366 Display information about target caches
9369 @deffn Command {aarch64 dbginit}
9370 This command enables debugging by clearing the OS Lock and sticky power-down and reset
9371 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
9372 target code relies on. In a configuration file, the command would typically be called from a
9373 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
9374 However, normally it is not necessary to use the command at all.
9377 @deffn Command {aarch64 disassemble} address [count]
9379 Disassembles @var{count} instructions starting at @var{address}.
9380 If @var{count} is not specified, a single instruction is disassembled.
9383 @deffn Command {aarch64 smp} [on|off]
9384 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
9385 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
9386 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
9387 group. With SMP handling disabled, all targets need to be treated individually.
9390 @deffn Command {aarch64 maskisr} [@option{on}|@option{off}]
9391 Selects whether interrupts will be processed when single stepping. The default configuration is
9395 @deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
9396 Cause @command{$target_name} to halt when an exception is taken. Any combination of
9397 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
9398 @command{$target_name} will halt before taking the exception. In order to resume
9399 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
9400 Issuing the command without options prints the current configuration.
9403 @section EnSilica eSi-RISC Architecture
9405 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
9406 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
9408 @subsection eSi-RISC Configuration
9410 @deffn Command {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
9411 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
9412 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
9415 @deffn Command {esirisc hwdc} (@option{all}|@option{none}|mask ...)
9416 Configure hardware debug control. The HWDC register controls which exceptions return
9417 control back to the debugger. Possible masks are @option{all}, @option{none},
9418 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
9419 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
9422 @subsection eSi-RISC Operation
9424 @deffn Command {esirisc flush_caches}
9425 Flush instruction and data caches. This command requires that the target is halted
9426 when the command is issued and configured with an instruction or data cache.
9429 @subsection eSi-Trace Configuration
9431 eSi-RISC targets may be configured with support for instruction tracing. Trace
9432 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
9433 is typically employed to move trace data off-device using a high-speed
9434 peripheral (eg. SPI). Collected trace data is encoded in one of three different
9435 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
9436 fifo} must be issued along with @command{esirisc trace format} before trace data
9439 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
9440 needed, collected trace data can be dumped to a file and processed by external
9444 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
9445 for this issue is to configure DMA to copy trace data to an in-memory buffer,
9446 which can then be passed to the @command{esirisc trace analyze} and
9447 @command{esirisc trace dump} commands.
9449 It is possible to corrupt trace data when using a FIFO if the peripheral
9450 responsible for draining data from the FIFO is not fast enough. This can be
9451 managed by enabling flow control, however this can impact timing-sensitive
9452 software operation on the CPU.
9455 @deffn Command {esirisc trace buffer} address size [@option{wrap}]
9456 Configure trace buffer using the provided address and size. If the @option{wrap}
9457 option is specified, trace collection will continue once the end of the buffer
9458 is reached. By default, wrap is disabled.
9461 @deffn Command {esirisc trace fifo} address
9462 Configure trace FIFO using the provided address.
9465 @deffn Command {esirisc trace flow_control} (@option{enable}|@option{disable})
9466 Enable or disable stalling the CPU to collect trace data. By default, flow
9467 control is disabled.
9470 @deffn Command {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
9471 Configure trace format and number of PC bits to be captured. @option{pc_bits}
9472 must be within 1 and 31 as the LSB is not collected. If external tooling is used
9473 to analyze collected trace data, these values must match.
9475 Supported trace formats:
9477 @item @option{full} capture full trace data, allowing execution history and
9478 timing to be determined.
9479 @item @option{branch} capture taken branch instructions and branch target
9481 @item @option{icache} capture instruction cache misses.
9485 @deffn Command {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
9486 Configure trigger start condition using the provided start data and mask. A
9487 brief description of each condition is provided below; for more detail on how
9488 these values are used, see the eSi-RISC Architecture Manual.
9490 Supported conditions:
9492 @item @option{none} manual tracing (see @command{esirisc trace start}).
9493 @item @option{pc} start tracing if the PC matches start data and mask.
9494 @item @option{load} start tracing if the effective address of a load
9495 instruction matches start data and mask.
9496 @item @option{store} start tracing if the effective address of a store
9497 instruction matches start data and mask.
9498 @item @option{exception} start tracing if the EID of an exception matches start
9500 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
9501 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
9502 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
9503 @item @option{high} start tracing when an external signal is a logical high.
9504 @item @option{low} start tracing when an external signal is a logical low.
9508 @deffn Command {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
9509 Configure trigger stop condition using the provided stop data and mask. A brief
9510 description of each condition is provided below; for more detail on how these
9511 values are used, see the eSi-RISC Architecture Manual.
9513 Supported conditions:
9515 @item @option{none} manual tracing (see @command{esirisc trace stop}).
9516 @item @option{pc} stop tracing if the PC matches stop data and mask.
9517 @item @option{load} stop tracing if the effective address of a load
9518 instruction matches stop data and mask.
9519 @item @option{store} stop tracing if the effective address of a store
9520 instruction matches stop data and mask.
9521 @item @option{exception} stop tracing if the EID of an exception matches stop
9523 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
9524 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
9525 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
9529 @deffn Command {esirisc trace trigger delay} (@option{trigger}) [cycles]
9530 Configure trigger start/stop delay in clock cycles.
9534 @item @option{none} no delay to start or stop collection.
9535 @item @option{start} delay @option{cycles} after trigger to start collection.
9536 @item @option{stop} delay @option{cycles} after trigger to stop collection.
9537 @item @option{both} delay @option{cycles} after both triggers to start or stop
9542 @subsection eSi-Trace Operation
9544 @deffn Command {esirisc trace init}
9545 Initialize trace collection. This command must be called any time the
9546 configuration changes. If a trace buffer has been configured, the contents will
9547 be overwritten when trace collection starts.
9550 @deffn Command {esirisc trace info}
9551 Display trace configuration.
9554 @deffn Command {esirisc trace status}
9555 Display trace collection status.
9558 @deffn Command {esirisc trace start}
9559 Start manual trace collection.
9562 @deffn Command {esirisc trace stop}
9563 Stop manual trace collection.
9566 @deffn Command {esirisc trace analyze} [address size]
9567 Analyze collected trace data. This command may only be used if a trace buffer
9568 has been configured. If a trace FIFO has been configured, trace data must be
9569 copied to an in-memory buffer identified by the @option{address} and
9570 @option{size} options using DMA.
9573 @deffn Command {esirisc trace dump} [address size] @file{filename}
9574 Dump collected trace data to file. This command may only be used if a trace
9575 buffer has been configured. If a trace FIFO has been configured, trace data must
9576 be copied to an in-memory buffer identified by the @option{address} and
9577 @option{size} options using DMA.
9580 @section Intel Architecture
9582 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
9583 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
9584 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
9585 software debug and the CLTAP is used for SoC level operations.
9586 Useful docs are here: https://communities.intel.com/community/makers/documentation
9588 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
9589 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
9590 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
9593 @subsection x86 32-bit specific commands
9594 The three main address spaces for x86 are memory, I/O and configuration space.
9595 These commands allow a user to read and write to the 64Kbyte I/O address space.
9597 @deffn Command {x86_32 idw} address
9598 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
9601 @deffn Command {x86_32 idh} address
9602 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
9605 @deffn Command {x86_32 idb} address
9606 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
9609 @deffn Command {x86_32 iww} address
9610 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
9613 @deffn Command {x86_32 iwh} address
9614 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
9617 @deffn Command {x86_32 iwb} address
9618 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
9621 @section OpenRISC Architecture
9623 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
9624 configured with any of the TAP / Debug Unit available.
9626 @subsection TAP and Debug Unit selection commands
9627 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
9628 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
9630 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
9631 Select between the Advanced Debug Interface and the classic one.
9633 An option can be passed as a second argument to the debug unit.
9635 When using the Advanced Debug Interface, option = 1 means the RTL core is
9636 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
9637 between bytes while doing read or write bursts.
9640 @subsection Registers commands
9641 @deffn Command {addreg} [name] [address] [feature] [reg_group]
9642 Add a new register in the cpu register list. This register will be
9643 included in the generated target descriptor file.
9645 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
9647 @strong{[reg_group]} can be anything. The default register list defines "system",
9648 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
9653 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
9658 @deffn Command {readgroup} (@option{group})
9659 Display all registers in @emph{group}.
9661 @emph{group} can be "system",
9662 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
9663 "timer" or any new group created with addreg command.
9666 @section RISC-V Architecture
9668 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
9669 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
9670 harts. (It's possible to increase this limit to 1024 by changing
9671 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
9672 Debug Specification, but there is also support for legacy targets that
9673 implement version 0.11.
9675 @subsection RISC-V Terminology
9677 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
9678 another hart, or may be a separate core. RISC-V treats those the same, and
9679 OpenOCD exposes each hart as a separate core.
9681 @subsection RISC-V Debug Configuration Commands
9683 @deffn Command {riscv expose_csrs} n0[-m0][,n1[-m1]]...
9684 Configure a list of inclusive ranges for CSRs to expose in addition to the
9685 standard ones. This must be executed before `init`.
9687 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
9688 and then only if the corresponding extension appears to be implemented. This
9689 command can be used if OpenOCD gets this wrong, or a target implements custom
9693 @deffn Command {riscv expose_custom} n0[-m0][,n1[-m1]]...
9694 The RISC-V Debug Specification allows targets to expose custom registers
9695 through abstract commands. (See Section 3.5.1.1 in that document.) This command
9696 configures a list of inclusive ranges of those registers to expose. Number 0
9697 indicates the first custom register, whose abstract command number is 0xc000.
9698 This command must be executed before `init`.
9701 @deffn Command {riscv set_command_timeout_sec} [seconds]
9702 Set the wall-clock timeout (in seconds) for individual commands. The default
9703 should work fine for all but the slowest targets (eg. simulators).
9706 @deffn Command {riscv set_reset_timeout_sec} [seconds]
9707 Set the maximum time to wait for a hart to come out of reset after reset is
9711 @deffn Command {riscv set_scratch_ram} none|[address]
9712 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
9713 This is used to access 64-bit floating point registers on 32-bit targets.
9716 @deffn Command {riscv set_prefer_sba} on|off
9717 When on, prefer to use System Bus Access to access memory. When off (default),
9718 prefer to use the Program Buffer to access memory.
9721 @deffn Command {riscv set_enable_virtual} on|off
9722 When on, memory accesses are performed on physical or virtual memory depending
9723 on the current system configuration. When off (default), all memory accessses are performed
9727 @deffn Command {riscv set_enable_virt2phys} on|off
9728 When on (default), memory accesses are performed on physical or virtual memory
9729 depending on the current satp configuration. When off, all memory accessses are
9730 performed on physical memory.
9733 @deffn Command {riscv resume_order} normal|reversed
9734 Some software assumes all harts are executing nearly continuously. Such
9735 software may be sensitive to the order that harts are resumed in. On harts
9736 that don't support hasel, this option allows the user to choose the order the
9737 harts are resumed in. If you are using this option, it's probably masking a
9738 race condition problem in your code.
9740 Normal order is from lowest hart index to highest. This is the default
9741 behavior. Reversed order is from highest hart index to lowest.
9744 @deffn Command {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
9745 Set the IR value for the specified JTAG register. This is useful, for
9746 example, when using the existing JTAG interface on a Xilinx FPGA by
9747 way of BSCANE2 primitives that only permit a limited selection of IR
9750 When utilizing version 0.11 of the RISC-V Debug Specification,
9751 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
9752 and DBUS registers, respectively.
9755 @deffn Command {riscv use_bscan_tunnel} value
9756 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
9757 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
9760 @deffn Command {riscv set_ebreakm} on|off
9761 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
9762 OpenOCD. When off, they generate a breakpoint exception handled internally.
9765 @deffn Command {riscv set_ebreaks} on|off
9766 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
9767 OpenOCD. When off, they generate a breakpoint exception handled internally.
9770 @deffn Command {riscv set_ebreaku} on|off
9771 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
9772 OpenOCD. When off, they generate a breakpoint exception handled internally.
9775 @subsection RISC-V Authentication Commands
9777 The following commands can be used to authenticate to a RISC-V system. Eg. a
9778 trivial challenge-response protocol could be implemented as follows in a
9779 configuration file, immediately following @command{init}:
9781 set challenge [riscv authdata_read]
9782 riscv authdata_write [expr $challenge + 1]
9785 @deffn Command {riscv authdata_read}
9786 Return the 32-bit value read from authdata.
9789 @deffn Command {riscv authdata_write} value
9790 Write the 32-bit value to authdata.
9793 @subsection RISC-V DMI Commands
9795 The following commands allow direct access to the Debug Module Interface, which
9796 can be used to interact with custom debug features.
9798 @deffn Command {riscv dmi_read} address
9799 Perform a 32-bit DMI read at address, returning the value.
9802 @deffn Command {riscv dmi_write} address value
9803 Perform a 32-bit DMI write of value at address.
9806 @section ARC Architecture
9809 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
9810 designers can optimize for a wide range of uses, from deeply embedded to
9811 high-performance host applications in a variety of market segments. See more
9812 at: http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx.
9813 OpenOCD currently supports ARC EM processors.
9814 There is a set ARC-specific OpenOCD commands that allow low-level
9815 access to the core and provide necessary support for ARC extensibility and
9816 configurability capabilities. ARC processors has much more configuration
9817 capabilities than most of the other processors and in addition there is an
9818 extension interface that allows SoC designers to add custom registers and
9819 instructions. For the OpenOCD that mostly means that set of core and AUX
9820 registers in target will vary and is not fixed for a particular processor
9821 model. To enable extensibility several TCL commands are provided that allow to
9822 describe those optional registers in OpenOCD configuration files. Moreover
9823 those commands allow for a dynamic target features discovery.
9826 @subsection General ARC commands
9828 @deffn {Config Command} {arc add-reg} configparams
9830 Add a new register to processor target. By default newly created register is
9831 marked as not existing. @var{configparams} must have following required
9836 @item @code{-name} name
9837 @*Name of a register.
9839 @item @code{-num} number
9840 @*Architectural register number: core register number or AUX register number.
9842 @item @code{-feature} XML_feature
9843 @*Name of GDB XML target description feature.
9847 @var{configparams} may have following optional arguments:
9851 @item @code{-gdbnum} number
9852 @*GDB register number. It is recommended to not assign GDB register number
9853 manually, because there would be a risk that two register will have same
9854 number. When register GDB number is not set with this option, then register
9855 will get a previous register number + 1. This option is required only for those
9856 registers that must be at particular address expected by GDB.
9859 @*This option specifies that register is a core registers. If not - this is an
9860 AUX register. AUX registers and core registers reside in different address
9864 @*This options specifies that register is a BCR register. BCR means Build
9865 Configuration Registers - this is a special type of AUX registers that are read
9866 only and non-volatile, that is - they never change their value. Therefore OpenOCD
9867 never invalidates values of those registers in internal caches. Because BCR is a
9868 type of AUX registers, this option cannot be used with @code{-core}.
9870 @item @code{-type} type_name
9871 @*Name of type of this register. This can be either one of the basic GDB types,
9872 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
9875 @* If specified then this is a "general" register. General registers are always
9876 read by OpenOCD on context save (when core has just been halted) and is always
9877 transferred to GDB client in a response to g-packet. Contrary to this,
9878 non-general registers are read and sent to GDB client on-demand. In general it
9879 is not recommended to apply this option to custom registers.
9885 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
9886 Adds new register type of ``flags'' class. ``Flags'' types can contain only
9887 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
9890 @anchor{add-reg-type-struct}
9891 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
9892 Adds new register type of ``struct'' class. ``Struct'' types can contain either
9893 bit-fields or fields of other types, however at the moment only bit fields are
9894 supported. Structure bit field definition looks like @code{-bitfield name
9898 @deffn {Command} {arc get-reg-field} reg-name field-name
9899 Returns value of bit-field in a register. Register must be ``struct'' register
9900 type, @xref{add-reg-type-struct} command definition.
9903 @deffn {Command} {arc set-reg-exists} reg-names...
9904 Specify that some register exists. Any amount of names can be passed
9905 as an argument for a single command invocation.
9908 @subsection ARC JTAG commands
9910 @deffn {Command} {arc jtag set-aux-reg} regnum value
9911 This command writes value to AUX register via its number. This command access
9912 register in target directly via JTAG, bypassing any OpenOCD internal caches,
9913 therefore it is unsafe to use if that register can be operated by other means.
9917 @deffn {Command} {arc jtag set-core-reg} regnum value
9918 This command is similar to @command{arc jtag set-aux-reg} but is for core
9922 @deffn {Command} {arc jtag get-aux-reg} regnum
9923 This command returns the value storded in AUX register via its number. This commands access
9924 register in target directly via JTAG, bypassing any OpenOCD internal caches,
9925 therefore it is unsafe to use if that register can be operated by other means.
9929 @deffn {Command} {arc jtag get-core-reg} regnum
9930 This command is similar to @command{arc jtag get-aux-reg} but is for core
9934 @section STM8 Architecture
9935 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
9936 STMicroelectronics, based on a proprietary 8-bit core architecture.
9938 OpenOCD supports debugging STM8 through the STMicroelectronics debug
9939 protocol SWIM, @pxref{swimtransport,,SWIM}.
9941 @anchor{softwaredebugmessagesandtracing}
9942 @section Software Debug Messages and Tracing
9943 @cindex Linux-ARM DCC support
9947 OpenOCD can process certain requests from target software, when
9948 the target uses appropriate libraries.
9949 The most powerful mechanism is semihosting, but there is also
9950 a lighter weight mechanism using only the DCC channel.
9952 Currently @command{target_request debugmsgs}
9953 is supported only for @option{arm7_9} and @option{cortex_m} cores.
9954 These messages are received as part of target polling, so
9955 you need to have @command{poll on} active to receive them.
9956 They are intrusive in that they will affect program execution
9957 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
9959 See @file{libdcc} in the contrib dir for more details.
9960 In addition to sending strings, characters, and
9961 arrays of various size integers from the target,
9962 @file{libdcc} also exports a software trace point mechanism.
9963 The target being debugged may
9964 issue trace messages which include a 24-bit @dfn{trace point} number.
9965 Trace point support includes two distinct mechanisms,
9966 each supported by a command:
9969 @item @emph{History} ... A circular buffer of trace points
9970 can be set up, and then displayed at any time.
9971 This tracks where code has been, which can be invaluable in
9972 finding out how some fault was triggered.
9974 The buffer may overflow, since it collects records continuously.
9975 It may be useful to use some of the 24 bits to represent a
9976 particular event, and other bits to hold data.
9978 @item @emph{Counting} ... An array of counters can be set up,
9979 and then displayed at any time.
9980 This can help establish code coverage and identify hot spots.
9982 The array of counters is directly indexed by the trace point
9983 number, so trace points with higher numbers are not counted.
9986 Linux-ARM kernels have a ``Kernel low-level debugging
9987 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
9988 depends on CONFIG_DEBUG_LL) which uses this mechanism to
9989 deliver messages before a serial console can be activated.
9990 This is not the same format used by @file{libdcc}.
9991 Other software, such as the U-Boot boot loader, sometimes
9992 does the same thing.
9994 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
9995 Displays current handling of target DCC message requests.
9996 These messages may be sent to the debugger while the target is running.
9997 The optional @option{enable} and @option{charmsg} parameters
9998 both enable the messages, while @option{disable} disables them.
10000 With @option{charmsg} the DCC words each contain one character,
10001 as used by Linux with CONFIG_DEBUG_ICEDCC;
10002 otherwise the libdcc format is used.
10005 @deffn Command {trace history} [@option{clear}|count]
10006 With no parameter, displays all the trace points that have triggered
10007 in the order they triggered.
10008 With the parameter @option{clear}, erases all current trace history records.
10009 With a @var{count} parameter, allocates space for that many
10013 @deffn Command {trace point} [@option{clear}|identifier]
10014 With no parameter, displays all trace point identifiers and how many times
10015 they have been triggered.
10016 With the parameter @option{clear}, erases all current trace point counters.
10017 With a numeric @var{identifier} parameter, creates a new a trace point counter
10018 and associates it with that identifier.
10020 @emph{Important:} The identifier and the trace point number
10021 are not related except by this command.
10022 These trace point numbers always start at zero (from server startup,
10023 or after @command{trace point clear}) and count up from there.
10027 @node JTAG Commands
10028 @chapter JTAG Commands
10029 @cindex JTAG Commands
10030 Most general purpose JTAG commands have been presented earlier.
10031 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
10032 Lower level JTAG commands, as presented here,
10033 may be needed to work with targets which require special
10034 attention during operations such as reset or initialization.
10036 To use these commands you will need to understand some
10037 of the basics of JTAG, including:
10040 @item A JTAG scan chain consists of a sequence of individual TAP
10041 devices such as a CPUs.
10042 @item Control operations involve moving each TAP through the same
10043 standard state machine (in parallel)
10044 using their shared TMS and clock signals.
10045 @item Data transfer involves shifting data through the chain of
10046 instruction or data registers of each TAP, writing new register values
10047 while the reading previous ones.
10048 @item Data register sizes are a function of the instruction active in
10049 a given TAP, while instruction register sizes are fixed for each TAP.
10050 All TAPs support a BYPASS instruction with a single bit data register.
10051 @item The way OpenOCD differentiates between TAP devices is by
10052 shifting different instructions into (and out of) their instruction
10056 @section Low Level JTAG Commands
10058 These commands are used by developers who need to access
10059 JTAG instruction or data registers, possibly controlling
10060 the order of TAP state transitions.
10061 If you're not debugging OpenOCD internals, or bringing up a
10062 new JTAG adapter or a new type of TAP device (like a CPU or
10063 JTAG router), you probably won't need to use these commands.
10064 In a debug session that doesn't use JTAG for its transport protocol,
10065 these commands are not available.
10067 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
10068 Loads the data register of @var{tap} with a series of bit fields
10069 that specify the entire register.
10070 Each field is @var{numbits} bits long with
10071 a numeric @var{value} (hexadecimal encouraged).
10072 The return value holds the original value of each
10075 For example, a 38 bit number might be specified as one
10076 field of 32 bits then one of 6 bits.
10077 @emph{For portability, never pass fields which are more
10078 than 32 bits long. Many OpenOCD implementations do not
10079 support 64-bit (or larger) integer values.}
10081 All TAPs other than @var{tap} must be in BYPASS mode.
10082 The single bit in their data registers does not matter.
10084 When @var{tap_state} is specified, the JTAG state machine is left
10086 For example @sc{drpause} might be specified, so that more
10087 instructions can be issued before re-entering the @sc{run/idle} state.
10088 If the end state is not specified, the @sc{run/idle} state is entered.
10091 OpenOCD does not record information about data register lengths,
10092 so @emph{it is important that you get the bit field lengths right}.
10093 Remember that different JTAG instructions refer to different
10094 data registers, which may have different lengths.
10095 Moreover, those lengths may not be fixed;
10096 the SCAN_N instruction can change the length of
10097 the register accessed by the INTEST instruction
10098 (by connecting a different scan chain).
10102 @deffn Command {flush_count}
10103 Returns the number of times the JTAG queue has been flushed.
10104 This may be used for performance tuning.
10106 For example, flushing a queue over USB involves a
10107 minimum latency, often several milliseconds, which does
10108 not change with the amount of data which is written.
10109 You may be able to identify performance problems by finding
10110 tasks which waste bandwidth by flushing small transfers too often,
10111 instead of batching them into larger operations.
10114 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
10115 For each @var{tap} listed, loads the instruction register
10116 with its associated numeric @var{instruction}.
10117 (The number of bits in that instruction may be displayed
10118 using the @command{scan_chain} command.)
10119 For other TAPs, a BYPASS instruction is loaded.
10121 When @var{tap_state} is specified, the JTAG state machine is left
10123 For example @sc{irpause} might be specified, so the data register
10124 can be loaded before re-entering the @sc{run/idle} state.
10125 If the end state is not specified, the @sc{run/idle} state is entered.
10128 OpenOCD currently supports only a single field for instruction
10129 register values, unlike data register values.
10130 For TAPs where the instruction register length is more than 32 bits,
10131 portable scripts currently must issue only BYPASS instructions.
10135 @deffn Command {pathmove} start_state [next_state ...]
10136 Start by moving to @var{start_state}, which
10137 must be one of the @emph{stable} states.
10138 Unless it is the only state given, this will often be the
10139 current state, so that no TCK transitions are needed.
10140 Then, in a series of single state transitions
10141 (conforming to the JTAG state machine) shift to
10142 each @var{next_state} in sequence, one per TCK cycle.
10143 The final state must also be stable.
10146 @deffn Command {runtest} @var{num_cycles}
10147 Move to the @sc{run/idle} state, and execute at least
10148 @var{num_cycles} of the JTAG clock (TCK).
10149 Instructions often need some time
10150 to execute before they take effect.
10153 @c tms_sequence (short|long)
10154 @c ... temporary, debug-only, other than USBprog bug workaround...
10156 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
10157 Verify values captured during @sc{ircapture} and returned
10158 during IR scans. Default is enabled, but this can be
10159 overridden by @command{verify_jtag}.
10160 This flag is ignored when validating JTAG chain configuration.
10163 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
10164 Enables verification of DR and IR scans, to help detect
10165 programming errors. For IR scans, @command{verify_ircapture}
10166 must also be enabled.
10167 Default is enabled.
10170 @section TAP state names
10171 @cindex TAP state names
10173 The @var{tap_state} names used by OpenOCD in the @command{drscan},
10174 @command{irscan}, and @command{pathmove} commands are the same
10175 as those used in SVF boundary scan documents, except that
10176 SVF uses @sc{idle} instead of @sc{run/idle}.
10179 @item @b{RESET} ... @emph{stable} (with TMS high);
10180 acts as if TRST were pulsed
10181 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
10183 @item @b{DRCAPTURE}
10184 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
10185 through the data register
10187 @item @b{DRPAUSE} ... @emph{stable}; data register ready
10188 for update or more shifting
10192 @item @b{IRCAPTURE}
10193 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
10194 through the instruction register
10196 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
10197 for update or more shifting
10202 Note that only six of those states are fully ``stable'' in the
10203 face of TMS fixed (low except for @sc{reset})
10204 and a free-running JTAG clock. For all the
10205 others, the next TCK transition changes to a new state.
10208 @item From @sc{drshift} and @sc{irshift}, clock transitions will
10209 produce side effects by changing register contents. The values
10210 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
10211 may not be as expected.
10212 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
10213 choices after @command{drscan} or @command{irscan} commands,
10214 since they are free of JTAG side effects.
10215 @item @sc{run/idle} may have side effects that appear at non-JTAG
10216 levels, such as advancing the ARM9E-S instruction pipeline.
10217 Consult the documentation for the TAP(s) you are working with.
10220 @node Boundary Scan Commands
10221 @chapter Boundary Scan Commands
10223 One of the original purposes of JTAG was to support
10224 boundary scan based hardware testing.
10225 Although its primary focus is to support On-Chip Debugging,
10226 OpenOCD also includes some boundary scan commands.
10228 @section SVF: Serial Vector Format
10229 @cindex Serial Vector Format
10232 The Serial Vector Format, better known as @dfn{SVF}, is a
10233 way to represent JTAG test patterns in text files.
10234 In a debug session using JTAG for its transport protocol,
10235 OpenOCD supports running such test files.
10237 @deffn Command {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
10238 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
10239 This issues a JTAG reset (Test-Logic-Reset) and then
10240 runs the SVF script from @file{filename}.
10242 Arguments can be specified in any order; the optional dash doesn't
10243 affect their semantics.
10247 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
10248 specified by the SVF file with HIR, TIR, HDR and TDR commands;
10249 instead, calculate them automatically according to the current JTAG
10250 chain configuration, targeting @var{tapname};
10251 @item @option{[-]quiet} do not log every command before execution;
10252 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
10253 on the real interface;
10254 @item @option{[-]progress} enable progress indication;
10255 @item @option{[-]ignore_error} continue execution despite TDO check
10260 @section XSVF: Xilinx Serial Vector Format
10261 @cindex Xilinx Serial Vector Format
10264 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
10265 binary representation of SVF which is optimized for use with
10267 In a debug session using JTAG for its transport protocol,
10268 OpenOCD supports running such test files.
10270 @quotation Important
10271 Not all XSVF commands are supported.
10274 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
10275 This issues a JTAG reset (Test-Logic-Reset) and then
10276 runs the XSVF script from @file{filename}.
10277 When a @var{tapname} is specified, the commands are directed at
10279 When @option{virt2} is specified, the @sc{xruntest} command counts
10280 are interpreted as TCK cycles instead of microseconds.
10281 Unless the @option{quiet} option is specified,
10282 messages are logged for comments and some retries.
10285 The OpenOCD sources also include two utility scripts
10286 for working with XSVF; they are not currently installed
10287 after building the software.
10288 You may find them useful:
10291 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
10292 syntax understood by the @command{xsvf} command; see notes below.
10293 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
10294 understands the OpenOCD extensions.
10297 The input format accepts a handful of non-standard extensions.
10298 These include three opcodes corresponding to SVF extensions
10299 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
10300 two opcodes supporting a more accurate translation of SVF
10301 (XTRST, XWAITSTATE).
10302 If @emph{xsvfdump} shows a file is using those opcodes, it
10303 probably will not be usable with other XSVF tools.
10306 @node Utility Commands
10307 @chapter Utility Commands
10308 @cindex Utility Commands
10310 @section RAM testing
10311 @cindex RAM testing
10313 There is often a need to stress-test random access memory (RAM) for
10314 errors. OpenOCD comes with a Tcl implementation of well-known memory
10315 testing procedures allowing the detection of all sorts of issues with
10316 electrical wiring, defective chips, PCB layout and other common
10319 To use them, you usually need to initialise your RAM controller first;
10320 consult your SoC's documentation to get the recommended list of
10321 register operations and translate them to the corresponding
10322 @command{mww}/@command{mwb} commands.
10324 Load the memory testing functions with
10327 source [find tools/memtest.tcl]
10330 to get access to the following facilities:
10332 @deffn Command {memTestDataBus} address
10333 Test the data bus wiring in a memory region by performing a walking
10334 1's test at a fixed address within that region.
10337 @deffn Command {memTestAddressBus} baseaddress size
10338 Perform a walking 1's test on the relevant bits of the address and
10339 check for aliasing. This test will find single-bit address failures
10340 such as stuck-high, stuck-low, and shorted pins.
10343 @deffn Command {memTestDevice} baseaddress size
10344 Test the integrity of a physical memory device by performing an
10345 increment/decrement test over the entire region. In the process every
10346 storage bit in the device is tested as zero and as one.
10349 @deffn Command {runAllMemTests} baseaddress size
10350 Run all of the above tests over a specified memory region.
10353 @section Firmware recovery helpers
10354 @cindex Firmware recovery
10356 OpenOCD includes an easy-to-use script to facilitate mass-market
10357 devices recovery with JTAG.
10359 For quickstart instructions run:
10361 openocd -f tools/firmware-recovery.tcl -c firmware_help
10367 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
10368 be used to access files on PCs (either the developer's PC or some other PC).
10370 The way this works on the ZY1000 is to prefix a filename by
10371 "/tftp/ip/" and append the TFTP path on the TFTP
10372 server (tftpd). For example,
10375 load_image /tftp/10.0.0.96/c:\temp\abc.elf
10378 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
10379 if the file was hosted on the embedded host.
10381 In order to achieve decent performance, you must choose a TFTP server
10382 that supports a packet size bigger than the default packet size (512 bytes). There
10383 are numerous TFTP servers out there (free and commercial) and you will have to do
10384 a bit of googling to find something that fits your requirements.
10386 @node GDB and OpenOCD
10387 @chapter GDB and OpenOCD
10389 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
10390 to debug remote targets.
10391 Setting up GDB to work with OpenOCD can involve several components:
10394 @item The OpenOCD server support for GDB may need to be configured.
10395 @xref{gdbconfiguration,,GDB Configuration}.
10396 @item GDB's support for OpenOCD may need configuration,
10397 as shown in this chapter.
10398 @item If you have a GUI environment like Eclipse,
10399 that also will probably need to be configured.
10402 Of course, the version of GDB you use will need to be one which has
10403 been built to know about the target CPU you're using. It's probably
10404 part of the tool chain you're using. For example, if you are doing
10405 cross-development for ARM on an x86 PC, instead of using the native
10406 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
10407 if that's the tool chain used to compile your code.
10409 @section Connecting to GDB
10410 @cindex Connecting to GDB
10411 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
10412 instance GDB 6.3 has a known bug that produces bogus memory access
10413 errors, which has since been fixed; see
10414 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
10416 OpenOCD can communicate with GDB in two ways:
10420 A socket (TCP/IP) connection is typically started as follows:
10422 target extended-remote localhost:3333
10424 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
10426 The extended remote protocol is a super-set of the remote protocol and should
10427 be the preferred choice. More details are available in GDB documentation
10428 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
10430 To speed-up typing, any GDB command can be abbreviated, including the extended
10431 remote command above that becomes:
10436 @b{Note:} If any backward compatibility issue requires using the old remote
10437 protocol in place of the extended remote one, the former protocol is still
10438 available through the command:
10440 target remote localhost:3333
10444 A pipe connection is typically started as follows:
10446 target extended-remote | openocd -c "gdb_port pipe; log_output openocd.log"
10448 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
10449 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
10450 session. log_output sends the log output to a file to ensure that the pipe is
10451 not saturated when using higher debug level outputs.
10454 To list the available OpenOCD commands type @command{monitor help} on the
10457 @section Sample GDB session startup
10459 With the remote protocol, GDB sessions start a little differently
10460 than they do when you're debugging locally.
10461 Here's an example showing how to start a debug session with a
10463 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
10464 Most programs would be written into flash (address 0) and run from there.
10467 $ arm-none-eabi-gdb example.elf
10468 (gdb) target extended-remote localhost:3333
10469 Remote debugging using localhost:3333
10471 (gdb) monitor reset halt
10474 Loading section .vectors, size 0x100 lma 0x20000000
10475 Loading section .text, size 0x5a0 lma 0x20000100
10476 Loading section .data, size 0x18 lma 0x200006a0
10477 Start address 0x2000061c, load size 1720
10478 Transfer rate: 22 KB/sec, 573 bytes/write.
10484 You could then interrupt the GDB session to make the program break,
10485 type @command{where} to show the stack, @command{list} to show the
10486 code around the program counter, @command{step} through code,
10487 set breakpoints or watchpoints, and so on.
10489 @section Configuring GDB for OpenOCD
10491 OpenOCD supports the gdb @option{qSupported} packet, this enables information
10492 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
10493 packet size and the device's memory map.
10494 You do not need to configure the packet size by hand,
10495 and the relevant parts of the memory map should be automatically
10496 set up when you declare (NOR) flash banks.
10498 However, there are other things which GDB can't currently query.
10499 You may need to set those up by hand.
10500 As OpenOCD starts up, you will often see a line reporting
10504 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
10507 You can pass that information to GDB with these commands:
10510 set remote hardware-breakpoint-limit 6
10511 set remote hardware-watchpoint-limit 4
10514 With that particular hardware (Cortex-M3) the hardware breakpoints
10515 only work for code running from flash memory. Most other ARM systems
10516 do not have such restrictions.
10518 Rather than typing such commands interactively, you may prefer to
10519 save them in a file and have GDB execute them as it starts, perhaps
10520 using a @file{.gdbinit} in your project directory or starting GDB
10521 using @command{gdb -x filename}.
10523 @section Programming using GDB
10524 @cindex Programming using GDB
10525 @anchor{programmingusinggdb}
10527 By default the target memory map is sent to GDB. This can be disabled by
10528 the following OpenOCD configuration option:
10530 gdb_memory_map disable
10532 For this to function correctly a valid flash configuration must also be set
10533 in OpenOCD. For faster performance you should also configure a valid
10536 Informing GDB of the memory map of the target will enable GDB to protect any
10537 flash areas of the target and use hardware breakpoints by default. This means
10538 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
10539 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
10541 To view the configured memory map in GDB, use the GDB command @option{info mem}.
10542 All other unassigned addresses within GDB are treated as RAM.
10544 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
10545 This can be changed to the old behaviour by using the following GDB command
10547 set mem inaccessible-by-default off
10550 If @command{gdb_flash_program enable} is also used, GDB will be able to
10551 program any flash memory using the vFlash interface.
10553 GDB will look at the target memory map when a load command is given, if any
10554 areas to be programmed lie within the target flash area the vFlash packets
10557 If the target needs configuring before GDB programming, set target
10558 event gdb-flash-erase-start:
10560 $_TARGETNAME configure -event gdb-flash-erase-start BODY
10562 @xref{targetevents,,Target Events}, for other GDB programming related events.
10564 To verify any flash programming the GDB command @option{compare-sections}
10567 @section Using GDB as a non-intrusive memory inspector
10568 @cindex Using GDB as a non-intrusive memory inspector
10569 @anchor{gdbmeminspect}
10571 If your project controls more than a blinking LED, let's say a heavy industrial
10572 robot or an experimental nuclear reactor, stopping the controlling process
10573 just because you want to attach GDB is not a good option.
10575 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
10576 Though there is a possible setup where the target does not get stopped
10577 and GDB treats it as it were running.
10578 If the target supports background access to memory while it is running,
10579 you can use GDB in this mode to inspect memory (mainly global variables)
10580 without any intrusion of the target process.
10582 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
10583 Place following command after target configuration:
10585 $_TARGETNAME configure -event gdb-attach @{@}
10588 If any of installed flash banks does not support probe on running target,
10589 switch off gdb_memory_map:
10591 gdb_memory_map disable
10594 Ensure GDB is configured without interrupt-on-connect.
10595 Some GDB versions set it by default, some does not.
10597 set remote interrupt-on-connect off
10600 If you switched gdb_memory_map off, you may want to setup GDB memory map
10601 manually or issue @command{set mem inaccessible-by-default off}
10603 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
10604 of a running target. Do not use GDB commands @command{continue},
10605 @command{step} or @command{next} as they synchronize GDB with your target
10606 and GDB would require stopping the target to get the prompt back.
10608 Do not use this mode under an IDE like Eclipse as it caches values of
10609 previously shown varibles.
10611 @section RTOS Support
10612 @cindex RTOS Support
10613 @anchor{gdbrtossupport}
10615 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
10616 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
10618 @xref{Threads, Debugging Programs with Multiple Threads,
10619 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
10622 @* An example setup is below:
10625 $_TARGETNAME configure -rtos auto
10628 This will attempt to auto detect the RTOS within your application.
10630 Currently supported rtos's include:
10632 @item @option{eCos}
10633 @item @option{ThreadX}
10634 @item @option{FreeRTOS}
10635 @item @option{linux}
10636 @item @option{ChibiOS}
10637 @item @option{embKernel}
10639 @item @option{uCOS-III}
10640 @item @option{nuttx}
10641 @item @option{RIOT}
10642 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
10645 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
10646 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
10650 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
10651 @item ThreadX symbols
10652 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
10653 @item FreeRTOS symbols
10654 @c The following is taken from recent texinfo to provide compatibility
10655 @c with ancient versions that do not support @raggedright
10658 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
10659 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
10660 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
10661 uxCurrentNumberOfTasks, uxTopUsedPriority.
10665 @item linux symbols
10667 @item ChibiOS symbols
10668 rlist, ch_debug, chSysInit.
10669 @item embKernel symbols
10670 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
10671 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
10673 _mqx_kernel_data, MQX_init_struct.
10674 @item uC/OS-III symbols
10675 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
10676 @item nuttx symbols
10677 g_readytorun, g_tasklisttable
10679 sched_threads, sched_num_threads, sched_active_pid, max_threads, _tcb_name_offset
10682 For most RTOS supported the above symbols will be exported by default. However for
10683 some, eg. FreeRTOS and uC/OS-III, extra steps must be taken.
10685 These RTOSes may require additional OpenOCD-specific file to be linked
10686 along with the project:
10690 contrib/rtos-helpers/FreeRTOS-openocd.c
10692 contrib/rtos-helpers/uCOS-III-openocd.c
10695 @anchor{usingopenocdsmpwithgdb}
10696 @section Using OpenOCD SMP with GDB
10700 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
10701 ("hardware threads") in an SMP system as threads to GDB. With this extension,
10702 GDB can be used to inspect the state of an SMP system in a natural way.
10703 After halting the system, using the GDB command @command{info threads} will
10704 list the context of each active CPU core in the system. GDB's @command{thread}
10705 command can be used to switch the view to a different CPU core.
10706 The @command{step} and @command{stepi} commands can be used to step a specific core
10707 while other cores are free-running or remain halted, depending on the
10708 scheduler-locking mode configured in GDB.
10710 @section Legacy SMP core switching support
10712 This method is deprecated in favor of the @emph{hwthread} pseudo RTOS.
10715 For SMP support following GDB serial protocol packet have been defined :
10717 @item j - smp status request
10718 @item J - smp set request
10721 OpenOCD implements :
10723 @item @option{jc} packet for reading core id displayed by
10724 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
10725 @option{E01} for target not smp.
10726 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
10727 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
10728 for target not smp or @option{OK} on success.
10731 Handling of this packet within GDB can be done :
10733 @item by the creation of an internal variable (i.e @option{_core}) by mean
10734 of function allocate_computed_value allowing following GDB command.
10737 #Jc01 packet is sent
10739 #jc packet is sent and result is affected in $
10742 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
10743 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
10746 # toggle0 : force display of coreid 0
10752 # toggle1 : force display of coreid 1
10761 @node Tcl Scripting API
10762 @chapter Tcl Scripting API
10763 @cindex Tcl Scripting API
10764 @cindex Tcl scripts
10767 Tcl commands are stateless; e.g. the @command{telnet} command has
10768 a concept of currently active target, the Tcl API proc's take this sort
10769 of state information as an argument to each proc.
10771 There are three main types of return values: single value, name value
10772 pair list and lists.
10774 Name value pair. The proc 'foo' below returns a name/value pair
10778 > set foo(me) Duane
10779 > set foo(you) Oyvind
10780 > set foo(mouse) Micky
10781 > set foo(duck) Donald
10793 me Duane you Oyvind mouse Micky duck Donald
10796 Thus, to get the names of the associative array is easy:
10799 foreach { name value } [set foo] {
10800 puts "Name: $name, Value: $value"
10804 Lists returned should be relatively small. Otherwise, a range
10805 should be passed in to the proc in question.
10807 @section Internal low-level Commands
10809 By "low-level," we mean commands that a human would typically not
10813 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
10815 Read memory and return as a Tcl array for script processing
10816 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
10818 Convert a Tcl array to memory locations and write the values
10819 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
10821 Return information about the flash banks
10823 @item @b{capture} <@var{command}>
10825 Run <@var{command}> and return full log output that was produced during
10826 its execution. Example:
10829 > capture "reset init"
10834 OpenOCD commands can consist of two words, e.g. "flash banks". The
10835 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
10836 called "flash_banks".
10838 @section OpenOCD specific Global Variables
10840 Real Tcl has ::tcl_platform(), and platform::identify, and many other
10841 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
10842 holds one of the following values:
10845 @item @b{cygwin} Running under Cygwin
10846 @item @b{darwin} Darwin (Mac-OS) is the underlying operating system.
10847 @item @b{freebsd} Running under FreeBSD
10848 @item @b{openbsd} Running under OpenBSD
10849 @item @b{netbsd} Running under NetBSD
10850 @item @b{linux} Linux is the underlying operating system
10851 @item @b{mingw32} Running under MingW32
10852 @item @b{winxx} Built using Microsoft Visual Studio
10853 @item @b{ecos} Running under eCos
10854 @item @b{other} Unknown, none of the above.
10857 Note: 'winxx' was chosen because today (March-2009) no distinction is made between Win32 and Win64.
10860 We should add support for a variable like Tcl variable
10861 @code{tcl_platform(platform)}, it should be called
10862 @code{jim_platform} (because it
10863 is jim, not real tcl).
10866 @section Tcl RPC server
10869 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
10870 commands and receive the results.
10872 To access it, your application needs to connect to a configured TCP port
10873 (see @command{tcl_port}). Then it can pass any string to the
10874 interpreter terminating it with @code{0x1a} and wait for the return
10875 value (it will be terminated with @code{0x1a} as well). This can be
10876 repeated as many times as desired without reopening the connection.
10878 It is not needed anymore to prefix the OpenOCD commands with
10879 @code{ocd_} to get the results back. But sometimes you might need the
10880 @command{capture} command.
10882 See @file{contrib/rpc_examples/} for specific client implementations.
10884 @section Tcl RPC server notifications
10885 @cindex RPC Notifications
10887 Notifications are sent asynchronously to other commands being executed over
10888 the RPC server, so the port must be polled continuously.
10890 Target event, state and reset notifications are emitted as Tcl associative arrays
10891 in the following format.
10894 type target_event event [event-name]
10895 type target_state state [state-name]
10896 type target_reset mode [reset-mode]
10899 @deffn {Command} tcl_notifications [on/off]
10900 Toggle output of target notifications to the current Tcl RPC server.
10901 Only available from the Tcl RPC server.
10906 @section Tcl RPC server trace output
10907 @cindex RPC trace output
10909 Trace data is sent asynchronously to other commands being executed over
10910 the RPC server, so the port must be polled continuously.
10912 Target trace data is emitted as a Tcl associative array in the following format.
10915 type target_trace data [trace-data-hex-encoded]
10918 @deffn {Command} tcl_trace [on/off]
10919 Toggle output of target trace data to the current Tcl RPC server.
10920 Only available from the Tcl RPC server.
10923 See an example application here:
10924 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
10933 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
10935 @cindex adaptive clocking
10938 In digital circuit design it is often referred to as ``clock
10939 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
10940 operating at some speed, your CPU target is operating at another.
10941 The two clocks are not synchronised, they are ``asynchronous''
10943 In order for the two to work together they must be synchronised
10944 well enough to work; JTAG can't go ten times faster than the CPU,
10945 for example. There are 2 basic options:
10948 Use a special "adaptive clocking" circuit to change the JTAG
10949 clock rate to match what the CPU currently supports.
10951 The JTAG clock must be fixed at some speed that's enough slower than
10952 the CPU clock that all TMS and TDI transitions can be detected.
10955 @b{Does this really matter?} For some chips and some situations, this
10956 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
10957 the CPU has no difficulty keeping up with JTAG.
10958 Startup sequences are often problematic though, as are other
10959 situations where the CPU clock rate changes (perhaps to save
10962 For example, Atmel AT91SAM chips start operation from reset with
10963 a 32kHz system clock. Boot firmware may activate the main oscillator
10964 and PLL before switching to a faster clock (perhaps that 500 MHz
10966 If you're using JTAG to debug that startup sequence, you must slow
10967 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
10968 JTAG can use a faster clock.
10970 Consider also debugging a 500MHz ARM926 hand held battery powered
10971 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
10972 clock, between keystrokes unless it has work to do. When would
10973 that 5 MHz JTAG clock be usable?
10975 @b{Solution #1 - A special circuit}
10977 In order to make use of this,
10978 your CPU, board, and JTAG adapter must all support the RTCK
10979 feature. Not all of them support this; keep reading!
10981 The RTCK ("Return TCK") signal in some ARM chips is used to help with
10982 this problem. ARM has a good description of the problem described at
10983 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
10984 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
10985 work? / how does adaptive clocking work?''.
10987 The nice thing about adaptive clocking is that ``battery powered hand
10988 held device example'' - the adaptiveness works perfectly all the
10989 time. One can set a break point or halt the system in the deep power
10990 down code, slow step out until the system speeds up.
10992 Note that adaptive clocking may also need to work at the board level,
10993 when a board-level scan chain has multiple chips.
10994 Parallel clock voting schemes are good way to implement this,
10995 both within and between chips, and can easily be implemented
10997 It's not difficult to have logic fan a module's input TCK signal out
10998 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
10999 back with the right polarity before changing the output RTCK signal.
11000 Texas Instruments makes some clock voting logic available
11001 for free (with no support) in VHDL form; see
11002 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
11004 @b{Solution #2 - Always works - but may be slower}
11006 Often this is a perfectly acceptable solution.
11008 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
11009 the target clock speed. But what that ``magic division'' is varies
11010 depending on the chips on your board.
11011 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
11012 ARM11 cores use an 8:1 division.
11013 @b{Xilinx rule of thumb} is 1/12 the clock speed.
11015 Note: most full speed FT2232 based JTAG adapters are limited to a
11016 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
11017 often support faster clock rates (and adaptive clocking).
11019 You can still debug the 'low power' situations - you just need to
11020 either use a fixed and very slow JTAG clock rate ... or else
11021 manually adjust the clock speed at every step. (Adjusting is painful
11022 and tedious, and is not always practical.)
11024 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
11025 have a special debug mode in your application that does a ``high power
11026 sleep''. If you are careful - 98% of your problems can be debugged
11029 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
11030 operation in your idle loops even if you don't otherwise change the CPU
11032 That operation gates the CPU clock, and thus the JTAG clock; which
11033 prevents JTAG access. One consequence is not being able to @command{halt}
11034 cores which are executing that @emph{wait for interrupt} operation.
11036 To set the JTAG frequency use the command:
11039 # Example: 1.234MHz
11044 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
11046 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
11047 around Windows filenames.
11060 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
11062 Make sure you have Cygwin installed, or at least a version of OpenOCD that
11063 claims to come with all the necessary DLLs. When using Cygwin, try launching
11064 OpenOCD from the Cygwin shell.
11066 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
11067 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
11068 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
11070 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
11071 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
11072 software breakpoints consume one of the two available hardware breakpoints.
11074 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
11076 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
11077 clock at the time you're programming the flash. If you've specified the crystal's
11078 frequency, make sure the PLL is disabled. If you've specified the full core speed
11079 (e.g. 60MHz), make sure the PLL is enabled.
11081 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
11082 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
11083 out while waiting for end of scan, rtck was disabled".
11085 Make sure your PC's parallel port operates in EPP mode. You might have to try several
11086 settings in your PC BIOS (ECP, EPP, and different versions of those).
11088 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
11089 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
11090 memory read caused data abort".
11092 The errors are non-fatal, and are the result of GDB trying to trace stack frames
11093 beyond the last valid frame. It might be possible to prevent this by setting up
11094 a proper "initial" stack frame, if you happen to know what exactly has to
11095 be done, feel free to add this here.
11097 @b{Simple:} In your startup code - push 8 registers of zeros onto the
11098 stack before calling main(). What GDB is doing is ``climbing'' the run
11099 time stack by reading various values on the stack using the standard
11100 call frame for the target. GDB keeps going - until one of 2 things
11101 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
11102 stackframes have been processed. By pushing zeros on the stack, GDB
11105 @b{Debugging Interrupt Service Routines} - In your ISR before you call
11106 your C code, do the same - artificially push some zeros onto the stack,
11107 remember to pop them off when the ISR is done.
11109 @b{Also note:} If you have a multi-threaded operating system, they
11110 often do not @b{in the intrest of saving memory} waste these few
11114 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
11115 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
11117 This warning doesn't indicate any serious problem, as long as you don't want to
11118 debug your core right out of reset. Your .cfg file specified @option{reset_config
11119 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
11120 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
11121 independently. With this setup, it's not possible to halt the core right out of
11122 reset, everything else should work fine.
11124 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
11125 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
11126 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
11127 quit with an error message. Is there a stability issue with OpenOCD?
11129 No, this is not a stability issue concerning OpenOCD. Most users have solved
11130 this issue by simply using a self-powered USB hub, which they connect their
11131 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
11132 supply stable enough for the Amontec JTAGkey to be operated.
11134 @b{Laptops running on battery have this problem too...}
11136 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
11137 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
11138 What does that mean and what might be the reason for this?
11140 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
11141 has closed the connection to OpenOCD. This might be a GDB issue.
11143 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
11144 are described, there is a parameter for specifying the clock frequency
11145 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
11146 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
11147 specified in kilohertz. However, I do have a quartz crystal of a
11148 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
11149 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
11152 No. The clock frequency specified here must be given as an integral number.
11153 However, this clock frequency is used by the In-Application-Programming (IAP)
11154 routines of the LPC2000 family only, which seems to be very tolerant concerning
11155 the given clock frequency, so a slight difference between the specified clock
11156 frequency and the actual clock frequency will not cause any trouble.
11158 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
11160 Well, yes and no. Commands can be given in arbitrary order, yet the
11161 devices listed for the JTAG scan chain must be given in the right
11162 order (jtag newdevice), with the device closest to the TDO-Pin being
11163 listed first. In general, whenever objects of the same type exist
11164 which require an index number, then these objects must be given in the
11165 right order (jtag newtap, targets and flash banks - a target
11166 references a jtag newtap and a flash bank references a target).
11168 You can use the ``scan_chain'' command to verify and display the tap order.
11170 Also, some commands can't execute until after @command{init} has been
11171 processed. Such commands include @command{nand probe} and everything
11172 else that needs to write to controller registers, perhaps for setting
11173 up DRAM and loading it with code.
11175 @anchor{faqtaporder}
11176 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
11179 Yes; whenever you have more than one, you must declare them in
11180 the same order used by the hardware.
11182 Many newer devices have multiple JTAG TAPs. For example:
11183 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
11184 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
11185 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
11186 connected to the boundary scan TAP, which then connects to the
11187 Cortex-M3 TAP, which then connects to the TDO pin.
11189 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
11190 (2) The boundary scan TAP. If your board includes an additional JTAG
11191 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
11192 place it before or after the STM32 chip in the chain. For example:
11195 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
11196 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
11197 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
11198 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
11199 @item Xilinx TDO Pin -> OpenOCD TDO (input)
11202 The ``jtag device'' commands would thus be in the order shown below. Note:
11205 @item jtag newtap Xilinx tap -irlen ...
11206 @item jtag newtap stm32 cpu -irlen ...
11207 @item jtag newtap stm32 bs -irlen ...
11208 @item # Create the debug target and say where it is
11209 @item target create stm32.cpu -chain-position stm32.cpu ...
11213 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
11214 log file, I can see these error messages: Error: arm7_9_common.c:561
11215 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
11221 @node Tcl Crash Course
11222 @chapter Tcl Crash Course
11225 Not everyone knows Tcl - this is not intended to be a replacement for
11226 learning Tcl, the intent of this chapter is to give you some idea of
11227 how the Tcl scripts work.
11229 This chapter is written with two audiences in mind. (1) OpenOCD users
11230 who need to understand a bit more of how Jim-Tcl works so they can do
11231 something useful, and (2) those that want to add a new command to
11234 @section Tcl Rule #1
11235 There is a famous joke, it goes like this:
11237 @item Rule #1: The wife is always correct
11238 @item Rule #2: If you think otherwise, See Rule #1
11241 The Tcl equal is this:
11244 @item Rule #1: Everything is a string
11245 @item Rule #2: If you think otherwise, See Rule #1
11248 As in the famous joke, the consequences of Rule #1 are profound. Once
11249 you understand Rule #1, you will understand Tcl.
11251 @section Tcl Rule #1b
11252 There is a second pair of rules.
11254 @item Rule #1: Control flow does not exist. Only commands
11255 @* For example: the classic FOR loop or IF statement is not a control
11256 flow item, they are commands, there is no such thing as control flow
11258 @item Rule #2: If you think otherwise, See Rule #1
11259 @* Actually what happens is this: There are commands that by
11260 convention, act like control flow key words in other languages. One of
11261 those commands is the word ``for'', another command is ``if''.
11264 @section Per Rule #1 - All Results are strings
11265 Every Tcl command results in a string. The word ``result'' is used
11266 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
11267 Everything is a string}
11269 @section Tcl Quoting Operators
11270 In life of a Tcl script, there are two important periods of time, the
11271 difference is subtle.
11274 @item Evaluation Time
11277 The two key items here are how ``quoted things'' work in Tcl. Tcl has
11278 three primary quoting constructs, the [square-brackets] the
11279 @{curly-braces@} and ``double-quotes''
11281 By now you should know $VARIABLES always start with a $DOLLAR
11282 sign. BTW: To set a variable, you actually use the command ``set'', as
11283 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
11284 = 1'' statement, but without the equal sign.
11287 @item @b{[square-brackets]}
11288 @* @b{[square-brackets]} are command substitutions. It operates much
11289 like Unix Shell `back-ticks`. The result of a [square-bracket]
11290 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
11291 string}. These two statements are roughly identical:
11295 echo "The Date is: $X"
11298 puts "The Date is: $X"
11300 @item @b{``double-quoted-things''}
11301 @* @b{``double-quoted-things''} are just simply quoted
11302 text. $VARIABLES and [square-brackets] are expanded in place - the
11303 result however is exactly 1 string. @i{Remember Rule #1 - Everything
11307 puts "It is now \"[date]\", $x is in 1 hour"
11309 @item @b{@{Curly-Braces@}}
11310 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
11311 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
11312 'single-quote' operators in BASH shell scripts, with the added
11313 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
11314 nested 3 times@}@}@} NOTE: [date] is a bad example;
11315 at this writing, Jim/OpenOCD does not have a date command.
11318 @section Consequences of Rule 1/2/3/4
11320 The consequences of Rule 1 are profound.
11322 @subsection Tokenisation & Execution.
11324 Of course, whitespace, blank lines and #comment lines are handled in
11327 As a script is parsed, each (multi) line in the script file is
11328 tokenised and according to the quoting rules. After tokenisation, that
11329 line is immediately executed.
11331 Multi line statements end with one or more ``still-open''
11332 @{curly-braces@} which - eventually - closes a few lines later.
11334 @subsection Command Execution
11336 Remember earlier: There are no ``control flow''
11337 statements in Tcl. Instead there are COMMANDS that simply act like
11338 control flow operators.
11340 Commands are executed like this:
11343 @item Parse the next line into (argc) and (argv[]).
11344 @item Look up (argv[0]) in a table and call its function.
11345 @item Repeat until End Of File.
11348 It sort of works like this:
11351 ReadAndParse( &argc, &argv );
11353 cmdPtr = LookupCommand( argv[0] );
11355 (*cmdPtr->Execute)( argc, argv );
11359 When the command ``proc'' is parsed (which creates a procedure
11360 function) it gets 3 parameters on the command line. @b{1} the name of
11361 the proc (function), @b{2} the list of parameters, and @b{3} the body
11362 of the function. Not the choice of words: LIST and BODY. The PROC
11363 command stores these items in a table somewhere so it can be found by
11364 ``LookupCommand()''
11366 @subsection The FOR command
11368 The most interesting command to look at is the FOR command. In Tcl,
11369 the FOR command is normally implemented in C. Remember, FOR is a
11370 command just like any other command.
11372 When the ascii text containing the FOR command is parsed, the parser
11373 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
11377 @item The ascii text 'for'
11378 @item The start text
11379 @item The test expression
11380 @item The next text
11381 @item The body text
11384 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
11385 Remember @i{Rule #1 - Everything is a string.} The key point is this:
11386 Often many of those parameters are in @{curly-braces@} - thus the
11387 variables inside are not expanded or replaced until later.
11389 Remember that every Tcl command looks like the classic ``main( argc,
11390 argv )'' function in C. In JimTCL - they actually look like this:
11394 MyCommand( Jim_Interp *interp,
11396 Jim_Obj * const *argvs );
11399 Real Tcl is nearly identical. Although the newer versions have
11400 introduced a byte-code parser and interpreter, but at the core, it
11401 still operates in the same basic way.
11403 @subsection FOR command implementation
11405 To understand Tcl it is perhaps most helpful to see the FOR
11406 command. Remember, it is a COMMAND not a control flow structure.
11408 In Tcl there are two underlying C helper functions.
11410 Remember Rule #1 - You are a string.
11412 The @b{first} helper parses and executes commands found in an ascii
11413 string. Commands can be separated by semicolons, or newlines. While
11414 parsing, variables are expanded via the quoting rules.
11416 The @b{second} helper evaluates an ascii string as a numerical
11417 expression and returns a value.
11419 Here is an example of how the @b{FOR} command could be
11420 implemented. The pseudo code below does not show error handling.
11422 void Execute_AsciiString( void *interp, const char *string );
11424 int Evaluate_AsciiExpression( void *interp, const char *string );
11427 MyForCommand( void *interp,
11432 SetResult( interp, "WRONG number of parameters");
11436 // argv[0] = the ascii string just like C
11438 // Execute the start statement.
11439 Execute_AsciiString( interp, argv[1] );
11441 // Top of loop test
11443 i = Evaluate_AsciiExpression(interp, argv[2]);
11447 // Execute the body
11448 Execute_AsciiString( interp, argv[3] );
11450 // Execute the LOOP part
11451 Execute_AsciiString( interp, argv[4] );
11455 SetResult( interp, "" );
11460 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
11461 in the same basic way.
11463 @section OpenOCD Tcl Usage
11465 @subsection source and find commands
11466 @b{Where:} In many configuration files
11467 @* Example: @b{ source [find FILENAME] }
11468 @*Remember the parsing rules
11470 @item The @command{find} command is in square brackets,
11471 and is executed with the parameter FILENAME. It should find and return
11472 the full path to a file with that name; it uses an internal search path.
11473 The RESULT is a string, which is substituted into the command line in
11474 place of the bracketed @command{find} command.
11475 (Don't try to use a FILENAME which includes the "#" character.
11476 That character begins Tcl comments.)
11477 @item The @command{source} command is executed with the resulting filename;
11478 it reads a file and executes as a script.
11480 @subsection format command
11481 @b{Where:} Generally occurs in numerous places.
11482 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
11488 puts [format "The answer: %d" [expr $x * $y]]
11491 @item The SET command creates 2 variables, X and Y.
11492 @item The double [nested] EXPR command performs math
11493 @* The EXPR command produces numerical result as a string.
11494 @* Refer to Rule #1
11495 @item The format command is executed, producing a single string
11496 @* Refer to Rule #1.
11497 @item The PUTS command outputs the text.
11499 @subsection Body or Inlined Text
11500 @b{Where:} Various TARGET scripts.
11503 proc someproc @{@} @{
11504 ... multiple lines of stuff ...
11506 $_TARGETNAME configure -event FOO someproc
11507 #2 Good - no variables
11508 $_TARGETNAME configure -event foo "this ; that;"
11509 #3 Good Curly Braces
11510 $_TARGETNAME configure -event FOO @{
11511 puts "Time: [date]"
11513 #4 DANGER DANGER DANGER
11514 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
11517 @item The $_TARGETNAME is an OpenOCD variable convention.
11518 @*@b{$_TARGETNAME} represents the last target created, the value changes
11519 each time a new target is created. Remember the parsing rules. When
11520 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
11521 the name of the target which happens to be a TARGET (object)
11523 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
11524 @*There are 4 examples:
11526 @item The TCLBODY is a simple string that happens to be a proc name
11527 @item The TCLBODY is several simple commands separated by semicolons
11528 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
11529 @item The TCLBODY is a string with variables that get expanded.
11532 In the end, when the target event FOO occurs the TCLBODY is
11533 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
11534 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
11536 Remember the parsing rules. In case #3, @{curly-braces@} mean the
11537 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
11538 and the text is evaluated. In case #4, they are replaced before the
11539 ``Target Object Command'' is executed. This occurs at the same time
11540 $_TARGETNAME is replaced. In case #4 the date will never
11541 change. @{BTW: [date] is a bad example; at this writing,
11542 Jim/OpenOCD does not have a date command@}
11544 @subsection Global Variables
11545 @b{Where:} You might discover this when writing your own procs @* In
11546 simple terms: Inside a PROC, if you need to access a global variable
11547 you must say so. See also ``upvar''. Example:
11549 proc myproc @{ @} @{
11550 set y 0 #Local variable Y
11551 global x #Global variable X
11552 puts [format "X=%d, Y=%d" $x $y]
11555 @section Other Tcl Hacks
11556 @b{Dynamic variable creation}
11558 # Dynamically create a bunch of variables.
11559 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
11561 set vn [format "BIT%d" $x]
11565 set $vn [expr (1 << $x)]
11568 @b{Dynamic proc/command creation}
11570 # One "X" function - 5 uart functions.
11571 foreach who @{A B C D E@}
11572 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
11578 @node OpenOCD Concept Index
11579 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
11580 @comment case issue with ``Index.html'' and ``index.html''
11581 @comment Occurs when creating ``--html --no-split'' output
11582 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
11583 @unnumbered OpenOCD Concept Index
11587 @node Command and Driver Index
11588 @unnumbered Command and Driver Index