1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
160 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 STMicroelectronics has an adapter called @b{ST-LINK}.
481 They only work with STMicroelectronics chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
491 @* This is available standalone and as part of some kits.
492 @* Link: @url{http://www.st.com/stlink-v3}
495 For info the original ST-LINK enumerates using the mass storage usb class; however,
496 its implementation is completely broken. The result is this causes issues under Linux.
497 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
499 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
500 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
503 @section USB TI/Stellaris ICDI based
504 Texas Instruments has an adapter called @b{ICDI}.
505 It is not to be confused with the FTDI based adapters that were originally fitted to their
506 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
508 @section USB CMSIS-DAP based
509 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
510 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
515 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
517 @item @b{USB - Presto}
518 @* Link: @url{http://tools.asix.net/prg_presto.htm}
520 @item @b{Versaloon-Link}
521 @* Link: @url{http://www.versaloon.com}
523 @item @b{ARM-JTAG-EW}
524 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
527 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
530 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
533 @* Link: @url{http://code.google.com/p/estick-jtag/}
535 @item @b{Keil ULINK v1}
536 @* Link: @url{http://www.keil.com/ulink1/}
538 @item @b{TI XDS110 Debug Probe}
539 @* The XDS110 is included as the embedded debug probe on many Texas Instruments
540 LaunchPad evaluation boards.
541 @* The XDS110 is also available as a stand-alone USB debug probe. The XDS110
542 stand-alone probe has the additional ability to supply voltage to the target
543 board via its AUX FUNCTIONS port. Use the
544 @command{xds110_supply_voltage <millivolts>} command to set the voltage. 0 turns
545 off the supply. Otherwise, the supply can be set to any value in the range 1800
547 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS110}
548 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Support_Utilities}
551 @section IBM PC Parallel Printer Port Based
553 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
554 and the Macraigor Wiggler. There are many clones and variations of
557 Note that parallel ports are becoming much less common, so if you
558 have the choice you should probably avoid these adapters in favor
563 @item @b{Wiggler} - There are many clones of this.
564 @* Link: @url{http://www.macraigor.com/wiggler.htm}
566 @item @b{DLC5} - From XILINX - There are many clones of this
567 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
568 produced, PDF schematics are easily found and it is easy to make.
570 @item @b{Amontec - JTAG Accelerator}
571 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
574 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
576 @item @b{Wiggler_ntrst_inverted}
577 @* Yet another variation - See the source code, src/jtag/parport.c
579 @item @b{old_amt_wiggler}
580 @* Unknown - probably not on the market today
583 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
586 @* Link: @url{http://www.amontec.com/chameleon.shtml}
592 @* ispDownload from Lattice Semiconductor
593 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
596 @* From STMicroelectronics;
597 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
605 @* An EP93xx based Linux machine using the GPIO pins directly.
608 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
610 @item @b{bcm2835gpio}
611 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
614 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
617 @* A JTAG driver acting as a client for the JTAG VPI server interface.
618 @* Link: @url{http://github.com/fjullien/jtag_vpi}
623 @chapter About Jim-Tcl
627 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
628 This programming language provides a simple and extensible
631 All commands presented in this Guide are extensions to Jim-Tcl.
632 You can use them as simple commands, without needing to learn
633 much of anything about Tcl.
634 Alternatively, you can write Tcl programs with them.
636 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
637 There is an active and responsive community, get on the mailing list
638 if you have any questions. Jim-Tcl maintainers also lurk on the
639 OpenOCD mailing list.
642 @item @b{Jim vs. Tcl}
643 @* Jim-Tcl is a stripped down version of the well known Tcl language,
644 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
645 fewer features. Jim-Tcl is several dozens of .C files and .H files and
646 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
647 4.2 MB .zip file containing 1540 files.
649 @item @b{Missing Features}
650 @* Our practice has been: Add/clone the real Tcl feature if/when
651 needed. We welcome Jim-Tcl improvements, not bloat. Also there
652 are a large number of optional Jim-Tcl features that are not
656 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
657 command interpreter today is a mixture of (newer)
658 Jim-Tcl commands, and the (older) original command interpreter.
661 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
662 can type a Tcl for() loop, set variables, etc.
663 Some of the commands documented in this guide are implemented
664 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
666 @item @b{Historical Note}
667 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
668 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
669 as a Git submodule, which greatly simplified upgrading Jim-Tcl
670 to benefit from new features and bugfixes in Jim-Tcl.
672 @item @b{Need a crash course in Tcl?}
673 @*@xref{Tcl Crash Course}.
678 @cindex command line options
680 @cindex directory search
682 Properly installing OpenOCD sets up your operating system to grant it access
683 to the debug adapters. On Linux, this usually involves installing a file
684 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
685 that works for many common adapters is shipped with OpenOCD in the
686 @file{contrib} directory. MS-Windows needs
687 complex and confusing driver configuration for every peripheral. Such issues
688 are unique to each operating system, and are not detailed in this User's Guide.
690 Then later you will invoke the OpenOCD server, with various options to
691 tell it how each debug session should work.
692 The @option{--help} option shows:
696 --help | -h display this help
697 --version | -v display OpenOCD version
698 --file | -f use configuration file <name>
699 --search | -s dir to search for config files and scripts
700 --debug | -d set debug level to 3
701 | -d<n> set debug level to <level>
702 --log_output | -l redirect log output to file <name>
703 --command | -c run <command>
706 If you don't give any @option{-f} or @option{-c} options,
707 OpenOCD tries to read the configuration file @file{openocd.cfg}.
708 To specify one or more different
709 configuration files, use @option{-f} options. For example:
712 openocd -f config1.cfg -f config2.cfg -f config3.cfg
715 Configuration files and scripts are searched for in
717 @item the current directory,
718 @item any search dir specified on the command line using the @option{-s} option,
719 @item any search dir specified using the @command{add_script_search_dir} command,
720 @item @file{$HOME/.openocd} (not on Windows),
721 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
722 @item the site wide script library @file{$pkgdatadir/site} and
723 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
725 The first found file with a matching file name will be used.
728 Don't try to use configuration script names or paths which
729 include the "#" character. That character begins Tcl comments.
732 @section Simple setup, no customization
734 In the best case, you can use two scripts from one of the script
735 libraries, hook up your JTAG adapter, and start the server ... and
736 your JTAG setup will just work "out of the box". Always try to
737 start by reusing those scripts, but assume you'll need more
738 customization even if this works. @xref{OpenOCD Project Setup}.
740 If you find a script for your JTAG adapter, and for your board or
741 target, you may be able to hook up your JTAG adapter then start
742 the server with some variation of one of the following:
745 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
746 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
749 You might also need to configure which reset signals are present,
750 using @option{-c 'reset_config trst_and_srst'} or something similar.
751 If all goes well you'll see output something like
754 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
755 For bug reports, read
756 http://openocd.org/doc/doxygen/bugs.html
757 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
758 (mfg: 0x23b, part: 0xba00, ver: 0x3)
761 Seeing that "tap/device found" message, and no warnings, means
762 the JTAG communication is working. That's a key milestone, but
763 you'll probably need more project-specific setup.
765 @section What OpenOCD does as it starts
767 OpenOCD starts by processing the configuration commands provided
768 on the command line or, if there were no @option{-c command} or
769 @option{-f file.cfg} options given, in @file{openocd.cfg}.
770 @xref{configurationstage,,Configuration Stage}.
771 At the end of the configuration stage it verifies the JTAG scan
772 chain defined using those commands; your configuration should
773 ensure that this always succeeds.
774 Normally, OpenOCD then starts running as a server.
775 Alternatively, commands may be used to terminate the configuration
776 stage early, perform work (such as updating some flash memory),
777 and then shut down without acting as a server.
779 Once OpenOCD starts running as a server, it waits for connections from
780 clients (Telnet, GDB, RPC) and processes the commands issued through
783 If you are having problems, you can enable internal debug messages via
784 the @option{-d} option.
786 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
787 @option{-c} command line switch.
789 To enable debug output (when reporting problems or working on OpenOCD
790 itself), use the @option{-d} command line switch. This sets the
791 @option{debug_level} to "3", outputting the most information,
792 including debug messages. The default setting is "2", outputting only
793 informational messages, warnings and errors. You can also change this
794 setting from within a telnet or gdb session using @command{debug_level<n>}
795 (@pxref{debuglevel,,debug_level}).
797 You can redirect all output from the server to a file using the
798 @option{-l <logfile>} switch.
800 Note! OpenOCD will launch the GDB & telnet server even if it can not
801 establish a connection with the target. In general, it is possible for
802 the JTAG controller to be unresponsive until the target is set up
803 correctly via e.g. GDB monitor commands in a GDB init script.
805 @node OpenOCD Project Setup
806 @chapter OpenOCD Project Setup
808 To use OpenOCD with your development projects, you need to do more than
809 just connect the JTAG adapter hardware (dongle) to your development board
810 and start the OpenOCD server.
811 You also need to configure your OpenOCD server so that it knows
812 about your adapter and board, and helps your work.
813 You may also want to connect OpenOCD to GDB, possibly
814 using Eclipse or some other GUI.
816 @section Hooking up the JTAG Adapter
818 Today's most common case is a dongle with a JTAG cable on one side
819 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
820 and a USB cable on the other.
821 Instead of USB, some cables use Ethernet;
822 older ones may use a PC parallel port, or even a serial port.
825 @item @emph{Start with power to your target board turned off},
826 and nothing connected to your JTAG adapter.
827 If you're particularly paranoid, unplug power to the board.
828 It's important to have the ground signal properly set up,
829 unless you are using a JTAG adapter which provides
830 galvanic isolation between the target board and the
833 @item @emph{Be sure it's the right kind of JTAG connector.}
834 If your dongle has a 20-pin ARM connector, you need some kind
835 of adapter (or octopus, see below) to hook it up to
836 boards using 14-pin or 10-pin connectors ... or to 20-pin
837 connectors which don't use ARM's pinout.
839 In the same vein, make sure the voltage levels are compatible.
840 Not all JTAG adapters have the level shifters needed to work
841 with 1.2 Volt boards.
843 @item @emph{Be certain the cable is properly oriented} or you might
844 damage your board. In most cases there are only two possible
845 ways to connect the cable.
846 Connect the JTAG cable from your adapter to the board.
847 Be sure it's firmly connected.
849 In the best case, the connector is keyed to physically
850 prevent you from inserting it wrong.
851 This is most often done using a slot on the board's male connector
852 housing, which must match a key on the JTAG cable's female connector.
853 If there's no housing, then you must look carefully and
854 make sure pin 1 on the cable hooks up to pin 1 on the board.
855 Ribbon cables are frequently all grey except for a wire on one
856 edge, which is red. The red wire is pin 1.
858 Sometimes dongles provide cables where one end is an ``octopus'' of
859 color coded single-wire connectors, instead of a connector block.
860 These are great when converting from one JTAG pinout to another,
861 but are tedious to set up.
862 Use these with connector pinout diagrams to help you match up the
863 adapter signals to the right board pins.
865 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
866 A USB, parallel, or serial port connector will go to the host which
867 you are using to run OpenOCD.
868 For Ethernet, consult the documentation and your network administrator.
870 For USB-based JTAG adapters you have an easy sanity check at this point:
871 does the host operating system see the JTAG adapter? If you're running
872 Linux, try the @command{lsusb} command. If that host is an
873 MS-Windows host, you'll need to install a driver before OpenOCD works.
875 @item @emph{Connect the adapter's power supply, if needed.}
876 This step is primarily for non-USB adapters,
877 but sometimes USB adapters need extra power.
879 @item @emph{Power up the target board.}
880 Unless you just let the magic smoke escape,
881 you're now ready to set up the OpenOCD server
882 so you can use JTAG to work with that board.
886 Talk with the OpenOCD server using
887 telnet (@code{telnet localhost 4444} on many systems) or GDB.
888 @xref{GDB and OpenOCD}.
890 @section Project Directory
892 There are many ways you can configure OpenOCD and start it up.
894 A simple way to organize them all involves keeping a
895 single directory for your work with a given board.
896 When you start OpenOCD from that directory,
897 it searches there first for configuration files, scripts,
898 files accessed through semihosting,
899 and for code you upload to the target board.
900 It is also the natural place to write files,
901 such as log files and data you download from the board.
903 @section Configuration Basics
905 There are two basic ways of configuring OpenOCD, and
906 a variety of ways you can mix them.
907 Think of the difference as just being how you start the server:
910 @item Many @option{-f file} or @option{-c command} options on the command line
911 @item No options, but a @dfn{user config file}
912 in the current directory named @file{openocd.cfg}
915 Here is an example @file{openocd.cfg} file for a setup
916 using a Signalyzer FT2232-based JTAG adapter to talk to
917 a board with an Atmel AT91SAM7X256 microcontroller:
920 source [find interface/ftdi/signalyzer.cfg]
922 # GDB can also flash my flash!
923 gdb_memory_map enable
924 gdb_flash_program enable
926 source [find target/sam7x256.cfg]
929 Here is the command line equivalent of that configuration:
932 openocd -f interface/ftdi/signalyzer.cfg \
933 -c "gdb_memory_map enable" \
934 -c "gdb_flash_program enable" \
935 -f target/sam7x256.cfg
938 You could wrap such long command lines in shell scripts,
939 each supporting a different development task.
940 One might re-flash the board with a specific firmware version.
941 Another might set up a particular debugging or run-time environment.
944 At this writing (October 2009) the command line method has
945 problems with how it treats variables.
946 For example, after @option{-c "set VAR value"}, or doing the
947 same in a script, the variable @var{VAR} will have no value
948 that can be tested in a later script.
951 Here we will focus on the simpler solution: one user config
952 file, including basic configuration plus any TCL procedures
953 to simplify your work.
955 @section User Config Files
956 @cindex config file, user
957 @cindex user config file
958 @cindex config file, overview
960 A user configuration file ties together all the parts of a project
962 One of the following will match your situation best:
965 @item Ideally almost everything comes from configuration files
966 provided by someone else.
967 For example, OpenOCD distributes a @file{scripts} directory
968 (probably in @file{/usr/share/openocd/scripts} on Linux).
969 Board and tool vendors can provide these too, as can individual
970 user sites; the @option{-s} command line option lets you say
971 where to find these files. (@xref{Running}.)
972 The AT91SAM7X256 example above works this way.
974 Three main types of non-user configuration file each have their
975 own subdirectory in the @file{scripts} directory:
978 @item @b{interface} -- one for each different debug adapter;
979 @item @b{board} -- one for each different board
980 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
983 Best case: include just two files, and they handle everything else.
984 The first is an interface config file.
985 The second is board-specific, and it sets up the JTAG TAPs and
986 their GDB targets (by deferring to some @file{target.cfg} file),
987 declares all flash memory, and leaves you nothing to do except
991 source [find interface/olimex-jtag-tiny.cfg]
992 source [find board/csb337.cfg]
995 Boards with a single microcontroller often won't need more
996 than the target config file, as in the AT91SAM7X256 example.
997 That's because there is no external memory (flash, DDR RAM), and
998 the board differences are encapsulated by application code.
1000 @item Maybe you don't know yet what your board looks like to JTAG.
1001 Once you know the @file{interface.cfg} file to use, you may
1002 need help from OpenOCD to discover what's on the board.
1003 Once you find the JTAG TAPs, you can just search for appropriate
1005 configuration files ... or write your own, from the bottom up.
1006 @xref{autoprobing,,Autoprobing}.
1008 @item You can often reuse some standard config files but
1009 need to write a few new ones, probably a @file{board.cfg} file.
1010 You will be using commands described later in this User's Guide,
1011 and working with the guidelines in the next chapter.
1013 For example, there may be configuration files for your JTAG adapter
1014 and target chip, but you need a new board-specific config file
1015 giving access to your particular flash chips.
1016 Or you might need to write another target chip configuration file
1017 for a new chip built around the Cortex-M3 core.
1020 When you write new configuration files, please submit
1021 them for inclusion in the next OpenOCD release.
1022 For example, a @file{board/newboard.cfg} file will help the
1023 next users of that board, and a @file{target/newcpu.cfg}
1024 will help support users of any board using that chip.
1028 You may may need to write some C code.
1029 It may be as simple as supporting a new FT2232 or parport
1030 based adapter; a bit more involved, like a NAND or NOR flash
1031 controller driver; or a big piece of work like supporting
1032 a new chip architecture.
1035 Reuse the existing config files when you can.
1036 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1037 You may find a board configuration that's a good example to follow.
1039 When you write config files, separate the reusable parts
1040 (things every user of that interface, chip, or board needs)
1041 from ones specific to your environment and debugging approach.
1045 For example, a @code{gdb-attach} event handler that invokes
1046 the @command{reset init} command will interfere with debugging
1047 early boot code, which performs some of the same actions
1048 that the @code{reset-init} event handler does.
1051 Likewise, the @command{arm9 vector_catch} command (or
1052 @cindex vector_catch
1053 its siblings @command{xscale vector_catch}
1054 and @command{cortex_m vector_catch}) can be a time-saver
1055 during some debug sessions, but don't make everyone use that either.
1056 Keep those kinds of debugging aids in your user config file,
1057 along with messaging and tracing setup.
1058 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1061 You might need to override some defaults.
1062 For example, you might need to move, shrink, or back up the target's
1063 work area if your application needs much SRAM.
1066 TCP/IP port configuration is another example of something which
1067 is environment-specific, and should only appear in
1068 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1071 @section Project-Specific Utilities
1073 A few project-specific utility
1074 routines may well speed up your work.
1075 Write them, and keep them in your project's user config file.
1077 For example, if you are making a boot loader work on a
1078 board, it's nice to be able to debug the ``after it's
1079 loaded to RAM'' parts separately from the finicky early
1080 code which sets up the DDR RAM controller and clocks.
1081 A script like this one, or a more GDB-aware sibling,
1085 proc ramboot @{ @} @{
1086 # Reset, running the target's "reset-init" scripts
1087 # to initialize clocks and the DDR RAM controller.
1088 # Leave the CPU halted.
1091 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1092 load_image u-boot.bin 0x20000000
1099 Then once that code is working you will need to make it
1100 boot from NOR flash; a different utility would help.
1101 Alternatively, some developers write to flash using GDB.
1102 (You might use a similar script if you're working with a flash
1103 based microcontroller application instead of a boot loader.)
1106 proc newboot @{ @} @{
1107 # Reset, leaving the CPU halted. The "reset-init" event
1108 # proc gives faster access to the CPU and to NOR flash;
1109 # "reset halt" would be slower.
1112 # Write standard version of U-Boot into the first two
1113 # sectors of NOR flash ... the standard version should
1114 # do the same lowlevel init as "reset-init".
1115 flash protect 0 0 1 off
1116 flash erase_sector 0 0 1
1117 flash write_bank 0 u-boot.bin 0x0
1118 flash protect 0 0 1 on
1120 # Reboot from scratch using that new boot loader.
1125 You may need more complicated utility procedures when booting
1127 That often involves an extra bootloader stage,
1128 running from on-chip SRAM to perform DDR RAM setup so it can load
1129 the main bootloader code (which won't fit into that SRAM).
1131 Other helper scripts might be used to write production system images,
1132 involving considerably more than just a three stage bootloader.
1134 @section Target Software Changes
1136 Sometimes you may want to make some small changes to the software
1137 you're developing, to help make JTAG debugging work better.
1138 For example, in C or assembly language code you might
1139 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1140 handling issues like:
1144 @item @b{Watchdog Timers}...
1145 Watchdog timers are typically used to automatically reset systems if
1146 some application task doesn't periodically reset the timer. (The
1147 assumption is that the system has locked up if the task can't run.)
1148 When a JTAG debugger halts the system, that task won't be able to run
1149 and reset the timer ... potentially causing resets in the middle of
1150 your debug sessions.
1152 It's rarely a good idea to disable such watchdogs, since their usage
1153 needs to be debugged just like all other parts of your firmware.
1154 That might however be your only option.
1156 Look instead for chip-specific ways to stop the watchdog from counting
1157 while the system is in a debug halt state. It may be simplest to set
1158 that non-counting mode in your debugger startup scripts. You may however
1159 need a different approach when, for example, a motor could be physically
1160 damaged by firmware remaining inactive in a debug halt state. That might
1161 involve a type of firmware mode where that "non-counting" mode is disabled
1162 at the beginning then re-enabled at the end; a watchdog reset might fire
1163 and complicate the debug session, but hardware (or people) would be
1164 protected.@footnote{Note that many systems support a "monitor mode" debug
1165 that is a somewhat cleaner way to address such issues. You can think of
1166 it as only halting part of the system, maybe just one task,
1167 instead of the whole thing.
1168 At this writing, January 2010, OpenOCD based debugging does not support
1169 monitor mode debug, only "halt mode" debug.}
1171 @item @b{ARM Semihosting}...
1172 @cindex ARM semihosting
1173 When linked with a special runtime library provided with many
1174 toolchains@footnote{See chapter 8 "Semihosting" in
1175 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1176 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1177 The CodeSourcery EABI toolchain also includes a semihosting library.},
1178 your target code can use I/O facilities on the debug host. That library
1179 provides a small set of system calls which are handled by OpenOCD.
1180 It can let the debugger provide your system console and a file system,
1181 helping with early debugging or providing a more capable environment
1182 for sometimes-complex tasks like installing system firmware onto
1185 @item @b{ARM Wait-For-Interrupt}...
1186 Many ARM chips synchronize the JTAG clock using the core clock.
1187 Low power states which stop that core clock thus prevent JTAG access.
1188 Idle loops in tasking environments often enter those low power states
1189 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1191 You may want to @emph{disable that instruction} in source code,
1192 or otherwise prevent using that state,
1193 to ensure you can get JTAG access at any time.@footnote{As a more
1194 polite alternative, some processors have special debug-oriented
1195 registers which can be used to change various features including
1196 how the low power states are clocked while debugging.
1197 The STM32 DBGMCU_CR register is an example; at the cost of extra
1198 power consumption, JTAG can be used during low power states.}
1199 For example, the OpenOCD @command{halt} command may not
1200 work for an idle processor otherwise.
1202 @item @b{Delay after reset}...
1203 Not all chips have good support for debugger access
1204 right after reset; many LPC2xxx chips have issues here.
1205 Similarly, applications that reconfigure pins used for
1206 JTAG access as they start will also block debugger access.
1208 To work with boards like this, @emph{enable a short delay loop}
1209 the first thing after reset, before "real" startup activities.
1210 For example, one second's delay is usually more than enough
1211 time for a JTAG debugger to attach, so that
1212 early code execution can be debugged
1213 or firmware can be replaced.
1215 @item @b{Debug Communications Channel (DCC)}...
1216 Some processors include mechanisms to send messages over JTAG.
1217 Many ARM cores support these, as do some cores from other vendors.
1218 (OpenOCD may be able to use this DCC internally, speeding up some
1219 operations like writing to memory.)
1221 Your application may want to deliver various debugging messages
1222 over JTAG, by @emph{linking with a small library of code}
1223 provided with OpenOCD and using the utilities there to send
1224 various kinds of message.
1225 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1229 @section Target Hardware Setup
1231 Chip vendors often provide software development boards which
1232 are highly configurable, so that they can support all options
1233 that product boards may require. @emph{Make sure that any
1234 jumpers or switches match the system configuration you are
1237 Common issues include:
1241 @item @b{JTAG setup} ...
1242 Boards may support more than one JTAG configuration.
1243 Examples include jumpers controlling pullups versus pulldowns
1244 on the nTRST and/or nSRST signals, and choice of connectors
1245 (e.g. which of two headers on the base board,
1246 or one from a daughtercard).
1247 For some Texas Instruments boards, you may need to jumper the
1248 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1250 @item @b{Boot Modes} ...
1251 Complex chips often support multiple boot modes, controlled
1252 by external jumpers. Make sure this is set up correctly.
1253 For example many i.MX boards from NXP need to be jumpered
1254 to "ATX mode" to start booting using the on-chip ROM, when
1255 using second stage bootloader code stored in a NAND flash chip.
1257 Such explicit configuration is common, and not limited to
1258 booting from NAND. You might also need to set jumpers to
1259 start booting using code loaded from an MMC/SD card; external
1260 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1261 flash; some external host; or various other sources.
1264 @item @b{Memory Addressing} ...
1265 Boards which support multiple boot modes may also have jumpers
1266 to configure memory addressing. One board, for example, jumpers
1267 external chipselect 0 (used for booting) to address either
1268 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1269 or NAND flash. When it's jumpered to address NAND flash, that
1270 board must also be told to start booting from on-chip ROM.
1272 Your @file{board.cfg} file may also need to be told this jumper
1273 configuration, so that it can know whether to declare NOR flash
1274 using @command{flash bank} or instead declare NAND flash with
1275 @command{nand device}; and likewise which probe to perform in
1276 its @code{reset-init} handler.
1278 A closely related issue is bus width. Jumpers might need to
1279 distinguish between 8 bit or 16 bit bus access for the flash
1280 used to start booting.
1282 @item @b{Peripheral Access} ...
1283 Development boards generally provide access to every peripheral
1284 on the chip, sometimes in multiple modes (such as by providing
1285 multiple audio codec chips).
1286 This interacts with software
1287 configuration of pin multiplexing, where for example a
1288 given pin may be routed either to the MMC/SD controller
1289 or the GPIO controller. It also often interacts with
1290 configuration jumpers. One jumper may be used to route
1291 signals to an MMC/SD card slot or an expansion bus (which
1292 might in turn affect booting); others might control which
1293 audio or video codecs are used.
1297 Plus you should of course have @code{reset-init} event handlers
1298 which set up the hardware to match that jumper configuration.
1299 That includes in particular any oscillator or PLL used to clock
1300 the CPU, and any memory controllers needed to access external
1301 memory and peripherals. Without such handlers, you won't be
1302 able to access those resources without working target firmware
1303 which can do that setup ... this can be awkward when you're
1304 trying to debug that target firmware. Even if there's a ROM
1305 bootloader which handles a few issues, it rarely provides full
1306 access to all board-specific capabilities.
1309 @node Config File Guidelines
1310 @chapter Config File Guidelines
1312 This chapter is aimed at any user who needs to write a config file,
1313 including developers and integrators of OpenOCD and any user who
1314 needs to get a new board working smoothly.
1315 It provides guidelines for creating those files.
1317 You should find the following directories under
1318 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1319 them as-is where you can; or as models for new files.
1321 @item @file{interface} ...
1322 These are for debug adapters. Files that specify configuration to use
1323 specific JTAG, SWD and other adapters go here.
1324 @item @file{board} ...
1325 Think Circuit Board, PWA, PCB, they go by many names. Board files
1326 contain initialization items that are specific to a board.
1328 They reuse target configuration files, since the same
1329 microprocessor chips are used on many boards,
1330 but support for external parts varies widely. For
1331 example, the SDRAM initialization sequence for the board, or the type
1332 of external flash and what address it uses. Any initialization
1333 sequence to enable that external flash or SDRAM should be found in the
1334 board file. Boards may also contain multiple targets: two CPUs; or
1336 @item @file{target} ...
1337 Think chip. The ``target'' directory represents the JTAG TAPs
1339 which OpenOCD should control, not a board. Two common types of targets
1340 are ARM chips and FPGA or CPLD chips.
1341 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1342 the target config file defines all of them.
1343 @item @emph{more} ... browse for other library files which may be useful.
1344 For example, there are various generic and CPU-specific utilities.
1347 The @file{openocd.cfg} user config
1348 file may override features in any of the above files by
1349 setting variables before sourcing the target file, or by adding
1350 commands specific to their situation.
1352 @section Interface Config Files
1354 The user config file
1355 should be able to source one of these files with a command like this:
1358 source [find interface/FOOBAR.cfg]
1361 A preconfigured interface file should exist for every debug adapter
1362 in use today with OpenOCD.
1363 That said, perhaps some of these config files
1364 have only been used by the developer who created it.
1366 A separate chapter gives information about how to set these up.
1367 @xref{Debug Adapter Configuration}.
1368 Read the OpenOCD source code (and Developer's Guide)
1369 if you have a new kind of hardware interface
1370 and need to provide a driver for it.
1372 @section Board Config Files
1373 @cindex config file, board
1374 @cindex board config file
1376 The user config file
1377 should be able to source one of these files with a command like this:
1380 source [find board/FOOBAR.cfg]
1383 The point of a board config file is to package everything
1384 about a given board that user config files need to know.
1385 In summary the board files should contain (if present)
1388 @item One or more @command{source [find target/...cfg]} statements
1389 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1390 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1391 @item Target @code{reset} handlers for SDRAM and I/O configuration
1392 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1393 @item All things that are not ``inside a chip''
1396 Generic things inside target chips belong in target config files,
1397 not board config files. So for example a @code{reset-init} event
1398 handler should know board-specific oscillator and PLL parameters,
1399 which it passes to target-specific utility code.
1401 The most complex task of a board config file is creating such a
1402 @code{reset-init} event handler.
1403 Define those handlers last, after you verify the rest of the board
1404 configuration works.
1406 @subsection Communication Between Config files
1408 In addition to target-specific utility code, another way that
1409 board and target config files communicate is by following a
1410 convention on how to use certain variables.
1412 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1413 Thus the rule we follow in OpenOCD is this: Variables that begin with
1414 a leading underscore are temporary in nature, and can be modified and
1415 used at will within a target configuration file.
1417 Complex board config files can do the things like this,
1418 for a board with three chips:
1421 # Chip #1: PXA270 for network side, big endian
1422 set CHIPNAME network
1424 source [find target/pxa270.cfg]
1425 # on return: _TARGETNAME = network.cpu
1426 # other commands can refer to the "network.cpu" target.
1427 $_TARGETNAME configure .... events for this CPU..
1429 # Chip #2: PXA270 for video side, little endian
1432 source [find target/pxa270.cfg]
1433 # on return: _TARGETNAME = video.cpu
1434 # other commands can refer to the "video.cpu" target.
1435 $_TARGETNAME configure .... events for this CPU..
1437 # Chip #3: Xilinx FPGA for glue logic
1440 source [find target/spartan3.cfg]
1443 That example is oversimplified because it doesn't show any flash memory,
1444 or the @code{reset-init} event handlers to initialize external DRAM
1445 or (assuming it needs it) load a configuration into the FPGA.
1446 Such features are usually needed for low-level work with many boards,
1447 where ``low level'' implies that the board initialization software may
1448 not be working. (That's a common reason to need JTAG tools. Another
1449 is to enable working with microcontroller-based systems, which often
1450 have no debugging support except a JTAG connector.)
1452 Target config files may also export utility functions to board and user
1453 config files. Such functions should use name prefixes, to help avoid
1456 Board files could also accept input variables from user config files.
1457 For example, there might be a @code{J4_JUMPER} setting used to identify
1458 what kind of flash memory a development board is using, or how to set
1459 up other clocks and peripherals.
1461 @subsection Variable Naming Convention
1462 @cindex variable names
1464 Most boards have only one instance of a chip.
1465 However, it should be easy to create a board with more than
1466 one such chip (as shown above).
1467 Accordingly, we encourage these conventions for naming
1468 variables associated with different @file{target.cfg} files,
1469 to promote consistency and
1470 so that board files can override target defaults.
1472 Inputs to target config files include:
1475 @item @code{CHIPNAME} ...
1476 This gives a name to the overall chip, and is used as part of
1477 tap identifier dotted names.
1478 While the default is normally provided by the chip manufacturer,
1479 board files may need to distinguish between instances of a chip.
1480 @item @code{ENDIAN} ...
1481 By default @option{little} - although chips may hard-wire @option{big}.
1482 Chips that can't change endianess don't need to use this variable.
1483 @item @code{CPUTAPID} ...
1484 When OpenOCD examines the JTAG chain, it can be told verify the
1485 chips against the JTAG IDCODE register.
1486 The target file will hold one or more defaults, but sometimes the
1487 chip in a board will use a different ID (perhaps a newer revision).
1490 Outputs from target config files include:
1493 @item @code{_TARGETNAME} ...
1494 By convention, this variable is created by the target configuration
1495 script. The board configuration file may make use of this variable to
1496 configure things like a ``reset init'' script, or other things
1497 specific to that board and that target.
1498 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1499 @code{_TARGETNAME1}, ... etc.
1502 @subsection The reset-init Event Handler
1503 @cindex event, reset-init
1504 @cindex reset-init handler
1506 Board config files run in the OpenOCD configuration stage;
1507 they can't use TAPs or targets, since they haven't been
1509 This means you can't write memory or access chip registers;
1510 you can't even verify that a flash chip is present.
1511 That's done later in event handlers, of which the target @code{reset-init}
1512 handler is one of the most important.
1514 Except on microcontrollers, the basic job of @code{reset-init} event
1515 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1516 Microcontrollers rarely use boot loaders; they run right out of their
1517 on-chip flash and SRAM memory. But they may want to use one of these
1518 handlers too, if just for developer convenience.
1521 Because this is so very board-specific, and chip-specific, no examples
1523 Instead, look at the board config files distributed with OpenOCD.
1524 If you have a boot loader, its source code will help; so will
1525 configuration files for other JTAG tools
1526 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1529 Some of this code could probably be shared between different boards.
1530 For example, setting up a DRAM controller often doesn't differ by
1531 much except the bus width (16 bits or 32?) and memory timings, so a
1532 reusable TCL procedure loaded by the @file{target.cfg} file might take
1533 those as parameters.
1534 Similarly with oscillator, PLL, and clock setup;
1535 and disabling the watchdog.
1536 Structure the code cleanly, and provide comments to help
1537 the next developer doing such work.
1538 (@emph{You might be that next person} trying to reuse init code!)
1540 The last thing normally done in a @code{reset-init} handler is probing
1541 whatever flash memory was configured. For most chips that needs to be
1542 done while the associated target is halted, either because JTAG memory
1543 access uses the CPU or to prevent conflicting CPU access.
1545 @subsection JTAG Clock Rate
1547 Before your @code{reset-init} handler has set up
1548 the PLLs and clocking, you may need to run with
1549 a low JTAG clock rate.
1550 @xref{jtagspeed,,JTAG Speed}.
1551 Then you'd increase that rate after your handler has
1552 made it possible to use the faster JTAG clock.
1553 When the initial low speed is board-specific, for example
1554 because it depends on a board-specific oscillator speed, then
1555 you should probably set it up in the board config file;
1556 if it's target-specific, it belongs in the target config file.
1558 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1559 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1560 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1561 Consult chip documentation to determine the peak JTAG clock rate,
1562 which might be less than that.
1565 On most ARMs, JTAG clock detection is coupled to the core clock, so
1566 software using a @option{wait for interrupt} operation blocks JTAG access.
1567 Adaptive clocking provides a partial workaround, but a more complete
1568 solution just avoids using that instruction with JTAG debuggers.
1571 If both the chip and the board support adaptive clocking,
1572 use the @command{jtag_rclk}
1573 command, in case your board is used with JTAG adapter which
1574 also supports it. Otherwise use @command{adapter_khz}.
1575 Set the slow rate at the beginning of the reset sequence,
1576 and the faster rate as soon as the clocks are at full speed.
1578 @anchor{theinitboardprocedure}
1579 @subsection The init_board procedure
1580 @cindex init_board procedure
1582 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1583 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1584 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1585 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1586 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1587 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1588 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1589 Additionally ``linear'' board config file will most likely fail when target config file uses
1590 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1591 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1592 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1593 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1595 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1596 the original), allowing greater code reuse.
1599 ### board_file.cfg ###
1601 # source target file that does most of the config in init_targets
1602 source [find target/target.cfg]
1604 proc enable_fast_clock @{@} @{
1605 # enables fast on-board clock source
1606 # configures the chip to use it
1609 # initialize only board specifics - reset, clock, adapter frequency
1610 proc init_board @{@} @{
1611 reset_config trst_and_srst trst_pulls_srst
1613 $_TARGETNAME configure -event reset-start @{
1617 $_TARGETNAME configure -event reset-init @{
1624 @section Target Config Files
1625 @cindex config file, target
1626 @cindex target config file
1628 Board config files communicate with target config files using
1629 naming conventions as described above, and may source one or
1630 more target config files like this:
1633 source [find target/FOOBAR.cfg]
1636 The point of a target config file is to package everything
1637 about a given chip that board config files need to know.
1638 In summary the target files should contain
1642 @item Add TAPs to the scan chain
1643 @item Add CPU targets (includes GDB support)
1644 @item CPU/Chip/CPU-Core specific features
1648 As a rule of thumb, a target file sets up only one chip.
1649 For a microcontroller, that will often include a single TAP,
1650 which is a CPU needing a GDB target, and its on-chip flash.
1652 More complex chips may include multiple TAPs, and the target
1653 config file may need to define them all before OpenOCD
1654 can talk to the chip.
1655 For example, some phone chips have JTAG scan chains that include
1656 an ARM core for operating system use, a DSP,
1657 another ARM core embedded in an image processing engine,
1658 and other processing engines.
1660 @subsection Default Value Boiler Plate Code
1662 All target configuration files should start with code like this,
1663 letting board config files express environment-specific
1664 differences in how things should be set up.
1667 # Boards may override chip names, perhaps based on role,
1668 # but the default should match what the vendor uses
1669 if @{ [info exists CHIPNAME] @} @{
1670 set _CHIPNAME $CHIPNAME
1672 set _CHIPNAME sam7x256
1675 # ONLY use ENDIAN with targets that can change it.
1676 if @{ [info exists ENDIAN] @} @{
1682 # TAP identifiers may change as chips mature, for example with
1683 # new revision fields (the "3" here). Pick a good default; you
1684 # can pass several such identifiers to the "jtag newtap" command.
1685 if @{ [info exists CPUTAPID ] @} @{
1686 set _CPUTAPID $CPUTAPID
1688 set _CPUTAPID 0x3f0f0f0f
1691 @c but 0x3f0f0f0f is for an str73x part ...
1693 @emph{Remember:} Board config files may include multiple target
1694 config files, or the same target file multiple times
1695 (changing at least @code{CHIPNAME}).
1697 Likewise, the target configuration file should define
1698 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1699 use it later on when defining debug targets:
1702 set _TARGETNAME $_CHIPNAME.cpu
1703 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1706 @subsection Adding TAPs to the Scan Chain
1707 After the ``defaults'' are set up,
1708 add the TAPs on each chip to the JTAG scan chain.
1709 @xref{TAP Declaration}, and the naming convention
1712 In the simplest case the chip has only one TAP,
1713 probably for a CPU or FPGA.
1714 The config file for the Atmel AT91SAM7X256
1715 looks (in part) like this:
1718 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1721 A board with two such at91sam7 chips would be able
1722 to source such a config file twice, with different
1723 values for @code{CHIPNAME}, so
1724 it adds a different TAP each time.
1726 If there are nonzero @option{-expected-id} values,
1727 OpenOCD attempts to verify the actual tap id against those values.
1728 It will issue error messages if there is mismatch, which
1729 can help to pinpoint problems in OpenOCD configurations.
1732 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1733 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1734 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1735 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1736 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1739 There are more complex examples too, with chips that have
1740 multiple TAPs. Ones worth looking at include:
1743 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1744 plus a JRC to enable them
1745 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1746 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1747 is not currently used)
1750 @subsection Add CPU targets
1752 After adding a TAP for a CPU, you should set it up so that
1753 GDB and other commands can use it.
1754 @xref{CPU Configuration}.
1755 For the at91sam7 example above, the command can look like this;
1756 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1757 to little endian, and this chip doesn't support changing that.
1760 set _TARGETNAME $_CHIPNAME.cpu
1761 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1764 Work areas are small RAM areas associated with CPU targets.
1765 They are used by OpenOCD to speed up downloads,
1766 and to download small snippets of code to program flash chips.
1767 If the chip includes a form of ``on-chip-ram'' - and many do - define
1768 a work area if you can.
1769 Again using the at91sam7 as an example, this can look like:
1772 $_TARGETNAME configure -work-area-phys 0x00200000 \
1773 -work-area-size 0x4000 -work-area-backup 0
1776 @anchor{definecputargetsworkinginsmp}
1777 @subsection Define CPU targets working in SMP
1779 After setting targets, you can define a list of targets working in SMP.
1782 set _TARGETNAME_1 $_CHIPNAME.cpu1
1783 set _TARGETNAME_2 $_CHIPNAME.cpu2
1784 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1785 -coreid 0 -dbgbase $_DAP_DBG1
1786 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1787 -coreid 1 -dbgbase $_DAP_DBG2
1788 #define 2 targets working in smp.
1789 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1791 In the above example on cortex_a, 2 cpus are working in SMP.
1792 In SMP only one GDB instance is created and :
1794 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1795 @item halt command triggers the halt of all targets in the list.
1796 @item resume command triggers the write context and the restart of all targets in the list.
1797 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1798 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1799 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1802 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1803 command have been implemented.
1805 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1806 @item cortex_a smp_off : disable SMP mode, the current target is the one
1807 displayed in the GDB session, only this target is now controlled by GDB
1808 session. This behaviour is useful during system boot up.
1809 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1816 #0 : coreid 0 is displayed to GDB ,
1817 #-> -1 : next resume triggers a real resume
1818 > cortex_a smp_gdb 1
1820 #0 :coreid 0 is displayed to GDB ,
1821 #->1 : next resume displays coreid 1 to GDB
1825 #1 :coreid 1 is displayed to GDB ,
1826 #->1 : next resume displays coreid 1 to GDB
1827 > cortex_a smp_gdb -1
1829 #1 :coreid 1 is displayed to GDB,
1830 #->-1 : next resume triggers a real resume
1834 @subsection Chip Reset Setup
1836 As a rule, you should put the @command{reset_config} command
1837 into the board file. Most things you think you know about a
1838 chip can be tweaked by the board.
1840 Some chips have specific ways the TRST and SRST signals are
1841 managed. In the unusual case that these are @emph{chip specific}
1842 and can never be changed by board wiring, they could go here.
1843 For example, some chips can't support JTAG debugging without
1846 Provide a @code{reset-assert} event handler if you can.
1847 Such a handler uses JTAG operations to reset the target,
1848 letting this target config be used in systems which don't
1849 provide the optional SRST signal, or on systems where you
1850 don't want to reset all targets at once.
1851 Such a handler might write to chip registers to force a reset,
1852 use a JRC to do that (preferable -- the target may be wedged!),
1853 or force a watchdog timer to trigger.
1854 (For Cortex-M targets, this is not necessary. The target
1855 driver knows how to use trigger an NVIC reset when SRST is
1858 Some chips need special attention during reset handling if
1859 they're going to be used with JTAG.
1860 An example might be needing to send some commands right
1861 after the target's TAP has been reset, providing a
1862 @code{reset-deassert-post} event handler that writes a chip
1863 register to report that JTAG debugging is being done.
1864 Another would be reconfiguring the watchdog so that it stops
1865 counting while the core is halted in the debugger.
1867 JTAG clocking constraints often change during reset, and in
1868 some cases target config files (rather than board config files)
1869 are the right places to handle some of those issues.
1870 For example, immediately after reset most chips run using a
1871 slower clock than they will use later.
1872 That means that after reset (and potentially, as OpenOCD
1873 first starts up) they must use a slower JTAG clock rate
1874 than they will use later.
1875 @xref{jtagspeed,,JTAG Speed}.
1877 @quotation Important
1878 When you are debugging code that runs right after chip
1879 reset, getting these issues right is critical.
1880 In particular, if you see intermittent failures when
1881 OpenOCD verifies the scan chain after reset,
1882 look at how you are setting up JTAG clocking.
1885 @anchor{theinittargetsprocedure}
1886 @subsection The init_targets procedure
1887 @cindex init_targets procedure
1889 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1890 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1891 procedure called @code{init_targets}, which will be executed when entering run stage
1892 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1893 Such procedure can be overridden by ``next level'' script (which sources the original).
1894 This concept facilitates code reuse when basic target config files provide generic configuration
1895 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1896 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1897 because sourcing them executes every initialization commands they provide.
1900 ### generic_file.cfg ###
1902 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1903 # basic initialization procedure ...
1906 proc init_targets @{@} @{
1907 # initializes generic chip with 4kB of flash and 1kB of RAM
1908 setup_my_chip MY_GENERIC_CHIP 4096 1024
1911 ### specific_file.cfg ###
1913 source [find target/generic_file.cfg]
1915 proc init_targets @{@} @{
1916 # initializes specific chip with 128kB of flash and 64kB of RAM
1917 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1921 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1922 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1924 For an example of this scheme see LPC2000 target config files.
1926 The @code{init_boards} procedure is a similar concept concerning board config files
1927 (@xref{theinitboardprocedure,,The init_board procedure}.)
1929 @anchor{theinittargeteventsprocedure}
1930 @subsection The init_target_events procedure
1931 @cindex init_target_events procedure
1933 A special procedure called @code{init_target_events} is run just after
1934 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1935 procedure}.) and before @code{init_board}
1936 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1937 to set up default target events for the targets that do not have those
1938 events already assigned.
1940 @subsection ARM Core Specific Hacks
1942 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1943 special high speed download features - enable it.
1945 If present, the MMU, the MPU and the CACHE should be disabled.
1947 Some ARM cores are equipped with trace support, which permits
1948 examination of the instruction and data bus activity. Trace
1949 activity is controlled through an ``Embedded Trace Module'' (ETM)
1950 on one of the core's scan chains. The ETM emits voluminous data
1951 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1952 If you are using an external trace port,
1953 configure it in your board config file.
1954 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1955 configure it in your target config file.
1958 etm config $_TARGETNAME 16 normal full etb
1959 etb config $_TARGETNAME $_CHIPNAME.etb
1962 @subsection Internal Flash Configuration
1964 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1966 @b{Never ever} in the ``target configuration file'' define any type of
1967 flash that is external to the chip. (For example a BOOT flash on
1968 Chip Select 0.) Such flash information goes in a board file - not
1969 the TARGET (chip) file.
1973 @item at91sam7x256 - has 256K flash YES enable it.
1974 @item str912 - has flash internal YES enable it.
1975 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1976 @item pxa270 - again - CS0 flash - it goes in the board file.
1979 @anchor{translatingconfigurationfiles}
1980 @section Translating Configuration Files
1982 If you have a configuration file for another hardware debugger
1983 or toolset (Abatron, BDI2000, BDI3000, CCS,
1984 Lauterbach, SEGGER, Macraigor, etc.), translating
1985 it into OpenOCD syntax is often quite straightforward. The most tricky
1986 part of creating a configuration script is oftentimes the reset init
1987 sequence where e.g. PLLs, DRAM and the like is set up.
1989 One trick that you can use when translating is to write small
1990 Tcl procedures to translate the syntax into OpenOCD syntax. This
1991 can avoid manual translation errors and make it easier to
1992 convert other scripts later on.
1994 Example of transforming quirky arguments to a simple search and
1998 # Lauterbach syntax(?)
2000 # Data.Set c15:0x042f %long 0x40000015
2002 # OpenOCD syntax when using procedure below.
2004 # setc15 0x01 0x00050078
2006 proc setc15 @{regs value@} @{
2009 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2011 arm mcr 15 [expr ($regs>>12)&0x7] \
2012 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2013 [expr ($regs>>8)&0x7] $value
2019 @node Server Configuration
2020 @chapter Server Configuration
2021 @cindex initialization
2022 The commands here are commonly found in the openocd.cfg file and are
2023 used to specify what TCP/IP ports are used, and how GDB should be
2026 @anchor{configurationstage}
2027 @section Configuration Stage
2028 @cindex configuration stage
2029 @cindex config command
2031 When the OpenOCD server process starts up, it enters a
2032 @emph{configuration stage} which is the only time that
2033 certain commands, @emph{configuration commands}, may be issued.
2034 Normally, configuration commands are only available
2035 inside startup scripts.
2037 In this manual, the definition of a configuration command is
2038 presented as a @emph{Config Command}, not as a @emph{Command}
2039 which may be issued interactively.
2040 The runtime @command{help} command also highlights configuration
2041 commands, and those which may be issued at any time.
2043 Those configuration commands include declaration of TAPs,
2045 the interface used for JTAG communication,
2046 and other basic setup.
2047 The server must leave the configuration stage before it
2048 may access or activate TAPs.
2049 After it leaves this stage, configuration commands may no
2052 @anchor{enteringtherunstage}
2053 @section Entering the Run Stage
2055 The first thing OpenOCD does after leaving the configuration
2056 stage is to verify that it can talk to the scan chain
2057 (list of TAPs) which has been configured.
2058 It will warn if it doesn't find TAPs it expects to find,
2059 or finds TAPs that aren't supposed to be there.
2060 You should see no errors at this point.
2061 If you see errors, resolve them by correcting the
2062 commands you used to configure the server.
2063 Common errors include using an initial JTAG speed that's too
2064 fast, and not providing the right IDCODE values for the TAPs
2067 Once OpenOCD has entered the run stage, a number of commands
2069 A number of these relate to the debug targets you may have declared.
2070 For example, the @command{mww} command will not be available until
2071 a target has been successfully instantiated.
2072 If you want to use those commands, you may need to force
2073 entry to the run stage.
2075 @deffn {Config Command} init
2076 This command terminates the configuration stage and
2077 enters the run stage. This helps when you need to have
2078 the startup scripts manage tasks such as resetting the target,
2079 programming flash, etc. To reset the CPU upon startup, add "init" and
2080 "reset" at the end of the config script or at the end of the OpenOCD
2081 command line using the @option{-c} command line switch.
2083 If this command does not appear in any startup/configuration file
2084 OpenOCD executes the command for you after processing all
2085 configuration files and/or command line options.
2087 @b{NOTE:} This command normally occurs at or near the end of your
2088 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2089 targets ready. For example: If your openocd.cfg file needs to
2090 read/write memory on your target, @command{init} must occur before
2091 the memory read/write commands. This includes @command{nand probe}.
2094 @deffn {Overridable Procedure} jtag_init
2095 This is invoked at server startup to verify that it can talk
2096 to the scan chain (list of TAPs) which has been configured.
2098 The default implementation first tries @command{jtag arp_init},
2099 which uses only a lightweight JTAG reset before examining the
2101 If that fails, it tries again, using a harder reset
2102 from the overridable procedure @command{init_reset}.
2104 Implementations must have verified the JTAG scan chain before
2106 This is done by calling @command{jtag arp_init}
2107 (or @command{jtag arp_init-reset}).
2111 @section TCP/IP Ports
2116 The OpenOCD server accepts remote commands in several syntaxes.
2117 Each syntax uses a different TCP/IP port, which you may specify
2118 only during configuration (before those ports are opened).
2120 For reasons including security, you may wish to prevent remote
2121 access using one or more of these ports.
2122 In such cases, just specify the relevant port number as "disabled".
2123 If you disable all access through TCP/IP, you will need to
2124 use the command line @option{-pipe} option.
2127 @deffn {Command} gdb_port [number]
2129 Normally gdb listens to a TCP/IP port, but GDB can also
2130 communicate via pipes(stdin/out or named pipes). The name
2131 "gdb_port" stuck because it covers probably more than 90% of
2132 the normal use cases.
2134 No arguments reports GDB port. "pipe" means listen to stdin
2135 output to stdout, an integer is base port number, "disabled"
2136 disables the gdb server.
2138 When using "pipe", also use log_output to redirect the log
2139 output to a file so as not to flood the stdin/out pipes.
2141 The -p/--pipe option is deprecated and a warning is printed
2142 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2144 Any other string is interpreted as named pipe to listen to.
2145 Output pipe is the same name as input pipe, but with 'o' appended,
2146 e.g. /var/gdb, /var/gdbo.
2148 The GDB port for the first target will be the base port, the
2149 second target will listen on gdb_port + 1, and so on.
2150 When not specified during the configuration stage,
2151 the port @var{number} defaults to 3333.
2152 When @var{number} is not a numeric value, incrementing it to compute
2153 the next port number does not work. In this case, specify the proper
2154 @var{number} for each target by using the option @code{-gdb-port} of the
2155 commands @command{target create} or @command{$target_name configure}.
2156 @xref{gdbportoverride,,option -gdb-port}.
2158 Note: when using "gdb_port pipe", increasing the default remote timeout in
2159 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2160 cause initialization to fail with "Unknown remote qXfer reply: OK".
2163 @deffn {Command} tcl_port [number]
2164 Specify or query the port used for a simplified RPC
2165 connection that can be used by clients to issue TCL commands and get the
2166 output from the Tcl engine.
2167 Intended as a machine interface.
2168 When not specified during the configuration stage,
2169 the port @var{number} defaults to 6666.
2170 When specified as "disabled", this service is not activated.
2173 @deffn {Command} telnet_port [number]
2174 Specify or query the
2175 port on which to listen for incoming telnet connections.
2176 This port is intended for interaction with one human through TCL commands.
2177 When not specified during the configuration stage,
2178 the port @var{number} defaults to 4444.
2179 When specified as "disabled", this service is not activated.
2182 @anchor{gdbconfiguration}
2183 @section GDB Configuration
2185 @cindex GDB configuration
2186 You can reconfigure some GDB behaviors if needed.
2187 The ones listed here are static and global.
2188 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2189 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2191 @anchor{gdbbreakpointoverride}
2192 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2193 Force breakpoint type for gdb @command{break} commands.
2194 This option supports GDB GUIs which don't
2195 distinguish hard versus soft breakpoints, if the default OpenOCD and
2196 GDB behaviour is not sufficient. GDB normally uses hardware
2197 breakpoints if the memory map has been set up for flash regions.
2200 @anchor{gdbflashprogram}
2201 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2202 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2203 vFlash packet is received.
2204 The default behaviour is @option{enable}.
2207 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2208 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2209 requested. GDB will then know when to set hardware breakpoints, and program flash
2210 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2211 for flash programming to work.
2212 Default behaviour is @option{enable}.
2213 @xref{gdbflashprogram,,gdb_flash_program}.
2216 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2217 Specifies whether data aborts cause an error to be reported
2218 by GDB memory read packets.
2219 The default behaviour is @option{disable};
2220 use @option{enable} see these errors reported.
2223 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2224 Specifies whether register accesses requested by GDB register read/write
2225 packets report errors or not.
2226 The default behaviour is @option{disable};
2227 use @option{enable} see these errors reported.
2230 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2231 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2232 The default behaviour is @option{enable}.
2235 @deffn {Command} gdb_save_tdesc
2236 Saves the target description file to the local file system.
2238 The file name is @i{target_name}.xml.
2241 @anchor{eventpolling}
2242 @section Event Polling
2244 Hardware debuggers are parts of asynchronous systems,
2245 where significant events can happen at any time.
2246 The OpenOCD server needs to detect some of these events,
2247 so it can report them to through TCL command line
2250 Examples of such events include:
2253 @item One of the targets can stop running ... maybe it triggers
2254 a code breakpoint or data watchpoint, or halts itself.
2255 @item Messages may be sent over ``debug message'' channels ... many
2256 targets support such messages sent over JTAG,
2257 for receipt by the person debugging or tools.
2258 @item Loss of power ... some adapters can detect these events.
2259 @item Resets not issued through JTAG ... such reset sources
2260 can include button presses or other system hardware, sometimes
2261 including the target itself (perhaps through a watchdog).
2262 @item Debug instrumentation sometimes supports event triggering
2263 such as ``trace buffer full'' (so it can quickly be emptied)
2264 or other signals (to correlate with code behavior).
2267 None of those events are signaled through standard JTAG signals.
2268 However, most conventions for JTAG connectors include voltage
2269 level and system reset (SRST) signal detection.
2270 Some connectors also include instrumentation signals, which
2271 can imply events when those signals are inputs.
2273 In general, OpenOCD needs to periodically check for those events,
2274 either by looking at the status of signals on the JTAG connector
2275 or by sending synchronous ``tell me your status'' JTAG requests
2276 to the various active targets.
2277 There is a command to manage and monitor that polling,
2278 which is normally done in the background.
2280 @deffn Command poll [@option{on}|@option{off}]
2281 Poll the current target for its current state.
2282 (Also, @pxref{targetcurstate,,target curstate}.)
2283 If that target is in debug mode, architecture
2284 specific information about the current state is printed.
2285 An optional parameter
2286 allows background polling to be enabled and disabled.
2288 You could use this from the TCL command shell, or
2289 from GDB using @command{monitor poll} command.
2290 Leave background polling enabled while you're using GDB.
2293 background polling: on
2294 target state: halted
2295 target halted in ARM state due to debug-request, \
2296 current mode: Supervisor
2297 cpsr: 0x800000d3 pc: 0x11081bfc
2298 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2303 @node Debug Adapter Configuration
2304 @chapter Debug Adapter Configuration
2305 @cindex config file, interface
2306 @cindex interface config file
2308 Correctly installing OpenOCD includes making your operating system give
2309 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2310 are used to select which one is used, and to configure how it is used.
2313 Because OpenOCD started out with a focus purely on JTAG, you may find
2314 places where it wrongly presumes JTAG is the only transport protocol
2315 in use. Be aware that recent versions of OpenOCD are removing that
2316 limitation. JTAG remains more functional than most other transports.
2317 Other transports do not support boundary scan operations, or may be
2318 specific to a given chip vendor. Some might be usable only for
2319 programming flash memory, instead of also for debugging.
2322 Debug Adapters/Interfaces/Dongles are normally configured
2323 through commands in an interface configuration
2324 file which is sourced by your @file{openocd.cfg} file, or
2325 through a command line @option{-f interface/....cfg} option.
2328 source [find interface/olimex-jtag-tiny.cfg]
2332 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2333 A few cases are so simple that you only need to say what driver to use:
2340 Most adapters need a bit more configuration than that.
2343 @section Interface Configuration
2345 The interface command tells OpenOCD what type of debug adapter you are
2346 using. Depending on the type of adapter, you may need to use one or
2347 more additional commands to further identify or configure the adapter.
2349 @deffn {Config Command} {interface} name
2350 Use the interface driver @var{name} to connect to the
2354 @deffn Command {interface_list}
2355 List the debug adapter drivers that have been built into
2356 the running copy of OpenOCD.
2358 @deffn Command {interface transports} transport_name+
2359 Specifies the transports supported by this debug adapter.
2360 The adapter driver builds-in similar knowledge; use this only
2361 when external configuration (such as jumpering) changes what
2362 the hardware can support.
2367 @deffn Command {adapter_name}
2368 Returns the name of the debug adapter driver being used.
2371 @anchor{adapter_usb_location}
2372 @deffn Command {adapter usb location} <bus>-<port>[.<port>]...
2373 Specifies the physical USB port of the adapter to use. The path
2374 roots at @var{bus} and walks down the physical ports, with each
2375 @var{port} option specifying a deeper level in the bus topology, the last
2376 @var{port} denoting where the target adapter is actually plugged.
2377 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2379 This command is only available if your libusb1 is at least version 1.0.16.
2382 @section Interface Drivers
2384 Each of the interface drivers listed here must be explicitly
2385 enabled when OpenOCD is configured, in order to be made
2386 available at run time.
2388 @deffn {Interface Driver} {amt_jtagaccel}
2389 Amontec Chameleon in its JTAG Accelerator configuration,
2390 connected to a PC's EPP mode parallel port.
2391 This defines some driver-specific commands:
2393 @deffn {Config Command} {parport_port} number
2394 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2395 the number of the @file{/dev/parport} device.
2398 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2399 Displays status of RTCK option.
2400 Optionally sets that option first.
2404 @deffn {Interface Driver} {arm-jtag-ew}
2405 Olimex ARM-JTAG-EW USB adapter
2406 This has one driver-specific command:
2408 @deffn Command {armjtagew_info}
2413 @deffn {Interface Driver} {at91rm9200}
2414 Supports bitbanged JTAG from the local system,
2415 presuming that system is an Atmel AT91rm9200
2416 and a specific set of GPIOs is used.
2417 @c command: at91rm9200_device NAME
2418 @c chooses among list of bit configs ... only one option
2421 @deffn {Interface Driver} {cmsis-dap}
2422 ARM CMSIS-DAP compliant based adapter.
2424 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2425 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2426 the driver will attempt to auto detect the CMSIS-DAP device.
2427 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2429 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2433 @deffn {Config Command} {cmsis_dap_serial} [serial]
2434 Specifies the @var{serial} of the CMSIS-DAP device to use.
2435 If not specified, serial numbers are not considered.
2438 @deffn {Command} {cmsis-dap info}
2439 Display various device information, like hardware version, firmware version, current bus status.
2443 @deffn {Interface Driver} {dummy}
2444 A dummy software-only driver for debugging.
2447 @deffn {Interface Driver} {ep93xx}
2448 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2451 @deffn {Interface Driver} {ftdi}
2452 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2453 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2455 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2456 bypassing intermediate libraries like libftdi or D2XX.
2458 Support for new FTDI based adapters can be added completely through
2459 configuration files, without the need to patch and rebuild OpenOCD.
2461 The driver uses a signal abstraction to enable Tcl configuration files to
2462 define outputs for one or several FTDI GPIO. These outputs can then be
2463 controlled using the @command{ftdi_set_signal} command. Special signal names
2464 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2465 will be used for their customary purpose. Inputs can be read using the
2466 @command{ftdi_get_signal} command.
2468 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2469 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2470 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2471 required by the protocol, to tell the adapter to drive the data output onto
2472 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2474 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2475 be controlled differently. In order to support tristateable signals such as
2476 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2477 signal. The following output buffer configurations are supported:
2480 @item Push-pull with one FTDI output as (non-)inverted data line
2481 @item Open drain with one FTDI output as (non-)inverted output-enable
2482 @item Tristate with one FTDI output as (non-)inverted data line and another
2483 FTDI output as (non-)inverted output-enable
2484 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2485 switching data and direction as necessary
2488 These interfaces have several commands, used to configure the driver
2489 before initializing the JTAG scan chain:
2491 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2492 The vendor ID and product ID of the adapter. Up to eight
2493 [@var{vid}, @var{pid}] pairs may be given, e.g.
2495 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2499 @deffn {Config Command} {ftdi_device_desc} description
2500 Provides the USB device description (the @emph{iProduct string})
2501 of the adapter. If not specified, the device description is ignored
2502 during device selection.
2505 @deffn {Config Command} {ftdi_serial} serial-number
2506 Specifies the @var{serial-number} of the adapter to use,
2507 in case the vendor provides unique IDs and more than one adapter
2508 is connected to the host.
2509 If not specified, serial numbers are not considered.
2510 (Note that USB serial numbers can be arbitrary Unicode strings,
2511 and are not restricted to containing only decimal digits.)
2514 @deffn {Config Command} {ftdi_location} <bus>-<port>[.<port>]...
2515 @emph{DEPRECATED -- avoid using this.
2516 Use the @xref{adapter_usb_location, adapter usb location} command instead.}
2518 Specifies the physical USB port of the adapter to use. The path
2519 roots at @var{bus} and walks down the physical ports, with each
2520 @var{port} option specifying a deeper level in the bus topology, the last
2521 @var{port} denoting where the target adapter is actually plugged.
2522 The USB bus topology can be queried with the command @emph{lsusb -t}.
2524 This command is only available if your libusb1 is at least version 1.0.16.
2527 @deffn {Config Command} {ftdi_channel} channel
2528 Selects the channel of the FTDI device to use for MPSSE operations. Most
2529 adapters use the default, channel 0, but there are exceptions.
2532 @deffn {Config Command} {ftdi_layout_init} data direction
2533 Specifies the initial values of the FTDI GPIO data and direction registers.
2534 Each value is a 16-bit number corresponding to the concatenation of the high
2535 and low FTDI GPIO registers. The values should be selected based on the
2536 schematics of the adapter, such that all signals are set to safe levels with
2537 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2538 and initially asserted reset signals.
2541 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2542 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2543 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2544 register bitmasks to tell the driver the connection and type of the output
2545 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2546 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2547 used with inverting data inputs and @option{-data} with non-inverting inputs.
2548 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2549 not-output-enable) input to the output buffer is connected. The options
2550 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2551 with the method @command{ftdi_get_signal}.
2553 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2554 simple open-collector transistor driver would be specified with @option{-oe}
2555 only. In that case the signal can only be set to drive low or to Hi-Z and the
2556 driver will complain if the signal is set to drive high. Which means that if
2557 it's a reset signal, @command{reset_config} must be specified as
2558 @option{srst_open_drain}, not @option{srst_push_pull}.
2560 A special case is provided when @option{-data} and @option{-oe} is set to the
2561 same bitmask. Then the FTDI pin is considered being connected straight to the
2562 target without any buffer. The FTDI pin is then switched between output and
2563 input as necessary to provide the full set of low, high and Hi-Z
2564 characteristics. In all other cases, the pins specified in a signal definition
2565 are always driven by the FTDI.
2567 If @option{-alias} or @option{-nalias} is used, the signal is created
2568 identical (or with data inverted) to an already specified signal
2572 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2573 Set a previously defined signal to the specified level.
2575 @item @option{0}, drive low
2576 @item @option{1}, drive high
2577 @item @option{z}, set to high-impedance
2581 @deffn {Command} {ftdi_get_signal} name
2582 Get the value of a previously defined signal.
2585 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2586 Configure TCK edge at which the adapter samples the value of the TDO signal
2588 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2589 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2590 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2591 stability at higher JTAG clocks.
2593 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2594 @item @option{falling}, sample TDO on falling edge of TCK
2598 For example adapter definitions, see the configuration files shipped in the
2599 @file{interface/ftdi} directory.
2603 @deffn {Interface Driver} {ft232r}
2604 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2605 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2606 It currently doesn't support using CBUS pins as GPIO.
2608 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2615 @item DCD(10) - SRST
2618 User can change default pinout by supplying configuration
2619 commands with GPIO numbers or RS232 signal names.
2620 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2621 They differ from physical pin numbers.
2622 For details see actual FTDI chip datasheets.
2623 Every JTAG line must be configured to unique GPIO number
2624 different than any other JTAG line, even those lines
2625 that are sometimes not used like TRST or SRST.
2639 These interfaces have several commands, used to configure the driver
2640 before initializing the JTAG scan chain:
2642 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2643 The vendor ID and product ID of the adapter. If not specified, default
2644 0x0403:0x6001 is used.
2647 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2648 Specifies the @var{serial} of the adapter to use, in case the
2649 vendor provides unique IDs and more than one adapter is connected to
2650 the host. If not specified, serial numbers are not considered.
2653 @deffn {Config Command} {ft232r_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2654 Set four JTAG GPIO numbers at once.
2655 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2658 @deffn {Config Command} {ft232r_tck_num} @var{tck}
2659 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2662 @deffn {Config Command} {ft232r_tms_num} @var{tms}
2663 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2666 @deffn {Config Command} {ft232r_tdi_num} @var{tdi}
2667 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2670 @deffn {Config Command} {ft232r_tdo_num} @var{tdo}
2671 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2674 @deffn {Config Command} {ft232r_trst_num} @var{trst}
2675 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2678 @deffn {Config Command} {ft232r_srst_num} @var{srst}
2679 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2682 @deffn {Config Command} {ft232r_restore_serial} @var{word}
2683 Restore serial port after JTAG. This USB bitmode control word
2684 (16-bit) will be sent before quit. Lower byte should
2685 set GPIO direction register to a "sane" state:
2686 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2687 byte is usually 0 to disable bitbang mode.
2688 When kernel driver reattaches, serial port should continue to work.
2689 Value 0xFFFF disables sending control word and serial port,
2690 then kernel driver will not reattach.
2691 If not specified, default 0xFFFF is used.
2696 @deffn {Interface Driver} {remote_bitbang}
2697 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2698 with a remote process and sends ASCII encoded bitbang requests to that process
2699 instead of directly driving JTAG.
2701 The remote_bitbang driver is useful for debugging software running on
2702 processors which are being simulated.
2704 @deffn {Config Command} {remote_bitbang_port} number
2705 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2706 sockets instead of TCP.
2709 @deffn {Config Command} {remote_bitbang_host} hostname
2710 Specifies the hostname of the remote process to connect to using TCP, or the
2711 name of the UNIX socket to use if remote_bitbang_port is 0.
2714 For example, to connect remotely via TCP to the host foobar you might have
2718 interface remote_bitbang
2719 remote_bitbang_port 3335
2720 remote_bitbang_host foobar
2723 To connect to another process running locally via UNIX sockets with socket
2727 interface remote_bitbang
2728 remote_bitbang_port 0
2729 remote_bitbang_host mysocket
2733 @deffn {Interface Driver} {usb_blaster}
2734 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2735 for FTDI chips. These interfaces have several commands, used to
2736 configure the driver before initializing the JTAG scan chain:
2738 @deffn {Config Command} {usb_blaster_device_desc} description
2739 Provides the USB device description (the @emph{iProduct string})
2740 of the FTDI FT245 device. If not
2741 specified, the FTDI default value is used. This setting is only valid
2742 if compiled with FTD2XX support.
2745 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2746 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2747 default values are used.
2748 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2749 Altera USB-Blaster (default):
2751 usb_blaster_vid_pid 0x09FB 0x6001
2753 The following VID/PID is for Kolja Waschk's USB JTAG:
2755 usb_blaster_vid_pid 0x16C0 0x06AD
2759 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2760 Sets the state or function of the unused GPIO pins on USB-Blasters
2761 (pins 6 and 8 on the female JTAG header). These pins can be used as
2762 SRST and/or TRST provided the appropriate connections are made on the
2765 For example, to use pin 6 as SRST:
2767 usb_blaster_pin pin6 s
2768 reset_config srst_only
2772 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2773 Chooses the low level access method for the adapter. If not specified,
2774 @option{ftdi} is selected unless it wasn't enabled during the
2775 configure stage. USB-Blaster II needs @option{ublast2}.
2778 @deffn {Command} {usb_blaster_firmware} @var{path}
2779 This command specifies @var{path} to access USB-Blaster II firmware
2780 image. To be used with USB-Blaster II only.
2785 @deffn {Interface Driver} {gw16012}
2786 Gateworks GW16012 JTAG programmer.
2787 This has one driver-specific command:
2789 @deffn {Config Command} {parport_port} [port_number]
2790 Display either the address of the I/O port
2791 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2792 If a parameter is provided, first switch to use that port.
2793 This is a write-once setting.
2797 @deffn {Interface Driver} {jlink}
2798 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2801 @quotation Compatibility Note
2802 SEGGER released many firmware versions for the many hardware versions they
2803 produced. OpenOCD was extensively tested and intended to run on all of them,
2804 but some combinations were reported as incompatible. As a general
2805 recommendation, it is advisable to use the latest firmware version
2806 available for each hardware version. However the current V8 is a moving
2807 target, and SEGGER firmware versions released after the OpenOCD was
2808 released may not be compatible. In such cases it is recommended to
2809 revert to the last known functional version. For 0.5.0, this is from
2810 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2811 version is from "May 3 2012 18:36:22", packed with 4.46f.
2814 @deffn {Command} {jlink hwstatus}
2815 Display various hardware related information, for example target voltage and pin
2818 @deffn {Command} {jlink freemem}
2819 Display free device internal memory.
2821 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2822 Set the JTAG command version to be used. Without argument, show the actual JTAG
2825 @deffn {Command} {jlink config}
2826 Display the device configuration.
2828 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2829 Set the target power state on JTAG-pin 19. Without argument, show the target
2832 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2833 Set the MAC address of the device. Without argument, show the MAC address.
2835 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2836 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2837 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2840 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2841 Set the USB address of the device. This will also change the USB Product ID
2842 (PID) of the device. Without argument, show the USB address.
2844 @deffn {Command} {jlink config reset}
2845 Reset the current configuration.
2847 @deffn {Command} {jlink config write}
2848 Write the current configuration to the internal persistent storage.
2850 @deffn {Command} {jlink emucom write <channel> <data>}
2851 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2854 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2855 the EMUCOM channel 0x10:
2857 > jlink emucom write 0x10 aa0b23
2860 @deffn {Command} {jlink emucom read <channel> <length>}
2861 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2864 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2866 > jlink emucom read 0x0 4
2870 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2871 Set the USB address of the interface, in case more than one adapter is connected
2872 to the host. If not specified, USB addresses are not considered. Device
2873 selection via USB address is deprecated and the serial number should be used
2876 As a configuration command, it can be used only before 'init'.
2878 @deffn {Config} {jlink serial} <serial number>
2879 Set the serial number of the interface, in case more than one adapter is
2880 connected to the host. If not specified, serial numbers are not considered.
2882 As a configuration command, it can be used only before 'init'.
2886 @deffn {Interface Driver} {kitprog}
2887 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2888 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2889 families, but it is possible to use it with some other devices. If you are using
2890 this adapter with a PSoC or a PRoC, you may need to add
2891 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2892 configuration script.
2894 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2895 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2896 be used with this driver, and must either be used with the cmsis-dap driver or
2897 switched back to KitProg mode. See the Cypress KitProg User Guide for
2898 instructions on how to switch KitProg modes.
2902 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2904 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2905 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2906 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2907 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2908 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2909 SWD sequence must be sent after every target reset in order to re-establish
2910 communications with the target.
2911 @item Due in part to the limitation above, KitProg devices with firmware below
2912 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2913 communicate with PSoC 5LP devices. This is because, assuming debug is not
2914 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2915 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2916 could only be sent with an acquisition sequence.
2919 @deffn {Config Command} {kitprog_init_acquire_psoc}
2920 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2921 Please be aware that the acquisition sequence hard-resets the target.
2924 @deffn {Config Command} {kitprog_serial} serial
2925 Select a KitProg device by its @var{serial}. If left unspecified, the first
2926 device detected by OpenOCD will be used.
2929 @deffn {Command} {kitprog acquire_psoc}
2930 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2931 outside of the target-specific configuration scripts since it hard-resets the
2932 target as a side-effect.
2933 This is necessary for "reset halt" on some PSoC 4 series devices.
2936 @deffn {Command} {kitprog info}
2937 Display various adapter information, such as the hardware version, firmware
2938 version, and target voltage.
2942 @deffn {Interface Driver} {parport}
2943 Supports PC parallel port bit-banging cables:
2944 Wigglers, PLD download cable, and more.
2945 These interfaces have several commands, used to configure the driver
2946 before initializing the JTAG scan chain:
2948 @deffn {Config Command} {parport_cable} name
2949 Set the layout of the parallel port cable used to connect to the target.
2950 This is a write-once setting.
2951 Currently valid cable @var{name} values include:
2954 @item @b{altium} Altium Universal JTAG cable.
2955 @item @b{arm-jtag} Same as original wiggler except SRST and
2956 TRST connections reversed and TRST is also inverted.
2957 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2958 in configuration mode. This is only used to
2959 program the Chameleon itself, not a connected target.
2960 @item @b{dlc5} The Xilinx Parallel cable III.
2961 @item @b{flashlink} The ST Parallel cable.
2962 @item @b{lattice} Lattice ispDOWNLOAD Cable
2963 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2965 Amontec's Chameleon Programmer. The new version available from
2966 the website uses the original Wiggler layout ('@var{wiggler}')
2967 @item @b{triton} The parallel port adapter found on the
2968 ``Karo Triton 1 Development Board''.
2969 This is also the layout used by the HollyGates design
2970 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2971 @item @b{wiggler} The original Wiggler layout, also supported by
2972 several clones, such as the Olimex ARM-JTAG
2973 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2974 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2978 @deffn {Config Command} {parport_port} [port_number]
2979 Display either the address of the I/O port
2980 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2981 If a parameter is provided, first switch to use that port.
2982 This is a write-once setting.
2984 When using PPDEV to access the parallel port, use the number of the parallel port:
2985 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2986 you may encounter a problem.
2989 @deffn Command {parport_toggling_time} [nanoseconds]
2990 Displays how many nanoseconds the hardware needs to toggle TCK;
2991 the parport driver uses this value to obey the
2992 @command{adapter_khz} configuration.
2993 When the optional @var{nanoseconds} parameter is given,
2994 that setting is changed before displaying the current value.
2996 The default setting should work reasonably well on commodity PC hardware.
2997 However, you may want to calibrate for your specific hardware.
2999 To measure the toggling time with a logic analyzer or a digital storage
3000 oscilloscope, follow the procedure below:
3002 > parport_toggling_time 1000
3005 This sets the maximum JTAG clock speed of the hardware, but
3006 the actual speed probably deviates from the requested 500 kHz.
3007 Now, measure the time between the two closest spaced TCK transitions.
3008 You can use @command{runtest 1000} or something similar to generate a
3009 large set of samples.
3010 Update the setting to match your measurement:
3012 > parport_toggling_time <measured nanoseconds>
3014 Now the clock speed will be a better match for @command{adapter_khz rate}
3015 commands given in OpenOCD scripts and event handlers.
3017 You can do something similar with many digital multimeters, but note
3018 that you'll probably need to run the clock continuously for several
3019 seconds before it decides what clock rate to show. Adjust the
3020 toggling time up or down until the measured clock rate is a good
3021 match for the adapter_khz rate you specified; be conservative.
3025 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3026 This will configure the parallel driver to write a known
3027 cable-specific value to the parallel interface on exiting OpenOCD.
3030 For example, the interface configuration file for a
3031 classic ``Wiggler'' cable on LPT2 might look something like this:
3036 parport_cable wiggler
3040 @deffn {Interface Driver} {presto}
3041 ASIX PRESTO USB JTAG programmer.
3042 @deffn {Config Command} {presto_serial} serial_string
3043 Configures the USB serial number of the Presto device to use.
3047 @deffn {Interface Driver} {rlink}
3048 Raisonance RLink USB adapter
3051 @deffn {Interface Driver} {usbprog}
3052 usbprog is a freely programmable USB adapter.
3055 @deffn {Interface Driver} {vsllink}
3056 vsllink is part of Versaloon which is a versatile USB programmer.
3059 This defines quite a few driver-specific commands,
3060 which are not currently documented here.
3064 @anchor{hla_interface}
3065 @deffn {Interface Driver} {hla}
3066 This is a driver that supports multiple High Level Adapters.
3067 This type of adapter does not expose some of the lower level api's
3068 that OpenOCD would normally use to access the target.
3070 Currently supported adapters include the STMicroelectronics ST-LINK and TI ICDI.
3071 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3072 versions of firmware where serial number is reset after first use. Suggest
3073 using ST firmware update utility to upgrade ST-LINK firmware even if current
3074 version reported is V2.J21.S4.
3076 @deffn {Config Command} {hla_device_desc} description
3077 Currently Not Supported.
3080 @deffn {Config Command} {hla_serial} serial
3081 Specifies the serial number of the adapter.
3084 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3085 Specifies the adapter layout to use.
3088 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3089 Pairs of vendor IDs and product IDs of the device.
3092 @deffn {Command} {hla_command} command
3093 Execute a custom adapter-specific command. The @var{command} string is
3094 passed as is to the underlying adapter layout handler.
3098 @deffn {Interface Driver} {opendous}
3099 opendous-jtag is a freely programmable USB adapter.
3102 @deffn {Interface Driver} {ulink}
3103 This is the Keil ULINK v1 JTAG debugger.
3106 @deffn {Interface Driver} {ZY1000}
3107 This is the Zylin ZY1000 JTAG debugger.
3111 This defines some driver-specific commands,
3112 which are not currently documented here.
3115 @deffn Command power [@option{on}|@option{off}]
3116 Turn power switch to target on/off.
3117 No arguments: print status.
3120 @deffn {Interface Driver} {bcm2835gpio}
3121 This SoC is present in Raspberry Pi which is a cheap single-board computer
3122 exposing some GPIOs on its expansion header.
3124 The driver accesses memory-mapped GPIO peripheral registers directly
3125 for maximum performance, but the only possible race condition is for
3126 the pins' modes/muxing (which is highly unlikely), so it should be
3127 able to coexist nicely with both sysfs bitbanging and various
3128 peripherals' kernel drivers. The driver restores the previous
3129 configuration on exit.
3131 See @file{interface/raspberrypi-native.cfg} for a sample config and
3136 @deffn {Interface Driver} {imx_gpio}
3137 i.MX SoC is present in many community boards. Wandboard is an example
3138 of the one which is most popular.
3140 This driver is mostly the same as bcm2835gpio.
3142 See @file{interface/imx-native.cfg} for a sample config and
3148 @deffn {Interface Driver} {openjtag}
3149 OpenJTAG compatible USB adapter.
3150 This defines some driver-specific commands:
3152 @deffn {Config Command} {openjtag_variant} variant
3153 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3154 Currently valid @var{variant} values include:
3157 @item @b{standard} Standard variant (default).
3158 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3159 (see @uref{http://www.cypress.com/?rID=82870}).
3163 @deffn {Config Command} {openjtag_device_desc} string
3164 The USB device description string of the adapter.
3165 This value is only used with the standard variant.
3169 @section Transport Configuration
3171 As noted earlier, depending on the version of OpenOCD you use,
3172 and the debug adapter you are using,
3173 several transports may be available to
3174 communicate with debug targets (or perhaps to program flash memory).
3175 @deffn Command {transport list}
3176 displays the names of the transports supported by this
3180 @deffn Command {transport select} @option{transport_name}
3181 Select which of the supported transports to use in this OpenOCD session.
3183 When invoked with @option{transport_name}, attempts to select the named
3184 transport. The transport must be supported by the debug adapter
3185 hardware and by the version of OpenOCD you are using (including the
3188 If no transport has been selected and no @option{transport_name} is
3189 provided, @command{transport select} auto-selects the first transport
3190 supported by the debug adapter.
3192 @command{transport select} always returns the name of the session's selected
3196 @subsection JTAG Transport
3198 JTAG is the original transport supported by OpenOCD, and most
3199 of the OpenOCD commands support it.
3200 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3201 each of which must be explicitly declared.
3202 JTAG supports both debugging and boundary scan testing.
3203 Flash programming support is built on top of debug support.
3205 JTAG transport is selected with the command @command{transport select
3206 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3207 driver}, in which case the command is @command{transport select
3210 @subsection SWD Transport
3212 @cindex Serial Wire Debug
3213 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3214 Debug Access Point (DAP, which must be explicitly declared.
3215 (SWD uses fewer signal wires than JTAG.)
3216 SWD is debug-oriented, and does not support boundary scan testing.
3217 Flash programming support is built on top of debug support.
3218 (Some processors support both JTAG and SWD.)
3220 SWD transport is selected with the command @command{transport select
3221 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3222 driver}, in which case the command is @command{transport select
3225 @deffn Command {swd newdap} ...
3226 Declares a single DAP which uses SWD transport.
3227 Parameters are currently the same as "jtag newtap" but this is
3230 @deffn Command {swd wcr trn prescale}
3231 Updates TRN (turnaround delay) and prescaling.fields of the
3232 Wire Control Register (WCR).
3233 No parameters: displays current settings.
3236 @subsection SPI Transport
3238 @cindex Serial Peripheral Interface
3239 The Serial Peripheral Interface (SPI) is a general purpose transport
3240 which uses four wire signaling. Some processors use it as part of a
3241 solution for flash programming.
3245 JTAG clock setup is part of system setup.
3246 It @emph{does not belong with interface setup} since any interface
3247 only knows a few of the constraints for the JTAG clock speed.
3248 Sometimes the JTAG speed is
3249 changed during the target initialization process: (1) slow at
3250 reset, (2) program the CPU clocks, (3) run fast.
3251 Both the "slow" and "fast" clock rates are functions of the
3252 oscillators used, the chip, the board design, and sometimes
3253 power management software that may be active.
3255 The speed used during reset, and the scan chain verification which
3256 follows reset, can be adjusted using a @code{reset-start}
3257 target event handler.
3258 It can then be reconfigured to a faster speed by a
3259 @code{reset-init} target event handler after it reprograms those
3260 CPU clocks, or manually (if something else, such as a boot loader,
3261 sets up those clocks).
3262 @xref{targetevents,,Target Events}.
3263 When the initial low JTAG speed is a chip characteristic, perhaps
3264 because of a required oscillator speed, provide such a handler
3265 in the target config file.
3266 When that speed is a function of a board-specific characteristic
3267 such as which speed oscillator is used, it belongs in the board
3268 config file instead.
3269 In both cases it's safest to also set the initial JTAG clock rate
3270 to that same slow speed, so that OpenOCD never starts up using a
3271 clock speed that's faster than the scan chain can support.
3275 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3278 If your system supports adaptive clocking (RTCK), configuring
3279 JTAG to use that is probably the most robust approach.
3280 However, it introduces delays to synchronize clocks; so it
3281 may not be the fastest solution.
3283 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3284 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3285 which support adaptive clocking.
3287 @deffn {Command} adapter_khz max_speed_kHz
3288 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3289 JTAG interfaces usually support a limited number of
3290 speeds. The speed actually used won't be faster
3291 than the speed specified.
3293 Chip data sheets generally include a top JTAG clock rate.
3294 The actual rate is often a function of a CPU core clock,
3295 and is normally less than that peak rate.
3296 For example, most ARM cores accept at most one sixth of the CPU clock.
3298 Speed 0 (khz) selects RTCK method.
3299 @xref{faqrtck,,FAQ RTCK}.
3300 If your system uses RTCK, you won't need to change the
3301 JTAG clocking after setup.
3302 Not all interfaces, boards, or targets support ``rtck''.
3303 If the interface device can not
3304 support it, an error is returned when you try to use RTCK.
3307 @defun jtag_rclk fallback_speed_kHz
3308 @cindex adaptive clocking
3310 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3311 If that fails (maybe the interface, board, or target doesn't
3312 support it), falls back to the specified frequency.
3314 # Fall back to 3mhz if RTCK is not supported
3319 @node Reset Configuration
3320 @chapter Reset Configuration
3321 @cindex Reset Configuration
3323 Every system configuration may require a different reset
3324 configuration. This can also be quite confusing.
3325 Resets also interact with @var{reset-init} event handlers,
3326 which do things like setting up clocks and DRAM, and
3327 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3328 They can also interact with JTAG routers.
3329 Please see the various board files for examples.
3332 To maintainers and integrators:
3333 Reset configuration touches several things at once.
3334 Normally the board configuration file
3335 should define it and assume that the JTAG adapter supports
3336 everything that's wired up to the board's JTAG connector.
3338 However, the target configuration file could also make note
3339 of something the silicon vendor has done inside the chip,
3340 which will be true for most (or all) boards using that chip.
3341 And when the JTAG adapter doesn't support everything, the
3342 user configuration file will need to override parts of
3343 the reset configuration provided by other files.
3346 @section Types of Reset
3348 There are many kinds of reset possible through JTAG, but
3349 they may not all work with a given board and adapter.
3350 That's part of why reset configuration can be error prone.
3354 @emph{System Reset} ... the @emph{SRST} hardware signal
3355 resets all chips connected to the JTAG adapter, such as processors,
3356 power management chips, and I/O controllers. Normally resets triggered
3357 with this signal behave exactly like pressing a RESET button.
3359 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3360 just the TAP controllers connected to the JTAG adapter.
3361 Such resets should not be visible to the rest of the system; resetting a
3362 device's TAP controller just puts that controller into a known state.
3364 @emph{Emulation Reset} ... many devices can be reset through JTAG
3365 commands. These resets are often distinguishable from system
3366 resets, either explicitly (a "reset reason" register says so)
3367 or implicitly (not all parts of the chip get reset).
3369 @emph{Other Resets} ... system-on-chip devices often support
3370 several other types of reset.
3371 You may need to arrange that a watchdog timer stops
3372 while debugging, preventing a watchdog reset.
3373 There may be individual module resets.
3376 In the best case, OpenOCD can hold SRST, then reset
3377 the TAPs via TRST and send commands through JTAG to halt the
3378 CPU at the reset vector before the 1st instruction is executed.
3379 Then when it finally releases the SRST signal, the system is
3380 halted under debugger control before any code has executed.
3381 This is the behavior required to support the @command{reset halt}
3382 and @command{reset init} commands; after @command{reset init} a
3383 board-specific script might do things like setting up DRAM.
3384 (@xref{resetcommand,,Reset Command}.)
3386 @anchor{srstandtrstissues}
3387 @section SRST and TRST Issues
3389 Because SRST and TRST are hardware signals, they can have a
3390 variety of system-specific constraints. Some of the most
3395 @item @emph{Signal not available} ... Some boards don't wire
3396 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3397 support such signals even if they are wired up.
3398 Use the @command{reset_config} @var{signals} options to say
3399 when either of those signals is not connected.
3400 When SRST is not available, your code might not be able to rely
3401 on controllers having been fully reset during code startup.
3402 Missing TRST is not a problem, since JTAG-level resets can
3403 be triggered using with TMS signaling.
3405 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3406 adapter will connect SRST to TRST, instead of keeping them separate.
3407 Use the @command{reset_config} @var{combination} options to say
3408 when those signals aren't properly independent.
3410 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3411 delay circuit, reset supervisor, or on-chip features can extend
3412 the effect of a JTAG adapter's reset for some time after the adapter
3413 stops issuing the reset. For example, there may be chip or board
3414 requirements that all reset pulses last for at least a
3415 certain amount of time; and reset buttons commonly have
3416 hardware debouncing.
3417 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3418 commands to say when extra delays are needed.
3420 @item @emph{Drive type} ... Reset lines often have a pullup
3421 resistor, letting the JTAG interface treat them as open-drain
3422 signals. But that's not a requirement, so the adapter may need
3423 to use push/pull output drivers.
3424 Also, with weak pullups it may be advisable to drive
3425 signals to both levels (push/pull) to minimize rise times.
3426 Use the @command{reset_config} @var{trst_type} and
3427 @var{srst_type} parameters to say how to drive reset signals.
3429 @item @emph{Special initialization} ... Targets sometimes need
3430 special JTAG initialization sequences to handle chip-specific
3431 issues (not limited to errata).
3432 For example, certain JTAG commands might need to be issued while
3433 the system as a whole is in a reset state (SRST active)
3434 but the JTAG scan chain is usable (TRST inactive).
3435 Many systems treat combined assertion of SRST and TRST as a
3436 trigger for a harder reset than SRST alone.
3437 Such custom reset handling is discussed later in this chapter.
3440 There can also be other issues.
3441 Some devices don't fully conform to the JTAG specifications.
3442 Trivial system-specific differences are common, such as
3443 SRST and TRST using slightly different names.
3444 There are also vendors who distribute key JTAG documentation for
3445 their chips only to developers who have signed a Non-Disclosure
3448 Sometimes there are chip-specific extensions like a requirement to use
3449 the normally-optional TRST signal (precluding use of JTAG adapters which
3450 don't pass TRST through), or needing extra steps to complete a TAP reset.
3452 In short, SRST and especially TRST handling may be very finicky,
3453 needing to cope with both architecture and board specific constraints.
3455 @section Commands for Handling Resets
3457 @deffn {Command} adapter_nsrst_assert_width milliseconds
3458 Minimum amount of time (in milliseconds) OpenOCD should wait
3459 after asserting nSRST (active-low system reset) before
3460 allowing it to be deasserted.
3463 @deffn {Command} adapter_nsrst_delay milliseconds
3464 How long (in milliseconds) OpenOCD should wait after deasserting
3465 nSRST (active-low system reset) before starting new JTAG operations.
3466 When a board has a reset button connected to SRST line it will
3467 probably have hardware debouncing, implying you should use this.
3470 @deffn {Command} jtag_ntrst_assert_width milliseconds
3471 Minimum amount of time (in milliseconds) OpenOCD should wait
3472 after asserting nTRST (active-low JTAG TAP reset) before
3473 allowing it to be deasserted.
3476 @deffn {Command} jtag_ntrst_delay milliseconds
3477 How long (in milliseconds) OpenOCD should wait after deasserting
3478 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3481 @anchor {reset_config}
3482 @deffn {Command} reset_config mode_flag ...
3483 This command displays or modifies the reset configuration
3484 of your combination of JTAG board and target in target
3485 configuration scripts.
3487 Information earlier in this section describes the kind of problems
3488 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3489 As a rule this command belongs only in board config files,
3490 describing issues like @emph{board doesn't connect TRST};
3491 or in user config files, addressing limitations derived
3492 from a particular combination of interface and board.
3493 (An unlikely example would be using a TRST-only adapter
3494 with a board that only wires up SRST.)
3496 The @var{mode_flag} options can be specified in any order, but only one
3497 of each type -- @var{signals}, @var{combination}, @var{gates},
3498 @var{trst_type}, @var{srst_type} and @var{connect_type}
3499 -- may be specified at a time.
3500 If you don't provide a new value for a given type, its previous
3501 value (perhaps the default) is unchanged.
3502 For example, this means that you don't need to say anything at all about
3503 TRST just to declare that if the JTAG adapter should want to drive SRST,
3504 it must explicitly be driven high (@option{srst_push_pull}).
3508 @var{signals} can specify which of the reset signals are connected.
3509 For example, If the JTAG interface provides SRST, but the board doesn't
3510 connect that signal properly, then OpenOCD can't use it.
3511 Possible values are @option{none} (the default), @option{trst_only},
3512 @option{srst_only} and @option{trst_and_srst}.
3515 If your board provides SRST and/or TRST through the JTAG connector,
3516 you must declare that so those signals can be used.
3520 The @var{combination} is an optional value specifying broken reset
3521 signal implementations.
3522 The default behaviour if no option given is @option{separate},
3523 indicating everything behaves normally.
3524 @option{srst_pulls_trst} states that the
3525 test logic is reset together with the reset of the system (e.g. NXP
3526 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3527 the system is reset together with the test logic (only hypothetical, I
3528 haven't seen hardware with such a bug, and can be worked around).
3529 @option{combined} implies both @option{srst_pulls_trst} and
3530 @option{trst_pulls_srst}.
3533 The @var{gates} tokens control flags that describe some cases where
3534 JTAG may be unavailable during reset.
3535 @option{srst_gates_jtag} (default)
3536 indicates that asserting SRST gates the
3537 JTAG clock. This means that no communication can happen on JTAG
3538 while SRST is asserted.
3539 Its converse is @option{srst_nogate}, indicating that JTAG commands
3540 can safely be issued while SRST is active.
3543 The @var{connect_type} tokens control flags that describe some cases where
3544 SRST is asserted while connecting to the target. @option{srst_nogate}
3545 is required to use this option.
3546 @option{connect_deassert_srst} (default)
3547 indicates that SRST will not be asserted while connecting to the target.
3548 Its converse is @option{connect_assert_srst}, indicating that SRST will
3549 be asserted before any target connection.
3550 Only some targets support this feature, STM32 and STR9 are examples.
3551 This feature is useful if you are unable to connect to your target due
3552 to incorrect options byte config or illegal program execution.
3555 The optional @var{trst_type} and @var{srst_type} parameters allow the
3556 driver mode of each reset line to be specified. These values only affect
3557 JTAG interfaces with support for different driver modes, like the Amontec
3558 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3559 relevant signal (TRST or SRST) is not connected.
3563 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3564 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3565 Most boards connect this signal to a pulldown, so the JTAG TAPs
3566 never leave reset unless they are hooked up to a JTAG adapter.
3569 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3570 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3571 Most boards connect this signal to a pullup, and allow the
3572 signal to be pulled low by various events including system
3573 power-up and pressing a reset button.
3577 @section Custom Reset Handling
3580 OpenOCD has several ways to help support the various reset
3581 mechanisms provided by chip and board vendors.
3582 The commands shown in the previous section give standard parameters.
3583 There are also @emph{event handlers} associated with TAPs or Targets.
3584 Those handlers are Tcl procedures you can provide, which are invoked
3585 at particular points in the reset sequence.
3587 @emph{When SRST is not an option} you must set
3588 up a @code{reset-assert} event handler for your target.
3589 For example, some JTAG adapters don't include the SRST signal;
3590 and some boards have multiple targets, and you won't always
3591 want to reset everything at once.
3593 After configuring those mechanisms, you might still
3594 find your board doesn't start up or reset correctly.
3595 For example, maybe it needs a slightly different sequence
3596 of SRST and/or TRST manipulations, because of quirks that
3597 the @command{reset_config} mechanism doesn't address;
3598 or asserting both might trigger a stronger reset, which
3599 needs special attention.
3601 Experiment with lower level operations, such as @command{jtag_reset}
3602 and the @command{jtag arp_*} operations shown here,
3603 to find a sequence of operations that works.
3604 @xref{JTAG Commands}.
3605 When you find a working sequence, it can be used to override
3606 @command{jtag_init}, which fires during OpenOCD startup
3607 (@pxref{configurationstage,,Configuration Stage});
3608 or @command{init_reset}, which fires during reset processing.
3610 You might also want to provide some project-specific reset
3611 schemes. For example, on a multi-target board the standard
3612 @command{reset} command would reset all targets, but you
3613 may need the ability to reset only one target at time and
3614 thus want to avoid using the board-wide SRST signal.
3616 @deffn {Overridable Procedure} init_reset mode
3617 This is invoked near the beginning of the @command{reset} command,
3618 usually to provide as much of a cold (power-up) reset as practical.
3619 By default it is also invoked from @command{jtag_init} if
3620 the scan chain does not respond to pure JTAG operations.
3621 The @var{mode} parameter is the parameter given to the
3622 low level reset command (@option{halt},
3623 @option{init}, or @option{run}), @option{setup},
3624 or potentially some other value.
3626 The default implementation just invokes @command{jtag arp_init-reset}.
3627 Replacements will normally build on low level JTAG
3628 operations such as @command{jtag_reset}.
3629 Operations here must not address individual TAPs
3630 (or their associated targets)
3631 until the JTAG scan chain has first been verified to work.
3633 Implementations must have verified the JTAG scan chain before
3635 This is done by calling @command{jtag arp_init}
3636 (or @command{jtag arp_init-reset}).
3639 @deffn Command {jtag arp_init}
3640 This validates the scan chain using just the four
3641 standard JTAG signals (TMS, TCK, TDI, TDO).
3642 It starts by issuing a JTAG-only reset.
3643 Then it performs checks to verify that the scan chain configuration
3644 matches the TAPs it can observe.
3645 Those checks include checking IDCODE values for each active TAP,
3646 and verifying the length of their instruction registers using
3647 TAP @code{-ircapture} and @code{-irmask} values.
3648 If these tests all pass, TAP @code{setup} events are
3649 issued to all TAPs with handlers for that event.
3652 @deffn Command {jtag arp_init-reset}
3653 This uses TRST and SRST to try resetting
3654 everything on the JTAG scan chain
3655 (and anything else connected to SRST).
3656 It then invokes the logic of @command{jtag arp_init}.
3660 @node TAP Declaration
3661 @chapter TAP Declaration
3662 @cindex TAP declaration
3663 @cindex TAP configuration
3665 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3666 TAPs serve many roles, including:
3669 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3670 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3671 Others do it indirectly, making a CPU do it.
3672 @item @b{Program Download} Using the same CPU support GDB uses,
3673 you can initialize a DRAM controller, download code to DRAM, and then
3674 start running that code.
3675 @item @b{Boundary Scan} Most chips support boundary scan, which
3676 helps test for board assembly problems like solder bridges
3677 and missing connections.
3680 OpenOCD must know about the active TAPs on your board(s).
3681 Setting up the TAPs is the core task of your configuration files.
3682 Once those TAPs are set up, you can pass their names to code
3683 which sets up CPUs and exports them as GDB targets,
3684 probes flash memory, performs low-level JTAG operations, and more.
3686 @section Scan Chains
3689 TAPs are part of a hardware @dfn{scan chain},
3690 which is a daisy chain of TAPs.
3691 They also need to be added to
3692 OpenOCD's software mirror of that hardware list,
3693 giving each member a name and associating other data with it.
3694 Simple scan chains, with a single TAP, are common in
3695 systems with a single microcontroller or microprocessor.
3696 More complex chips may have several TAPs internally.
3697 Very complex scan chains might have a dozen or more TAPs:
3698 several in one chip, more in the next, and connecting
3699 to other boards with their own chips and TAPs.
3701 You can display the list with the @command{scan_chain} command.
3702 (Don't confuse this with the list displayed by the @command{targets}
3703 command, presented in the next chapter.
3704 That only displays TAPs for CPUs which are configured as
3706 Here's what the scan chain might look like for a chip more than one TAP:
3709 TapName Enabled IdCode Expected IrLen IrCap IrMask
3710 -- ------------------ ------- ---------- ---------- ----- ----- ------
3711 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3712 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3713 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3716 OpenOCD can detect some of that information, but not all
3717 of it. @xref{autoprobing,,Autoprobing}.
3718 Unfortunately, those TAPs can't always be autoconfigured,
3719 because not all devices provide good support for that.
3720 JTAG doesn't require supporting IDCODE instructions, and
3721 chips with JTAG routers may not link TAPs into the chain
3722 until they are told to do so.
3724 The configuration mechanism currently supported by OpenOCD
3725 requires explicit configuration of all TAP devices using
3726 @command{jtag newtap} commands, as detailed later in this chapter.
3727 A command like this would declare one tap and name it @code{chip1.cpu}:
3730 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3733 Each target configuration file lists the TAPs provided
3735 Board configuration files combine all the targets on a board,
3737 Note that @emph{the order in which TAPs are declared is very important.}
3738 That declaration order must match the order in the JTAG scan chain,
3739 both inside a single chip and between them.
3740 @xref{faqtaporder,,FAQ TAP Order}.
3742 For example, the STMicroelectronics STR912 chip has
3743 three separate TAPs@footnote{See the ST
3744 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3745 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3746 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3747 To configure those taps, @file{target/str912.cfg}
3748 includes commands something like this:
3751 jtag newtap str912 flash ... params ...
3752 jtag newtap str912 cpu ... params ...
3753 jtag newtap str912 bs ... params ...
3756 Actual config files typically use a variable such as @code{$_CHIPNAME}
3757 instead of literals like @option{str912}, to support more than one chip
3758 of each type. @xref{Config File Guidelines}.
3760 @deffn Command {jtag names}
3761 Returns the names of all current TAPs in the scan chain.
3762 Use @command{jtag cget} or @command{jtag tapisenabled}
3763 to examine attributes and state of each TAP.
3765 foreach t [jtag names] @{
3766 puts [format "TAP: %s\n" $t]
3771 @deffn Command {scan_chain}
3772 Displays the TAPs in the scan chain configuration,
3774 The set of TAPs listed by this command is fixed by
3775 exiting the OpenOCD configuration stage,
3776 but systems with a JTAG router can
3777 enable or disable TAPs dynamically.
3780 @c FIXME! "jtag cget" should be able to return all TAP
3781 @c attributes, like "$target_name cget" does for targets.
3783 @c Probably want "jtag eventlist", and a "tap-reset" event
3784 @c (on entry to RESET state).
3789 When TAP objects are declared with @command{jtag newtap},
3790 a @dfn{dotted.name} is created for the TAP, combining the
3791 name of a module (usually a chip) and a label for the TAP.
3792 For example: @code{xilinx.tap}, @code{str912.flash},
3793 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3794 Many other commands use that dotted.name to manipulate or
3795 refer to the TAP. For example, CPU configuration uses the
3796 name, as does declaration of NAND or NOR flash banks.
3798 The components of a dotted name should follow ``C'' symbol
3799 name rules: start with an alphabetic character, then numbers
3800 and underscores are OK; while others (including dots!) are not.
3802 @section TAP Declaration Commands
3804 @c shouldn't this be(come) a {Config Command}?
3805 @deffn Command {jtag newtap} chipname tapname configparams...
3806 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3807 and configured according to the various @var{configparams}.
3809 The @var{chipname} is a symbolic name for the chip.
3810 Conventionally target config files use @code{$_CHIPNAME},
3811 defaulting to the model name given by the chip vendor but
3814 @cindex TAP naming convention
3815 The @var{tapname} reflects the role of that TAP,
3816 and should follow this convention:
3819 @item @code{bs} -- For boundary scan if this is a separate TAP;
3820 @item @code{cpu} -- The main CPU of the chip, alternatively
3821 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3822 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3823 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3824 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3825 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3826 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3827 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3829 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3830 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3831 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3832 a JTAG TAP; that TAP should be named @code{sdma}.
3835 Every TAP requires at least the following @var{configparams}:
3838 @item @code{-irlen} @var{NUMBER}
3839 @*The length in bits of the
3840 instruction register, such as 4 or 5 bits.
3843 A TAP may also provide optional @var{configparams}:
3846 @item @code{-disable} (or @code{-enable})
3847 @*Use the @code{-disable} parameter to flag a TAP which is not
3848 linked into the scan chain after a reset using either TRST
3849 or the JTAG state machine's @sc{reset} state.
3850 You may use @code{-enable} to highlight the default state
3851 (the TAP is linked in).
3852 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3853 @item @code{-expected-id} @var{NUMBER}
3854 @*A non-zero @var{number} represents a 32-bit IDCODE
3855 which you expect to find when the scan chain is examined.
3856 These codes are not required by all JTAG devices.
3857 @emph{Repeat the option} as many times as required if more than one
3858 ID code could appear (for example, multiple versions).
3859 Specify @var{number} as zero to suppress warnings about IDCODE
3860 values that were found but not included in the list.
3862 Provide this value if at all possible, since it lets OpenOCD
3863 tell when the scan chain it sees isn't right. These values
3864 are provided in vendors' chip documentation, usually a technical
3865 reference manual. Sometimes you may need to probe the JTAG
3866 hardware to find these values.
3867 @xref{autoprobing,,Autoprobing}.
3868 @item @code{-ignore-version}
3869 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3870 option. When vendors put out multiple versions of a chip, or use the same
3871 JTAG-level ID for several largely-compatible chips, it may be more practical
3872 to ignore the version field than to update config files to handle all of
3873 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3874 @item @code{-ircapture} @var{NUMBER}
3875 @*The bit pattern loaded by the TAP into the JTAG shift register
3876 on entry to the @sc{ircapture} state, such as 0x01.
3877 JTAG requires the two LSBs of this value to be 01.
3878 By default, @code{-ircapture} and @code{-irmask} are set
3879 up to verify that two-bit value. You may provide
3880 additional bits if you know them, or indicate that
3881 a TAP doesn't conform to the JTAG specification.
3882 @item @code{-irmask} @var{NUMBER}
3883 @*A mask used with @code{-ircapture}
3884 to verify that instruction scans work correctly.
3885 Such scans are not used by OpenOCD except to verify that
3886 there seems to be no problems with JTAG scan chain operations.
3887 @item @code{-ignore-syspwrupack}
3888 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
3889 register during initial examination and when checking the sticky error bit.
3890 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
3891 devices do not set the ack bit until sometime later.
3895 @section Other TAP commands
3897 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3898 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3899 At this writing this TAP attribute
3900 mechanism is used only for event handling.
3901 (It is not a direct analogue of the @code{cget}/@code{configure}
3902 mechanism for debugger targets.)
3903 See the next section for information about the available events.
3905 The @code{configure} subcommand assigns an event handler,
3906 a TCL string which is evaluated when the event is triggered.
3907 The @code{cget} subcommand returns that handler.
3914 OpenOCD includes two event mechanisms.
3915 The one presented here applies to all JTAG TAPs.
3916 The other applies to debugger targets,
3917 which are associated with certain TAPs.
3919 The TAP events currently defined are:
3922 @item @b{post-reset}
3923 @* The TAP has just completed a JTAG reset.
3924 The tap may still be in the JTAG @sc{reset} state.
3925 Handlers for these events might perform initialization sequences
3926 such as issuing TCK cycles, TMS sequences to ensure
3927 exit from the ARM SWD mode, and more.
3929 Because the scan chain has not yet been verified, handlers for these events
3930 @emph{should not issue commands which scan the JTAG IR or DR registers}
3931 of any particular target.
3932 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3934 @* The scan chain has been reset and verified.
3935 This handler may enable TAPs as needed.
3936 @item @b{tap-disable}
3937 @* The TAP needs to be disabled. This handler should
3938 implement @command{jtag tapdisable}
3939 by issuing the relevant JTAG commands.
3940 @item @b{tap-enable}
3941 @* The TAP needs to be enabled. This handler should
3942 implement @command{jtag tapenable}
3943 by issuing the relevant JTAG commands.
3946 If you need some action after each JTAG reset which isn't actually
3947 specific to any TAP (since you can't yet trust the scan chain's
3948 contents to be accurate), you might:
3951 jtag configure CHIP.jrc -event post-reset @{
3952 echo "JTAG Reset done"
3953 ... non-scan jtag operations to be done after reset
3958 @anchor{enablinganddisablingtaps}
3959 @section Enabling and Disabling TAPs
3960 @cindex JTAG Route Controller
3963 In some systems, a @dfn{JTAG Route Controller} (JRC)
3964 is used to enable and/or disable specific JTAG TAPs.
3965 Many ARM-based chips from Texas Instruments include
3966 an ``ICEPick'' module, which is a JRC.
3967 Such chips include DaVinci and OMAP3 processors.
3969 A given TAP may not be visible until the JRC has been
3970 told to link it into the scan chain; and if the JRC
3971 has been told to unlink that TAP, it will no longer
3973 Such routers address problems that JTAG ``bypass mode''
3977 @item The scan chain can only go as fast as its slowest TAP.
3978 @item Having many TAPs slows instruction scans, since all
3979 TAPs receive new instructions.
3980 @item TAPs in the scan chain must be powered up, which wastes
3981 power and prevents debugging some power management mechanisms.
3984 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3985 as implied by the existence of JTAG routers.
3986 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3987 does include a kind of JTAG router functionality.
3989 @c (a) currently the event handlers don't seem to be able to
3990 @c fail in a way that could lead to no-change-of-state.
3992 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3993 shown below, and is implemented using TAP event handlers.
3994 So for example, when defining a TAP for a CPU connected to
3995 a JTAG router, your @file{target.cfg} file
3996 should define TAP event handlers using
3997 code that looks something like this:
4000 jtag configure CHIP.cpu -event tap-enable @{
4001 ... jtag operations using CHIP.jrc
4003 jtag configure CHIP.cpu -event tap-disable @{
4004 ... jtag operations using CHIP.jrc
4008 Then you might want that CPU's TAP enabled almost all the time:
4011 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4014 Note how that particular setup event handler declaration
4015 uses quotes to evaluate @code{$CHIP} when the event is configured.
4016 Using brackets @{ @} would cause it to be evaluated later,
4017 at runtime, when it might have a different value.
4019 @deffn Command {jtag tapdisable} dotted.name
4020 If necessary, disables the tap
4021 by sending it a @option{tap-disable} event.
4022 Returns the string "1" if the tap
4023 specified by @var{dotted.name} is enabled,
4024 and "0" if it is disabled.
4027 @deffn Command {jtag tapenable} dotted.name
4028 If necessary, enables the tap
4029 by sending it a @option{tap-enable} event.
4030 Returns the string "1" if the tap
4031 specified by @var{dotted.name} is enabled,
4032 and "0" if it is disabled.
4035 @deffn Command {jtag tapisenabled} dotted.name
4036 Returns the string "1" if the tap
4037 specified by @var{dotted.name} is enabled,
4038 and "0" if it is disabled.
4041 Humans will find the @command{scan_chain} command more helpful
4042 for querying the state of the JTAG taps.
4046 @anchor{autoprobing}
4047 @section Autoprobing
4049 @cindex JTAG autoprobe
4051 TAP configuration is the first thing that needs to be done
4052 after interface and reset configuration. Sometimes it's
4053 hard finding out what TAPs exist, or how they are identified.
4054 Vendor documentation is not always easy to find and use.
4056 To help you get past such problems, OpenOCD has a limited
4057 @emph{autoprobing} ability to look at the scan chain, doing
4058 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4059 To use this mechanism, start the OpenOCD server with only data
4060 that configures your JTAG interface, and arranges to come up
4061 with a slow clock (many devices don't support fast JTAG clocks
4062 right when they come out of reset).
4064 For example, your @file{openocd.cfg} file might have:
4067 source [find interface/olimex-arm-usb-tiny-h.cfg]
4068 reset_config trst_and_srst
4072 When you start the server without any TAPs configured, it will
4073 attempt to autoconfigure the TAPs. There are two parts to this:
4076 @item @emph{TAP discovery} ...
4077 After a JTAG reset (sometimes a system reset may be needed too),
4078 each TAP's data registers will hold the contents of either the
4079 IDCODE or BYPASS register.
4080 If JTAG communication is working, OpenOCD will see each TAP,
4081 and report what @option{-expected-id} to use with it.
4082 @item @emph{IR Length discovery} ...
4083 Unfortunately JTAG does not provide a reliable way to find out
4084 the value of the @option{-irlen} parameter to use with a TAP
4086 If OpenOCD can discover the length of a TAP's instruction
4087 register, it will report it.
4088 Otherwise you may need to consult vendor documentation, such
4089 as chip data sheets or BSDL files.
4092 In many cases your board will have a simple scan chain with just
4093 a single device. Here's what OpenOCD reported with one board
4094 that's a bit more complex:
4098 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4099 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4100 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4101 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4102 AUTO auto0.tap - use "... -irlen 4"
4103 AUTO auto1.tap - use "... -irlen 4"
4104 AUTO auto2.tap - use "... -irlen 6"
4105 no gdb ports allocated as no target has been specified
4108 Given that information, you should be able to either find some existing
4109 config files to use, or create your own. If you create your own, you
4110 would configure from the bottom up: first a @file{target.cfg} file
4111 with these TAPs, any targets associated with them, and any on-chip
4112 resources; then a @file{board.cfg} with off-chip resources, clocking,
4115 @anchor{dapdeclaration}
4116 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4117 @cindex DAP declaration
4119 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4120 no longer implicitly created together with the target. It must be
4121 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4122 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4123 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4125 The @command{dap} command group supports the following sub-commands:
4127 @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
4128 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4129 @var{dotted.name}. This also creates a new command (@command{dap_name})
4130 which is used for various purposes including additional configuration.
4131 There can only be one DAP for each JTAG tap in the system.
4133 A DAP may also provide optional @var{configparams}:
4136 @item @code{-ignore-syspwrupack}
4137 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4138 register during initial examination and when checking the sticky error bit.
4139 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4140 devices do not set the ack bit until sometime later.
4144 @deffn Command {dap names}
4145 This command returns a list of all registered DAP objects. It it useful mainly
4149 @deffn Command {dap info} [num]
4150 Displays the ROM table for MEM-AP @var{num},
4151 defaulting to the currently selected AP of the currently selected target.
4154 @deffn Command {dap init}
4155 Initialize all registered DAPs. This command is used internally
4156 during initialization. It can be issued at any time after the
4157 initialization, too.
4160 The following commands exist as subcommands of DAP instances:
4162 @deffn Command {$dap_name info} [num]
4163 Displays the ROM table for MEM-AP @var{num},
4164 defaulting to the currently selected AP.
4167 @deffn Command {$dap_name apid} [num]
4168 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4171 @anchor{DAP subcommand apreg}
4172 @deffn Command {$dap_name apreg} ap_num reg [value]
4173 Displays content of a register @var{reg} from AP @var{ap_num}
4174 or set a new value @var{value}.
4175 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4178 @deffn Command {$dap_name apsel} [num]
4179 Select AP @var{num}, defaulting to 0.
4182 @deffn Command {$dap_name dpreg} reg [value]
4183 Displays the content of DP register at address @var{reg}, or set it to a new
4186 In case of SWD, @var{reg} is a value in packed format
4187 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4188 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4190 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4191 background activity by OpenOCD while you are operating at such low-level.
4194 @deffn Command {$dap_name baseaddr} [num]
4195 Displays debug base address from MEM-AP @var{num},
4196 defaulting to the currently selected AP.
4199 @deffn Command {$dap_name memaccess} [value]
4200 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4201 memory bus access [0-255], giving additional time to respond to reads.
4202 If @var{value} is defined, first assigns that.
4205 @deffn Command {$dap_name apcsw} [value [mask]]
4206 Displays or changes CSW bit pattern for MEM-AP transfers.
4208 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4209 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4210 and the result is written to the real CSW register. All bits except dynamically
4211 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4212 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4215 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4216 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4219 kx.dap apcsw 0x2000000
4222 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4223 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4224 and leaves the rest of the pattern intact. It configures memory access through
4225 DCache on Cortex-M7.
4227 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4228 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4231 Another example clears SPROT bit and leaves the rest of pattern intact:
4233 set CSW_SPROT [expr 1 << 30]
4234 samv.dap apcsw 0 $CSW_SPROT
4237 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4238 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4240 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4241 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4242 example with a proper dap name:
4244 xxx.dap apcsw default
4248 @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
4249 Set/get quirks mode for TI TMS450/TMS570 processors
4254 @node CPU Configuration
4255 @chapter CPU Configuration
4258 This chapter discusses how to set up GDB debug targets for CPUs.
4259 You can also access these targets without GDB
4260 (@pxref{Architecture and Core Commands},
4261 and @ref{targetstatehandling,,Target State handling}) and
4262 through various kinds of NAND and NOR flash commands.
4263 If you have multiple CPUs you can have multiple such targets.
4265 We'll start by looking at how to examine the targets you have,
4266 then look at how to add one more target and how to configure it.
4268 @section Target List
4269 @cindex target, current
4270 @cindex target, list
4272 All targets that have been set up are part of a list,
4273 where each member has a name.
4274 That name should normally be the same as the TAP name.
4275 You can display the list with the @command{targets}
4277 This display often has only one CPU; here's what it might
4278 look like with more than one:
4280 TargetName Type Endian TapName State
4281 -- ------------------ ---------- ------ ------------------ ------------
4282 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4283 1 MyTarget cortex_m little mychip.foo tap-disabled
4286 One member of that list is the @dfn{current target}, which
4287 is implicitly referenced by many commands.
4288 It's the one marked with a @code{*} near the target name.
4289 In particular, memory addresses often refer to the address
4290 space seen by that current target.
4291 Commands like @command{mdw} (memory display words)
4292 and @command{flash erase_address} (erase NOR flash blocks)
4293 are examples; and there are many more.
4295 Several commands let you examine the list of targets:
4297 @deffn Command {target current}
4298 Returns the name of the current target.
4301 @deffn Command {target names}
4302 Lists the names of all current targets in the list.
4304 foreach t [target names] @{
4305 puts [format "Target: %s\n" $t]
4310 @c yep, "target list" would have been better.
4311 @c plus maybe "target setdefault".
4313 @deffn Command targets [name]
4314 @emph{Note: the name of this command is plural. Other target
4315 command names are singular.}
4317 With no parameter, this command displays a table of all known
4318 targets in a user friendly form.
4320 With a parameter, this command sets the current target to
4321 the given target with the given @var{name}; this is
4322 only relevant on boards which have more than one target.
4325 @section Target CPU Types
4329 Each target has a @dfn{CPU type}, as shown in the output of
4330 the @command{targets} command. You need to specify that type
4331 when calling @command{target create}.
4332 The CPU type indicates more than just the instruction set.
4333 It also indicates how that instruction set is implemented,
4334 what kind of debug support it integrates,
4335 whether it has an MMU (and if so, what kind),
4336 what core-specific commands may be available
4337 (@pxref{Architecture and Core Commands}),
4340 It's easy to see what target types are supported,
4341 since there's a command to list them.
4343 @anchor{targettypes}
4344 @deffn Command {target types}
4345 Lists all supported target types.
4346 At this writing, the supported CPU types are:
4349 @item @code{arm11} -- this is a generation of ARMv6 cores
4350 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4351 @item @code{arm7tdmi} -- this is an ARMv4 core
4352 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4353 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4354 @item @code{arm966e} -- this is an ARMv5 core
4355 @item @code{arm9tdmi} -- this is an ARMv4 core
4356 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4357 (Support for this is preliminary and incomplete.)
4358 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4359 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4360 compact Thumb2 instruction set.
4361 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4362 @item @code{dragonite} -- resembles arm966e
4363 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4364 (Support for this is still incomplete.)
4365 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4366 The current implementation supports eSi-32xx cores.
4367 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4368 @item @code{feroceon} -- resembles arm926
4369 @item @code{mips_m4k} -- a MIPS core
4370 @item @code{xscale} -- this is actually an architecture,
4371 not a CPU type. It is based on the ARMv5 architecture.
4372 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4373 The current implementation supports three JTAG TAP cores:
4374 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4375 allowing access to physical memory addresses independently of CPU cores.
4377 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4378 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4379 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4381 And two debug interfaces cores:
4383 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4384 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4389 To avoid being confused by the variety of ARM based cores, remember
4390 this key point: @emph{ARM is a technology licencing company}.
4391 (See: @url{http://www.arm.com}.)
4392 The CPU name used by OpenOCD will reflect the CPU design that was
4393 licensed, not a vendor brand which incorporates that design.
4394 Name prefixes like arm7, arm9, arm11, and cortex
4395 reflect design generations;
4396 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4397 reflect an architecture version implemented by a CPU design.
4399 @anchor{targetconfiguration}
4400 @section Target Configuration
4402 Before creating a ``target'', you must have added its TAP to the scan chain.
4403 When you've added that TAP, you will have a @code{dotted.name}
4404 which is used to set up the CPU support.
4405 The chip-specific configuration file will normally configure its CPU(s)
4406 right after it adds all of the chip's TAPs to the scan chain.
4408 Although you can set up a target in one step, it's often clearer if you
4409 use shorter commands and do it in two steps: create it, then configure
4411 All operations on the target after it's created will use a new
4412 command, created as part of target creation.
4414 The two main things to configure after target creation are
4415 a work area, which usually has target-specific defaults even
4416 if the board setup code overrides them later;
4417 and event handlers (@pxref{targetevents,,Target Events}), which tend
4418 to be much more board-specific.
4419 The key steps you use might look something like this
4422 dap create mychip.dap -chain-position mychip.cpu
4423 target create MyTarget cortex_m -dap mychip.dap
4424 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4425 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4426 MyTarget configure -event reset-init @{ myboard_reinit @}
4429 You should specify a working area if you can; typically it uses some
4431 Such a working area can speed up many things, including bulk
4432 writes to target memory;
4433 flash operations like checking to see if memory needs to be erased;
4434 GDB memory checksumming;
4438 On more complex chips, the work area can become
4439 inaccessible when application code
4440 (such as an operating system)
4441 enables or disables the MMU.
4442 For example, the particular MMU context used to access the virtual
4443 address will probably matter ... and that context might not have
4444 easy access to other addresses needed.
4445 At this writing, OpenOCD doesn't have much MMU intelligence.
4448 It's often very useful to define a @code{reset-init} event handler.
4449 For systems that are normally used with a boot loader,
4450 common tasks include updating clocks and initializing memory
4452 That may be needed to let you write the boot loader into flash,
4453 in order to ``de-brick'' your board; or to load programs into
4454 external DDR memory without having run the boot loader.
4456 @deffn Command {target create} target_name type configparams...
4457 This command creates a GDB debug target that refers to a specific JTAG tap.
4458 It enters that target into a list, and creates a new
4459 command (@command{@var{target_name}}) which is used for various
4460 purposes including additional configuration.
4463 @item @var{target_name} ... is the name of the debug target.
4464 By convention this should be the same as the @emph{dotted.name}
4465 of the TAP associated with this target, which must be specified here
4466 using the @code{-chain-position @var{dotted.name}} configparam.
4468 This name is also used to create the target object command,
4469 referred to here as @command{$target_name},
4470 and in other places the target needs to be identified.
4471 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4472 @item @var{configparams} ... all parameters accepted by
4473 @command{$target_name configure} are permitted.
4474 If the target is big-endian, set it here with @code{-endian big}.
4476 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4477 @code{-dap @var{dap_name}} here.
4481 @deffn Command {$target_name configure} configparams...
4482 The options accepted by this command may also be
4483 specified as parameters to @command{target create}.
4484 Their values can later be queried one at a time by
4485 using the @command{$target_name cget} command.
4487 @emph{Warning:} changing some of these after setup is dangerous.
4488 For example, moving a target from one TAP to another;
4489 and changing its endianness.
4493 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4494 used to access this target.
4496 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4497 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4498 create and manage DAP instances.
4500 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4501 whether the CPU uses big or little endian conventions
4503 @item @code{-event} @var{event_name} @var{event_body} --
4504 @xref{targetevents,,Target Events}.
4505 Note that this updates a list of named event handlers.
4506 Calling this twice with two different event names assigns
4507 two different handlers, but calling it twice with the
4508 same event name assigns only one handler.
4510 Current target is temporarily overridden to the event issuing target
4511 before handler code starts and switched back after handler is done.
4513 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4514 whether the work area gets backed up; by default,
4515 @emph{it is not backed up.}
4516 When possible, use a working_area that doesn't need to be backed up,
4517 since performing a backup slows down operations.
4518 For example, the beginning of an SRAM block is likely to
4519 be used by most build systems, but the end is often unused.
4521 @item @code{-work-area-size} @var{size} -- specify work are size,
4522 in bytes. The same size applies regardless of whether its physical
4523 or virtual address is being used.
4525 @item @code{-work-area-phys} @var{address} -- set the work area
4526 base @var{address} to be used when no MMU is active.
4528 @item @code{-work-area-virt} @var{address} -- set the work area
4529 base @var{address} to be used when an MMU is active.
4530 @emph{Do not specify a value for this except on targets with an MMU.}
4531 The value should normally correspond to a static mapping for the
4532 @code{-work-area-phys} address, set up by the current operating system.
4535 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4536 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4537 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4538 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}
4539 @xref{gdbrtossupport,,RTOS Support}.
4541 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4542 scan and after a reset. A manual call to arp_examine is required to
4543 access the target for debugging.
4545 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4546 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4547 Use this option with systems where multiple, independent cores are connected
4548 to separate access ports of the same DAP.
4550 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4551 to the target. Currently, only the @code{aarch64} target makes use of this option,
4552 where it is a mandatory configuration for the target run control.
4553 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4554 for instruction on how to declare and control a CTI instance.
4556 @anchor{gdbportoverride}
4557 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4558 possible values of the parameter @var{number}, which are not only numeric values.
4559 Use this option to override, for this target only, the global parameter set with
4560 command @command{gdb_port}.
4561 @xref{gdb_port,,command gdb_port}.
4565 @section Other $target_name Commands
4566 @cindex object command
4568 The Tcl/Tk language has the concept of object commands,
4569 and OpenOCD adopts that same model for targets.
4571 A good Tk example is a on screen button.
4572 Once a button is created a button
4573 has a name (a path in Tk terms) and that name is useable as a first
4574 class command. For example in Tk, one can create a button and later
4575 configure it like this:
4579 button .foobar -background red -command @{ foo @}
4581 .foobar configure -foreground blue
4583 set x [.foobar cget -background]
4585 puts [format "The button is %s" $x]
4588 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4589 button, and its object commands are invoked the same way.
4592 str912.cpu mww 0x1234 0x42
4593 omap3530.cpu mww 0x5555 123
4596 The commands supported by OpenOCD target objects are:
4598 @deffn Command {$target_name arp_examine} @option{allow-defer}
4599 @deffnx Command {$target_name arp_halt}
4600 @deffnx Command {$target_name arp_poll}
4601 @deffnx Command {$target_name arp_reset}
4602 @deffnx Command {$target_name arp_waitstate}
4603 Internal OpenOCD scripts (most notably @file{startup.tcl})
4604 use these to deal with specific reset cases.
4605 They are not otherwise documented here.
4608 @deffn Command {$target_name array2mem} arrayname width address count
4609 @deffnx Command {$target_name mem2array} arrayname width address count
4610 These provide an efficient script-oriented interface to memory.
4611 The @code{array2mem} primitive writes bytes, halfwords, or words;
4612 while @code{mem2array} reads them.
4613 In both cases, the TCL side uses an array, and
4614 the target side uses raw memory.
4616 The efficiency comes from enabling the use of
4617 bulk JTAG data transfer operations.
4618 The script orientation comes from working with data
4619 values that are packaged for use by TCL scripts;
4620 @command{mdw} type primitives only print data they retrieve,
4621 and neither store nor return those values.
4624 @item @var{arrayname} ... is the name of an array variable
4625 @item @var{width} ... is 8/16/32 - indicating the memory access size
4626 @item @var{address} ... is the target memory address
4627 @item @var{count} ... is the number of elements to process
4631 @deffn Command {$target_name cget} queryparm
4632 Each configuration parameter accepted by
4633 @command{$target_name configure}
4634 can be individually queried, to return its current value.
4635 The @var{queryparm} is a parameter name
4636 accepted by that command, such as @code{-work-area-phys}.
4637 There are a few special cases:
4640 @item @code{-event} @var{event_name} -- returns the handler for the
4641 event named @var{event_name}.
4642 This is a special case because setting a handler requires
4644 @item @code{-type} -- returns the target type.
4645 This is a special case because this is set using
4646 @command{target create} and can't be changed
4647 using @command{$target_name configure}.
4650 For example, if you wanted to summarize information about
4651 all the targets you might use something like this:
4654 foreach name [target names] @{
4655 set y [$name cget -endian]
4656 set z [$name cget -type]
4657 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4663 @anchor{targetcurstate}
4664 @deffn Command {$target_name curstate}
4665 Displays the current target state:
4666 @code{debug-running},
4669 @code{running}, or @code{unknown}.
4670 (Also, @pxref{eventpolling,,Event Polling}.)
4673 @deffn Command {$target_name eventlist}
4674 Displays a table listing all event handlers
4675 currently associated with this target.
4676 @xref{targetevents,,Target Events}.
4679 @deffn Command {$target_name invoke-event} event_name
4680 Invokes the handler for the event named @var{event_name}.
4681 (This is primarily intended for use by OpenOCD framework
4682 code, for example by the reset code in @file{startup.tcl}.)
4685 @deffn Command {$target_name mdw} addr [count]
4686 @deffnx Command {$target_name mdh} addr [count]
4687 @deffnx Command {$target_name mdb} addr [count]
4688 Display contents of address @var{addr}, as
4689 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4690 or 8-bit bytes (@command{mdb}).
4691 If @var{count} is specified, displays that many units.
4692 (If you want to manipulate the data instead of displaying it,
4693 see the @code{mem2array} primitives.)
4696 @deffn Command {$target_name mww} addr word
4697 @deffnx Command {$target_name mwh} addr halfword
4698 @deffnx Command {$target_name mwb} addr byte
4699 Writes the specified @var{word} (32 bits),
4700 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4701 at the specified address @var{addr}.
4704 @anchor{targetevents}
4705 @section Target Events
4706 @cindex target events
4708 At various times, certain things can happen, or you want them to happen.
4711 @item What should happen when GDB connects? Should your target reset?
4712 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4713 @item Is using SRST appropriate (and possible) on your system?
4714 Or instead of that, do you need to issue JTAG commands to trigger reset?
4715 SRST usually resets everything on the scan chain, which can be inappropriate.
4716 @item During reset, do you need to write to certain memory locations
4717 to set up system clocks or
4718 to reconfigure the SDRAM?
4719 How about configuring the watchdog timer, or other peripherals,
4720 to stop running while you hold the core stopped for debugging?
4723 All of the above items can be addressed by target event handlers.
4724 These are set up by @command{$target_name configure -event} or
4725 @command{target create ... -event}.
4727 The programmer's model matches the @code{-command} option used in Tcl/Tk
4728 buttons and events. The two examples below act the same, but one creates
4729 and invokes a small procedure while the other inlines it.
4732 proc my_init_proc @{ @} @{
4733 echo "Disabling watchdog..."
4734 mww 0xfffffd44 0x00008000
4736 mychip.cpu configure -event reset-init my_init_proc
4737 mychip.cpu configure -event reset-init @{
4738 echo "Disabling watchdog..."
4739 mww 0xfffffd44 0x00008000
4743 The following target events are defined:
4746 @item @b{debug-halted}
4747 @* The target has halted for debug reasons (i.e.: breakpoint)
4748 @item @b{debug-resumed}
4749 @* The target has resumed (i.e.: GDB said run)
4750 @item @b{early-halted}
4751 @* Occurs early in the halt process
4752 @item @b{examine-start}
4753 @* Before target examine is called.
4754 @item @b{examine-end}
4755 @* After target examine is called with no errors.
4756 @item @b{gdb-attach}
4757 @* When GDB connects. Issued before any GDB communication with the target
4758 starts. GDB expects the target is halted during attachment.
4759 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
4760 connect GDB to running target.
4761 The event can be also used to set up the target so it is possible to probe flash.
4762 Probing flash is necessary during GDB connect if you want to use
4763 @pxref{programmingusinggdb,,programming using GDB}.
4764 Another use of the flash memory map is for GDB to automatically choose
4765 hardware or software breakpoints depending on whether the breakpoint
4766 is in RAM or read only memory.
4767 Default is @code{halt}
4768 @item @b{gdb-detach}
4769 @* When GDB disconnects
4771 @* When the target has halted and GDB is not doing anything (see early halt)
4772 @item @b{gdb-flash-erase-start}
4773 @* Before the GDB flash process tries to erase the flash (default is
4775 @item @b{gdb-flash-erase-end}
4776 @* After the GDB flash process has finished erasing the flash
4777 @item @b{gdb-flash-write-start}
4778 @* Before GDB writes to the flash
4779 @item @b{gdb-flash-write-end}
4780 @* After GDB writes to the flash (default is @code{reset halt})
4782 @* Before the target steps, GDB is trying to start/resume the target
4784 @* The target has halted
4785 @item @b{reset-assert-pre}
4786 @* Issued as part of @command{reset} processing
4787 after @command{reset-start} was triggered
4788 but before either SRST alone is asserted on the scan chain,
4789 or @code{reset-assert} is triggered.
4790 @item @b{reset-assert}
4791 @* Issued as part of @command{reset} processing
4792 after @command{reset-assert-pre} was triggered.
4793 When such a handler is present, cores which support this event will use
4794 it instead of asserting SRST.
4795 This support is essential for debugging with JTAG interfaces which
4796 don't include an SRST line (JTAG doesn't require SRST), and for
4797 selective reset on scan chains that have multiple targets.
4798 @item @b{reset-assert-post}
4799 @* Issued as part of @command{reset} processing
4800 after @code{reset-assert} has been triggered.
4801 or the target asserted SRST on the entire scan chain.
4802 @item @b{reset-deassert-pre}
4803 @* Issued as part of @command{reset} processing
4804 after @code{reset-assert-post} has been triggered.
4805 @item @b{reset-deassert-post}
4806 @* Issued as part of @command{reset} processing
4807 after @code{reset-deassert-pre} has been triggered
4808 and (if the target is using it) after SRST has been
4809 released on the scan chain.
4811 @* Issued as the final step in @command{reset} processing.
4812 @item @b{reset-init}
4813 @* Used by @b{reset init} command for board-specific initialization.
4814 This event fires after @emph{reset-deassert-post}.
4816 This is where you would configure PLLs and clocking, set up DRAM so
4817 you can download programs that don't fit in on-chip SRAM, set up pin
4818 multiplexing, and so on.
4819 (You may be able to switch to a fast JTAG clock rate here, after
4820 the target clocks are fully set up.)
4821 @item @b{reset-start}
4822 @* Issued as the first step in @command{reset} processing
4823 before @command{reset-assert-pre} is called.
4825 This is the most robust place to use @command{jtag_rclk}
4826 or @command{adapter_khz} to switch to a low JTAG clock rate,
4827 when reset disables PLLs needed to use a fast clock.
4828 @item @b{resume-start}
4829 @* Before any target is resumed
4830 @item @b{resume-end}
4831 @* After all targets have resumed
4833 @* Target has resumed
4834 @item @b{trace-config}
4835 @* After target hardware trace configuration was changed
4838 @node Flash Commands
4839 @chapter Flash Commands
4841 OpenOCD has different commands for NOR and NAND flash;
4842 the ``flash'' command works with NOR flash, while
4843 the ``nand'' command works with NAND flash.
4844 This partially reflects different hardware technologies:
4845 NOR flash usually supports direct CPU instruction and data bus access,
4846 while data from a NAND flash must be copied to memory before it can be
4847 used. (SPI flash must also be copied to memory before use.)
4848 However, the documentation also uses ``flash'' as a generic term;
4849 for example, ``Put flash configuration in board-specific files''.
4853 @item Configure via the command @command{flash bank}
4854 @* Do this in a board-specific configuration file,
4855 passing parameters as needed by the driver.
4856 @item Operate on the flash via @command{flash subcommand}
4857 @* Often commands to manipulate the flash are typed by a human, or run
4858 via a script in some automated way. Common tasks include writing a
4859 boot loader, operating system, or other data.
4861 @* Flashing via GDB requires the flash be configured via ``flash
4862 bank'', and the GDB flash features be enabled.
4863 @xref{gdbconfiguration,,GDB Configuration}.
4866 Many CPUs have the ability to ``boot'' from the first flash bank.
4867 This means that misprogramming that bank can ``brick'' a system,
4868 so that it can't boot.
4869 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4870 board by (re)installing working boot firmware.
4872 @anchor{norconfiguration}
4873 @section Flash Configuration Commands
4874 @cindex flash configuration
4876 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4877 Configures a flash bank which provides persistent storage
4878 for addresses from @math{base} to @math{base + size - 1}.
4879 These banks will often be visible to GDB through the target's memory map.
4880 In some cases, configuring a flash bank will activate extra commands;
4881 see the driver-specific documentation.
4884 @item @var{name} ... may be used to reference the flash bank
4885 in other flash commands. A number is also available.
4886 @item @var{driver} ... identifies the controller driver
4887 associated with the flash bank being declared.
4888 This is usually @code{cfi} for external flash, or else
4889 the name of a microcontroller with embedded flash memory.
4890 @xref{flashdriverlist,,Flash Driver List}.
4891 @item @var{base} ... Base address of the flash chip.
4892 @item @var{size} ... Size of the chip, in bytes.
4893 For some drivers, this value is detected from the hardware.
4894 @item @var{chip_width} ... Width of the flash chip, in bytes;
4895 ignored for most microcontroller drivers.
4896 @item @var{bus_width} ... Width of the data bus used to access the
4897 chip, in bytes; ignored for most microcontroller drivers.
4898 @item @var{target} ... Names the target used to issue
4899 commands to the flash controller.
4900 @comment Actually, it's currently a controller-specific parameter...
4901 @item @var{driver_options} ... drivers may support, or require,
4902 additional parameters. See the driver-specific documentation
4903 for more information.
4906 This command is not available after OpenOCD initialization has completed.
4907 Use it in board specific configuration files, not interactively.
4911 @comment the REAL name for this command is "ocd_flash_banks"
4912 @comment less confusing would be: "flash list" (like "nand list")
4913 @deffn Command {flash banks}
4914 Prints a one-line summary of each device that was
4915 declared using @command{flash bank}, numbered from zero.
4916 Note that this is the @emph{plural} form;
4917 the @emph{singular} form is a very different command.
4920 @deffn Command {flash list}
4921 Retrieves a list of associative arrays for each device that was
4922 declared using @command{flash bank}, numbered from zero.
4923 This returned list can be manipulated easily from within scripts.
4926 @deffn Command {flash probe} num
4927 Identify the flash, or validate the parameters of the configured flash. Operation
4928 depends on the flash type.
4929 The @var{num} parameter is a value shown by @command{flash banks}.
4930 Most flash commands will implicitly @emph{autoprobe} the bank;
4931 flash drivers can distinguish between probing and autoprobing,
4932 but most don't bother.
4935 @section Erasing, Reading, Writing to Flash
4936 @cindex flash erasing
4937 @cindex flash reading
4938 @cindex flash writing
4939 @cindex flash programming
4940 @anchor{flashprogrammingcommands}
4942 One feature distinguishing NOR flash from NAND or serial flash technologies
4943 is that for read access, it acts exactly like any other addressable memory.
4944 This means you can use normal memory read commands like @command{mdw} or
4945 @command{dump_image} with it, with no special @command{flash} subcommands.
4946 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4948 Write access works differently. Flash memory normally needs to be erased
4949 before it's written. Erasing a sector turns all of its bits to ones, and
4950 writing can turn ones into zeroes. This is why there are special commands
4951 for interactive erasing and writing, and why GDB needs to know which parts
4952 of the address space hold NOR flash memory.
4955 Most of these erase and write commands leverage the fact that NOR flash
4956 chips consume target address space. They implicitly refer to the current
4957 JTAG target, and map from an address in that target's address space
4958 back to a flash bank.
4959 @comment In May 2009, those mappings may fail if any bank associated
4960 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
4961 A few commands use abstract addressing based on bank and sector numbers,
4962 and don't depend on searching the current target and its address space.
4963 Avoid confusing the two command models.
4966 Some flash chips implement software protection against accidental writes,
4967 since such buggy writes could in some cases ``brick'' a system.
4968 For such systems, erasing and writing may require sector protection to be
4970 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4971 and AT91SAM7 on-chip flash.
4972 @xref{flashprotect,,flash protect}.
4974 @deffn Command {flash erase_sector} num first last
4975 Erase sectors in bank @var{num}, starting at sector @var{first}
4976 up to and including @var{last}.
4977 Sector numbering starts at 0.
4978 Providing a @var{last} sector of @option{last}
4979 specifies "to the end of the flash bank".
4980 The @var{num} parameter is a value shown by @command{flash banks}.
4983 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4984 Erase sectors starting at @var{address} for @var{length} bytes.
4985 Unless @option{pad} is specified, @math{address} must begin a
4986 flash sector, and @math{address + length - 1} must end a sector.
4987 Specifying @option{pad} erases extra data at the beginning and/or
4988 end of the specified region, as needed to erase only full sectors.
4989 The flash bank to use is inferred from the @var{address}, and
4990 the specified length must stay within that bank.
4991 As a special case, when @var{length} is zero and @var{address} is
4992 the start of the bank, the whole flash is erased.
4993 If @option{unlock} is specified, then the flash is unprotected
4994 before erase starts.
4997 @deffn Command {flash fillw} address word length
4998 @deffnx Command {flash fillh} address halfword length
4999 @deffnx Command {flash fillb} address byte length
5000 Fills flash memory with the specified @var{word} (32 bits),
5001 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5002 starting at @var{address} and continuing
5003 for @var{length} units (word/halfword/byte).
5004 No erasure is done before writing; when needed, that must be done
5005 before issuing this command.
5006 Writes are done in blocks of up to 1024 bytes, and each write is
5007 verified by reading back the data and comparing it to what was written.
5008 The flash bank to use is inferred from the @var{address} of
5009 each block, and the specified length must stay within that bank.
5011 @comment no current checks for errors if fill blocks touch multiple banks!
5013 @deffn Command {flash write_bank} num filename [offset]
5014 Write the binary @file{filename} to flash bank @var{num},
5015 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5016 is omitted, start at the beginning of the flash bank.
5017 The @var{num} parameter is a value shown by @command{flash banks}.
5020 @deffn Command {flash read_bank} num filename [offset [length]]
5021 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5022 and write the contents to the binary @file{filename}. If @var{offset} is
5023 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5024 read the remaining bytes from the flash bank.
5025 The @var{num} parameter is a value shown by @command{flash banks}.
5028 @deffn Command {flash verify_bank} num filename [offset]
5029 Compare the contents of the binary file @var{filename} with the contents of the
5030 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5031 start at the beginning of the flash bank. Fail if the contents do not match.
5032 The @var{num} parameter is a value shown by @command{flash banks}.
5035 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
5036 Write the image @file{filename} to the current target's flash bank(s).
5037 Only loadable sections from the image are written.
5038 A relocation @var{offset} may be specified, in which case it is added
5039 to the base address for each section in the image.
5040 The file [@var{type}] can be specified
5041 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5042 @option{elf} (ELF file), @option{s19} (Motorola s19).
5043 @option{mem}, or @option{builder}.
5044 The relevant flash sectors will be erased prior to programming
5045 if the @option{erase} parameter is given. If @option{unlock} is
5046 provided, then the flash banks are unlocked before erase and
5047 program. The flash bank to use is inferred from the address of
5051 Be careful using the @option{erase} flag when the flash is holding
5052 data you want to preserve.
5053 Portions of the flash outside those described in the image's
5054 sections might be erased with no notice.
5057 When a section of the image being written does not fill out all the
5058 sectors it uses, the unwritten parts of those sectors are necessarily
5059 also erased, because sectors can't be partially erased.
5061 Data stored in sector "holes" between image sections are also affected.
5062 For example, "@command{flash write_image erase ...}" of an image with
5063 one byte at the beginning of a flash bank and one byte at the end
5064 erases the entire bank -- not just the two sectors being written.
5066 Also, when flash protection is important, you must re-apply it after
5067 it has been removed by the @option{unlock} flag.
5072 @section Other Flash commands
5073 @cindex flash protection
5075 @deffn Command {flash erase_check} num
5076 Check erase state of sectors in flash bank @var{num},
5077 and display that status.
5078 The @var{num} parameter is a value shown by @command{flash banks}.
5081 @deffn Command {flash info} num [sectors]
5082 Print info about flash bank @var{num}, a list of protection blocks
5083 and their status. Use @option{sectors} to show a list of sectors instead.
5085 The @var{num} parameter is a value shown by @command{flash banks}.
5086 This command will first query the hardware, it does not print cached
5087 and possibly stale information.
5090 @anchor{flashprotect}
5091 @deffn Command {flash protect} num first last (@option{on}|@option{off})
5092 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5093 in flash bank @var{num}, starting at protection block @var{first}
5094 and continuing up to and including @var{last}.
5095 Providing a @var{last} block of @option{last}
5096 specifies "to the end of the flash bank".
5097 The @var{num} parameter is a value shown by @command{flash banks}.
5098 The protection block is usually identical to a flash sector.
5099 Some devices may utilize a protection block distinct from flash sector.
5100 See @command{flash info} for a list of protection blocks.
5103 @deffn Command {flash padded_value} num value
5104 Sets the default value used for padding any image sections, This should
5105 normally match the flash bank erased value. If not specified by this
5106 command or the flash driver then it defaults to 0xff.
5110 @deffn Command {program} filename [verify] [reset] [exit] [offset]
5111 This is a helper script that simplifies using OpenOCD as a standalone
5112 programmer. The only required parameter is @option{filename}, the others are optional.
5113 @xref{Flash Programming}.
5116 @anchor{flashdriverlist}
5117 @section Flash Driver List
5118 As noted above, the @command{flash bank} command requires a driver name,
5119 and allows driver-specific options and behaviors.
5120 Some drivers also activate driver-specific commands.
5122 @deffn {Flash Driver} virtual
5123 This is a special driver that maps a previously defined bank to another
5124 address. All bank settings will be copied from the master physical bank.
5126 The @var{virtual} driver defines one mandatory parameters,
5129 @item @var{master_bank} The bank that this virtual address refers to.
5132 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5133 the flash bank defined at address 0x1fc00000. Any command executed on
5134 the virtual banks is actually performed on the physical banks.
5136 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5137 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5138 $_TARGETNAME $_FLASHNAME
5139 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5140 $_TARGETNAME $_FLASHNAME
5144 @subsection External Flash
5146 @deffn {Flash Driver} cfi
5147 @cindex Common Flash Interface
5149 The ``Common Flash Interface'' (CFI) is the main standard for
5150 external NOR flash chips, each of which connects to a
5151 specific external chip select on the CPU.
5152 Frequently the first such chip is used to boot the system.
5153 Your board's @code{reset-init} handler might need to
5154 configure additional chip selects using other commands (like: @command{mww} to
5155 configure a bus and its timings), or
5156 perhaps configure a GPIO pin that controls the ``write protect'' pin
5158 The CFI driver can use a target-specific working area to significantly
5161 The CFI driver can accept the following optional parameters, in any order:
5164 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5165 like AM29LV010 and similar types.
5166 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5167 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5168 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5169 swapped when writing data values (i.e. not CFI commands).
5172 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5173 wide on a sixteen bit bus:
5176 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5177 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5180 To configure one bank of 32 MBytes
5181 built from two sixteen bit (two byte) wide parts wired in parallel
5182 to create a thirty-two bit (four byte) bus with doubled throughput:
5185 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5188 @c "cfi part_id" disabled
5191 @deffn {Flash Driver} jtagspi
5192 @cindex Generic JTAG2SPI driver
5196 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5197 SPI flash connected to them. To access this flash from the host, the device
5198 is first programmed with a special proxy bitstream that
5199 exposes the SPI flash on the device's JTAG interface. The flash can then be
5200 accessed through JTAG.
5202 Since signaling between JTAG and SPI is compatible, all that is required for
5203 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5204 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5205 a bitstream for several Xilinx FPGAs can be found in
5206 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5207 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5209 This flash bank driver requires a target on a JTAG tap and will access that
5210 tap directly. Since no support from the target is needed, the target can be a
5211 "testee" dummy. Since the target does not expose the flash memory
5212 mapping, target commands that would otherwise be expected to access the flash
5213 will not work. These include all @command{*_image} and
5214 @command{$target_name m*} commands as well as @command{program}. Equivalent
5215 functionality is available through the @command{flash write_bank},
5216 @command{flash read_bank}, and @command{flash verify_bank} commands.
5219 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5220 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5221 @var{USER1} instruction.
5225 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5226 set _XILINX_USER1 0x02
5227 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5228 $_TARGETNAME $_XILINX_USER1
5232 @deffn {Flash Driver} xcf
5233 @cindex Xilinx Platform flash driver
5235 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5236 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5237 only difference is special registers controlling its FPGA specific behavior.
5238 They must be properly configured for successful FPGA loading using
5239 additional @var{xcf} driver command:
5241 @deffn Command {xcf ccb} <bank_id>
5242 command accepts additional parameters:
5244 @item @var{external|internal} ... selects clock source.
5245 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5246 @item @var{slave|master} ... selects slave of master mode for flash device.
5247 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5251 xcf ccb 0 external parallel slave 40
5253 All of them must be specified even if clock frequency is pointless
5254 in slave mode. If only bank id specified than command prints current
5255 CCB register value. Note: there is no need to write this register
5256 every time you erase/program data sectors because it stores in
5260 @deffn Command {xcf configure} <bank_id>
5261 Initiates FPGA loading procedure. Useful if your board has no "configure"
5268 Additional driver notes:
5270 @item Only single revision supported.
5271 @item Driver automatically detects need of bit reverse, but
5272 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5273 (Intel hex) file types supported.
5274 @item For additional info check xapp972.pdf and ug380.pdf.
5278 @deffn {Flash Driver} lpcspifi
5279 @cindex NXP SPI Flash Interface
5282 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5283 Flash Interface (SPIFI) peripheral that can drive and provide
5284 memory mapped access to external SPI flash devices.
5286 The lpcspifi driver initializes this interface and provides
5287 program and erase functionality for these serial flash devices.
5288 Use of this driver @b{requires} a working area of at least 1kB
5289 to be configured on the target device; more than this will
5290 significantly reduce flash programming times.
5292 The setup command only requires the @var{base} parameter. All
5293 other parameters are ignored, and the flash size and layout
5294 are configured by the driver.
5297 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5302 @deffn {Flash Driver} stmsmi
5303 @cindex STMicroelectronics Serial Memory Interface
5306 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5307 SPEAr MPU family) include a proprietary
5308 ``Serial Memory Interface'' (SMI) controller able to drive external
5310 Depending on specific device and board configuration, up to 4 external
5311 flash devices can be connected.
5313 SMI makes the flash content directly accessible in the CPU address
5314 space; each external device is mapped in a memory bank.
5315 CPU can directly read data, execute code and boot from SMI banks.
5316 Normal OpenOCD commands like @command{mdw} can be used to display
5319 The setup command only requires the @var{base} parameter in order
5320 to identify the memory bank.
5321 All other parameters are ignored. Additional information, like
5322 flash size, are detected automatically.
5325 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5330 @deffn {Flash Driver} mrvlqspi
5331 This driver supports QSPI flash controller of Marvell's Wireless
5332 Microcontroller platform.
5334 The flash size is autodetected based on the table of known JEDEC IDs
5335 hardcoded in the OpenOCD sources.
5338 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5343 @deffn {Flash Driver} ath79
5344 @cindex Atheros ath79 SPI driver
5346 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5348 On reset a SPI flash connected to the first chip select (CS0) is made
5349 directly read-accessible in the CPU address space (up to 16MBytes)
5350 and is usually used to store the bootloader and operating system.
5351 Normal OpenOCD commands like @command{mdw} can be used to display
5352 the flash content while it is in memory-mapped mode (only the first
5353 4MBytes are accessible without additional configuration on reset).
5355 The setup command only requires the @var{base} parameter in order
5356 to identify the memory bank. The actual value for the base address
5357 is not otherwise used by the driver. However the mapping is passed
5358 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5359 address should be the actual memory mapped base address. For unmapped
5360 chipselects (CS1 and CS2) care should be taken to use a base address
5361 that does not overlap with real memory regions.
5362 Additional information, like flash size, are detected automatically.
5363 An optional additional parameter sets the chipselect for the bank,
5364 with the default CS0.
5365 CS1 and CS2 require additional GPIO setup before they can be used
5366 since the alternate function must be enabled on the GPIO pin
5367 CS1/CS2 is routed to on the given SoC.
5370 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
5372 # When using multiple chipselects the base should be different for each,
5373 # otherwise the write_image command is not able to distinguish the
5375 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
5376 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5377 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5382 @deffn {Flash Driver} fespi
5383 @cindex Freedom E SPI
5386 SiFive's Freedom E SPI controller, used in HiFive and other boards.
5389 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
5393 @subsection Internal Flash (Microcontrollers)
5395 @deffn {Flash Driver} aduc702x
5396 The ADUC702x analog microcontrollers from Analog Devices
5397 include internal flash and use ARM7TDMI cores.
5398 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5399 The setup command only requires the @var{target} argument
5400 since all devices in this family have the same memory layout.
5403 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5407 @deffn {Flash Driver} ambiqmicro
5410 All members of the Apollo microcontroller family from
5411 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5412 The host connects over USB to an FTDI interface that communicates
5413 with the target using SWD.
5415 The @var{ambiqmicro} driver reads the Chip Information Register detect
5416 the device class of the MCU.
5417 The Flash and SRAM sizes directly follow device class, and are used
5418 to set up the flash banks.
5419 If this fails, the driver will use default values set to the minimum
5420 sizes of an Apollo chip.
5422 All Apollo chips have two flash banks of the same size.
5423 In all cases the first flash bank starts at location 0,
5424 and the second bank starts after the first.
5428 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5429 # Flash bank 1 - same size as bank0, starts after bank 0.
5430 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5434 Flash is programmed using custom entry points into the bootloader.
5435 This is the only way to program the flash as no flash control registers
5436 are available to the user.
5438 The @var{ambiqmicro} driver adds some additional commands:
5440 @deffn Command {ambiqmicro mass_erase} <bank>
5443 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
5446 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
5447 Program OTP is a one time operation to create write protected flash.
5448 The user writes sectors to SRAM starting at 0x10000010.
5449 Program OTP will write these sectors from SRAM to flash, and write protect
5455 @deffn {Flash Driver} at91samd
5457 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
5458 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5460 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
5462 The devices have one flash bank:
5465 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
5468 @deffn Command {at91samd chip-erase}
5469 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5470 used to erase a chip back to its factory state and does not require the
5471 processor to be halted.
5474 @deffn Command {at91samd set-security}
5475 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5476 to the Flash and can only be undone by using the chip-erase command which
5477 erases the Flash contents and turns off the security bit. Warning: at this
5478 time, openocd will not be able to communicate with a secured chip and it is
5479 therefore not possible to chip-erase it without using another tool.
5482 at91samd set-security enable
5486 @deffn Command {at91samd eeprom}
5487 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5488 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5489 must be one of the permitted sizes according to the datasheet. Settings are
5490 written immediately but only take effect on MCU reset. EEPROM emulation
5491 requires additional firmware support and the minimum EEPROM size may not be
5492 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5493 in order to disable this feature.
5497 at91samd eeprom 1024
5501 @deffn Command {at91samd bootloader}
5502 Shows or sets the bootloader size configuration, stored in the User Row of the
5503 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5504 must be specified in bytes and it must be one of the permitted sizes according
5505 to the datasheet. Settings are written immediately but only take effect on
5506 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5510 at91samd bootloader 16384
5514 @deffn Command {at91samd dsu_reset_deassert}
5515 This command releases internal reset held by DSU
5516 and prepares reset vector catch in case of reset halt.
5517 Command is used internally in event event reset-deassert-post.
5520 @deffn Command {at91samd nvmuserrow}
5521 Writes or reads the entire 64 bit wide NVM user row register which is located at
5522 0x804000. This register includes various fuses lock-bits and factory calibration
5523 data. Reading the register is done by invoking this command without any
5524 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
5525 is the register value to be written and the second one is an optional changemask.
5526 Every bit which value in changemask is 0 will stay unchanged. The lock- and
5527 reserved-bits are masked out and cannot be changed.
5531 >at91samd nvmuserrow
5532 NVMUSERROW: 0xFFFFFC5DD8E0C788
5533 # Write 0xFFFFFC5DD8E0C788 to user row
5534 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
5535 # Write 0x12300 to user row but leave other bits and low byte unchanged
5536 >at91samd nvmuserrow 0x12345 0xFFF00
5543 @deffn {Flash Driver} at91sam3
5545 All members of the AT91SAM3 microcontroller family from
5546 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5547 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5548 that the driver was orginaly developed and tested using the
5549 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5550 the family was cribbed from the data sheet. @emph{Note to future
5551 readers/updaters: Please remove this worrisome comment after other
5552 chips are confirmed.}
5554 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5555 have one flash bank. In all cases the flash banks are at
5556 the following fixed locations:
5559 # Flash bank 0 - all chips
5560 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5561 # Flash bank 1 - only 256K chips
5562 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5565 Internally, the AT91SAM3 flash memory is organized as follows.
5566 Unlike the AT91SAM7 chips, these are not used as parameters
5567 to the @command{flash bank} command:
5570 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5571 @item @emph{Bank Size:} 128K/64K Per flash bank
5572 @item @emph{Sectors:} 16 or 8 per bank
5573 @item @emph{SectorSize:} 8K Per Sector
5574 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5577 The AT91SAM3 driver adds some additional commands:
5579 @deffn Command {at91sam3 gpnvm}
5580 @deffnx Command {at91sam3 gpnvm clear} number
5581 @deffnx Command {at91sam3 gpnvm set} number
5582 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5583 With no parameters, @command{show} or @command{show all},
5584 shows the status of all GPNVM bits.
5585 With @command{show} @var{number}, displays that bit.
5587 With @command{set} @var{number} or @command{clear} @var{number},
5588 modifies that GPNVM bit.
5591 @deffn Command {at91sam3 info}
5592 This command attempts to display information about the AT91SAM3
5593 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5594 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5595 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5596 various clock configuration registers and attempts to display how it
5597 believes the chip is configured. By default, the SLOWCLK is assumed to
5598 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5601 @deffn Command {at91sam3 slowclk} [value]
5602 This command shows/sets the slow clock frequency used in the
5603 @command{at91sam3 info} command calculations above.
5607 @deffn {Flash Driver} at91sam4
5609 All members of the AT91SAM4 microcontroller family from
5610 Atmel include internal flash and use ARM's Cortex-M4 core.
5611 This driver uses the same command names/syntax as @xref{at91sam3}.
5614 @deffn {Flash Driver} at91sam4l
5616 All members of the AT91SAM4L microcontroller family from
5617 Atmel include internal flash and use ARM's Cortex-M4 core.
5618 This driver uses the same command names/syntax as @xref{at91sam3}.
5620 The AT91SAM4L driver adds some additional commands:
5621 @deffn Command {at91sam4l smap_reset_deassert}
5622 This command releases internal reset held by SMAP
5623 and prepares reset vector catch in case of reset halt.
5624 Command is used internally in event event reset-deassert-post.
5629 @deffn {Flash Driver} atsame5
5631 All members of the SAM E54, E53, E51 and D51 microcontroller
5632 families from Microchip (former Atmel) include internal flash
5633 and use ARM's Cortex-M4 core.
5635 The devices have two ECC flash banks with a swapping feature.
5636 This driver handles both banks together as it were one.
5637 Bank swapping is not supported yet.
5640 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
5643 @deffn Command {atsame5 bootloader}
5644 Shows or sets the bootloader size configuration, stored in the User Page of the
5645 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5646 must be specified in bytes. The nearest bigger protection size is used.
5647 Settings are written immediately but only take effect on MCU reset.
5648 Setting the bootloader size to 0 disables bootloader protection.
5652 atsame5 bootloader 16384
5656 @deffn Command {atsame5 chip-erase}
5657 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5658 used to erase a chip back to its factory state and does not require the
5659 processor to be halted.
5662 @deffn Command {atsame5 dsu_reset_deassert}
5663 This command releases internal reset held by DSU
5664 and prepares reset vector catch in case of reset halt.
5665 Command is used internally in event event reset-deassert-post.
5668 @deffn Command {atsame5 userpage}
5669 Writes or reads the first 64 bits of NVM User Page which is located at
5670 0x804000. This field includes various fuses.
5671 Reading is done by invoking this command without any arguments.
5672 Writing is possible by giving 1 or 2 hex values. The first argument
5673 is the value to be written and the second one is an optional bit mask
5674 (a zero bit in the mask means the bit stays unchanged).
5675 The reserved fields are always masked out and cannot be changed.
5680 USER PAGE: 0xAEECFF80FE9A9239
5682 >atsame5 userpage 0xAEECFF80FE9A9239
5683 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other bits unchanged
5684 # (setup SmartEEPROM of virtual size 8192 bytes)
5685 >atsame5 userpage 0x4200000000 0x7f00000000
5691 @deffn {Flash Driver} atsamv
5693 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
5694 Atmel include internal flash and use ARM's Cortex-M7 core.
5695 This driver uses the same command names/syntax as @xref{at91sam3}.
5698 @deffn {Flash Driver} at91sam7
5699 All members of the AT91SAM7 microcontroller family from Atmel include
5700 internal flash and use ARM7TDMI cores. The driver automatically
5701 recognizes a number of these chips using the chip identification
5702 register, and autoconfigures itself.
5705 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5708 For chips which are not recognized by the controller driver, you must
5709 provide additional parameters in the following order:
5712 @item @var{chip_model} ... label used with @command{flash info}
5714 @item @var{sectors_per_bank}
5715 @item @var{pages_per_sector}
5716 @item @var{pages_size}
5717 @item @var{num_nvm_bits}
5718 @item @var{freq_khz} ... required if an external clock is provided,
5719 optional (but recommended) when the oscillator frequency is known
5722 It is recommended that you provide zeroes for all of those values
5723 except the clock frequency, so that everything except that frequency
5724 will be autoconfigured.
5725 Knowing the frequency helps ensure correct timings for flash access.
5727 The flash controller handles erases automatically on a page (128/256 byte)
5728 basis, so explicit erase commands are not necessary for flash programming.
5729 However, there is an ``EraseAll`` command that can erase an entire flash
5730 plane (of up to 256KB), and it will be used automatically when you issue
5731 @command{flash erase_sector} or @command{flash erase_address} commands.
5733 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5734 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5735 bit for the processor. Each processor has a number of such bits,
5736 used for controlling features such as brownout detection (so they
5737 are not truly general purpose).
5739 This assumes that the first flash bank (number 0) is associated with
5740 the appropriate at91sam7 target.
5745 @deffn {Flash Driver} avr
5746 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5747 @emph{The current implementation is incomplete.}
5748 @comment - defines mass_erase ... pointless given flash_erase_address
5751 @deffn {Flash Driver} bluenrg-x
5752 STMicroelectronics BlueNRG-1 and BlueNRG-2 Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0 core and internal flash memory.
5753 The driver automatically recognizes these chips using
5754 the chip identification registers, and autoconfigures itself.
5757 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
5760 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
5761 each single sector one by one.
5764 flash erase_sector 0 0 79 # It will perform a mass erase on BlueNRG-1
5768 flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2
5771 Triggering a mass erase is also useful when users want to disable readout protection.
5774 @deffn {Flash Driver} cc26xx
5775 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
5776 Instruments include internal flash. The cc26xx flash driver supports both the
5777 CC13xx and CC26xx family of devices. The driver automatically recognizes the
5778 specific version's flash parameters and autoconfigures itself. The flash bank
5779 starts at address 0.
5782 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
5786 @deffn {Flash Driver} cc3220sf
5787 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
5788 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
5789 supports the internal flash. The serial flash on SimpleLink boards is
5790 programmed via the bootloader over a UART connection. Security features of
5791 the CC3220SF may erase the internal flash during power on reset. Refer to
5792 documentation at @url{www.ti.com/cc3220sf} for details on security features
5793 and programming the serial flash.
5796 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
5800 @deffn {Flash Driver} efm32
5801 All members of the EFM32 microcontroller family from Energy Micro include
5802 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
5803 a number of these chips using the chip identification register, and
5804 autoconfigures itself.
5806 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5808 A special feature of efm32 controllers is that it is possible to completely disable the
5809 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
5810 this via the following command:
5814 The @var{num} parameter is a value shown by @command{flash banks}.
5815 Note that in order for this command to take effect, the target needs to be reset.
5816 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5820 @deffn {Flash Driver} esirisc
5821 Members of the eSi-RISC family may optionally include internal flash programmed
5822 via the eSi-TSMC Flash interface. Additional parameters are required to
5823 configure the driver: @option{cfg_address} is the base address of the
5824 configuration register interface, @option{clock_hz} is the expected clock
5825 frequency, and @option{wait_states} is the number of configured read wait states.
5828 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
5829 $_TARGETNAME cfg_address clock_hz wait_states
5832 @deffn Command {esirisc flash mass_erase} bank_id
5833 Erase all pages in data memory for the bank identified by @option{bank_id}.
5836 @deffn Command {esirisc flash ref_erase} bank_id
5837 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
5838 is an uncommon operation.}
5842 @deffn {Flash Driver} fm3
5843 All members of the FM3 microcontroller family from Fujitsu
5844 include internal flash and use ARM Cortex-M3 cores.
5845 The @var{fm3} driver uses the @var{target} parameter to select the
5846 correct bank config, it can currently be one of the following:
5847 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5848 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5851 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5855 @deffn {Flash Driver} fm4
5856 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
5857 include internal flash and use ARM Cortex-M4 cores.
5858 The @var{fm4} driver uses a @var{family} parameter to select the
5859 correct bank config, it can currently be one of the following:
5860 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
5861 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
5862 with @code{x} treated as wildcard and otherwise case (and any trailing
5863 characters) ignored.
5866 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
5867 $_TARGETNAME S6E2CCAJ0A
5868 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
5869 $_TARGETNAME S6E2CCAJ0A
5871 @emph{The current implementation is incomplete. Protection is not supported,
5872 nor is Chip Erase (only Sector Erase is implemented).}
5875 @deffn {Flash Driver} kinetis
5877 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
5878 from NXP (former Freescale) include
5879 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
5880 recognizes flash size and a number of flash banks (1-4) using the chip
5881 identification register, and autoconfigures itself.
5882 Use kinetis_ke driver for KE0x and KEAx devices.
5884 The @var{kinetis} driver defines option:
5886 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
5890 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
5893 @deffn Command {kinetis create_banks}
5894 Configuration command enables automatic creation of additional flash banks
5895 based on real flash layout of device. Banks are created during device probe.
5896 Use 'flash probe 0' to force probe.
5899 @deffn Command {kinetis fcf_source} [protection|write]
5900 Select what source is used when writing to a Flash Configuration Field.
5901 @option{protection} mode builds FCF content from protection bits previously
5902 set by 'flash protect' command.
5903 This mode is default. MCU is protected from unwanted locking by immediate
5904 writing FCF after erase of relevant sector.
5905 @option{write} mode enables direct write to FCF.
5906 Protection cannot be set by 'flash protect' command. FCF is written along
5907 with the rest of a flash image.
5908 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
5911 @deffn Command {kinetis fopt} [num]
5912 Set value to write to FOPT byte of Flash Configuration Field.
5913 Used in kinetis 'fcf_source protection' mode only.
5916 @deffn Command {kinetis mdm check_security}
5917 Checks status of device security lock. Used internally in examine-end event.
5920 @deffn Command {kinetis mdm halt}
5921 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
5922 loop when connecting to an unsecured target.
5925 @deffn Command {kinetis mdm mass_erase}
5926 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
5927 back to its factory state, removing security. It does not require the processor
5928 to be halted, however the target will remain in a halted state after this
5932 @deffn Command {kinetis nvm_partition}
5933 For FlexNVM devices only (KxxDX and KxxFX).
5934 Command shows or sets data flash or EEPROM backup size in kilobytes,
5935 sets two EEPROM blocks sizes in bytes and enables/disables loading
5936 of EEPROM contents to FlexRAM during reset.
5938 For details see device reference manual, Flash Memory Module,
5939 Program Partition command.
5941 Setting is possible only once after mass_erase.
5942 Reset the device after partition setting.
5944 Show partition size:
5946 kinetis nvm_partition info
5949 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
5950 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
5952 kinetis nvm_partition dataflash 32 512 1536 on
5955 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
5956 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
5958 kinetis nvm_partition eebkp 16 1024 1024 off
5962 @deffn Command {kinetis mdm reset}
5963 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
5964 RESET pin, which can be used to reset other hardware on board.
5967 @deffn Command {kinetis disable_wdog}
5968 For Kx devices only (KLx has different COP watchdog, it is not supported).
5969 Command disables watchdog timer.
5973 @deffn {Flash Driver} kinetis_ke
5975 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
5976 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
5977 the KE0x sub-family using the chip identification register, and
5978 autoconfigures itself.
5979 Use kinetis (not kinetis_ke) driver for KE1x devices.
5982 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
5985 @deffn Command {kinetis_ke mdm check_security}
5986 Checks status of device security lock. Used internally in examine-end event.
5989 @deffn Command {kinetis_ke mdm mass_erase}
5990 Issues a complete Flash erase via the MDM-AP.
5991 This can be used to erase a chip back to its factory state.
5992 Command removes security lock from a device (use of SRST highly recommended).
5993 It does not require the processor to be halted.
5996 @deffn Command {kinetis_ke disable_wdog}
5997 Command disables watchdog timer.
6001 @deffn {Flash Driver} lpc2000
6002 This is the driver to support internal flash of all members of the
6003 LPC11(x)00 and LPC1300 microcontroller families and most members of
6004 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6005 LPC8Nxx and NHS31xx microcontroller families from NXP.
6008 There are LPC2000 devices which are not supported by the @var{lpc2000}
6010 The LPC2888 is supported by the @var{lpc288x} driver.
6011 The LPC29xx family is supported by the @var{lpc2900} driver.
6014 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6015 which must appear in the following order:
6018 @item @var{variant} ... required, may be
6019 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6020 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6021 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6022 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6024 @option{lpc800} (LPC8xx)
6025 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6026 @option{lpc1500} (LPC15xx)
6027 @option{lpc54100} (LPC541xx)
6028 @option{lpc4000} (LPC40xx)
6029 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6030 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6031 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6032 at which the core is running
6033 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6034 telling the driver to calculate a valid checksum for the exception vector table.
6036 If you don't provide @option{calc_checksum} when you're writing the vector
6037 table, the boot ROM will almost certainly ignore your flash image.
6038 However, if you do provide it,
6039 with most tool chains @command{verify_image} will fail.
6041 @item @option{iap_entry} ... optional telling the driver to use a different
6042 ROM IAP entry point.
6045 LPC flashes don't require the chip and bus width to be specified.
6048 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6049 lpc2000_v2 14765 calc_checksum
6052 @deffn {Command} {lpc2000 part_id} bank
6053 Displays the four byte part identifier associated with
6054 the specified flash @var{bank}.
6058 @deffn {Flash Driver} lpc288x
6059 The LPC2888 microcontroller from NXP needs slightly different flash
6060 support from its lpc2000 siblings.
6061 The @var{lpc288x} driver defines one mandatory parameter,
6062 the programming clock rate in Hz.
6063 LPC flashes don't require the chip and bus width to be specified.
6066 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6070 @deffn {Flash Driver} lpc2900
6071 This driver supports the LPC29xx ARM968E based microcontroller family
6074 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6075 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6076 sector layout are auto-configured by the driver.
6077 The driver has one additional mandatory parameter: The CPU clock rate
6078 (in kHz) at the time the flash operations will take place. Most of the time this
6079 will not be the crystal frequency, but a higher PLL frequency. The
6080 @code{reset-init} event handler in the board script is usually the place where
6083 The driver rejects flashless devices (currently the LPC2930).
6085 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6086 It must be handled much more like NAND flash memory, and will therefore be
6087 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6089 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6090 sector needs to be erased or programmed, it is automatically unprotected.
6091 What is shown as protection status in the @code{flash info} command, is
6092 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6093 sector from ever being erased or programmed again. As this is an irreversible
6094 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6095 and not by the standard @code{flash protect} command.
6097 Example for a 125 MHz clock frequency:
6099 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6102 Some @code{lpc2900}-specific commands are defined. In the following command list,
6103 the @var{bank} parameter is the bank number as obtained by the
6104 @code{flash banks} command.
6106 @deffn Command {lpc2900 signature} bank
6107 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6108 content. This is a hardware feature of the flash block, hence the calculation is
6109 very fast. You may use this to verify the content of a programmed device against
6114 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6118 @deffn Command {lpc2900 read_custom} bank filename
6119 Reads the 912 bytes of customer information from the flash index sector, and
6120 saves it to a file in binary format.
6123 lpc2900 read_custom 0 /path_to/customer_info.bin
6127 The index sector of the flash is a @emph{write-only} sector. It cannot be
6128 erased! In order to guard against unintentional write access, all following
6129 commands need to be preceded by a successful call to the @code{password}
6132 @deffn Command {lpc2900 password} bank password
6133 You need to use this command right before each of the following commands:
6134 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6135 @code{lpc2900 secure_jtag}.
6137 The password string is fixed to "I_know_what_I_am_doing".
6140 lpc2900 password 0 I_know_what_I_am_doing
6141 Potentially dangerous operation allowed in next command!
6145 @deffn Command {lpc2900 write_custom} bank filename type
6146 Writes the content of the file into the customer info space of the flash index
6147 sector. The filetype can be specified with the @var{type} field. Possible values
6148 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6149 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6150 contain a single section, and the contained data length must be exactly
6152 @quotation Attention
6153 This cannot be reverted! Be careful!
6157 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6161 @deffn Command {lpc2900 secure_sector} bank first last
6162 Secures the sector range from @var{first} to @var{last} (including) against
6163 further program and erase operations. The sector security will be effective
6164 after the next power cycle.
6165 @quotation Attention
6166 This cannot be reverted! Be careful!
6168 Secured sectors appear as @emph{protected} in the @code{flash info} command.
6171 lpc2900 secure_sector 0 1 1
6173 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
6174 # 0: 0x00000000 (0x2000 8kB) not protected
6175 # 1: 0x00002000 (0x2000 8kB) protected
6176 # 2: 0x00004000 (0x2000 8kB) not protected
6180 @deffn Command {lpc2900 secure_jtag} bank
6181 Irreversibly disable the JTAG port. The new JTAG security setting will be
6182 effective after the next power cycle.
6183 @quotation Attention
6184 This cannot be reverted! Be careful!
6188 lpc2900 secure_jtag 0
6193 @deffn {Flash Driver} mdr
6194 This drivers handles the integrated NOR flash on Milandr Cortex-M
6195 based controllers. A known limitation is that the Info memory can't be
6196 read or verified as it's not memory mapped.
6199 flash bank <name> mdr <base> <size> \
6200 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
6204 @item @var{type} - 0 for main memory, 1 for info memory
6205 @item @var{page_count} - total number of pages
6206 @item @var{sec_count} - number of sector per page count
6211 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
6212 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
6213 0 0 $_TARGETNAME 1 1 4
6215 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
6216 0 0 $_TARGETNAME 0 32 4
6221 @deffn {Flash Driver} msp432
6222 All versions of the SimpleLink MSP432 microcontrollers from Texas
6223 Instruments include internal flash. The msp432 flash driver automatically
6224 recognizes the specific version's flash parameters and autoconfigures itself.
6225 Main program flash (starting at address 0) is flash bank 0. Information flash
6226 region on MSP432P4 versions (starting at address 0x200000) is flash bank 1.
6229 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
6232 @deffn Command {msp432 mass_erase} [main|all]
6233 Performs a complete erase of flash. By default, @command{mass_erase} will erase
6234 only the main program flash.
6236 On MSP432P4 versions, using @command{mass_erase all} will erase both the
6237 main program and information flash regions. To also erase the BSL in information
6238 flash, the user must first use the @command{bsl} command.
6241 @deffn Command {msp432 bsl} [unlock|lock]
6242 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
6243 region in information flash so that flash commands can erase or write the BSL.
6244 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
6246 To erase and program the BSL:
6249 flash erase_address 0x202000 0x2000
6250 flash write_image bsl.bin 0x202000
6256 @deffn {Flash Driver} niietcm4
6257 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6258 based controllers. Flash size and sector layout are auto-configured by the driver.
6259 Main flash memory is called "Bootflash" and has main region and info region.
6260 Info region is NOT memory mapped by default,
6261 but it can replace first part of main region if needed.
6262 Full erase, single and block writes are supported for both main and info regions.
6263 There is additional not memory mapped flash called "Userflash", which
6264 also have division into regions: main and info.
6265 Purpose of userflash - to store system and user settings.
6266 Driver has special commands to perform operations with this memory.
6269 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6272 Some niietcm4-specific commands are defined:
6274 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
6275 Read byte from main or info userflash region.
6278 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6279 Write byte to main or info userflash region.
6282 @deffn Command {niietcm4 uflash_full_erase} bank
6283 Erase all userflash including info region.
6286 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6287 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6290 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
6291 Check sectors protect.
6294 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6295 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6298 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
6299 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6302 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6303 Configure external memory interface for boot.
6306 @deffn Command {niietcm4 service_mode_erase} bank
6307 Perform emergency erase of all flash (bootflash and userflash).
6310 @deffn Command {niietcm4 driver_info} bank
6311 Show information about flash driver.
6316 @deffn {Flash Driver} nrf5
6317 All members of the nRF51 microcontroller families from Nordic Semiconductor
6318 include internal flash and use ARM Cortex-M0 core.
6319 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
6320 internal flash and use an ARM Cortex-M4F core.
6323 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6326 Some nrf5-specific commands are defined:
6328 @deffn Command {nrf5 mass_erase}
6329 Erases the contents of the code memory and user information
6330 configuration registers as well. It must be noted that this command
6331 works only for chips that do not have factory pre-programmed region 0
6337 @deffn {Flash Driver} ocl
6338 This driver is an implementation of the ``on chip flash loader''
6339 protocol proposed by Pavel Chromy.
6341 It is a minimalistic command-response protocol intended to be used
6342 over a DCC when communicating with an internal or external flash
6343 loader running from RAM. An example implementation for AT91SAM7x is
6344 available in @file{contrib/loaders/flash/at91sam7x/}.
6347 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
6351 @deffn {Flash Driver} pic32mx
6352 The PIC32MX microcontrollers are based on the MIPS 4K cores,
6353 and integrate flash memory.
6356 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
6357 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
6360 @comment numerous *disabled* commands are defined:
6361 @comment - chip_erase ... pointless given flash_erase_address
6362 @comment - lock, unlock ... pointless given protect on/off (yes?)
6363 @comment - pgm_word ... shouldn't bank be deduced from address??
6364 Some pic32mx-specific commands are defined:
6365 @deffn Command {pic32mx pgm_word} address value bank
6366 Programs the specified 32-bit @var{value} at the given @var{address}
6367 in the specified chip @var{bank}.
6369 @deffn Command {pic32mx unlock} bank
6370 Unlock and erase specified chip @var{bank}.
6371 This will remove any Code Protection.
6375 @deffn {Flash Driver} psoc4
6376 All members of the PSoC 41xx/42xx microcontroller family from Cypress
6377 include internal flash and use ARM Cortex-M0 cores.
6378 The driver automatically recognizes a number of these chips using
6379 the chip identification register, and autoconfigures itself.
6381 Note: Erased internal flash reads as 00.
6382 System ROM of PSoC 4 does not implement erase of a flash sector.
6385 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
6388 psoc4-specific commands
6389 @deffn Command {psoc4 flash_autoerase} num (on|off)
6390 Enables or disables autoerase mode for a flash bank.
6392 If flash_autoerase is off, use mass_erase before flash programming.
6393 Flash erase command fails if region to erase is not whole flash memory.
6395 If flash_autoerase is on, a sector is both erased and programmed in one
6396 system ROM call. Flash erase command is ignored.
6397 This mode is suitable for gdb load.
6399 The @var{num} parameter is a value shown by @command{flash banks}.
6402 @deffn Command {psoc4 mass_erase} num
6403 Erases the contents of the flash memory, protection and security lock.
6405 The @var{num} parameter is a value shown by @command{flash banks}.
6409 @deffn {Flash Driver} psoc5lp
6410 All members of the PSoC 5LP microcontroller family from Cypress
6411 include internal program flash and use ARM Cortex-M3 cores.
6412 The driver probes for a number of these chips and autoconfigures itself,
6413 apart from the base address.
6416 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
6419 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
6420 @quotation Attention
6421 If flash operations are performed in ECC-disabled mode, they will also affect
6422 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
6423 then also erase the corresponding 2k data bytes in the 0x48000000 area.
6424 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
6427 Commands defined in the @var{psoc5lp} driver:
6429 @deffn Command {psoc5lp mass_erase}
6430 Erases all flash data and ECC/configuration bytes, all flash protection rows,
6431 and all row latches in all flash arrays on the device.
6435 @deffn {Flash Driver} psoc5lp_eeprom
6436 All members of the PSoC 5LP microcontroller family from Cypress
6437 include internal EEPROM and use ARM Cortex-M3 cores.
6438 The driver probes for a number of these chips and autoconfigures itself,
6439 apart from the base address.
6442 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
6446 @deffn {Flash Driver} psoc5lp_nvl
6447 All members of the PSoC 5LP microcontroller family from Cypress
6448 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
6449 The driver probes for a number of these chips and autoconfigures itself.
6452 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
6455 PSoC 5LP chips have multiple NV Latches:
6458 @item Device Configuration NV Latch - 4 bytes
6459 @item Write Once (WO) NV Latch - 4 bytes
6462 @b{Note:} This driver only implements the Device Configuration NVL.
6464 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
6465 @quotation Attention
6466 Switching ECC mode via write to Device Configuration NVL will require a reset
6467 after successful write.
6471 @deffn {Flash Driver} psoc6
6472 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
6473 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
6474 the same Flash/RAM/MMIO address space.
6476 Flash in PSoC6 is split into three regions:
6478 @item Main Flash - this is the main storage for user application.
6479 Total size varies among devices, sector size: 256 kBytes, row size:
6480 512 bytes. Supports erase operation on individual rows.
6481 @item Work Flash - intended to be used as storage for user data
6482 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
6483 row size: 512 bytes.
6484 @item Supervisory Flash - special region which contains device-specific
6485 service data. This region does not support erase operation. Only few rows can
6486 be programmed by the user, most of the rows are read only. Programming
6487 operation will erase row automatically.
6490 All three flash regions are supported by the driver. Flash geometry is detected
6491 automatically by parsing data in SPCIF_GEOMETRY register.
6493 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
6496 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm0
6497 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm0
6498 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm0
6499 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm0
6500 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm0
6501 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm0
6503 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm4
6504 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm4
6505 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm4
6506 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm4
6507 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm4
6508 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm4
6511 psoc6-specific commands
6512 @deffn Command {psoc6 reset_halt}
6513 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
6514 When invoked for CM0+ target, it will set break point at application entry point
6515 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
6516 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
6517 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
6520 @deffn Command {psoc6 mass_erase} num
6521 Erases the contents given flash bank. The @var{num} parameter is a value shown
6522 by @command{flash banks}.
6523 Note: only Main and Work flash regions support Erase operation.
6527 @deffn {Flash Driver} sim3x
6528 All members of the SiM3 microcontroller family from Silicon Laboratories
6529 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
6531 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
6532 If this fails, it will use the @var{size} parameter as the size of flash bank.
6535 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
6538 There are 2 commands defined in the @var{sim3x} driver:
6540 @deffn Command {sim3x mass_erase}
6541 Erases the complete flash. This is used to unlock the flash.
6542 And this command is only possible when using the SWD interface.
6545 @deffn Command {sim3x lock}
6546 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
6550 @deffn {Flash Driver} stellaris
6551 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
6552 families from Texas Instruments include internal flash. The driver
6553 automatically recognizes a number of these chips using the chip
6554 identification register, and autoconfigures itself.
6557 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
6560 @deffn Command {stellaris recover}
6561 Performs the @emph{Recovering a "Locked" Device} procedure to restore
6562 the flash and its associated nonvolatile registers to their factory
6563 default values (erased). This is the only way to remove flash
6564 protection or re-enable debugging if that capability has been
6567 Note that the final "power cycle the chip" step in this procedure
6568 must be performed by hand, since OpenOCD can't do it.
6570 if more than one Stellaris chip is connected, the procedure is
6571 applied to all of them.
6576 @deffn {Flash Driver} stm32f1x
6577 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
6578 from STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
6579 The driver automatically recognizes a number of these chips using
6580 the chip identification register, and autoconfigures itself.
6583 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
6586 Note that some devices have been found that have a flash size register that contains
6587 an invalid value, to workaround this issue you can override the probed value used by
6591 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
6594 If you have a target with dual flash banks then define the second bank
6595 as per the following example.
6597 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
6600 Some stm32f1x-specific commands are defined:
6602 @deffn Command {stm32f1x lock} num
6603 Locks the entire stm32 device against reading.
6604 The @var{num} parameter is a value shown by @command{flash banks}.
6607 @deffn Command {stm32f1x unlock} num
6608 Unlocks the entire stm32 device for reading. This command will cause
6609 a mass erase of the entire stm32 device if previously locked.
6610 The @var{num} parameter is a value shown by @command{flash banks}.
6613 @deffn Command {stm32f1x mass_erase} num
6614 Mass erases the entire stm32 device.
6615 The @var{num} parameter is a value shown by @command{flash banks}.
6618 @deffn Command {stm32f1x options_read} num
6619 Reads and displays active stm32 option bytes loaded during POR
6620 or upon executing the @command{stm32f1x options_load} command.
6621 The @var{num} parameter is a value shown by @command{flash banks}.
6624 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
6625 Writes the stm32 option byte with the specified values.
6626 The @var{num} parameter is a value shown by @command{flash banks}.
6627 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
6630 @deffn Command {stm32f1x options_load} num
6631 Generates a special kind of reset to re-load the stm32 option bytes written
6632 by the @command{stm32f1x options_write} or @command{flash protect} commands
6633 without having to power cycle the target. Not applicable to stm32f1x devices.
6634 The @var{num} parameter is a value shown by @command{flash banks}.
6638 @deffn {Flash Driver} stm32f2x
6639 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
6640 include internal flash and use ARM Cortex-M3/M4/M7 cores.
6641 The driver automatically recognizes a number of these chips using
6642 the chip identification register, and autoconfigures itself.
6645 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
6648 If you use OTP (One-Time Programmable) memory define it as a second bank
6649 as per the following example.
6651 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
6654 @deffn Command {stm32f2x otp } num (@option{enable}|@option{disable}|@option{show})
6655 Enables or disables OTP write commands for bank @var{num}.
6656 The @var{num} parameter is a value shown by @command{flash banks}.
6659 Note that some devices have been found that have a flash size register that contains
6660 an invalid value, to workaround this issue you can override the probed value used by
6664 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
6667 Some stm32f2x-specific commands are defined:
6669 @deffn Command {stm32f2x lock} num
6670 Locks the entire stm32 device.
6671 The @var{num} parameter is a value shown by @command{flash banks}.
6674 @deffn Command {stm32f2x unlock} num
6675 Unlocks the entire stm32 device.
6676 The @var{num} parameter is a value shown by @command{flash banks}.
6679 @deffn Command {stm32f2x mass_erase} num
6680 Mass erases the entire stm32f2x device.
6681 The @var{num} parameter is a value shown by @command{flash banks}.
6684 @deffn Command {stm32f2x options_read} num
6685 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
6686 The @var{num} parameter is a value shown by @command{flash banks}.
6689 @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
6690 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
6691 Warning: The meaning of the various bits depends on the device, always check datasheet!
6692 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
6693 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
6694 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
6697 @deffn Command {stm32f2x optcr2_write} num optcr2
6698 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
6699 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
6703 @deffn {Flash Driver} stm32h7x
6704 All members of the STM32H7 microcontroller families from STMicroelectronics
6705 include internal flash and use ARM Cortex-M7 core.
6706 The driver automatically recognizes a number of these chips using
6707 the chip identification register, and autoconfigures itself.
6710 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
6713 Note that some devices have been found that have a flash size register that contains
6714 an invalid value, to workaround this issue you can override the probed value used by
6718 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
6721 Some stm32h7x-specific commands are defined:
6723 @deffn Command {stm32h7x lock} num
6724 Locks the entire stm32 device.
6725 The @var{num} parameter is a value shown by @command{flash banks}.
6728 @deffn Command {stm32h7x unlock} num
6729 Unlocks the entire stm32 device.
6730 The @var{num} parameter is a value shown by @command{flash banks}.
6733 @deffn Command {stm32h7x mass_erase} num
6734 Mass erases the entire stm32h7x device.
6735 The @var{num} parameter is a value shown by @command{flash banks}.
6739 @deffn {Flash Driver} stm32lx
6740 All members of the STM32L microcontroller families from STMicroelectronics
6741 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
6742 The driver automatically recognizes a number of these chips using
6743 the chip identification register, and autoconfigures itself.
6746 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
6749 Note that some devices have been found that have a flash size register that contains
6750 an invalid value, to workaround this issue you can override the probed value used by
6751 the flash driver. If you use 0 as the bank base address, it tells the
6752 driver to autodetect the bank location assuming you're configuring the
6756 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
6759 Some stm32lx-specific commands are defined:
6761 @deffn Command {stm32lx lock} num
6762 Locks the entire stm32 device.
6763 The @var{num} parameter is a value shown by @command{flash banks}.
6766 @deffn Command {stm32lx unlock} num
6767 Unlocks the entire stm32 device.
6768 The @var{num} parameter is a value shown by @command{flash banks}.
6771 @deffn Command {stm32lx mass_erase} num
6772 Mass erases the entire stm32lx device (all flash banks and EEPROM
6773 data). This is the only way to unlock a protected flash (unless RDP
6774 Level is 2 which can't be unlocked at all).
6775 The @var{num} parameter is a value shown by @command{flash banks}.
6779 @deffn {Flash Driver} stm32l4x
6780 All members of the STM32L4 microcontroller families from STMicroelectronics
6781 include internal flash and use ARM Cortex-M4 cores.
6782 The driver automatically recognizes a number of these chips using
6783 the chip identification register, and autoconfigures itself.
6786 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
6789 Note that some devices have been found that have a flash size register that contains
6790 an invalid value, to workaround this issue you can override the probed value used by
6794 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
6797 Some stm32l4x-specific commands are defined:
6799 @deffn Command {stm32l4x lock} num
6800 Locks the entire stm32 device.
6801 The @var{num} parameter is a value shown by @command{flash banks}.
6804 @deffn Command {stm32l4x unlock} num
6805 Unlocks the entire stm32 device.
6806 The @var{num} parameter is a value shown by @command{flash banks}.
6809 @deffn Command {stm32l4x mass_erase} num
6810 Mass erases the entire stm32l4x device.
6811 The @var{num} parameter is a value shown by @command{flash banks}.
6814 @deffn Command {stm32l4x option_read} num reg_offset
6815 Reads an option byte register from the stm32l4x device.
6816 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6817 is the register offset of the Option byte to read.
6819 For example to read the FLASH_OPTR register:
6821 stm32l4x option_read 0 0x20
6822 # Option Register: <0x40022020> = 0xffeff8aa
6825 The above example will read out the FLASH_OPTR register which contains the RDP
6826 option byte, Watchdog configuration, BOR level etc.
6829 @deffn Command {stm32l4x option_write} num reg_offset reg_mask
6830 Write an option byte register of the stm32l4x device.
6831 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6832 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
6833 to apply when writing the register (only bits with a '1' will be touched).
6835 For example to write the WRP1AR option bytes:
6837 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
6840 The above example will write the WRP1AR option register configuring the Write protection
6841 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
6842 This will effectively write protect all sectors in flash bank 1.
6845 @deffn Command {stm32l4x option_load} num
6846 Forces a re-load of the option byte registers. Will cause a reset of the device.
6847 The @var{num} parameter is a value shown by @command{flash banks}.
6851 @deffn {Flash Driver} str7x
6852 All members of the STR7 microcontroller family from STMicroelectronics
6853 include internal flash and use ARM7TDMI cores.
6854 The @var{str7x} driver defines one mandatory parameter, @var{variant},
6855 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
6858 flash bank $_FLASHNAME str7x \
6859 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
6862 @deffn Command {str7x disable_jtag} bank
6863 Activate the Debug/Readout protection mechanism
6864 for the specified flash bank.
6868 @deffn {Flash Driver} str9x
6869 Most members of the STR9 microcontroller family from STMicroelectronics
6870 include internal flash and use ARM966E cores.
6871 The str9 needs the flash controller to be configured using
6872 the @command{str9x flash_config} command prior to Flash programming.
6875 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
6876 str9x flash_config 0 4 2 0 0x80000
6879 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
6880 Configures the str9 flash controller.
6881 The @var{num} parameter is a value shown by @command{flash banks}.
6884 @item @var{bbsr} - Boot Bank Size register
6885 @item @var{nbbsr} - Non Boot Bank Size register
6886 @item @var{bbadr} - Boot Bank Start Address register
6887 @item @var{nbbadr} - Boot Bank Start Address register
6893 @deffn {Flash Driver} str9xpec
6896 Only use this driver for locking/unlocking the device or configuring the option bytes.
6897 Use the standard str9 driver for programming.
6898 Before using the flash commands the turbo mode must be enabled using the
6899 @command{str9xpec enable_turbo} command.
6901 Here is some background info to help
6902 you better understand how this driver works. OpenOCD has two flash drivers for
6906 Standard driver @option{str9x} programmed via the str9 core. Normally used for
6907 flash programming as it is faster than the @option{str9xpec} driver.
6909 Direct programming @option{str9xpec} using the flash controller. This is an
6910 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
6911 core does not need to be running to program using this flash driver. Typical use
6912 for this driver is locking/unlocking the target and programming the option bytes.
6915 Before we run any commands using the @option{str9xpec} driver we must first disable
6916 the str9 core. This example assumes the @option{str9xpec} driver has been
6917 configured for flash bank 0.
6919 # assert srst, we do not want core running
6920 # while accessing str9xpec flash driver
6922 # turn off target polling
6925 str9xpec enable_turbo 0
6927 str9xpec options_read 0
6928 # re-enable str9 core
6929 str9xpec disable_turbo 0
6933 The above example will read the str9 option bytes.
6934 When performing a unlock remember that you will not be able to halt the str9 - it
6935 has been locked. Halting the core is not required for the @option{str9xpec} driver
6936 as mentioned above, just issue the commands above manually or from a telnet prompt.
6938 Several str9xpec-specific commands are defined:
6940 @deffn Command {str9xpec disable_turbo} num
6941 Restore the str9 into JTAG chain.
6944 @deffn Command {str9xpec enable_turbo} num
6945 Enable turbo mode, will simply remove the str9 from the chain and talk
6946 directly to the embedded flash controller.
6949 @deffn Command {str9xpec lock} num
6950 Lock str9 device. The str9 will only respond to an unlock command that will
6954 @deffn Command {str9xpec part_id} num
6955 Prints the part identifier for bank @var{num}.
6958 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
6959 Configure str9 boot bank.
6962 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
6963 Configure str9 lvd source.
6966 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
6967 Configure str9 lvd threshold.
6970 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
6971 Configure str9 lvd reset warning source.
6974 @deffn Command {str9xpec options_read} num
6975 Read str9 option bytes.
6978 @deffn Command {str9xpec options_write} num
6979 Write str9 option bytes.
6982 @deffn Command {str9xpec unlock} num
6988 @deffn {Flash Driver} tms470
6989 Most members of the TMS470 microcontroller family from Texas Instruments
6990 include internal flash and use ARM7TDMI cores.
6991 This driver doesn't require the chip and bus width to be specified.
6993 Some tms470-specific commands are defined:
6995 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
6996 Saves programming keys in a register, to enable flash erase and write commands.
6999 @deffn Command {tms470 osc_mhz} clock_mhz
7000 Reports the clock speed, which is used to calculate timings.
7003 @deffn Command {tms470 plldis} (0|1)
7004 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
7009 @deffn {Flash Driver} w600
7010 W60x series Wi-Fi SoC from WinnerMicro
7011 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
7012 The @var{w600} driver uses the @var{target} parameter to select the
7013 correct bank config.
7016 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
7020 @deffn {Flash Driver} xmc1xxx
7021 All members of the XMC1xxx microcontroller family from Infineon.
7022 This driver does not require the chip and bus width to be specified.
7025 @deffn {Flash Driver} xmc4xxx
7026 All members of the XMC4xxx microcontroller family from Infineon.
7027 This driver does not require the chip and bus width to be specified.
7029 Some xmc4xxx-specific commands are defined:
7031 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
7032 Saves flash protection passwords which are used to lock the user flash
7035 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
7036 Removes Flash write protection from the selected user bank
7041 @section NAND Flash Commands
7044 Compared to NOR or SPI flash, NAND devices are inexpensive
7045 and high density. Today's NAND chips, and multi-chip modules,
7046 commonly hold multiple GigaBytes of data.
7048 NAND chips consist of a number of ``erase blocks'' of a given
7049 size (such as 128 KBytes), each of which is divided into a
7050 number of pages (of perhaps 512 or 2048 bytes each). Each
7051 page of a NAND flash has an ``out of band'' (OOB) area to hold
7052 Error Correcting Code (ECC) and other metadata, usually 16 bytes
7053 of OOB for every 512 bytes of page data.
7055 One key characteristic of NAND flash is that its error rate
7056 is higher than that of NOR flash. In normal operation, that
7057 ECC is used to correct and detect errors. However, NAND
7058 blocks can also wear out and become unusable; those blocks
7059 are then marked "bad". NAND chips are even shipped from the
7060 manufacturer with a few bad blocks. The highest density chips
7061 use a technology (MLC) that wears out more quickly, so ECC
7062 support is increasingly important as a way to detect blocks
7063 that have begun to fail, and help to preserve data integrity
7064 with techniques such as wear leveling.
7066 Software is used to manage the ECC. Some controllers don't
7067 support ECC directly; in those cases, software ECC is used.
7068 Other controllers speed up the ECC calculations with hardware.
7069 Single-bit error correction hardware is routine. Controllers
7070 geared for newer MLC chips may correct 4 or more errors for
7071 every 512 bytes of data.
7073 You will need to make sure that any data you write using
7074 OpenOCD includes the appropriate kind of ECC. For example,
7075 that may mean passing the @code{oob_softecc} flag when
7076 writing NAND data, or ensuring that the correct hardware
7079 The basic steps for using NAND devices include:
7081 @item Declare via the command @command{nand device}
7082 @* Do this in a board-specific configuration file,
7083 passing parameters as needed by the controller.
7084 @item Configure each device using @command{nand probe}.
7085 @* Do this only after the associated target is set up,
7086 such as in its reset-init script or in procures defined
7087 to access that device.
7088 @item Operate on the flash via @command{nand subcommand}
7089 @* Often commands to manipulate the flash are typed by a human, or run
7090 via a script in some automated way. Common task include writing a
7091 boot loader, operating system, or other data needed to initialize or
7095 @b{NOTE:} At the time this text was written, the largest NAND
7096 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
7097 This is because the variables used to hold offsets and lengths
7098 are only 32 bits wide.
7099 (Larger chips may work in some cases, unless an offset or length
7100 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
7101 Some larger devices will work, since they are actually multi-chip
7102 modules with two smaller chips and individual chipselect lines.
7104 @anchor{nandconfiguration}
7105 @subsection NAND Configuration Commands
7106 @cindex NAND configuration
7108 NAND chips must be declared in configuration scripts,
7109 plus some additional configuration that's done after
7110 OpenOCD has initialized.
7112 @deffn {Config Command} {nand device} name driver target [configparams...]
7113 Declares a NAND device, which can be read and written to
7114 after it has been configured through @command{nand probe}.
7115 In OpenOCD, devices are single chips; this is unlike some
7116 operating systems, which may manage multiple chips as if
7117 they were a single (larger) device.
7118 In some cases, configuring a device will activate extra
7119 commands; see the controller-specific documentation.
7121 @b{NOTE:} This command is not available after OpenOCD
7122 initialization has completed. Use it in board specific
7123 configuration files, not interactively.
7126 @item @var{name} ... may be used to reference the NAND bank
7127 in most other NAND commands. A number is also available.
7128 @item @var{driver} ... identifies the NAND controller driver
7129 associated with the NAND device being declared.
7130 @xref{nanddriverlist,,NAND Driver List}.
7131 @item @var{target} ... names the target used when issuing
7132 commands to the NAND controller.
7133 @comment Actually, it's currently a controller-specific parameter...
7134 @item @var{configparams} ... controllers may support, or require,
7135 additional parameters. See the controller-specific documentation
7136 for more information.
7140 @deffn Command {nand list}
7141 Prints a summary of each device declared
7142 using @command{nand device}, numbered from zero.
7143 Note that un-probed devices show no details.
7146 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7147 blocksize: 131072, blocks: 8192
7148 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7149 blocksize: 131072, blocks: 8192
7154 @deffn Command {nand probe} num
7155 Probes the specified device to determine key characteristics
7156 like its page and block sizes, and how many blocks it has.
7157 The @var{num} parameter is the value shown by @command{nand list}.
7158 You must (successfully) probe a device before you can use
7159 it with most other NAND commands.
7162 @subsection Erasing, Reading, Writing to NAND Flash
7164 @deffn Command {nand dump} num filename offset length [oob_option]
7165 @cindex NAND reading
7166 Reads binary data from the NAND device and writes it to the file,
7167 starting at the specified offset.
7168 The @var{num} parameter is the value shown by @command{nand list}.
7170 Use a complete path name for @var{filename}, so you don't depend
7171 on the directory used to start the OpenOCD server.
7173 The @var{offset} and @var{length} must be exact multiples of the
7174 device's page size. They describe a data region; the OOB data
7175 associated with each such page may also be accessed.
7177 @b{NOTE:} At the time this text was written, no error correction
7178 was done on the data that's read, unless raw access was disabled
7179 and the underlying NAND controller driver had a @code{read_page}
7180 method which handled that error correction.
7182 By default, only page data is saved to the specified file.
7183 Use an @var{oob_option} parameter to save OOB data:
7185 @item no oob_* parameter
7186 @*Output file holds only page data; OOB is discarded.
7187 @item @code{oob_raw}
7188 @*Output file interleaves page data and OOB data;
7189 the file will be longer than "length" by the size of the
7190 spare areas associated with each data page.
7191 Note that this kind of "raw" access is different from
7192 what's implied by @command{nand raw_access}, which just
7193 controls whether a hardware-aware access method is used.
7194 @item @code{oob_only}
7195 @*Output file has only raw OOB data, and will
7196 be smaller than "length" since it will contain only the
7197 spare areas associated with each data page.
7201 @deffn Command {nand erase} num [offset length]
7202 @cindex NAND erasing
7203 @cindex NAND programming
7204 Erases blocks on the specified NAND device, starting at the
7205 specified @var{offset} and continuing for @var{length} bytes.
7206 Both of those values must be exact multiples of the device's
7207 block size, and the region they specify must fit entirely in the chip.
7208 If those parameters are not specified,
7209 the whole NAND chip will be erased.
7210 The @var{num} parameter is the value shown by @command{nand list}.
7212 @b{NOTE:} This command will try to erase bad blocks, when told
7213 to do so, which will probably invalidate the manufacturer's bad
7215 For the remainder of the current server session, @command{nand info}
7216 will still report that the block ``is'' bad.
7219 @deffn Command {nand write} num filename offset [option...]
7220 @cindex NAND writing
7221 @cindex NAND programming
7222 Writes binary data from the file into the specified NAND device,
7223 starting at the specified offset. Those pages should already
7224 have been erased; you can't change zero bits to one bits.
7225 The @var{num} parameter is the value shown by @command{nand list}.
7227 Use a complete path name for @var{filename}, so you don't depend
7228 on the directory used to start the OpenOCD server.
7230 The @var{offset} must be an exact multiple of the device's page size.
7231 All data in the file will be written, assuming it doesn't run
7232 past the end of the device.
7233 Only full pages are written, and any extra space in the last
7234 page will be filled with 0xff bytes. (That includes OOB data,
7235 if that's being written.)
7237 @b{NOTE:} At the time this text was written, bad blocks are
7238 ignored. That is, this routine will not skip bad blocks,
7239 but will instead try to write them. This can cause problems.
7241 Provide at most one @var{option} parameter. With some
7242 NAND drivers, the meanings of these parameters may change
7243 if @command{nand raw_access} was used to disable hardware ECC.
7245 @item no oob_* parameter
7246 @*File has only page data, which is written.
7247 If raw access is in use, the OOB area will not be written.
7248 Otherwise, if the underlying NAND controller driver has
7249 a @code{write_page} routine, that routine may write the OOB
7250 with hardware-computed ECC data.
7251 @item @code{oob_only}
7252 @*File has only raw OOB data, which is written to the OOB area.
7253 Each page's data area stays untouched. @i{This can be a dangerous
7254 option}, since it can invalidate the ECC data.
7255 You may need to force raw access to use this mode.
7256 @item @code{oob_raw}
7257 @*File interleaves data and OOB data, both of which are written
7258 If raw access is enabled, the data is written first, then the
7260 Otherwise, if the underlying NAND controller driver has
7261 a @code{write_page} routine, that routine may modify the OOB
7262 before it's written, to include hardware-computed ECC data.
7263 @item @code{oob_softecc}
7264 @*File has only page data, which is written.
7265 The OOB area is filled with 0xff, except for a standard 1-bit
7266 software ECC code stored in conventional locations.
7267 You might need to force raw access to use this mode, to prevent
7268 the underlying driver from applying hardware ECC.
7269 @item @code{oob_softecc_kw}
7270 @*File has only page data, which is written.
7271 The OOB area is filled with 0xff, except for a 4-bit software ECC
7272 specific to the boot ROM in Marvell Kirkwood SoCs.
7273 You might need to force raw access to use this mode, to prevent
7274 the underlying driver from applying hardware ECC.
7278 @deffn Command {nand verify} num filename offset [option...]
7279 @cindex NAND verification
7280 @cindex NAND programming
7281 Verify the binary data in the file has been programmed to the
7282 specified NAND device, starting at the specified offset.
7283 The @var{num} parameter is the value shown by @command{nand list}.
7285 Use a complete path name for @var{filename}, so you don't depend
7286 on the directory used to start the OpenOCD server.
7288 The @var{offset} must be an exact multiple of the device's page size.
7289 All data in the file will be read and compared to the contents of the
7290 flash, assuming it doesn't run past the end of the device.
7291 As with @command{nand write}, only full pages are verified, so any extra
7292 space in the last page will be filled with 0xff bytes.
7294 The same @var{options} accepted by @command{nand write},
7295 and the file will be processed similarly to produce the buffers that
7296 can be compared against the contents produced from @command{nand dump}.
7298 @b{NOTE:} This will not work when the underlying NAND controller
7299 driver's @code{write_page} routine must update the OOB with a
7300 hardware-computed ECC before the data is written. This limitation may
7301 be removed in a future release.
7304 @subsection Other NAND commands
7305 @cindex NAND other commands
7307 @deffn Command {nand check_bad_blocks} num [offset length]
7308 Checks for manufacturer bad block markers on the specified NAND
7309 device. If no parameters are provided, checks the whole
7310 device; otherwise, starts at the specified @var{offset} and
7311 continues for @var{length} bytes.
7312 Both of those values must be exact multiples of the device's
7313 block size, and the region they specify must fit entirely in the chip.
7314 The @var{num} parameter is the value shown by @command{nand list}.
7316 @b{NOTE:} Before using this command you should force raw access
7317 with @command{nand raw_access enable} to ensure that the underlying
7318 driver will not try to apply hardware ECC.
7321 @deffn Command {nand info} num
7322 The @var{num} parameter is the value shown by @command{nand list}.
7323 This prints the one-line summary from "nand list", plus for
7324 devices which have been probed this also prints any known
7325 status for each block.
7328 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
7329 Sets or clears an flag affecting how page I/O is done.
7330 The @var{num} parameter is the value shown by @command{nand list}.
7332 This flag is cleared (disabled) by default, but changing that
7333 value won't affect all NAND devices. The key factor is whether
7334 the underlying driver provides @code{read_page} or @code{write_page}
7335 methods. If it doesn't provide those methods, the setting of
7336 this flag is irrelevant; all access is effectively ``raw''.
7338 When those methods exist, they are normally used when reading
7339 data (@command{nand dump} or reading bad block markers) or
7340 writing it (@command{nand write}). However, enabling
7341 raw access (setting the flag) prevents use of those methods,
7342 bypassing hardware ECC logic.
7343 @i{This can be a dangerous option}, since writing blocks
7344 with the wrong ECC data can cause them to be marked as bad.
7347 @anchor{nanddriverlist}
7348 @subsection NAND Driver List
7349 As noted above, the @command{nand device} command allows
7350 driver-specific options and behaviors.
7351 Some controllers also activate controller-specific commands.
7353 @deffn {NAND Driver} at91sam9
7354 This driver handles the NAND controllers found on AT91SAM9 family chips from
7355 Atmel. It takes two extra parameters: address of the NAND chip;
7356 address of the ECC controller.
7358 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
7360 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
7361 @code{read_page} methods are used to utilize the ECC hardware unless they are
7362 disabled by using the @command{nand raw_access} command. There are four
7363 additional commands that are needed to fully configure the AT91SAM9 NAND
7364 controller. Two are optional; most boards use the same wiring for ALE/CLE:
7365 @deffn Command {at91sam9 cle} num addr_line
7366 Configure the address line used for latching commands. The @var{num}
7367 parameter is the value shown by @command{nand list}.
7369 @deffn Command {at91sam9 ale} num addr_line
7370 Configure the address line used for latching addresses. The @var{num}
7371 parameter is the value shown by @command{nand list}.
7374 For the next two commands, it is assumed that the pins have already been
7375 properly configured for input or output.
7376 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
7377 Configure the RDY/nBUSY input from the NAND device. The @var{num}
7378 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7379 is the base address of the PIO controller and @var{pin} is the pin number.
7381 @deffn Command {at91sam9 ce} num pio_base_addr pin
7382 Configure the chip enable input to the NAND device. The @var{num}
7383 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7384 is the base address of the PIO controller and @var{pin} is the pin number.
7388 @deffn {NAND Driver} davinci
7389 This driver handles the NAND controllers found on DaVinci family
7390 chips from Texas Instruments.
7391 It takes three extra parameters:
7392 address of the NAND chip;
7393 hardware ECC mode to use (@option{hwecc1},
7394 @option{hwecc4}, @option{hwecc4_infix});
7395 address of the AEMIF controller on this processor.
7397 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
7399 All DaVinci processors support the single-bit ECC hardware,
7400 and newer ones also support the four-bit ECC hardware.
7401 The @code{write_page} and @code{read_page} methods are used
7402 to implement those ECC modes, unless they are disabled using
7403 the @command{nand raw_access} command.
7406 @deffn {NAND Driver} lpc3180
7407 These controllers require an extra @command{nand device}
7408 parameter: the clock rate used by the controller.
7409 @deffn Command {lpc3180 select} num [mlc|slc]
7410 Configures use of the MLC or SLC controller mode.
7411 MLC implies use of hardware ECC.
7412 The @var{num} parameter is the value shown by @command{nand list}.
7415 At this writing, this driver includes @code{write_page}
7416 and @code{read_page} methods. Using @command{nand raw_access}
7417 to disable those methods will prevent use of hardware ECC
7418 in the MLC controller mode, but won't change SLC behavior.
7420 @comment current lpc3180 code won't issue 5-byte address cycles
7422 @deffn {NAND Driver} mx3
7423 This driver handles the NAND controller in i.MX31. The mxc driver
7424 should work for this chip as well.
7427 @deffn {NAND Driver} mxc
7428 This driver handles the NAND controller found in Freescale i.MX
7429 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
7430 The driver takes 3 extra arguments, chip (@option{mx27},
7431 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
7432 and optionally if bad block information should be swapped between
7433 main area and spare area (@option{biswap}), defaults to off.
7435 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
7437 @deffn Command {mxc biswap} bank_num [enable|disable]
7438 Turns on/off bad block information swapping from main area,
7439 without parameter query status.
7443 @deffn {NAND Driver} orion
7444 These controllers require an extra @command{nand device}
7445 parameter: the address of the controller.
7447 nand device orion 0xd8000000
7449 These controllers don't define any specialized commands.
7450 At this writing, their drivers don't include @code{write_page}
7451 or @code{read_page} methods, so @command{nand raw_access} won't
7452 change any behavior.
7455 @deffn {NAND Driver} s3c2410
7456 @deffnx {NAND Driver} s3c2412
7457 @deffnx {NAND Driver} s3c2440
7458 @deffnx {NAND Driver} s3c2443
7459 @deffnx {NAND Driver} s3c6400
7460 These S3C family controllers don't have any special
7461 @command{nand device} options, and don't define any
7462 specialized commands.
7463 At this writing, their drivers don't include @code{write_page}
7464 or @code{read_page} methods, so @command{nand raw_access} won't
7465 change any behavior.
7470 @subsection mFlash Configuration
7471 @cindex mFlash Configuration
7473 @deffn {Config Command} {mflash bank} soc base RST_pin target
7474 Configures a mflash for @var{soc} host bank at
7476 The pin number format depends on the host GPIO naming convention.
7477 Currently, the mflash driver supports s3c2440 and pxa270.
7479 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
7482 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
7485 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
7488 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
7492 @subsection mFlash commands
7493 @cindex mFlash commands
7495 @deffn Command {mflash config pll} frequency
7496 Configure mflash PLL.
7497 The @var{frequency} is the mflash input frequency, in Hz.
7498 Issuing this command will erase mflash's whole internal nand and write new pll.
7499 After this command, mflash needs power-on-reset for normal operation.
7500 If pll was newly configured, storage and boot(optional) info also need to be update.
7503 @deffn Command {mflash config boot}
7504 Configure bootable option.
7505 If bootable option is set, mflash offer the first 8 sectors
7509 @deffn Command {mflash config storage}
7510 Configure storage information.
7511 For the normal storage operation, this information must be
7515 @deffn Command {mflash dump} num filename offset size
7516 Dump @var{size} bytes, starting at @var{offset} bytes from the
7517 beginning of the bank @var{num}, to the file named @var{filename}.
7520 @deffn Command {mflash probe}
7524 @deffn Command {mflash write} num filename offset
7525 Write the binary file @var{filename} to mflash bank @var{num}, starting at
7526 @var{offset} bytes from the beginning of the bank.
7529 @node Flash Programming
7530 @chapter Flash Programming
7532 OpenOCD implements numerous ways to program the target flash, whether internal or external.
7533 Programming can be achieved by either using GDB @ref{programmingusinggdb,,Programming using GDB},
7534 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
7536 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
7537 OpenOCD will program/verify/reset the target and optionally shutdown.
7539 The script is executed as follows and by default the following actions will be performed.
7541 @item 'init' is executed.
7542 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
7543 @item @code{flash write_image} is called to erase and write any flash using the filename given.
7544 @item @code{verify_image} is called if @option{verify} parameter is given.
7545 @item @code{reset run} is called if @option{reset} parameter is given.
7546 @item OpenOCD is shutdown if @option{exit} parameter is given.
7549 An example of usage is given below. @xref{program}.
7552 # program and verify using elf/hex/s19. verify and reset
7553 # are optional parameters
7554 openocd -f board/stm32f3discovery.cfg \
7555 -c "program filename.elf verify reset exit"
7557 # binary files need the flash address passing
7558 openocd -f board/stm32f3discovery.cfg \
7559 -c "program filename.bin exit 0x08000000"
7562 @node PLD/FPGA Commands
7563 @chapter PLD/FPGA Commands
7567 Programmable Logic Devices (PLDs) and the more flexible
7568 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
7569 OpenOCD can support programming them.
7570 Although PLDs are generally restrictive (cells are less functional, and
7571 there are no special purpose cells for memory or computational tasks),
7572 they share the same OpenOCD infrastructure.
7573 Accordingly, both are called PLDs here.
7575 @section PLD/FPGA Configuration and Commands
7577 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
7578 OpenOCD maintains a list of PLDs available for use in various commands.
7579 Also, each such PLD requires a driver.
7581 They are referenced by the number shown by the @command{pld devices} command,
7582 and new PLDs are defined by @command{pld device driver_name}.
7584 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
7585 Defines a new PLD device, supported by driver @var{driver_name},
7586 using the TAP named @var{tap_name}.
7587 The driver may make use of any @var{driver_options} to configure its
7591 @deffn {Command} {pld devices}
7592 Lists the PLDs and their numbers.
7595 @deffn {Command} {pld load} num filename
7596 Loads the file @file{filename} into the PLD identified by @var{num}.
7597 The file format must be inferred by the driver.
7600 @section PLD/FPGA Drivers, Options, and Commands
7602 Drivers may support PLD-specific options to the @command{pld device}
7603 definition command, and may also define commands usable only with
7604 that particular type of PLD.
7606 @deffn {FPGA Driver} virtex2 [no_jstart]
7607 Virtex-II is a family of FPGAs sold by Xilinx.
7608 It supports the IEEE 1532 standard for In-System Configuration (ISC).
7610 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
7611 loading the bitstream. While required for Series2, Series3, and Series6, it
7612 breaks bitstream loading on Series7.
7614 @deffn {Command} {virtex2 read_stat} num
7615 Reads and displays the Virtex-II status register (STAT)
7620 @node General Commands
7621 @chapter General Commands
7624 The commands documented in this chapter here are common commands that
7625 you, as a human, may want to type and see the output of. Configuration type
7626 commands are documented elsewhere.
7630 @item @b{Source Of Commands}
7631 @* OpenOCD commands can occur in a configuration script (discussed
7632 elsewhere) or typed manually by a human or supplied programmatically,
7633 or via one of several TCP/IP Ports.
7635 @item @b{From the human}
7636 @* A human should interact with the telnet interface (default port: 4444)
7637 or via GDB (default port 3333).
7639 To issue commands from within a GDB session, use the @option{monitor}
7640 command, e.g. use @option{monitor poll} to issue the @option{poll}
7641 command. All output is relayed through the GDB session.
7643 @item @b{Machine Interface}
7644 The Tcl interface's intent is to be a machine interface. The default Tcl
7649 @section Server Commands
7651 @deffn {Command} exit
7652 Exits the current telnet session.
7655 @deffn {Command} help [string]
7656 With no parameters, prints help text for all commands.
7657 Otherwise, prints each helptext containing @var{string}.
7658 Not every command provides helptext.
7660 Configuration commands, and commands valid at any time, are
7661 explicitly noted in parenthesis.
7662 In most cases, no such restriction is listed; this indicates commands
7663 which are only available after the configuration stage has completed.
7666 @deffn Command sleep msec [@option{busy}]
7667 Wait for at least @var{msec} milliseconds before resuming.
7668 If @option{busy} is passed, busy-wait instead of sleeping.
7669 (This option is strongly discouraged.)
7670 Useful in connection with script files
7671 (@command{script} command and @command{target_name} configuration).
7674 @deffn Command shutdown [@option{error}]
7675 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
7676 other). If option @option{error} is used, OpenOCD will return a
7677 non-zero exit code to the parent process.
7679 Like any TCL commands, also @command{shutdown} can be redefined, e.g.:
7682 rename shutdown original_shutdown
7683 proc shutdown @{@} @{
7684 puts "This is my implementation of shutdown"
7685 # my own stuff before exit OpenOCD
7689 If user types CTRL-C or kills OpenOCD, either the command @command{shutdown}
7690 or its replacement will be automatically executed before OpenOCD exits.
7694 @deffn Command debug_level [n]
7695 @cindex message level
7696 Display debug level.
7697 If @var{n} (from 0..4) is provided, then set it to that level.
7698 This affects the kind of messages sent to the server log.
7699 Level 0 is error messages only;
7700 level 1 adds warnings;
7701 level 2 adds informational messages;
7702 level 3 adds debugging messages;
7703 and level 4 adds verbose low-level debug messages.
7704 The default is level 2, but that can be overridden on
7705 the command line along with the location of that log
7706 file (which is normally the server's standard output).
7710 @deffn Command echo [-n] message
7711 Logs a message at "user" priority.
7712 Output @var{message} to stdout.
7713 Option "-n" suppresses trailing newline.
7715 echo "Downloading kernel -- please wait"
7719 @deffn Command log_output [filename]
7720 Redirect logging to @var{filename};
7721 the initial log output channel is stderr.
7724 @deffn Command add_script_search_dir [directory]
7725 Add @var{directory} to the file/script search path.
7728 @deffn Command bindto [@var{name}]
7729 Specify hostname or IPv4 address on which to listen for incoming
7730 TCP/IP connections. By default, OpenOCD will listen on the loopback
7731 interface only. If your network environment is safe, @code{bindto
7732 0.0.0.0} can be used to cover all available interfaces.
7735 @anchor{targetstatehandling}
7736 @section Target State handling
7739 @cindex target initialization
7741 In this section ``target'' refers to a CPU configured as
7742 shown earlier (@pxref{CPU Configuration}).
7743 These commands, like many, implicitly refer to
7744 a current target which is used to perform the
7745 various operations. The current target may be changed
7746 by using @command{targets} command with the name of the
7747 target which should become current.
7749 @deffn Command reg [(number|name) [(value|'force')]]
7750 Access a single register by @var{number} or by its @var{name}.
7751 The target must generally be halted before access to CPU core
7752 registers is allowed. Depending on the hardware, some other
7753 registers may be accessible while the target is running.
7755 @emph{With no arguments}:
7756 list all available registers for the current target,
7757 showing number, name, size, value, and cache status.
7758 For valid entries, a value is shown; valid entries
7759 which are also dirty (and will be written back later)
7760 are flagged as such.
7762 @emph{With number/name}: display that register's value.
7763 Use @var{force} argument to read directly from the target,
7764 bypassing any internal cache.
7766 @emph{With both number/name and value}: set register's value.
7767 Writes may be held in a writeback cache internal to OpenOCD,
7768 so that setting the value marks the register as dirty instead
7769 of immediately flushing that value. Resuming CPU execution
7770 (including by single stepping) or otherwise activating the
7771 relevant module will flush such values.
7773 Cores may have surprisingly many registers in their
7774 Debug and trace infrastructure:
7779 (0) r0 (/32): 0x0000D3C2 (dirty)
7780 (1) r1 (/32): 0xFD61F31C
7783 (164) ETM_contextid_comparator_mask (/32)
7788 @deffn Command halt [ms]
7789 @deffnx Command wait_halt [ms]
7790 The @command{halt} command first sends a halt request to the target,
7791 which @command{wait_halt} doesn't.
7792 Otherwise these behave the same: wait up to @var{ms} milliseconds,
7793 or 5 seconds if there is no parameter, for the target to halt
7794 (and enter debug mode).
7795 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
7798 On ARM cores, software using the @emph{wait for interrupt} operation
7799 often blocks the JTAG access needed by a @command{halt} command.
7800 This is because that operation also puts the core into a low
7801 power mode by gating the core clock;
7802 but the core clock is needed to detect JTAG clock transitions.
7804 One partial workaround uses adaptive clocking: when the core is
7805 interrupted the operation completes, then JTAG clocks are accepted
7806 at least until the interrupt handler completes.
7807 However, this workaround is often unusable since the processor, board,
7808 and JTAG adapter must all support adaptive JTAG clocking.
7809 Also, it can't work until an interrupt is issued.
7811 A more complete workaround is to not use that operation while you
7812 work with a JTAG debugger.
7813 Tasking environments generally have idle loops where the body is the
7814 @emph{wait for interrupt} operation.
7815 (On older cores, it is a coprocessor action;
7816 newer cores have a @option{wfi} instruction.)
7817 Such loops can just remove that operation, at the cost of higher
7818 power consumption (because the CPU is needlessly clocked).
7823 @deffn Command resume [address]
7824 Resume the target at its current code position,
7825 or the optional @var{address} if it is provided.
7826 OpenOCD will wait 5 seconds for the target to resume.
7829 @deffn Command step [address]
7830 Single-step the target at its current code position,
7831 or the optional @var{address} if it is provided.
7834 @anchor{resetcommand}
7835 @deffn Command reset
7836 @deffnx Command {reset run}
7837 @deffnx Command {reset halt}
7838 @deffnx Command {reset init}
7839 Perform as hard a reset as possible, using SRST if possible.
7840 @emph{All defined targets will be reset, and target
7841 events will fire during the reset sequence.}
7843 The optional parameter specifies what should
7844 happen after the reset.
7845 If there is no parameter, a @command{reset run} is executed.
7846 The other options will not work on all systems.
7847 @xref{Reset Configuration}.
7850 @item @b{run} Let the target run
7851 @item @b{halt} Immediately halt the target
7852 @item @b{init} Immediately halt the target, and execute the reset-init script
7856 @deffn Command soft_reset_halt
7857 Requesting target halt and executing a soft reset. This is often used
7858 when a target cannot be reset and halted. The target, after reset is
7859 released begins to execute code. OpenOCD attempts to stop the CPU and
7860 then sets the program counter back to the reset vector. Unfortunately
7861 the code that was executed may have left the hardware in an unknown
7865 @section I/O Utilities
7867 These commands are available when
7868 OpenOCD is built with @option{--enable-ioutil}.
7869 They are mainly useful on embedded targets,
7871 Hosts with operating systems have complementary tools.
7873 @emph{Note:} there are several more such commands.
7875 @deffn Command append_file filename [string]*
7876 Appends the @var{string} parameters to
7877 the text file @file{filename}.
7878 Each string except the last one is followed by one space.
7879 The last string is followed by a newline.
7882 @deffn Command cat filename
7883 Reads and displays the text file @file{filename}.
7886 @deffn Command cp src_filename dest_filename
7887 Copies contents from the file @file{src_filename}
7888 into @file{dest_filename}.
7892 @emph{No description provided.}
7896 @emph{No description provided.}
7900 @emph{No description provided.}
7903 @deffn Command meminfo
7904 Display available RAM memory on OpenOCD host.
7905 Used in OpenOCD regression testing scripts.
7909 @emph{No description provided.}
7913 @emph{No description provided.}
7916 @deffn Command rm filename
7917 @c "rm" has both normal and Jim-level versions??
7918 Unlinks the file @file{filename}.
7921 @deffn Command trunc filename
7922 Removes all data in the file @file{filename}.
7925 @anchor{memoryaccess}
7926 @section Memory access commands
7927 @cindex memory access
7929 These commands allow accesses of a specific size to the memory
7930 system. Often these are used to configure the current target in some
7931 special way. For example - one may need to write certain values to the
7932 SDRAM controller to enable SDRAM.
7935 @item Use the @command{targets} (plural) command
7936 to change the current target.
7937 @item In system level scripts these commands are deprecated.
7938 Please use their TARGET object siblings to avoid making assumptions
7939 about what TAP is the current target, or about MMU configuration.
7942 @deffn Command mdw [phys] addr [count]
7943 @deffnx Command mdh [phys] addr [count]
7944 @deffnx Command mdb [phys] addr [count]
7945 Display contents of address @var{addr}, as
7946 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
7947 or 8-bit bytes (@command{mdb}).
7948 When the current target has an MMU which is present and active,
7949 @var{addr} is interpreted as a virtual address.
7950 Otherwise, or if the optional @var{phys} flag is specified,
7951 @var{addr} is interpreted as a physical address.
7952 If @var{count} is specified, displays that many units.
7953 (If you want to manipulate the data instead of displaying it,
7954 see the @code{mem2array} primitives.)
7957 @deffn Command mww [phys] addr word
7958 @deffnx Command mwh [phys] addr halfword
7959 @deffnx Command mwb [phys] addr byte
7960 Writes the specified @var{word} (32 bits),
7961 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
7962 at the specified address @var{addr}.
7963 When the current target has an MMU which is present and active,
7964 @var{addr} is interpreted as a virtual address.
7965 Otherwise, or if the optional @var{phys} flag is specified,
7966 @var{addr} is interpreted as a physical address.
7969 @anchor{imageaccess}
7970 @section Image loading commands
7971 @cindex image loading
7972 @cindex image dumping
7974 @deffn Command {dump_image} filename address size
7975 Dump @var{size} bytes of target memory starting at @var{address} to the
7976 binary file named @var{filename}.
7979 @deffn Command {fast_load}
7980 Loads an image stored in memory by @command{fast_load_image} to the
7981 current target. Must be preceded by fast_load_image.
7984 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
7985 Normally you should be using @command{load_image} or GDB load. However, for
7986 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
7987 host), storing the image in memory and uploading the image to the target
7988 can be a way to upload e.g. multiple debug sessions when the binary does not change.
7989 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
7990 memory, i.e. does not affect target. This approach is also useful when profiling
7991 target programming performance as I/O and target programming can easily be profiled
7995 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
7996 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
7997 The file format may optionally be specified
7998 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
7999 In addition the following arguments may be specified:
8000 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
8001 @var{max_length} - maximum number of bytes to load.
8003 proc load_image_bin @{fname foffset address length @} @{
8004 # Load data from fname filename at foffset offset to
8005 # target at address. Load at most length bytes.
8006 load_image $fname [expr $address - $foffset] bin \
8012 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
8013 Displays image section sizes and addresses
8014 as if @var{filename} were loaded into target memory
8015 starting at @var{address} (defaults to zero).
8016 The file format may optionally be specified
8017 (@option{bin}, @option{ihex}, or @option{elf})
8020 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
8021 Verify @var{filename} against target memory starting at @var{address}.
8022 The file format may optionally be specified
8023 (@option{bin}, @option{ihex}, or @option{elf})
8024 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
8027 @deffn Command {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
8028 Verify @var{filename} against target memory starting at @var{address}.
8029 The file format may optionally be specified
8030 (@option{bin}, @option{ihex}, or @option{elf})
8031 This perform a comparison using a CRC checksum only
8035 @section Breakpoint and Watchpoint commands
8039 CPUs often make debug modules accessible through JTAG, with
8040 hardware support for a handful of code breakpoints and data
8042 In addition, CPUs almost always support software breakpoints.
8044 @deffn Command {bp} [address len [@option{hw}]]
8045 With no parameters, lists all active breakpoints.
8046 Else sets a breakpoint on code execution starting
8047 at @var{address} for @var{length} bytes.
8048 This is a software breakpoint, unless @option{hw} is specified
8049 in which case it will be a hardware breakpoint.
8051 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
8052 for similar mechanisms that do not consume hardware breakpoints.)
8055 @deffn Command {rbp} address
8056 Remove the breakpoint at @var{address}.
8059 @deffn Command {rwp} address
8060 Remove data watchpoint on @var{address}
8063 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
8064 With no parameters, lists all active watchpoints.
8065 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
8066 The watch point is an "access" watchpoint unless
8067 the @option{r} or @option{w} parameter is provided,
8068 defining it as respectively a read or write watchpoint.
8069 If a @var{value} is provided, that value is used when determining if
8070 the watchpoint should trigger. The value may be first be masked
8071 using @var{mask} to mark ``don't care'' fields.
8074 @section Misc Commands
8077 @deffn Command {profile} seconds filename [start end]
8078 Profiling samples the CPU's program counter as quickly as possible,
8079 which is useful for non-intrusive stochastic profiling.
8080 Saves up to 10000 samples in @file{filename} using ``gmon.out''
8081 format. Optional @option{start} and @option{end} parameters allow to
8082 limit the address range.
8085 @deffn Command {version}
8086 Displays a string identifying the version of this OpenOCD server.
8089 @deffn Command {virt2phys} virtual_address
8090 Requests the current target to map the specified @var{virtual_address}
8091 to its corresponding physical address, and displays the result.
8094 @node Architecture and Core Commands
8095 @chapter Architecture and Core Commands
8096 @cindex Architecture Specific Commands
8097 @cindex Core Specific Commands
8099 Most CPUs have specialized JTAG operations to support debugging.
8100 OpenOCD packages most such operations in its standard command framework.
8101 Some of those operations don't fit well in that framework, so they are
8102 exposed here as architecture or implementation (core) specific commands.
8104 @anchor{armhardwaretracing}
8105 @section ARM Hardware Tracing
8110 CPUs based on ARM cores may include standard tracing interfaces,
8111 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
8112 address and data bus trace records to a ``Trace Port''.
8116 Development-oriented boards will sometimes provide a high speed
8117 trace connector for collecting that data, when the particular CPU
8118 supports such an interface.
8119 (The standard connector is a 38-pin Mictor, with both JTAG
8120 and trace port support.)
8121 Those trace connectors are supported by higher end JTAG adapters
8122 and some logic analyzer modules; frequently those modules can
8123 buffer several megabytes of trace data.
8124 Configuring an ETM coupled to such an external trace port belongs
8125 in the board-specific configuration file.
8127 If the CPU doesn't provide an external interface, it probably
8128 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
8129 dedicated SRAM. 4KBytes is one common ETB size.
8130 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
8131 (target) configuration file, since it works the same on all boards.
8134 ETM support in OpenOCD doesn't seem to be widely used yet.
8137 ETM support may be buggy, and at least some @command{etm config}
8138 parameters should be detected by asking the ETM for them.
8140 ETM trigger events could also implement a kind of complex
8141 hardware breakpoint, much more powerful than the simple
8142 watchpoint hardware exported by EmbeddedICE modules.
8143 @emph{Such breakpoints can be triggered even when using the
8144 dummy trace port driver}.
8146 It seems like a GDB hookup should be possible,
8147 as well as tracing only during specific states
8148 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
8150 There should be GUI tools to manipulate saved trace data and help
8151 analyse it in conjunction with the source code.
8152 It's unclear how much of a common interface is shared
8153 with the current XScale trace support, or should be
8154 shared with eventual Nexus-style trace module support.
8156 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
8157 for ETM modules is available. The code should be able to
8158 work with some newer cores; but not all of them support
8159 this original style of JTAG access.
8162 @subsection ETM Configuration
8163 ETM setup is coupled with the trace port driver configuration.
8165 @deffn {Config Command} {etm config} target width mode clocking driver
8166 Declares the ETM associated with @var{target}, and associates it
8167 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
8169 Several of the parameters must reflect the trace port capabilities,
8170 which are a function of silicon capabilities (exposed later
8171 using @command{etm info}) and of what hardware is connected to
8172 that port (such as an external pod, or ETB).
8173 The @var{width} must be either 4, 8, or 16,
8174 except with ETMv3.0 and newer modules which may also
8175 support 1, 2, 24, 32, 48, and 64 bit widths.
8176 (With those versions, @command{etm info} also shows whether
8177 the selected port width and mode are supported.)
8179 The @var{mode} must be @option{normal}, @option{multiplexed},
8180 or @option{demultiplexed}.
8181 The @var{clocking} must be @option{half} or @option{full}.
8184 With ETMv3.0 and newer, the bits set with the @var{mode} and
8185 @var{clocking} parameters both control the mode.
8186 This modified mode does not map to the values supported by
8187 previous ETM modules, so this syntax is subject to change.
8191 You can see the ETM registers using the @command{reg} command.
8192 Not all possible registers are present in every ETM.
8193 Most of the registers are write-only, and are used to configure
8194 what CPU activities are traced.
8198 @deffn Command {etm info}
8199 Displays information about the current target's ETM.
8200 This includes resource counts from the @code{ETM_CONFIG} register,
8201 as well as silicon capabilities (except on rather old modules).
8202 from the @code{ETM_SYS_CONFIG} register.
8205 @deffn Command {etm status}
8206 Displays status of the current target's ETM and trace port driver:
8207 is the ETM idle, or is it collecting data?
8208 Did trace data overflow?
8212 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
8213 Displays what data that ETM will collect.
8214 If arguments are provided, first configures that data.
8215 When the configuration changes, tracing is stopped
8216 and any buffered trace data is invalidated.
8219 @item @var{type} ... describing how data accesses are traced,
8220 when they pass any ViewData filtering that that was set up.
8222 @option{none} (save nothing),
8223 @option{data} (save data),
8224 @option{address} (save addresses),
8225 @option{all} (save data and addresses)
8226 @item @var{context_id_bits} ... 0, 8, 16, or 32
8227 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
8228 cycle-accurate instruction tracing.
8229 Before ETMv3, enabling this causes much extra data to be recorded.
8230 @item @var{branch_output} ... @option{enable} or @option{disable}.
8231 Disable this unless you need to try reconstructing the instruction
8232 trace stream without an image of the code.
8236 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
8237 Displays whether ETM triggering debug entry (like a breakpoint) is
8238 enabled or disabled, after optionally modifying that configuration.
8239 The default behaviour is @option{disable}.
8240 Any change takes effect after the next @command{etm start}.
8242 By using script commands to configure ETM registers, you can make the
8243 processor enter debug state automatically when certain conditions,
8244 more complex than supported by the breakpoint hardware, happen.
8247 @subsection ETM Trace Operation
8249 After setting up the ETM, you can use it to collect data.
8250 That data can be exported to files for later analysis.
8251 It can also be parsed with OpenOCD, for basic sanity checking.
8253 To configure what is being traced, you will need to write
8254 various trace registers using @command{reg ETM_*} commands.
8255 For the definitions of these registers, read ARM publication
8256 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
8257 Be aware that most of the relevant registers are write-only,
8258 and that ETM resources are limited. There are only a handful
8259 of address comparators, data comparators, counters, and so on.
8261 Examples of scenarios you might arrange to trace include:
8264 @item Code flow within a function, @emph{excluding} subroutines
8265 it calls. Use address range comparators to enable tracing
8266 for instruction access within that function's body.
8267 @item Code flow within a function, @emph{including} subroutines
8268 it calls. Use the sequencer and address comparators to activate
8269 tracing on an ``entered function'' state, then deactivate it by
8270 exiting that state when the function's exit code is invoked.
8271 @item Code flow starting at the fifth invocation of a function,
8272 combining one of the above models with a counter.
8273 @item CPU data accesses to the registers for a particular device,
8274 using address range comparators and the ViewData logic.
8275 @item Such data accesses only during IRQ handling, combining the above
8276 model with sequencer triggers which on entry and exit to the IRQ handler.
8277 @item @emph{... more}
8280 At this writing, September 2009, there are no Tcl utility
8281 procedures to help set up any common tracing scenarios.
8283 @deffn Command {etm analyze}
8284 Reads trace data into memory, if it wasn't already present.
8285 Decodes and prints the data that was collected.
8288 @deffn Command {etm dump} filename
8289 Stores the captured trace data in @file{filename}.
8292 @deffn Command {etm image} filename [base_address] [type]
8293 Opens an image file.
8296 @deffn Command {etm load} filename
8297 Loads captured trace data from @file{filename}.
8300 @deffn Command {etm start}
8301 Starts trace data collection.
8304 @deffn Command {etm stop}
8305 Stops trace data collection.
8308 @anchor{traceportdrivers}
8309 @subsection Trace Port Drivers
8311 To use an ETM trace port it must be associated with a driver.
8313 @deffn {Trace Port Driver} dummy
8314 Use the @option{dummy} driver if you are configuring an ETM that's
8315 not connected to anything (on-chip ETB or off-chip trace connector).
8316 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
8317 any trace data collection.}
8318 @deffn {Config Command} {etm_dummy config} target
8319 Associates the ETM for @var{target} with a dummy driver.
8323 @deffn {Trace Port Driver} etb
8324 Use the @option{etb} driver if you are configuring an ETM
8325 to use on-chip ETB memory.
8326 @deffn {Config Command} {etb config} target etb_tap
8327 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
8328 You can see the ETB registers using the @command{reg} command.
8330 @deffn Command {etb trigger_percent} [percent]
8331 This displays, or optionally changes, ETB behavior after the
8332 ETM's configured @emph{trigger} event fires.
8333 It controls how much more trace data is saved after the (single)
8334 trace trigger becomes active.
8337 @item The default corresponds to @emph{trace around} usage,
8338 recording 50 percent data before the event and the rest
8340 @item The minimum value of @var{percent} is 2 percent,
8341 recording almost exclusively data before the trigger.
8342 Such extreme @emph{trace before} usage can help figure out
8343 what caused that event to happen.
8344 @item The maximum value of @var{percent} is 100 percent,
8345 recording data almost exclusively after the event.
8346 This extreme @emph{trace after} usage might help sort out
8347 how the event caused trouble.
8349 @c REVISIT allow "break" too -- enter debug mode.
8354 @deffn {Trace Port Driver} oocd_trace
8355 This driver isn't available unless OpenOCD was explicitly configured
8356 with the @option{--enable-oocd_trace} option. You probably don't want
8357 to configure it unless you've built the appropriate prototype hardware;
8358 it's @emph{proof-of-concept} software.
8360 Use the @option{oocd_trace} driver if you are configuring an ETM that's
8361 connected to an off-chip trace connector.
8363 @deffn {Config Command} {oocd_trace config} target tty
8364 Associates the ETM for @var{target} with a trace driver which
8365 collects data through the serial port @var{tty}.
8368 @deffn Command {oocd_trace resync}
8369 Re-synchronizes with the capture clock.
8372 @deffn Command {oocd_trace status}
8373 Reports whether the capture clock is locked or not.
8377 @anchor{armcrosstrigger}
8378 @section ARM Cross-Trigger Interface
8381 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
8382 that connects event sources like tracing components or CPU cores with each
8383 other through a common trigger matrix (CTM). For ARMv8 architecture, a
8384 CTI is mandatory for core run control and each core has an individual
8385 CTI instance attached to it. OpenOCD has limited support for CTI using
8386 the @emph{cti} group of commands.
8388 @deffn Command {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-ctibase} base_address
8389 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
8390 @var{apn}. The @var{base_address} must match the base address of the CTI
8391 on the respective MEM-AP. All arguments are mandatory. This creates a
8392 new command @command{$cti_name} which is used for various purposes
8393 including additional configuration.
8396 @deffn Command {$cti_name enable} @option{on|off}
8397 Enable (@option{on}) or disable (@option{off}) the CTI.
8400 @deffn Command {$cti_name dump}
8401 Displays a register dump of the CTI.
8404 @deffn Command {$cti_name write } @var{reg_name} @var{value}
8405 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
8408 @deffn Command {$cti_name read} @var{reg_name}
8409 Print the value read from the CTI register with the symbolic name @var{reg_name}.
8412 @deffn Command {$cti_name testmode} @option{on|off}
8413 Enable (@option{on}) or disable (@option{off}) the integration test mode
8417 @deffn Command {cti names}
8418 Prints a list of names of all CTI objects created. This command is mainly
8419 useful in TCL scripting.
8422 @section Generic ARM
8425 These commands should be available on all ARM processors.
8426 They are available in addition to other core-specific
8427 commands that may be available.
8429 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
8430 Displays the core_state, optionally changing it to process
8431 either @option{arm} or @option{thumb} instructions.
8432 The target may later be resumed in the currently set core_state.
8433 (Processors may also support the Jazelle state, but
8434 that is not currently supported in OpenOCD.)
8437 @deffn Command {arm disassemble} address [count [@option{thumb}]]
8439 Disassembles @var{count} instructions starting at @var{address}.
8440 If @var{count} is not specified, a single instruction is disassembled.
8441 If @option{thumb} is specified, or the low bit of the address is set,
8442 Thumb2 (mixed 16/32-bit) instructions are used;
8443 else ARM (32-bit) instructions are used.
8444 (Processors may also support the Jazelle state, but
8445 those instructions are not currently understood by OpenOCD.)
8447 Note that all Thumb instructions are Thumb2 instructions,
8448 so older processors (without Thumb2 support) will still
8449 see correct disassembly of Thumb code.
8450 Also, ThumbEE opcodes are the same as Thumb2,
8451 with a handful of exceptions.
8452 ThumbEE disassembly currently has no explicit support.
8455 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
8456 Write @var{value} to a coprocessor @var{pX} register
8457 passing parameters @var{CRn},
8458 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8459 and using the MCR instruction.
8460 (Parameter sequence matches the ARM instruction, but omits
8464 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
8465 Read a coprocessor @var{pX} register passing parameters @var{CRn},
8466 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8467 and the MRC instruction.
8468 Returns the result so it can be manipulated by Jim scripts.
8469 (Parameter sequence matches the ARM instruction, but omits
8473 @deffn Command {arm reg}
8474 Display a table of all banked core registers, fetching the current value from every
8475 core mode if necessary.
8478 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
8479 @cindex ARM semihosting
8480 Display status of semihosting, after optionally changing that status.
8482 Semihosting allows for code executing on an ARM target to use the
8483 I/O facilities on the host computer i.e. the system where OpenOCD
8484 is running. The target application must be linked against a library
8485 implementing the ARM semihosting convention that forwards operation
8486 requests by using a special SVC instruction that is trapped at the
8487 Supervisor Call vector by OpenOCD.
8490 @deffn Command {arm semihosting_cmdline} [@option{enable}|@option{disable}]
8491 @cindex ARM semihosting
8492 Set the command line to be passed to the debugger.
8495 arm semihosting_cmdline argv0 argv1 argv2 ...
8498 This option lets one set the command line arguments to be passed to
8499 the program. The first argument (argv0) is the program name in a
8500 standard C environment (argv[0]). Depending on the program (not much
8501 programs look at argv[0]), argv0 is ignored and can be any string.
8504 @deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
8505 @cindex ARM semihosting
8506 Display status of semihosting fileio, after optionally changing that
8509 Enabling this option forwards semihosting I/O to GDB process using the
8510 File-I/O remote protocol extension. This is especially useful for
8511 interacting with remote files or displaying console messages in the
8515 @deffn Command {arm semihosting_resexit} [@option{enable}|@option{disable}]
8516 @cindex ARM semihosting
8517 Enable resumable SEMIHOSTING_SYS_EXIT.
8519 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
8520 things are simple, the openocd process calls exit() and passes
8521 the value returned by the target.
8523 When SEMIHOSTING_SYS_EXIT is called during a debug session,
8524 by default execution returns to the debugger, leaving the
8525 debugger in a HALT state, similar to the state entered when
8526 encountering a break.
8528 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
8529 return normally, as any semihosting call, and do not break
8531 The standard allows this to happen, but the condition
8532 to trigger it is a bit obscure ("by performing an RDI_Execute
8533 request or equivalent").
8535 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
8536 this option (default: disabled).
8539 @section ARMv4 and ARMv5 Architecture
8543 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
8544 and introduced core parts of the instruction set in use today.
8545 That includes the Thumb instruction set, introduced in the ARMv4T
8548 @subsection ARM7 and ARM9 specific commands
8552 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
8553 ARM9TDMI, ARM920T or ARM926EJ-S.
8554 They are available in addition to the ARM commands,
8555 and any other core-specific commands that may be available.
8557 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
8558 Displays the value of the flag controlling use of the
8559 the EmbeddedIce DBGRQ signal to force entry into debug mode,
8560 instead of breakpoints.
8561 If a boolean parameter is provided, first assigns that flag.
8564 safe for all but ARM7TDMI-S cores (like NXP LPC).
8565 This feature is enabled by default on most ARM9 cores,
8566 including ARM9TDMI, ARM920T, and ARM926EJ-S.
8569 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
8571 Displays the value of the flag controlling use of the debug communications
8572 channel (DCC) to write larger (>128 byte) amounts of memory.
8573 If a boolean parameter is provided, first assigns that flag.
8575 DCC downloads offer a huge speed increase, but might be
8576 unsafe, especially with targets running at very low speeds. This command was introduced
8577 with OpenOCD rev. 60, and requires a few bytes of working area.
8580 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
8581 Displays the value of the flag controlling use of memory writes and reads
8582 that don't check completion of the operation.
8583 If a boolean parameter is provided, first assigns that flag.
8585 This provides a huge speed increase, especially with USB JTAG
8586 cables (FT2232), but might be unsafe if used with targets running at very low
8587 speeds, like the 32kHz startup clock of an AT91RM9200.
8590 @subsection ARM720T specific commands
8593 These commands are available to ARM720T based CPUs,
8594 which are implementations of the ARMv4T architecture
8595 based on the ARM7TDMI-S integer core.
8596 They are available in addition to the ARM and ARM7/ARM9 commands.
8598 @deffn Command {arm720t cp15} opcode [value]
8599 @emph{DEPRECATED -- avoid using this.
8600 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8602 Display cp15 register returned by the ARM instruction @var{opcode};
8603 else if a @var{value} is provided, that value is written to that register.
8604 The @var{opcode} should be the value of either an MRC or MCR instruction.
8607 @subsection ARM9 specific commands
8610 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
8612 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
8614 @c 9-june-2009: tried this on arm920t, it didn't work.
8615 @c no-params always lists nothing caught, and that's how it acts.
8616 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
8617 @c versions have different rules about when they commit writes.
8619 @anchor{arm9vectorcatch}
8620 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
8621 @cindex vector_catch
8622 Vector Catch hardware provides a sort of dedicated breakpoint
8623 for hardware events such as reset, interrupt, and abort.
8624 You can use this to conserve normal breakpoint resources,
8625 so long as you're not concerned with code that branches directly
8626 to those hardware vectors.
8628 This always finishes by listing the current configuration.
8629 If parameters are provided, it first reconfigures the
8630 vector catch hardware to intercept
8631 @option{all} of the hardware vectors,
8632 @option{none} of them,
8633 or a list with one or more of the following:
8634 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
8635 @option{irq} @option{fiq}.
8638 @subsection ARM920T specific commands
8641 These commands are available to ARM920T based CPUs,
8642 which are implementations of the ARMv4T architecture
8643 built using the ARM9TDMI integer core.
8644 They are available in addition to the ARM, ARM7/ARM9,
8647 @deffn Command {arm920t cache_info}
8648 Print information about the caches found. This allows to see whether your target
8649 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
8652 @deffn Command {arm920t cp15} regnum [value]
8653 Display cp15 register @var{regnum};
8654 else if a @var{value} is provided, that value is written to that register.
8655 This uses "physical access" and the register number is as
8656 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
8657 (Not all registers can be written.)
8660 @deffn Command {arm920t cp15i} opcode [value [address]]
8661 @emph{DEPRECATED -- avoid using this.
8662 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8664 Interpreted access using ARM instruction @var{opcode}, which should
8665 be the value of either an MRC or MCR instruction
8666 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
8667 If no @var{value} is provided, the result is displayed.
8668 Else if that value is written using the specified @var{address},
8669 or using zero if no other address is provided.
8672 @deffn Command {arm920t read_cache} filename
8673 Dump the content of ICache and DCache to a file named @file{filename}.
8676 @deffn Command {arm920t read_mmu} filename
8677 Dump the content of the ITLB and DTLB to a file named @file{filename}.
8680 @subsection ARM926ej-s specific commands
8683 These commands are available to ARM926ej-s based CPUs,
8684 which are implementations of the ARMv5TEJ architecture
8685 based on the ARM9EJ-S integer core.
8686 They are available in addition to the ARM, ARM7/ARM9,
8689 The Feroceon cores also support these commands, although
8690 they are not built from ARM926ej-s designs.
8692 @deffn Command {arm926ejs cache_info}
8693 Print information about the caches found.
8696 @subsection ARM966E specific commands
8699 These commands are available to ARM966 based CPUs,
8700 which are implementations of the ARMv5TE architecture.
8701 They are available in addition to the ARM, ARM7/ARM9,
8704 @deffn Command {arm966e cp15} regnum [value]
8705 Display cp15 register @var{regnum};
8706 else if a @var{value} is provided, that value is written to that register.
8707 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
8709 There is no current control over bits 31..30 from that table,
8710 as required for BIST support.
8713 @subsection XScale specific commands
8716 Some notes about the debug implementation on the XScale CPUs:
8718 The XScale CPU provides a special debug-only mini-instruction cache
8719 (mini-IC) in which exception vectors and target-resident debug handler
8720 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
8721 must point vector 0 (the reset vector) to the entry of the debug
8722 handler. However, this means that the complete first cacheline in the
8723 mini-IC is marked valid, which makes the CPU fetch all exception
8724 handlers from the mini-IC, ignoring the code in RAM.
8726 To address this situation, OpenOCD provides the @code{xscale
8727 vector_table} command, which allows the user to explicitly write
8728 individual entries to either the high or low vector table stored in
8731 It is recommended to place a pc-relative indirect branch in the vector
8732 table, and put the branch destination somewhere in memory. Doing so
8733 makes sure the code in the vector table stays constant regardless of
8734 code layout in memory:
8737 ldr pc,[pc,#0x100-8]
8738 ldr pc,[pc,#0x100-8]
8739 ldr pc,[pc,#0x100-8]
8740 ldr pc,[pc,#0x100-8]
8741 ldr pc,[pc,#0x100-8]
8742 ldr pc,[pc,#0x100-8]
8743 ldr pc,[pc,#0x100-8]
8744 ldr pc,[pc,#0x100-8]
8746 .long real_reset_vector
8747 .long real_ui_handler
8748 .long real_swi_handler
8750 .long real_data_abort
8751 .long 0 /* unused */
8752 .long real_irq_handler
8753 .long real_fiq_handler
8756 Alternatively, you may choose to keep some or all of the mini-IC
8757 vector table entries synced with those written to memory by your
8758 system software. The mini-IC can not be modified while the processor
8759 is executing, but for each vector table entry not previously defined
8760 using the @code{xscale vector_table} command, OpenOCD will copy the
8761 value from memory to the mini-IC every time execution resumes from a
8762 halt. This is done for both high and low vector tables (although the
8763 table not in use may not be mapped to valid memory, and in this case
8764 that copy operation will silently fail). This means that you will
8765 need to briefly halt execution at some strategic point during system
8766 start-up; e.g., after the software has initialized the vector table,
8767 but before exceptions are enabled. A breakpoint can be used to
8768 accomplish this once the appropriate location in the start-up code has
8769 been identified. A watchpoint over the vector table region is helpful
8770 in finding the location if you're not sure. Note that the same
8771 situation exists any time the vector table is modified by the system
8774 The debug handler must be placed somewhere in the address space using
8775 the @code{xscale debug_handler} command. The allowed locations for the
8776 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
8777 0xfffff800). The default value is 0xfe000800.
8779 XScale has resources to support two hardware breakpoints and two
8780 watchpoints. However, the following restrictions on watchpoint
8781 functionality apply: (1) the value and mask arguments to the @code{wp}
8782 command are not supported, (2) the watchpoint length must be a
8783 power of two and not less than four, and can not be greater than the
8784 watchpoint address, and (3) a watchpoint with a length greater than
8785 four consumes all the watchpoint hardware resources. This means that
8786 at any one time, you can have enabled either two watchpoints with a
8787 length of four, or one watchpoint with a length greater than four.
8789 These commands are available to XScale based CPUs,
8790 which are implementations of the ARMv5TE architecture.
8792 @deffn Command {xscale analyze_trace}
8793 Displays the contents of the trace buffer.
8796 @deffn Command {xscale cache_clean_address} address
8797 Changes the address used when cleaning the data cache.
8800 @deffn Command {xscale cache_info}
8801 Displays information about the CPU caches.
8804 @deffn Command {xscale cp15} regnum [value]
8805 Display cp15 register @var{regnum};
8806 else if a @var{value} is provided, that value is written to that register.
8809 @deffn Command {xscale debug_handler} target address
8810 Changes the address used for the specified target's debug handler.
8813 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
8814 Enables or disable the CPU's data cache.
8817 @deffn Command {xscale dump_trace} filename
8818 Dumps the raw contents of the trace buffer to @file{filename}.
8821 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
8822 Enables or disable the CPU's instruction cache.
8825 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
8826 Enables or disable the CPU's memory management unit.
8829 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
8830 Displays the trace buffer status, after optionally
8831 enabling or disabling the trace buffer
8832 and modifying how it is emptied.
8835 @deffn Command {xscale trace_image} filename [offset [type]]
8836 Opens a trace image from @file{filename}, optionally rebasing
8837 its segment addresses by @var{offset}.
8838 The image @var{type} may be one of
8839 @option{bin} (binary), @option{ihex} (Intel hex),
8840 @option{elf} (ELF file), @option{s19} (Motorola s19),
8841 @option{mem}, or @option{builder}.
8844 @anchor{xscalevectorcatch}
8845 @deffn Command {xscale vector_catch} [mask]
8846 @cindex vector_catch
8847 Display a bitmask showing the hardware vectors to catch.
8848 If the optional parameter is provided, first set the bitmask to that value.
8850 The mask bits correspond with bit 16..23 in the DCSR:
8853 0x02 Trap Undefined Instructions
8854 0x04 Trap Software Interrupt
8855 0x08 Trap Prefetch Abort
8856 0x10 Trap Data Abort
8863 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
8864 @cindex vector_table
8866 Set an entry in the mini-IC vector table. There are two tables: one for
8867 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
8868 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
8869 points to the debug handler entry and can not be overwritten.
8870 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
8872 Without arguments, the current settings are displayed.
8876 @section ARMv6 Architecture
8879 @subsection ARM11 specific commands
8882 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
8883 Displays the value of the memwrite burst-enable flag,
8884 which is enabled by default.
8885 If a boolean parameter is provided, first assigns that flag.
8886 Burst writes are only used for memory writes larger than 1 word.
8887 They improve performance by assuming that the CPU has read each data
8888 word over JTAG and completed its write before the next word arrives,
8889 instead of polling for a status flag to verify that completion.
8890 This is usually safe, because JTAG runs much slower than the CPU.
8893 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
8894 Displays the value of the memwrite error_fatal flag,
8895 which is enabled by default.
8896 If a boolean parameter is provided, first assigns that flag.
8897 When set, certain memory write errors cause earlier transfer termination.
8900 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
8901 Displays the value of the flag controlling whether
8902 IRQs are enabled during single stepping;
8903 they are disabled by default.
8904 If a boolean parameter is provided, first assigns that.
8907 @deffn Command {arm11 vcr} [value]
8908 @cindex vector_catch
8909 Displays the value of the @emph{Vector Catch Register (VCR)},
8910 coprocessor 14 register 7.
8911 If @var{value} is defined, first assigns that.
8913 Vector Catch hardware provides dedicated breakpoints
8914 for certain hardware events.
8915 The specific bit values are core-specific (as in fact is using
8916 coprocessor 14 register 7 itself) but all current ARM11
8917 cores @emph{except the ARM1176} use the same six bits.
8920 @section ARMv7 and ARMv8 Architecture
8924 @subsection ARMv7-A specific commands
8927 @deffn Command {cortex_a cache_info}
8928 display information about target caches
8931 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
8932 Work around issues with software breakpoints when the program text is
8933 mapped read-only by the operating system. This option sets the CP15 DACR
8934 to "all-manager" to bypass MMU permission checks on memory access.
8938 @deffn Command {cortex_a dbginit}
8939 Initialize core debug
8940 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8943 @deffn Command {cortex_a smp_off}
8947 @deffn Command {cortex_a smp_on}
8951 @deffn Command {cortex_a smp_gdb} [core_id]
8952 Display/set the current core displayed in GDB
8955 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
8956 Selects whether interrupts will be processed when single stepping
8959 @deffn Command {cache_config l2x} [base way]
8963 @deffn Command {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
8964 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
8965 memory location @var{address}. When dumping the table from @var{address}, print at most
8966 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
8967 possible (4096) entries are printed.
8970 @subsection ARMv7-R specific commands
8973 @deffn Command {cortex_r dbginit}
8974 Initialize core debug
8975 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8978 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
8979 Selects whether interrupts will be processed when single stepping
8983 @subsection ARMv7-M specific commands
8991 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
8992 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
8993 @var{TRACECLKIN_freq} [@var{trace_freq}]))
8995 ARMv7-M architecture provides several modules to generate debugging
8996 information internally (ITM, DWT and ETM). Their output is directed
8997 through TPIU to be captured externally either on an SWO pin (this
8998 configuration is called SWV) or on a synchronous parallel trace port.
9000 This command configures the TPIU module of the target and, if internal
9001 capture mode is selected, starts to capture trace output by using the
9002 debugger adapter features.
9004 Some targets require additional actions to be performed in the
9005 @b{trace-config} handler for trace port to be activated.
9009 @item @option{disable} disable TPIU handling;
9010 @item @option{external} configure TPIU to let user capture trace
9011 output externally (with an additional UART or logic analyzer hardware);
9012 @item @option{internal @var{filename}} configure TPIU and debug adapter to
9013 gather trace data and append it to @var{filename} (which can be
9014 either a regular file or a named pipe);
9015 @item @option{internal -} configure TPIU and debug adapter to
9016 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
9017 @item @option{sync @var{port_width}} use synchronous parallel trace output
9018 mode, and set port width to @var{port_width};
9019 @item @option{manchester} use asynchronous SWO mode with Manchester
9021 @item @option{uart} use asynchronous SWO mode with NRZ (same as
9022 regular UART 8N1) coding;
9023 @item @var{formatter_enable} is @option{on} or @option{off} to enable
9024 or disable TPIU formatter which needs to be used when both ITM and ETM
9025 data is to be output via SWO;
9026 @item @var{TRACECLKIN_freq} this should be specified to match target's
9027 current TRACECLKIN frequency (usually the same as HCLK);
9028 @item @var{trace_freq} trace port frequency. Can be omitted in
9029 internal mode to let the adapter driver select the maximum supported
9035 @item STM32L152 board is programmed with an application that configures
9036 PLL to provide core clock with 24MHz frequency; to use ITM output it's
9039 #include <libopencm3/cm3/itm.h>
9044 (the most obvious way is to use the first stimulus port for printf,
9045 for that this ITM_STIM8 assignment can be used inside _write(); to make it
9046 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
9047 ITM_STIM_FIFOREADY));});
9048 @item An FT2232H UART is connected to the SWO pin of the board;
9049 @item Commands to configure UART for 12MHz baud rate:
9051 $ setserial /dev/ttyUSB1 spd_cust divisor 5
9052 $ stty -F /dev/ttyUSB1 38400
9054 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
9055 baud with our custom divisor to get 12MHz)
9056 @item @code{itmdump -f /dev/ttyUSB1 -d1}
9057 @item OpenOCD invocation line:
9059 openocd -f interface/stlink.cfg \
9060 -c "transport select hla_swd" \
9061 -f target/stm32l1.cfg \
9062 -c "tpiu config external uart off 24000000 12000000"
9067 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
9068 Enable or disable trace output for ITM stimulus @var{port} (counting
9069 from 0). Port 0 is enabled on target creation automatically.
9072 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
9073 Enable or disable trace output for all ITM stimulus ports.
9076 @subsection Cortex-M specific commands
9079 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
9080 Control masking (disabling) interrupts during target step/resume.
9082 The @option{auto} option handles interrupts during stepping in a way that they
9083 get served but don't disturb the program flow. The step command first allows
9084 pending interrupt handlers to execute, then disables interrupts and steps over
9085 the next instruction where the core was halted. After the step interrupts
9086 are enabled again. If the interrupt handlers don't complete within 500ms,
9087 the step command leaves with the core running.
9089 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
9090 option. If no breakpoint is available at the time of the step, then the step
9091 is taken with interrupts enabled, i.e. the same way the @option{off} option
9094 Default is @option{auto}.
9097 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
9098 @cindex vector_catch
9099 Vector Catch hardware provides dedicated breakpoints
9100 for certain hardware events.
9102 Parameters request interception of
9103 @option{all} of these hardware event vectors,
9104 @option{none} of them,
9105 or one or more of the following:
9106 @option{hard_err} for a HardFault exception;
9107 @option{mm_err} for a MemManage exception;
9108 @option{bus_err} for a BusFault exception;
9111 @option{chk_err}, or
9112 @option{nocp_err} for various UsageFault exceptions; or
9114 If NVIC setup code does not enable them,
9115 MemManage, BusFault, and UsageFault exceptions
9116 are mapped to HardFault.
9117 UsageFault checks for
9118 divide-by-zero and unaligned access
9119 must also be explicitly enabled.
9121 This finishes by listing the current vector catch configuration.
9124 @deffn Command {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
9125 Control reset handling if hardware srst is not fitted
9126 @xref{reset_config,,reset_config}.
9129 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
9130 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
9133 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
9134 This however has the disadvantage of only resetting the core, all peripherals
9135 are unaffected. A solution would be to use a @code{reset-init} event handler
9136 to manually reset the peripherals.
9137 @xref{targetevents,,Target Events}.
9139 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
9143 @subsection ARMv8-A specific commands
9147 @deffn Command {aarch64 cache_info}
9148 Display information about target caches
9151 @deffn Command {aarch64 dbginit}
9152 This command enables debugging by clearing the OS Lock and sticky power-down and reset
9153 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
9154 target code relies on. In a configuration file, the command would typically be called from a
9155 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
9156 However, normally it is not necessary to use the command at all.
9159 @deffn Command {aarch64 smp_on|smp_off}
9160 Enable and disable SMP handling. The state of SMP handling influences the way targets in an SMP group
9161 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
9162 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
9163 group. With SMP handling disabled, all targets need to be treated individually.
9166 @deffn Command {aarch64 maskisr} [@option{on}|@option{off}]
9167 Selects whether interrupts will be processed when single stepping. The default configuration is
9171 @section EnSilica eSi-RISC Architecture
9173 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
9174 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
9176 @subsection eSi-RISC Configuration
9178 @deffn Command {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
9179 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
9180 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
9183 @deffn Command {esirisc hwdc} (@option{all}|@option{none}|mask ...)
9184 Configure hardware debug control. The HWDC register controls which exceptions return
9185 control back to the debugger. Possible masks are @option{all}, @option{none},
9186 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
9187 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
9190 @subsection eSi-RISC Operation
9192 @deffn Command {esirisc flush_caches}
9193 Flush instruction and data caches. This command requires that the target is halted
9194 when the command is issued and configured with an instruction or data cache.
9197 @subsection eSi-Trace Configuration
9199 eSi-RISC targets may be configured with support for instruction tracing. Trace
9200 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
9201 is typically employed to move trace data off-device using a high-speed
9202 peripheral (eg. SPI). Collected trace data is encoded in one of three different
9203 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
9204 fifo} must be issued along with @command{esirisc trace format} before trace data
9207 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
9208 needed, collected trace data can be dumped to a file and processed by external
9212 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
9213 for this issue is to configure DMA to copy trace data to an in-memory buffer,
9214 which can then be passed to the @command{esirisc trace analyze} and
9215 @command{esirisc trace dump} commands.
9217 It is possible to corrupt trace data when using a FIFO if the peripheral
9218 responsible for draining data from the FIFO is not fast enough. This can be
9219 managed by enabling flow control, however this can impact timing-sensitive
9220 software operation on the CPU.
9223 @deffn Command {esirisc trace buffer} address size [@option{wrap}]
9224 Configure trace buffer using the provided address and size. If the @option{wrap}
9225 option is specified, trace collection will continue once the end of the buffer
9226 is reached. By default, wrap is disabled.
9229 @deffn Command {esirisc trace fifo} address
9230 Configure trace FIFO using the provided address.
9233 @deffn Command {esirisc trace flow_control} (@option{enable}|@option{disable})
9234 Enable or disable stalling the CPU to collect trace data. By default, flow
9235 control is disabled.
9238 @deffn Command {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
9239 Configure trace format and number of PC bits to be captured. @option{pc_bits}
9240 must be within 1 and 31 as the LSB is not collected. If external tooling is used
9241 to analyze collected trace data, these values must match.
9243 Supported trace formats:
9245 @item @option{full} capture full trace data, allowing execution history and
9246 timing to be determined.
9247 @item @option{branch} capture taken branch instructions and branch target
9249 @item @option{icache} capture instruction cache misses.
9253 @deffn Command {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
9254 Configure trigger start condition using the provided start data and mask. A
9255 brief description of each condition is provided below; for more detail on how
9256 these values are used, see the eSi-RISC Architecture Manual.
9258 Supported conditions:
9260 @item @option{none} manual tracing (see @command{esirisc trace start}).
9261 @item @option{pc} start tracing if the PC matches start data and mask.
9262 @item @option{load} start tracing if the effective address of a load
9263 instruction matches start data and mask.
9264 @item @option{store} start tracing if the effective address of a store
9265 instruction matches start data and mask.
9266 @item @option{exception} start tracing if the EID of an exception matches start
9268 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
9269 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
9270 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
9271 @item @option{high} start tracing when an external signal is a logical high.
9272 @item @option{low} start tracing when an external signal is a logical low.
9276 @deffn Command {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
9277 Configure trigger stop condition using the provided stop data and mask. A brief
9278 description of each condition is provided below; for more detail on how these
9279 values are used, see the eSi-RISC Architecture Manual.
9281 Supported conditions:
9283 @item @option{none} manual tracing (see @command{esirisc trace stop}).
9284 @item @option{pc} stop tracing if the PC matches stop data and mask.
9285 @item @option{load} stop tracing if the effective address of a load
9286 instruction matches stop data and mask.
9287 @item @option{store} stop tracing if the effective address of a store
9288 instruction matches stop data and mask.
9289 @item @option{exception} stop tracing if the EID of an exception matches stop
9291 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
9292 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
9293 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
9297 @deffn Command {esirisc trace trigger delay} (@option{trigger}) [cycles]
9298 Configure trigger start/stop delay in clock cycles.
9302 @item @option{none} no delay to start or stop collection.
9303 @item @option{start} delay @option{cycles} after trigger to start collection.
9304 @item @option{stop} delay @option{cycles} after trigger to stop collection.
9305 @item @option{both} delay @option{cycles} after both triggers to start or stop
9310 @subsection eSi-Trace Operation
9312 @deffn Command {esirisc trace init}
9313 Initialize trace collection. This command must be called any time the
9314 configuration changes. If an trace buffer has been configured, the contents will
9315 be overwritten when trace collection starts.
9318 @deffn Command {esirisc trace info}
9319 Display trace configuration.
9322 @deffn Command {esirisc trace status}
9323 Display trace collection status.
9326 @deffn Command {esirisc trace start}
9327 Start manual trace collection.
9330 @deffn Command {esirisc trace stop}
9331 Stop manual trace collection.
9334 @deffn Command {esirisc trace analyze} [address size]
9335 Analyze collected trace data. This command may only be used if a trace buffer
9336 has been configured. If a trace FIFO has been configured, trace data must be
9337 copied to an in-memory buffer identified by the @option{address} and
9338 @option{size} options using DMA.
9341 @deffn Command {esirisc trace dump} [address size] @file{filename}
9342 Dump collected trace data to file. This command may only be used if a trace
9343 buffer has been configured. If a trace FIFO has been configured, trace data must
9344 be copied to an in-memory buffer identified by the @option{address} and
9345 @option{size} options using DMA.
9348 @deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
9349 Cause @command{$target_name} to halt when an exception is taken. Any combination of
9350 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
9351 @command{$target_name} will halt before taking the exception. In order to resume
9352 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
9353 Issuing the command without options prints the current configuration.
9356 @section Intel Architecture
9358 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
9359 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
9360 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
9361 software debug and the CLTAP is used for SoC level operations.
9362 Useful docs are here: https://communities.intel.com/community/makers/documentation
9364 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
9365 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
9366 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
9369 @subsection x86 32-bit specific commands
9370 The three main address spaces for x86 are memory, I/O and configuration space.
9371 These commands allow a user to read and write to the 64Kbyte I/O address space.
9373 @deffn Command {x86_32 idw} address
9374 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
9377 @deffn Command {x86_32 idh} address
9378 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
9381 @deffn Command {x86_32 idb} address
9382 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
9385 @deffn Command {x86_32 iww} address
9386 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
9389 @deffn Command {x86_32 iwh} address
9390 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
9393 @deffn Command {x86_32 iwb} address
9394 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
9397 @section OpenRISC Architecture
9399 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
9400 configured with any of the TAP / Debug Unit available.
9402 @subsection TAP and Debug Unit selection commands
9403 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
9404 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
9406 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
9407 Select between the Advanced Debug Interface and the classic one.
9409 An option can be passed as a second argument to the debug unit.
9411 When using the Advanced Debug Interface, option = 1 means the RTL core is
9412 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
9413 between bytes while doing read or write bursts.
9416 @subsection Registers commands
9417 @deffn Command {addreg} [name] [address] [feature] [reg_group]
9418 Add a new register in the cpu register list. This register will be
9419 included in the generated target descriptor file.
9421 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
9423 @strong{[reg_group]} can be anything. The default register list defines "system",
9424 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
9429 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
9434 @deffn Command {readgroup} (@option{group})
9435 Display all registers in @emph{group}.
9437 @emph{group} can be "system",
9438 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
9439 "timer" or any new group created with addreg command.
9442 @section RISC-V Architecture
9444 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
9445 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
9446 harts. (It's possible to increase this limit to 1024 by changing
9447 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
9448 Debug Specification, but there is also support for legacy targets that
9449 implement version 0.11.
9451 @subsection RISC-V Terminology
9453 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
9454 another hart, or may be a separate core. RISC-V treats those the same, and
9455 OpenOCD exposes each hart as a separate core.
9457 @subsection RISC-V Debug Configuration Commands
9459 @deffn Command {riscv expose_csrs} n0[-m0][,n1[-m1]]...
9460 Configure a list of inclusive ranges for CSRs to expose in addition to the
9461 standard ones. This must be executed before `init`.
9463 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
9464 and then only if the corresponding extension appears to be implemented. This
9465 command can be used if OpenOCD gets this wrong, or a target implements custom
9469 @deffn Command {riscv set_command_timeout_sec} [seconds]
9470 Set the wall-clock timeout (in seconds) for individual commands. The default
9471 should work fine for all but the slowest targets (eg. simulators).
9474 @deffn Command {riscv set_reset_timeout_sec} [seconds]
9475 Set the maximum time to wait for a hart to come out of reset after reset is
9479 @deffn Command {riscv set_scratch_ram} none|[address]
9480 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
9481 This is used to access 64-bit floating point registers on 32-bit targets.
9484 @deffn Command {riscv set_prefer_sba} on|off
9485 When on, prefer to use System Bus Access to access memory. When off, prefer to
9486 use the Program Buffer to access memory.
9489 @subsection RISC-V Authentication Commands
9491 The following commands can be used to authenticate to a RISC-V system. Eg. a
9492 trivial challenge-response protocol could be implemented as follows in a
9493 configuration file, immediately following @command{init}:
9495 set challenge [ocd_riscv authdata_read]
9496 riscv authdata_write [expr $challenge + 1]
9499 @deffn Command {riscv authdata_read}
9500 Return the 32-bit value read from authdata. Note that to get read value back in
9501 a TCL script, it needs to be invoked as @command{ocd_riscv authdata_read}.
9504 @deffn Command {riscv authdata_write} value
9505 Write the 32-bit value to authdata.
9508 @subsection RISC-V DMI Commands
9510 The following commands allow direct access to the Debug Module Interface, which
9511 can be used to interact with custom debug features.
9513 @deffn Command {riscv dmi_read}
9514 Perform a 32-bit DMI read at address, returning the value. Note that to get
9515 read value back in a TCL script, it needs to be invoked as @command{ocd_riscv
9519 @deffn Command {riscv dmi_write} address value
9520 Perform a 32-bit DMI write of value at address.
9523 @anchor{softwaredebugmessagesandtracing}
9524 @section Software Debug Messages and Tracing
9525 @cindex Linux-ARM DCC support
9529 OpenOCD can process certain requests from target software, when
9530 the target uses appropriate libraries.
9531 The most powerful mechanism is semihosting, but there is also
9532 a lighter weight mechanism using only the DCC channel.
9534 Currently @command{target_request debugmsgs}
9535 is supported only for @option{arm7_9} and @option{cortex_m} cores.
9536 These messages are received as part of target polling, so
9537 you need to have @command{poll on} active to receive them.
9538 They are intrusive in that they will affect program execution
9539 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
9541 See @file{libdcc} in the contrib dir for more details.
9542 In addition to sending strings, characters, and
9543 arrays of various size integers from the target,
9544 @file{libdcc} also exports a software trace point mechanism.
9545 The target being debugged may
9546 issue trace messages which include a 24-bit @dfn{trace point} number.
9547 Trace point support includes two distinct mechanisms,
9548 each supported by a command:
9551 @item @emph{History} ... A circular buffer of trace points
9552 can be set up, and then displayed at any time.
9553 This tracks where code has been, which can be invaluable in
9554 finding out how some fault was triggered.
9556 The buffer may overflow, since it collects records continuously.
9557 It may be useful to use some of the 24 bits to represent a
9558 particular event, and other bits to hold data.
9560 @item @emph{Counting} ... An array of counters can be set up,
9561 and then displayed at any time.
9562 This can help establish code coverage and identify hot spots.
9564 The array of counters is directly indexed by the trace point
9565 number, so trace points with higher numbers are not counted.
9568 Linux-ARM kernels have a ``Kernel low-level debugging
9569 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
9570 depends on CONFIG_DEBUG_LL) which uses this mechanism to
9571 deliver messages before a serial console can be activated.
9572 This is not the same format used by @file{libdcc}.
9573 Other software, such as the U-Boot boot loader, sometimes
9574 does the same thing.
9576 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
9577 Displays current handling of target DCC message requests.
9578 These messages may be sent to the debugger while the target is running.
9579 The optional @option{enable} and @option{charmsg} parameters
9580 both enable the messages, while @option{disable} disables them.
9582 With @option{charmsg} the DCC words each contain one character,
9583 as used by Linux with CONFIG_DEBUG_ICEDCC;
9584 otherwise the libdcc format is used.
9587 @deffn Command {trace history} [@option{clear}|count]
9588 With no parameter, displays all the trace points that have triggered
9589 in the order they triggered.
9590 With the parameter @option{clear}, erases all current trace history records.
9591 With a @var{count} parameter, allocates space for that many
9595 @deffn Command {trace point} [@option{clear}|identifier]
9596 With no parameter, displays all trace point identifiers and how many times
9597 they have been triggered.
9598 With the parameter @option{clear}, erases all current trace point counters.
9599 With a numeric @var{identifier} parameter, creates a new a trace point counter
9600 and associates it with that identifier.
9602 @emph{Important:} The identifier and the trace point number
9603 are not related except by this command.
9604 These trace point numbers always start at zero (from server startup,
9605 or after @command{trace point clear}) and count up from there.
9610 @chapter JTAG Commands
9611 @cindex JTAG Commands
9612 Most general purpose JTAG commands have been presented earlier.
9613 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
9614 Lower level JTAG commands, as presented here,
9615 may be needed to work with targets which require special
9616 attention during operations such as reset or initialization.
9618 To use these commands you will need to understand some
9619 of the basics of JTAG, including:
9622 @item A JTAG scan chain consists of a sequence of individual TAP
9623 devices such as a CPUs.
9624 @item Control operations involve moving each TAP through the same
9625 standard state machine (in parallel)
9626 using their shared TMS and clock signals.
9627 @item Data transfer involves shifting data through the chain of
9628 instruction or data registers of each TAP, writing new register values
9629 while the reading previous ones.
9630 @item Data register sizes are a function of the instruction active in
9631 a given TAP, while instruction register sizes are fixed for each TAP.
9632 All TAPs support a BYPASS instruction with a single bit data register.
9633 @item The way OpenOCD differentiates between TAP devices is by
9634 shifting different instructions into (and out of) their instruction
9638 @section Low Level JTAG Commands
9640 These commands are used by developers who need to access
9641 JTAG instruction or data registers, possibly controlling
9642 the order of TAP state transitions.
9643 If you're not debugging OpenOCD internals, or bringing up a
9644 new JTAG adapter or a new type of TAP device (like a CPU or
9645 JTAG router), you probably won't need to use these commands.
9646 In a debug session that doesn't use JTAG for its transport protocol,
9647 these commands are not available.
9649 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
9650 Loads the data register of @var{tap} with a series of bit fields
9651 that specify the entire register.
9652 Each field is @var{numbits} bits long with
9653 a numeric @var{value} (hexadecimal encouraged).
9654 The return value holds the original value of each
9657 For example, a 38 bit number might be specified as one
9658 field of 32 bits then one of 6 bits.
9659 @emph{For portability, never pass fields which are more
9660 than 32 bits long. Many OpenOCD implementations do not
9661 support 64-bit (or larger) integer values.}
9663 All TAPs other than @var{tap} must be in BYPASS mode.
9664 The single bit in their data registers does not matter.
9666 When @var{tap_state} is specified, the JTAG state machine is left
9668 For example @sc{drpause} might be specified, so that more
9669 instructions can be issued before re-entering the @sc{run/idle} state.
9670 If the end state is not specified, the @sc{run/idle} state is entered.
9673 OpenOCD does not record information about data register lengths,
9674 so @emph{it is important that you get the bit field lengths right}.
9675 Remember that different JTAG instructions refer to different
9676 data registers, which may have different lengths.
9677 Moreover, those lengths may not be fixed;
9678 the SCAN_N instruction can change the length of
9679 the register accessed by the INTEST instruction
9680 (by connecting a different scan chain).
9684 @deffn Command {flush_count}
9685 Returns the number of times the JTAG queue has been flushed.
9686 This may be used for performance tuning.
9688 For example, flushing a queue over USB involves a
9689 minimum latency, often several milliseconds, which does
9690 not change with the amount of data which is written.
9691 You may be able to identify performance problems by finding
9692 tasks which waste bandwidth by flushing small transfers too often,
9693 instead of batching them into larger operations.
9696 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
9697 For each @var{tap} listed, loads the instruction register
9698 with its associated numeric @var{instruction}.
9699 (The number of bits in that instruction may be displayed
9700 using the @command{scan_chain} command.)
9701 For other TAPs, a BYPASS instruction is loaded.
9703 When @var{tap_state} is specified, the JTAG state machine is left
9705 For example @sc{irpause} might be specified, so the data register
9706 can be loaded before re-entering the @sc{run/idle} state.
9707 If the end state is not specified, the @sc{run/idle} state is entered.
9710 OpenOCD currently supports only a single field for instruction
9711 register values, unlike data register values.
9712 For TAPs where the instruction register length is more than 32 bits,
9713 portable scripts currently must issue only BYPASS instructions.
9717 @deffn Command {jtag_reset} trst srst
9718 Set values of reset signals.
9719 The @var{trst} and @var{srst} parameter values may be
9720 @option{0}, indicating that reset is inactive (pulled or driven high),
9721 or @option{1}, indicating it is active (pulled or driven low).
9722 The @command{reset_config} command should already have been used
9723 to configure how the board and JTAG adapter treat these two
9724 signals, and to say if either signal is even present.
9725 @xref{Reset Configuration}.
9727 Note that TRST is specially handled.
9728 It actually signifies JTAG's @sc{reset} state.
9729 So if the board doesn't support the optional TRST signal,
9730 or it doesn't support it along with the specified SRST value,
9731 JTAG reset is triggered with TMS and TCK signals
9732 instead of the TRST signal.
9733 And no matter how that JTAG reset is triggered, once
9734 the scan chain enters @sc{reset} with TRST inactive,
9735 TAP @code{post-reset} events are delivered to all TAPs
9736 with handlers for that event.
9739 @deffn Command {pathmove} start_state [next_state ...]
9740 Start by moving to @var{start_state}, which
9741 must be one of the @emph{stable} states.
9742 Unless it is the only state given, this will often be the
9743 current state, so that no TCK transitions are needed.
9744 Then, in a series of single state transitions
9745 (conforming to the JTAG state machine) shift to
9746 each @var{next_state} in sequence, one per TCK cycle.
9747 The final state must also be stable.
9750 @deffn Command {runtest} @var{num_cycles}
9751 Move to the @sc{run/idle} state, and execute at least
9752 @var{num_cycles} of the JTAG clock (TCK).
9753 Instructions often need some time
9754 to execute before they take effect.
9757 @c tms_sequence (short|long)
9758 @c ... temporary, debug-only, other than USBprog bug workaround...
9760 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
9761 Verify values captured during @sc{ircapture} and returned
9762 during IR scans. Default is enabled, but this can be
9763 overridden by @command{verify_jtag}.
9764 This flag is ignored when validating JTAG chain configuration.
9767 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
9768 Enables verification of DR and IR scans, to help detect
9769 programming errors. For IR scans, @command{verify_ircapture}
9770 must also be enabled.
9774 @section TAP state names
9775 @cindex TAP state names
9777 The @var{tap_state} names used by OpenOCD in the @command{drscan},
9778 @command{irscan}, and @command{pathmove} commands are the same
9779 as those used in SVF boundary scan documents, except that
9780 SVF uses @sc{idle} instead of @sc{run/idle}.
9783 @item @b{RESET} ... @emph{stable} (with TMS high);
9784 acts as if TRST were pulsed
9785 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
9788 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
9789 through the data register
9791 @item @b{DRPAUSE} ... @emph{stable}; data register ready
9792 for update or more shifting
9797 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
9798 through the instruction register
9800 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
9801 for update or more shifting
9806 Note that only six of those states are fully ``stable'' in the
9807 face of TMS fixed (low except for @sc{reset})
9808 and a free-running JTAG clock. For all the
9809 others, the next TCK transition changes to a new state.
9812 @item From @sc{drshift} and @sc{irshift}, clock transitions will
9813 produce side effects by changing register contents. The values
9814 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
9815 may not be as expected.
9816 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
9817 choices after @command{drscan} or @command{irscan} commands,
9818 since they are free of JTAG side effects.
9819 @item @sc{run/idle} may have side effects that appear at non-JTAG
9820 levels, such as advancing the ARM9E-S instruction pipeline.
9821 Consult the documentation for the TAP(s) you are working with.
9824 @node Boundary Scan Commands
9825 @chapter Boundary Scan Commands
9827 One of the original purposes of JTAG was to support
9828 boundary scan based hardware testing.
9829 Although its primary focus is to support On-Chip Debugging,
9830 OpenOCD also includes some boundary scan commands.
9832 @section SVF: Serial Vector Format
9833 @cindex Serial Vector Format
9836 The Serial Vector Format, better known as @dfn{SVF}, is a
9837 way to represent JTAG test patterns in text files.
9838 In a debug session using JTAG for its transport protocol,
9839 OpenOCD supports running such test files.
9841 @deffn Command {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
9842 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
9843 This issues a JTAG reset (Test-Logic-Reset) and then
9844 runs the SVF script from @file{filename}.
9846 Arguments can be specified in any order; the optional dash doesn't
9847 affect their semantics.
9851 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
9852 specified by the SVF file with HIR, TIR, HDR and TDR commands;
9853 instead, calculate them automatically according to the current JTAG
9854 chain configuration, targeting @var{tapname};
9855 @item @option{[-]quiet} do not log every command before execution;
9856 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
9857 on the real interface;
9858 @item @option{[-]progress} enable progress indication;
9859 @item @option{[-]ignore_error} continue execution despite TDO check
9864 @section XSVF: Xilinx Serial Vector Format
9865 @cindex Xilinx Serial Vector Format
9868 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
9869 binary representation of SVF which is optimized for use with
9871 In a debug session using JTAG for its transport protocol,
9872 OpenOCD supports running such test files.
9874 @quotation Important
9875 Not all XSVF commands are supported.
9878 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
9879 This issues a JTAG reset (Test-Logic-Reset) and then
9880 runs the XSVF script from @file{filename}.
9881 When a @var{tapname} is specified, the commands are directed at
9883 When @option{virt2} is specified, the @sc{xruntest} command counts
9884 are interpreted as TCK cycles instead of microseconds.
9885 Unless the @option{quiet} option is specified,
9886 messages are logged for comments and some retries.
9889 The OpenOCD sources also include two utility scripts
9890 for working with XSVF; they are not currently installed
9891 after building the software.
9892 You may find them useful:
9895 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
9896 syntax understood by the @command{xsvf} command; see notes below.
9897 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
9898 understands the OpenOCD extensions.
9901 The input format accepts a handful of non-standard extensions.
9902 These include three opcodes corresponding to SVF extensions
9903 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
9904 two opcodes supporting a more accurate translation of SVF
9905 (XTRST, XWAITSTATE).
9906 If @emph{xsvfdump} shows a file is using those opcodes, it
9907 probably will not be usable with other XSVF tools.
9910 @node Utility Commands
9911 @chapter Utility Commands
9912 @cindex Utility Commands
9914 @section RAM testing
9917 There is often a need to stress-test random access memory (RAM) for
9918 errors. OpenOCD comes with a Tcl implementation of well-known memory
9919 testing procedures allowing the detection of all sorts of issues with
9920 electrical wiring, defective chips, PCB layout and other common
9923 To use them, you usually need to initialise your RAM controller first;
9924 consult your SoC's documentation to get the recommended list of
9925 register operations and translate them to the corresponding
9926 @command{mww}/@command{mwb} commands.
9928 Load the memory testing functions with
9931 source [find tools/memtest.tcl]
9934 to get access to the following facilities:
9936 @deffn Command {memTestDataBus} address
9937 Test the data bus wiring in a memory region by performing a walking
9938 1's test at a fixed address within that region.
9941 @deffn Command {memTestAddressBus} baseaddress size
9942 Perform a walking 1's test on the relevant bits of the address and
9943 check for aliasing. This test will find single-bit address failures
9944 such as stuck-high, stuck-low, and shorted pins.
9947 @deffn Command {memTestDevice} baseaddress size
9948 Test the integrity of a physical memory device by performing an
9949 increment/decrement test over the entire region. In the process every
9950 storage bit in the device is tested as zero and as one.
9953 @deffn Command {runAllMemTests} baseaddress size
9954 Run all of the above tests over a specified memory region.
9957 @section Firmware recovery helpers
9958 @cindex Firmware recovery
9960 OpenOCD includes an easy-to-use script to facilitate mass-market
9961 devices recovery with JTAG.
9963 For quickstart instructions run:
9965 openocd -f tools/firmware-recovery.tcl -c firmware_help
9971 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
9972 be used to access files on PCs (either the developer's PC or some other PC).
9974 The way this works on the ZY1000 is to prefix a filename by
9975 "/tftp/ip/" and append the TFTP path on the TFTP
9976 server (tftpd). For example,
9979 load_image /tftp/10.0.0.96/c:\temp\abc.elf
9982 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
9983 if the file was hosted on the embedded host.
9985 In order to achieve decent performance, you must choose a TFTP server
9986 that supports a packet size bigger than the default packet size (512 bytes). There
9987 are numerous TFTP servers out there (free and commercial) and you will have to do
9988 a bit of googling to find something that fits your requirements.
9990 @node GDB and OpenOCD
9991 @chapter GDB and OpenOCD
9993 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
9994 to debug remote targets.
9995 Setting up GDB to work with OpenOCD can involve several components:
9998 @item The OpenOCD server support for GDB may need to be configured.
9999 @xref{gdbconfiguration,,GDB Configuration}.
10000 @item GDB's support for OpenOCD may need configuration,
10001 as shown in this chapter.
10002 @item If you have a GUI environment like Eclipse,
10003 that also will probably need to be configured.
10006 Of course, the version of GDB you use will need to be one which has
10007 been built to know about the target CPU you're using. It's probably
10008 part of the tool chain you're using. For example, if you are doing
10009 cross-development for ARM on an x86 PC, instead of using the native
10010 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
10011 if that's the tool chain used to compile your code.
10013 @section Connecting to GDB
10014 @cindex Connecting to GDB
10015 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
10016 instance GDB 6.3 has a known bug that produces bogus memory access
10017 errors, which has since been fixed; see
10018 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
10020 OpenOCD can communicate with GDB in two ways:
10024 A socket (TCP/IP) connection is typically started as follows:
10026 target remote localhost:3333
10028 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
10030 It is also possible to use the GDB extended remote protocol as follows:
10032 target extended-remote localhost:3333
10035 A pipe connection is typically started as follows:
10037 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
10039 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
10040 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
10041 session. log_output sends the log output to a file to ensure that the pipe is
10042 not saturated when using higher debug level outputs.
10045 To list the available OpenOCD commands type @command{monitor help} on the
10048 @section Sample GDB session startup
10050 With the remote protocol, GDB sessions start a little differently
10051 than they do when you're debugging locally.
10052 Here's an example showing how to start a debug session with a
10054 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
10055 Most programs would be written into flash (address 0) and run from there.
10058 $ arm-none-eabi-gdb example.elf
10059 (gdb) target remote localhost:3333
10060 Remote debugging using localhost:3333
10062 (gdb) monitor reset halt
10065 Loading section .vectors, size 0x100 lma 0x20000000
10066 Loading section .text, size 0x5a0 lma 0x20000100
10067 Loading section .data, size 0x18 lma 0x200006a0
10068 Start address 0x2000061c, load size 1720
10069 Transfer rate: 22 KB/sec, 573 bytes/write.
10075 You could then interrupt the GDB session to make the program break,
10076 type @command{where} to show the stack, @command{list} to show the
10077 code around the program counter, @command{step} through code,
10078 set breakpoints or watchpoints, and so on.
10080 @section Configuring GDB for OpenOCD
10082 OpenOCD supports the gdb @option{qSupported} packet, this enables information
10083 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
10084 packet size and the device's memory map.
10085 You do not need to configure the packet size by hand,
10086 and the relevant parts of the memory map should be automatically
10087 set up when you declare (NOR) flash banks.
10089 However, there are other things which GDB can't currently query.
10090 You may need to set those up by hand.
10091 As OpenOCD starts up, you will often see a line reporting
10095 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
10098 You can pass that information to GDB with these commands:
10101 set remote hardware-breakpoint-limit 6
10102 set remote hardware-watchpoint-limit 4
10105 With that particular hardware (Cortex-M3) the hardware breakpoints
10106 only work for code running from flash memory. Most other ARM systems
10107 do not have such restrictions.
10109 Rather than typing such commands interactively, you may prefer to
10110 save them in a file and have GDB execute them as it starts, perhaps
10111 using a @file{.gdbinit} in your project directory or starting GDB
10112 using @command{gdb -x filename}.
10114 @section Programming using GDB
10115 @cindex Programming using GDB
10116 @anchor{programmingusinggdb}
10118 By default the target memory map is sent to GDB. This can be disabled by
10119 the following OpenOCD configuration option:
10121 gdb_memory_map disable
10123 For this to function correctly a valid flash configuration must also be set
10124 in OpenOCD. For faster performance you should also configure a valid
10127 Informing GDB of the memory map of the target will enable GDB to protect any
10128 flash areas of the target and use hardware breakpoints by default. This means
10129 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
10130 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
10132 To view the configured memory map in GDB, use the GDB command @option{info mem}.
10133 All other unassigned addresses within GDB are treated as RAM.
10135 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
10136 This can be changed to the old behaviour by using the following GDB command
10138 set mem inaccessible-by-default off
10141 If @command{gdb_flash_program enable} is also used, GDB will be able to
10142 program any flash memory using the vFlash interface.
10144 GDB will look at the target memory map when a load command is given, if any
10145 areas to be programmed lie within the target flash area the vFlash packets
10148 If the target needs configuring before GDB programming, set target
10149 event gdb-flash-erase-start:
10151 $_TARGETNAME configure -event gdb-flash-erase-start BODY
10153 @xref{targetevents,,Target Events}, for other GDB programming related events.
10155 To verify any flash programming the GDB command @option{compare-sections}
10158 @section Using GDB as a non-intrusive memory inspector
10159 @cindex Using GDB as a non-intrusive memory inspector
10160 @anchor{gdbmeminspect}
10162 If your project controls more than a blinking LED, let's say a heavy industrial
10163 robot or an experimental nuclear reactor, stopping the controlling process
10164 just because you want to attach GDB is not a good option.
10166 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
10167 Though there is a possible setup where the target does not get stopped
10168 and GDB treats it as it were running.
10169 If the target supports background access to memory while it is running,
10170 you can use GDB in this mode to inspect memory (mainly global variables)
10171 without any intrusion of the target process.
10173 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
10174 Place following command after target configuration:
10176 $_TARGETNAME configure -event gdb-attach @{@}
10179 If any of installed flash banks does not support probe on running target,
10180 switch off gdb_memory_map:
10182 gdb_memory_map disable
10185 Ensure GDB is configured without interrupt-on-connect.
10186 Some GDB versions set it by default, some does not.
10188 set remote interrupt-on-connect off
10191 If you switched gdb_memory_map off, you may want to setup GDB memory map
10192 manually or issue @command{set mem inaccessible-by-default off}
10194 Now you can issue GDB command @command{target remote ...} and inspect memory
10195 of a running target. Do not use GDB commands @command{continue},
10196 @command{step} or @command{next} as they synchronize GDB with your target
10197 and GDB would require stopping the target to get the prompt back.
10199 Do not use this mode under an IDE like Eclipse as it caches values of
10200 previously shown varibles.
10202 @section RTOS Support
10203 @cindex RTOS Support
10204 @anchor{gdbrtossupport}
10206 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
10207 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
10209 @xref{Threads, Debugging Programs with Multiple Threads,
10210 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
10213 @* An example setup is below:
10216 $_TARGETNAME configure -rtos auto
10219 This will attempt to auto detect the RTOS within your application.
10221 Currently supported rtos's include:
10223 @item @option{eCos}
10224 @item @option{ThreadX}
10225 @item @option{FreeRTOS}
10226 @item @option{linux}
10227 @item @option{ChibiOS}
10228 @item @option{embKernel}
10230 @item @option{uCOS-III}
10231 @item @option{nuttx}
10232 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
10235 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
10236 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
10240 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
10241 @item ThreadX symbols
10242 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
10243 @item FreeRTOS symbols
10244 @c The following is taken from recent texinfo to provide compatibility
10245 @c with ancient versions that do not support @raggedright
10248 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
10249 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
10250 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
10251 uxCurrentNumberOfTasks, uxTopUsedPriority.
10255 @item linux symbols
10257 @item ChibiOS symbols
10258 rlist, ch_debug, chSysInit.
10259 @item embKernel symbols
10260 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
10261 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
10263 _mqx_kernel_data, MQX_init_struct.
10264 @item uC/OS-III symbols
10265 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
10266 @item nuttx symbols
10267 g_readytorun, g_tasklisttable
10270 For most RTOS supported the above symbols will be exported by default. However for
10271 some, eg. FreeRTOS and uC/OS-III, extra steps must be taken.
10273 These RTOSes may require additional OpenOCD-specific file to be linked
10274 along with the project:
10278 contrib/rtos-helpers/FreeRTOS-openocd.c
10280 contrib/rtos-helpers/uCOS-III-openocd.c
10283 @anchor{usingopenocdsmpwithgdb}
10284 @section Using OpenOCD SMP with GDB
10288 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
10289 ("hardware threads") in an SMP system as threads to GDB. With this extension,
10290 GDB can be used to inspect the state of an SMP system in a natural way.
10291 After halting the system, using the GDB command @command{info threads} will
10292 list the context of each active CPU core in the system. GDB's @command{thread}
10293 command can be used to switch the view to a different CPU core.
10294 The @command{step} and @command{stepi} commands can be used to step a specific core
10295 while other cores are free-running or remain halted, depending on the
10296 scheduler-locking mode configured in GDB.
10298 @section Legacy SMP core switching support
10300 This method is deprecated in favor of the @emph{hwthread} pseudo RTOS.
10303 For SMP support following GDB serial protocol packet have been defined :
10305 @item j - smp status request
10306 @item J - smp set request
10309 OpenOCD implements :
10311 @item @option{jc} packet for reading core id displayed by
10312 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
10313 @option{E01} for target not smp.
10314 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
10315 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
10316 for target not smp or @option{OK} on success.
10319 Handling of this packet within GDB can be done :
10321 @item by the creation of an internal variable (i.e @option{_core}) by mean
10322 of function allocate_computed_value allowing following GDB command.
10325 #Jc01 packet is sent
10327 #jc packet is sent and result is affected in $
10330 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
10331 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
10334 # toggle0 : force display of coreid 0
10340 # toggle1 : force display of coreid 1
10349 @node Tcl Scripting API
10350 @chapter Tcl Scripting API
10351 @cindex Tcl Scripting API
10352 @cindex Tcl scripts
10355 Tcl commands are stateless; e.g. the @command{telnet} command has
10356 a concept of currently active target, the Tcl API proc's take this sort
10357 of state information as an argument to each proc.
10359 There are three main types of return values: single value, name value
10360 pair list and lists.
10362 Name value pair. The proc 'foo' below returns a name/value pair
10366 > set foo(me) Duane
10367 > set foo(you) Oyvind
10368 > set foo(mouse) Micky
10369 > set foo(duck) Donald
10381 me Duane you Oyvind mouse Micky duck Donald
10384 Thus, to get the names of the associative array is easy:
10387 foreach { name value } [set foo] {
10388 puts "Name: $name, Value: $value"
10392 Lists returned should be relatively small. Otherwise, a range
10393 should be passed in to the proc in question.
10395 @section Internal low-level Commands
10397 By "low-level," we mean commands that a human would typically not
10400 Some low-level commands need to be prefixed with "ocd_"; e.g.
10401 @command{ocd_flash_banks}
10402 is the low-level API upon which @command{flash banks} is implemented.
10405 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
10407 Read memory and return as a Tcl array for script processing
10408 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
10410 Convert a Tcl array to memory locations and write the values
10411 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
10413 Return information about the flash banks
10415 @item @b{capture} <@var{command}>
10417 Run <@var{command}> and return full log output that was produced during
10418 its execution. Example:
10421 > capture "reset init"
10426 OpenOCD commands can consist of two words, e.g. "flash banks". The
10427 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
10428 called "flash_banks".
10430 @section OpenOCD specific Global Variables
10432 Real Tcl has ::tcl_platform(), and platform::identify, and many other
10433 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
10434 holds one of the following values:
10437 @item @b{cygwin} Running under Cygwin
10438 @item @b{darwin} Darwin (Mac-OS) is the underlying operating system.
10439 @item @b{freebsd} Running under FreeBSD
10440 @item @b{openbsd} Running under OpenBSD
10441 @item @b{netbsd} Running under NetBSD
10442 @item @b{linux} Linux is the underlying operating system
10443 @item @b{mingw32} Running under MingW32
10444 @item @b{winxx} Built using Microsoft Visual Studio
10445 @item @b{ecos} Running under eCos
10446 @item @b{other} Unknown, none of the above.
10449 Note: 'winxx' was chosen because today (March-2009) no distinction is made between Win32 and Win64.
10452 We should add support for a variable like Tcl variable
10453 @code{tcl_platform(platform)}, it should be called
10454 @code{jim_platform} (because it
10455 is jim, not real tcl).
10458 @section Tcl RPC server
10461 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
10462 commands and receive the results.
10464 To access it, your application needs to connect to a configured TCP port
10465 (see @command{tcl_port}). Then it can pass any string to the
10466 interpreter terminating it with @code{0x1a} and wait for the return
10467 value (it will be terminated with @code{0x1a} as well). This can be
10468 repeated as many times as desired without reopening the connection.
10470 Remember that most of the OpenOCD commands need to be prefixed with
10471 @code{ocd_} to get the results back. Sometimes you might also need the
10472 @command{capture} command.
10474 See @file{contrib/rpc_examples/} for specific client implementations.
10476 @section Tcl RPC server notifications
10477 @cindex RPC Notifications
10479 Notifications are sent asynchronously to other commands being executed over
10480 the RPC server, so the port must be polled continuously.
10482 Target event, state and reset notifications are emitted as Tcl associative arrays
10483 in the following format.
10486 type target_event event [event-name]
10487 type target_state state [state-name]
10488 type target_reset mode [reset-mode]
10491 @deffn {Command} tcl_notifications [on/off]
10492 Toggle output of target notifications to the current Tcl RPC server.
10493 Only available from the Tcl RPC server.
10498 @section Tcl RPC server trace output
10499 @cindex RPC trace output
10501 Trace data is sent asynchronously to other commands being executed over
10502 the RPC server, so the port must be polled continuously.
10504 Target trace data is emitted as a Tcl associative array in the following format.
10507 type target_trace data [trace-data-hex-encoded]
10510 @deffn {Command} tcl_trace [on/off]
10511 Toggle output of target trace data to the current Tcl RPC server.
10512 Only available from the Tcl RPC server.
10515 See an example application here:
10516 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
10525 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
10527 @cindex adaptive clocking
10530 In digital circuit design it is often referred to as ``clock
10531 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
10532 operating at some speed, your CPU target is operating at another.
10533 The two clocks are not synchronised, they are ``asynchronous''
10535 In order for the two to work together they must be synchronised
10536 well enough to work; JTAG can't go ten times faster than the CPU,
10537 for example. There are 2 basic options:
10540 Use a special "adaptive clocking" circuit to change the JTAG
10541 clock rate to match what the CPU currently supports.
10543 The JTAG clock must be fixed at some speed that's enough slower than
10544 the CPU clock that all TMS and TDI transitions can be detected.
10547 @b{Does this really matter?} For some chips and some situations, this
10548 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
10549 the CPU has no difficulty keeping up with JTAG.
10550 Startup sequences are often problematic though, as are other
10551 situations where the CPU clock rate changes (perhaps to save
10554 For example, Atmel AT91SAM chips start operation from reset with
10555 a 32kHz system clock. Boot firmware may activate the main oscillator
10556 and PLL before switching to a faster clock (perhaps that 500 MHz
10558 If you're using JTAG to debug that startup sequence, you must slow
10559 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
10560 JTAG can use a faster clock.
10562 Consider also debugging a 500MHz ARM926 hand held battery powered
10563 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
10564 clock, between keystrokes unless it has work to do. When would
10565 that 5 MHz JTAG clock be usable?
10567 @b{Solution #1 - A special circuit}
10569 In order to make use of this,
10570 your CPU, board, and JTAG adapter must all support the RTCK
10571 feature. Not all of them support this; keep reading!
10573 The RTCK ("Return TCK") signal in some ARM chips is used to help with
10574 this problem. ARM has a good description of the problem described at
10575 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
10576 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
10577 work? / how does adaptive clocking work?''.
10579 The nice thing about adaptive clocking is that ``battery powered hand
10580 held device example'' - the adaptiveness works perfectly all the
10581 time. One can set a break point or halt the system in the deep power
10582 down code, slow step out until the system speeds up.
10584 Note that adaptive clocking may also need to work at the board level,
10585 when a board-level scan chain has multiple chips.
10586 Parallel clock voting schemes are good way to implement this,
10587 both within and between chips, and can easily be implemented
10589 It's not difficult to have logic fan a module's input TCK signal out
10590 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
10591 back with the right polarity before changing the output RTCK signal.
10592 Texas Instruments makes some clock voting logic available
10593 for free (with no support) in VHDL form; see
10594 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
10596 @b{Solution #2 - Always works - but may be slower}
10598 Often this is a perfectly acceptable solution.
10600 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
10601 the target clock speed. But what that ``magic division'' is varies
10602 depending on the chips on your board.
10603 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
10604 ARM11 cores use an 8:1 division.
10605 @b{Xilinx rule of thumb} is 1/12 the clock speed.
10607 Note: most full speed FT2232 based JTAG adapters are limited to a
10608 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
10609 often support faster clock rates (and adaptive clocking).
10611 You can still debug the 'low power' situations - you just need to
10612 either use a fixed and very slow JTAG clock rate ... or else
10613 manually adjust the clock speed at every step. (Adjusting is painful
10614 and tedious, and is not always practical.)
10616 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
10617 have a special debug mode in your application that does a ``high power
10618 sleep''. If you are careful - 98% of your problems can be debugged
10621 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
10622 operation in your idle loops even if you don't otherwise change the CPU
10624 That operation gates the CPU clock, and thus the JTAG clock; which
10625 prevents JTAG access. One consequence is not being able to @command{halt}
10626 cores which are executing that @emph{wait for interrupt} operation.
10628 To set the JTAG frequency use the command:
10631 # Example: 1.234MHz
10636 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
10638 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
10639 around Windows filenames.
10652 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
10654 Make sure you have Cygwin installed, or at least a version of OpenOCD that
10655 claims to come with all the necessary DLLs. When using Cygwin, try launching
10656 OpenOCD from the Cygwin shell.
10658 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
10659 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
10660 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
10662 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
10663 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
10664 software breakpoints consume one of the two available hardware breakpoints.
10666 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
10668 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
10669 clock at the time you're programming the flash. If you've specified the crystal's
10670 frequency, make sure the PLL is disabled. If you've specified the full core speed
10671 (e.g. 60MHz), make sure the PLL is enabled.
10673 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
10674 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
10675 out while waiting for end of scan, rtck was disabled".
10677 Make sure your PC's parallel port operates in EPP mode. You might have to try several
10678 settings in your PC BIOS (ECP, EPP, and different versions of those).
10680 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
10681 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
10682 memory read caused data abort".
10684 The errors are non-fatal, and are the result of GDB trying to trace stack frames
10685 beyond the last valid frame. It might be possible to prevent this by setting up
10686 a proper "initial" stack frame, if you happen to know what exactly has to
10687 be done, feel free to add this here.
10689 @b{Simple:} In your startup code - push 8 registers of zeros onto the
10690 stack before calling main(). What GDB is doing is ``climbing'' the run
10691 time stack by reading various values on the stack using the standard
10692 call frame for the target. GDB keeps going - until one of 2 things
10693 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
10694 stackframes have been processed. By pushing zeros on the stack, GDB
10697 @b{Debugging Interrupt Service Routines} - In your ISR before you call
10698 your C code, do the same - artificially push some zeros onto the stack,
10699 remember to pop them off when the ISR is done.
10701 @b{Also note:} If you have a multi-threaded operating system, they
10702 often do not @b{in the intrest of saving memory} waste these few
10706 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
10707 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
10709 This warning doesn't indicate any serious problem, as long as you don't want to
10710 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
10711 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
10712 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
10713 independently. With this setup, it's not possible to halt the core right out of
10714 reset, everything else should work fine.
10716 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
10717 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
10718 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
10719 quit with an error message. Is there a stability issue with OpenOCD?
10721 No, this is not a stability issue concerning OpenOCD. Most users have solved
10722 this issue by simply using a self-powered USB hub, which they connect their
10723 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
10724 supply stable enough for the Amontec JTAGkey to be operated.
10726 @b{Laptops running on battery have this problem too...}
10728 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
10729 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
10730 What does that mean and what might be the reason for this?
10732 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
10733 has closed the connection to OpenOCD. This might be a GDB issue.
10735 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
10736 are described, there is a parameter for specifying the clock frequency
10737 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
10738 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
10739 specified in kilohertz. However, I do have a quartz crystal of a
10740 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
10741 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
10744 No. The clock frequency specified here must be given as an integral number.
10745 However, this clock frequency is used by the In-Application-Programming (IAP)
10746 routines of the LPC2000 family only, which seems to be very tolerant concerning
10747 the given clock frequency, so a slight difference between the specified clock
10748 frequency and the actual clock frequency will not cause any trouble.
10750 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
10752 Well, yes and no. Commands can be given in arbitrary order, yet the
10753 devices listed for the JTAG scan chain must be given in the right
10754 order (jtag newdevice), with the device closest to the TDO-Pin being
10755 listed first. In general, whenever objects of the same type exist
10756 which require an index number, then these objects must be given in the
10757 right order (jtag newtap, targets and flash banks - a target
10758 references a jtag newtap and a flash bank references a target).
10760 You can use the ``scan_chain'' command to verify and display the tap order.
10762 Also, some commands can't execute until after @command{init} has been
10763 processed. Such commands include @command{nand probe} and everything
10764 else that needs to write to controller registers, perhaps for setting
10765 up DRAM and loading it with code.
10767 @anchor{faqtaporder}
10768 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
10771 Yes; whenever you have more than one, you must declare them in
10772 the same order used by the hardware.
10774 Many newer devices have multiple JTAG TAPs. For example:
10775 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
10776 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
10777 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
10778 connected to the boundary scan TAP, which then connects to the
10779 Cortex-M3 TAP, which then connects to the TDO pin.
10781 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
10782 (2) The boundary scan TAP. If your board includes an additional JTAG
10783 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
10784 place it before or after the STM32 chip in the chain. For example:
10787 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
10788 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
10789 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
10790 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
10791 @item Xilinx TDO Pin -> OpenOCD TDO (input)
10794 The ``jtag device'' commands would thus be in the order shown below. Note:
10797 @item jtag newtap Xilinx tap -irlen ...
10798 @item jtag newtap stm32 cpu -irlen ...
10799 @item jtag newtap stm32 bs -irlen ...
10800 @item # Create the debug target and say where it is
10801 @item target create stm32.cpu -chain-position stm32.cpu ...
10805 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
10806 log file, I can see these error messages: Error: arm7_9_common.c:561
10807 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
10813 @node Tcl Crash Course
10814 @chapter Tcl Crash Course
10817 Not everyone knows Tcl - this is not intended to be a replacement for
10818 learning Tcl, the intent of this chapter is to give you some idea of
10819 how the Tcl scripts work.
10821 This chapter is written with two audiences in mind. (1) OpenOCD users
10822 who need to understand a bit more of how Jim-Tcl works so they can do
10823 something useful, and (2) those that want to add a new command to
10826 @section Tcl Rule #1
10827 There is a famous joke, it goes like this:
10829 @item Rule #1: The wife is always correct
10830 @item Rule #2: If you think otherwise, See Rule #1
10833 The Tcl equal is this:
10836 @item Rule #1: Everything is a string
10837 @item Rule #2: If you think otherwise, See Rule #1
10840 As in the famous joke, the consequences of Rule #1 are profound. Once
10841 you understand Rule #1, you will understand Tcl.
10843 @section Tcl Rule #1b
10844 There is a second pair of rules.
10846 @item Rule #1: Control flow does not exist. Only commands
10847 @* For example: the classic FOR loop or IF statement is not a control
10848 flow item, they are commands, there is no such thing as control flow
10850 @item Rule #2: If you think otherwise, See Rule #1
10851 @* Actually what happens is this: There are commands that by
10852 convention, act like control flow key words in other languages. One of
10853 those commands is the word ``for'', another command is ``if''.
10856 @section Per Rule #1 - All Results are strings
10857 Every Tcl command results in a string. The word ``result'' is used
10858 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
10859 Everything is a string}
10861 @section Tcl Quoting Operators
10862 In life of a Tcl script, there are two important periods of time, the
10863 difference is subtle.
10866 @item Evaluation Time
10869 The two key items here are how ``quoted things'' work in Tcl. Tcl has
10870 three primary quoting constructs, the [square-brackets] the
10871 @{curly-braces@} and ``double-quotes''
10873 By now you should know $VARIABLES always start with a $DOLLAR
10874 sign. BTW: To set a variable, you actually use the command ``set'', as
10875 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
10876 = 1'' statement, but without the equal sign.
10879 @item @b{[square-brackets]}
10880 @* @b{[square-brackets]} are command substitutions. It operates much
10881 like Unix Shell `back-ticks`. The result of a [square-bracket]
10882 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
10883 string}. These two statements are roughly identical:
10887 echo "The Date is: $X"
10890 puts "The Date is: $X"
10892 @item @b{``double-quoted-things''}
10893 @* @b{``double-quoted-things''} are just simply quoted
10894 text. $VARIABLES and [square-brackets] are expanded in place - the
10895 result however is exactly 1 string. @i{Remember Rule #1 - Everything
10899 puts "It is now \"[date]\", $x is in 1 hour"
10901 @item @b{@{Curly-Braces@}}
10902 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
10903 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
10904 'single-quote' operators in BASH shell scripts, with the added
10905 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
10906 nested 3 times@}@}@} NOTE: [date] is a bad example;
10907 at this writing, Jim/OpenOCD does not have a date command.
10910 @section Consequences of Rule 1/2/3/4
10912 The consequences of Rule 1 are profound.
10914 @subsection Tokenisation & Execution.
10916 Of course, whitespace, blank lines and #comment lines are handled in
10919 As a script is parsed, each (multi) line in the script file is
10920 tokenised and according to the quoting rules. After tokenisation, that
10921 line is immediately executed.
10923 Multi line statements end with one or more ``still-open''
10924 @{curly-braces@} which - eventually - closes a few lines later.
10926 @subsection Command Execution
10928 Remember earlier: There are no ``control flow''
10929 statements in Tcl. Instead there are COMMANDS that simply act like
10930 control flow operators.
10932 Commands are executed like this:
10935 @item Parse the next line into (argc) and (argv[]).
10936 @item Look up (argv[0]) in a table and call its function.
10937 @item Repeat until End Of File.
10940 It sort of works like this:
10943 ReadAndParse( &argc, &argv );
10945 cmdPtr = LookupCommand( argv[0] );
10947 (*cmdPtr->Execute)( argc, argv );
10951 When the command ``proc'' is parsed (which creates a procedure
10952 function) it gets 3 parameters on the command line. @b{1} the name of
10953 the proc (function), @b{2} the list of parameters, and @b{3} the body
10954 of the function. Not the choice of words: LIST and BODY. The PROC
10955 command stores these items in a table somewhere so it can be found by
10956 ``LookupCommand()''
10958 @subsection The FOR command
10960 The most interesting command to look at is the FOR command. In Tcl,
10961 the FOR command is normally implemented in C. Remember, FOR is a
10962 command just like any other command.
10964 When the ascii text containing the FOR command is parsed, the parser
10965 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
10969 @item The ascii text 'for'
10970 @item The start text
10971 @item The test expression
10972 @item The next text
10973 @item The body text
10976 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
10977 Remember @i{Rule #1 - Everything is a string.} The key point is this:
10978 Often many of those parameters are in @{curly-braces@} - thus the
10979 variables inside are not expanded or replaced until later.
10981 Remember that every Tcl command looks like the classic ``main( argc,
10982 argv )'' function in C. In JimTCL - they actually look like this:
10986 MyCommand( Jim_Interp *interp,
10988 Jim_Obj * const *argvs );
10991 Real Tcl is nearly identical. Although the newer versions have
10992 introduced a byte-code parser and interpreter, but at the core, it
10993 still operates in the same basic way.
10995 @subsection FOR command implementation
10997 To understand Tcl it is perhaps most helpful to see the FOR
10998 command. Remember, it is a COMMAND not a control flow structure.
11000 In Tcl there are two underlying C helper functions.
11002 Remember Rule #1 - You are a string.
11004 The @b{first} helper parses and executes commands found in an ascii
11005 string. Commands can be separated by semicolons, or newlines. While
11006 parsing, variables are expanded via the quoting rules.
11008 The @b{second} helper evaluates an ascii string as a numerical
11009 expression and returns a value.
11011 Here is an example of how the @b{FOR} command could be
11012 implemented. The pseudo code below does not show error handling.
11014 void Execute_AsciiString( void *interp, const char *string );
11016 int Evaluate_AsciiExpression( void *interp, const char *string );
11019 MyForCommand( void *interp,
11024 SetResult( interp, "WRONG number of parameters");
11028 // argv[0] = the ascii string just like C
11030 // Execute the start statement.
11031 Execute_AsciiString( interp, argv[1] );
11033 // Top of loop test
11035 i = Evaluate_AsciiExpression(interp, argv[2]);
11039 // Execute the body
11040 Execute_AsciiString( interp, argv[3] );
11042 // Execute the LOOP part
11043 Execute_AsciiString( interp, argv[4] );
11047 SetResult( interp, "" );
11052 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
11053 in the same basic way.
11055 @section OpenOCD Tcl Usage
11057 @subsection source and find commands
11058 @b{Where:} In many configuration files
11059 @* Example: @b{ source [find FILENAME] }
11060 @*Remember the parsing rules
11062 @item The @command{find} command is in square brackets,
11063 and is executed with the parameter FILENAME. It should find and return
11064 the full path to a file with that name; it uses an internal search path.
11065 The RESULT is a string, which is substituted into the command line in
11066 place of the bracketed @command{find} command.
11067 (Don't try to use a FILENAME which includes the "#" character.
11068 That character begins Tcl comments.)
11069 @item The @command{source} command is executed with the resulting filename;
11070 it reads a file and executes as a script.
11072 @subsection format command
11073 @b{Where:} Generally occurs in numerous places.
11074 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
11080 puts [format "The answer: %d" [expr $x * $y]]
11083 @item The SET command creates 2 variables, X and Y.
11084 @item The double [nested] EXPR command performs math
11085 @* The EXPR command produces numerical result as a string.
11086 @* Refer to Rule #1
11087 @item The format command is executed, producing a single string
11088 @* Refer to Rule #1.
11089 @item The PUTS command outputs the text.
11091 @subsection Body or Inlined Text
11092 @b{Where:} Various TARGET scripts.
11095 proc someproc @{@} @{
11096 ... multiple lines of stuff ...
11098 $_TARGETNAME configure -event FOO someproc
11099 #2 Good - no variables
11100 $_TARGETNAME configure -event foo "this ; that;"
11101 #3 Good Curly Braces
11102 $_TARGETNAME configure -event FOO @{
11103 puts "Time: [date]"
11105 #4 DANGER DANGER DANGER
11106 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
11109 @item The $_TARGETNAME is an OpenOCD variable convention.
11110 @*@b{$_TARGETNAME} represents the last target created, the value changes
11111 each time a new target is created. Remember the parsing rules. When
11112 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
11113 the name of the target which happens to be a TARGET (object)
11115 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
11116 @*There are 4 examples:
11118 @item The TCLBODY is a simple string that happens to be a proc name
11119 @item The TCLBODY is several simple commands separated by semicolons
11120 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
11121 @item The TCLBODY is a string with variables that get expanded.
11124 In the end, when the target event FOO occurs the TCLBODY is
11125 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
11126 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
11128 Remember the parsing rules. In case #3, @{curly-braces@} mean the
11129 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
11130 and the text is evaluated. In case #4, they are replaced before the
11131 ``Target Object Command'' is executed. This occurs at the same time
11132 $_TARGETNAME is replaced. In case #4 the date will never
11133 change. @{BTW: [date] is a bad example; at this writing,
11134 Jim/OpenOCD does not have a date command@}
11136 @subsection Global Variables
11137 @b{Where:} You might discover this when writing your own procs @* In
11138 simple terms: Inside a PROC, if you need to access a global variable
11139 you must say so. See also ``upvar''. Example:
11141 proc myproc @{ @} @{
11142 set y 0 #Local variable Y
11143 global x #Global variable X
11144 puts [format "X=%d, Y=%d" $x $y]
11147 @section Other Tcl Hacks
11148 @b{Dynamic variable creation}
11150 # Dynamically create a bunch of variables.
11151 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
11153 set vn [format "BIT%d" $x]
11157 set $vn [expr (1 << $x)]
11160 @b{Dynamic proc/command creation}
11162 # One "X" function - 5 uart functions.
11163 foreach who @{A B C D E@}
11164 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
11170 @node OpenOCD Concept Index
11171 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
11172 @comment case issue with ``Index.html'' and ``index.html''
11173 @comment Occurs when creating ``--html --no-split'' output
11174 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
11175 @unnumbered OpenOCD Concept Index
11179 @node Command and Driver Index
11180 @unnumbered Command and Driver Index