1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
160 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 STMicroelectronics has an adapter called @b{ST-LINK}.
481 They only work with STMicroelectronics chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
491 @* This is available standalone and as part of some kits.
492 @* Link: @url{http://www.st.com/stlink-v3}
495 For info the original ST-LINK enumerates using the mass storage usb class; however,
496 its implementation is completely broken. The result is this causes issues under Linux.
497 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
499 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
500 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
503 @section USB TI/Stellaris ICDI based
504 Texas Instruments has an adapter called @b{ICDI}.
505 It is not to be confused with the FTDI based adapters that were originally fitted to their
506 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
508 @section USB CMSIS-DAP based
509 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
510 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
515 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
517 @item @b{USB - Presto}
518 @* Link: @url{http://tools.asix.net/prg_presto.htm}
520 @item @b{Versaloon-Link}
521 @* Link: @url{http://www.versaloon.com}
523 @item @b{ARM-JTAG-EW}
524 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
527 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
530 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
533 @* Link: @url{http://code.google.com/p/estick-jtag/}
535 @item @b{Keil ULINK v1}
536 @* Link: @url{http://www.keil.com/ulink1/}
538 @item @b{TI XDS110 Debug Probe}
539 @* The XDS110 is included as the embedded debug probe on many Texas Instruments
540 LaunchPad evaluation boards.
541 @* The XDS110 is also available as a stand-alone USB debug probe. The XDS110
542 stand-alone probe has the additional ability to supply voltage to the target
543 board via its AUX FUNCTIONS port. Use the
544 @command{xds110_supply_voltage <millivolts>} command to set the voltage. 0 turns
545 off the supply. Otherwise, the supply can be set to any value in the range 1800
547 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS110}
548 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Support_Utilities}
551 @section IBM PC Parallel Printer Port Based
553 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
554 and the Macraigor Wiggler. There are many clones and variations of
557 Note that parallel ports are becoming much less common, so if you
558 have the choice you should probably avoid these adapters in favor
563 @item @b{Wiggler} - There are many clones of this.
564 @* Link: @url{http://www.macraigor.com/wiggler.htm}
566 @item @b{DLC5} - From XILINX - There are many clones of this
567 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
568 produced, PDF schematics are easily found and it is easy to make.
570 @item @b{Amontec - JTAG Accelerator}
571 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
574 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
576 @item @b{Wiggler_ntrst_inverted}
577 @* Yet another variation - See the source code, src/jtag/parport.c
579 @item @b{old_amt_wiggler}
580 @* Unknown - probably not on the market today
583 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
586 @* Link: @url{http://www.amontec.com/chameleon.shtml}
592 @* ispDownload from Lattice Semiconductor
593 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
596 @* From STMicroelectronics;
597 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
605 @* An EP93xx based Linux machine using the GPIO pins directly.
608 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
610 @item @b{bcm2835gpio}
611 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
614 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
617 @* A JTAG driver acting as a client for the JTAG VPI server interface.
618 @* Link: @url{http://github.com/fjullien/jtag_vpi}
620 @item @b{xlnx_pcie_xvc}
621 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG interface.
626 @chapter About Jim-Tcl
630 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
631 This programming language provides a simple and extensible
634 All commands presented in this Guide are extensions to Jim-Tcl.
635 You can use them as simple commands, without needing to learn
636 much of anything about Tcl.
637 Alternatively, you can write Tcl programs with them.
639 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
640 There is an active and responsive community, get on the mailing list
641 if you have any questions. Jim-Tcl maintainers also lurk on the
642 OpenOCD mailing list.
645 @item @b{Jim vs. Tcl}
646 @* Jim-Tcl is a stripped down version of the well known Tcl language,
647 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
648 fewer features. Jim-Tcl is several dozens of .C files and .H files and
649 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
650 4.2 MB .zip file containing 1540 files.
652 @item @b{Missing Features}
653 @* Our practice has been: Add/clone the real Tcl feature if/when
654 needed. We welcome Jim-Tcl improvements, not bloat. Also there
655 are a large number of optional Jim-Tcl features that are not
659 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
660 command interpreter today is a mixture of (newer)
661 Jim-Tcl commands, and the (older) original command interpreter.
664 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
665 can type a Tcl for() loop, set variables, etc.
666 Some of the commands documented in this guide are implemented
667 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
669 @item @b{Historical Note}
670 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
671 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
672 as a Git submodule, which greatly simplified upgrading Jim-Tcl
673 to benefit from new features and bugfixes in Jim-Tcl.
675 @item @b{Need a crash course in Tcl?}
676 @*@xref{Tcl Crash Course}.
681 @cindex command line options
683 @cindex directory search
685 Properly installing OpenOCD sets up your operating system to grant it access
686 to the debug adapters. On Linux, this usually involves installing a file
687 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
688 that works for many common adapters is shipped with OpenOCD in the
689 @file{contrib} directory. MS-Windows needs
690 complex and confusing driver configuration for every peripheral. Such issues
691 are unique to each operating system, and are not detailed in this User's Guide.
693 Then later you will invoke the OpenOCD server, with various options to
694 tell it how each debug session should work.
695 The @option{--help} option shows:
699 --help | -h display this help
700 --version | -v display OpenOCD version
701 --file | -f use configuration file <name>
702 --search | -s dir to search for config files and scripts
703 --debug | -d set debug level to 3
704 | -d<n> set debug level to <level>
705 --log_output | -l redirect log output to file <name>
706 --command | -c run <command>
709 If you don't give any @option{-f} or @option{-c} options,
710 OpenOCD tries to read the configuration file @file{openocd.cfg}.
711 To specify one or more different
712 configuration files, use @option{-f} options. For example:
715 openocd -f config1.cfg -f config2.cfg -f config3.cfg
718 Configuration files and scripts are searched for in
720 @item the current directory,
721 @item any search dir specified on the command line using the @option{-s} option,
722 @item any search dir specified using the @command{add_script_search_dir} command,
723 @item @file{$HOME/.openocd} (not on Windows),
724 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
725 @item the site wide script library @file{$pkgdatadir/site} and
726 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
728 The first found file with a matching file name will be used.
731 Don't try to use configuration script names or paths which
732 include the "#" character. That character begins Tcl comments.
735 @section Simple setup, no customization
737 In the best case, you can use two scripts from one of the script
738 libraries, hook up your JTAG adapter, and start the server ... and
739 your JTAG setup will just work "out of the box". Always try to
740 start by reusing those scripts, but assume you'll need more
741 customization even if this works. @xref{OpenOCD Project Setup}.
743 If you find a script for your JTAG adapter, and for your board or
744 target, you may be able to hook up your JTAG adapter then start
745 the server with some variation of one of the following:
748 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
749 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
752 You might also need to configure which reset signals are present,
753 using @option{-c 'reset_config trst_and_srst'} or something similar.
754 If all goes well you'll see output something like
757 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
758 For bug reports, read
759 http://openocd.org/doc/doxygen/bugs.html
760 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
761 (mfg: 0x23b, part: 0xba00, ver: 0x3)
764 Seeing that "tap/device found" message, and no warnings, means
765 the JTAG communication is working. That's a key milestone, but
766 you'll probably need more project-specific setup.
768 @section What OpenOCD does as it starts
770 OpenOCD starts by processing the configuration commands provided
771 on the command line or, if there were no @option{-c command} or
772 @option{-f file.cfg} options given, in @file{openocd.cfg}.
773 @xref{configurationstage,,Configuration Stage}.
774 At the end of the configuration stage it verifies the JTAG scan
775 chain defined using those commands; your configuration should
776 ensure that this always succeeds.
777 Normally, OpenOCD then starts running as a server.
778 Alternatively, commands may be used to terminate the configuration
779 stage early, perform work (such as updating some flash memory),
780 and then shut down without acting as a server.
782 Once OpenOCD starts running as a server, it waits for connections from
783 clients (Telnet, GDB, RPC) and processes the commands issued through
786 If you are having problems, you can enable internal debug messages via
787 the @option{-d} option.
789 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
790 @option{-c} command line switch.
792 To enable debug output (when reporting problems or working on OpenOCD
793 itself), use the @option{-d} command line switch. This sets the
794 @option{debug_level} to "3", outputting the most information,
795 including debug messages. The default setting is "2", outputting only
796 informational messages, warnings and errors. You can also change this
797 setting from within a telnet or gdb session using @command{debug_level<n>}
798 (@pxref{debuglevel,,debug_level}).
800 You can redirect all output from the server to a file using the
801 @option{-l <logfile>} switch.
803 Note! OpenOCD will launch the GDB & telnet server even if it can not
804 establish a connection with the target. In general, it is possible for
805 the JTAG controller to be unresponsive until the target is set up
806 correctly via e.g. GDB monitor commands in a GDB init script.
808 @node OpenOCD Project Setup
809 @chapter OpenOCD Project Setup
811 To use OpenOCD with your development projects, you need to do more than
812 just connect the JTAG adapter hardware (dongle) to your development board
813 and start the OpenOCD server.
814 You also need to configure your OpenOCD server so that it knows
815 about your adapter and board, and helps your work.
816 You may also want to connect OpenOCD to GDB, possibly
817 using Eclipse or some other GUI.
819 @section Hooking up the JTAG Adapter
821 Today's most common case is a dongle with a JTAG cable on one side
822 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
823 and a USB cable on the other.
824 Instead of USB, some cables use Ethernet;
825 older ones may use a PC parallel port, or even a serial port.
828 @item @emph{Start with power to your target board turned off},
829 and nothing connected to your JTAG adapter.
830 If you're particularly paranoid, unplug power to the board.
831 It's important to have the ground signal properly set up,
832 unless you are using a JTAG adapter which provides
833 galvanic isolation between the target board and the
836 @item @emph{Be sure it's the right kind of JTAG connector.}
837 If your dongle has a 20-pin ARM connector, you need some kind
838 of adapter (or octopus, see below) to hook it up to
839 boards using 14-pin or 10-pin connectors ... or to 20-pin
840 connectors which don't use ARM's pinout.
842 In the same vein, make sure the voltage levels are compatible.
843 Not all JTAG adapters have the level shifters needed to work
844 with 1.2 Volt boards.
846 @item @emph{Be certain the cable is properly oriented} or you might
847 damage your board. In most cases there are only two possible
848 ways to connect the cable.
849 Connect the JTAG cable from your adapter to the board.
850 Be sure it's firmly connected.
852 In the best case, the connector is keyed to physically
853 prevent you from inserting it wrong.
854 This is most often done using a slot on the board's male connector
855 housing, which must match a key on the JTAG cable's female connector.
856 If there's no housing, then you must look carefully and
857 make sure pin 1 on the cable hooks up to pin 1 on the board.
858 Ribbon cables are frequently all grey except for a wire on one
859 edge, which is red. The red wire is pin 1.
861 Sometimes dongles provide cables where one end is an ``octopus'' of
862 color coded single-wire connectors, instead of a connector block.
863 These are great when converting from one JTAG pinout to another,
864 but are tedious to set up.
865 Use these with connector pinout diagrams to help you match up the
866 adapter signals to the right board pins.
868 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
869 A USB, parallel, or serial port connector will go to the host which
870 you are using to run OpenOCD.
871 For Ethernet, consult the documentation and your network administrator.
873 For USB-based JTAG adapters you have an easy sanity check at this point:
874 does the host operating system see the JTAG adapter? If you're running
875 Linux, try the @command{lsusb} command. If that host is an
876 MS-Windows host, you'll need to install a driver before OpenOCD works.
878 @item @emph{Connect the adapter's power supply, if needed.}
879 This step is primarily for non-USB adapters,
880 but sometimes USB adapters need extra power.
882 @item @emph{Power up the target board.}
883 Unless you just let the magic smoke escape,
884 you're now ready to set up the OpenOCD server
885 so you can use JTAG to work with that board.
889 Talk with the OpenOCD server using
890 telnet (@code{telnet localhost 4444} on many systems) or GDB.
891 @xref{GDB and OpenOCD}.
893 @section Project Directory
895 There are many ways you can configure OpenOCD and start it up.
897 A simple way to organize them all involves keeping a
898 single directory for your work with a given board.
899 When you start OpenOCD from that directory,
900 it searches there first for configuration files, scripts,
901 files accessed through semihosting,
902 and for code you upload to the target board.
903 It is also the natural place to write files,
904 such as log files and data you download from the board.
906 @section Configuration Basics
908 There are two basic ways of configuring OpenOCD, and
909 a variety of ways you can mix them.
910 Think of the difference as just being how you start the server:
913 @item Many @option{-f file} or @option{-c command} options on the command line
914 @item No options, but a @dfn{user config file}
915 in the current directory named @file{openocd.cfg}
918 Here is an example @file{openocd.cfg} file for a setup
919 using a Signalyzer FT2232-based JTAG adapter to talk to
920 a board with an Atmel AT91SAM7X256 microcontroller:
923 source [find interface/ftdi/signalyzer.cfg]
925 # GDB can also flash my flash!
926 gdb_memory_map enable
927 gdb_flash_program enable
929 source [find target/sam7x256.cfg]
932 Here is the command line equivalent of that configuration:
935 openocd -f interface/ftdi/signalyzer.cfg \
936 -c "gdb_memory_map enable" \
937 -c "gdb_flash_program enable" \
938 -f target/sam7x256.cfg
941 You could wrap such long command lines in shell scripts,
942 each supporting a different development task.
943 One might re-flash the board with a specific firmware version.
944 Another might set up a particular debugging or run-time environment.
947 At this writing (October 2009) the command line method has
948 problems with how it treats variables.
949 For example, after @option{-c "set VAR value"}, or doing the
950 same in a script, the variable @var{VAR} will have no value
951 that can be tested in a later script.
954 Here we will focus on the simpler solution: one user config
955 file, including basic configuration plus any TCL procedures
956 to simplify your work.
958 @section User Config Files
959 @cindex config file, user
960 @cindex user config file
961 @cindex config file, overview
963 A user configuration file ties together all the parts of a project
965 One of the following will match your situation best:
968 @item Ideally almost everything comes from configuration files
969 provided by someone else.
970 For example, OpenOCD distributes a @file{scripts} directory
971 (probably in @file{/usr/share/openocd/scripts} on Linux).
972 Board and tool vendors can provide these too, as can individual
973 user sites; the @option{-s} command line option lets you say
974 where to find these files. (@xref{Running}.)
975 The AT91SAM7X256 example above works this way.
977 Three main types of non-user configuration file each have their
978 own subdirectory in the @file{scripts} directory:
981 @item @b{interface} -- one for each different debug adapter;
982 @item @b{board} -- one for each different board
983 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
986 Best case: include just two files, and they handle everything else.
987 The first is an interface config file.
988 The second is board-specific, and it sets up the JTAG TAPs and
989 their GDB targets (by deferring to some @file{target.cfg} file),
990 declares all flash memory, and leaves you nothing to do except
994 source [find interface/olimex-jtag-tiny.cfg]
995 source [find board/csb337.cfg]
998 Boards with a single microcontroller often won't need more
999 than the target config file, as in the AT91SAM7X256 example.
1000 That's because there is no external memory (flash, DDR RAM), and
1001 the board differences are encapsulated by application code.
1003 @item Maybe you don't know yet what your board looks like to JTAG.
1004 Once you know the @file{interface.cfg} file to use, you may
1005 need help from OpenOCD to discover what's on the board.
1006 Once you find the JTAG TAPs, you can just search for appropriate
1008 configuration files ... or write your own, from the bottom up.
1009 @xref{autoprobing,,Autoprobing}.
1011 @item You can often reuse some standard config files but
1012 need to write a few new ones, probably a @file{board.cfg} file.
1013 You will be using commands described later in this User's Guide,
1014 and working with the guidelines in the next chapter.
1016 For example, there may be configuration files for your JTAG adapter
1017 and target chip, but you need a new board-specific config file
1018 giving access to your particular flash chips.
1019 Or you might need to write another target chip configuration file
1020 for a new chip built around the Cortex-M3 core.
1023 When you write new configuration files, please submit
1024 them for inclusion in the next OpenOCD release.
1025 For example, a @file{board/newboard.cfg} file will help the
1026 next users of that board, and a @file{target/newcpu.cfg}
1027 will help support users of any board using that chip.
1031 You may may need to write some C code.
1032 It may be as simple as supporting a new FT2232 or parport
1033 based adapter; a bit more involved, like a NAND or NOR flash
1034 controller driver; or a big piece of work like supporting
1035 a new chip architecture.
1038 Reuse the existing config files when you can.
1039 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1040 You may find a board configuration that's a good example to follow.
1042 When you write config files, separate the reusable parts
1043 (things every user of that interface, chip, or board needs)
1044 from ones specific to your environment and debugging approach.
1048 For example, a @code{gdb-attach} event handler that invokes
1049 the @command{reset init} command will interfere with debugging
1050 early boot code, which performs some of the same actions
1051 that the @code{reset-init} event handler does.
1054 Likewise, the @command{arm9 vector_catch} command (or
1055 @cindex vector_catch
1056 its siblings @command{xscale vector_catch}
1057 and @command{cortex_m vector_catch}) can be a time-saver
1058 during some debug sessions, but don't make everyone use that either.
1059 Keep those kinds of debugging aids in your user config file,
1060 along with messaging and tracing setup.
1061 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1064 You might need to override some defaults.
1065 For example, you might need to move, shrink, or back up the target's
1066 work area if your application needs much SRAM.
1069 TCP/IP port configuration is another example of something which
1070 is environment-specific, and should only appear in
1071 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1074 @section Project-Specific Utilities
1076 A few project-specific utility
1077 routines may well speed up your work.
1078 Write them, and keep them in your project's user config file.
1080 For example, if you are making a boot loader work on a
1081 board, it's nice to be able to debug the ``after it's
1082 loaded to RAM'' parts separately from the finicky early
1083 code which sets up the DDR RAM controller and clocks.
1084 A script like this one, or a more GDB-aware sibling,
1088 proc ramboot @{ @} @{
1089 # Reset, running the target's "reset-init" scripts
1090 # to initialize clocks and the DDR RAM controller.
1091 # Leave the CPU halted.
1094 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1095 load_image u-boot.bin 0x20000000
1102 Then once that code is working you will need to make it
1103 boot from NOR flash; a different utility would help.
1104 Alternatively, some developers write to flash using GDB.
1105 (You might use a similar script if you're working with a flash
1106 based microcontroller application instead of a boot loader.)
1109 proc newboot @{ @} @{
1110 # Reset, leaving the CPU halted. The "reset-init" event
1111 # proc gives faster access to the CPU and to NOR flash;
1112 # "reset halt" would be slower.
1115 # Write standard version of U-Boot into the first two
1116 # sectors of NOR flash ... the standard version should
1117 # do the same lowlevel init as "reset-init".
1118 flash protect 0 0 1 off
1119 flash erase_sector 0 0 1
1120 flash write_bank 0 u-boot.bin 0x0
1121 flash protect 0 0 1 on
1123 # Reboot from scratch using that new boot loader.
1128 You may need more complicated utility procedures when booting
1130 That often involves an extra bootloader stage,
1131 running from on-chip SRAM to perform DDR RAM setup so it can load
1132 the main bootloader code (which won't fit into that SRAM).
1134 Other helper scripts might be used to write production system images,
1135 involving considerably more than just a three stage bootloader.
1137 @section Target Software Changes
1139 Sometimes you may want to make some small changes to the software
1140 you're developing, to help make JTAG debugging work better.
1141 For example, in C or assembly language code you might
1142 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1143 handling issues like:
1147 @item @b{Watchdog Timers}...
1148 Watchdog timers are typically used to automatically reset systems if
1149 some application task doesn't periodically reset the timer. (The
1150 assumption is that the system has locked up if the task can't run.)
1151 When a JTAG debugger halts the system, that task won't be able to run
1152 and reset the timer ... potentially causing resets in the middle of
1153 your debug sessions.
1155 It's rarely a good idea to disable such watchdogs, since their usage
1156 needs to be debugged just like all other parts of your firmware.
1157 That might however be your only option.
1159 Look instead for chip-specific ways to stop the watchdog from counting
1160 while the system is in a debug halt state. It may be simplest to set
1161 that non-counting mode in your debugger startup scripts. You may however
1162 need a different approach when, for example, a motor could be physically
1163 damaged by firmware remaining inactive in a debug halt state. That might
1164 involve a type of firmware mode where that "non-counting" mode is disabled
1165 at the beginning then re-enabled at the end; a watchdog reset might fire
1166 and complicate the debug session, but hardware (or people) would be
1167 protected.@footnote{Note that many systems support a "monitor mode" debug
1168 that is a somewhat cleaner way to address such issues. You can think of
1169 it as only halting part of the system, maybe just one task,
1170 instead of the whole thing.
1171 At this writing, January 2010, OpenOCD based debugging does not support
1172 monitor mode debug, only "halt mode" debug.}
1174 @item @b{ARM Semihosting}...
1175 @cindex ARM semihosting
1176 When linked with a special runtime library provided with many
1177 toolchains@footnote{See chapter 8 "Semihosting" in
1178 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1179 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1180 The CodeSourcery EABI toolchain also includes a semihosting library.},
1181 your target code can use I/O facilities on the debug host. That library
1182 provides a small set of system calls which are handled by OpenOCD.
1183 It can let the debugger provide your system console and a file system,
1184 helping with early debugging or providing a more capable environment
1185 for sometimes-complex tasks like installing system firmware onto
1188 @item @b{ARM Wait-For-Interrupt}...
1189 Many ARM chips synchronize the JTAG clock using the core clock.
1190 Low power states which stop that core clock thus prevent JTAG access.
1191 Idle loops in tasking environments often enter those low power states
1192 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1194 You may want to @emph{disable that instruction} in source code,
1195 or otherwise prevent using that state,
1196 to ensure you can get JTAG access at any time.@footnote{As a more
1197 polite alternative, some processors have special debug-oriented
1198 registers which can be used to change various features including
1199 how the low power states are clocked while debugging.
1200 The STM32 DBGMCU_CR register is an example; at the cost of extra
1201 power consumption, JTAG can be used during low power states.}
1202 For example, the OpenOCD @command{halt} command may not
1203 work for an idle processor otherwise.
1205 @item @b{Delay after reset}...
1206 Not all chips have good support for debugger access
1207 right after reset; many LPC2xxx chips have issues here.
1208 Similarly, applications that reconfigure pins used for
1209 JTAG access as they start will also block debugger access.
1211 To work with boards like this, @emph{enable a short delay loop}
1212 the first thing after reset, before "real" startup activities.
1213 For example, one second's delay is usually more than enough
1214 time for a JTAG debugger to attach, so that
1215 early code execution can be debugged
1216 or firmware can be replaced.
1218 @item @b{Debug Communications Channel (DCC)}...
1219 Some processors include mechanisms to send messages over JTAG.
1220 Many ARM cores support these, as do some cores from other vendors.
1221 (OpenOCD may be able to use this DCC internally, speeding up some
1222 operations like writing to memory.)
1224 Your application may want to deliver various debugging messages
1225 over JTAG, by @emph{linking with a small library of code}
1226 provided with OpenOCD and using the utilities there to send
1227 various kinds of message.
1228 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1232 @section Target Hardware Setup
1234 Chip vendors often provide software development boards which
1235 are highly configurable, so that they can support all options
1236 that product boards may require. @emph{Make sure that any
1237 jumpers or switches match the system configuration you are
1240 Common issues include:
1244 @item @b{JTAG setup} ...
1245 Boards may support more than one JTAG configuration.
1246 Examples include jumpers controlling pullups versus pulldowns
1247 on the nTRST and/or nSRST signals, and choice of connectors
1248 (e.g. which of two headers on the base board,
1249 or one from a daughtercard).
1250 For some Texas Instruments boards, you may need to jumper the
1251 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1253 @item @b{Boot Modes} ...
1254 Complex chips often support multiple boot modes, controlled
1255 by external jumpers. Make sure this is set up correctly.
1256 For example many i.MX boards from NXP need to be jumpered
1257 to "ATX mode" to start booting using the on-chip ROM, when
1258 using second stage bootloader code stored in a NAND flash chip.
1260 Such explicit configuration is common, and not limited to
1261 booting from NAND. You might also need to set jumpers to
1262 start booting using code loaded from an MMC/SD card; external
1263 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1264 flash; some external host; or various other sources.
1267 @item @b{Memory Addressing} ...
1268 Boards which support multiple boot modes may also have jumpers
1269 to configure memory addressing. One board, for example, jumpers
1270 external chipselect 0 (used for booting) to address either
1271 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1272 or NAND flash. When it's jumpered to address NAND flash, that
1273 board must also be told to start booting from on-chip ROM.
1275 Your @file{board.cfg} file may also need to be told this jumper
1276 configuration, so that it can know whether to declare NOR flash
1277 using @command{flash bank} or instead declare NAND flash with
1278 @command{nand device}; and likewise which probe to perform in
1279 its @code{reset-init} handler.
1281 A closely related issue is bus width. Jumpers might need to
1282 distinguish between 8 bit or 16 bit bus access for the flash
1283 used to start booting.
1285 @item @b{Peripheral Access} ...
1286 Development boards generally provide access to every peripheral
1287 on the chip, sometimes in multiple modes (such as by providing
1288 multiple audio codec chips).
1289 This interacts with software
1290 configuration of pin multiplexing, where for example a
1291 given pin may be routed either to the MMC/SD controller
1292 or the GPIO controller. It also often interacts with
1293 configuration jumpers. One jumper may be used to route
1294 signals to an MMC/SD card slot or an expansion bus (which
1295 might in turn affect booting); others might control which
1296 audio or video codecs are used.
1300 Plus you should of course have @code{reset-init} event handlers
1301 which set up the hardware to match that jumper configuration.
1302 That includes in particular any oscillator or PLL used to clock
1303 the CPU, and any memory controllers needed to access external
1304 memory and peripherals. Without such handlers, you won't be
1305 able to access those resources without working target firmware
1306 which can do that setup ... this can be awkward when you're
1307 trying to debug that target firmware. Even if there's a ROM
1308 bootloader which handles a few issues, it rarely provides full
1309 access to all board-specific capabilities.
1312 @node Config File Guidelines
1313 @chapter Config File Guidelines
1315 This chapter is aimed at any user who needs to write a config file,
1316 including developers and integrators of OpenOCD and any user who
1317 needs to get a new board working smoothly.
1318 It provides guidelines for creating those files.
1320 You should find the following directories under
1321 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1322 them as-is where you can; or as models for new files.
1324 @item @file{interface} ...
1325 These are for debug adapters. Files that specify configuration to use
1326 specific JTAG, SWD and other adapters go here.
1327 @item @file{board} ...
1328 Think Circuit Board, PWA, PCB, they go by many names. Board files
1329 contain initialization items that are specific to a board.
1331 They reuse target configuration files, since the same
1332 microprocessor chips are used on many boards,
1333 but support for external parts varies widely. For
1334 example, the SDRAM initialization sequence for the board, or the type
1335 of external flash and what address it uses. Any initialization
1336 sequence to enable that external flash or SDRAM should be found in the
1337 board file. Boards may also contain multiple targets: two CPUs; or
1339 @item @file{target} ...
1340 Think chip. The ``target'' directory represents the JTAG TAPs
1342 which OpenOCD should control, not a board. Two common types of targets
1343 are ARM chips and FPGA or CPLD chips.
1344 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1345 the target config file defines all of them.
1346 @item @emph{more} ... browse for other library files which may be useful.
1347 For example, there are various generic and CPU-specific utilities.
1350 The @file{openocd.cfg} user config
1351 file may override features in any of the above files by
1352 setting variables before sourcing the target file, or by adding
1353 commands specific to their situation.
1355 @section Interface Config Files
1357 The user config file
1358 should be able to source one of these files with a command like this:
1361 source [find interface/FOOBAR.cfg]
1364 A preconfigured interface file should exist for every debug adapter
1365 in use today with OpenOCD.
1366 That said, perhaps some of these config files
1367 have only been used by the developer who created it.
1369 A separate chapter gives information about how to set these up.
1370 @xref{Debug Adapter Configuration}.
1371 Read the OpenOCD source code (and Developer's Guide)
1372 if you have a new kind of hardware interface
1373 and need to provide a driver for it.
1375 @section Board Config Files
1376 @cindex config file, board
1377 @cindex board config file
1379 The user config file
1380 should be able to source one of these files with a command like this:
1383 source [find board/FOOBAR.cfg]
1386 The point of a board config file is to package everything
1387 about a given board that user config files need to know.
1388 In summary the board files should contain (if present)
1391 @item One or more @command{source [find target/...cfg]} statements
1392 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1393 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1394 @item Target @code{reset} handlers for SDRAM and I/O configuration
1395 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1396 @item All things that are not ``inside a chip''
1399 Generic things inside target chips belong in target config files,
1400 not board config files. So for example a @code{reset-init} event
1401 handler should know board-specific oscillator and PLL parameters,
1402 which it passes to target-specific utility code.
1404 The most complex task of a board config file is creating such a
1405 @code{reset-init} event handler.
1406 Define those handlers last, after you verify the rest of the board
1407 configuration works.
1409 @subsection Communication Between Config files
1411 In addition to target-specific utility code, another way that
1412 board and target config files communicate is by following a
1413 convention on how to use certain variables.
1415 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1416 Thus the rule we follow in OpenOCD is this: Variables that begin with
1417 a leading underscore are temporary in nature, and can be modified and
1418 used at will within a target configuration file.
1420 Complex board config files can do the things like this,
1421 for a board with three chips:
1424 # Chip #1: PXA270 for network side, big endian
1425 set CHIPNAME network
1427 source [find target/pxa270.cfg]
1428 # on return: _TARGETNAME = network.cpu
1429 # other commands can refer to the "network.cpu" target.
1430 $_TARGETNAME configure .... events for this CPU..
1432 # Chip #2: PXA270 for video side, little endian
1435 source [find target/pxa270.cfg]
1436 # on return: _TARGETNAME = video.cpu
1437 # other commands can refer to the "video.cpu" target.
1438 $_TARGETNAME configure .... events for this CPU..
1440 # Chip #3: Xilinx FPGA for glue logic
1443 source [find target/spartan3.cfg]
1446 That example is oversimplified because it doesn't show any flash memory,
1447 or the @code{reset-init} event handlers to initialize external DRAM
1448 or (assuming it needs it) load a configuration into the FPGA.
1449 Such features are usually needed for low-level work with many boards,
1450 where ``low level'' implies that the board initialization software may
1451 not be working. (That's a common reason to need JTAG tools. Another
1452 is to enable working with microcontroller-based systems, which often
1453 have no debugging support except a JTAG connector.)
1455 Target config files may also export utility functions to board and user
1456 config files. Such functions should use name prefixes, to help avoid
1459 Board files could also accept input variables from user config files.
1460 For example, there might be a @code{J4_JUMPER} setting used to identify
1461 what kind of flash memory a development board is using, or how to set
1462 up other clocks and peripherals.
1464 @subsection Variable Naming Convention
1465 @cindex variable names
1467 Most boards have only one instance of a chip.
1468 However, it should be easy to create a board with more than
1469 one such chip (as shown above).
1470 Accordingly, we encourage these conventions for naming
1471 variables associated with different @file{target.cfg} files,
1472 to promote consistency and
1473 so that board files can override target defaults.
1475 Inputs to target config files include:
1478 @item @code{CHIPNAME} ...
1479 This gives a name to the overall chip, and is used as part of
1480 tap identifier dotted names.
1481 While the default is normally provided by the chip manufacturer,
1482 board files may need to distinguish between instances of a chip.
1483 @item @code{ENDIAN} ...
1484 By default @option{little} - although chips may hard-wire @option{big}.
1485 Chips that can't change endianess don't need to use this variable.
1486 @item @code{CPUTAPID} ...
1487 When OpenOCD examines the JTAG chain, it can be told verify the
1488 chips against the JTAG IDCODE register.
1489 The target file will hold one or more defaults, but sometimes the
1490 chip in a board will use a different ID (perhaps a newer revision).
1493 Outputs from target config files include:
1496 @item @code{_TARGETNAME} ...
1497 By convention, this variable is created by the target configuration
1498 script. The board configuration file may make use of this variable to
1499 configure things like a ``reset init'' script, or other things
1500 specific to that board and that target.
1501 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1502 @code{_TARGETNAME1}, ... etc.
1505 @subsection The reset-init Event Handler
1506 @cindex event, reset-init
1507 @cindex reset-init handler
1509 Board config files run in the OpenOCD configuration stage;
1510 they can't use TAPs or targets, since they haven't been
1512 This means you can't write memory or access chip registers;
1513 you can't even verify that a flash chip is present.
1514 That's done later in event handlers, of which the target @code{reset-init}
1515 handler is one of the most important.
1517 Except on microcontrollers, the basic job of @code{reset-init} event
1518 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1519 Microcontrollers rarely use boot loaders; they run right out of their
1520 on-chip flash and SRAM memory. But they may want to use one of these
1521 handlers too, if just for developer convenience.
1524 Because this is so very board-specific, and chip-specific, no examples
1526 Instead, look at the board config files distributed with OpenOCD.
1527 If you have a boot loader, its source code will help; so will
1528 configuration files for other JTAG tools
1529 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1532 Some of this code could probably be shared between different boards.
1533 For example, setting up a DRAM controller often doesn't differ by
1534 much except the bus width (16 bits or 32?) and memory timings, so a
1535 reusable TCL procedure loaded by the @file{target.cfg} file might take
1536 those as parameters.
1537 Similarly with oscillator, PLL, and clock setup;
1538 and disabling the watchdog.
1539 Structure the code cleanly, and provide comments to help
1540 the next developer doing such work.
1541 (@emph{You might be that next person} trying to reuse init code!)
1543 The last thing normally done in a @code{reset-init} handler is probing
1544 whatever flash memory was configured. For most chips that needs to be
1545 done while the associated target is halted, either because JTAG memory
1546 access uses the CPU or to prevent conflicting CPU access.
1548 @subsection JTAG Clock Rate
1550 Before your @code{reset-init} handler has set up
1551 the PLLs and clocking, you may need to run with
1552 a low JTAG clock rate.
1553 @xref{jtagspeed,,JTAG Speed}.
1554 Then you'd increase that rate after your handler has
1555 made it possible to use the faster JTAG clock.
1556 When the initial low speed is board-specific, for example
1557 because it depends on a board-specific oscillator speed, then
1558 you should probably set it up in the board config file;
1559 if it's target-specific, it belongs in the target config file.
1561 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1562 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1563 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1564 Consult chip documentation to determine the peak JTAG clock rate,
1565 which might be less than that.
1568 On most ARMs, JTAG clock detection is coupled to the core clock, so
1569 software using a @option{wait for interrupt} operation blocks JTAG access.
1570 Adaptive clocking provides a partial workaround, but a more complete
1571 solution just avoids using that instruction with JTAG debuggers.
1574 If both the chip and the board support adaptive clocking,
1575 use the @command{jtag_rclk}
1576 command, in case your board is used with JTAG adapter which
1577 also supports it. Otherwise use @command{adapter speed}.
1578 Set the slow rate at the beginning of the reset sequence,
1579 and the faster rate as soon as the clocks are at full speed.
1581 @anchor{theinitboardprocedure}
1582 @subsection The init_board procedure
1583 @cindex init_board procedure
1585 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1586 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1587 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1588 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1589 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1590 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1591 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1592 Additionally ``linear'' board config file will most likely fail when target config file uses
1593 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1594 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1595 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1596 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1598 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1599 the original), allowing greater code reuse.
1602 ### board_file.cfg ###
1604 # source target file that does most of the config in init_targets
1605 source [find target/target.cfg]
1607 proc enable_fast_clock @{@} @{
1608 # enables fast on-board clock source
1609 # configures the chip to use it
1612 # initialize only board specifics - reset, clock, adapter frequency
1613 proc init_board @{@} @{
1614 reset_config trst_and_srst trst_pulls_srst
1616 $_TARGETNAME configure -event reset-start @{
1620 $_TARGETNAME configure -event reset-init @{
1627 @section Target Config Files
1628 @cindex config file, target
1629 @cindex target config file
1631 Board config files communicate with target config files using
1632 naming conventions as described above, and may source one or
1633 more target config files like this:
1636 source [find target/FOOBAR.cfg]
1639 The point of a target config file is to package everything
1640 about a given chip that board config files need to know.
1641 In summary the target files should contain
1645 @item Add TAPs to the scan chain
1646 @item Add CPU targets (includes GDB support)
1647 @item CPU/Chip/CPU-Core specific features
1651 As a rule of thumb, a target file sets up only one chip.
1652 For a microcontroller, that will often include a single TAP,
1653 which is a CPU needing a GDB target, and its on-chip flash.
1655 More complex chips may include multiple TAPs, and the target
1656 config file may need to define them all before OpenOCD
1657 can talk to the chip.
1658 For example, some phone chips have JTAG scan chains that include
1659 an ARM core for operating system use, a DSP,
1660 another ARM core embedded in an image processing engine,
1661 and other processing engines.
1663 @subsection Default Value Boiler Plate Code
1665 All target configuration files should start with code like this,
1666 letting board config files express environment-specific
1667 differences in how things should be set up.
1670 # Boards may override chip names, perhaps based on role,
1671 # but the default should match what the vendor uses
1672 if @{ [info exists CHIPNAME] @} @{
1673 set _CHIPNAME $CHIPNAME
1675 set _CHIPNAME sam7x256
1678 # ONLY use ENDIAN with targets that can change it.
1679 if @{ [info exists ENDIAN] @} @{
1685 # TAP identifiers may change as chips mature, for example with
1686 # new revision fields (the "3" here). Pick a good default; you
1687 # can pass several such identifiers to the "jtag newtap" command.
1688 if @{ [info exists CPUTAPID ] @} @{
1689 set _CPUTAPID $CPUTAPID
1691 set _CPUTAPID 0x3f0f0f0f
1694 @c but 0x3f0f0f0f is for an str73x part ...
1696 @emph{Remember:} Board config files may include multiple target
1697 config files, or the same target file multiple times
1698 (changing at least @code{CHIPNAME}).
1700 Likewise, the target configuration file should define
1701 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1702 use it later on when defining debug targets:
1705 set _TARGETNAME $_CHIPNAME.cpu
1706 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1709 @subsection Adding TAPs to the Scan Chain
1710 After the ``defaults'' are set up,
1711 add the TAPs on each chip to the JTAG scan chain.
1712 @xref{TAP Declaration}, and the naming convention
1715 In the simplest case the chip has only one TAP,
1716 probably for a CPU or FPGA.
1717 The config file for the Atmel AT91SAM7X256
1718 looks (in part) like this:
1721 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1724 A board with two such at91sam7 chips would be able
1725 to source such a config file twice, with different
1726 values for @code{CHIPNAME}, so
1727 it adds a different TAP each time.
1729 If there are nonzero @option{-expected-id} values,
1730 OpenOCD attempts to verify the actual tap id against those values.
1731 It will issue error messages if there is mismatch, which
1732 can help to pinpoint problems in OpenOCD configurations.
1735 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1736 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1737 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1738 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1739 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1742 There are more complex examples too, with chips that have
1743 multiple TAPs. Ones worth looking at include:
1746 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1747 plus a JRC to enable them
1748 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1749 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1750 is not currently used)
1753 @subsection Add CPU targets
1755 After adding a TAP for a CPU, you should set it up so that
1756 GDB and other commands can use it.
1757 @xref{CPU Configuration}.
1758 For the at91sam7 example above, the command can look like this;
1759 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1760 to little endian, and this chip doesn't support changing that.
1763 set _TARGETNAME $_CHIPNAME.cpu
1764 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1767 Work areas are small RAM areas associated with CPU targets.
1768 They are used by OpenOCD to speed up downloads,
1769 and to download small snippets of code to program flash chips.
1770 If the chip includes a form of ``on-chip-ram'' - and many do - define
1771 a work area if you can.
1772 Again using the at91sam7 as an example, this can look like:
1775 $_TARGETNAME configure -work-area-phys 0x00200000 \
1776 -work-area-size 0x4000 -work-area-backup 0
1779 @anchor{definecputargetsworkinginsmp}
1780 @subsection Define CPU targets working in SMP
1782 After setting targets, you can define a list of targets working in SMP.
1785 set _TARGETNAME_1 $_CHIPNAME.cpu1
1786 set _TARGETNAME_2 $_CHIPNAME.cpu2
1787 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1788 -coreid 0 -dbgbase $_DAP_DBG1
1789 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1790 -coreid 1 -dbgbase $_DAP_DBG2
1791 #define 2 targets working in smp.
1792 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1794 In the above example on cortex_a, 2 cpus are working in SMP.
1795 In SMP only one GDB instance is created and :
1797 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1798 @item halt command triggers the halt of all targets in the list.
1799 @item resume command triggers the write context and the restart of all targets in the list.
1800 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1801 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1802 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1805 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1806 command have been implemented.
1808 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1809 @item cortex_a smp off : disable SMP mode, the current target is the one
1810 displayed in the GDB session, only this target is now controlled by GDB
1811 session. This behaviour is useful during system boot up.
1812 @item cortex_a smp : display current SMP mode.
1813 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1820 #0 : coreid 0 is displayed to GDB ,
1821 #-> -1 : next resume triggers a real resume
1822 > cortex_a smp_gdb 1
1824 #0 :coreid 0 is displayed to GDB ,
1825 #->1 : next resume displays coreid 1 to GDB
1829 #1 :coreid 1 is displayed to GDB ,
1830 #->1 : next resume displays coreid 1 to GDB
1831 > cortex_a smp_gdb -1
1833 #1 :coreid 1 is displayed to GDB,
1834 #->-1 : next resume triggers a real resume
1838 @subsection Chip Reset Setup
1840 As a rule, you should put the @command{reset_config} command
1841 into the board file. Most things you think you know about a
1842 chip can be tweaked by the board.
1844 Some chips have specific ways the TRST and SRST signals are
1845 managed. In the unusual case that these are @emph{chip specific}
1846 and can never be changed by board wiring, they could go here.
1847 For example, some chips can't support JTAG debugging without
1850 Provide a @code{reset-assert} event handler if you can.
1851 Such a handler uses JTAG operations to reset the target,
1852 letting this target config be used in systems which don't
1853 provide the optional SRST signal, or on systems where you
1854 don't want to reset all targets at once.
1855 Such a handler might write to chip registers to force a reset,
1856 use a JRC to do that (preferable -- the target may be wedged!),
1857 or force a watchdog timer to trigger.
1858 (For Cortex-M targets, this is not necessary. The target
1859 driver knows how to use trigger an NVIC reset when SRST is
1862 Some chips need special attention during reset handling if
1863 they're going to be used with JTAG.
1864 An example might be needing to send some commands right
1865 after the target's TAP has been reset, providing a
1866 @code{reset-deassert-post} event handler that writes a chip
1867 register to report that JTAG debugging is being done.
1868 Another would be reconfiguring the watchdog so that it stops
1869 counting while the core is halted in the debugger.
1871 JTAG clocking constraints often change during reset, and in
1872 some cases target config files (rather than board config files)
1873 are the right places to handle some of those issues.
1874 For example, immediately after reset most chips run using a
1875 slower clock than they will use later.
1876 That means that after reset (and potentially, as OpenOCD
1877 first starts up) they must use a slower JTAG clock rate
1878 than they will use later.
1879 @xref{jtagspeed,,JTAG Speed}.
1881 @quotation Important
1882 When you are debugging code that runs right after chip
1883 reset, getting these issues right is critical.
1884 In particular, if you see intermittent failures when
1885 OpenOCD verifies the scan chain after reset,
1886 look at how you are setting up JTAG clocking.
1889 @anchor{theinittargetsprocedure}
1890 @subsection The init_targets procedure
1891 @cindex init_targets procedure
1893 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1894 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1895 procedure called @code{init_targets}, which will be executed when entering run stage
1896 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1897 Such procedure can be overridden by ``next level'' script (which sources the original).
1898 This concept facilitates code reuse when basic target config files provide generic configuration
1899 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1900 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1901 because sourcing them executes every initialization commands they provide.
1904 ### generic_file.cfg ###
1906 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1907 # basic initialization procedure ...
1910 proc init_targets @{@} @{
1911 # initializes generic chip with 4kB of flash and 1kB of RAM
1912 setup_my_chip MY_GENERIC_CHIP 4096 1024
1915 ### specific_file.cfg ###
1917 source [find target/generic_file.cfg]
1919 proc init_targets @{@} @{
1920 # initializes specific chip with 128kB of flash and 64kB of RAM
1921 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1925 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1926 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1928 For an example of this scheme see LPC2000 target config files.
1930 The @code{init_boards} procedure is a similar concept concerning board config files
1931 (@xref{theinitboardprocedure,,The init_board procedure}.)
1933 @anchor{theinittargeteventsprocedure}
1934 @subsection The init_target_events procedure
1935 @cindex init_target_events procedure
1937 A special procedure called @code{init_target_events} is run just after
1938 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1939 procedure}.) and before @code{init_board}
1940 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1941 to set up default target events for the targets that do not have those
1942 events already assigned.
1944 @subsection ARM Core Specific Hacks
1946 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1947 special high speed download features - enable it.
1949 If present, the MMU, the MPU and the CACHE should be disabled.
1951 Some ARM cores are equipped with trace support, which permits
1952 examination of the instruction and data bus activity. Trace
1953 activity is controlled through an ``Embedded Trace Module'' (ETM)
1954 on one of the core's scan chains. The ETM emits voluminous data
1955 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1956 If you are using an external trace port,
1957 configure it in your board config file.
1958 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1959 configure it in your target config file.
1962 etm config $_TARGETNAME 16 normal full etb
1963 etb config $_TARGETNAME $_CHIPNAME.etb
1966 @subsection Internal Flash Configuration
1968 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1970 @b{Never ever} in the ``target configuration file'' define any type of
1971 flash that is external to the chip. (For example a BOOT flash on
1972 Chip Select 0.) Such flash information goes in a board file - not
1973 the TARGET (chip) file.
1977 @item at91sam7x256 - has 256K flash YES enable it.
1978 @item str912 - has flash internal YES enable it.
1979 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1980 @item pxa270 - again - CS0 flash - it goes in the board file.
1983 @anchor{translatingconfigurationfiles}
1984 @section Translating Configuration Files
1986 If you have a configuration file for another hardware debugger
1987 or toolset (Abatron, BDI2000, BDI3000, CCS,
1988 Lauterbach, SEGGER, Macraigor, etc.), translating
1989 it into OpenOCD syntax is often quite straightforward. The most tricky
1990 part of creating a configuration script is oftentimes the reset init
1991 sequence where e.g. PLLs, DRAM and the like is set up.
1993 One trick that you can use when translating is to write small
1994 Tcl procedures to translate the syntax into OpenOCD syntax. This
1995 can avoid manual translation errors and make it easier to
1996 convert other scripts later on.
1998 Example of transforming quirky arguments to a simple search and
2002 # Lauterbach syntax(?)
2004 # Data.Set c15:0x042f %long 0x40000015
2006 # OpenOCD syntax when using procedure below.
2008 # setc15 0x01 0x00050078
2010 proc setc15 @{regs value@} @{
2013 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2015 arm mcr 15 [expr ($regs>>12)&0x7] \
2016 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2017 [expr ($regs>>8)&0x7] $value
2023 @node Server Configuration
2024 @chapter Server Configuration
2025 @cindex initialization
2026 The commands here are commonly found in the openocd.cfg file and are
2027 used to specify what TCP/IP ports are used, and how GDB should be
2030 @anchor{configurationstage}
2031 @section Configuration Stage
2032 @cindex configuration stage
2033 @cindex config command
2035 When the OpenOCD server process starts up, it enters a
2036 @emph{configuration stage} which is the only time that
2037 certain commands, @emph{configuration commands}, may be issued.
2038 Normally, configuration commands are only available
2039 inside startup scripts.
2041 In this manual, the definition of a configuration command is
2042 presented as a @emph{Config Command}, not as a @emph{Command}
2043 which may be issued interactively.
2044 The runtime @command{help} command also highlights configuration
2045 commands, and those which may be issued at any time.
2047 Those configuration commands include declaration of TAPs,
2049 the interface used for JTAG communication,
2050 and other basic setup.
2051 The server must leave the configuration stage before it
2052 may access or activate TAPs.
2053 After it leaves this stage, configuration commands may no
2056 @anchor{enteringtherunstage}
2057 @section Entering the Run Stage
2059 The first thing OpenOCD does after leaving the configuration
2060 stage is to verify that it can talk to the scan chain
2061 (list of TAPs) which has been configured.
2062 It will warn if it doesn't find TAPs it expects to find,
2063 or finds TAPs that aren't supposed to be there.
2064 You should see no errors at this point.
2065 If you see errors, resolve them by correcting the
2066 commands you used to configure the server.
2067 Common errors include using an initial JTAG speed that's too
2068 fast, and not providing the right IDCODE values for the TAPs
2071 Once OpenOCD has entered the run stage, a number of commands
2073 A number of these relate to the debug targets you may have declared.
2074 For example, the @command{mww} command will not be available until
2075 a target has been successfully instantiated.
2076 If you want to use those commands, you may need to force
2077 entry to the run stage.
2079 @deffn {Config Command} init
2080 This command terminates the configuration stage and
2081 enters the run stage. This helps when you need to have
2082 the startup scripts manage tasks such as resetting the target,
2083 programming flash, etc. To reset the CPU upon startup, add "init" and
2084 "reset" at the end of the config script or at the end of the OpenOCD
2085 command line using the @option{-c} command line switch.
2087 If this command does not appear in any startup/configuration file
2088 OpenOCD executes the command for you after processing all
2089 configuration files and/or command line options.
2091 @b{NOTE:} This command normally occurs at or near the end of your
2092 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2093 targets ready. For example: If your openocd.cfg file needs to
2094 read/write memory on your target, @command{init} must occur before
2095 the memory read/write commands. This includes @command{nand probe}.
2098 @deffn {Overridable Procedure} jtag_init
2099 This is invoked at server startup to verify that it can talk
2100 to the scan chain (list of TAPs) which has been configured.
2102 The default implementation first tries @command{jtag arp_init},
2103 which uses only a lightweight JTAG reset before examining the
2105 If that fails, it tries again, using a harder reset
2106 from the overridable procedure @command{init_reset}.
2108 Implementations must have verified the JTAG scan chain before
2110 This is done by calling @command{jtag arp_init}
2111 (or @command{jtag arp_init-reset}).
2115 @section TCP/IP Ports
2120 The OpenOCD server accepts remote commands in several syntaxes.
2121 Each syntax uses a different TCP/IP port, which you may specify
2122 only during configuration (before those ports are opened).
2124 For reasons including security, you may wish to prevent remote
2125 access using one or more of these ports.
2126 In such cases, just specify the relevant port number as "disabled".
2127 If you disable all access through TCP/IP, you will need to
2128 use the command line @option{-pipe} option.
2131 @deffn {Command} gdb_port [number]
2133 Normally gdb listens to a TCP/IP port, but GDB can also
2134 communicate via pipes(stdin/out or named pipes). The name
2135 "gdb_port" stuck because it covers probably more than 90% of
2136 the normal use cases.
2138 No arguments reports GDB port. "pipe" means listen to stdin
2139 output to stdout, an integer is base port number, "disabled"
2140 disables the gdb server.
2142 When using "pipe", also use log_output to redirect the log
2143 output to a file so as not to flood the stdin/out pipes.
2145 The -p/--pipe option is deprecated and a warning is printed
2146 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2148 Any other string is interpreted as named pipe to listen to.
2149 Output pipe is the same name as input pipe, but with 'o' appended,
2150 e.g. /var/gdb, /var/gdbo.
2152 The GDB port for the first target will be the base port, the
2153 second target will listen on gdb_port + 1, and so on.
2154 When not specified during the configuration stage,
2155 the port @var{number} defaults to 3333.
2156 When @var{number} is not a numeric value, incrementing it to compute
2157 the next port number does not work. In this case, specify the proper
2158 @var{number} for each target by using the option @code{-gdb-port} of the
2159 commands @command{target create} or @command{$target_name configure}.
2160 @xref{gdbportoverride,,option -gdb-port}.
2162 Note: when using "gdb_port pipe", increasing the default remote timeout in
2163 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2164 cause initialization to fail with "Unknown remote qXfer reply: OK".
2167 @deffn {Command} tcl_port [number]
2168 Specify or query the port used for a simplified RPC
2169 connection that can be used by clients to issue TCL commands and get the
2170 output from the Tcl engine.
2171 Intended as a machine interface.
2172 When not specified during the configuration stage,
2173 the port @var{number} defaults to 6666.
2174 When specified as "disabled", this service is not activated.
2177 @deffn {Command} telnet_port [number]
2178 Specify or query the
2179 port on which to listen for incoming telnet connections.
2180 This port is intended for interaction with one human through TCL commands.
2181 When not specified during the configuration stage,
2182 the port @var{number} defaults to 4444.
2183 When specified as "disabled", this service is not activated.
2186 @anchor{gdbconfiguration}
2187 @section GDB Configuration
2189 @cindex GDB configuration
2190 You can reconfigure some GDB behaviors if needed.
2191 The ones listed here are static and global.
2192 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2193 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2195 @anchor{gdbbreakpointoverride}
2196 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2197 Force breakpoint type for gdb @command{break} commands.
2198 This option supports GDB GUIs which don't
2199 distinguish hard versus soft breakpoints, if the default OpenOCD and
2200 GDB behaviour is not sufficient. GDB normally uses hardware
2201 breakpoints if the memory map has been set up for flash regions.
2204 @anchor{gdbflashprogram}
2205 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2206 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2207 vFlash packet is received.
2208 The default behaviour is @option{enable}.
2211 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2212 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2213 requested. GDB will then know when to set hardware breakpoints, and program flash
2214 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2215 for flash programming to work.
2216 Default behaviour is @option{enable}.
2217 @xref{gdbflashprogram,,gdb_flash_program}.
2220 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2221 Specifies whether data aborts cause an error to be reported
2222 by GDB memory read packets.
2223 The default behaviour is @option{disable};
2224 use @option{enable} see these errors reported.
2227 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2228 Specifies whether register accesses requested by GDB register read/write
2229 packets report errors or not.
2230 The default behaviour is @option{disable};
2231 use @option{enable} see these errors reported.
2234 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2235 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2236 The default behaviour is @option{enable}.
2239 @deffn {Command} gdb_save_tdesc
2240 Saves the target description file to the local file system.
2242 The file name is @i{target_name}.xml.
2245 @anchor{eventpolling}
2246 @section Event Polling
2248 Hardware debuggers are parts of asynchronous systems,
2249 where significant events can happen at any time.
2250 The OpenOCD server needs to detect some of these events,
2251 so it can report them to through TCL command line
2254 Examples of such events include:
2257 @item One of the targets can stop running ... maybe it triggers
2258 a code breakpoint or data watchpoint, or halts itself.
2259 @item Messages may be sent over ``debug message'' channels ... many
2260 targets support such messages sent over JTAG,
2261 for receipt by the person debugging or tools.
2262 @item Loss of power ... some adapters can detect these events.
2263 @item Resets not issued through JTAG ... such reset sources
2264 can include button presses or other system hardware, sometimes
2265 including the target itself (perhaps through a watchdog).
2266 @item Debug instrumentation sometimes supports event triggering
2267 such as ``trace buffer full'' (so it can quickly be emptied)
2268 or other signals (to correlate with code behavior).
2271 None of those events are signaled through standard JTAG signals.
2272 However, most conventions for JTAG connectors include voltage
2273 level and system reset (SRST) signal detection.
2274 Some connectors also include instrumentation signals, which
2275 can imply events when those signals are inputs.
2277 In general, OpenOCD needs to periodically check for those events,
2278 either by looking at the status of signals on the JTAG connector
2279 or by sending synchronous ``tell me your status'' JTAG requests
2280 to the various active targets.
2281 There is a command to manage and monitor that polling,
2282 which is normally done in the background.
2284 @deffn Command poll [@option{on}|@option{off}]
2285 Poll the current target for its current state.
2286 (Also, @pxref{targetcurstate,,target curstate}.)
2287 If that target is in debug mode, architecture
2288 specific information about the current state is printed.
2289 An optional parameter
2290 allows background polling to be enabled and disabled.
2292 You could use this from the TCL command shell, or
2293 from GDB using @command{monitor poll} command.
2294 Leave background polling enabled while you're using GDB.
2297 background polling: on
2298 target state: halted
2299 target halted in ARM state due to debug-request, \
2300 current mode: Supervisor
2301 cpsr: 0x800000d3 pc: 0x11081bfc
2302 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2307 @node Debug Adapter Configuration
2308 @chapter Debug Adapter Configuration
2309 @cindex config file, interface
2310 @cindex interface config file
2312 Correctly installing OpenOCD includes making your operating system give
2313 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2314 are used to select which one is used, and to configure how it is used.
2317 Because OpenOCD started out with a focus purely on JTAG, you may find
2318 places where it wrongly presumes JTAG is the only transport protocol
2319 in use. Be aware that recent versions of OpenOCD are removing that
2320 limitation. JTAG remains more functional than most other transports.
2321 Other transports do not support boundary scan operations, or may be
2322 specific to a given chip vendor. Some might be usable only for
2323 programming flash memory, instead of also for debugging.
2326 Debug Adapters/Interfaces/Dongles are normally configured
2327 through commands in an interface configuration
2328 file which is sourced by your @file{openocd.cfg} file, or
2329 through a command line @option{-f interface/....cfg} option.
2332 source [find interface/olimex-jtag-tiny.cfg]
2336 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2337 A few cases are so simple that you only need to say what driver to use:
2344 Most adapters need a bit more configuration than that.
2347 @section Adapter Configuration
2349 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2350 using. Depending on the type of adapter, you may need to use one or
2351 more additional commands to further identify or configure the adapter.
2353 @deffn {Config Command} {adapter driver} name
2354 Use the adapter driver @var{name} to connect to the
2358 @deffn Command {adapter list}
2359 List the debug adapter drivers that have been built into
2360 the running copy of OpenOCD.
2362 @deffn Command {adapter transports} transport_name+
2363 Specifies the transports supported by this debug adapter.
2364 The adapter driver builds-in similar knowledge; use this only
2365 when external configuration (such as jumpering) changes what
2366 the hardware can support.
2371 @deffn Command {adapter name}
2372 Returns the name of the debug adapter driver being used.
2375 @anchor{adapter_usb_location}
2376 @deffn Command {adapter usb location} [<bus>-<port>[.<port>]...]
2377 Displays or specifies the physical USB port of the adapter to use. The path
2378 roots at @var{bus} and walks down the physical ports, with each
2379 @var{port} option specifying a deeper level in the bus topology, the last
2380 @var{port} denoting where the target adapter is actually plugged.
2381 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2383 This command is only available if your libusb1 is at least version 1.0.16.
2386 @section Interface Drivers
2388 Each of the interface drivers listed here must be explicitly
2389 enabled when OpenOCD is configured, in order to be made
2390 available at run time.
2392 @deffn {Interface Driver} {amt_jtagaccel}
2393 Amontec Chameleon in its JTAG Accelerator configuration,
2394 connected to a PC's EPP mode parallel port.
2395 This defines some driver-specific commands:
2397 @deffn {Config Command} {parport_port} number
2398 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2399 the number of the @file{/dev/parport} device.
2402 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2403 Displays status of RTCK option.
2404 Optionally sets that option first.
2408 @deffn {Interface Driver} {arm-jtag-ew}
2409 Olimex ARM-JTAG-EW USB adapter
2410 This has one driver-specific command:
2412 @deffn Command {armjtagew_info}
2417 @deffn {Interface Driver} {at91rm9200}
2418 Supports bitbanged JTAG from the local system,
2419 presuming that system is an Atmel AT91rm9200
2420 and a specific set of GPIOs is used.
2421 @c command: at91rm9200_device NAME
2422 @c chooses among list of bit configs ... only one option
2425 @deffn {Interface Driver} {cmsis-dap}
2426 ARM CMSIS-DAP compliant based adapter.
2428 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2429 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2430 the driver will attempt to auto detect the CMSIS-DAP device.
2431 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2433 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2437 @deffn {Config Command} {cmsis_dap_serial} [serial]
2438 Specifies the @var{serial} of the CMSIS-DAP device to use.
2439 If not specified, serial numbers are not considered.
2442 @deffn {Command} {cmsis-dap info}
2443 Display various device information, like hardware version, firmware version, current bus status.
2447 @deffn {Interface Driver} {dummy}
2448 A dummy software-only driver for debugging.
2451 @deffn {Interface Driver} {ep93xx}
2452 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2455 @deffn {Interface Driver} {ftdi}
2456 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2457 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2459 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2460 bypassing intermediate libraries like libftdi or D2XX.
2462 Support for new FTDI based adapters can be added completely through
2463 configuration files, without the need to patch and rebuild OpenOCD.
2465 The driver uses a signal abstraction to enable Tcl configuration files to
2466 define outputs for one or several FTDI GPIO. These outputs can then be
2467 controlled using the @command{ftdi_set_signal} command. Special signal names
2468 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2469 will be used for their customary purpose. Inputs can be read using the
2470 @command{ftdi_get_signal} command.
2472 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2473 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2474 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2475 required by the protocol, to tell the adapter to drive the data output onto
2476 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2478 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2479 be controlled differently. In order to support tristateable signals such as
2480 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2481 signal. The following output buffer configurations are supported:
2484 @item Push-pull with one FTDI output as (non-)inverted data line
2485 @item Open drain with one FTDI output as (non-)inverted output-enable
2486 @item Tristate with one FTDI output as (non-)inverted data line and another
2487 FTDI output as (non-)inverted output-enable
2488 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2489 switching data and direction as necessary
2492 These interfaces have several commands, used to configure the driver
2493 before initializing the JTAG scan chain:
2495 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2496 The vendor ID and product ID of the adapter. Up to eight
2497 [@var{vid}, @var{pid}] pairs may be given, e.g.
2499 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2503 @deffn {Config Command} {ftdi_device_desc} description
2504 Provides the USB device description (the @emph{iProduct string})
2505 of the adapter. If not specified, the device description is ignored
2506 during device selection.
2509 @deffn {Config Command} {ftdi_serial} serial-number
2510 Specifies the @var{serial-number} of the adapter to use,
2511 in case the vendor provides unique IDs and more than one adapter
2512 is connected to the host.
2513 If not specified, serial numbers are not considered.
2514 (Note that USB serial numbers can be arbitrary Unicode strings,
2515 and are not restricted to containing only decimal digits.)
2518 @deffn {Config Command} {ftdi_location} <bus>-<port>[.<port>]...
2519 @emph{DEPRECATED -- avoid using this.
2520 Use the command @ref{adapter_usb_location,,adapter usb location} instead.}
2522 Specifies the physical USB port of the adapter to use. The path
2523 roots at @var{bus} and walks down the physical ports, with each
2524 @var{port} option specifying a deeper level in the bus topology, the last
2525 @var{port} denoting where the target adapter is actually plugged.
2526 The USB bus topology can be queried with the command @emph{lsusb -t}.
2528 This command is only available if your libusb1 is at least version 1.0.16.
2531 @deffn {Config Command} {ftdi_channel} channel
2532 Selects the channel of the FTDI device to use for MPSSE operations. Most
2533 adapters use the default, channel 0, but there are exceptions.
2536 @deffn {Config Command} {ftdi_layout_init} data direction
2537 Specifies the initial values of the FTDI GPIO data and direction registers.
2538 Each value is a 16-bit number corresponding to the concatenation of the high
2539 and low FTDI GPIO registers. The values should be selected based on the
2540 schematics of the adapter, such that all signals are set to safe levels with
2541 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2542 and initially asserted reset signals.
2545 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2546 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2547 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2548 register bitmasks to tell the driver the connection and type of the output
2549 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2550 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2551 used with inverting data inputs and @option{-data} with non-inverting inputs.
2552 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2553 not-output-enable) input to the output buffer is connected. The options
2554 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2555 with the method @command{ftdi_get_signal}.
2557 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2558 simple open-collector transistor driver would be specified with @option{-oe}
2559 only. In that case the signal can only be set to drive low or to Hi-Z and the
2560 driver will complain if the signal is set to drive high. Which means that if
2561 it's a reset signal, @command{reset_config} must be specified as
2562 @option{srst_open_drain}, not @option{srst_push_pull}.
2564 A special case is provided when @option{-data} and @option{-oe} is set to the
2565 same bitmask. Then the FTDI pin is considered being connected straight to the
2566 target without any buffer. The FTDI pin is then switched between output and
2567 input as necessary to provide the full set of low, high and Hi-Z
2568 characteristics. In all other cases, the pins specified in a signal definition
2569 are always driven by the FTDI.
2571 If @option{-alias} or @option{-nalias} is used, the signal is created
2572 identical (or with data inverted) to an already specified signal
2576 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2577 Set a previously defined signal to the specified level.
2579 @item @option{0}, drive low
2580 @item @option{1}, drive high
2581 @item @option{z}, set to high-impedance
2585 @deffn {Command} {ftdi_get_signal} name
2586 Get the value of a previously defined signal.
2589 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2590 Configure TCK edge at which the adapter samples the value of the TDO signal
2592 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2593 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2594 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2595 stability at higher JTAG clocks.
2597 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2598 @item @option{falling}, sample TDO on falling edge of TCK
2602 For example adapter definitions, see the configuration files shipped in the
2603 @file{interface/ftdi} directory.
2607 @deffn {Interface Driver} {ft232r}
2608 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2609 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2610 It currently doesn't support using CBUS pins as GPIO.
2612 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2619 @item DCD(10) - SRST
2622 User can change default pinout by supplying configuration
2623 commands with GPIO numbers or RS232 signal names.
2624 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2625 They differ from physical pin numbers.
2626 For details see actual FTDI chip datasheets.
2627 Every JTAG line must be configured to unique GPIO number
2628 different than any other JTAG line, even those lines
2629 that are sometimes not used like TRST or SRST.
2643 These interfaces have several commands, used to configure the driver
2644 before initializing the JTAG scan chain:
2646 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2647 The vendor ID and product ID of the adapter. If not specified, default
2648 0x0403:0x6001 is used.
2651 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2652 Specifies the @var{serial} of the adapter to use, in case the
2653 vendor provides unique IDs and more than one adapter is connected to
2654 the host. If not specified, serial numbers are not considered.
2657 @deffn {Config Command} {ft232r_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2658 Set four JTAG GPIO numbers at once.
2659 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2662 @deffn {Config Command} {ft232r_tck_num} @var{tck}
2663 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2666 @deffn {Config Command} {ft232r_tms_num} @var{tms}
2667 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2670 @deffn {Config Command} {ft232r_tdi_num} @var{tdi}
2671 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2674 @deffn {Config Command} {ft232r_tdo_num} @var{tdo}
2675 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2678 @deffn {Config Command} {ft232r_trst_num} @var{trst}
2679 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2682 @deffn {Config Command} {ft232r_srst_num} @var{srst}
2683 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2686 @deffn {Config Command} {ft232r_restore_serial} @var{word}
2687 Restore serial port after JTAG. This USB bitmode control word
2688 (16-bit) will be sent before quit. Lower byte should
2689 set GPIO direction register to a "sane" state:
2690 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2691 byte is usually 0 to disable bitbang mode.
2692 When kernel driver reattaches, serial port should continue to work.
2693 Value 0xFFFF disables sending control word and serial port,
2694 then kernel driver will not reattach.
2695 If not specified, default 0xFFFF is used.
2700 @deffn {Interface Driver} {remote_bitbang}
2701 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2702 with a remote process and sends ASCII encoded bitbang requests to that process
2703 instead of directly driving JTAG.
2705 The remote_bitbang driver is useful for debugging software running on
2706 processors which are being simulated.
2708 @deffn {Config Command} {remote_bitbang_port} number
2709 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2710 sockets instead of TCP.
2713 @deffn {Config Command} {remote_bitbang_host} hostname
2714 Specifies the hostname of the remote process to connect to using TCP, or the
2715 name of the UNIX socket to use if remote_bitbang_port is 0.
2718 For example, to connect remotely via TCP to the host foobar you might have
2722 interface remote_bitbang
2723 remote_bitbang_port 3335
2724 remote_bitbang_host foobar
2727 To connect to another process running locally via UNIX sockets with socket
2731 interface remote_bitbang
2732 remote_bitbang_port 0
2733 remote_bitbang_host mysocket
2737 @deffn {Interface Driver} {usb_blaster}
2738 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2739 for FTDI chips. These interfaces have several commands, used to
2740 configure the driver before initializing the JTAG scan chain:
2742 @deffn {Config Command} {usb_blaster_device_desc} description
2743 Provides the USB device description (the @emph{iProduct string})
2744 of the FTDI FT245 device. If not
2745 specified, the FTDI default value is used. This setting is only valid
2746 if compiled with FTD2XX support.
2749 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2750 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2751 default values are used.
2752 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2753 Altera USB-Blaster (default):
2755 usb_blaster_vid_pid 0x09FB 0x6001
2757 The following VID/PID is for Kolja Waschk's USB JTAG:
2759 usb_blaster_vid_pid 0x16C0 0x06AD
2763 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2764 Sets the state or function of the unused GPIO pins on USB-Blasters
2765 (pins 6 and 8 on the female JTAG header). These pins can be used as
2766 SRST and/or TRST provided the appropriate connections are made on the
2769 For example, to use pin 6 as SRST:
2771 usb_blaster_pin pin6 s
2772 reset_config srst_only
2776 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2777 Chooses the low level access method for the adapter. If not specified,
2778 @option{ftdi} is selected unless it wasn't enabled during the
2779 configure stage. USB-Blaster II needs @option{ublast2}.
2782 @deffn {Command} {usb_blaster_firmware} @var{path}
2783 This command specifies @var{path} to access USB-Blaster II firmware
2784 image. To be used with USB-Blaster II only.
2789 @deffn {Interface Driver} {gw16012}
2790 Gateworks GW16012 JTAG programmer.
2791 This has one driver-specific command:
2793 @deffn {Config Command} {parport_port} [port_number]
2794 Display either the address of the I/O port
2795 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2796 If a parameter is provided, first switch to use that port.
2797 This is a write-once setting.
2801 @deffn {Interface Driver} {jlink}
2802 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2805 @quotation Compatibility Note
2806 SEGGER released many firmware versions for the many hardware versions they
2807 produced. OpenOCD was extensively tested and intended to run on all of them,
2808 but some combinations were reported as incompatible. As a general
2809 recommendation, it is advisable to use the latest firmware version
2810 available for each hardware version. However the current V8 is a moving
2811 target, and SEGGER firmware versions released after the OpenOCD was
2812 released may not be compatible. In such cases it is recommended to
2813 revert to the last known functional version. For 0.5.0, this is from
2814 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2815 version is from "May 3 2012 18:36:22", packed with 4.46f.
2818 @deffn {Command} {jlink hwstatus}
2819 Display various hardware related information, for example target voltage and pin
2822 @deffn {Command} {jlink freemem}
2823 Display free device internal memory.
2825 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2826 Set the JTAG command version to be used. Without argument, show the actual JTAG
2829 @deffn {Command} {jlink config}
2830 Display the device configuration.
2832 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2833 Set the target power state on JTAG-pin 19. Without argument, show the target
2836 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2837 Set the MAC address of the device. Without argument, show the MAC address.
2839 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2840 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2841 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2844 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2845 Set the USB address of the device. This will also change the USB Product ID
2846 (PID) of the device. Without argument, show the USB address.
2848 @deffn {Command} {jlink config reset}
2849 Reset the current configuration.
2851 @deffn {Command} {jlink config write}
2852 Write the current configuration to the internal persistent storage.
2854 @deffn {Command} {jlink emucom write <channel> <data>}
2855 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2858 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2859 the EMUCOM channel 0x10:
2861 > jlink emucom write 0x10 aa0b23
2864 @deffn {Command} {jlink emucom read <channel> <length>}
2865 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2868 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2870 > jlink emucom read 0x0 4
2874 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2875 Set the USB address of the interface, in case more than one adapter is connected
2876 to the host. If not specified, USB addresses are not considered. Device
2877 selection via USB address is deprecated and the serial number should be used
2880 As a configuration command, it can be used only before 'init'.
2882 @deffn {Config} {jlink serial} <serial number>
2883 Set the serial number of the interface, in case more than one adapter is
2884 connected to the host. If not specified, serial numbers are not considered.
2886 As a configuration command, it can be used only before 'init'.
2890 @deffn {Interface Driver} {kitprog}
2891 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2892 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2893 families, but it is possible to use it with some other devices. If you are using
2894 this adapter with a PSoC or a PRoC, you may need to add
2895 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2896 configuration script.
2898 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2899 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2900 be used with this driver, and must either be used with the cmsis-dap driver or
2901 switched back to KitProg mode. See the Cypress KitProg User Guide for
2902 instructions on how to switch KitProg modes.
2906 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2908 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2909 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2910 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2911 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2912 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2913 SWD sequence must be sent after every target reset in order to re-establish
2914 communications with the target.
2915 @item Due in part to the limitation above, KitProg devices with firmware below
2916 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2917 communicate with PSoC 5LP devices. This is because, assuming debug is not
2918 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2919 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2920 could only be sent with an acquisition sequence.
2923 @deffn {Config Command} {kitprog_init_acquire_psoc}
2924 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2925 Please be aware that the acquisition sequence hard-resets the target.
2928 @deffn {Config Command} {kitprog_serial} serial
2929 Select a KitProg device by its @var{serial}. If left unspecified, the first
2930 device detected by OpenOCD will be used.
2933 @deffn {Command} {kitprog acquire_psoc}
2934 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2935 outside of the target-specific configuration scripts since it hard-resets the
2936 target as a side-effect.
2937 This is necessary for "reset halt" on some PSoC 4 series devices.
2940 @deffn {Command} {kitprog info}
2941 Display various adapter information, such as the hardware version, firmware
2942 version, and target voltage.
2946 @deffn {Interface Driver} {parport}
2947 Supports PC parallel port bit-banging cables:
2948 Wigglers, PLD download cable, and more.
2949 These interfaces have several commands, used to configure the driver
2950 before initializing the JTAG scan chain:
2952 @deffn {Config Command} {parport_cable} name
2953 Set the layout of the parallel port cable used to connect to the target.
2954 This is a write-once setting.
2955 Currently valid cable @var{name} values include:
2958 @item @b{altium} Altium Universal JTAG cable.
2959 @item @b{arm-jtag} Same as original wiggler except SRST and
2960 TRST connections reversed and TRST is also inverted.
2961 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2962 in configuration mode. This is only used to
2963 program the Chameleon itself, not a connected target.
2964 @item @b{dlc5} The Xilinx Parallel cable III.
2965 @item @b{flashlink} The ST Parallel cable.
2966 @item @b{lattice} Lattice ispDOWNLOAD Cable
2967 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2969 Amontec's Chameleon Programmer. The new version available from
2970 the website uses the original Wiggler layout ('@var{wiggler}')
2971 @item @b{triton} The parallel port adapter found on the
2972 ``Karo Triton 1 Development Board''.
2973 This is also the layout used by the HollyGates design
2974 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2975 @item @b{wiggler} The original Wiggler layout, also supported by
2976 several clones, such as the Olimex ARM-JTAG
2977 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2978 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2982 @deffn {Config Command} {parport_port} [port_number]
2983 Display either the address of the I/O port
2984 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2985 If a parameter is provided, first switch to use that port.
2986 This is a write-once setting.
2988 When using PPDEV to access the parallel port, use the number of the parallel port:
2989 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2990 you may encounter a problem.
2993 @deffn Command {parport_toggling_time} [nanoseconds]
2994 Displays how many nanoseconds the hardware needs to toggle TCK;
2995 the parport driver uses this value to obey the
2996 @command{adapter speed} configuration.
2997 When the optional @var{nanoseconds} parameter is given,
2998 that setting is changed before displaying the current value.
3000 The default setting should work reasonably well on commodity PC hardware.
3001 However, you may want to calibrate for your specific hardware.
3003 To measure the toggling time with a logic analyzer or a digital storage
3004 oscilloscope, follow the procedure below:
3006 > parport_toggling_time 1000
3009 This sets the maximum JTAG clock speed of the hardware, but
3010 the actual speed probably deviates from the requested 500 kHz.
3011 Now, measure the time between the two closest spaced TCK transitions.
3012 You can use @command{runtest 1000} or something similar to generate a
3013 large set of samples.
3014 Update the setting to match your measurement:
3016 > parport_toggling_time <measured nanoseconds>
3018 Now the clock speed will be a better match for @command{adapter speed}
3019 command given in OpenOCD scripts and event handlers.
3021 You can do something similar with many digital multimeters, but note
3022 that you'll probably need to run the clock continuously for several
3023 seconds before it decides what clock rate to show. Adjust the
3024 toggling time up or down until the measured clock rate is a good
3025 match with the rate you specified in the @command{adapter speed} command;
3030 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3031 This will configure the parallel driver to write a known
3032 cable-specific value to the parallel interface on exiting OpenOCD.
3035 For example, the interface configuration file for a
3036 classic ``Wiggler'' cable on LPT2 might look something like this:
3041 parport_cable wiggler
3045 @deffn {Interface Driver} {presto}
3046 ASIX PRESTO USB JTAG programmer.
3047 @deffn {Config Command} {presto_serial} serial_string
3048 Configures the USB serial number of the Presto device to use.
3052 @deffn {Interface Driver} {rlink}
3053 Raisonance RLink USB adapter
3056 @deffn {Interface Driver} {usbprog}
3057 usbprog is a freely programmable USB adapter.
3060 @deffn {Interface Driver} {vsllink}
3061 vsllink is part of Versaloon which is a versatile USB programmer.
3064 This defines quite a few driver-specific commands,
3065 which are not currently documented here.
3069 @anchor{hla_interface}
3070 @deffn {Interface Driver} {hla}
3071 This is a driver that supports multiple High Level Adapters.
3072 This type of adapter does not expose some of the lower level api's
3073 that OpenOCD would normally use to access the target.
3075 Currently supported adapters include the STMicroelectronics ST-LINK and TI ICDI.
3076 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3077 versions of firmware where serial number is reset after first use. Suggest
3078 using ST firmware update utility to upgrade ST-LINK firmware even if current
3079 version reported is V2.J21.S4.
3081 @deffn {Config Command} {hla_device_desc} description
3082 Currently Not Supported.
3085 @deffn {Config Command} {hla_serial} serial
3086 Specifies the serial number of the adapter.
3089 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3090 Specifies the adapter layout to use.
3093 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3094 Pairs of vendor IDs and product IDs of the device.
3097 @deffn {Command} {hla_command} command
3098 Execute a custom adapter-specific command. The @var{command} string is
3099 passed as is to the underlying adapter layout handler.
3103 @anchor{st_link_dap_interface}
3104 @deffn {Interface Driver} {st-link}
3105 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3106 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3107 directly access the arm ADIv5 DAP.
3109 The new API provide access to multiple AP on the same DAP, but the
3110 maximum number of the AP port is limited by the specific firmware version
3111 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3112 An error is returned for any AP number above the maximum allowed value.
3114 @emph{Note:} Either these same adapters and their older versions are
3115 also supported by @ref{hla_interface, the hla interface driver}.
3117 @deffn {Config Command} {st-link serial} serial
3118 Specifies the serial number of the adapter.
3121 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3122 Pairs of vendor IDs and product IDs of the device.
3126 @deffn {Interface Driver} {opendous}
3127 opendous-jtag is a freely programmable USB adapter.
3130 @deffn {Interface Driver} {ulink}
3131 This is the Keil ULINK v1 JTAG debugger.
3134 @deffn {Interface Driver} {xlnx_pcie_xvc}
3135 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3136 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3137 fabric based JTAG devices such as Cortex-M1/M3 microcontrollers. Access to this is
3138 exposed via extended capability registers in the PCI Express configuration space.
3140 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3142 @deffn {Config Command} {xlnx_pcie_xvc_config} device
3143 Specifies the PCI Express device via parameter @var{device} to use.
3145 The correct value for @var{device} can be obtained by looking at the output
3146 of lscpi -D (first column) for the corresponding device.
3148 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3153 @deffn {Interface Driver} {ZY1000}
3154 This is the Zylin ZY1000 JTAG debugger.
3158 This defines some driver-specific commands,
3159 which are not currently documented here.
3162 @deffn Command power [@option{on}|@option{off}]
3163 Turn power switch to target on/off.
3164 No arguments: print status.
3167 @deffn {Interface Driver} {bcm2835gpio}
3168 This SoC is present in Raspberry Pi which is a cheap single-board computer
3169 exposing some GPIOs on its expansion header.
3171 The driver accesses memory-mapped GPIO peripheral registers directly
3172 for maximum performance, but the only possible race condition is for
3173 the pins' modes/muxing (which is highly unlikely), so it should be
3174 able to coexist nicely with both sysfs bitbanging and various
3175 peripherals' kernel drivers. The driver restores the previous
3176 configuration on exit.
3178 See @file{interface/raspberrypi-native.cfg} for a sample config and
3183 @deffn {Interface Driver} {imx_gpio}
3184 i.MX SoC is present in many community boards. Wandboard is an example
3185 of the one which is most popular.
3187 This driver is mostly the same as bcm2835gpio.
3189 See @file{interface/imx-native.cfg} for a sample config and
3195 @deffn {Interface Driver} {openjtag}
3196 OpenJTAG compatible USB adapter.
3197 This defines some driver-specific commands:
3199 @deffn {Config Command} {openjtag_variant} variant
3200 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3201 Currently valid @var{variant} values include:
3204 @item @b{standard} Standard variant (default).
3205 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3206 (see @uref{http://www.cypress.com/?rID=82870}).
3210 @deffn {Config Command} {openjtag_device_desc} string
3211 The USB device description string of the adapter.
3212 This value is only used with the standard variant.
3216 @section Transport Configuration
3218 As noted earlier, depending on the version of OpenOCD you use,
3219 and the debug adapter you are using,
3220 several transports may be available to
3221 communicate with debug targets (or perhaps to program flash memory).
3222 @deffn Command {transport list}
3223 displays the names of the transports supported by this
3227 @deffn Command {transport select} @option{transport_name}
3228 Select which of the supported transports to use in this OpenOCD session.
3230 When invoked with @option{transport_name}, attempts to select the named
3231 transport. The transport must be supported by the debug adapter
3232 hardware and by the version of OpenOCD you are using (including the
3235 If no transport has been selected and no @option{transport_name} is
3236 provided, @command{transport select} auto-selects the first transport
3237 supported by the debug adapter.
3239 @command{transport select} always returns the name of the session's selected
3243 @subsection JTAG Transport
3245 JTAG is the original transport supported by OpenOCD, and most
3246 of the OpenOCD commands support it.
3247 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3248 each of which must be explicitly declared.
3249 JTAG supports both debugging and boundary scan testing.
3250 Flash programming support is built on top of debug support.
3252 JTAG transport is selected with the command @command{transport select
3253 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3254 driver} (in which case the command is @command{transport select hla_jtag})
3255 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3256 the command is @command{transport select dapdirect_jtag}).
3258 @subsection SWD Transport
3260 @cindex Serial Wire Debug
3261 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3262 Debug Access Point (DAP, which must be explicitly declared.
3263 (SWD uses fewer signal wires than JTAG.)
3264 SWD is debug-oriented, and does not support boundary scan testing.
3265 Flash programming support is built on top of debug support.
3266 (Some processors support both JTAG and SWD.)
3268 SWD transport is selected with the command @command{transport select
3269 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3270 driver} (in which case the command is @command{transport select hla_swd})
3271 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3272 the command is @command{transport select dapdirect_swd}).
3274 @deffn Command {swd newdap} ...
3275 Declares a single DAP which uses SWD transport.
3276 Parameters are currently the same as "jtag newtap" but this is
3279 @deffn Command {swd wcr trn prescale}
3280 Updates TRN (turnaround delay) and prescaling.fields of the
3281 Wire Control Register (WCR).
3282 No parameters: displays current settings.
3285 @subsection SPI Transport
3287 @cindex Serial Peripheral Interface
3288 The Serial Peripheral Interface (SPI) is a general purpose transport
3289 which uses four wire signaling. Some processors use it as part of a
3290 solution for flash programming.
3294 JTAG clock setup is part of system setup.
3295 It @emph{does not belong with interface setup} since any interface
3296 only knows a few of the constraints for the JTAG clock speed.
3297 Sometimes the JTAG speed is
3298 changed during the target initialization process: (1) slow at
3299 reset, (2) program the CPU clocks, (3) run fast.
3300 Both the "slow" and "fast" clock rates are functions of the
3301 oscillators used, the chip, the board design, and sometimes
3302 power management software that may be active.
3304 The speed used during reset, and the scan chain verification which
3305 follows reset, can be adjusted using a @code{reset-start}
3306 target event handler.
3307 It can then be reconfigured to a faster speed by a
3308 @code{reset-init} target event handler after it reprograms those
3309 CPU clocks, or manually (if something else, such as a boot loader,
3310 sets up those clocks).
3311 @xref{targetevents,,Target Events}.
3312 When the initial low JTAG speed is a chip characteristic, perhaps
3313 because of a required oscillator speed, provide such a handler
3314 in the target config file.
3315 When that speed is a function of a board-specific characteristic
3316 such as which speed oscillator is used, it belongs in the board
3317 config file instead.
3318 In both cases it's safest to also set the initial JTAG clock rate
3319 to that same slow speed, so that OpenOCD never starts up using a
3320 clock speed that's faster than the scan chain can support.
3324 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3327 If your system supports adaptive clocking (RTCK), configuring
3328 JTAG to use that is probably the most robust approach.
3329 However, it introduces delays to synchronize clocks; so it
3330 may not be the fastest solution.
3332 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3333 instead of @command{adapter speed}, but only for (ARM) cores and boards
3334 which support adaptive clocking.
3336 @deffn {Command} adapter speed max_speed_kHz
3337 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3338 JTAG interfaces usually support a limited number of
3339 speeds. The speed actually used won't be faster
3340 than the speed specified.
3342 Chip data sheets generally include a top JTAG clock rate.
3343 The actual rate is often a function of a CPU core clock,
3344 and is normally less than that peak rate.
3345 For example, most ARM cores accept at most one sixth of the CPU clock.
3347 Speed 0 (khz) selects RTCK method.
3348 @xref{faqrtck,,FAQ RTCK}.
3349 If your system uses RTCK, you won't need to change the
3350 JTAG clocking after setup.
3351 Not all interfaces, boards, or targets support ``rtck''.
3352 If the interface device can not
3353 support it, an error is returned when you try to use RTCK.
3356 @defun jtag_rclk fallback_speed_kHz
3357 @cindex adaptive clocking
3359 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3360 If that fails (maybe the interface, board, or target doesn't
3361 support it), falls back to the specified frequency.
3363 # Fall back to 3mhz if RTCK is not supported
3368 @node Reset Configuration
3369 @chapter Reset Configuration
3370 @cindex Reset Configuration
3372 Every system configuration may require a different reset
3373 configuration. This can also be quite confusing.
3374 Resets also interact with @var{reset-init} event handlers,
3375 which do things like setting up clocks and DRAM, and
3376 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3377 They can also interact with JTAG routers.
3378 Please see the various board files for examples.
3381 To maintainers and integrators:
3382 Reset configuration touches several things at once.
3383 Normally the board configuration file
3384 should define it and assume that the JTAG adapter supports
3385 everything that's wired up to the board's JTAG connector.
3387 However, the target configuration file could also make note
3388 of something the silicon vendor has done inside the chip,
3389 which will be true for most (or all) boards using that chip.
3390 And when the JTAG adapter doesn't support everything, the
3391 user configuration file will need to override parts of
3392 the reset configuration provided by other files.
3395 @section Types of Reset
3397 There are many kinds of reset possible through JTAG, but
3398 they may not all work with a given board and adapter.
3399 That's part of why reset configuration can be error prone.
3403 @emph{System Reset} ... the @emph{SRST} hardware signal
3404 resets all chips connected to the JTAG adapter, such as processors,
3405 power management chips, and I/O controllers. Normally resets triggered
3406 with this signal behave exactly like pressing a RESET button.
3408 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3409 just the TAP controllers connected to the JTAG adapter.
3410 Such resets should not be visible to the rest of the system; resetting a
3411 device's TAP controller just puts that controller into a known state.
3413 @emph{Emulation Reset} ... many devices can be reset through JTAG
3414 commands. These resets are often distinguishable from system
3415 resets, either explicitly (a "reset reason" register says so)
3416 or implicitly (not all parts of the chip get reset).
3418 @emph{Other Resets} ... system-on-chip devices often support
3419 several other types of reset.
3420 You may need to arrange that a watchdog timer stops
3421 while debugging, preventing a watchdog reset.
3422 There may be individual module resets.
3425 In the best case, OpenOCD can hold SRST, then reset
3426 the TAPs via TRST and send commands through JTAG to halt the
3427 CPU at the reset vector before the 1st instruction is executed.
3428 Then when it finally releases the SRST signal, the system is
3429 halted under debugger control before any code has executed.
3430 This is the behavior required to support the @command{reset halt}
3431 and @command{reset init} commands; after @command{reset init} a
3432 board-specific script might do things like setting up DRAM.
3433 (@xref{resetcommand,,Reset Command}.)
3435 @anchor{srstandtrstissues}
3436 @section SRST and TRST Issues
3438 Because SRST and TRST are hardware signals, they can have a
3439 variety of system-specific constraints. Some of the most
3444 @item @emph{Signal not available} ... Some boards don't wire
3445 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3446 support such signals even if they are wired up.
3447 Use the @command{reset_config} @var{signals} options to say
3448 when either of those signals is not connected.
3449 When SRST is not available, your code might not be able to rely
3450 on controllers having been fully reset during code startup.
3451 Missing TRST is not a problem, since JTAG-level resets can
3452 be triggered using with TMS signaling.
3454 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3455 adapter will connect SRST to TRST, instead of keeping them separate.
3456 Use the @command{reset_config} @var{combination} options to say
3457 when those signals aren't properly independent.
3459 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3460 delay circuit, reset supervisor, or on-chip features can extend
3461 the effect of a JTAG adapter's reset for some time after the adapter
3462 stops issuing the reset. For example, there may be chip or board
3463 requirements that all reset pulses last for at least a
3464 certain amount of time; and reset buttons commonly have
3465 hardware debouncing.
3466 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3467 commands to say when extra delays are needed.
3469 @item @emph{Drive type} ... Reset lines often have a pullup
3470 resistor, letting the JTAG interface treat them as open-drain
3471 signals. But that's not a requirement, so the adapter may need
3472 to use push/pull output drivers.
3473 Also, with weak pullups it may be advisable to drive
3474 signals to both levels (push/pull) to minimize rise times.
3475 Use the @command{reset_config} @var{trst_type} and
3476 @var{srst_type} parameters to say how to drive reset signals.
3478 @item @emph{Special initialization} ... Targets sometimes need
3479 special JTAG initialization sequences to handle chip-specific
3480 issues (not limited to errata).
3481 For example, certain JTAG commands might need to be issued while
3482 the system as a whole is in a reset state (SRST active)
3483 but the JTAG scan chain is usable (TRST inactive).
3484 Many systems treat combined assertion of SRST and TRST as a
3485 trigger for a harder reset than SRST alone.
3486 Such custom reset handling is discussed later in this chapter.
3489 There can also be other issues.
3490 Some devices don't fully conform to the JTAG specifications.
3491 Trivial system-specific differences are common, such as
3492 SRST and TRST using slightly different names.
3493 There are also vendors who distribute key JTAG documentation for
3494 their chips only to developers who have signed a Non-Disclosure
3497 Sometimes there are chip-specific extensions like a requirement to use
3498 the normally-optional TRST signal (precluding use of JTAG adapters which
3499 don't pass TRST through), or needing extra steps to complete a TAP reset.
3501 In short, SRST and especially TRST handling may be very finicky,
3502 needing to cope with both architecture and board specific constraints.
3504 @section Commands for Handling Resets
3506 @deffn {Command} adapter srst pulse_width milliseconds
3507 Minimum amount of time (in milliseconds) OpenOCD should wait
3508 after asserting nSRST (active-low system reset) before
3509 allowing it to be deasserted.
3512 @deffn {Command} adapter srst delay milliseconds
3513 How long (in milliseconds) OpenOCD should wait after deasserting
3514 nSRST (active-low system reset) before starting new JTAG operations.
3515 When a board has a reset button connected to SRST line it will
3516 probably have hardware debouncing, implying you should use this.
3519 @deffn {Command} jtag_ntrst_assert_width milliseconds
3520 Minimum amount of time (in milliseconds) OpenOCD should wait
3521 after asserting nTRST (active-low JTAG TAP reset) before
3522 allowing it to be deasserted.
3525 @deffn {Command} jtag_ntrst_delay milliseconds
3526 How long (in milliseconds) OpenOCD should wait after deasserting
3527 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3530 @anchor{reset_config}
3531 @deffn {Command} reset_config mode_flag ...
3532 This command displays or modifies the reset configuration
3533 of your combination of JTAG board and target in target
3534 configuration scripts.
3536 Information earlier in this section describes the kind of problems
3537 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3538 As a rule this command belongs only in board config files,
3539 describing issues like @emph{board doesn't connect TRST};
3540 or in user config files, addressing limitations derived
3541 from a particular combination of interface and board.
3542 (An unlikely example would be using a TRST-only adapter
3543 with a board that only wires up SRST.)
3545 The @var{mode_flag} options can be specified in any order, but only one
3546 of each type -- @var{signals}, @var{combination}, @var{gates},
3547 @var{trst_type}, @var{srst_type} and @var{connect_type}
3548 -- may be specified at a time.
3549 If you don't provide a new value for a given type, its previous
3550 value (perhaps the default) is unchanged.
3551 For example, this means that you don't need to say anything at all about
3552 TRST just to declare that if the JTAG adapter should want to drive SRST,
3553 it must explicitly be driven high (@option{srst_push_pull}).
3557 @var{signals} can specify which of the reset signals are connected.
3558 For example, If the JTAG interface provides SRST, but the board doesn't
3559 connect that signal properly, then OpenOCD can't use it.
3560 Possible values are @option{none} (the default), @option{trst_only},
3561 @option{srst_only} and @option{trst_and_srst}.
3564 If your board provides SRST and/or TRST through the JTAG connector,
3565 you must declare that so those signals can be used.
3569 The @var{combination} is an optional value specifying broken reset
3570 signal implementations.
3571 The default behaviour if no option given is @option{separate},
3572 indicating everything behaves normally.
3573 @option{srst_pulls_trst} states that the
3574 test logic is reset together with the reset of the system (e.g. NXP
3575 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3576 the system is reset together with the test logic (only hypothetical, I
3577 haven't seen hardware with such a bug, and can be worked around).
3578 @option{combined} implies both @option{srst_pulls_trst} and
3579 @option{trst_pulls_srst}.
3582 The @var{gates} tokens control flags that describe some cases where
3583 JTAG may be unavailable during reset.
3584 @option{srst_gates_jtag} (default)
3585 indicates that asserting SRST gates the
3586 JTAG clock. This means that no communication can happen on JTAG
3587 while SRST is asserted.
3588 Its converse is @option{srst_nogate}, indicating that JTAG commands
3589 can safely be issued while SRST is active.
3592 The @var{connect_type} tokens control flags that describe some cases where
3593 SRST is asserted while connecting to the target. @option{srst_nogate}
3594 is required to use this option.
3595 @option{connect_deassert_srst} (default)
3596 indicates that SRST will not be asserted while connecting to the target.
3597 Its converse is @option{connect_assert_srst}, indicating that SRST will
3598 be asserted before any target connection.
3599 Only some targets support this feature, STM32 and STR9 are examples.
3600 This feature is useful if you are unable to connect to your target due
3601 to incorrect options byte config or illegal program execution.
3604 The optional @var{trst_type} and @var{srst_type} parameters allow the
3605 driver mode of each reset line to be specified. These values only affect
3606 JTAG interfaces with support for different driver modes, like the Amontec
3607 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3608 relevant signal (TRST or SRST) is not connected.
3612 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3613 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3614 Most boards connect this signal to a pulldown, so the JTAG TAPs
3615 never leave reset unless they are hooked up to a JTAG adapter.
3618 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3619 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3620 Most boards connect this signal to a pullup, and allow the
3621 signal to be pulled low by various events including system
3622 power-up and pressing a reset button.
3626 @section Custom Reset Handling
3629 OpenOCD has several ways to help support the various reset
3630 mechanisms provided by chip and board vendors.
3631 The commands shown in the previous section give standard parameters.
3632 There are also @emph{event handlers} associated with TAPs or Targets.
3633 Those handlers are Tcl procedures you can provide, which are invoked
3634 at particular points in the reset sequence.
3636 @emph{When SRST is not an option} you must set
3637 up a @code{reset-assert} event handler for your target.
3638 For example, some JTAG adapters don't include the SRST signal;
3639 and some boards have multiple targets, and you won't always
3640 want to reset everything at once.
3642 After configuring those mechanisms, you might still
3643 find your board doesn't start up or reset correctly.
3644 For example, maybe it needs a slightly different sequence
3645 of SRST and/or TRST manipulations, because of quirks that
3646 the @command{reset_config} mechanism doesn't address;
3647 or asserting both might trigger a stronger reset, which
3648 needs special attention.
3650 Experiment with lower level operations, such as
3651 @command{adapter assert}, @command{adapter deassert}
3652 and the @command{jtag arp_*} operations shown here,
3653 to find a sequence of operations that works.
3654 @xref{JTAG Commands}.
3655 When you find a working sequence, it can be used to override
3656 @command{jtag_init}, which fires during OpenOCD startup
3657 (@pxref{configurationstage,,Configuration Stage});
3658 or @command{init_reset}, which fires during reset processing.
3660 You might also want to provide some project-specific reset
3661 schemes. For example, on a multi-target board the standard
3662 @command{reset} command would reset all targets, but you
3663 may need the ability to reset only one target at time and
3664 thus want to avoid using the board-wide SRST signal.
3666 @deffn {Overridable Procedure} init_reset mode
3667 This is invoked near the beginning of the @command{reset} command,
3668 usually to provide as much of a cold (power-up) reset as practical.
3669 By default it is also invoked from @command{jtag_init} if
3670 the scan chain does not respond to pure JTAG operations.
3671 The @var{mode} parameter is the parameter given to the
3672 low level reset command (@option{halt},
3673 @option{init}, or @option{run}), @option{setup},
3674 or potentially some other value.
3676 The default implementation just invokes @command{jtag arp_init-reset}.
3677 Replacements will normally build on low level JTAG
3678 operations such as @command{adapter assert} and @command{adapter deassert}.
3679 Operations here must not address individual TAPs
3680 (or their associated targets)
3681 until the JTAG scan chain has first been verified to work.
3683 Implementations must have verified the JTAG scan chain before
3685 This is done by calling @command{jtag arp_init}
3686 (or @command{jtag arp_init-reset}).
3689 @deffn Command {jtag arp_init}
3690 This validates the scan chain using just the four
3691 standard JTAG signals (TMS, TCK, TDI, TDO).
3692 It starts by issuing a JTAG-only reset.
3693 Then it performs checks to verify that the scan chain configuration
3694 matches the TAPs it can observe.
3695 Those checks include checking IDCODE values for each active TAP,
3696 and verifying the length of their instruction registers using
3697 TAP @code{-ircapture} and @code{-irmask} values.
3698 If these tests all pass, TAP @code{setup} events are
3699 issued to all TAPs with handlers for that event.
3702 @deffn Command {jtag arp_init-reset}
3703 This uses TRST and SRST to try resetting
3704 everything on the JTAG scan chain
3705 (and anything else connected to SRST).
3706 It then invokes the logic of @command{jtag arp_init}.
3710 @node TAP Declaration
3711 @chapter TAP Declaration
3712 @cindex TAP declaration
3713 @cindex TAP configuration
3715 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3716 TAPs serve many roles, including:
3719 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3720 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3721 Others do it indirectly, making a CPU do it.
3722 @item @b{Program Download} Using the same CPU support GDB uses,
3723 you can initialize a DRAM controller, download code to DRAM, and then
3724 start running that code.
3725 @item @b{Boundary Scan} Most chips support boundary scan, which
3726 helps test for board assembly problems like solder bridges
3727 and missing connections.
3730 OpenOCD must know about the active TAPs on your board(s).
3731 Setting up the TAPs is the core task of your configuration files.
3732 Once those TAPs are set up, you can pass their names to code
3733 which sets up CPUs and exports them as GDB targets,
3734 probes flash memory, performs low-level JTAG operations, and more.
3736 @section Scan Chains
3739 TAPs are part of a hardware @dfn{scan chain},
3740 which is a daisy chain of TAPs.
3741 They also need to be added to
3742 OpenOCD's software mirror of that hardware list,
3743 giving each member a name and associating other data with it.
3744 Simple scan chains, with a single TAP, are common in
3745 systems with a single microcontroller or microprocessor.
3746 More complex chips may have several TAPs internally.
3747 Very complex scan chains might have a dozen or more TAPs:
3748 several in one chip, more in the next, and connecting
3749 to other boards with their own chips and TAPs.
3751 You can display the list with the @command{scan_chain} command.
3752 (Don't confuse this with the list displayed by the @command{targets}
3753 command, presented in the next chapter.
3754 That only displays TAPs for CPUs which are configured as
3756 Here's what the scan chain might look like for a chip more than one TAP:
3759 TapName Enabled IdCode Expected IrLen IrCap IrMask
3760 -- ------------------ ------- ---------- ---------- ----- ----- ------
3761 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3762 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3763 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3766 OpenOCD can detect some of that information, but not all
3767 of it. @xref{autoprobing,,Autoprobing}.
3768 Unfortunately, those TAPs can't always be autoconfigured,
3769 because not all devices provide good support for that.
3770 JTAG doesn't require supporting IDCODE instructions, and
3771 chips with JTAG routers may not link TAPs into the chain
3772 until they are told to do so.
3774 The configuration mechanism currently supported by OpenOCD
3775 requires explicit configuration of all TAP devices using
3776 @command{jtag newtap} commands, as detailed later in this chapter.
3777 A command like this would declare one tap and name it @code{chip1.cpu}:
3780 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3783 Each target configuration file lists the TAPs provided
3785 Board configuration files combine all the targets on a board,
3787 Note that @emph{the order in which TAPs are declared is very important.}
3788 That declaration order must match the order in the JTAG scan chain,
3789 both inside a single chip and between them.
3790 @xref{faqtaporder,,FAQ TAP Order}.
3792 For example, the STMicroelectronics STR912 chip has
3793 three separate TAPs@footnote{See the ST
3794 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3795 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3796 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3797 To configure those taps, @file{target/str912.cfg}
3798 includes commands something like this:
3801 jtag newtap str912 flash ... params ...
3802 jtag newtap str912 cpu ... params ...
3803 jtag newtap str912 bs ... params ...
3806 Actual config files typically use a variable such as @code{$_CHIPNAME}
3807 instead of literals like @option{str912}, to support more than one chip
3808 of each type. @xref{Config File Guidelines}.
3810 @deffn Command {jtag names}
3811 Returns the names of all current TAPs in the scan chain.
3812 Use @command{jtag cget} or @command{jtag tapisenabled}
3813 to examine attributes and state of each TAP.
3815 foreach t [jtag names] @{
3816 puts [format "TAP: %s\n" $t]
3821 @deffn Command {scan_chain}
3822 Displays the TAPs in the scan chain configuration,
3824 The set of TAPs listed by this command is fixed by
3825 exiting the OpenOCD configuration stage,
3826 but systems with a JTAG router can
3827 enable or disable TAPs dynamically.
3830 @c FIXME! "jtag cget" should be able to return all TAP
3831 @c attributes, like "$target_name cget" does for targets.
3833 @c Probably want "jtag eventlist", and a "tap-reset" event
3834 @c (on entry to RESET state).
3839 When TAP objects are declared with @command{jtag newtap},
3840 a @dfn{dotted.name} is created for the TAP, combining the
3841 name of a module (usually a chip) and a label for the TAP.
3842 For example: @code{xilinx.tap}, @code{str912.flash},
3843 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3844 Many other commands use that dotted.name to manipulate or
3845 refer to the TAP. For example, CPU configuration uses the
3846 name, as does declaration of NAND or NOR flash banks.
3848 The components of a dotted name should follow ``C'' symbol
3849 name rules: start with an alphabetic character, then numbers
3850 and underscores are OK; while others (including dots!) are not.
3852 @section TAP Declaration Commands
3854 @c shouldn't this be(come) a {Config Command}?
3855 @deffn Command {jtag newtap} chipname tapname configparams...
3856 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3857 and configured according to the various @var{configparams}.
3859 The @var{chipname} is a symbolic name for the chip.
3860 Conventionally target config files use @code{$_CHIPNAME},
3861 defaulting to the model name given by the chip vendor but
3864 @cindex TAP naming convention
3865 The @var{tapname} reflects the role of that TAP,
3866 and should follow this convention:
3869 @item @code{bs} -- For boundary scan if this is a separate TAP;
3870 @item @code{cpu} -- The main CPU of the chip, alternatively
3871 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3872 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3873 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3874 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3875 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3876 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3877 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3879 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3880 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3881 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3882 a JTAG TAP; that TAP should be named @code{sdma}.
3885 Every TAP requires at least the following @var{configparams}:
3888 @item @code{-irlen} @var{NUMBER}
3889 @*The length in bits of the
3890 instruction register, such as 4 or 5 bits.
3893 A TAP may also provide optional @var{configparams}:
3896 @item @code{-disable} (or @code{-enable})
3897 @*Use the @code{-disable} parameter to flag a TAP which is not
3898 linked into the scan chain after a reset using either TRST
3899 or the JTAG state machine's @sc{reset} state.
3900 You may use @code{-enable} to highlight the default state
3901 (the TAP is linked in).
3902 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3903 @item @code{-expected-id} @var{NUMBER}
3904 @*A non-zero @var{number} represents a 32-bit IDCODE
3905 which you expect to find when the scan chain is examined.
3906 These codes are not required by all JTAG devices.
3907 @emph{Repeat the option} as many times as required if more than one
3908 ID code could appear (for example, multiple versions).
3909 Specify @var{number} as zero to suppress warnings about IDCODE
3910 values that were found but not included in the list.
3912 Provide this value if at all possible, since it lets OpenOCD
3913 tell when the scan chain it sees isn't right. These values
3914 are provided in vendors' chip documentation, usually a technical
3915 reference manual. Sometimes you may need to probe the JTAG
3916 hardware to find these values.
3917 @xref{autoprobing,,Autoprobing}.
3918 @item @code{-ignore-version}
3919 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3920 option. When vendors put out multiple versions of a chip, or use the same
3921 JTAG-level ID for several largely-compatible chips, it may be more practical
3922 to ignore the version field than to update config files to handle all of
3923 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3924 @item @code{-ircapture} @var{NUMBER}
3925 @*The bit pattern loaded by the TAP into the JTAG shift register
3926 on entry to the @sc{ircapture} state, such as 0x01.
3927 JTAG requires the two LSBs of this value to be 01.
3928 By default, @code{-ircapture} and @code{-irmask} are set
3929 up to verify that two-bit value. You may provide
3930 additional bits if you know them, or indicate that
3931 a TAP doesn't conform to the JTAG specification.
3932 @item @code{-irmask} @var{NUMBER}
3933 @*A mask used with @code{-ircapture}
3934 to verify that instruction scans work correctly.
3935 Such scans are not used by OpenOCD except to verify that
3936 there seems to be no problems with JTAG scan chain operations.
3937 @item @code{-ignore-syspwrupack}
3938 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
3939 register during initial examination and when checking the sticky error bit.
3940 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
3941 devices do not set the ack bit until sometime later.
3945 @section Other TAP commands
3947 @deffn Command {jtag cget} dotted.name @option{-idcode}
3948 Get the value of the IDCODE found in hardware.
3951 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3952 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3953 At this writing this TAP attribute
3954 mechanism is limited and used mostly for event handling.
3955 (It is not a direct analogue of the @code{cget}/@code{configure}
3956 mechanism for debugger targets.)
3957 See the next section for information about the available events.
3959 The @code{configure} subcommand assigns an event handler,
3960 a TCL string which is evaluated when the event is triggered.
3961 The @code{cget} subcommand returns that handler.
3968 OpenOCD includes two event mechanisms.
3969 The one presented here applies to all JTAG TAPs.
3970 The other applies to debugger targets,
3971 which are associated with certain TAPs.
3973 The TAP events currently defined are:
3976 @item @b{post-reset}
3977 @* The TAP has just completed a JTAG reset.
3978 The tap may still be in the JTAG @sc{reset} state.
3979 Handlers for these events might perform initialization sequences
3980 such as issuing TCK cycles, TMS sequences to ensure
3981 exit from the ARM SWD mode, and more.
3983 Because the scan chain has not yet been verified, handlers for these events
3984 @emph{should not issue commands which scan the JTAG IR or DR registers}
3985 of any particular target.
3986 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3988 @* The scan chain has been reset and verified.
3989 This handler may enable TAPs as needed.
3990 @item @b{tap-disable}
3991 @* The TAP needs to be disabled. This handler should
3992 implement @command{jtag tapdisable}
3993 by issuing the relevant JTAG commands.
3994 @item @b{tap-enable}
3995 @* The TAP needs to be enabled. This handler should
3996 implement @command{jtag tapenable}
3997 by issuing the relevant JTAG commands.
4000 If you need some action after each JTAG reset which isn't actually
4001 specific to any TAP (since you can't yet trust the scan chain's
4002 contents to be accurate), you might:
4005 jtag configure CHIP.jrc -event post-reset @{
4006 echo "JTAG Reset done"
4007 ... non-scan jtag operations to be done after reset
4012 @anchor{enablinganddisablingtaps}
4013 @section Enabling and Disabling TAPs
4014 @cindex JTAG Route Controller
4017 In some systems, a @dfn{JTAG Route Controller} (JRC)
4018 is used to enable and/or disable specific JTAG TAPs.
4019 Many ARM-based chips from Texas Instruments include
4020 an ``ICEPick'' module, which is a JRC.
4021 Such chips include DaVinci and OMAP3 processors.
4023 A given TAP may not be visible until the JRC has been
4024 told to link it into the scan chain; and if the JRC
4025 has been told to unlink that TAP, it will no longer
4027 Such routers address problems that JTAG ``bypass mode''
4031 @item The scan chain can only go as fast as its slowest TAP.
4032 @item Having many TAPs slows instruction scans, since all
4033 TAPs receive new instructions.
4034 @item TAPs in the scan chain must be powered up, which wastes
4035 power and prevents debugging some power management mechanisms.
4038 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4039 as implied by the existence of JTAG routers.
4040 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4041 does include a kind of JTAG router functionality.
4043 @c (a) currently the event handlers don't seem to be able to
4044 @c fail in a way that could lead to no-change-of-state.
4046 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4047 shown below, and is implemented using TAP event handlers.
4048 So for example, when defining a TAP for a CPU connected to
4049 a JTAG router, your @file{target.cfg} file
4050 should define TAP event handlers using
4051 code that looks something like this:
4054 jtag configure CHIP.cpu -event tap-enable @{
4055 ... jtag operations using CHIP.jrc
4057 jtag configure CHIP.cpu -event tap-disable @{
4058 ... jtag operations using CHIP.jrc
4062 Then you might want that CPU's TAP enabled almost all the time:
4065 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4068 Note how that particular setup event handler declaration
4069 uses quotes to evaluate @code{$CHIP} when the event is configured.
4070 Using brackets @{ @} would cause it to be evaluated later,
4071 at runtime, when it might have a different value.
4073 @deffn Command {jtag tapdisable} dotted.name
4074 If necessary, disables the tap
4075 by sending it a @option{tap-disable} event.
4076 Returns the string "1" if the tap
4077 specified by @var{dotted.name} is enabled,
4078 and "0" if it is disabled.
4081 @deffn Command {jtag tapenable} dotted.name
4082 If necessary, enables the tap
4083 by sending it a @option{tap-enable} event.
4084 Returns the string "1" if the tap
4085 specified by @var{dotted.name} is enabled,
4086 and "0" if it is disabled.
4089 @deffn Command {jtag tapisenabled} dotted.name
4090 Returns the string "1" if the tap
4091 specified by @var{dotted.name} is enabled,
4092 and "0" if it is disabled.
4095 Humans will find the @command{scan_chain} command more helpful
4096 for querying the state of the JTAG taps.
4100 @anchor{autoprobing}
4101 @section Autoprobing
4103 @cindex JTAG autoprobe
4105 TAP configuration is the first thing that needs to be done
4106 after interface and reset configuration. Sometimes it's
4107 hard finding out what TAPs exist, or how they are identified.
4108 Vendor documentation is not always easy to find and use.
4110 To help you get past such problems, OpenOCD has a limited
4111 @emph{autoprobing} ability to look at the scan chain, doing
4112 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4113 To use this mechanism, start the OpenOCD server with only data
4114 that configures your JTAG interface, and arranges to come up
4115 with a slow clock (many devices don't support fast JTAG clocks
4116 right when they come out of reset).
4118 For example, your @file{openocd.cfg} file might have:
4121 source [find interface/olimex-arm-usb-tiny-h.cfg]
4122 reset_config trst_and_srst
4126 When you start the server without any TAPs configured, it will
4127 attempt to autoconfigure the TAPs. There are two parts to this:
4130 @item @emph{TAP discovery} ...
4131 After a JTAG reset (sometimes a system reset may be needed too),
4132 each TAP's data registers will hold the contents of either the
4133 IDCODE or BYPASS register.
4134 If JTAG communication is working, OpenOCD will see each TAP,
4135 and report what @option{-expected-id} to use with it.
4136 @item @emph{IR Length discovery} ...
4137 Unfortunately JTAG does not provide a reliable way to find out
4138 the value of the @option{-irlen} parameter to use with a TAP
4140 If OpenOCD can discover the length of a TAP's instruction
4141 register, it will report it.
4142 Otherwise you may need to consult vendor documentation, such
4143 as chip data sheets or BSDL files.
4146 In many cases your board will have a simple scan chain with just
4147 a single device. Here's what OpenOCD reported with one board
4148 that's a bit more complex:
4152 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4153 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4154 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4155 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4156 AUTO auto0.tap - use "... -irlen 4"
4157 AUTO auto1.tap - use "... -irlen 4"
4158 AUTO auto2.tap - use "... -irlen 6"
4159 no gdb ports allocated as no target has been specified
4162 Given that information, you should be able to either find some existing
4163 config files to use, or create your own. If you create your own, you
4164 would configure from the bottom up: first a @file{target.cfg} file
4165 with these TAPs, any targets associated with them, and any on-chip
4166 resources; then a @file{board.cfg} with off-chip resources, clocking,
4169 @anchor{dapdeclaration}
4170 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4171 @cindex DAP declaration
4173 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4174 no longer implicitly created together with the target. It must be
4175 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4176 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4177 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4179 The @command{dap} command group supports the following sub-commands:
4181 @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
4182 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4183 @var{dotted.name}. This also creates a new command (@command{dap_name})
4184 which is used for various purposes including additional configuration.
4185 There can only be one DAP for each JTAG tap in the system.
4187 A DAP may also provide optional @var{configparams}:
4190 @item @code{-ignore-syspwrupack}
4191 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4192 register during initial examination and when checking the sticky error bit.
4193 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4194 devices do not set the ack bit until sometime later.
4198 @deffn Command {dap names}
4199 This command returns a list of all registered DAP objects. It it useful mainly
4203 @deffn Command {dap info} [num]
4204 Displays the ROM table for MEM-AP @var{num},
4205 defaulting to the currently selected AP of the currently selected target.
4208 @deffn Command {dap init}
4209 Initialize all registered DAPs. This command is used internally
4210 during initialization. It can be issued at any time after the
4211 initialization, too.
4214 The following commands exist as subcommands of DAP instances:
4216 @deffn Command {$dap_name info} [num]
4217 Displays the ROM table for MEM-AP @var{num},
4218 defaulting to the currently selected AP.
4221 @deffn Command {$dap_name apid} [num]
4222 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4225 @anchor{DAP subcommand apreg}
4226 @deffn Command {$dap_name apreg} ap_num reg [value]
4227 Displays content of a register @var{reg} from AP @var{ap_num}
4228 or set a new value @var{value}.
4229 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4232 @deffn Command {$dap_name apsel} [num]
4233 Select AP @var{num}, defaulting to 0.
4236 @deffn Command {$dap_name dpreg} reg [value]
4237 Displays the content of DP register at address @var{reg}, or set it to a new
4240 In case of SWD, @var{reg} is a value in packed format
4241 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4242 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4244 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4245 background activity by OpenOCD while you are operating at such low-level.
4248 @deffn Command {$dap_name baseaddr} [num]
4249 Displays debug base address from MEM-AP @var{num},
4250 defaulting to the currently selected AP.
4253 @deffn Command {$dap_name memaccess} [value]
4254 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4255 memory bus access [0-255], giving additional time to respond to reads.
4256 If @var{value} is defined, first assigns that.
4259 @deffn Command {$dap_name apcsw} [value [mask]]
4260 Displays or changes CSW bit pattern for MEM-AP transfers.
4262 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4263 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4264 and the result is written to the real CSW register. All bits except dynamically
4265 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4266 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4269 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4270 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4273 kx.dap apcsw 0x2000000
4276 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4277 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4278 and leaves the rest of the pattern intact. It configures memory access through
4279 DCache on Cortex-M7.
4281 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4282 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4285 Another example clears SPROT bit and leaves the rest of pattern intact:
4287 set CSW_SPROT [expr 1 << 30]
4288 samv.dap apcsw 0 $CSW_SPROT
4291 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4292 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4294 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4295 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4296 example with a proper dap name:
4298 xxx.dap apcsw default
4302 @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
4303 Set/get quirks mode for TI TMS450/TMS570 processors
4308 @node CPU Configuration
4309 @chapter CPU Configuration
4312 This chapter discusses how to set up GDB debug targets for CPUs.
4313 You can also access these targets without GDB
4314 (@pxref{Architecture and Core Commands},
4315 and @ref{targetstatehandling,,Target State handling}) and
4316 through various kinds of NAND and NOR flash commands.
4317 If you have multiple CPUs you can have multiple such targets.
4319 We'll start by looking at how to examine the targets you have,
4320 then look at how to add one more target and how to configure it.
4322 @section Target List
4323 @cindex target, current
4324 @cindex target, list
4326 All targets that have been set up are part of a list,
4327 where each member has a name.
4328 That name should normally be the same as the TAP name.
4329 You can display the list with the @command{targets}
4331 This display often has only one CPU; here's what it might
4332 look like with more than one:
4334 TargetName Type Endian TapName State
4335 -- ------------------ ---------- ------ ------------------ ------------
4336 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4337 1 MyTarget cortex_m little mychip.foo tap-disabled
4340 One member of that list is the @dfn{current target}, which
4341 is implicitly referenced by many commands.
4342 It's the one marked with a @code{*} near the target name.
4343 In particular, memory addresses often refer to the address
4344 space seen by that current target.
4345 Commands like @command{mdw} (memory display words)
4346 and @command{flash erase_address} (erase NOR flash blocks)
4347 are examples; and there are many more.
4349 Several commands let you examine the list of targets:
4351 @deffn Command {target current}
4352 Returns the name of the current target.
4355 @deffn Command {target names}
4356 Lists the names of all current targets in the list.
4358 foreach t [target names] @{
4359 puts [format "Target: %s\n" $t]
4364 @c yep, "target list" would have been better.
4365 @c plus maybe "target setdefault".
4367 @deffn Command targets [name]
4368 @emph{Note: the name of this command is plural. Other target
4369 command names are singular.}
4371 With no parameter, this command displays a table of all known
4372 targets in a user friendly form.
4374 With a parameter, this command sets the current target to
4375 the given target with the given @var{name}; this is
4376 only relevant on boards which have more than one target.
4379 @section Target CPU Types
4383 Each target has a @dfn{CPU type}, as shown in the output of
4384 the @command{targets} command. You need to specify that type
4385 when calling @command{target create}.
4386 The CPU type indicates more than just the instruction set.
4387 It also indicates how that instruction set is implemented,
4388 what kind of debug support it integrates,
4389 whether it has an MMU (and if so, what kind),
4390 what core-specific commands may be available
4391 (@pxref{Architecture and Core Commands}),
4394 It's easy to see what target types are supported,
4395 since there's a command to list them.
4397 @anchor{targettypes}
4398 @deffn Command {target types}
4399 Lists all supported target types.
4400 At this writing, the supported CPU types are:
4403 @item @code{arm11} -- this is a generation of ARMv6 cores
4404 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4405 @item @code{arm7tdmi} -- this is an ARMv4 core
4406 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4407 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4408 @item @code{arm966e} -- this is an ARMv5 core
4409 @item @code{arm9tdmi} -- this is an ARMv4 core
4410 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4411 (Support for this is preliminary and incomplete.)
4412 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4413 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4414 compact Thumb2 instruction set.
4415 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4416 @item @code{dragonite} -- resembles arm966e
4417 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4418 (Support for this is still incomplete.)
4419 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4420 The current implementation supports eSi-32xx cores.
4421 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4422 @item @code{feroceon} -- resembles arm926
4423 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs.
4424 @item @code{mips_m4k} -- a MIPS core
4425 @item @code{xscale} -- this is actually an architecture,
4426 not a CPU type. It is based on the ARMv5 architecture.
4427 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4428 The current implementation supports three JTAG TAP cores:
4429 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4430 allowing access to physical memory addresses independently of CPU cores.
4432 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4433 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4434 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4436 And two debug interfaces cores:
4438 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4439 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project@comma{}dbg_interface})
4444 To avoid being confused by the variety of ARM based cores, remember
4445 this key point: @emph{ARM is a technology licencing company}.
4446 (See: @url{http://www.arm.com}.)
4447 The CPU name used by OpenOCD will reflect the CPU design that was
4448 licensed, not a vendor brand which incorporates that design.
4449 Name prefixes like arm7, arm9, arm11, and cortex
4450 reflect design generations;
4451 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4452 reflect an architecture version implemented by a CPU design.
4454 @anchor{targetconfiguration}
4455 @section Target Configuration
4457 Before creating a ``target'', you must have added its TAP to the scan chain.
4458 When you've added that TAP, you will have a @code{dotted.name}
4459 which is used to set up the CPU support.
4460 The chip-specific configuration file will normally configure its CPU(s)
4461 right after it adds all of the chip's TAPs to the scan chain.
4463 Although you can set up a target in one step, it's often clearer if you
4464 use shorter commands and do it in two steps: create it, then configure
4466 All operations on the target after it's created will use a new
4467 command, created as part of target creation.
4469 The two main things to configure after target creation are
4470 a work area, which usually has target-specific defaults even
4471 if the board setup code overrides them later;
4472 and event handlers (@pxref{targetevents,,Target Events}), which tend
4473 to be much more board-specific.
4474 The key steps you use might look something like this
4477 dap create mychip.dap -chain-position mychip.cpu
4478 target create MyTarget cortex_m -dap mychip.dap
4479 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4480 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4481 MyTarget configure -event reset-init @{ myboard_reinit @}
4484 You should specify a working area if you can; typically it uses some
4486 Such a working area can speed up many things, including bulk
4487 writes to target memory;
4488 flash operations like checking to see if memory needs to be erased;
4489 GDB memory checksumming;
4493 On more complex chips, the work area can become
4494 inaccessible when application code
4495 (such as an operating system)
4496 enables or disables the MMU.
4497 For example, the particular MMU context used to access the virtual
4498 address will probably matter ... and that context might not have
4499 easy access to other addresses needed.
4500 At this writing, OpenOCD doesn't have much MMU intelligence.
4503 It's often very useful to define a @code{reset-init} event handler.
4504 For systems that are normally used with a boot loader,
4505 common tasks include updating clocks and initializing memory
4507 That may be needed to let you write the boot loader into flash,
4508 in order to ``de-brick'' your board; or to load programs into
4509 external DDR memory without having run the boot loader.
4511 @deffn Command {target create} target_name type configparams...
4512 This command creates a GDB debug target that refers to a specific JTAG tap.
4513 It enters that target into a list, and creates a new
4514 command (@command{@var{target_name}}) which is used for various
4515 purposes including additional configuration.
4518 @item @var{target_name} ... is the name of the debug target.
4519 By convention this should be the same as the @emph{dotted.name}
4520 of the TAP associated with this target, which must be specified here
4521 using the @code{-chain-position @var{dotted.name}} configparam.
4523 This name is also used to create the target object command,
4524 referred to here as @command{$target_name},
4525 and in other places the target needs to be identified.
4526 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4527 @item @var{configparams} ... all parameters accepted by
4528 @command{$target_name configure} are permitted.
4529 If the target is big-endian, set it here with @code{-endian big}.
4531 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4532 @code{-dap @var{dap_name}} here.
4536 @deffn Command {$target_name configure} configparams...
4537 The options accepted by this command may also be
4538 specified as parameters to @command{target create}.
4539 Their values can later be queried one at a time by
4540 using the @command{$target_name cget} command.
4542 @emph{Warning:} changing some of these after setup is dangerous.
4543 For example, moving a target from one TAP to another;
4544 and changing its endianness.
4548 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4549 used to access this target.
4551 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4552 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4553 create and manage DAP instances.
4555 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4556 whether the CPU uses big or little endian conventions
4558 @item @code{-event} @var{event_name} @var{event_body} --
4559 @xref{targetevents,,Target Events}.
4560 Note that this updates a list of named event handlers.
4561 Calling this twice with two different event names assigns
4562 two different handlers, but calling it twice with the
4563 same event name assigns only one handler.
4565 Current target is temporarily overridden to the event issuing target
4566 before handler code starts and switched back after handler is done.
4568 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4569 whether the work area gets backed up; by default,
4570 @emph{it is not backed up.}
4571 When possible, use a working_area that doesn't need to be backed up,
4572 since performing a backup slows down operations.
4573 For example, the beginning of an SRAM block is likely to
4574 be used by most build systems, but the end is often unused.
4576 @item @code{-work-area-size} @var{size} -- specify work are size,
4577 in bytes. The same size applies regardless of whether its physical
4578 or virtual address is being used.
4580 @item @code{-work-area-phys} @var{address} -- set the work area
4581 base @var{address} to be used when no MMU is active.
4583 @item @code{-work-area-virt} @var{address} -- set the work area
4584 base @var{address} to be used when an MMU is active.
4585 @emph{Do not specify a value for this except on targets with an MMU.}
4586 The value should normally correspond to a static mapping for the
4587 @code{-work-area-phys} address, set up by the current operating system.
4590 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4591 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4592 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4593 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}
4594 @xref{gdbrtossupport,,RTOS Support}.
4596 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4597 scan and after a reset. A manual call to arp_examine is required to
4598 access the target for debugging.
4600 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4601 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4602 Use this option with systems where multiple, independent cores are connected
4603 to separate access ports of the same DAP.
4605 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4606 to the target. Currently, only the @code{aarch64} target makes use of this option,
4607 where it is a mandatory configuration for the target run control.
4608 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4609 for instruction on how to declare and control a CTI instance.
4611 @anchor{gdbportoverride}
4612 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4613 possible values of the parameter @var{number}, which are not only numeric values.
4614 Use this option to override, for this target only, the global parameter set with
4615 command @command{gdb_port}.
4616 @xref{gdb_port,,command gdb_port}.
4620 @section Other $target_name Commands
4621 @cindex object command
4623 The Tcl/Tk language has the concept of object commands,
4624 and OpenOCD adopts that same model for targets.
4626 A good Tk example is a on screen button.
4627 Once a button is created a button
4628 has a name (a path in Tk terms) and that name is useable as a first
4629 class command. For example in Tk, one can create a button and later
4630 configure it like this:
4634 button .foobar -background red -command @{ foo @}
4636 .foobar configure -foreground blue
4638 set x [.foobar cget -background]
4640 puts [format "The button is %s" $x]
4643 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4644 button, and its object commands are invoked the same way.
4647 str912.cpu mww 0x1234 0x42
4648 omap3530.cpu mww 0x5555 123
4651 The commands supported by OpenOCD target objects are:
4653 @deffn Command {$target_name arp_examine} @option{allow-defer}
4654 @deffnx Command {$target_name arp_halt}
4655 @deffnx Command {$target_name arp_poll}
4656 @deffnx Command {$target_name arp_reset}
4657 @deffnx Command {$target_name arp_waitstate}
4658 Internal OpenOCD scripts (most notably @file{startup.tcl})
4659 use these to deal with specific reset cases.
4660 They are not otherwise documented here.
4663 @deffn Command {$target_name array2mem} arrayname width address count
4664 @deffnx Command {$target_name mem2array} arrayname width address count
4665 These provide an efficient script-oriented interface to memory.
4666 The @code{array2mem} primitive writes bytes, halfwords, or words;
4667 while @code{mem2array} reads them.
4668 In both cases, the TCL side uses an array, and
4669 the target side uses raw memory.
4671 The efficiency comes from enabling the use of
4672 bulk JTAG data transfer operations.
4673 The script orientation comes from working with data
4674 values that are packaged for use by TCL scripts;
4675 @command{mdw} type primitives only print data they retrieve,
4676 and neither store nor return those values.
4679 @item @var{arrayname} ... is the name of an array variable
4680 @item @var{width} ... is 8/16/32 - indicating the memory access size
4681 @item @var{address} ... is the target memory address
4682 @item @var{count} ... is the number of elements to process
4686 @deffn Command {$target_name cget} queryparm
4687 Each configuration parameter accepted by
4688 @command{$target_name configure}
4689 can be individually queried, to return its current value.
4690 The @var{queryparm} is a parameter name
4691 accepted by that command, such as @code{-work-area-phys}.
4692 There are a few special cases:
4695 @item @code{-event} @var{event_name} -- returns the handler for the
4696 event named @var{event_name}.
4697 This is a special case because setting a handler requires
4699 @item @code{-type} -- returns the target type.
4700 This is a special case because this is set using
4701 @command{target create} and can't be changed
4702 using @command{$target_name configure}.
4705 For example, if you wanted to summarize information about
4706 all the targets you might use something like this:
4709 foreach name [target names] @{
4710 set y [$name cget -endian]
4711 set z [$name cget -type]
4712 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4718 @anchor{targetcurstate}
4719 @deffn Command {$target_name curstate}
4720 Displays the current target state:
4721 @code{debug-running},
4724 @code{running}, or @code{unknown}.
4725 (Also, @pxref{eventpolling,,Event Polling}.)
4728 @deffn Command {$target_name eventlist}
4729 Displays a table listing all event handlers
4730 currently associated with this target.
4731 @xref{targetevents,,Target Events}.
4734 @deffn Command {$target_name invoke-event} event_name
4735 Invokes the handler for the event named @var{event_name}.
4736 (This is primarily intended for use by OpenOCD framework
4737 code, for example by the reset code in @file{startup.tcl}.)
4740 @deffn Command {$target_name mdd} [phys] addr [count]
4741 @deffnx Command {$target_name mdw} [phys] addr [count]
4742 @deffnx Command {$target_name mdh} [phys] addr [count]
4743 @deffnx Command {$target_name mdb} [phys] addr [count]
4744 Display contents of address @var{addr}, as
4745 64-bit doublewords (@command{mdd}),
4746 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4747 or 8-bit bytes (@command{mdb}).
4748 When the current target has an MMU which is present and active,
4749 @var{addr} is interpreted as a virtual address.
4750 Otherwise, or if the optional @var{phys} flag is specified,
4751 @var{addr} is interpreted as a physical address.
4752 If @var{count} is specified, displays that many units.
4753 (If you want to manipulate the data instead of displaying it,
4754 see the @code{mem2array} primitives.)
4757 @deffn Command {$target_name mwd} [phys] addr doubleword [count]
4758 @deffnx Command {$target_name mww} [phys] addr word [count]
4759 @deffnx Command {$target_name mwh} [phys] addr halfword [count]
4760 @deffnx Command {$target_name mwb} [phys] addr byte [count]
4761 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
4762 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
4763 at the specified address @var{addr}.
4764 When the current target has an MMU which is present and active,
4765 @var{addr} is interpreted as a virtual address.
4766 Otherwise, or if the optional @var{phys} flag is specified,
4767 @var{addr} is interpreted as a physical address.
4768 If @var{count} is specified, fills that many units of consecutive address.
4771 @anchor{targetevents}
4772 @section Target Events
4773 @cindex target events
4775 At various times, certain things can happen, or you want them to happen.
4778 @item What should happen when GDB connects? Should your target reset?
4779 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4780 @item Is using SRST appropriate (and possible) on your system?
4781 Or instead of that, do you need to issue JTAG commands to trigger reset?
4782 SRST usually resets everything on the scan chain, which can be inappropriate.
4783 @item During reset, do you need to write to certain memory locations
4784 to set up system clocks or
4785 to reconfigure the SDRAM?
4786 How about configuring the watchdog timer, or other peripherals,
4787 to stop running while you hold the core stopped for debugging?
4790 All of the above items can be addressed by target event handlers.
4791 These are set up by @command{$target_name configure -event} or
4792 @command{target create ... -event}.
4794 The programmer's model matches the @code{-command} option used in Tcl/Tk
4795 buttons and events. The two examples below act the same, but one creates
4796 and invokes a small procedure while the other inlines it.
4799 proc my_init_proc @{ @} @{
4800 echo "Disabling watchdog..."
4801 mww 0xfffffd44 0x00008000
4803 mychip.cpu configure -event reset-init my_init_proc
4804 mychip.cpu configure -event reset-init @{
4805 echo "Disabling watchdog..."
4806 mww 0xfffffd44 0x00008000
4810 The following target events are defined:
4813 @item @b{debug-halted}
4814 @* The target has halted for debug reasons (i.e.: breakpoint)
4815 @item @b{debug-resumed}
4816 @* The target has resumed (i.e.: GDB said run)
4817 @item @b{early-halted}
4818 @* Occurs early in the halt process
4819 @item @b{examine-start}
4820 @* Before target examine is called.
4821 @item @b{examine-end}
4822 @* After target examine is called with no errors.
4823 @item @b{gdb-attach}
4824 @* When GDB connects. Issued before any GDB communication with the target
4825 starts. GDB expects the target is halted during attachment.
4826 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
4827 connect GDB to running target.
4828 The event can be also used to set up the target so it is possible to probe flash.
4829 Probing flash is necessary during GDB connect if you want to use
4830 @pxref{programmingusinggdb,,programming using GDB}.
4831 Another use of the flash memory map is for GDB to automatically choose
4832 hardware or software breakpoints depending on whether the breakpoint
4833 is in RAM or read only memory.
4834 Default is @code{halt}
4835 @item @b{gdb-detach}
4836 @* When GDB disconnects
4838 @* When the target has halted and GDB is not doing anything (see early halt)
4839 @item @b{gdb-flash-erase-start}
4840 @* Before the GDB flash process tries to erase the flash (default is
4842 @item @b{gdb-flash-erase-end}
4843 @* After the GDB flash process has finished erasing the flash
4844 @item @b{gdb-flash-write-start}
4845 @* Before GDB writes to the flash
4846 @item @b{gdb-flash-write-end}
4847 @* After GDB writes to the flash (default is @code{reset halt})
4849 @* Before the target steps, GDB is trying to start/resume the target
4851 @* The target has halted
4852 @item @b{reset-assert-pre}
4853 @* Issued as part of @command{reset} processing
4854 after @command{reset-start} was triggered
4855 but before either SRST alone is asserted on the scan chain,
4856 or @code{reset-assert} is triggered.
4857 @item @b{reset-assert}
4858 @* Issued as part of @command{reset} processing
4859 after @command{reset-assert-pre} was triggered.
4860 When such a handler is present, cores which support this event will use
4861 it instead of asserting SRST.
4862 This support is essential for debugging with JTAG interfaces which
4863 don't include an SRST line (JTAG doesn't require SRST), and for
4864 selective reset on scan chains that have multiple targets.
4865 @item @b{reset-assert-post}
4866 @* Issued as part of @command{reset} processing
4867 after @code{reset-assert} has been triggered.
4868 or the target asserted SRST on the entire scan chain.
4869 @item @b{reset-deassert-pre}
4870 @* Issued as part of @command{reset} processing
4871 after @code{reset-assert-post} has been triggered.
4872 @item @b{reset-deassert-post}
4873 @* Issued as part of @command{reset} processing
4874 after @code{reset-deassert-pre} has been triggered
4875 and (if the target is using it) after SRST has been
4876 released on the scan chain.
4878 @* Issued as the final step in @command{reset} processing.
4879 @item @b{reset-init}
4880 @* Used by @b{reset init} command for board-specific initialization.
4881 This event fires after @emph{reset-deassert-post}.
4883 This is where you would configure PLLs and clocking, set up DRAM so
4884 you can download programs that don't fit in on-chip SRAM, set up pin
4885 multiplexing, and so on.
4886 (You may be able to switch to a fast JTAG clock rate here, after
4887 the target clocks are fully set up.)
4888 @item @b{reset-start}
4889 @* Issued as the first step in @command{reset} processing
4890 before @command{reset-assert-pre} is called.
4892 This is the most robust place to use @command{jtag_rclk}
4893 or @command{adapter speed} to switch to a low JTAG clock rate,
4894 when reset disables PLLs needed to use a fast clock.
4895 @item @b{resume-start}
4896 @* Before any target is resumed
4897 @item @b{resume-end}
4898 @* After all targets have resumed
4900 @* Target has resumed
4901 @item @b{trace-config}
4902 @* After target hardware trace configuration was changed
4905 @node Flash Commands
4906 @chapter Flash Commands
4908 OpenOCD has different commands for NOR and NAND flash;
4909 the ``flash'' command works with NOR flash, while
4910 the ``nand'' command works with NAND flash.
4911 This partially reflects different hardware technologies:
4912 NOR flash usually supports direct CPU instruction and data bus access,
4913 while data from a NAND flash must be copied to memory before it can be
4914 used. (SPI flash must also be copied to memory before use.)
4915 However, the documentation also uses ``flash'' as a generic term;
4916 for example, ``Put flash configuration in board-specific files''.
4920 @item Configure via the command @command{flash bank}
4921 @* Do this in a board-specific configuration file,
4922 passing parameters as needed by the driver.
4923 @item Operate on the flash via @command{flash subcommand}
4924 @* Often commands to manipulate the flash are typed by a human, or run
4925 via a script in some automated way. Common tasks include writing a
4926 boot loader, operating system, or other data.
4928 @* Flashing via GDB requires the flash be configured via ``flash
4929 bank'', and the GDB flash features be enabled.
4930 @xref{gdbconfiguration,,GDB Configuration}.
4933 Many CPUs have the ability to ``boot'' from the first flash bank.
4934 This means that misprogramming that bank can ``brick'' a system,
4935 so that it can't boot.
4936 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4937 board by (re)installing working boot firmware.
4939 @anchor{norconfiguration}
4940 @section Flash Configuration Commands
4941 @cindex flash configuration
4943 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4944 Configures a flash bank which provides persistent storage
4945 for addresses from @math{base} to @math{base + size - 1}.
4946 These banks will often be visible to GDB through the target's memory map.
4947 In some cases, configuring a flash bank will activate extra commands;
4948 see the driver-specific documentation.
4951 @item @var{name} ... may be used to reference the flash bank
4952 in other flash commands. A number is also available.
4953 @item @var{driver} ... identifies the controller driver
4954 associated with the flash bank being declared.
4955 This is usually @code{cfi} for external flash, or else
4956 the name of a microcontroller with embedded flash memory.
4957 @xref{flashdriverlist,,Flash Driver List}.
4958 @item @var{base} ... Base address of the flash chip.
4959 @item @var{size} ... Size of the chip, in bytes.
4960 For some drivers, this value is detected from the hardware.
4961 @item @var{chip_width} ... Width of the flash chip, in bytes;
4962 ignored for most microcontroller drivers.
4963 @item @var{bus_width} ... Width of the data bus used to access the
4964 chip, in bytes; ignored for most microcontroller drivers.
4965 @item @var{target} ... Names the target used to issue
4966 commands to the flash controller.
4967 @comment Actually, it's currently a controller-specific parameter...
4968 @item @var{driver_options} ... drivers may support, or require,
4969 additional parameters. See the driver-specific documentation
4970 for more information.
4973 This command is not available after OpenOCD initialization has completed.
4974 Use it in board specific configuration files, not interactively.
4978 @comment less confusing would be: "flash list" (like "nand list")
4979 @deffn Command {flash banks}
4980 Prints a one-line summary of each device that was
4981 declared using @command{flash bank}, numbered from zero.
4982 Note that this is the @emph{plural} form;
4983 the @emph{singular} form is a very different command.
4986 @deffn Command {flash list}
4987 Retrieves a list of associative arrays for each device that was
4988 declared using @command{flash bank}, numbered from zero.
4989 This returned list can be manipulated easily from within scripts.
4992 @deffn Command {flash probe} num
4993 Identify the flash, or validate the parameters of the configured flash. Operation
4994 depends on the flash type.
4995 The @var{num} parameter is a value shown by @command{flash banks}.
4996 Most flash commands will implicitly @emph{autoprobe} the bank;
4997 flash drivers can distinguish between probing and autoprobing,
4998 but most don't bother.
5001 @section Preparing a Target before Flash Programming
5003 The target device should be in well defined state before the flash programming
5006 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5007 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5008 until the programming session is finished.
5010 If you use @ref{programmingusinggdb,,Programming using GDB},
5011 the target is prepared automatically in the event gdb-flash-erase-start
5013 The jimtcl script @command{program} calls @command{reset init} explicitly.
5015 @section Erasing, Reading, Writing to Flash
5016 @cindex flash erasing
5017 @cindex flash reading
5018 @cindex flash writing
5019 @cindex flash programming
5020 @anchor{flashprogrammingcommands}
5022 One feature distinguishing NOR flash from NAND or serial flash technologies
5023 is that for read access, it acts exactly like any other addressable memory.
5024 This means you can use normal memory read commands like @command{mdw} or
5025 @command{dump_image} with it, with no special @command{flash} subcommands.
5026 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5028 Write access works differently. Flash memory normally needs to be erased
5029 before it's written. Erasing a sector turns all of its bits to ones, and
5030 writing can turn ones into zeroes. This is why there are special commands
5031 for interactive erasing and writing, and why GDB needs to know which parts
5032 of the address space hold NOR flash memory.
5035 Most of these erase and write commands leverage the fact that NOR flash
5036 chips consume target address space. They implicitly refer to the current
5037 JTAG target, and map from an address in that target's address space
5038 back to a flash bank.
5039 @comment In May 2009, those mappings may fail if any bank associated
5040 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5041 A few commands use abstract addressing based on bank and sector numbers,
5042 and don't depend on searching the current target and its address space.
5043 Avoid confusing the two command models.
5046 Some flash chips implement software protection against accidental writes,
5047 since such buggy writes could in some cases ``brick'' a system.
5048 For such systems, erasing and writing may require sector protection to be
5050 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5051 and AT91SAM7 on-chip flash.
5052 @xref{flashprotect,,flash protect}.
5054 @deffn Command {flash erase_sector} num first last
5055 Erase sectors in bank @var{num}, starting at sector @var{first}
5056 up to and including @var{last}.
5057 Sector numbering starts at 0.
5058 Providing a @var{last} sector of @option{last}
5059 specifies "to the end of the flash bank".
5060 The @var{num} parameter is a value shown by @command{flash banks}.
5063 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
5064 Erase sectors starting at @var{address} for @var{length} bytes.
5065 Unless @option{pad} is specified, @math{address} must begin a
5066 flash sector, and @math{address + length - 1} must end a sector.
5067 Specifying @option{pad} erases extra data at the beginning and/or
5068 end of the specified region, as needed to erase only full sectors.
5069 The flash bank to use is inferred from the @var{address}, and
5070 the specified length must stay within that bank.
5071 As a special case, when @var{length} is zero and @var{address} is
5072 the start of the bank, the whole flash is erased.
5073 If @option{unlock} is specified, then the flash is unprotected
5074 before erase starts.
5077 @deffn Command {flash fillw} address word length
5078 @deffnx Command {flash fillh} address halfword length
5079 @deffnx Command {flash fillb} address byte length
5080 Fills flash memory with the specified @var{word} (32 bits),
5081 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5082 starting at @var{address} and continuing
5083 for @var{length} units (word/halfword/byte).
5084 No erasure is done before writing; when needed, that must be done
5085 before issuing this command.
5086 Writes are done in blocks of up to 1024 bytes, and each write is
5087 verified by reading back the data and comparing it to what was written.
5088 The flash bank to use is inferred from the @var{address} of
5089 each block, and the specified length must stay within that bank.
5091 @comment no current checks for errors if fill blocks touch multiple banks!
5093 @deffn Command {flash write_bank} num filename [offset]
5094 Write the binary @file{filename} to flash bank @var{num},
5095 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5096 is omitted, start at the beginning of the flash bank.
5097 The @var{num} parameter is a value shown by @command{flash banks}.
5100 @deffn Command {flash read_bank} num filename [offset [length]]
5101 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5102 and write the contents to the binary @file{filename}. If @var{offset} is
5103 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5104 read the remaining bytes from the flash bank.
5105 The @var{num} parameter is a value shown by @command{flash banks}.
5108 @deffn Command {flash verify_bank} num filename [offset]
5109 Compare the contents of the binary file @var{filename} with the contents of the
5110 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5111 start at the beginning of the flash bank. Fail if the contents do not match.
5112 The @var{num} parameter is a value shown by @command{flash banks}.
5115 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
5116 Write the image @file{filename} to the current target's flash bank(s).
5117 Only loadable sections from the image are written.
5118 A relocation @var{offset} may be specified, in which case it is added
5119 to the base address for each section in the image.
5120 The file [@var{type}] can be specified
5121 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5122 @option{elf} (ELF file), @option{s19} (Motorola s19).
5123 @option{mem}, or @option{builder}.
5124 The relevant flash sectors will be erased prior to programming
5125 if the @option{erase} parameter is given. If @option{unlock} is
5126 provided, then the flash banks are unlocked before erase and
5127 program. The flash bank to use is inferred from the address of
5131 Be careful using the @option{erase} flag when the flash is holding
5132 data you want to preserve.
5133 Portions of the flash outside those described in the image's
5134 sections might be erased with no notice.
5137 When a section of the image being written does not fill out all the
5138 sectors it uses, the unwritten parts of those sectors are necessarily
5139 also erased, because sectors can't be partially erased.
5141 Data stored in sector "holes" between image sections are also affected.
5142 For example, "@command{flash write_image erase ...}" of an image with
5143 one byte at the beginning of a flash bank and one byte at the end
5144 erases the entire bank -- not just the two sectors being written.
5146 Also, when flash protection is important, you must re-apply it after
5147 it has been removed by the @option{unlock} flag.
5152 @section Other Flash commands
5153 @cindex flash protection
5155 @deffn Command {flash erase_check} num
5156 Check erase state of sectors in flash bank @var{num},
5157 and display that status.
5158 The @var{num} parameter is a value shown by @command{flash banks}.
5161 @deffn Command {flash info} num [sectors]
5162 Print info about flash bank @var{num}, a list of protection blocks
5163 and their status. Use @option{sectors} to show a list of sectors instead.
5165 The @var{num} parameter is a value shown by @command{flash banks}.
5166 This command will first query the hardware, it does not print cached
5167 and possibly stale information.
5170 @anchor{flashprotect}
5171 @deffn Command {flash protect} num first last (@option{on}|@option{off})
5172 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5173 in flash bank @var{num}, starting at protection block @var{first}
5174 and continuing up to and including @var{last}.
5175 Providing a @var{last} block of @option{last}
5176 specifies "to the end of the flash bank".
5177 The @var{num} parameter is a value shown by @command{flash banks}.
5178 The protection block is usually identical to a flash sector.
5179 Some devices may utilize a protection block distinct from flash sector.
5180 See @command{flash info} for a list of protection blocks.
5183 @deffn Command {flash padded_value} num value
5184 Sets the default value used for padding any image sections, This should
5185 normally match the flash bank erased value. If not specified by this
5186 command or the flash driver then it defaults to 0xff.
5190 @deffn Command {program} filename [preverify] [verify] [reset] [exit] [offset]
5191 This is a helper script that simplifies using OpenOCD as a standalone
5192 programmer. The only required parameter is @option{filename}, the others are optional.
5193 @xref{Flash Programming}.
5196 @anchor{flashdriverlist}
5197 @section Flash Driver List
5198 As noted above, the @command{flash bank} command requires a driver name,
5199 and allows driver-specific options and behaviors.
5200 Some drivers also activate driver-specific commands.
5202 @deffn {Flash Driver} virtual
5203 This is a special driver that maps a previously defined bank to another
5204 address. All bank settings will be copied from the master physical bank.
5206 The @var{virtual} driver defines one mandatory parameters,
5209 @item @var{master_bank} The bank that this virtual address refers to.
5212 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5213 the flash bank defined at address 0x1fc00000. Any command executed on
5214 the virtual banks is actually performed on the physical banks.
5216 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5217 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5218 $_TARGETNAME $_FLASHNAME
5219 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5220 $_TARGETNAME $_FLASHNAME
5224 @subsection External Flash
5226 @deffn {Flash Driver} cfi
5227 @cindex Common Flash Interface
5229 The ``Common Flash Interface'' (CFI) is the main standard for
5230 external NOR flash chips, each of which connects to a
5231 specific external chip select on the CPU.
5232 Frequently the first such chip is used to boot the system.
5233 Your board's @code{reset-init} handler might need to
5234 configure additional chip selects using other commands (like: @command{mww} to
5235 configure a bus and its timings), or
5236 perhaps configure a GPIO pin that controls the ``write protect'' pin
5238 The CFI driver can use a target-specific working area to significantly
5241 The CFI driver can accept the following optional parameters, in any order:
5244 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5245 like AM29LV010 and similar types.
5246 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5247 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5248 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5249 swapped when writing data values (i.e. not CFI commands).
5252 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5253 wide on a sixteen bit bus:
5256 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5257 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5260 To configure one bank of 32 MBytes
5261 built from two sixteen bit (two byte) wide parts wired in parallel
5262 to create a thirty-two bit (four byte) bus with doubled throughput:
5265 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5268 @c "cfi part_id" disabled
5271 @deffn {Flash Driver} jtagspi
5272 @cindex Generic JTAG2SPI driver
5276 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5277 SPI flash connected to them. To access this flash from the host, the device
5278 is first programmed with a special proxy bitstream that
5279 exposes the SPI flash on the device's JTAG interface. The flash can then be
5280 accessed through JTAG.
5282 Since signaling between JTAG and SPI is compatible, all that is required for
5283 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5284 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5285 a bitstream for several Xilinx FPGAs can be found in
5286 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5287 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5289 This flash bank driver requires a target on a JTAG tap and will access that
5290 tap directly. Since no support from the target is needed, the target can be a
5291 "testee" dummy. Since the target does not expose the flash memory
5292 mapping, target commands that would otherwise be expected to access the flash
5293 will not work. These include all @command{*_image} and
5294 @command{$target_name m*} commands as well as @command{program}. Equivalent
5295 functionality is available through the @command{flash write_bank},
5296 @command{flash read_bank}, and @command{flash verify_bank} commands.
5299 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5300 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5301 @var{USER1} instruction.
5305 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5306 set _XILINX_USER1 0x02
5307 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5308 $_TARGETNAME $_XILINX_USER1
5312 @deffn {Flash Driver} xcf
5313 @cindex Xilinx Platform flash driver
5315 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5316 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5317 only difference is special registers controlling its FPGA specific behavior.
5318 They must be properly configured for successful FPGA loading using
5319 additional @var{xcf} driver command:
5321 @deffn Command {xcf ccb} <bank_id>
5322 command accepts additional parameters:
5324 @item @var{external|internal} ... selects clock source.
5325 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5326 @item @var{slave|master} ... selects slave of master mode for flash device.
5327 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5331 xcf ccb 0 external parallel slave 40
5333 All of them must be specified even if clock frequency is pointless
5334 in slave mode. If only bank id specified than command prints current
5335 CCB register value. Note: there is no need to write this register
5336 every time you erase/program data sectors because it stores in
5340 @deffn Command {xcf configure} <bank_id>
5341 Initiates FPGA loading procedure. Useful if your board has no "configure"
5348 Additional driver notes:
5350 @item Only single revision supported.
5351 @item Driver automatically detects need of bit reverse, but
5352 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5353 (Intel hex) file types supported.
5354 @item For additional info check xapp972.pdf and ug380.pdf.
5358 @deffn {Flash Driver} lpcspifi
5359 @cindex NXP SPI Flash Interface
5362 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5363 Flash Interface (SPIFI) peripheral that can drive and provide
5364 memory mapped access to external SPI flash devices.
5366 The lpcspifi driver initializes this interface and provides
5367 program and erase functionality for these serial flash devices.
5368 Use of this driver @b{requires} a working area of at least 1kB
5369 to be configured on the target device; more than this will
5370 significantly reduce flash programming times.
5372 The setup command only requires the @var{base} parameter. All
5373 other parameters are ignored, and the flash size and layout
5374 are configured by the driver.
5377 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5382 @deffn {Flash Driver} stmsmi
5383 @cindex STMicroelectronics Serial Memory Interface
5386 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5387 SPEAr MPU family) include a proprietary
5388 ``Serial Memory Interface'' (SMI) controller able to drive external
5390 Depending on specific device and board configuration, up to 4 external
5391 flash devices can be connected.
5393 SMI makes the flash content directly accessible in the CPU address
5394 space; each external device is mapped in a memory bank.
5395 CPU can directly read data, execute code and boot from SMI banks.
5396 Normal OpenOCD commands like @command{mdw} can be used to display
5399 The setup command only requires the @var{base} parameter in order
5400 to identify the memory bank.
5401 All other parameters are ignored. Additional information, like
5402 flash size, are detected automatically.
5405 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5410 @deffn {Flash Driver} mrvlqspi
5411 This driver supports QSPI flash controller of Marvell's Wireless
5412 Microcontroller platform.
5414 The flash size is autodetected based on the table of known JEDEC IDs
5415 hardcoded in the OpenOCD sources.
5418 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5423 @deffn {Flash Driver} ath79
5424 @cindex Atheros ath79 SPI driver
5426 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5428 On reset a SPI flash connected to the first chip select (CS0) is made
5429 directly read-accessible in the CPU address space (up to 16MBytes)
5430 and is usually used to store the bootloader and operating system.
5431 Normal OpenOCD commands like @command{mdw} can be used to display
5432 the flash content while it is in memory-mapped mode (only the first
5433 4MBytes are accessible without additional configuration on reset).
5435 The setup command only requires the @var{base} parameter in order
5436 to identify the memory bank. The actual value for the base address
5437 is not otherwise used by the driver. However the mapping is passed
5438 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5439 address should be the actual memory mapped base address. For unmapped
5440 chipselects (CS1 and CS2) care should be taken to use a base address
5441 that does not overlap with real memory regions.
5442 Additional information, like flash size, are detected automatically.
5443 An optional additional parameter sets the chipselect for the bank,
5444 with the default CS0.
5445 CS1 and CS2 require additional GPIO setup before they can be used
5446 since the alternate function must be enabled on the GPIO pin
5447 CS1/CS2 is routed to on the given SoC.
5450 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
5452 # When using multiple chipselects the base should be different for each,
5453 # otherwise the write_image command is not able to distinguish the
5455 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
5456 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5457 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5462 @deffn {Flash Driver} fespi
5463 @cindex Freedom E SPI
5466 SiFive's Freedom E SPI controller, used in HiFive and other boards.
5469 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
5473 @subsection Internal Flash (Microcontrollers)
5475 @deffn {Flash Driver} aduc702x
5476 The ADUC702x analog microcontrollers from Analog Devices
5477 include internal flash and use ARM7TDMI cores.
5478 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5479 The setup command only requires the @var{target} argument
5480 since all devices in this family have the same memory layout.
5483 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5487 @deffn {Flash Driver} ambiqmicro
5490 All members of the Apollo microcontroller family from
5491 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5492 The host connects over USB to an FTDI interface that communicates
5493 with the target using SWD.
5495 The @var{ambiqmicro} driver reads the Chip Information Register detect
5496 the device class of the MCU.
5497 The Flash and SRAM sizes directly follow device class, and are used
5498 to set up the flash banks.
5499 If this fails, the driver will use default values set to the minimum
5500 sizes of an Apollo chip.
5502 All Apollo chips have two flash banks of the same size.
5503 In all cases the first flash bank starts at location 0,
5504 and the second bank starts after the first.
5508 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5509 # Flash bank 1 - same size as bank0, starts after bank 0.
5510 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5514 Flash is programmed using custom entry points into the bootloader.
5515 This is the only way to program the flash as no flash control registers
5516 are available to the user.
5518 The @var{ambiqmicro} driver adds some additional commands:
5520 @deffn Command {ambiqmicro mass_erase} <bank>
5523 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
5526 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
5527 Program OTP is a one time operation to create write protected flash.
5528 The user writes sectors to SRAM starting at 0x10000010.
5529 Program OTP will write these sectors from SRAM to flash, and write protect
5535 @deffn {Flash Driver} at91samd
5537 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
5538 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5540 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
5542 The devices have one flash bank:
5545 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
5548 @deffn Command {at91samd chip-erase}
5549 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5550 used to erase a chip back to its factory state and does not require the
5551 processor to be halted.
5554 @deffn Command {at91samd set-security}
5555 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5556 to the Flash and can only be undone by using the chip-erase command which
5557 erases the Flash contents and turns off the security bit. Warning: at this
5558 time, openocd will not be able to communicate with a secured chip and it is
5559 therefore not possible to chip-erase it without using another tool.
5562 at91samd set-security enable
5566 @deffn Command {at91samd eeprom}
5567 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5568 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5569 must be one of the permitted sizes according to the datasheet. Settings are
5570 written immediately but only take effect on MCU reset. EEPROM emulation
5571 requires additional firmware support and the minimum EEPROM size may not be
5572 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5573 in order to disable this feature.
5577 at91samd eeprom 1024
5581 @deffn Command {at91samd bootloader}
5582 Shows or sets the bootloader size configuration, stored in the User Row of the
5583 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5584 must be specified in bytes and it must be one of the permitted sizes according
5585 to the datasheet. Settings are written immediately but only take effect on
5586 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5590 at91samd bootloader 16384
5594 @deffn Command {at91samd dsu_reset_deassert}
5595 This command releases internal reset held by DSU
5596 and prepares reset vector catch in case of reset halt.
5597 Command is used internally in event event reset-deassert-post.
5600 @deffn Command {at91samd nvmuserrow}
5601 Writes or reads the entire 64 bit wide NVM user row register which is located at
5602 0x804000. This register includes various fuses lock-bits and factory calibration
5603 data. Reading the register is done by invoking this command without any
5604 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
5605 is the register value to be written and the second one is an optional changemask.
5606 Every bit which value in changemask is 0 will stay unchanged. The lock- and
5607 reserved-bits are masked out and cannot be changed.
5611 >at91samd nvmuserrow
5612 NVMUSERROW: 0xFFFFFC5DD8E0C788
5613 # Write 0xFFFFFC5DD8E0C788 to user row
5614 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
5615 # Write 0x12300 to user row but leave other bits and low byte unchanged
5616 >at91samd nvmuserrow 0x12345 0xFFF00
5623 @deffn {Flash Driver} at91sam3
5625 All members of the AT91SAM3 microcontroller family from
5626 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5627 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5628 that the driver was orginaly developed and tested using the
5629 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5630 the family was cribbed from the data sheet. @emph{Note to future
5631 readers/updaters: Please remove this worrisome comment after other
5632 chips are confirmed.}
5634 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5635 have one flash bank. In all cases the flash banks are at
5636 the following fixed locations:
5639 # Flash bank 0 - all chips
5640 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5641 # Flash bank 1 - only 256K chips
5642 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5645 Internally, the AT91SAM3 flash memory is organized as follows.
5646 Unlike the AT91SAM7 chips, these are not used as parameters
5647 to the @command{flash bank} command:
5650 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5651 @item @emph{Bank Size:} 128K/64K Per flash bank
5652 @item @emph{Sectors:} 16 or 8 per bank
5653 @item @emph{SectorSize:} 8K Per Sector
5654 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5657 The AT91SAM3 driver adds some additional commands:
5659 @deffn Command {at91sam3 gpnvm}
5660 @deffnx Command {at91sam3 gpnvm clear} number
5661 @deffnx Command {at91sam3 gpnvm set} number
5662 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5663 With no parameters, @command{show} or @command{show all},
5664 shows the status of all GPNVM bits.
5665 With @command{show} @var{number}, displays that bit.
5667 With @command{set} @var{number} or @command{clear} @var{number},
5668 modifies that GPNVM bit.
5671 @deffn Command {at91sam3 info}
5672 This command attempts to display information about the AT91SAM3
5673 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5674 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5675 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5676 various clock configuration registers and attempts to display how it
5677 believes the chip is configured. By default, the SLOWCLK is assumed to
5678 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5681 @deffn Command {at91sam3 slowclk} [value]
5682 This command shows/sets the slow clock frequency used in the
5683 @command{at91sam3 info} command calculations above.
5687 @deffn {Flash Driver} at91sam4
5689 All members of the AT91SAM4 microcontroller family from
5690 Atmel include internal flash and use ARM's Cortex-M4 core.
5691 This driver uses the same command names/syntax as @xref{at91sam3}.
5694 @deffn {Flash Driver} at91sam4l
5696 All members of the AT91SAM4L microcontroller family from
5697 Atmel include internal flash and use ARM's Cortex-M4 core.
5698 This driver uses the same command names/syntax as @xref{at91sam3}.
5700 The AT91SAM4L driver adds some additional commands:
5701 @deffn Command {at91sam4l smap_reset_deassert}
5702 This command releases internal reset held by SMAP
5703 and prepares reset vector catch in case of reset halt.
5704 Command is used internally in event event reset-deassert-post.
5709 @deffn {Flash Driver} atsame5
5711 All members of the SAM E54, E53, E51 and D51 microcontroller
5712 families from Microchip (former Atmel) include internal flash
5713 and use ARM's Cortex-M4 core.
5715 The devices have two ECC flash banks with a swapping feature.
5716 This driver handles both banks together as it were one.
5717 Bank swapping is not supported yet.
5720 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
5723 @deffn Command {atsame5 bootloader}
5724 Shows or sets the bootloader size configuration, stored in the User Page of the
5725 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5726 must be specified in bytes. The nearest bigger protection size is used.
5727 Settings are written immediately but only take effect on MCU reset.
5728 Setting the bootloader size to 0 disables bootloader protection.
5732 atsame5 bootloader 16384
5736 @deffn Command {atsame5 chip-erase}
5737 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5738 used to erase a chip back to its factory state and does not require the
5739 processor to be halted.
5742 @deffn Command {atsame5 dsu_reset_deassert}
5743 This command releases internal reset held by DSU
5744 and prepares reset vector catch in case of reset halt.
5745 Command is used internally in event event reset-deassert-post.
5748 @deffn Command {atsame5 userpage}
5749 Writes or reads the first 64 bits of NVM User Page which is located at
5750 0x804000. This field includes various fuses.
5751 Reading is done by invoking this command without any arguments.
5752 Writing is possible by giving 1 or 2 hex values. The first argument
5753 is the value to be written and the second one is an optional bit mask
5754 (a zero bit in the mask means the bit stays unchanged).
5755 The reserved fields are always masked out and cannot be changed.
5760 USER PAGE: 0xAEECFF80FE9A9239
5762 >atsame5 userpage 0xAEECFF80FE9A9239
5763 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other bits unchanged
5764 # (setup SmartEEPROM of virtual size 8192 bytes)
5765 >atsame5 userpage 0x4200000000 0x7f00000000
5771 @deffn {Flash Driver} atsamv
5773 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
5774 Atmel include internal flash and use ARM's Cortex-M7 core.
5775 This driver uses the same command names/syntax as @xref{at91sam3}.
5778 @deffn {Flash Driver} at91sam7
5779 All members of the AT91SAM7 microcontroller family from Atmel include
5780 internal flash and use ARM7TDMI cores. The driver automatically
5781 recognizes a number of these chips using the chip identification
5782 register, and autoconfigures itself.
5785 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5788 For chips which are not recognized by the controller driver, you must
5789 provide additional parameters in the following order:
5792 @item @var{chip_model} ... label used with @command{flash info}
5794 @item @var{sectors_per_bank}
5795 @item @var{pages_per_sector}
5796 @item @var{pages_size}
5797 @item @var{num_nvm_bits}
5798 @item @var{freq_khz} ... required if an external clock is provided,
5799 optional (but recommended) when the oscillator frequency is known
5802 It is recommended that you provide zeroes for all of those values
5803 except the clock frequency, so that everything except that frequency
5804 will be autoconfigured.
5805 Knowing the frequency helps ensure correct timings for flash access.
5807 The flash controller handles erases automatically on a page (128/256 byte)
5808 basis, so explicit erase commands are not necessary for flash programming.
5809 However, there is an ``EraseAll`` command that can erase an entire flash
5810 plane (of up to 256KB), and it will be used automatically when you issue
5811 @command{flash erase_sector} or @command{flash erase_address} commands.
5813 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5814 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5815 bit for the processor. Each processor has a number of such bits,
5816 used for controlling features such as brownout detection (so they
5817 are not truly general purpose).
5819 This assumes that the first flash bank (number 0) is associated with
5820 the appropriate at91sam7 target.
5825 @deffn {Flash Driver} avr
5826 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5827 @emph{The current implementation is incomplete.}
5828 @comment - defines mass_erase ... pointless given flash_erase_address
5831 @deffn {Flash Driver} bluenrg-x
5832 STMicroelectronics BlueNRG-1 and BlueNRG-2 Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0 core and internal flash memory.
5833 The driver automatically recognizes these chips using
5834 the chip identification registers, and autoconfigures itself.
5837 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
5840 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
5841 each single sector one by one.
5844 flash erase_sector 0 0 79 # It will perform a mass erase on BlueNRG-1
5848 flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2
5851 Triggering a mass erase is also useful when users want to disable readout protection.
5854 @deffn {Flash Driver} cc26xx
5855 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
5856 Instruments include internal flash. The cc26xx flash driver supports both the
5857 CC13xx and CC26xx family of devices. The driver automatically recognizes the
5858 specific version's flash parameters and autoconfigures itself. The flash bank
5859 starts at address 0.
5862 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
5866 @deffn {Flash Driver} cc3220sf
5867 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
5868 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
5869 supports the internal flash. The serial flash on SimpleLink boards is
5870 programmed via the bootloader over a UART connection. Security features of
5871 the CC3220SF may erase the internal flash during power on reset. Refer to
5872 documentation at @url{www.ti.com/cc3220sf} for details on security features
5873 and programming the serial flash.
5876 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
5880 @deffn {Flash Driver} efm32
5881 All members of the EFM32 microcontroller family from Energy Micro include
5882 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
5883 a number of these chips using the chip identification register, and
5884 autoconfigures itself.
5886 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5888 A special feature of efm32 controllers is that it is possible to completely disable the
5889 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
5890 this via the following command:
5894 The @var{num} parameter is a value shown by @command{flash banks}.
5895 Note that in order for this command to take effect, the target needs to be reset.
5896 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5900 @deffn {Flash Driver} esirisc
5901 Members of the eSi-RISC family may optionally include internal flash programmed
5902 via the eSi-TSMC Flash interface. Additional parameters are required to
5903 configure the driver: @option{cfg_address} is the base address of the
5904 configuration register interface, @option{clock_hz} is the expected clock
5905 frequency, and @option{wait_states} is the number of configured read wait states.
5908 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
5909 $_TARGETNAME cfg_address clock_hz wait_states
5912 @deffn Command {esirisc flash mass_erase} bank_id
5913 Erase all pages in data memory for the bank identified by @option{bank_id}.
5916 @deffn Command {esirisc flash ref_erase} bank_id
5917 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
5918 is an uncommon operation.}
5922 @deffn {Flash Driver} fm3
5923 All members of the FM3 microcontroller family from Fujitsu
5924 include internal flash and use ARM Cortex-M3 cores.
5925 The @var{fm3} driver uses the @var{target} parameter to select the
5926 correct bank config, it can currently be one of the following:
5927 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5928 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5931 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5935 @deffn {Flash Driver} fm4
5936 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
5937 include internal flash and use ARM Cortex-M4 cores.
5938 The @var{fm4} driver uses a @var{family} parameter to select the
5939 correct bank config, it can currently be one of the following:
5940 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
5941 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
5942 with @code{x} treated as wildcard and otherwise case (and any trailing
5943 characters) ignored.
5946 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
5947 $_TARGETNAME S6E2CCAJ0A
5948 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
5949 $_TARGETNAME S6E2CCAJ0A
5951 @emph{The current implementation is incomplete. Protection is not supported,
5952 nor is Chip Erase (only Sector Erase is implemented).}
5955 @deffn {Flash Driver} kinetis
5957 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
5958 from NXP (former Freescale) include
5959 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
5960 recognizes flash size and a number of flash banks (1-4) using the chip
5961 identification register, and autoconfigures itself.
5962 Use kinetis_ke driver for KE0x and KEAx devices.
5964 The @var{kinetis} driver defines option:
5966 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
5970 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
5973 @deffn Command {kinetis create_banks}
5974 Configuration command enables automatic creation of additional flash banks
5975 based on real flash layout of device. Banks are created during device probe.
5976 Use 'flash probe 0' to force probe.
5979 @deffn Command {kinetis fcf_source} [protection|write]
5980 Select what source is used when writing to a Flash Configuration Field.
5981 @option{protection} mode builds FCF content from protection bits previously
5982 set by 'flash protect' command.
5983 This mode is default. MCU is protected from unwanted locking by immediate
5984 writing FCF after erase of relevant sector.
5985 @option{write} mode enables direct write to FCF.
5986 Protection cannot be set by 'flash protect' command. FCF is written along
5987 with the rest of a flash image.
5988 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
5991 @deffn Command {kinetis fopt} [num]
5992 Set value to write to FOPT byte of Flash Configuration Field.
5993 Used in kinetis 'fcf_source protection' mode only.
5996 @deffn Command {kinetis mdm check_security}
5997 Checks status of device security lock. Used internally in examine-end event.
6000 @deffn Command {kinetis mdm halt}
6001 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6002 loop when connecting to an unsecured target.
6005 @deffn Command {kinetis mdm mass_erase}
6006 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6007 back to its factory state, removing security. It does not require the processor
6008 to be halted, however the target will remain in a halted state after this
6012 @deffn Command {kinetis nvm_partition}
6013 For FlexNVM devices only (KxxDX and KxxFX).
6014 Command shows or sets data flash or EEPROM backup size in kilobytes,
6015 sets two EEPROM blocks sizes in bytes and enables/disables loading
6016 of EEPROM contents to FlexRAM during reset.
6018 For details see device reference manual, Flash Memory Module,
6019 Program Partition command.
6021 Setting is possible only once after mass_erase.
6022 Reset the device after partition setting.
6024 Show partition size:
6026 kinetis nvm_partition info
6029 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6030 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6032 kinetis nvm_partition dataflash 32 512 1536 on
6035 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6036 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6038 kinetis nvm_partition eebkp 16 1024 1024 off
6042 @deffn Command {kinetis mdm reset}
6043 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6044 RESET pin, which can be used to reset other hardware on board.
6047 @deffn Command {kinetis disable_wdog}
6048 For Kx devices only (KLx has different COP watchdog, it is not supported).
6049 Command disables watchdog timer.
6053 @deffn {Flash Driver} kinetis_ke
6055 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6056 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6057 the KE0x sub-family using the chip identification register, and
6058 autoconfigures itself.
6059 Use kinetis (not kinetis_ke) driver for KE1x devices.
6062 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6065 @deffn Command {kinetis_ke mdm check_security}
6066 Checks status of device security lock. Used internally in examine-end event.
6069 @deffn Command {kinetis_ke mdm mass_erase}
6070 Issues a complete Flash erase via the MDM-AP.
6071 This can be used to erase a chip back to its factory state.
6072 Command removes security lock from a device (use of SRST highly recommended).
6073 It does not require the processor to be halted.
6076 @deffn Command {kinetis_ke disable_wdog}
6077 Command disables watchdog timer.
6081 @deffn {Flash Driver} lpc2000
6082 This is the driver to support internal flash of all members of the
6083 LPC11(x)00 and LPC1300 microcontroller families and most members of
6084 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6085 LPC8Nxx and NHS31xx microcontroller families from NXP.
6088 There are LPC2000 devices which are not supported by the @var{lpc2000}
6090 The LPC2888 is supported by the @var{lpc288x} driver.
6091 The LPC29xx family is supported by the @var{lpc2900} driver.
6094 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6095 which must appear in the following order:
6098 @item @var{variant} ... required, may be
6099 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6100 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6101 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6102 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6104 @option{lpc800} (LPC8xx)
6105 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6106 @option{lpc1500} (LPC15xx)
6107 @option{lpc54100} (LPC541xx)
6108 @option{lpc4000} (LPC40xx)
6109 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6110 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6111 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6112 at which the core is running
6113 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6114 telling the driver to calculate a valid checksum for the exception vector table.
6116 If you don't provide @option{calc_checksum} when you're writing the vector
6117 table, the boot ROM will almost certainly ignore your flash image.
6118 However, if you do provide it,
6119 with most tool chains @command{verify_image} will fail.
6121 @item @option{iap_entry} ... optional telling the driver to use a different
6122 ROM IAP entry point.
6125 LPC flashes don't require the chip and bus width to be specified.
6128 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6129 lpc2000_v2 14765 calc_checksum
6132 @deffn {Command} {lpc2000 part_id} bank
6133 Displays the four byte part identifier associated with
6134 the specified flash @var{bank}.
6138 @deffn {Flash Driver} lpc288x
6139 The LPC2888 microcontroller from NXP needs slightly different flash
6140 support from its lpc2000 siblings.
6141 The @var{lpc288x} driver defines one mandatory parameter,
6142 the programming clock rate in Hz.
6143 LPC flashes don't require the chip and bus width to be specified.
6146 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6150 @deffn {Flash Driver} lpc2900
6151 This driver supports the LPC29xx ARM968E based microcontroller family
6154 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6155 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6156 sector layout are auto-configured by the driver.
6157 The driver has one additional mandatory parameter: The CPU clock rate
6158 (in kHz) at the time the flash operations will take place. Most of the time this
6159 will not be the crystal frequency, but a higher PLL frequency. The
6160 @code{reset-init} event handler in the board script is usually the place where
6163 The driver rejects flashless devices (currently the LPC2930).
6165 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6166 It must be handled much more like NAND flash memory, and will therefore be
6167 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6169 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6170 sector needs to be erased or programmed, it is automatically unprotected.
6171 What is shown as protection status in the @code{flash info} command, is
6172 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6173 sector from ever being erased or programmed again. As this is an irreversible
6174 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6175 and not by the standard @code{flash protect} command.
6177 Example for a 125 MHz clock frequency:
6179 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6182 Some @code{lpc2900}-specific commands are defined. In the following command list,
6183 the @var{bank} parameter is the bank number as obtained by the
6184 @code{flash banks} command.
6186 @deffn Command {lpc2900 signature} bank
6187 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6188 content. This is a hardware feature of the flash block, hence the calculation is
6189 very fast. You may use this to verify the content of a programmed device against
6194 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6198 @deffn Command {lpc2900 read_custom} bank filename
6199 Reads the 912 bytes of customer information from the flash index sector, and
6200 saves it to a file in binary format.
6203 lpc2900 read_custom 0 /path_to/customer_info.bin
6207 The index sector of the flash is a @emph{write-only} sector. It cannot be
6208 erased! In order to guard against unintentional write access, all following
6209 commands need to be preceded by a successful call to the @code{password}
6212 @deffn Command {lpc2900 password} bank password
6213 You need to use this command right before each of the following commands:
6214 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6215 @code{lpc2900 secure_jtag}.
6217 The password string is fixed to "I_know_what_I_am_doing".
6220 lpc2900 password 0 I_know_what_I_am_doing
6221 Potentially dangerous operation allowed in next command!
6225 @deffn Command {lpc2900 write_custom} bank filename type
6226 Writes the content of the file into the customer info space of the flash index
6227 sector. The filetype can be specified with the @var{type} field. Possible values
6228 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6229 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6230 contain a single section, and the contained data length must be exactly
6232 @quotation Attention
6233 This cannot be reverted! Be careful!
6237 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6241 @deffn Command {lpc2900 secure_sector} bank first last
6242 Secures the sector range from @var{first} to @var{last} (including) against
6243 further program and erase operations. The sector security will be effective
6244 after the next power cycle.
6245 @quotation Attention
6246 This cannot be reverted! Be careful!
6248 Secured sectors appear as @emph{protected} in the @code{flash info} command.
6251 lpc2900 secure_sector 0 1 1
6253 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
6254 # 0: 0x00000000 (0x2000 8kB) not protected
6255 # 1: 0x00002000 (0x2000 8kB) protected
6256 # 2: 0x00004000 (0x2000 8kB) not protected
6260 @deffn Command {lpc2900 secure_jtag} bank
6261 Irreversibly disable the JTAG port. The new JTAG security setting will be
6262 effective after the next power cycle.
6263 @quotation Attention
6264 This cannot be reverted! Be careful!
6268 lpc2900 secure_jtag 0
6273 @deffn {Flash Driver} mdr
6274 This drivers handles the integrated NOR flash on Milandr Cortex-M
6275 based controllers. A known limitation is that the Info memory can't be
6276 read or verified as it's not memory mapped.
6279 flash bank <name> mdr <base> <size> \
6280 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
6284 @item @var{type} - 0 for main memory, 1 for info memory
6285 @item @var{page_count} - total number of pages
6286 @item @var{sec_count} - number of sector per page count
6291 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
6292 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
6293 0 0 $_TARGETNAME 1 1 4
6295 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
6296 0 0 $_TARGETNAME 0 32 4
6301 @deffn {Flash Driver} msp432
6302 All versions of the SimpleLink MSP432 microcontrollers from Texas
6303 Instruments include internal flash. The msp432 flash driver automatically
6304 recognizes the specific version's flash parameters and autoconfigures itself.
6305 Main program flash (starting at address 0) is flash bank 0. Information flash
6306 region on MSP432P4 versions (starting at address 0x200000) is flash bank 1.
6309 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
6312 @deffn Command {msp432 mass_erase} [main|all]
6313 Performs a complete erase of flash. By default, @command{mass_erase} will erase
6314 only the main program flash.
6316 On MSP432P4 versions, using @command{mass_erase all} will erase both the
6317 main program and information flash regions. To also erase the BSL in information
6318 flash, the user must first use the @command{bsl} command.
6321 @deffn Command {msp432 bsl} [unlock|lock]
6322 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
6323 region in information flash so that flash commands can erase or write the BSL.
6324 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
6326 To erase and program the BSL:
6329 flash erase_address 0x202000 0x2000
6330 flash write_image bsl.bin 0x202000
6336 @deffn {Flash Driver} niietcm4
6337 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6338 based controllers. Flash size and sector layout are auto-configured by the driver.
6339 Main flash memory is called "Bootflash" and has main region and info region.
6340 Info region is NOT memory mapped by default,
6341 but it can replace first part of main region if needed.
6342 Full erase, single and block writes are supported for both main and info regions.
6343 There is additional not memory mapped flash called "Userflash", which
6344 also have division into regions: main and info.
6345 Purpose of userflash - to store system and user settings.
6346 Driver has special commands to perform operations with this memory.
6349 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6352 Some niietcm4-specific commands are defined:
6354 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
6355 Read byte from main or info userflash region.
6358 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6359 Write byte to main or info userflash region.
6362 @deffn Command {niietcm4 uflash_full_erase} bank
6363 Erase all userflash including info region.
6366 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6367 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6370 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
6371 Check sectors protect.
6374 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6375 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6378 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
6379 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6382 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6383 Configure external memory interface for boot.
6386 @deffn Command {niietcm4 service_mode_erase} bank
6387 Perform emergency erase of all flash (bootflash and userflash).
6390 @deffn Command {niietcm4 driver_info} bank
6391 Show information about flash driver.
6396 @deffn {Flash Driver} nrf5
6397 All members of the nRF51 microcontroller families from Nordic Semiconductor
6398 include internal flash and use ARM Cortex-M0 core.
6399 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
6400 internal flash and use an ARM Cortex-M4F core.
6403 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6406 Some nrf5-specific commands are defined:
6408 @deffn Command {nrf5 mass_erase}
6409 Erases the contents of the code memory and user information
6410 configuration registers as well. It must be noted that this command
6411 works only for chips that do not have factory pre-programmed region 0
6415 @deffn Command {nrf5 info}
6416 Decodes and shows informations from FICR and UICR registers.
6421 @deffn {Flash Driver} ocl
6422 This driver is an implementation of the ``on chip flash loader''
6423 protocol proposed by Pavel Chromy.
6425 It is a minimalistic command-response protocol intended to be used
6426 over a DCC when communicating with an internal or external flash
6427 loader running from RAM. An example implementation for AT91SAM7x is
6428 available in @file{contrib/loaders/flash/at91sam7x/}.
6431 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
6435 @deffn {Flash Driver} pic32mx
6436 The PIC32MX microcontrollers are based on the MIPS 4K cores,
6437 and integrate flash memory.
6440 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
6441 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
6444 @comment numerous *disabled* commands are defined:
6445 @comment - chip_erase ... pointless given flash_erase_address
6446 @comment - lock, unlock ... pointless given protect on/off (yes?)
6447 @comment - pgm_word ... shouldn't bank be deduced from address??
6448 Some pic32mx-specific commands are defined:
6449 @deffn Command {pic32mx pgm_word} address value bank
6450 Programs the specified 32-bit @var{value} at the given @var{address}
6451 in the specified chip @var{bank}.
6453 @deffn Command {pic32mx unlock} bank
6454 Unlock and erase specified chip @var{bank}.
6455 This will remove any Code Protection.
6459 @deffn {Flash Driver} psoc4
6460 All members of the PSoC 41xx/42xx microcontroller family from Cypress
6461 include internal flash and use ARM Cortex-M0 cores.
6462 The driver automatically recognizes a number of these chips using
6463 the chip identification register, and autoconfigures itself.
6465 Note: Erased internal flash reads as 00.
6466 System ROM of PSoC 4 does not implement erase of a flash sector.
6469 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
6472 psoc4-specific commands
6473 @deffn Command {psoc4 flash_autoerase} num (on|off)
6474 Enables or disables autoerase mode for a flash bank.
6476 If flash_autoerase is off, use mass_erase before flash programming.
6477 Flash erase command fails if region to erase is not whole flash memory.
6479 If flash_autoerase is on, a sector is both erased and programmed in one
6480 system ROM call. Flash erase command is ignored.
6481 This mode is suitable for gdb load.
6483 The @var{num} parameter is a value shown by @command{flash banks}.
6486 @deffn Command {psoc4 mass_erase} num
6487 Erases the contents of the flash memory, protection and security lock.
6489 The @var{num} parameter is a value shown by @command{flash banks}.
6493 @deffn {Flash Driver} psoc5lp
6494 All members of the PSoC 5LP microcontroller family from Cypress
6495 include internal program flash and use ARM Cortex-M3 cores.
6496 The driver probes for a number of these chips and autoconfigures itself,
6497 apart from the base address.
6500 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
6503 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
6504 @quotation Attention
6505 If flash operations are performed in ECC-disabled mode, they will also affect
6506 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
6507 then also erase the corresponding 2k data bytes in the 0x48000000 area.
6508 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
6511 Commands defined in the @var{psoc5lp} driver:
6513 @deffn Command {psoc5lp mass_erase}
6514 Erases all flash data and ECC/configuration bytes, all flash protection rows,
6515 and all row latches in all flash arrays on the device.
6519 @deffn {Flash Driver} psoc5lp_eeprom
6520 All members of the PSoC 5LP microcontroller family from Cypress
6521 include internal EEPROM and use ARM Cortex-M3 cores.
6522 The driver probes for a number of these chips and autoconfigures itself,
6523 apart from the base address.
6526 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
6530 @deffn {Flash Driver} psoc5lp_nvl
6531 All members of the PSoC 5LP microcontroller family from Cypress
6532 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
6533 The driver probes for a number of these chips and autoconfigures itself.
6536 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
6539 PSoC 5LP chips have multiple NV Latches:
6542 @item Device Configuration NV Latch - 4 bytes
6543 @item Write Once (WO) NV Latch - 4 bytes
6546 @b{Note:} This driver only implements the Device Configuration NVL.
6548 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
6549 @quotation Attention
6550 Switching ECC mode via write to Device Configuration NVL will require a reset
6551 after successful write.
6555 @deffn {Flash Driver} psoc6
6556 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
6557 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
6558 the same Flash/RAM/MMIO address space.
6560 Flash in PSoC6 is split into three regions:
6562 @item Main Flash - this is the main storage for user application.
6563 Total size varies among devices, sector size: 256 kBytes, row size:
6564 512 bytes. Supports erase operation on individual rows.
6565 @item Work Flash - intended to be used as storage for user data
6566 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
6567 row size: 512 bytes.
6568 @item Supervisory Flash - special region which contains device-specific
6569 service data. This region does not support erase operation. Only few rows can
6570 be programmed by the user, most of the rows are read only. Programming
6571 operation will erase row automatically.
6574 All three flash regions are supported by the driver. Flash geometry is detected
6575 automatically by parsing data in SPCIF_GEOMETRY register.
6577 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
6580 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm0
6581 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm0
6582 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm0
6583 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm0
6584 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm0
6585 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm0
6587 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm4
6588 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm4
6589 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm4
6590 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm4
6591 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm4
6592 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm4
6595 psoc6-specific commands
6596 @deffn Command {psoc6 reset_halt}
6597 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
6598 When invoked for CM0+ target, it will set break point at application entry point
6599 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
6600 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
6601 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
6604 @deffn Command {psoc6 mass_erase} num
6605 Erases the contents given flash bank. The @var{num} parameter is a value shown
6606 by @command{flash banks}.
6607 Note: only Main and Work flash regions support Erase operation.
6611 @deffn {Flash Driver} sim3x
6612 All members of the SiM3 microcontroller family from Silicon Laboratories
6613 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
6615 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
6616 If this fails, it will use the @var{size} parameter as the size of flash bank.
6619 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
6622 There are 2 commands defined in the @var{sim3x} driver:
6624 @deffn Command {sim3x mass_erase}
6625 Erases the complete flash. This is used to unlock the flash.
6626 And this command is only possible when using the SWD interface.
6629 @deffn Command {sim3x lock}
6630 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
6634 @deffn {Flash Driver} stellaris
6635 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
6636 families from Texas Instruments include internal flash. The driver
6637 automatically recognizes a number of these chips using the chip
6638 identification register, and autoconfigures itself.
6641 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
6644 @deffn Command {stellaris recover}
6645 Performs the @emph{Recovering a "Locked" Device} procedure to restore
6646 the flash and its associated nonvolatile registers to their factory
6647 default values (erased). This is the only way to remove flash
6648 protection or re-enable debugging if that capability has been
6651 Note that the final "power cycle the chip" step in this procedure
6652 must be performed by hand, since OpenOCD can't do it.
6654 if more than one Stellaris chip is connected, the procedure is
6655 applied to all of them.
6660 @deffn {Flash Driver} stm32f1x
6661 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
6662 from STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
6663 The driver automatically recognizes a number of these chips using
6664 the chip identification register, and autoconfigures itself.
6667 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
6670 Note that some devices have been found that have a flash size register that contains
6671 an invalid value, to workaround this issue you can override the probed value used by
6675 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
6678 If you have a target with dual flash banks then define the second bank
6679 as per the following example.
6681 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
6684 Some stm32f1x-specific commands are defined:
6686 @deffn Command {stm32f1x lock} num
6687 Locks the entire stm32 device against reading.
6688 The @var{num} parameter is a value shown by @command{flash banks}.
6691 @deffn Command {stm32f1x unlock} num
6692 Unlocks the entire stm32 device for reading. This command will cause
6693 a mass erase of the entire stm32 device if previously locked.
6694 The @var{num} parameter is a value shown by @command{flash banks}.
6697 @deffn Command {stm32f1x mass_erase} num
6698 Mass erases the entire stm32 device.
6699 The @var{num} parameter is a value shown by @command{flash banks}.
6702 @deffn Command {stm32f1x options_read} num
6703 Reads and displays active stm32 option bytes loaded during POR
6704 or upon executing the @command{stm32f1x options_load} command.
6705 The @var{num} parameter is a value shown by @command{flash banks}.
6708 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
6709 Writes the stm32 option byte with the specified values.
6710 The @var{num} parameter is a value shown by @command{flash banks}.
6711 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
6714 @deffn Command {stm32f1x options_load} num
6715 Generates a special kind of reset to re-load the stm32 option bytes written
6716 by the @command{stm32f1x options_write} or @command{flash protect} commands
6717 without having to power cycle the target. Not applicable to stm32f1x devices.
6718 The @var{num} parameter is a value shown by @command{flash banks}.
6722 @deffn {Flash Driver} stm32f2x
6723 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
6724 include internal flash and use ARM Cortex-M3/M4/M7 cores.
6725 The driver automatically recognizes a number of these chips using
6726 the chip identification register, and autoconfigures itself.
6729 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
6732 If you use OTP (One-Time Programmable) memory define it as a second bank
6733 as per the following example.
6735 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
6738 @deffn Command {stm32f2x otp } num (@option{enable}|@option{disable}|@option{show})
6739 Enables or disables OTP write commands for bank @var{num}.
6740 The @var{num} parameter is a value shown by @command{flash banks}.
6743 Note that some devices have been found that have a flash size register that contains
6744 an invalid value, to workaround this issue you can override the probed value used by
6748 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
6751 Some stm32f2x-specific commands are defined:
6753 @deffn Command {stm32f2x lock} num
6754 Locks the entire stm32 device.
6755 The @var{num} parameter is a value shown by @command{flash banks}.
6758 @deffn Command {stm32f2x unlock} num
6759 Unlocks the entire stm32 device.
6760 The @var{num} parameter is a value shown by @command{flash banks}.
6763 @deffn Command {stm32f2x mass_erase} num
6764 Mass erases the entire stm32f2x device.
6765 The @var{num} parameter is a value shown by @command{flash banks}.
6768 @deffn Command {stm32f2x options_read} num
6769 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
6770 The @var{num} parameter is a value shown by @command{flash banks}.
6773 @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
6774 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
6775 Warning: The meaning of the various bits depends on the device, always check datasheet!
6776 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
6777 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
6778 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
6781 @deffn Command {stm32f2x optcr2_write} num optcr2
6782 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
6783 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
6787 @deffn {Flash Driver} stm32h7x
6788 All members of the STM32H7 microcontroller families from STMicroelectronics
6789 include internal flash and use ARM Cortex-M7 core.
6790 The driver automatically recognizes a number of these chips using
6791 the chip identification register, and autoconfigures itself.
6794 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
6797 Note that some devices have been found that have a flash size register that contains
6798 an invalid value, to workaround this issue you can override the probed value used by
6802 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
6805 Some stm32h7x-specific commands are defined:
6807 @deffn Command {stm32h7x lock} num
6808 Locks the entire stm32 device.
6809 The @var{num} parameter is a value shown by @command{flash banks}.
6812 @deffn Command {stm32h7x unlock} num
6813 Unlocks the entire stm32 device.
6814 The @var{num} parameter is a value shown by @command{flash banks}.
6817 @deffn Command {stm32h7x mass_erase} num
6818 Mass erases the entire stm32h7x device.
6819 The @var{num} parameter is a value shown by @command{flash banks}.
6822 @deffn Command {stm32h7x option_read} num reg_offset
6823 Reads an option byte register from the stm32h7x device.
6824 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6825 is the register offset of the option byte to read from the used bank registers' base.
6826 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
6831 stm32h7x option_read 0 0x1c
6833 stm32h7x option_read 0 0x38
6835 stm32h7x option_read 1 0x38
6839 @deffn Command {stm32h7x option_write} num reg_offset value [reg_mask]
6840 Writes an option byte register of the stm32h7x device.
6841 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6842 is the register offset of the option byte to write from the used bank register base,
6843 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
6848 # swap bank 1 and bank 2 in dual bank devices, by setting SWAP_BANK_OPT bit in OPTSR_PRG
6849 stm32h7x option_write 0 0x20 0x8000000 0x8000000
6854 @deffn {Flash Driver} stm32lx
6855 All members of the STM32L microcontroller families from STMicroelectronics
6856 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
6857 The driver automatically recognizes a number of these chips using
6858 the chip identification register, and autoconfigures itself.
6861 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
6864 Note that some devices have been found that have a flash size register that contains
6865 an invalid value, to workaround this issue you can override the probed value used by
6866 the flash driver. If you use 0 as the bank base address, it tells the
6867 driver to autodetect the bank location assuming you're configuring the
6871 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
6874 Some stm32lx-specific commands are defined:
6876 @deffn Command {stm32lx lock} num
6877 Locks the entire stm32 device.
6878 The @var{num} parameter is a value shown by @command{flash banks}.
6881 @deffn Command {stm32lx unlock} num
6882 Unlocks the entire stm32 device.
6883 The @var{num} parameter is a value shown by @command{flash banks}.
6886 @deffn Command {stm32lx mass_erase} num
6887 Mass erases the entire stm32lx device (all flash banks and EEPROM
6888 data). This is the only way to unlock a protected flash (unless RDP
6889 Level is 2 which can't be unlocked at all).
6890 The @var{num} parameter is a value shown by @command{flash banks}.
6894 @deffn {Flash Driver} stm32l4x
6895 All members of the STM32L4 and STM32WB microcontroller families from STMicroelectronics
6896 include internal flash and use ARM Cortex-M4 cores.
6897 The driver automatically recognizes a number of these chips using
6898 the chip identification register, and autoconfigures itself.
6901 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
6904 Note that some devices have been found that have a flash size register that contains
6905 an invalid value, to workaround this issue you can override the probed value used by
6909 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
6912 Some stm32l4x-specific commands are defined:
6914 @deffn Command {stm32l4x lock} num
6915 Locks the entire stm32 device.
6916 The @var{num} parameter is a value shown by @command{flash banks}.
6919 @deffn Command {stm32l4x unlock} num
6920 Unlocks the entire stm32 device.
6921 The @var{num} parameter is a value shown by @command{flash banks}.
6924 @deffn Command {stm32l4x mass_erase} num
6925 Mass erases the entire stm32l4x device.
6926 The @var{num} parameter is a value shown by @command{flash banks}.
6929 @deffn Command {stm32l4x option_read} num reg_offset
6930 Reads an option byte register from the stm32l4x device.
6931 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6932 is the register offset of the Option byte to read.
6934 For example to read the FLASH_OPTR register:
6936 stm32l4x option_read 0 0x20
6937 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
6938 # Option Register (for STM32WBx): <0x58004020> = ...
6939 # The correct flash base address will be used automatically
6942 The above example will read out the FLASH_OPTR register which contains the RDP
6943 option byte, Watchdog configuration, BOR level etc.
6946 @deffn Command {stm32l4x option_write} num reg_offset reg_mask
6947 Write an option byte register of the stm32l4x device.
6948 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6949 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
6950 to apply when writing the register (only bits with a '1' will be touched).
6952 For example to write the WRP1AR option bytes:
6954 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
6957 The above example will write the WRP1AR option register configuring the Write protection
6958 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
6959 This will effectively write protect all sectors in flash bank 1.
6962 @deffn Command {stm32l4x option_load} num
6963 Forces a re-load of the option byte registers. Will cause a reset of the device.
6964 The @var{num} parameter is a value shown by @command{flash banks}.
6968 @deffn {Flash Driver} str7x
6969 All members of the STR7 microcontroller family from STMicroelectronics
6970 include internal flash and use ARM7TDMI cores.
6971 The @var{str7x} driver defines one mandatory parameter, @var{variant},
6972 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
6975 flash bank $_FLASHNAME str7x \
6976 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
6979 @deffn Command {str7x disable_jtag} bank
6980 Activate the Debug/Readout protection mechanism
6981 for the specified flash bank.
6985 @deffn {Flash Driver} str9x
6986 Most members of the STR9 microcontroller family from STMicroelectronics
6987 include internal flash and use ARM966E cores.
6988 The str9 needs the flash controller to be configured using
6989 the @command{str9x flash_config} command prior to Flash programming.
6992 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
6993 str9x flash_config 0 4 2 0 0x80000
6996 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
6997 Configures the str9 flash controller.
6998 The @var{num} parameter is a value shown by @command{flash banks}.
7001 @item @var{bbsr} - Boot Bank Size register
7002 @item @var{nbbsr} - Non Boot Bank Size register
7003 @item @var{bbadr} - Boot Bank Start Address register
7004 @item @var{nbbadr} - Boot Bank Start Address register
7010 @deffn {Flash Driver} str9xpec
7013 Only use this driver for locking/unlocking the device or configuring the option bytes.
7014 Use the standard str9 driver for programming.
7015 Before using the flash commands the turbo mode must be enabled using the
7016 @command{str9xpec enable_turbo} command.
7018 Here is some background info to help
7019 you better understand how this driver works. OpenOCD has two flash drivers for
7023 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7024 flash programming as it is faster than the @option{str9xpec} driver.
7026 Direct programming @option{str9xpec} using the flash controller. This is an
7027 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7028 core does not need to be running to program using this flash driver. Typical use
7029 for this driver is locking/unlocking the target and programming the option bytes.
7032 Before we run any commands using the @option{str9xpec} driver we must first disable
7033 the str9 core. This example assumes the @option{str9xpec} driver has been
7034 configured for flash bank 0.
7036 # assert srst, we do not want core running
7037 # while accessing str9xpec flash driver
7039 # turn off target polling
7042 str9xpec enable_turbo 0
7044 str9xpec options_read 0
7045 # re-enable str9 core
7046 str9xpec disable_turbo 0
7050 The above example will read the str9 option bytes.
7051 When performing a unlock remember that you will not be able to halt the str9 - it
7052 has been locked. Halting the core is not required for the @option{str9xpec} driver
7053 as mentioned above, just issue the commands above manually or from a telnet prompt.
7055 Several str9xpec-specific commands are defined:
7057 @deffn Command {str9xpec disable_turbo} num
7058 Restore the str9 into JTAG chain.
7061 @deffn Command {str9xpec enable_turbo} num
7062 Enable turbo mode, will simply remove the str9 from the chain and talk
7063 directly to the embedded flash controller.
7066 @deffn Command {str9xpec lock} num
7067 Lock str9 device. The str9 will only respond to an unlock command that will
7071 @deffn Command {str9xpec part_id} num
7072 Prints the part identifier for bank @var{num}.
7075 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7076 Configure str9 boot bank.
7079 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
7080 Configure str9 lvd source.
7083 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
7084 Configure str9 lvd threshold.
7087 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
7088 Configure str9 lvd reset warning source.
7091 @deffn Command {str9xpec options_read} num
7092 Read str9 option bytes.
7095 @deffn Command {str9xpec options_write} num
7096 Write str9 option bytes.
7099 @deffn Command {str9xpec unlock} num
7105 @deffn {Flash Driver} swm050
7107 All members of the swm050 microcontroller family from Foshan Synwit Tech.
7110 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
7113 One swm050-specific command is defined:
7115 @deffn Command {swm050 mass_erase} bank_id
7116 Erases the entire flash bank.
7122 @deffn {Flash Driver} tms470
7123 Most members of the TMS470 microcontroller family from Texas Instruments
7124 include internal flash and use ARM7TDMI cores.
7125 This driver doesn't require the chip and bus width to be specified.
7127 Some tms470-specific commands are defined:
7129 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
7130 Saves programming keys in a register, to enable flash erase and write commands.
7133 @deffn Command {tms470 osc_mhz} clock_mhz
7134 Reports the clock speed, which is used to calculate timings.
7137 @deffn Command {tms470 plldis} (0|1)
7138 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
7143 @deffn {Flash Driver} w600
7144 W60x series Wi-Fi SoC from WinnerMicro
7145 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
7146 The @var{w600} driver uses the @var{target} parameter to select the
7147 correct bank config.
7150 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
7154 @deffn {Flash Driver} xmc1xxx
7155 All members of the XMC1xxx microcontroller family from Infineon.
7156 This driver does not require the chip and bus width to be specified.
7159 @deffn {Flash Driver} xmc4xxx
7160 All members of the XMC4xxx microcontroller family from Infineon.
7161 This driver does not require the chip and bus width to be specified.
7163 Some xmc4xxx-specific commands are defined:
7165 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
7166 Saves flash protection passwords which are used to lock the user flash
7169 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
7170 Removes Flash write protection from the selected user bank
7175 @section NAND Flash Commands
7178 Compared to NOR or SPI flash, NAND devices are inexpensive
7179 and high density. Today's NAND chips, and multi-chip modules,
7180 commonly hold multiple GigaBytes of data.
7182 NAND chips consist of a number of ``erase blocks'' of a given
7183 size (such as 128 KBytes), each of which is divided into a
7184 number of pages (of perhaps 512 or 2048 bytes each). Each
7185 page of a NAND flash has an ``out of band'' (OOB) area to hold
7186 Error Correcting Code (ECC) and other metadata, usually 16 bytes
7187 of OOB for every 512 bytes of page data.
7189 One key characteristic of NAND flash is that its error rate
7190 is higher than that of NOR flash. In normal operation, that
7191 ECC is used to correct and detect errors. However, NAND
7192 blocks can also wear out and become unusable; those blocks
7193 are then marked "bad". NAND chips are even shipped from the
7194 manufacturer with a few bad blocks. The highest density chips
7195 use a technology (MLC) that wears out more quickly, so ECC
7196 support is increasingly important as a way to detect blocks
7197 that have begun to fail, and help to preserve data integrity
7198 with techniques such as wear leveling.
7200 Software is used to manage the ECC. Some controllers don't
7201 support ECC directly; in those cases, software ECC is used.
7202 Other controllers speed up the ECC calculations with hardware.
7203 Single-bit error correction hardware is routine. Controllers
7204 geared for newer MLC chips may correct 4 or more errors for
7205 every 512 bytes of data.
7207 You will need to make sure that any data you write using
7208 OpenOCD includes the appropriate kind of ECC. For example,
7209 that may mean passing the @code{oob_softecc} flag when
7210 writing NAND data, or ensuring that the correct hardware
7213 The basic steps for using NAND devices include:
7215 @item Declare via the command @command{nand device}
7216 @* Do this in a board-specific configuration file,
7217 passing parameters as needed by the controller.
7218 @item Configure each device using @command{nand probe}.
7219 @* Do this only after the associated target is set up,
7220 such as in its reset-init script or in procures defined
7221 to access that device.
7222 @item Operate on the flash via @command{nand subcommand}
7223 @* Often commands to manipulate the flash are typed by a human, or run
7224 via a script in some automated way. Common task include writing a
7225 boot loader, operating system, or other data needed to initialize or
7229 @b{NOTE:} At the time this text was written, the largest NAND
7230 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
7231 This is because the variables used to hold offsets and lengths
7232 are only 32 bits wide.
7233 (Larger chips may work in some cases, unless an offset or length
7234 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
7235 Some larger devices will work, since they are actually multi-chip
7236 modules with two smaller chips and individual chipselect lines.
7238 @anchor{nandconfiguration}
7239 @subsection NAND Configuration Commands
7240 @cindex NAND configuration
7242 NAND chips must be declared in configuration scripts,
7243 plus some additional configuration that's done after
7244 OpenOCD has initialized.
7246 @deffn {Config Command} {nand device} name driver target [configparams...]
7247 Declares a NAND device, which can be read and written to
7248 after it has been configured through @command{nand probe}.
7249 In OpenOCD, devices are single chips; this is unlike some
7250 operating systems, which may manage multiple chips as if
7251 they were a single (larger) device.
7252 In some cases, configuring a device will activate extra
7253 commands; see the controller-specific documentation.
7255 @b{NOTE:} This command is not available after OpenOCD
7256 initialization has completed. Use it in board specific
7257 configuration files, not interactively.
7260 @item @var{name} ... may be used to reference the NAND bank
7261 in most other NAND commands. A number is also available.
7262 @item @var{driver} ... identifies the NAND controller driver
7263 associated with the NAND device being declared.
7264 @xref{nanddriverlist,,NAND Driver List}.
7265 @item @var{target} ... names the target used when issuing
7266 commands to the NAND controller.
7267 @comment Actually, it's currently a controller-specific parameter...
7268 @item @var{configparams} ... controllers may support, or require,
7269 additional parameters. See the controller-specific documentation
7270 for more information.
7274 @deffn Command {nand list}
7275 Prints a summary of each device declared
7276 using @command{nand device}, numbered from zero.
7277 Note that un-probed devices show no details.
7280 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7281 blocksize: 131072, blocks: 8192
7282 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7283 blocksize: 131072, blocks: 8192
7288 @deffn Command {nand probe} num
7289 Probes the specified device to determine key characteristics
7290 like its page and block sizes, and how many blocks it has.
7291 The @var{num} parameter is the value shown by @command{nand list}.
7292 You must (successfully) probe a device before you can use
7293 it with most other NAND commands.
7296 @subsection Erasing, Reading, Writing to NAND Flash
7298 @deffn Command {nand dump} num filename offset length [oob_option]
7299 @cindex NAND reading
7300 Reads binary data from the NAND device and writes it to the file,
7301 starting at the specified offset.
7302 The @var{num} parameter is the value shown by @command{nand list}.
7304 Use a complete path name for @var{filename}, so you don't depend
7305 on the directory used to start the OpenOCD server.
7307 The @var{offset} and @var{length} must be exact multiples of the
7308 device's page size. They describe a data region; the OOB data
7309 associated with each such page may also be accessed.
7311 @b{NOTE:} At the time this text was written, no error correction
7312 was done on the data that's read, unless raw access was disabled
7313 and the underlying NAND controller driver had a @code{read_page}
7314 method which handled that error correction.
7316 By default, only page data is saved to the specified file.
7317 Use an @var{oob_option} parameter to save OOB data:
7319 @item no oob_* parameter
7320 @*Output file holds only page data; OOB is discarded.
7321 @item @code{oob_raw}
7322 @*Output file interleaves page data and OOB data;
7323 the file will be longer than "length" by the size of the
7324 spare areas associated with each data page.
7325 Note that this kind of "raw" access is different from
7326 what's implied by @command{nand raw_access}, which just
7327 controls whether a hardware-aware access method is used.
7328 @item @code{oob_only}
7329 @*Output file has only raw OOB data, and will
7330 be smaller than "length" since it will contain only the
7331 spare areas associated with each data page.
7335 @deffn Command {nand erase} num [offset length]
7336 @cindex NAND erasing
7337 @cindex NAND programming
7338 Erases blocks on the specified NAND device, starting at the
7339 specified @var{offset} and continuing for @var{length} bytes.
7340 Both of those values must be exact multiples of the device's
7341 block size, and the region they specify must fit entirely in the chip.
7342 If those parameters are not specified,
7343 the whole NAND chip will be erased.
7344 The @var{num} parameter is the value shown by @command{nand list}.
7346 @b{NOTE:} This command will try to erase bad blocks, when told
7347 to do so, which will probably invalidate the manufacturer's bad
7349 For the remainder of the current server session, @command{nand info}
7350 will still report that the block ``is'' bad.
7353 @deffn Command {nand write} num filename offset [option...]
7354 @cindex NAND writing
7355 @cindex NAND programming
7356 Writes binary data from the file into the specified NAND device,
7357 starting at the specified offset. Those pages should already
7358 have been erased; you can't change zero bits to one bits.
7359 The @var{num} parameter is the value shown by @command{nand list}.
7361 Use a complete path name for @var{filename}, so you don't depend
7362 on the directory used to start the OpenOCD server.
7364 The @var{offset} must be an exact multiple of the device's page size.
7365 All data in the file will be written, assuming it doesn't run
7366 past the end of the device.
7367 Only full pages are written, and any extra space in the last
7368 page will be filled with 0xff bytes. (That includes OOB data,
7369 if that's being written.)
7371 @b{NOTE:} At the time this text was written, bad blocks are
7372 ignored. That is, this routine will not skip bad blocks,
7373 but will instead try to write them. This can cause problems.
7375 Provide at most one @var{option} parameter. With some
7376 NAND drivers, the meanings of these parameters may change
7377 if @command{nand raw_access} was used to disable hardware ECC.
7379 @item no oob_* parameter
7380 @*File has only page data, which is written.
7381 If raw access is in use, the OOB area will not be written.
7382 Otherwise, if the underlying NAND controller driver has
7383 a @code{write_page} routine, that routine may write the OOB
7384 with hardware-computed ECC data.
7385 @item @code{oob_only}
7386 @*File has only raw OOB data, which is written to the OOB area.
7387 Each page's data area stays untouched. @i{This can be a dangerous
7388 option}, since it can invalidate the ECC data.
7389 You may need to force raw access to use this mode.
7390 @item @code{oob_raw}
7391 @*File interleaves data and OOB data, both of which are written
7392 If raw access is enabled, the data is written first, then the
7394 Otherwise, if the underlying NAND controller driver has
7395 a @code{write_page} routine, that routine may modify the OOB
7396 before it's written, to include hardware-computed ECC data.
7397 @item @code{oob_softecc}
7398 @*File has only page data, which is written.
7399 The OOB area is filled with 0xff, except for a standard 1-bit
7400 software ECC code stored in conventional locations.
7401 You might need to force raw access to use this mode, to prevent
7402 the underlying driver from applying hardware ECC.
7403 @item @code{oob_softecc_kw}
7404 @*File has only page data, which is written.
7405 The OOB area is filled with 0xff, except for a 4-bit software ECC
7406 specific to the boot ROM in Marvell Kirkwood SoCs.
7407 You might need to force raw access to use this mode, to prevent
7408 the underlying driver from applying hardware ECC.
7412 @deffn Command {nand verify} num filename offset [option...]
7413 @cindex NAND verification
7414 @cindex NAND programming
7415 Verify the binary data in the file has been programmed to the
7416 specified NAND device, starting at the specified offset.
7417 The @var{num} parameter is the value shown by @command{nand list}.
7419 Use a complete path name for @var{filename}, so you don't depend
7420 on the directory used to start the OpenOCD server.
7422 The @var{offset} must be an exact multiple of the device's page size.
7423 All data in the file will be read and compared to the contents of the
7424 flash, assuming it doesn't run past the end of the device.
7425 As with @command{nand write}, only full pages are verified, so any extra
7426 space in the last page will be filled with 0xff bytes.
7428 The same @var{options} accepted by @command{nand write},
7429 and the file will be processed similarly to produce the buffers that
7430 can be compared against the contents produced from @command{nand dump}.
7432 @b{NOTE:} This will not work when the underlying NAND controller
7433 driver's @code{write_page} routine must update the OOB with a
7434 hardware-computed ECC before the data is written. This limitation may
7435 be removed in a future release.
7438 @subsection Other NAND commands
7439 @cindex NAND other commands
7441 @deffn Command {nand check_bad_blocks} num [offset length]
7442 Checks for manufacturer bad block markers on the specified NAND
7443 device. If no parameters are provided, checks the whole
7444 device; otherwise, starts at the specified @var{offset} and
7445 continues for @var{length} bytes.
7446 Both of those values must be exact multiples of the device's
7447 block size, and the region they specify must fit entirely in the chip.
7448 The @var{num} parameter is the value shown by @command{nand list}.
7450 @b{NOTE:} Before using this command you should force raw access
7451 with @command{nand raw_access enable} to ensure that the underlying
7452 driver will not try to apply hardware ECC.
7455 @deffn Command {nand info} num
7456 The @var{num} parameter is the value shown by @command{nand list}.
7457 This prints the one-line summary from "nand list", plus for
7458 devices which have been probed this also prints any known
7459 status for each block.
7462 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
7463 Sets or clears an flag affecting how page I/O is done.
7464 The @var{num} parameter is the value shown by @command{nand list}.
7466 This flag is cleared (disabled) by default, but changing that
7467 value won't affect all NAND devices. The key factor is whether
7468 the underlying driver provides @code{read_page} or @code{write_page}
7469 methods. If it doesn't provide those methods, the setting of
7470 this flag is irrelevant; all access is effectively ``raw''.
7472 When those methods exist, they are normally used when reading
7473 data (@command{nand dump} or reading bad block markers) or
7474 writing it (@command{nand write}). However, enabling
7475 raw access (setting the flag) prevents use of those methods,
7476 bypassing hardware ECC logic.
7477 @i{This can be a dangerous option}, since writing blocks
7478 with the wrong ECC data can cause them to be marked as bad.
7481 @anchor{nanddriverlist}
7482 @subsection NAND Driver List
7483 As noted above, the @command{nand device} command allows
7484 driver-specific options and behaviors.
7485 Some controllers also activate controller-specific commands.
7487 @deffn {NAND Driver} at91sam9
7488 This driver handles the NAND controllers found on AT91SAM9 family chips from
7489 Atmel. It takes two extra parameters: address of the NAND chip;
7490 address of the ECC controller.
7492 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
7494 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
7495 @code{read_page} methods are used to utilize the ECC hardware unless they are
7496 disabled by using the @command{nand raw_access} command. There are four
7497 additional commands that are needed to fully configure the AT91SAM9 NAND
7498 controller. Two are optional; most boards use the same wiring for ALE/CLE:
7499 @deffn Command {at91sam9 cle} num addr_line
7500 Configure the address line used for latching commands. The @var{num}
7501 parameter is the value shown by @command{nand list}.
7503 @deffn Command {at91sam9 ale} num addr_line
7504 Configure the address line used for latching addresses. The @var{num}
7505 parameter is the value shown by @command{nand list}.
7508 For the next two commands, it is assumed that the pins have already been
7509 properly configured for input or output.
7510 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
7511 Configure the RDY/nBUSY input from the NAND device. The @var{num}
7512 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7513 is the base address of the PIO controller and @var{pin} is the pin number.
7515 @deffn Command {at91sam9 ce} num pio_base_addr pin
7516 Configure the chip enable input to the NAND device. The @var{num}
7517 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7518 is the base address of the PIO controller and @var{pin} is the pin number.
7522 @deffn {NAND Driver} davinci
7523 This driver handles the NAND controllers found on DaVinci family
7524 chips from Texas Instruments.
7525 It takes three extra parameters:
7526 address of the NAND chip;
7527 hardware ECC mode to use (@option{hwecc1},
7528 @option{hwecc4}, @option{hwecc4_infix});
7529 address of the AEMIF controller on this processor.
7531 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
7533 All DaVinci processors support the single-bit ECC hardware,
7534 and newer ones also support the four-bit ECC hardware.
7535 The @code{write_page} and @code{read_page} methods are used
7536 to implement those ECC modes, unless they are disabled using
7537 the @command{nand raw_access} command.
7540 @deffn {NAND Driver} lpc3180
7541 These controllers require an extra @command{nand device}
7542 parameter: the clock rate used by the controller.
7543 @deffn Command {lpc3180 select} num [mlc|slc]
7544 Configures use of the MLC or SLC controller mode.
7545 MLC implies use of hardware ECC.
7546 The @var{num} parameter is the value shown by @command{nand list}.
7549 At this writing, this driver includes @code{write_page}
7550 and @code{read_page} methods. Using @command{nand raw_access}
7551 to disable those methods will prevent use of hardware ECC
7552 in the MLC controller mode, but won't change SLC behavior.
7554 @comment current lpc3180 code won't issue 5-byte address cycles
7556 @deffn {NAND Driver} mx3
7557 This driver handles the NAND controller in i.MX31. The mxc driver
7558 should work for this chip as well.
7561 @deffn {NAND Driver} mxc
7562 This driver handles the NAND controller found in Freescale i.MX
7563 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
7564 The driver takes 3 extra arguments, chip (@option{mx27},
7565 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
7566 and optionally if bad block information should be swapped between
7567 main area and spare area (@option{biswap}), defaults to off.
7569 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
7571 @deffn Command {mxc biswap} bank_num [enable|disable]
7572 Turns on/off bad block information swapping from main area,
7573 without parameter query status.
7577 @deffn {NAND Driver} orion
7578 These controllers require an extra @command{nand device}
7579 parameter: the address of the controller.
7581 nand device orion 0xd8000000
7583 These controllers don't define any specialized commands.
7584 At this writing, their drivers don't include @code{write_page}
7585 or @code{read_page} methods, so @command{nand raw_access} won't
7586 change any behavior.
7589 @deffn {NAND Driver} s3c2410
7590 @deffnx {NAND Driver} s3c2412
7591 @deffnx {NAND Driver} s3c2440
7592 @deffnx {NAND Driver} s3c2443
7593 @deffnx {NAND Driver} s3c6400
7594 These S3C family controllers don't have any special
7595 @command{nand device} options, and don't define any
7596 specialized commands.
7597 At this writing, their drivers don't include @code{write_page}
7598 or @code{read_page} methods, so @command{nand raw_access} won't
7599 change any behavior.
7602 @node Flash Programming
7603 @chapter Flash Programming
7605 OpenOCD implements numerous ways to program the target flash, whether internal or external.
7606 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
7607 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
7609 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
7610 OpenOCD will program/verify/reset the target and optionally shutdown.
7612 The script is executed as follows and by default the following actions will be performed.
7614 @item 'init' is executed.
7615 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
7616 @item @code{flash write_image} is called to erase and write any flash using the filename given.
7617 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
7618 @item @code{verify_image} is called if @option{verify} parameter is given.
7619 @item @code{reset run} is called if @option{reset} parameter is given.
7620 @item OpenOCD is shutdown if @option{exit} parameter is given.
7623 An example of usage is given below. @xref{program}.
7626 # program and verify using elf/hex/s19. verify and reset
7627 # are optional parameters
7628 openocd -f board/stm32f3discovery.cfg \
7629 -c "program filename.elf verify reset exit"
7631 # binary files need the flash address passing
7632 openocd -f board/stm32f3discovery.cfg \
7633 -c "program filename.bin exit 0x08000000"
7636 @node PLD/FPGA Commands
7637 @chapter PLD/FPGA Commands
7641 Programmable Logic Devices (PLDs) and the more flexible
7642 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
7643 OpenOCD can support programming them.
7644 Although PLDs are generally restrictive (cells are less functional, and
7645 there are no special purpose cells for memory or computational tasks),
7646 they share the same OpenOCD infrastructure.
7647 Accordingly, both are called PLDs here.
7649 @section PLD/FPGA Configuration and Commands
7651 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
7652 OpenOCD maintains a list of PLDs available for use in various commands.
7653 Also, each such PLD requires a driver.
7655 They are referenced by the number shown by the @command{pld devices} command,
7656 and new PLDs are defined by @command{pld device driver_name}.
7658 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
7659 Defines a new PLD device, supported by driver @var{driver_name},
7660 using the TAP named @var{tap_name}.
7661 The driver may make use of any @var{driver_options} to configure its
7665 @deffn {Command} {pld devices}
7666 Lists the PLDs and their numbers.
7669 @deffn {Command} {pld load} num filename
7670 Loads the file @file{filename} into the PLD identified by @var{num}.
7671 The file format must be inferred by the driver.
7674 @section PLD/FPGA Drivers, Options, and Commands
7676 Drivers may support PLD-specific options to the @command{pld device}
7677 definition command, and may also define commands usable only with
7678 that particular type of PLD.
7680 @deffn {FPGA Driver} virtex2 [no_jstart]
7681 Virtex-II is a family of FPGAs sold by Xilinx.
7682 It supports the IEEE 1532 standard for In-System Configuration (ISC).
7684 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
7685 loading the bitstream. While required for Series2, Series3, and Series6, it
7686 breaks bitstream loading on Series7.
7688 @deffn {Command} {virtex2 read_stat} num
7689 Reads and displays the Virtex-II status register (STAT)
7694 @node General Commands
7695 @chapter General Commands
7698 The commands documented in this chapter here are common commands that
7699 you, as a human, may want to type and see the output of. Configuration type
7700 commands are documented elsewhere.
7704 @item @b{Source Of Commands}
7705 @* OpenOCD commands can occur in a configuration script (discussed
7706 elsewhere) or typed manually by a human or supplied programmatically,
7707 or via one of several TCP/IP Ports.
7709 @item @b{From the human}
7710 @* A human should interact with the telnet interface (default port: 4444)
7711 or via GDB (default port 3333).
7713 To issue commands from within a GDB session, use the @option{monitor}
7714 command, e.g. use @option{monitor poll} to issue the @option{poll}
7715 command. All output is relayed through the GDB session.
7717 @item @b{Machine Interface}
7718 The Tcl interface's intent is to be a machine interface. The default Tcl
7723 @section Server Commands
7725 @deffn {Command} exit
7726 Exits the current telnet session.
7729 @deffn {Command} help [string]
7730 With no parameters, prints help text for all commands.
7731 Otherwise, prints each helptext containing @var{string}.
7732 Not every command provides helptext.
7734 Configuration commands, and commands valid at any time, are
7735 explicitly noted in parenthesis.
7736 In most cases, no such restriction is listed; this indicates commands
7737 which are only available after the configuration stage has completed.
7740 @deffn Command sleep msec [@option{busy}]
7741 Wait for at least @var{msec} milliseconds before resuming.
7742 If @option{busy} is passed, busy-wait instead of sleeping.
7743 (This option is strongly discouraged.)
7744 Useful in connection with script files
7745 (@command{script} command and @command{target_name} configuration).
7748 @deffn Command shutdown [@option{error}]
7749 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
7750 other). If option @option{error} is used, OpenOCD will return a
7751 non-zero exit code to the parent process.
7753 Like any TCL commands, also @command{shutdown} can be redefined, e.g.:
7756 rename shutdown original_shutdown
7757 proc shutdown @{@} @{
7758 puts "This is my implementation of shutdown"
7759 # my own stuff before exit OpenOCD
7763 If user types CTRL-C or kills OpenOCD, either the command @command{shutdown}
7764 or its replacement will be automatically executed before OpenOCD exits.
7768 @deffn Command debug_level [n]
7769 @cindex message level
7770 Display debug level.
7771 If @var{n} (from 0..4) is provided, then set it to that level.
7772 This affects the kind of messages sent to the server log.
7773 Level 0 is error messages only;
7774 level 1 adds warnings;
7775 level 2 adds informational messages;
7776 level 3 adds debugging messages;
7777 and level 4 adds verbose low-level debug messages.
7778 The default is level 2, but that can be overridden on
7779 the command line along with the location of that log
7780 file (which is normally the server's standard output).
7784 @deffn Command echo [-n] message
7785 Logs a message at "user" priority.
7786 Output @var{message} to stdout.
7787 Option "-n" suppresses trailing newline.
7789 echo "Downloading kernel -- please wait"
7793 @deffn Command log_output [filename]
7794 Redirect logging to @var{filename};
7795 the initial log output channel is stderr.
7798 @deffn Command add_script_search_dir [directory]
7799 Add @var{directory} to the file/script search path.
7802 @deffn Command bindto [@var{name}]
7803 Specify hostname or IPv4 address on which to listen for incoming
7804 TCP/IP connections. By default, OpenOCD will listen on the loopback
7805 interface only. If your network environment is safe, @code{bindto
7806 0.0.0.0} can be used to cover all available interfaces.
7809 @anchor{targetstatehandling}
7810 @section Target State handling
7813 @cindex target initialization
7815 In this section ``target'' refers to a CPU configured as
7816 shown earlier (@pxref{CPU Configuration}).
7817 These commands, like many, implicitly refer to
7818 a current target which is used to perform the
7819 various operations. The current target may be changed
7820 by using @command{targets} command with the name of the
7821 target which should become current.
7823 @deffn Command reg [(number|name) [(value|'force')]]
7824 Access a single register by @var{number} or by its @var{name}.
7825 The target must generally be halted before access to CPU core
7826 registers is allowed. Depending on the hardware, some other
7827 registers may be accessible while the target is running.
7829 @emph{With no arguments}:
7830 list all available registers for the current target,
7831 showing number, name, size, value, and cache status.
7832 For valid entries, a value is shown; valid entries
7833 which are also dirty (and will be written back later)
7834 are flagged as such.
7836 @emph{With number/name}: display that register's value.
7837 Use @var{force} argument to read directly from the target,
7838 bypassing any internal cache.
7840 @emph{With both number/name and value}: set register's value.
7841 Writes may be held in a writeback cache internal to OpenOCD,
7842 so that setting the value marks the register as dirty instead
7843 of immediately flushing that value. Resuming CPU execution
7844 (including by single stepping) or otherwise activating the
7845 relevant module will flush such values.
7847 Cores may have surprisingly many registers in their
7848 Debug and trace infrastructure:
7853 (0) r0 (/32): 0x0000D3C2 (dirty)
7854 (1) r1 (/32): 0xFD61F31C
7857 (164) ETM_contextid_comparator_mask (/32)
7862 @deffn Command halt [ms]
7863 @deffnx Command wait_halt [ms]
7864 The @command{halt} command first sends a halt request to the target,
7865 which @command{wait_halt} doesn't.
7866 Otherwise these behave the same: wait up to @var{ms} milliseconds,
7867 or 5 seconds if there is no parameter, for the target to halt
7868 (and enter debug mode).
7869 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
7872 On ARM cores, software using the @emph{wait for interrupt} operation
7873 often blocks the JTAG access needed by a @command{halt} command.
7874 This is because that operation also puts the core into a low
7875 power mode by gating the core clock;
7876 but the core clock is needed to detect JTAG clock transitions.
7878 One partial workaround uses adaptive clocking: when the core is
7879 interrupted the operation completes, then JTAG clocks are accepted
7880 at least until the interrupt handler completes.
7881 However, this workaround is often unusable since the processor, board,
7882 and JTAG adapter must all support adaptive JTAG clocking.
7883 Also, it can't work until an interrupt is issued.
7885 A more complete workaround is to not use that operation while you
7886 work with a JTAG debugger.
7887 Tasking environments generally have idle loops where the body is the
7888 @emph{wait for interrupt} operation.
7889 (On older cores, it is a coprocessor action;
7890 newer cores have a @option{wfi} instruction.)
7891 Such loops can just remove that operation, at the cost of higher
7892 power consumption (because the CPU is needlessly clocked).
7897 @deffn Command resume [address]
7898 Resume the target at its current code position,
7899 or the optional @var{address} if it is provided.
7900 OpenOCD will wait 5 seconds for the target to resume.
7903 @deffn Command step [address]
7904 Single-step the target at its current code position,
7905 or the optional @var{address} if it is provided.
7908 @anchor{resetcommand}
7909 @deffn Command reset
7910 @deffnx Command {reset run}
7911 @deffnx Command {reset halt}
7912 @deffnx Command {reset init}
7913 Perform as hard a reset as possible, using SRST if possible.
7914 @emph{All defined targets will be reset, and target
7915 events will fire during the reset sequence.}
7917 The optional parameter specifies what should
7918 happen after the reset.
7919 If there is no parameter, a @command{reset run} is executed.
7920 The other options will not work on all systems.
7921 @xref{Reset Configuration}.
7924 @item @b{run} Let the target run
7925 @item @b{halt} Immediately halt the target
7926 @item @b{init} Immediately halt the target, and execute the reset-init script
7930 @deffn Command soft_reset_halt
7931 Requesting target halt and executing a soft reset. This is often used
7932 when a target cannot be reset and halted. The target, after reset is
7933 released begins to execute code. OpenOCD attempts to stop the CPU and
7934 then sets the program counter back to the reset vector. Unfortunately
7935 the code that was executed may have left the hardware in an unknown
7939 @deffn Command {adapter assert} [signal [assert|deassert signal]]
7940 @deffnx Command {adapter deassert} [signal [assert|deassert signal]]
7941 Set values of reset signals.
7942 Without parameters returns current status of the signals.
7943 The @var{signal} parameter values may be
7944 @option{srst}, indicating that srst signal is to be asserted or deasserted,
7945 @option{trst}, indicating that trst signal is to be asserted or deasserted.
7947 The @command{reset_config} command should already have been used
7948 to configure how the board and the adapter treat these two
7949 signals, and to say if either signal is even present.
7950 @xref{Reset Configuration}.
7951 Trying to assert a signal that is not present triggers an error.
7952 If a signal is present on the adapter and not specified in the command,
7953 the signal will not be modified.
7956 TRST is specially handled.
7957 It actually signifies JTAG's @sc{reset} state.
7958 So if the board doesn't support the optional TRST signal,
7959 or it doesn't support it along with the specified SRST value,
7960 JTAG reset is triggered with TMS and TCK signals
7961 instead of the TRST signal.
7962 And no matter how that JTAG reset is triggered, once
7963 the scan chain enters @sc{reset} with TRST inactive,
7964 TAP @code{post-reset} events are delivered to all TAPs
7965 with handlers for that event.
7969 @section I/O Utilities
7971 These commands are available when
7972 OpenOCD is built with @option{--enable-ioutil}.
7973 They are mainly useful on embedded targets,
7975 Hosts with operating systems have complementary tools.
7977 @emph{Note:} there are several more such commands.
7979 @deffn Command append_file filename [string]*
7980 Appends the @var{string} parameters to
7981 the text file @file{filename}.
7982 Each string except the last one is followed by one space.
7983 The last string is followed by a newline.
7986 @deffn Command cat filename
7987 Reads and displays the text file @file{filename}.
7990 @deffn Command cp src_filename dest_filename
7991 Copies contents from the file @file{src_filename}
7992 into @file{dest_filename}.
7996 @emph{No description provided.}
8000 @emph{No description provided.}
8004 @emph{No description provided.}
8007 @deffn Command meminfo
8008 Display available RAM memory on OpenOCD host.
8009 Used in OpenOCD regression testing scripts.
8013 @emph{No description provided.}
8017 @emph{No description provided.}
8020 @deffn Command rm filename
8021 @c "rm" has both normal and Jim-level versions??
8022 Unlinks the file @file{filename}.
8025 @deffn Command trunc filename
8026 Removes all data in the file @file{filename}.
8029 @anchor{memoryaccess}
8030 @section Memory access commands
8031 @cindex memory access
8033 These commands allow accesses of a specific size to the memory
8034 system. Often these are used to configure the current target in some
8035 special way. For example - one may need to write certain values to the
8036 SDRAM controller to enable SDRAM.
8039 @item Use the @command{targets} (plural) command
8040 to change the current target.
8041 @item In system level scripts these commands are deprecated.
8042 Please use their TARGET object siblings to avoid making assumptions
8043 about what TAP is the current target, or about MMU configuration.
8046 @deffn Command mdd [phys] addr [count]
8047 @deffnx Command mdw [phys] addr [count]
8048 @deffnx Command mdh [phys] addr [count]
8049 @deffnx Command mdb [phys] addr [count]
8050 Display contents of address @var{addr}, as
8051 64-bit doublewords (@command{mdd}),
8052 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8053 or 8-bit bytes (@command{mdb}).
8054 When the current target has an MMU which is present and active,
8055 @var{addr} is interpreted as a virtual address.
8056 Otherwise, or if the optional @var{phys} flag is specified,
8057 @var{addr} is interpreted as a physical address.
8058 If @var{count} is specified, displays that many units.
8059 (If you want to manipulate the data instead of displaying it,
8060 see the @code{mem2array} primitives.)
8063 @deffn Command mwd [phys] addr doubleword [count]
8064 @deffnx Command mww [phys] addr word [count]
8065 @deffnx Command mwh [phys] addr halfword [count]
8066 @deffnx Command mwb [phys] addr byte [count]
8067 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
8068 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
8069 at the specified address @var{addr}.
8070 When the current target has an MMU which is present and active,
8071 @var{addr} is interpreted as a virtual address.
8072 Otherwise, or if the optional @var{phys} flag is specified,
8073 @var{addr} is interpreted as a physical address.
8074 If @var{count} is specified, fills that many units of consecutive address.
8077 @anchor{imageaccess}
8078 @section Image loading commands
8079 @cindex image loading
8080 @cindex image dumping
8082 @deffn Command {dump_image} filename address size
8083 Dump @var{size} bytes of target memory starting at @var{address} to the
8084 binary file named @var{filename}.
8087 @deffn Command {fast_load}
8088 Loads an image stored in memory by @command{fast_load_image} to the
8089 current target. Must be preceded by fast_load_image.
8092 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
8093 Normally you should be using @command{load_image} or GDB load. However, for
8094 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
8095 host), storing the image in memory and uploading the image to the target
8096 can be a way to upload e.g. multiple debug sessions when the binary does not change.
8097 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
8098 memory, i.e. does not affect target. This approach is also useful when profiling
8099 target programming performance as I/O and target programming can easily be profiled
8103 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
8104 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
8105 The file format may optionally be specified
8106 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
8107 In addition the following arguments may be specified:
8108 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
8109 @var{max_length} - maximum number of bytes to load.
8111 proc load_image_bin @{fname foffset address length @} @{
8112 # Load data from fname filename at foffset offset to
8113 # target at address. Load at most length bytes.
8114 load_image $fname [expr $address - $foffset] bin \
8120 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
8121 Displays image section sizes and addresses
8122 as if @var{filename} were loaded into target memory
8123 starting at @var{address} (defaults to zero).
8124 The file format may optionally be specified
8125 (@option{bin}, @option{ihex}, or @option{elf})
8128 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
8129 Verify @var{filename} against target memory starting at @var{address}.
8130 The file format may optionally be specified
8131 (@option{bin}, @option{ihex}, or @option{elf})
8132 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
8135 @deffn Command {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
8136 Verify @var{filename} against target memory starting at @var{address}.
8137 The file format may optionally be specified
8138 (@option{bin}, @option{ihex}, or @option{elf})
8139 This perform a comparison using a CRC checksum only
8143 @section Breakpoint and Watchpoint commands
8147 CPUs often make debug modules accessible through JTAG, with
8148 hardware support for a handful of code breakpoints and data
8150 In addition, CPUs almost always support software breakpoints.
8152 @deffn Command {bp} [address len [@option{hw}]]
8153 With no parameters, lists all active breakpoints.
8154 Else sets a breakpoint on code execution starting
8155 at @var{address} for @var{length} bytes.
8156 This is a software breakpoint, unless @option{hw} is specified
8157 in which case it will be a hardware breakpoint.
8159 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
8160 for similar mechanisms that do not consume hardware breakpoints.)
8163 @deffn Command {rbp} address
8164 Remove the breakpoint at @var{address}.
8167 @deffn Command {rwp} address
8168 Remove data watchpoint on @var{address}
8171 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
8172 With no parameters, lists all active watchpoints.
8173 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
8174 The watch point is an "access" watchpoint unless
8175 the @option{r} or @option{w} parameter is provided,
8176 defining it as respectively a read or write watchpoint.
8177 If a @var{value} is provided, that value is used when determining if
8178 the watchpoint should trigger. The value may be first be masked
8179 using @var{mask} to mark ``don't care'' fields.
8182 @section Misc Commands
8185 @deffn Command {profile} seconds filename [start end]
8186 Profiling samples the CPU's program counter as quickly as possible,
8187 which is useful for non-intrusive stochastic profiling.
8188 Saves up to 10000 samples in @file{filename} using ``gmon.out''
8189 format. Optional @option{start} and @option{end} parameters allow to
8190 limit the address range.
8193 @deffn Command {version}
8194 Displays a string identifying the version of this OpenOCD server.
8197 @deffn Command {virt2phys} virtual_address
8198 Requests the current target to map the specified @var{virtual_address}
8199 to its corresponding physical address, and displays the result.
8202 @node Architecture and Core Commands
8203 @chapter Architecture and Core Commands
8204 @cindex Architecture Specific Commands
8205 @cindex Core Specific Commands
8207 Most CPUs have specialized JTAG operations to support debugging.
8208 OpenOCD packages most such operations in its standard command framework.
8209 Some of those operations don't fit well in that framework, so they are
8210 exposed here as architecture or implementation (core) specific commands.
8212 @anchor{armhardwaretracing}
8213 @section ARM Hardware Tracing
8218 CPUs based on ARM cores may include standard tracing interfaces,
8219 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
8220 address and data bus trace records to a ``Trace Port''.
8224 Development-oriented boards will sometimes provide a high speed
8225 trace connector for collecting that data, when the particular CPU
8226 supports such an interface.
8227 (The standard connector is a 38-pin Mictor, with both JTAG
8228 and trace port support.)
8229 Those trace connectors are supported by higher end JTAG adapters
8230 and some logic analyzer modules; frequently those modules can
8231 buffer several megabytes of trace data.
8232 Configuring an ETM coupled to such an external trace port belongs
8233 in the board-specific configuration file.
8235 If the CPU doesn't provide an external interface, it probably
8236 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
8237 dedicated SRAM. 4KBytes is one common ETB size.
8238 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
8239 (target) configuration file, since it works the same on all boards.
8242 ETM support in OpenOCD doesn't seem to be widely used yet.
8245 ETM support may be buggy, and at least some @command{etm config}
8246 parameters should be detected by asking the ETM for them.
8248 ETM trigger events could also implement a kind of complex
8249 hardware breakpoint, much more powerful than the simple
8250 watchpoint hardware exported by EmbeddedICE modules.
8251 @emph{Such breakpoints can be triggered even when using the
8252 dummy trace port driver}.
8254 It seems like a GDB hookup should be possible,
8255 as well as tracing only during specific states
8256 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
8258 There should be GUI tools to manipulate saved trace data and help
8259 analyse it in conjunction with the source code.
8260 It's unclear how much of a common interface is shared
8261 with the current XScale trace support, or should be
8262 shared with eventual Nexus-style trace module support.
8264 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
8265 for ETM modules is available. The code should be able to
8266 work with some newer cores; but not all of them support
8267 this original style of JTAG access.
8270 @subsection ETM Configuration
8271 ETM setup is coupled with the trace port driver configuration.
8273 @deffn {Config Command} {etm config} target width mode clocking driver
8274 Declares the ETM associated with @var{target}, and associates it
8275 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
8277 Several of the parameters must reflect the trace port capabilities,
8278 which are a function of silicon capabilities (exposed later
8279 using @command{etm info}) and of what hardware is connected to
8280 that port (such as an external pod, or ETB).
8281 The @var{width} must be either 4, 8, or 16,
8282 except with ETMv3.0 and newer modules which may also
8283 support 1, 2, 24, 32, 48, and 64 bit widths.
8284 (With those versions, @command{etm info} also shows whether
8285 the selected port width and mode are supported.)
8287 The @var{mode} must be @option{normal}, @option{multiplexed},
8288 or @option{demultiplexed}.
8289 The @var{clocking} must be @option{half} or @option{full}.
8292 With ETMv3.0 and newer, the bits set with the @var{mode} and
8293 @var{clocking} parameters both control the mode.
8294 This modified mode does not map to the values supported by
8295 previous ETM modules, so this syntax is subject to change.
8299 You can see the ETM registers using the @command{reg} command.
8300 Not all possible registers are present in every ETM.
8301 Most of the registers are write-only, and are used to configure
8302 what CPU activities are traced.
8306 @deffn Command {etm info}
8307 Displays information about the current target's ETM.
8308 This includes resource counts from the @code{ETM_CONFIG} register,
8309 as well as silicon capabilities (except on rather old modules).
8310 from the @code{ETM_SYS_CONFIG} register.
8313 @deffn Command {etm status}
8314 Displays status of the current target's ETM and trace port driver:
8315 is the ETM idle, or is it collecting data?
8316 Did trace data overflow?
8320 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
8321 Displays what data that ETM will collect.
8322 If arguments are provided, first configures that data.
8323 When the configuration changes, tracing is stopped
8324 and any buffered trace data is invalidated.
8327 @item @var{type} ... describing how data accesses are traced,
8328 when they pass any ViewData filtering that that was set up.
8330 @option{none} (save nothing),
8331 @option{data} (save data),
8332 @option{address} (save addresses),
8333 @option{all} (save data and addresses)
8334 @item @var{context_id_bits} ... 0, 8, 16, or 32
8335 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
8336 cycle-accurate instruction tracing.
8337 Before ETMv3, enabling this causes much extra data to be recorded.
8338 @item @var{branch_output} ... @option{enable} or @option{disable}.
8339 Disable this unless you need to try reconstructing the instruction
8340 trace stream without an image of the code.
8344 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
8345 Displays whether ETM triggering debug entry (like a breakpoint) is
8346 enabled or disabled, after optionally modifying that configuration.
8347 The default behaviour is @option{disable}.
8348 Any change takes effect after the next @command{etm start}.
8350 By using script commands to configure ETM registers, you can make the
8351 processor enter debug state automatically when certain conditions,
8352 more complex than supported by the breakpoint hardware, happen.
8355 @subsection ETM Trace Operation
8357 After setting up the ETM, you can use it to collect data.
8358 That data can be exported to files for later analysis.
8359 It can also be parsed with OpenOCD, for basic sanity checking.
8361 To configure what is being traced, you will need to write
8362 various trace registers using @command{reg ETM_*} commands.
8363 For the definitions of these registers, read ARM publication
8364 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
8365 Be aware that most of the relevant registers are write-only,
8366 and that ETM resources are limited. There are only a handful
8367 of address comparators, data comparators, counters, and so on.
8369 Examples of scenarios you might arrange to trace include:
8372 @item Code flow within a function, @emph{excluding} subroutines
8373 it calls. Use address range comparators to enable tracing
8374 for instruction access within that function's body.
8375 @item Code flow within a function, @emph{including} subroutines
8376 it calls. Use the sequencer and address comparators to activate
8377 tracing on an ``entered function'' state, then deactivate it by
8378 exiting that state when the function's exit code is invoked.
8379 @item Code flow starting at the fifth invocation of a function,
8380 combining one of the above models with a counter.
8381 @item CPU data accesses to the registers for a particular device,
8382 using address range comparators and the ViewData logic.
8383 @item Such data accesses only during IRQ handling, combining the above
8384 model with sequencer triggers which on entry and exit to the IRQ handler.
8385 @item @emph{... more}
8388 At this writing, September 2009, there are no Tcl utility
8389 procedures to help set up any common tracing scenarios.
8391 @deffn Command {etm analyze}
8392 Reads trace data into memory, if it wasn't already present.
8393 Decodes and prints the data that was collected.
8396 @deffn Command {etm dump} filename
8397 Stores the captured trace data in @file{filename}.
8400 @deffn Command {etm image} filename [base_address] [type]
8401 Opens an image file.
8404 @deffn Command {etm load} filename
8405 Loads captured trace data from @file{filename}.
8408 @deffn Command {etm start}
8409 Starts trace data collection.
8412 @deffn Command {etm stop}
8413 Stops trace data collection.
8416 @anchor{traceportdrivers}
8417 @subsection Trace Port Drivers
8419 To use an ETM trace port it must be associated with a driver.
8421 @deffn {Trace Port Driver} dummy
8422 Use the @option{dummy} driver if you are configuring an ETM that's
8423 not connected to anything (on-chip ETB or off-chip trace connector).
8424 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
8425 any trace data collection.}
8426 @deffn {Config Command} {etm_dummy config} target
8427 Associates the ETM for @var{target} with a dummy driver.
8431 @deffn {Trace Port Driver} etb
8432 Use the @option{etb} driver if you are configuring an ETM
8433 to use on-chip ETB memory.
8434 @deffn {Config Command} {etb config} target etb_tap
8435 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
8436 You can see the ETB registers using the @command{reg} command.
8438 @deffn Command {etb trigger_percent} [percent]
8439 This displays, or optionally changes, ETB behavior after the
8440 ETM's configured @emph{trigger} event fires.
8441 It controls how much more trace data is saved after the (single)
8442 trace trigger becomes active.
8445 @item The default corresponds to @emph{trace around} usage,
8446 recording 50 percent data before the event and the rest
8448 @item The minimum value of @var{percent} is 2 percent,
8449 recording almost exclusively data before the trigger.
8450 Such extreme @emph{trace before} usage can help figure out
8451 what caused that event to happen.
8452 @item The maximum value of @var{percent} is 100 percent,
8453 recording data almost exclusively after the event.
8454 This extreme @emph{trace after} usage might help sort out
8455 how the event caused trouble.
8457 @c REVISIT allow "break" too -- enter debug mode.
8462 @deffn {Trace Port Driver} oocd_trace
8463 This driver isn't available unless OpenOCD was explicitly configured
8464 with the @option{--enable-oocd_trace} option. You probably don't want
8465 to configure it unless you've built the appropriate prototype hardware;
8466 it's @emph{proof-of-concept} software.
8468 Use the @option{oocd_trace} driver if you are configuring an ETM that's
8469 connected to an off-chip trace connector.
8471 @deffn {Config Command} {oocd_trace config} target tty
8472 Associates the ETM for @var{target} with a trace driver which
8473 collects data through the serial port @var{tty}.
8476 @deffn Command {oocd_trace resync}
8477 Re-synchronizes with the capture clock.
8480 @deffn Command {oocd_trace status}
8481 Reports whether the capture clock is locked or not.
8485 @anchor{armcrosstrigger}
8486 @section ARM Cross-Trigger Interface
8489 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
8490 that connects event sources like tracing components or CPU cores with each
8491 other through a common trigger matrix (CTM). For ARMv8 architecture, a
8492 CTI is mandatory for core run control and each core has an individual
8493 CTI instance attached to it. OpenOCD has limited support for CTI using
8494 the @emph{cti} group of commands.
8496 @deffn Command {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-ctibase} base_address
8497 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
8498 @var{apn}. The @var{base_address} must match the base address of the CTI
8499 on the respective MEM-AP. All arguments are mandatory. This creates a
8500 new command @command{$cti_name} which is used for various purposes
8501 including additional configuration.
8504 @deffn Command {$cti_name enable} @option{on|off}
8505 Enable (@option{on}) or disable (@option{off}) the CTI.
8508 @deffn Command {$cti_name dump}
8509 Displays a register dump of the CTI.
8512 @deffn Command {$cti_name write } @var{reg_name} @var{value}
8513 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
8516 @deffn Command {$cti_name read} @var{reg_name}
8517 Print the value read from the CTI register with the symbolic name @var{reg_name}.
8520 @deffn Command {$cti_name ack} @var{event}
8521 Acknowledge a CTI @var{event}.
8524 @deffn Command {$cti_name channel} @var{channel_number} @var{operation}
8525 Perform a specific channel operation, the possible operations are:
8526 gate, ungate, set, clear and pulse
8529 @deffn Command {$cti_name testmode} @option{on|off}
8530 Enable (@option{on}) or disable (@option{off}) the integration test mode
8534 @deffn Command {cti names}
8535 Prints a list of names of all CTI objects created. This command is mainly
8536 useful in TCL scripting.
8539 @section Generic ARM
8542 These commands should be available on all ARM processors.
8543 They are available in addition to other core-specific
8544 commands that may be available.
8546 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
8547 Displays the core_state, optionally changing it to process
8548 either @option{arm} or @option{thumb} instructions.
8549 The target may later be resumed in the currently set core_state.
8550 (Processors may also support the Jazelle state, but
8551 that is not currently supported in OpenOCD.)
8554 @deffn Command {arm disassemble} address [count [@option{thumb}]]
8556 Disassembles @var{count} instructions starting at @var{address}.
8557 If @var{count} is not specified, a single instruction is disassembled.
8558 If @option{thumb} is specified, or the low bit of the address is set,
8559 Thumb2 (mixed 16/32-bit) instructions are used;
8560 else ARM (32-bit) instructions are used.
8561 (Processors may also support the Jazelle state, but
8562 those instructions are not currently understood by OpenOCD.)
8564 Note that all Thumb instructions are Thumb2 instructions,
8565 so older processors (without Thumb2 support) will still
8566 see correct disassembly of Thumb code.
8567 Also, ThumbEE opcodes are the same as Thumb2,
8568 with a handful of exceptions.
8569 ThumbEE disassembly currently has no explicit support.
8572 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
8573 Write @var{value} to a coprocessor @var{pX} register
8574 passing parameters @var{CRn},
8575 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8576 and using the MCR instruction.
8577 (Parameter sequence matches the ARM instruction, but omits
8581 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
8582 Read a coprocessor @var{pX} register passing parameters @var{CRn},
8583 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8584 and the MRC instruction.
8585 Returns the result so it can be manipulated by Jim scripts.
8586 (Parameter sequence matches the ARM instruction, but omits
8590 @deffn Command {arm reg}
8591 Display a table of all banked core registers, fetching the current value from every
8592 core mode if necessary.
8595 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
8596 @cindex ARM semihosting
8597 Display status of semihosting, after optionally changing that status.
8599 Semihosting allows for code executing on an ARM target to use the
8600 I/O facilities on the host computer i.e. the system where OpenOCD
8601 is running. The target application must be linked against a library
8602 implementing the ARM semihosting convention that forwards operation
8603 requests by using a special SVC instruction that is trapped at the
8604 Supervisor Call vector by OpenOCD.
8607 @deffn Command {arm semihosting_cmdline} [@option{enable}|@option{disable}]
8608 @cindex ARM semihosting
8609 Set the command line to be passed to the debugger.
8612 arm semihosting_cmdline argv0 argv1 argv2 ...
8615 This option lets one set the command line arguments to be passed to
8616 the program. The first argument (argv0) is the program name in a
8617 standard C environment (argv[0]). Depending on the program (not much
8618 programs look at argv[0]), argv0 is ignored and can be any string.
8621 @deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
8622 @cindex ARM semihosting
8623 Display status of semihosting fileio, after optionally changing that
8626 Enabling this option forwards semihosting I/O to GDB process using the
8627 File-I/O remote protocol extension. This is especially useful for
8628 interacting with remote files or displaying console messages in the
8632 @deffn Command {arm semihosting_resexit} [@option{enable}|@option{disable}]
8633 @cindex ARM semihosting
8634 Enable resumable SEMIHOSTING_SYS_EXIT.
8636 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
8637 things are simple, the openocd process calls exit() and passes
8638 the value returned by the target.
8640 When SEMIHOSTING_SYS_EXIT is called during a debug session,
8641 by default execution returns to the debugger, leaving the
8642 debugger in a HALT state, similar to the state entered when
8643 encountering a break.
8645 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
8646 return normally, as any semihosting call, and do not break
8648 The standard allows this to happen, but the condition
8649 to trigger it is a bit obscure ("by performing an RDI_Execute
8650 request or equivalent").
8652 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
8653 this option (default: disabled).
8656 @section ARMv4 and ARMv5 Architecture
8660 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
8661 and introduced core parts of the instruction set in use today.
8662 That includes the Thumb instruction set, introduced in the ARMv4T
8665 @subsection ARM7 and ARM9 specific commands
8669 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
8670 ARM9TDMI, ARM920T or ARM926EJ-S.
8671 They are available in addition to the ARM commands,
8672 and any other core-specific commands that may be available.
8674 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
8675 Displays the value of the flag controlling use of the
8676 the EmbeddedIce DBGRQ signal to force entry into debug mode,
8677 instead of breakpoints.
8678 If a boolean parameter is provided, first assigns that flag.
8681 safe for all but ARM7TDMI-S cores (like NXP LPC).
8682 This feature is enabled by default on most ARM9 cores,
8683 including ARM9TDMI, ARM920T, and ARM926EJ-S.
8686 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
8688 Displays the value of the flag controlling use of the debug communications
8689 channel (DCC) to write larger (>128 byte) amounts of memory.
8690 If a boolean parameter is provided, first assigns that flag.
8692 DCC downloads offer a huge speed increase, but might be
8693 unsafe, especially with targets running at very low speeds. This command was introduced
8694 with OpenOCD rev. 60, and requires a few bytes of working area.
8697 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
8698 Displays the value of the flag controlling use of memory writes and reads
8699 that don't check completion of the operation.
8700 If a boolean parameter is provided, first assigns that flag.
8702 This provides a huge speed increase, especially with USB JTAG
8703 cables (FT2232), but might be unsafe if used with targets running at very low
8704 speeds, like the 32kHz startup clock of an AT91RM9200.
8707 @subsection ARM720T specific commands
8710 These commands are available to ARM720T based CPUs,
8711 which are implementations of the ARMv4T architecture
8712 based on the ARM7TDMI-S integer core.
8713 They are available in addition to the ARM and ARM7/ARM9 commands.
8715 @deffn Command {arm720t cp15} opcode [value]
8716 @emph{DEPRECATED -- avoid using this.
8717 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8719 Display cp15 register returned by the ARM instruction @var{opcode};
8720 else if a @var{value} is provided, that value is written to that register.
8721 The @var{opcode} should be the value of either an MRC or MCR instruction.
8724 @subsection ARM9 specific commands
8727 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
8729 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
8731 @c 9-june-2009: tried this on arm920t, it didn't work.
8732 @c no-params always lists nothing caught, and that's how it acts.
8733 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
8734 @c versions have different rules about when they commit writes.
8736 @anchor{arm9vectorcatch}
8737 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
8738 @cindex vector_catch
8739 Vector Catch hardware provides a sort of dedicated breakpoint
8740 for hardware events such as reset, interrupt, and abort.
8741 You can use this to conserve normal breakpoint resources,
8742 so long as you're not concerned with code that branches directly
8743 to those hardware vectors.
8745 This always finishes by listing the current configuration.
8746 If parameters are provided, it first reconfigures the
8747 vector catch hardware to intercept
8748 @option{all} of the hardware vectors,
8749 @option{none} of them,
8750 or a list with one or more of the following:
8751 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
8752 @option{irq} @option{fiq}.
8755 @subsection ARM920T specific commands
8758 These commands are available to ARM920T based CPUs,
8759 which are implementations of the ARMv4T architecture
8760 built using the ARM9TDMI integer core.
8761 They are available in addition to the ARM, ARM7/ARM9,
8764 @deffn Command {arm920t cache_info}
8765 Print information about the caches found. This allows to see whether your target
8766 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
8769 @deffn Command {arm920t cp15} regnum [value]
8770 Display cp15 register @var{regnum};
8771 else if a @var{value} is provided, that value is written to that register.
8772 This uses "physical access" and the register number is as
8773 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
8774 (Not all registers can be written.)
8777 @deffn Command {arm920t cp15i} opcode [value [address]]
8778 @emph{DEPRECATED -- avoid using this.
8779 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8781 Interpreted access using ARM instruction @var{opcode}, which should
8782 be the value of either an MRC or MCR instruction
8783 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
8784 If no @var{value} is provided, the result is displayed.
8785 Else if that value is written using the specified @var{address},
8786 or using zero if no other address is provided.
8789 @deffn Command {arm920t read_cache} filename
8790 Dump the content of ICache and DCache to a file named @file{filename}.
8793 @deffn Command {arm920t read_mmu} filename
8794 Dump the content of the ITLB and DTLB to a file named @file{filename}.
8797 @subsection ARM926ej-s specific commands
8800 These commands are available to ARM926ej-s based CPUs,
8801 which are implementations of the ARMv5TEJ architecture
8802 based on the ARM9EJ-S integer core.
8803 They are available in addition to the ARM, ARM7/ARM9,
8806 The Feroceon cores also support these commands, although
8807 they are not built from ARM926ej-s designs.
8809 @deffn Command {arm926ejs cache_info}
8810 Print information about the caches found.
8813 @subsection ARM966E specific commands
8816 These commands are available to ARM966 based CPUs,
8817 which are implementations of the ARMv5TE architecture.
8818 They are available in addition to the ARM, ARM7/ARM9,
8821 @deffn Command {arm966e cp15} regnum [value]
8822 Display cp15 register @var{regnum};
8823 else if a @var{value} is provided, that value is written to that register.
8824 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
8826 There is no current control over bits 31..30 from that table,
8827 as required for BIST support.
8830 @subsection XScale specific commands
8833 Some notes about the debug implementation on the XScale CPUs:
8835 The XScale CPU provides a special debug-only mini-instruction cache
8836 (mini-IC) in which exception vectors and target-resident debug handler
8837 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
8838 must point vector 0 (the reset vector) to the entry of the debug
8839 handler. However, this means that the complete first cacheline in the
8840 mini-IC is marked valid, which makes the CPU fetch all exception
8841 handlers from the mini-IC, ignoring the code in RAM.
8843 To address this situation, OpenOCD provides the @code{xscale
8844 vector_table} command, which allows the user to explicitly write
8845 individual entries to either the high or low vector table stored in
8848 It is recommended to place a pc-relative indirect branch in the vector
8849 table, and put the branch destination somewhere in memory. Doing so
8850 makes sure the code in the vector table stays constant regardless of
8851 code layout in memory:
8854 ldr pc,[pc,#0x100-8]
8855 ldr pc,[pc,#0x100-8]
8856 ldr pc,[pc,#0x100-8]
8857 ldr pc,[pc,#0x100-8]
8858 ldr pc,[pc,#0x100-8]
8859 ldr pc,[pc,#0x100-8]
8860 ldr pc,[pc,#0x100-8]
8861 ldr pc,[pc,#0x100-8]
8863 .long real_reset_vector
8864 .long real_ui_handler
8865 .long real_swi_handler
8867 .long real_data_abort
8868 .long 0 /* unused */
8869 .long real_irq_handler
8870 .long real_fiq_handler
8873 Alternatively, you may choose to keep some or all of the mini-IC
8874 vector table entries synced with those written to memory by your
8875 system software. The mini-IC can not be modified while the processor
8876 is executing, but for each vector table entry not previously defined
8877 using the @code{xscale vector_table} command, OpenOCD will copy the
8878 value from memory to the mini-IC every time execution resumes from a
8879 halt. This is done for both high and low vector tables (although the
8880 table not in use may not be mapped to valid memory, and in this case
8881 that copy operation will silently fail). This means that you will
8882 need to briefly halt execution at some strategic point during system
8883 start-up; e.g., after the software has initialized the vector table,
8884 but before exceptions are enabled. A breakpoint can be used to
8885 accomplish this once the appropriate location in the start-up code has
8886 been identified. A watchpoint over the vector table region is helpful
8887 in finding the location if you're not sure. Note that the same
8888 situation exists any time the vector table is modified by the system
8891 The debug handler must be placed somewhere in the address space using
8892 the @code{xscale debug_handler} command. The allowed locations for the
8893 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
8894 0xfffff800). The default value is 0xfe000800.
8896 XScale has resources to support two hardware breakpoints and two
8897 watchpoints. However, the following restrictions on watchpoint
8898 functionality apply: (1) the value and mask arguments to the @code{wp}
8899 command are not supported, (2) the watchpoint length must be a
8900 power of two and not less than four, and can not be greater than the
8901 watchpoint address, and (3) a watchpoint with a length greater than
8902 four consumes all the watchpoint hardware resources. This means that
8903 at any one time, you can have enabled either two watchpoints with a
8904 length of four, or one watchpoint with a length greater than four.
8906 These commands are available to XScale based CPUs,
8907 which are implementations of the ARMv5TE architecture.
8909 @deffn Command {xscale analyze_trace}
8910 Displays the contents of the trace buffer.
8913 @deffn Command {xscale cache_clean_address} address
8914 Changes the address used when cleaning the data cache.
8917 @deffn Command {xscale cache_info}
8918 Displays information about the CPU caches.
8921 @deffn Command {xscale cp15} regnum [value]
8922 Display cp15 register @var{regnum};
8923 else if a @var{value} is provided, that value is written to that register.
8926 @deffn Command {xscale debug_handler} target address
8927 Changes the address used for the specified target's debug handler.
8930 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
8931 Enables or disable the CPU's data cache.
8934 @deffn Command {xscale dump_trace} filename
8935 Dumps the raw contents of the trace buffer to @file{filename}.
8938 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
8939 Enables or disable the CPU's instruction cache.
8942 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
8943 Enables or disable the CPU's memory management unit.
8946 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
8947 Displays the trace buffer status, after optionally
8948 enabling or disabling the trace buffer
8949 and modifying how it is emptied.
8952 @deffn Command {xscale trace_image} filename [offset [type]]
8953 Opens a trace image from @file{filename}, optionally rebasing
8954 its segment addresses by @var{offset}.
8955 The image @var{type} may be one of
8956 @option{bin} (binary), @option{ihex} (Intel hex),
8957 @option{elf} (ELF file), @option{s19} (Motorola s19),
8958 @option{mem}, or @option{builder}.
8961 @anchor{xscalevectorcatch}
8962 @deffn Command {xscale vector_catch} [mask]
8963 @cindex vector_catch
8964 Display a bitmask showing the hardware vectors to catch.
8965 If the optional parameter is provided, first set the bitmask to that value.
8967 The mask bits correspond with bit 16..23 in the DCSR:
8970 0x02 Trap Undefined Instructions
8971 0x04 Trap Software Interrupt
8972 0x08 Trap Prefetch Abort
8973 0x10 Trap Data Abort
8980 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
8981 @cindex vector_table
8983 Set an entry in the mini-IC vector table. There are two tables: one for
8984 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
8985 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
8986 points to the debug handler entry and can not be overwritten.
8987 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
8989 Without arguments, the current settings are displayed.
8993 @section ARMv6 Architecture
8996 @subsection ARM11 specific commands
8999 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
9000 Displays the value of the memwrite burst-enable flag,
9001 which is enabled by default.
9002 If a boolean parameter is provided, first assigns that flag.
9003 Burst writes are only used for memory writes larger than 1 word.
9004 They improve performance by assuming that the CPU has read each data
9005 word over JTAG and completed its write before the next word arrives,
9006 instead of polling for a status flag to verify that completion.
9007 This is usually safe, because JTAG runs much slower than the CPU.
9010 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
9011 Displays the value of the memwrite error_fatal flag,
9012 which is enabled by default.
9013 If a boolean parameter is provided, first assigns that flag.
9014 When set, certain memory write errors cause earlier transfer termination.
9017 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
9018 Displays the value of the flag controlling whether
9019 IRQs are enabled during single stepping;
9020 they are disabled by default.
9021 If a boolean parameter is provided, first assigns that.
9024 @deffn Command {arm11 vcr} [value]
9025 @cindex vector_catch
9026 Displays the value of the @emph{Vector Catch Register (VCR)},
9027 coprocessor 14 register 7.
9028 If @var{value} is defined, first assigns that.
9030 Vector Catch hardware provides dedicated breakpoints
9031 for certain hardware events.
9032 The specific bit values are core-specific (as in fact is using
9033 coprocessor 14 register 7 itself) but all current ARM11
9034 cores @emph{except the ARM1176} use the same six bits.
9037 @section ARMv7 and ARMv8 Architecture
9041 @subsection ARMv7-A specific commands
9044 @deffn Command {cortex_a cache_info}
9045 display information about target caches
9048 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
9049 Work around issues with software breakpoints when the program text is
9050 mapped read-only by the operating system. This option sets the CP15 DACR
9051 to "all-manager" to bypass MMU permission checks on memory access.
9055 @deffn Command {cortex_a dbginit}
9056 Initialize core debug
9057 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9060 @deffn Command {cortex_a smp} [on|off]
9061 Display/set the current SMP mode
9064 @deffn Command {cortex_a smp_gdb} [core_id]
9065 Display/set the current core displayed in GDB
9068 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
9069 Selects whether interrupts will be processed when single stepping
9072 @deffn Command {cache_config l2x} [base way]
9076 @deffn Command {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
9077 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
9078 memory location @var{address}. When dumping the table from @var{address}, print at most
9079 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
9080 possible (4096) entries are printed.
9083 @subsection ARMv7-R specific commands
9086 @deffn Command {cortex_r dbginit}
9087 Initialize core debug
9088 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9091 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
9092 Selects whether interrupts will be processed when single stepping
9096 @subsection ARMv7-M specific commands
9104 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
9105 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
9106 @var{TRACECLKIN_freq} [@var{trace_freq}]))
9108 ARMv7-M architecture provides several modules to generate debugging
9109 information internally (ITM, DWT and ETM). Their output is directed
9110 through TPIU to be captured externally either on an SWO pin (this
9111 configuration is called SWV) or on a synchronous parallel trace port.
9113 This command configures the TPIU module of the target and, if internal
9114 capture mode is selected, starts to capture trace output by using the
9115 debugger adapter features.
9117 Some targets require additional actions to be performed in the
9118 @b{trace-config} handler for trace port to be activated.
9122 @item @option{disable} disable TPIU handling;
9123 @item @option{external} configure TPIU to let user capture trace
9124 output externally (with an additional UART or logic analyzer hardware);
9125 @item @option{internal @var{filename}} configure TPIU and debug adapter to
9126 gather trace data and append it to @var{filename} (which can be
9127 either a regular file or a named pipe);
9128 @item @option{internal -} configure TPIU and debug adapter to
9129 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
9130 @item @option{sync @var{port_width}} use synchronous parallel trace output
9131 mode, and set port width to @var{port_width};
9132 @item @option{manchester} use asynchronous SWO mode with Manchester
9134 @item @option{uart} use asynchronous SWO mode with NRZ (same as
9135 regular UART 8N1) coding;
9136 @item @var{formatter_enable} is @option{on} or @option{off} to enable
9137 or disable TPIU formatter which needs to be used when both ITM and ETM
9138 data is to be output via SWO;
9139 @item @var{TRACECLKIN_freq} this should be specified to match target's
9140 current TRACECLKIN frequency (usually the same as HCLK);
9141 @item @var{trace_freq} trace port frequency. Can be omitted in
9142 internal mode to let the adapter driver select the maximum supported
9148 @item STM32L152 board is programmed with an application that configures
9149 PLL to provide core clock with 24MHz frequency; to use ITM output it's
9152 #include <libopencm3/cm3/itm.h>
9157 (the most obvious way is to use the first stimulus port for printf,
9158 for that this ITM_STIM8 assignment can be used inside _write(); to make it
9159 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
9160 ITM_STIM_FIFOREADY));});
9161 @item An FT2232H UART is connected to the SWO pin of the board;
9162 @item Commands to configure UART for 12MHz baud rate:
9164 $ setserial /dev/ttyUSB1 spd_cust divisor 5
9165 $ stty -F /dev/ttyUSB1 38400
9167 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
9168 baud with our custom divisor to get 12MHz)
9169 @item @code{itmdump -f /dev/ttyUSB1 -d1}
9170 @item OpenOCD invocation line:
9172 openocd -f interface/stlink.cfg \
9173 -c "transport select hla_swd" \
9174 -f target/stm32l1.cfg \
9175 -c "tpiu config external uart off 24000000 12000000"
9180 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
9181 Enable or disable trace output for ITM stimulus @var{port} (counting
9182 from 0). Port 0 is enabled on target creation automatically.
9185 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
9186 Enable or disable trace output for all ITM stimulus ports.
9189 @subsection Cortex-M specific commands
9192 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
9193 Control masking (disabling) interrupts during target step/resume.
9195 The @option{auto} option handles interrupts during stepping in a way that they
9196 get served but don't disturb the program flow. The step command first allows
9197 pending interrupt handlers to execute, then disables interrupts and steps over
9198 the next instruction where the core was halted. After the step interrupts
9199 are enabled again. If the interrupt handlers don't complete within 500ms,
9200 the step command leaves with the core running.
9202 The @option{steponly} option disables interrupts during single-stepping but
9203 enables them during normal execution. This can be used as a partial workaround
9204 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
9205 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
9207 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
9208 option. If no breakpoint is available at the time of the step, then the step
9209 is taken with interrupts enabled, i.e. the same way the @option{off} option
9212 Default is @option{auto}.
9215 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
9216 @cindex vector_catch
9217 Vector Catch hardware provides dedicated breakpoints
9218 for certain hardware events.
9220 Parameters request interception of
9221 @option{all} of these hardware event vectors,
9222 @option{none} of them,
9223 or one or more of the following:
9224 @option{hard_err} for a HardFault exception;
9225 @option{mm_err} for a MemManage exception;
9226 @option{bus_err} for a BusFault exception;
9229 @option{chk_err}, or
9230 @option{nocp_err} for various UsageFault exceptions; or
9232 If NVIC setup code does not enable them,
9233 MemManage, BusFault, and UsageFault exceptions
9234 are mapped to HardFault.
9235 UsageFault checks for
9236 divide-by-zero and unaligned access
9237 must also be explicitly enabled.
9239 This finishes by listing the current vector catch configuration.
9242 @deffn Command {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
9243 Control reset handling if hardware srst is not fitted
9244 @xref{reset_config,,reset_config}.
9247 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
9248 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
9251 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
9252 This however has the disadvantage of only resetting the core, all peripherals
9253 are unaffected. A solution would be to use a @code{reset-init} event handler
9254 to manually reset the peripherals.
9255 @xref{targetevents,,Target Events}.
9257 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
9261 @subsection ARMv8-A specific commands
9265 @deffn Command {aarch64 cache_info}
9266 Display information about target caches
9269 @deffn Command {aarch64 dbginit}
9270 This command enables debugging by clearing the OS Lock and sticky power-down and reset
9271 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
9272 target code relies on. In a configuration file, the command would typically be called from a
9273 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
9274 However, normally it is not necessary to use the command at all.
9277 @deffn Command {aarch64 smp} [on|off]
9278 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
9279 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
9280 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
9281 group. With SMP handling disabled, all targets need to be treated individually.
9284 @deffn Command {aarch64 maskisr} [@option{on}|@option{off}]
9285 Selects whether interrupts will be processed when single stepping. The default configuration is
9289 @deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
9290 Cause @command{$target_name} to halt when an exception is taken. Any combination of
9291 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
9292 @command{$target_name} will halt before taking the exception. In order to resume
9293 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
9294 Issuing the command without options prints the current configuration.
9297 @section EnSilica eSi-RISC Architecture
9299 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
9300 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
9302 @subsection eSi-RISC Configuration
9304 @deffn Command {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
9305 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
9306 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
9309 @deffn Command {esirisc hwdc} (@option{all}|@option{none}|mask ...)
9310 Configure hardware debug control. The HWDC register controls which exceptions return
9311 control back to the debugger. Possible masks are @option{all}, @option{none},
9312 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
9313 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
9316 @subsection eSi-RISC Operation
9318 @deffn Command {esirisc flush_caches}
9319 Flush instruction and data caches. This command requires that the target is halted
9320 when the command is issued and configured with an instruction or data cache.
9323 @subsection eSi-Trace Configuration
9325 eSi-RISC targets may be configured with support for instruction tracing. Trace
9326 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
9327 is typically employed to move trace data off-device using a high-speed
9328 peripheral (eg. SPI). Collected trace data is encoded in one of three different
9329 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
9330 fifo} must be issued along with @command{esirisc trace format} before trace data
9333 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
9334 needed, collected trace data can be dumped to a file and processed by external
9338 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
9339 for this issue is to configure DMA to copy trace data to an in-memory buffer,
9340 which can then be passed to the @command{esirisc trace analyze} and
9341 @command{esirisc trace dump} commands.
9343 It is possible to corrupt trace data when using a FIFO if the peripheral
9344 responsible for draining data from the FIFO is not fast enough. This can be
9345 managed by enabling flow control, however this can impact timing-sensitive
9346 software operation on the CPU.
9349 @deffn Command {esirisc trace buffer} address size [@option{wrap}]
9350 Configure trace buffer using the provided address and size. If the @option{wrap}
9351 option is specified, trace collection will continue once the end of the buffer
9352 is reached. By default, wrap is disabled.
9355 @deffn Command {esirisc trace fifo} address
9356 Configure trace FIFO using the provided address.
9359 @deffn Command {esirisc trace flow_control} (@option{enable}|@option{disable})
9360 Enable or disable stalling the CPU to collect trace data. By default, flow
9361 control is disabled.
9364 @deffn Command {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
9365 Configure trace format and number of PC bits to be captured. @option{pc_bits}
9366 must be within 1 and 31 as the LSB is not collected. If external tooling is used
9367 to analyze collected trace data, these values must match.
9369 Supported trace formats:
9371 @item @option{full} capture full trace data, allowing execution history and
9372 timing to be determined.
9373 @item @option{branch} capture taken branch instructions and branch target
9375 @item @option{icache} capture instruction cache misses.
9379 @deffn Command {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
9380 Configure trigger start condition using the provided start data and mask. A
9381 brief description of each condition is provided below; for more detail on how
9382 these values are used, see the eSi-RISC Architecture Manual.
9384 Supported conditions:
9386 @item @option{none} manual tracing (see @command{esirisc trace start}).
9387 @item @option{pc} start tracing if the PC matches start data and mask.
9388 @item @option{load} start tracing if the effective address of a load
9389 instruction matches start data and mask.
9390 @item @option{store} start tracing if the effective address of a store
9391 instruction matches start data and mask.
9392 @item @option{exception} start tracing if the EID of an exception matches start
9394 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
9395 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
9396 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
9397 @item @option{high} start tracing when an external signal is a logical high.
9398 @item @option{low} start tracing when an external signal is a logical low.
9402 @deffn Command {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
9403 Configure trigger stop condition using the provided stop data and mask. A brief
9404 description of each condition is provided below; for more detail on how these
9405 values are used, see the eSi-RISC Architecture Manual.
9407 Supported conditions:
9409 @item @option{none} manual tracing (see @command{esirisc trace stop}).
9410 @item @option{pc} stop tracing if the PC matches stop data and mask.
9411 @item @option{load} stop tracing if the effective address of a load
9412 instruction matches stop data and mask.
9413 @item @option{store} stop tracing if the effective address of a store
9414 instruction matches stop data and mask.
9415 @item @option{exception} stop tracing if the EID of an exception matches stop
9417 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
9418 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
9419 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
9423 @deffn Command {esirisc trace trigger delay} (@option{trigger}) [cycles]
9424 Configure trigger start/stop delay in clock cycles.
9428 @item @option{none} no delay to start or stop collection.
9429 @item @option{start} delay @option{cycles} after trigger to start collection.
9430 @item @option{stop} delay @option{cycles} after trigger to stop collection.
9431 @item @option{both} delay @option{cycles} after both triggers to start or stop
9436 @subsection eSi-Trace Operation
9438 @deffn Command {esirisc trace init}
9439 Initialize trace collection. This command must be called any time the
9440 configuration changes. If a trace buffer has been configured, the contents will
9441 be overwritten when trace collection starts.
9444 @deffn Command {esirisc trace info}
9445 Display trace configuration.
9448 @deffn Command {esirisc trace status}
9449 Display trace collection status.
9452 @deffn Command {esirisc trace start}
9453 Start manual trace collection.
9456 @deffn Command {esirisc trace stop}
9457 Stop manual trace collection.
9460 @deffn Command {esirisc trace analyze} [address size]
9461 Analyze collected trace data. This command may only be used if a trace buffer
9462 has been configured. If a trace FIFO has been configured, trace data must be
9463 copied to an in-memory buffer identified by the @option{address} and
9464 @option{size} options using DMA.
9467 @deffn Command {esirisc trace dump} [address size] @file{filename}
9468 Dump collected trace data to file. This command may only be used if a trace
9469 buffer has been configured. If a trace FIFO has been configured, trace data must
9470 be copied to an in-memory buffer identified by the @option{address} and
9471 @option{size} options using DMA.
9474 @section Intel Architecture
9476 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
9477 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
9478 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
9479 software debug and the CLTAP is used for SoC level operations.
9480 Useful docs are here: https://communities.intel.com/community/makers/documentation
9482 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
9483 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
9484 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
9487 @subsection x86 32-bit specific commands
9488 The three main address spaces for x86 are memory, I/O and configuration space.
9489 These commands allow a user to read and write to the 64Kbyte I/O address space.
9491 @deffn Command {x86_32 idw} address
9492 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
9495 @deffn Command {x86_32 idh} address
9496 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
9499 @deffn Command {x86_32 idb} address
9500 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
9503 @deffn Command {x86_32 iww} address
9504 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
9507 @deffn Command {x86_32 iwh} address
9508 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
9511 @deffn Command {x86_32 iwb} address
9512 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
9515 @section OpenRISC Architecture
9517 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
9518 configured with any of the TAP / Debug Unit available.
9520 @subsection TAP and Debug Unit selection commands
9521 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
9522 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
9524 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
9525 Select between the Advanced Debug Interface and the classic one.
9527 An option can be passed as a second argument to the debug unit.
9529 When using the Advanced Debug Interface, option = 1 means the RTL core is
9530 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
9531 between bytes while doing read or write bursts.
9534 @subsection Registers commands
9535 @deffn Command {addreg} [name] [address] [feature] [reg_group]
9536 Add a new register in the cpu register list. This register will be
9537 included in the generated target descriptor file.
9539 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
9541 @strong{[reg_group]} can be anything. The default register list defines "system",
9542 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
9547 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
9552 @deffn Command {readgroup} (@option{group})
9553 Display all registers in @emph{group}.
9555 @emph{group} can be "system",
9556 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
9557 "timer" or any new group created with addreg command.
9560 @section RISC-V Architecture
9562 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
9563 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
9564 harts. (It's possible to increase this limit to 1024 by changing
9565 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
9566 Debug Specification, but there is also support for legacy targets that
9567 implement version 0.11.
9569 @subsection RISC-V Terminology
9571 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
9572 another hart, or may be a separate core. RISC-V treats those the same, and
9573 OpenOCD exposes each hart as a separate core.
9575 @subsection RISC-V Debug Configuration Commands
9577 @deffn Command {riscv expose_csrs} n0[-m0][,n1[-m1]]...
9578 Configure a list of inclusive ranges for CSRs to expose in addition to the
9579 standard ones. This must be executed before `init`.
9581 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
9582 and then only if the corresponding extension appears to be implemented. This
9583 command can be used if OpenOCD gets this wrong, or a target implements custom
9587 @deffn Command {riscv expose_custom} n0[-m0][,n1[-m1]]...
9588 The RISC-V Debug Specification allows targets to expose custom registers
9589 through abstract commands. (See Section 3.5.1.1 in that document.) This command
9590 configures a list of inclusive ranges of those registers to expose. Number 0
9591 indicates the first custom register, whose abstract command number is 0xc000.
9592 This command must be executed before `init`.
9595 @deffn Command {riscv set_command_timeout_sec} [seconds]
9596 Set the wall-clock timeout (in seconds) for individual commands. The default
9597 should work fine for all but the slowest targets (eg. simulators).
9600 @deffn Command {riscv set_reset_timeout_sec} [seconds]
9601 Set the maximum time to wait for a hart to come out of reset after reset is
9605 @deffn Command {riscv set_scratch_ram} none|[address]
9606 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
9607 This is used to access 64-bit floating point registers on 32-bit targets.
9610 @deffn Command {riscv set_prefer_sba} on|off
9611 When on, prefer to use System Bus Access to access memory. When off, prefer to
9612 use the Program Buffer to access memory.
9615 @deffn Command {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
9616 Set the IR value for the specified JTAG register. This is useful, for
9617 example, when using the existing JTAG interface on a Xilinx FPGA by
9618 way of BSCANE2 primitives that only permit a limited selection of IR
9621 When utilizing version 0.11 of the RISC-V Debug Specification,
9622 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
9623 and DBUS registers, respectively.
9626 @subsection RISC-V Authentication Commands
9628 The following commands can be used to authenticate to a RISC-V system. Eg. a
9629 trivial challenge-response protocol could be implemented as follows in a
9630 configuration file, immediately following @command{init}:
9632 set challenge [riscv authdata_read]
9633 riscv authdata_write [expr $challenge + 1]
9636 @deffn Command {riscv authdata_read}
9637 Return the 32-bit value read from authdata.
9640 @deffn Command {riscv authdata_write} value
9641 Write the 32-bit value to authdata.
9644 @subsection RISC-V DMI Commands
9646 The following commands allow direct access to the Debug Module Interface, which
9647 can be used to interact with custom debug features.
9649 @deffn Command {riscv dmi_read}
9650 Perform a 32-bit DMI read at address, returning the value.
9653 @deffn Command {riscv dmi_write} address value
9654 Perform a 32-bit DMI write of value at address.
9657 @anchor{softwaredebugmessagesandtracing}
9658 @section Software Debug Messages and Tracing
9659 @cindex Linux-ARM DCC support
9663 OpenOCD can process certain requests from target software, when
9664 the target uses appropriate libraries.
9665 The most powerful mechanism is semihosting, but there is also
9666 a lighter weight mechanism using only the DCC channel.
9668 Currently @command{target_request debugmsgs}
9669 is supported only for @option{arm7_9} and @option{cortex_m} cores.
9670 These messages are received as part of target polling, so
9671 you need to have @command{poll on} active to receive them.
9672 They are intrusive in that they will affect program execution
9673 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
9675 See @file{libdcc} in the contrib dir for more details.
9676 In addition to sending strings, characters, and
9677 arrays of various size integers from the target,
9678 @file{libdcc} also exports a software trace point mechanism.
9679 The target being debugged may
9680 issue trace messages which include a 24-bit @dfn{trace point} number.
9681 Trace point support includes two distinct mechanisms,
9682 each supported by a command:
9685 @item @emph{History} ... A circular buffer of trace points
9686 can be set up, and then displayed at any time.
9687 This tracks where code has been, which can be invaluable in
9688 finding out how some fault was triggered.
9690 The buffer may overflow, since it collects records continuously.
9691 It may be useful to use some of the 24 bits to represent a
9692 particular event, and other bits to hold data.
9694 @item @emph{Counting} ... An array of counters can be set up,
9695 and then displayed at any time.
9696 This can help establish code coverage and identify hot spots.
9698 The array of counters is directly indexed by the trace point
9699 number, so trace points with higher numbers are not counted.
9702 Linux-ARM kernels have a ``Kernel low-level debugging
9703 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
9704 depends on CONFIG_DEBUG_LL) which uses this mechanism to
9705 deliver messages before a serial console can be activated.
9706 This is not the same format used by @file{libdcc}.
9707 Other software, such as the U-Boot boot loader, sometimes
9708 does the same thing.
9710 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
9711 Displays current handling of target DCC message requests.
9712 These messages may be sent to the debugger while the target is running.
9713 The optional @option{enable} and @option{charmsg} parameters
9714 both enable the messages, while @option{disable} disables them.
9716 With @option{charmsg} the DCC words each contain one character,
9717 as used by Linux with CONFIG_DEBUG_ICEDCC;
9718 otherwise the libdcc format is used.
9721 @deffn Command {trace history} [@option{clear}|count]
9722 With no parameter, displays all the trace points that have triggered
9723 in the order they triggered.
9724 With the parameter @option{clear}, erases all current trace history records.
9725 With a @var{count} parameter, allocates space for that many
9729 @deffn Command {trace point} [@option{clear}|identifier]
9730 With no parameter, displays all trace point identifiers and how many times
9731 they have been triggered.
9732 With the parameter @option{clear}, erases all current trace point counters.
9733 With a numeric @var{identifier} parameter, creates a new a trace point counter
9734 and associates it with that identifier.
9736 @emph{Important:} The identifier and the trace point number
9737 are not related except by this command.
9738 These trace point numbers always start at zero (from server startup,
9739 or after @command{trace point clear}) and count up from there.
9744 @chapter JTAG Commands
9745 @cindex JTAG Commands
9746 Most general purpose JTAG commands have been presented earlier.
9747 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
9748 Lower level JTAG commands, as presented here,
9749 may be needed to work with targets which require special
9750 attention during operations such as reset or initialization.
9752 To use these commands you will need to understand some
9753 of the basics of JTAG, including:
9756 @item A JTAG scan chain consists of a sequence of individual TAP
9757 devices such as a CPUs.
9758 @item Control operations involve moving each TAP through the same
9759 standard state machine (in parallel)
9760 using their shared TMS and clock signals.
9761 @item Data transfer involves shifting data through the chain of
9762 instruction or data registers of each TAP, writing new register values
9763 while the reading previous ones.
9764 @item Data register sizes are a function of the instruction active in
9765 a given TAP, while instruction register sizes are fixed for each TAP.
9766 All TAPs support a BYPASS instruction with a single bit data register.
9767 @item The way OpenOCD differentiates between TAP devices is by
9768 shifting different instructions into (and out of) their instruction
9772 @section Low Level JTAG Commands
9774 These commands are used by developers who need to access
9775 JTAG instruction or data registers, possibly controlling
9776 the order of TAP state transitions.
9777 If you're not debugging OpenOCD internals, or bringing up a
9778 new JTAG adapter or a new type of TAP device (like a CPU or
9779 JTAG router), you probably won't need to use these commands.
9780 In a debug session that doesn't use JTAG for its transport protocol,
9781 these commands are not available.
9783 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
9784 Loads the data register of @var{tap} with a series of bit fields
9785 that specify the entire register.
9786 Each field is @var{numbits} bits long with
9787 a numeric @var{value} (hexadecimal encouraged).
9788 The return value holds the original value of each
9791 For example, a 38 bit number might be specified as one
9792 field of 32 bits then one of 6 bits.
9793 @emph{For portability, never pass fields which are more
9794 than 32 bits long. Many OpenOCD implementations do not
9795 support 64-bit (or larger) integer values.}
9797 All TAPs other than @var{tap} must be in BYPASS mode.
9798 The single bit in their data registers does not matter.
9800 When @var{tap_state} is specified, the JTAG state machine is left
9802 For example @sc{drpause} might be specified, so that more
9803 instructions can be issued before re-entering the @sc{run/idle} state.
9804 If the end state is not specified, the @sc{run/idle} state is entered.
9807 OpenOCD does not record information about data register lengths,
9808 so @emph{it is important that you get the bit field lengths right}.
9809 Remember that different JTAG instructions refer to different
9810 data registers, which may have different lengths.
9811 Moreover, those lengths may not be fixed;
9812 the SCAN_N instruction can change the length of
9813 the register accessed by the INTEST instruction
9814 (by connecting a different scan chain).
9818 @deffn Command {flush_count}
9819 Returns the number of times the JTAG queue has been flushed.
9820 This may be used for performance tuning.
9822 For example, flushing a queue over USB involves a
9823 minimum latency, often several milliseconds, which does
9824 not change with the amount of data which is written.
9825 You may be able to identify performance problems by finding
9826 tasks which waste bandwidth by flushing small transfers too often,
9827 instead of batching them into larger operations.
9830 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
9831 For each @var{tap} listed, loads the instruction register
9832 with its associated numeric @var{instruction}.
9833 (The number of bits in that instruction may be displayed
9834 using the @command{scan_chain} command.)
9835 For other TAPs, a BYPASS instruction is loaded.
9837 When @var{tap_state} is specified, the JTAG state machine is left
9839 For example @sc{irpause} might be specified, so the data register
9840 can be loaded before re-entering the @sc{run/idle} state.
9841 If the end state is not specified, the @sc{run/idle} state is entered.
9844 OpenOCD currently supports only a single field for instruction
9845 register values, unlike data register values.
9846 For TAPs where the instruction register length is more than 32 bits,
9847 portable scripts currently must issue only BYPASS instructions.
9851 @deffn Command {pathmove} start_state [next_state ...]
9852 Start by moving to @var{start_state}, which
9853 must be one of the @emph{stable} states.
9854 Unless it is the only state given, this will often be the
9855 current state, so that no TCK transitions are needed.
9856 Then, in a series of single state transitions
9857 (conforming to the JTAG state machine) shift to
9858 each @var{next_state} in sequence, one per TCK cycle.
9859 The final state must also be stable.
9862 @deffn Command {runtest} @var{num_cycles}
9863 Move to the @sc{run/idle} state, and execute at least
9864 @var{num_cycles} of the JTAG clock (TCK).
9865 Instructions often need some time
9866 to execute before they take effect.
9869 @c tms_sequence (short|long)
9870 @c ... temporary, debug-only, other than USBprog bug workaround...
9872 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
9873 Verify values captured during @sc{ircapture} and returned
9874 during IR scans. Default is enabled, but this can be
9875 overridden by @command{verify_jtag}.
9876 This flag is ignored when validating JTAG chain configuration.
9879 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
9880 Enables verification of DR and IR scans, to help detect
9881 programming errors. For IR scans, @command{verify_ircapture}
9882 must also be enabled.
9886 @section TAP state names
9887 @cindex TAP state names
9889 The @var{tap_state} names used by OpenOCD in the @command{drscan},
9890 @command{irscan}, and @command{pathmove} commands are the same
9891 as those used in SVF boundary scan documents, except that
9892 SVF uses @sc{idle} instead of @sc{run/idle}.
9895 @item @b{RESET} ... @emph{stable} (with TMS high);
9896 acts as if TRST were pulsed
9897 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
9900 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
9901 through the data register
9903 @item @b{DRPAUSE} ... @emph{stable}; data register ready
9904 for update or more shifting
9909 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
9910 through the instruction register
9912 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
9913 for update or more shifting
9918 Note that only six of those states are fully ``stable'' in the
9919 face of TMS fixed (low except for @sc{reset})
9920 and a free-running JTAG clock. For all the
9921 others, the next TCK transition changes to a new state.
9924 @item From @sc{drshift} and @sc{irshift}, clock transitions will
9925 produce side effects by changing register contents. The values
9926 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
9927 may not be as expected.
9928 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
9929 choices after @command{drscan} or @command{irscan} commands,
9930 since they are free of JTAG side effects.
9931 @item @sc{run/idle} may have side effects that appear at non-JTAG
9932 levels, such as advancing the ARM9E-S instruction pipeline.
9933 Consult the documentation for the TAP(s) you are working with.
9936 @node Boundary Scan Commands
9937 @chapter Boundary Scan Commands
9939 One of the original purposes of JTAG was to support
9940 boundary scan based hardware testing.
9941 Although its primary focus is to support On-Chip Debugging,
9942 OpenOCD also includes some boundary scan commands.
9944 @section SVF: Serial Vector Format
9945 @cindex Serial Vector Format
9948 The Serial Vector Format, better known as @dfn{SVF}, is a
9949 way to represent JTAG test patterns in text files.
9950 In a debug session using JTAG for its transport protocol,
9951 OpenOCD supports running such test files.
9953 @deffn Command {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
9954 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
9955 This issues a JTAG reset (Test-Logic-Reset) and then
9956 runs the SVF script from @file{filename}.
9958 Arguments can be specified in any order; the optional dash doesn't
9959 affect their semantics.
9963 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
9964 specified by the SVF file with HIR, TIR, HDR and TDR commands;
9965 instead, calculate them automatically according to the current JTAG
9966 chain configuration, targeting @var{tapname};
9967 @item @option{[-]quiet} do not log every command before execution;
9968 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
9969 on the real interface;
9970 @item @option{[-]progress} enable progress indication;
9971 @item @option{[-]ignore_error} continue execution despite TDO check
9976 @section XSVF: Xilinx Serial Vector Format
9977 @cindex Xilinx Serial Vector Format
9980 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
9981 binary representation of SVF which is optimized for use with
9983 In a debug session using JTAG for its transport protocol,
9984 OpenOCD supports running such test files.
9986 @quotation Important
9987 Not all XSVF commands are supported.
9990 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
9991 This issues a JTAG reset (Test-Logic-Reset) and then
9992 runs the XSVF script from @file{filename}.
9993 When a @var{tapname} is specified, the commands are directed at
9995 When @option{virt2} is specified, the @sc{xruntest} command counts
9996 are interpreted as TCK cycles instead of microseconds.
9997 Unless the @option{quiet} option is specified,
9998 messages are logged for comments and some retries.
10001 The OpenOCD sources also include two utility scripts
10002 for working with XSVF; they are not currently installed
10003 after building the software.
10004 You may find them useful:
10007 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
10008 syntax understood by the @command{xsvf} command; see notes below.
10009 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
10010 understands the OpenOCD extensions.
10013 The input format accepts a handful of non-standard extensions.
10014 These include three opcodes corresponding to SVF extensions
10015 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
10016 two opcodes supporting a more accurate translation of SVF
10017 (XTRST, XWAITSTATE).
10018 If @emph{xsvfdump} shows a file is using those opcodes, it
10019 probably will not be usable with other XSVF tools.
10022 @node Utility Commands
10023 @chapter Utility Commands
10024 @cindex Utility Commands
10026 @section RAM testing
10027 @cindex RAM testing
10029 There is often a need to stress-test random access memory (RAM) for
10030 errors. OpenOCD comes with a Tcl implementation of well-known memory
10031 testing procedures allowing the detection of all sorts of issues with
10032 electrical wiring, defective chips, PCB layout and other common
10035 To use them, you usually need to initialise your RAM controller first;
10036 consult your SoC's documentation to get the recommended list of
10037 register operations and translate them to the corresponding
10038 @command{mww}/@command{mwb} commands.
10040 Load the memory testing functions with
10043 source [find tools/memtest.tcl]
10046 to get access to the following facilities:
10048 @deffn Command {memTestDataBus} address
10049 Test the data bus wiring in a memory region by performing a walking
10050 1's test at a fixed address within that region.
10053 @deffn Command {memTestAddressBus} baseaddress size
10054 Perform a walking 1's test on the relevant bits of the address and
10055 check for aliasing. This test will find single-bit address failures
10056 such as stuck-high, stuck-low, and shorted pins.
10059 @deffn Command {memTestDevice} baseaddress size
10060 Test the integrity of a physical memory device by performing an
10061 increment/decrement test over the entire region. In the process every
10062 storage bit in the device is tested as zero and as one.
10065 @deffn Command {runAllMemTests} baseaddress size
10066 Run all of the above tests over a specified memory region.
10069 @section Firmware recovery helpers
10070 @cindex Firmware recovery
10072 OpenOCD includes an easy-to-use script to facilitate mass-market
10073 devices recovery with JTAG.
10075 For quickstart instructions run:
10077 openocd -f tools/firmware-recovery.tcl -c firmware_help
10083 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
10084 be used to access files on PCs (either the developer's PC or some other PC).
10086 The way this works on the ZY1000 is to prefix a filename by
10087 "/tftp/ip/" and append the TFTP path on the TFTP
10088 server (tftpd). For example,
10091 load_image /tftp/10.0.0.96/c:\temp\abc.elf
10094 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
10095 if the file was hosted on the embedded host.
10097 In order to achieve decent performance, you must choose a TFTP server
10098 that supports a packet size bigger than the default packet size (512 bytes). There
10099 are numerous TFTP servers out there (free and commercial) and you will have to do
10100 a bit of googling to find something that fits your requirements.
10102 @node GDB and OpenOCD
10103 @chapter GDB and OpenOCD
10105 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
10106 to debug remote targets.
10107 Setting up GDB to work with OpenOCD can involve several components:
10110 @item The OpenOCD server support for GDB may need to be configured.
10111 @xref{gdbconfiguration,,GDB Configuration}.
10112 @item GDB's support for OpenOCD may need configuration,
10113 as shown in this chapter.
10114 @item If you have a GUI environment like Eclipse,
10115 that also will probably need to be configured.
10118 Of course, the version of GDB you use will need to be one which has
10119 been built to know about the target CPU you're using. It's probably
10120 part of the tool chain you're using. For example, if you are doing
10121 cross-development for ARM on an x86 PC, instead of using the native
10122 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
10123 if that's the tool chain used to compile your code.
10125 @section Connecting to GDB
10126 @cindex Connecting to GDB
10127 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
10128 instance GDB 6.3 has a known bug that produces bogus memory access
10129 errors, which has since been fixed; see
10130 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
10132 OpenOCD can communicate with GDB in two ways:
10136 A socket (TCP/IP) connection is typically started as follows:
10138 target remote localhost:3333
10140 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
10142 It is also possible to use the GDB extended remote protocol as follows:
10144 target extended-remote localhost:3333
10147 A pipe connection is typically started as follows:
10149 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
10151 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
10152 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
10153 session. log_output sends the log output to a file to ensure that the pipe is
10154 not saturated when using higher debug level outputs.
10157 To list the available OpenOCD commands type @command{monitor help} on the
10160 @section Sample GDB session startup
10162 With the remote protocol, GDB sessions start a little differently
10163 than they do when you're debugging locally.
10164 Here's an example showing how to start a debug session with a
10166 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
10167 Most programs would be written into flash (address 0) and run from there.
10170 $ arm-none-eabi-gdb example.elf
10171 (gdb) target remote localhost:3333
10172 Remote debugging using localhost:3333
10174 (gdb) monitor reset halt
10177 Loading section .vectors, size 0x100 lma 0x20000000
10178 Loading section .text, size 0x5a0 lma 0x20000100
10179 Loading section .data, size 0x18 lma 0x200006a0
10180 Start address 0x2000061c, load size 1720
10181 Transfer rate: 22 KB/sec, 573 bytes/write.
10187 You could then interrupt the GDB session to make the program break,
10188 type @command{where} to show the stack, @command{list} to show the
10189 code around the program counter, @command{step} through code,
10190 set breakpoints or watchpoints, and so on.
10192 @section Configuring GDB for OpenOCD
10194 OpenOCD supports the gdb @option{qSupported} packet, this enables information
10195 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
10196 packet size and the device's memory map.
10197 You do not need to configure the packet size by hand,
10198 and the relevant parts of the memory map should be automatically
10199 set up when you declare (NOR) flash banks.
10201 However, there are other things which GDB can't currently query.
10202 You may need to set those up by hand.
10203 As OpenOCD starts up, you will often see a line reporting
10207 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
10210 You can pass that information to GDB with these commands:
10213 set remote hardware-breakpoint-limit 6
10214 set remote hardware-watchpoint-limit 4
10217 With that particular hardware (Cortex-M3) the hardware breakpoints
10218 only work for code running from flash memory. Most other ARM systems
10219 do not have such restrictions.
10221 Rather than typing such commands interactively, you may prefer to
10222 save them in a file and have GDB execute them as it starts, perhaps
10223 using a @file{.gdbinit} in your project directory or starting GDB
10224 using @command{gdb -x filename}.
10226 @section Programming using GDB
10227 @cindex Programming using GDB
10228 @anchor{programmingusinggdb}
10230 By default the target memory map is sent to GDB. This can be disabled by
10231 the following OpenOCD configuration option:
10233 gdb_memory_map disable
10235 For this to function correctly a valid flash configuration must also be set
10236 in OpenOCD. For faster performance you should also configure a valid
10239 Informing GDB of the memory map of the target will enable GDB to protect any
10240 flash areas of the target and use hardware breakpoints by default. This means
10241 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
10242 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
10244 To view the configured memory map in GDB, use the GDB command @option{info mem}.
10245 All other unassigned addresses within GDB are treated as RAM.
10247 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
10248 This can be changed to the old behaviour by using the following GDB command
10250 set mem inaccessible-by-default off
10253 If @command{gdb_flash_program enable} is also used, GDB will be able to
10254 program any flash memory using the vFlash interface.
10256 GDB will look at the target memory map when a load command is given, if any
10257 areas to be programmed lie within the target flash area the vFlash packets
10260 If the target needs configuring before GDB programming, set target
10261 event gdb-flash-erase-start:
10263 $_TARGETNAME configure -event gdb-flash-erase-start BODY
10265 @xref{targetevents,,Target Events}, for other GDB programming related events.
10267 To verify any flash programming the GDB command @option{compare-sections}
10270 @section Using GDB as a non-intrusive memory inspector
10271 @cindex Using GDB as a non-intrusive memory inspector
10272 @anchor{gdbmeminspect}
10274 If your project controls more than a blinking LED, let's say a heavy industrial
10275 robot or an experimental nuclear reactor, stopping the controlling process
10276 just because you want to attach GDB is not a good option.
10278 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
10279 Though there is a possible setup where the target does not get stopped
10280 and GDB treats it as it were running.
10281 If the target supports background access to memory while it is running,
10282 you can use GDB in this mode to inspect memory (mainly global variables)
10283 without any intrusion of the target process.
10285 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
10286 Place following command after target configuration:
10288 $_TARGETNAME configure -event gdb-attach @{@}
10291 If any of installed flash banks does not support probe on running target,
10292 switch off gdb_memory_map:
10294 gdb_memory_map disable
10297 Ensure GDB is configured without interrupt-on-connect.
10298 Some GDB versions set it by default, some does not.
10300 set remote interrupt-on-connect off
10303 If you switched gdb_memory_map off, you may want to setup GDB memory map
10304 manually or issue @command{set mem inaccessible-by-default off}
10306 Now you can issue GDB command @command{target remote ...} and inspect memory
10307 of a running target. Do not use GDB commands @command{continue},
10308 @command{step} or @command{next} as they synchronize GDB with your target
10309 and GDB would require stopping the target to get the prompt back.
10311 Do not use this mode under an IDE like Eclipse as it caches values of
10312 previously shown varibles.
10314 @section RTOS Support
10315 @cindex RTOS Support
10316 @anchor{gdbrtossupport}
10318 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
10319 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
10321 @xref{Threads, Debugging Programs with Multiple Threads,
10322 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
10325 @* An example setup is below:
10328 $_TARGETNAME configure -rtos auto
10331 This will attempt to auto detect the RTOS within your application.
10333 Currently supported rtos's include:
10335 @item @option{eCos}
10336 @item @option{ThreadX}
10337 @item @option{FreeRTOS}
10338 @item @option{linux}
10339 @item @option{ChibiOS}
10340 @item @option{embKernel}
10342 @item @option{uCOS-III}
10343 @item @option{nuttx}
10344 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
10347 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
10348 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
10352 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
10353 @item ThreadX symbols
10354 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
10355 @item FreeRTOS symbols
10356 @c The following is taken from recent texinfo to provide compatibility
10357 @c with ancient versions that do not support @raggedright
10360 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
10361 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
10362 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
10363 uxCurrentNumberOfTasks, uxTopUsedPriority.
10367 @item linux symbols
10369 @item ChibiOS symbols
10370 rlist, ch_debug, chSysInit.
10371 @item embKernel symbols
10372 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
10373 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
10375 _mqx_kernel_data, MQX_init_struct.
10376 @item uC/OS-III symbols
10377 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
10378 @item nuttx symbols
10379 g_readytorun, g_tasklisttable
10382 For most RTOS supported the above symbols will be exported by default. However for
10383 some, eg. FreeRTOS and uC/OS-III, extra steps must be taken.
10385 These RTOSes may require additional OpenOCD-specific file to be linked
10386 along with the project:
10390 contrib/rtos-helpers/FreeRTOS-openocd.c
10392 contrib/rtos-helpers/uCOS-III-openocd.c
10395 @anchor{usingopenocdsmpwithgdb}
10396 @section Using OpenOCD SMP with GDB
10400 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
10401 ("hardware threads") in an SMP system as threads to GDB. With this extension,
10402 GDB can be used to inspect the state of an SMP system in a natural way.
10403 After halting the system, using the GDB command @command{info threads} will
10404 list the context of each active CPU core in the system. GDB's @command{thread}
10405 command can be used to switch the view to a different CPU core.
10406 The @command{step} and @command{stepi} commands can be used to step a specific core
10407 while other cores are free-running or remain halted, depending on the
10408 scheduler-locking mode configured in GDB.
10410 @section Legacy SMP core switching support
10412 This method is deprecated in favor of the @emph{hwthread} pseudo RTOS.
10415 For SMP support following GDB serial protocol packet have been defined :
10417 @item j - smp status request
10418 @item J - smp set request
10421 OpenOCD implements :
10423 @item @option{jc} packet for reading core id displayed by
10424 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
10425 @option{E01} for target not smp.
10426 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
10427 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
10428 for target not smp or @option{OK} on success.
10431 Handling of this packet within GDB can be done :
10433 @item by the creation of an internal variable (i.e @option{_core}) by mean
10434 of function allocate_computed_value allowing following GDB command.
10437 #Jc01 packet is sent
10439 #jc packet is sent and result is affected in $
10442 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
10443 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
10446 # toggle0 : force display of coreid 0
10452 # toggle1 : force display of coreid 1
10461 @node Tcl Scripting API
10462 @chapter Tcl Scripting API
10463 @cindex Tcl Scripting API
10464 @cindex Tcl scripts
10467 Tcl commands are stateless; e.g. the @command{telnet} command has
10468 a concept of currently active target, the Tcl API proc's take this sort
10469 of state information as an argument to each proc.
10471 There are three main types of return values: single value, name value
10472 pair list and lists.
10474 Name value pair. The proc 'foo' below returns a name/value pair
10478 > set foo(me) Duane
10479 > set foo(you) Oyvind
10480 > set foo(mouse) Micky
10481 > set foo(duck) Donald
10493 me Duane you Oyvind mouse Micky duck Donald
10496 Thus, to get the names of the associative array is easy:
10499 foreach { name value } [set foo] {
10500 puts "Name: $name, Value: $value"
10504 Lists returned should be relatively small. Otherwise, a range
10505 should be passed in to the proc in question.
10507 @section Internal low-level Commands
10509 By "low-level," we mean commands that a human would typically not
10513 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
10515 Read memory and return as a Tcl array for script processing
10516 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
10518 Convert a Tcl array to memory locations and write the values
10519 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
10521 Return information about the flash banks
10523 @item @b{capture} <@var{command}>
10525 Run <@var{command}> and return full log output that was produced during
10526 its execution. Example:
10529 > capture "reset init"
10534 OpenOCD commands can consist of two words, e.g. "flash banks". The
10535 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
10536 called "flash_banks".
10538 @section OpenOCD specific Global Variables
10540 Real Tcl has ::tcl_platform(), and platform::identify, and many other
10541 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
10542 holds one of the following values:
10545 @item @b{cygwin} Running under Cygwin
10546 @item @b{darwin} Darwin (Mac-OS) is the underlying operating system.
10547 @item @b{freebsd} Running under FreeBSD
10548 @item @b{openbsd} Running under OpenBSD
10549 @item @b{netbsd} Running under NetBSD
10550 @item @b{linux} Linux is the underlying operating system
10551 @item @b{mingw32} Running under MingW32
10552 @item @b{winxx} Built using Microsoft Visual Studio
10553 @item @b{ecos} Running under eCos
10554 @item @b{other} Unknown, none of the above.
10557 Note: 'winxx' was chosen because today (March-2009) no distinction is made between Win32 and Win64.
10560 We should add support for a variable like Tcl variable
10561 @code{tcl_platform(platform)}, it should be called
10562 @code{jim_platform} (because it
10563 is jim, not real tcl).
10566 @section Tcl RPC server
10569 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
10570 commands and receive the results.
10572 To access it, your application needs to connect to a configured TCP port
10573 (see @command{tcl_port}). Then it can pass any string to the
10574 interpreter terminating it with @code{0x1a} and wait for the return
10575 value (it will be terminated with @code{0x1a} as well). This can be
10576 repeated as many times as desired without reopening the connection.
10578 It is not needed anymore to prefix the OpenOCD commands with
10579 @code{ocd_} to get the results back. But sometimes you might need the
10580 @command{capture} command.
10582 See @file{contrib/rpc_examples/} for specific client implementations.
10584 @section Tcl RPC server notifications
10585 @cindex RPC Notifications
10587 Notifications are sent asynchronously to other commands being executed over
10588 the RPC server, so the port must be polled continuously.
10590 Target event, state and reset notifications are emitted as Tcl associative arrays
10591 in the following format.
10594 type target_event event [event-name]
10595 type target_state state [state-name]
10596 type target_reset mode [reset-mode]
10599 @deffn {Command} tcl_notifications [on/off]
10600 Toggle output of target notifications to the current Tcl RPC server.
10601 Only available from the Tcl RPC server.
10606 @section Tcl RPC server trace output
10607 @cindex RPC trace output
10609 Trace data is sent asynchronously to other commands being executed over
10610 the RPC server, so the port must be polled continuously.
10612 Target trace data is emitted as a Tcl associative array in the following format.
10615 type target_trace data [trace-data-hex-encoded]
10618 @deffn {Command} tcl_trace [on/off]
10619 Toggle output of target trace data to the current Tcl RPC server.
10620 Only available from the Tcl RPC server.
10623 See an example application here:
10624 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
10633 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
10635 @cindex adaptive clocking
10638 In digital circuit design it is often referred to as ``clock
10639 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
10640 operating at some speed, your CPU target is operating at another.
10641 The two clocks are not synchronised, they are ``asynchronous''
10643 In order for the two to work together they must be synchronised
10644 well enough to work; JTAG can't go ten times faster than the CPU,
10645 for example. There are 2 basic options:
10648 Use a special "adaptive clocking" circuit to change the JTAG
10649 clock rate to match what the CPU currently supports.
10651 The JTAG clock must be fixed at some speed that's enough slower than
10652 the CPU clock that all TMS and TDI transitions can be detected.
10655 @b{Does this really matter?} For some chips and some situations, this
10656 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
10657 the CPU has no difficulty keeping up with JTAG.
10658 Startup sequences are often problematic though, as are other
10659 situations where the CPU clock rate changes (perhaps to save
10662 For example, Atmel AT91SAM chips start operation from reset with
10663 a 32kHz system clock. Boot firmware may activate the main oscillator
10664 and PLL before switching to a faster clock (perhaps that 500 MHz
10666 If you're using JTAG to debug that startup sequence, you must slow
10667 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
10668 JTAG can use a faster clock.
10670 Consider also debugging a 500MHz ARM926 hand held battery powered
10671 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
10672 clock, between keystrokes unless it has work to do. When would
10673 that 5 MHz JTAG clock be usable?
10675 @b{Solution #1 - A special circuit}
10677 In order to make use of this,
10678 your CPU, board, and JTAG adapter must all support the RTCK
10679 feature. Not all of them support this; keep reading!
10681 The RTCK ("Return TCK") signal in some ARM chips is used to help with
10682 this problem. ARM has a good description of the problem described at
10683 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
10684 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
10685 work? / how does adaptive clocking work?''.
10687 The nice thing about adaptive clocking is that ``battery powered hand
10688 held device example'' - the adaptiveness works perfectly all the
10689 time. One can set a break point or halt the system in the deep power
10690 down code, slow step out until the system speeds up.
10692 Note that adaptive clocking may also need to work at the board level,
10693 when a board-level scan chain has multiple chips.
10694 Parallel clock voting schemes are good way to implement this,
10695 both within and between chips, and can easily be implemented
10697 It's not difficult to have logic fan a module's input TCK signal out
10698 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
10699 back with the right polarity before changing the output RTCK signal.
10700 Texas Instruments makes some clock voting logic available
10701 for free (with no support) in VHDL form; see
10702 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
10704 @b{Solution #2 - Always works - but may be slower}
10706 Often this is a perfectly acceptable solution.
10708 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
10709 the target clock speed. But what that ``magic division'' is varies
10710 depending on the chips on your board.
10711 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
10712 ARM11 cores use an 8:1 division.
10713 @b{Xilinx rule of thumb} is 1/12 the clock speed.
10715 Note: most full speed FT2232 based JTAG adapters are limited to a
10716 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
10717 often support faster clock rates (and adaptive clocking).
10719 You can still debug the 'low power' situations - you just need to
10720 either use a fixed and very slow JTAG clock rate ... or else
10721 manually adjust the clock speed at every step. (Adjusting is painful
10722 and tedious, and is not always practical.)
10724 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
10725 have a special debug mode in your application that does a ``high power
10726 sleep''. If you are careful - 98% of your problems can be debugged
10729 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
10730 operation in your idle loops even if you don't otherwise change the CPU
10732 That operation gates the CPU clock, and thus the JTAG clock; which
10733 prevents JTAG access. One consequence is not being able to @command{halt}
10734 cores which are executing that @emph{wait for interrupt} operation.
10736 To set the JTAG frequency use the command:
10739 # Example: 1.234MHz
10744 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
10746 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
10747 around Windows filenames.
10760 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
10762 Make sure you have Cygwin installed, or at least a version of OpenOCD that
10763 claims to come with all the necessary DLLs. When using Cygwin, try launching
10764 OpenOCD from the Cygwin shell.
10766 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
10767 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
10768 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
10770 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
10771 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
10772 software breakpoints consume one of the two available hardware breakpoints.
10774 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
10776 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
10777 clock at the time you're programming the flash. If you've specified the crystal's
10778 frequency, make sure the PLL is disabled. If you've specified the full core speed
10779 (e.g. 60MHz), make sure the PLL is enabled.
10781 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
10782 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
10783 out while waiting for end of scan, rtck was disabled".
10785 Make sure your PC's parallel port operates in EPP mode. You might have to try several
10786 settings in your PC BIOS (ECP, EPP, and different versions of those).
10788 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
10789 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
10790 memory read caused data abort".
10792 The errors are non-fatal, and are the result of GDB trying to trace stack frames
10793 beyond the last valid frame. It might be possible to prevent this by setting up
10794 a proper "initial" stack frame, if you happen to know what exactly has to
10795 be done, feel free to add this here.
10797 @b{Simple:} In your startup code - push 8 registers of zeros onto the
10798 stack before calling main(). What GDB is doing is ``climbing'' the run
10799 time stack by reading various values on the stack using the standard
10800 call frame for the target. GDB keeps going - until one of 2 things
10801 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
10802 stackframes have been processed. By pushing zeros on the stack, GDB
10805 @b{Debugging Interrupt Service Routines} - In your ISR before you call
10806 your C code, do the same - artificially push some zeros onto the stack,
10807 remember to pop them off when the ISR is done.
10809 @b{Also note:} If you have a multi-threaded operating system, they
10810 often do not @b{in the intrest of saving memory} waste these few
10814 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
10815 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
10817 This warning doesn't indicate any serious problem, as long as you don't want to
10818 debug your core right out of reset. Your .cfg file specified @option{reset_config
10819 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
10820 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
10821 independently. With this setup, it's not possible to halt the core right out of
10822 reset, everything else should work fine.
10824 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
10825 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
10826 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
10827 quit with an error message. Is there a stability issue with OpenOCD?
10829 No, this is not a stability issue concerning OpenOCD. Most users have solved
10830 this issue by simply using a self-powered USB hub, which they connect their
10831 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
10832 supply stable enough for the Amontec JTAGkey to be operated.
10834 @b{Laptops running on battery have this problem too...}
10836 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
10837 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
10838 What does that mean and what might be the reason for this?
10840 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
10841 has closed the connection to OpenOCD. This might be a GDB issue.
10843 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
10844 are described, there is a parameter for specifying the clock frequency
10845 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
10846 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
10847 specified in kilohertz. However, I do have a quartz crystal of a
10848 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
10849 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
10852 No. The clock frequency specified here must be given as an integral number.
10853 However, this clock frequency is used by the In-Application-Programming (IAP)
10854 routines of the LPC2000 family only, which seems to be very tolerant concerning
10855 the given clock frequency, so a slight difference between the specified clock
10856 frequency and the actual clock frequency will not cause any trouble.
10858 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
10860 Well, yes and no. Commands can be given in arbitrary order, yet the
10861 devices listed for the JTAG scan chain must be given in the right
10862 order (jtag newdevice), with the device closest to the TDO-Pin being
10863 listed first. In general, whenever objects of the same type exist
10864 which require an index number, then these objects must be given in the
10865 right order (jtag newtap, targets and flash banks - a target
10866 references a jtag newtap and a flash bank references a target).
10868 You can use the ``scan_chain'' command to verify and display the tap order.
10870 Also, some commands can't execute until after @command{init} has been
10871 processed. Such commands include @command{nand probe} and everything
10872 else that needs to write to controller registers, perhaps for setting
10873 up DRAM and loading it with code.
10875 @anchor{faqtaporder}
10876 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
10879 Yes; whenever you have more than one, you must declare them in
10880 the same order used by the hardware.
10882 Many newer devices have multiple JTAG TAPs. For example:
10883 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
10884 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
10885 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
10886 connected to the boundary scan TAP, which then connects to the
10887 Cortex-M3 TAP, which then connects to the TDO pin.
10889 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
10890 (2) The boundary scan TAP. If your board includes an additional JTAG
10891 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
10892 place it before or after the STM32 chip in the chain. For example:
10895 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
10896 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
10897 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
10898 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
10899 @item Xilinx TDO Pin -> OpenOCD TDO (input)
10902 The ``jtag device'' commands would thus be in the order shown below. Note:
10905 @item jtag newtap Xilinx tap -irlen ...
10906 @item jtag newtap stm32 cpu -irlen ...
10907 @item jtag newtap stm32 bs -irlen ...
10908 @item # Create the debug target and say where it is
10909 @item target create stm32.cpu -chain-position stm32.cpu ...
10913 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
10914 log file, I can see these error messages: Error: arm7_9_common.c:561
10915 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
10921 @node Tcl Crash Course
10922 @chapter Tcl Crash Course
10925 Not everyone knows Tcl - this is not intended to be a replacement for
10926 learning Tcl, the intent of this chapter is to give you some idea of
10927 how the Tcl scripts work.
10929 This chapter is written with two audiences in mind. (1) OpenOCD users
10930 who need to understand a bit more of how Jim-Tcl works so they can do
10931 something useful, and (2) those that want to add a new command to
10934 @section Tcl Rule #1
10935 There is a famous joke, it goes like this:
10937 @item Rule #1: The wife is always correct
10938 @item Rule #2: If you think otherwise, See Rule #1
10941 The Tcl equal is this:
10944 @item Rule #1: Everything is a string
10945 @item Rule #2: If you think otherwise, See Rule #1
10948 As in the famous joke, the consequences of Rule #1 are profound. Once
10949 you understand Rule #1, you will understand Tcl.
10951 @section Tcl Rule #1b
10952 There is a second pair of rules.
10954 @item Rule #1: Control flow does not exist. Only commands
10955 @* For example: the classic FOR loop or IF statement is not a control
10956 flow item, they are commands, there is no such thing as control flow
10958 @item Rule #2: If you think otherwise, See Rule #1
10959 @* Actually what happens is this: There are commands that by
10960 convention, act like control flow key words in other languages. One of
10961 those commands is the word ``for'', another command is ``if''.
10964 @section Per Rule #1 - All Results are strings
10965 Every Tcl command results in a string. The word ``result'' is used
10966 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
10967 Everything is a string}
10969 @section Tcl Quoting Operators
10970 In life of a Tcl script, there are two important periods of time, the
10971 difference is subtle.
10974 @item Evaluation Time
10977 The two key items here are how ``quoted things'' work in Tcl. Tcl has
10978 three primary quoting constructs, the [square-brackets] the
10979 @{curly-braces@} and ``double-quotes''
10981 By now you should know $VARIABLES always start with a $DOLLAR
10982 sign. BTW: To set a variable, you actually use the command ``set'', as
10983 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
10984 = 1'' statement, but without the equal sign.
10987 @item @b{[square-brackets]}
10988 @* @b{[square-brackets]} are command substitutions. It operates much
10989 like Unix Shell `back-ticks`. The result of a [square-bracket]
10990 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
10991 string}. These two statements are roughly identical:
10995 echo "The Date is: $X"
10998 puts "The Date is: $X"
11000 @item @b{``double-quoted-things''}
11001 @* @b{``double-quoted-things''} are just simply quoted
11002 text. $VARIABLES and [square-brackets] are expanded in place - the
11003 result however is exactly 1 string. @i{Remember Rule #1 - Everything
11007 puts "It is now \"[date]\", $x is in 1 hour"
11009 @item @b{@{Curly-Braces@}}
11010 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
11011 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
11012 'single-quote' operators in BASH shell scripts, with the added
11013 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
11014 nested 3 times@}@}@} NOTE: [date] is a bad example;
11015 at this writing, Jim/OpenOCD does not have a date command.
11018 @section Consequences of Rule 1/2/3/4
11020 The consequences of Rule 1 are profound.
11022 @subsection Tokenisation & Execution.
11024 Of course, whitespace, blank lines and #comment lines are handled in
11027 As a script is parsed, each (multi) line in the script file is
11028 tokenised and according to the quoting rules. After tokenisation, that
11029 line is immediately executed.
11031 Multi line statements end with one or more ``still-open''
11032 @{curly-braces@} which - eventually - closes a few lines later.
11034 @subsection Command Execution
11036 Remember earlier: There are no ``control flow''
11037 statements in Tcl. Instead there are COMMANDS that simply act like
11038 control flow operators.
11040 Commands are executed like this:
11043 @item Parse the next line into (argc) and (argv[]).
11044 @item Look up (argv[0]) in a table and call its function.
11045 @item Repeat until End Of File.
11048 It sort of works like this:
11051 ReadAndParse( &argc, &argv );
11053 cmdPtr = LookupCommand( argv[0] );
11055 (*cmdPtr->Execute)( argc, argv );
11059 When the command ``proc'' is parsed (which creates a procedure
11060 function) it gets 3 parameters on the command line. @b{1} the name of
11061 the proc (function), @b{2} the list of parameters, and @b{3} the body
11062 of the function. Not the choice of words: LIST and BODY. The PROC
11063 command stores these items in a table somewhere so it can be found by
11064 ``LookupCommand()''
11066 @subsection The FOR command
11068 The most interesting command to look at is the FOR command. In Tcl,
11069 the FOR command is normally implemented in C. Remember, FOR is a
11070 command just like any other command.
11072 When the ascii text containing the FOR command is parsed, the parser
11073 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
11077 @item The ascii text 'for'
11078 @item The start text
11079 @item The test expression
11080 @item The next text
11081 @item The body text
11084 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
11085 Remember @i{Rule #1 - Everything is a string.} The key point is this:
11086 Often many of those parameters are in @{curly-braces@} - thus the
11087 variables inside are not expanded or replaced until later.
11089 Remember that every Tcl command looks like the classic ``main( argc,
11090 argv )'' function in C. In JimTCL - they actually look like this:
11094 MyCommand( Jim_Interp *interp,
11096 Jim_Obj * const *argvs );
11099 Real Tcl is nearly identical. Although the newer versions have
11100 introduced a byte-code parser and interpreter, but at the core, it
11101 still operates in the same basic way.
11103 @subsection FOR command implementation
11105 To understand Tcl it is perhaps most helpful to see the FOR
11106 command. Remember, it is a COMMAND not a control flow structure.
11108 In Tcl there are two underlying C helper functions.
11110 Remember Rule #1 - You are a string.
11112 The @b{first} helper parses and executes commands found in an ascii
11113 string. Commands can be separated by semicolons, or newlines. While
11114 parsing, variables are expanded via the quoting rules.
11116 The @b{second} helper evaluates an ascii string as a numerical
11117 expression and returns a value.
11119 Here is an example of how the @b{FOR} command could be
11120 implemented. The pseudo code below does not show error handling.
11122 void Execute_AsciiString( void *interp, const char *string );
11124 int Evaluate_AsciiExpression( void *interp, const char *string );
11127 MyForCommand( void *interp,
11132 SetResult( interp, "WRONG number of parameters");
11136 // argv[0] = the ascii string just like C
11138 // Execute the start statement.
11139 Execute_AsciiString( interp, argv[1] );
11141 // Top of loop test
11143 i = Evaluate_AsciiExpression(interp, argv[2]);
11147 // Execute the body
11148 Execute_AsciiString( interp, argv[3] );
11150 // Execute the LOOP part
11151 Execute_AsciiString( interp, argv[4] );
11155 SetResult( interp, "" );
11160 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
11161 in the same basic way.
11163 @section OpenOCD Tcl Usage
11165 @subsection source and find commands
11166 @b{Where:} In many configuration files
11167 @* Example: @b{ source [find FILENAME] }
11168 @*Remember the parsing rules
11170 @item The @command{find} command is in square brackets,
11171 and is executed with the parameter FILENAME. It should find and return
11172 the full path to a file with that name; it uses an internal search path.
11173 The RESULT is a string, which is substituted into the command line in
11174 place of the bracketed @command{find} command.
11175 (Don't try to use a FILENAME which includes the "#" character.
11176 That character begins Tcl comments.)
11177 @item The @command{source} command is executed with the resulting filename;
11178 it reads a file and executes as a script.
11180 @subsection format command
11181 @b{Where:} Generally occurs in numerous places.
11182 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
11188 puts [format "The answer: %d" [expr $x * $y]]
11191 @item The SET command creates 2 variables, X and Y.
11192 @item The double [nested] EXPR command performs math
11193 @* The EXPR command produces numerical result as a string.
11194 @* Refer to Rule #1
11195 @item The format command is executed, producing a single string
11196 @* Refer to Rule #1.
11197 @item The PUTS command outputs the text.
11199 @subsection Body or Inlined Text
11200 @b{Where:} Various TARGET scripts.
11203 proc someproc @{@} @{
11204 ... multiple lines of stuff ...
11206 $_TARGETNAME configure -event FOO someproc
11207 #2 Good - no variables
11208 $_TARGETNAME configure -event foo "this ; that;"
11209 #3 Good Curly Braces
11210 $_TARGETNAME configure -event FOO @{
11211 puts "Time: [date]"
11213 #4 DANGER DANGER DANGER
11214 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
11217 @item The $_TARGETNAME is an OpenOCD variable convention.
11218 @*@b{$_TARGETNAME} represents the last target created, the value changes
11219 each time a new target is created. Remember the parsing rules. When
11220 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
11221 the name of the target which happens to be a TARGET (object)
11223 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
11224 @*There are 4 examples:
11226 @item The TCLBODY is a simple string that happens to be a proc name
11227 @item The TCLBODY is several simple commands separated by semicolons
11228 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
11229 @item The TCLBODY is a string with variables that get expanded.
11232 In the end, when the target event FOO occurs the TCLBODY is
11233 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
11234 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
11236 Remember the parsing rules. In case #3, @{curly-braces@} mean the
11237 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
11238 and the text is evaluated. In case #4, they are replaced before the
11239 ``Target Object Command'' is executed. This occurs at the same time
11240 $_TARGETNAME is replaced. In case #4 the date will never
11241 change. @{BTW: [date] is a bad example; at this writing,
11242 Jim/OpenOCD does not have a date command@}
11244 @subsection Global Variables
11245 @b{Where:} You might discover this when writing your own procs @* In
11246 simple terms: Inside a PROC, if you need to access a global variable
11247 you must say so. See also ``upvar''. Example:
11249 proc myproc @{ @} @{
11250 set y 0 #Local variable Y
11251 global x #Global variable X
11252 puts [format "X=%d, Y=%d" $x $y]
11255 @section Other Tcl Hacks
11256 @b{Dynamic variable creation}
11258 # Dynamically create a bunch of variables.
11259 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
11261 set vn [format "BIT%d" $x]
11265 set $vn [expr (1 << $x)]
11268 @b{Dynamic proc/command creation}
11270 # One "X" function - 5 uart functions.
11271 foreach who @{A B C D E@}
11272 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
11278 @node OpenOCD Concept Index
11279 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
11280 @comment case issue with ``Index.html'' and ``index.html''
11281 @comment Occurs when creating ``--html --no-split'' output
11282 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
11283 @unnumbered OpenOCD Concept Index
11287 @node Command and Driver Index
11288 @unnumbered Command and Driver Index