1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
536 @section IBM PC Parallel Printer Port Based
538 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
539 and the Macraigor Wiggler. There are many clones and variations of
542 Note that parallel ports are becoming much less common, so if you
543 have the choice you should probably avoid these adapters in favor
548 @item @b{Wiggler} - There are many clones of this.
549 @* Link: @url{http://www.macraigor.com/wiggler.htm}
551 @item @b{DLC5} - From XILINX - There are many clones of this
552 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
553 produced, PDF schematics are easily found and it is easy to make.
555 @item @b{Amontec - JTAG Accelerator}
556 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
559 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
561 @item @b{Wiggler_ntrst_inverted}
562 @* Yet another variation - See the source code, src/jtag/parport.c
564 @item @b{old_amt_wiggler}
565 @* Unknown - probably not on the market today
568 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
571 @* Link: @url{http://www.amontec.com/chameleon.shtml}
577 @* ispDownload from Lattice Semiconductor
578 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
581 @* From ST Microsystems;
582 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
590 @* An EP93xx based Linux machine using the GPIO pins directly.
593 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
595 @item @b{bcm2835gpio}
596 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
599 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
602 @* A JTAG driver acting as a client for the JTAG VPI server interface.
603 @* Link: @url{http://github.com/fjullien/jtag_vpi}
608 @chapter About Jim-Tcl
612 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
613 This programming language provides a simple and extensible
616 All commands presented in this Guide are extensions to Jim-Tcl.
617 You can use them as simple commands, without needing to learn
618 much of anything about Tcl.
619 Alternatively, you can write Tcl programs with them.
621 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
622 There is an active and responsive community, get on the mailing list
623 if you have any questions. Jim-Tcl maintainers also lurk on the
624 OpenOCD mailing list.
627 @item @b{Jim vs. Tcl}
628 @* Jim-Tcl is a stripped down version of the well known Tcl language,
629 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
630 fewer features. Jim-Tcl is several dozens of .C files and .H files and
631 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
632 4.2 MB .zip file containing 1540 files.
634 @item @b{Missing Features}
635 @* Our practice has been: Add/clone the real Tcl feature if/when
636 needed. We welcome Jim-Tcl improvements, not bloat. Also there
637 are a large number of optional Jim-Tcl features that are not
641 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
642 command interpreter today is a mixture of (newer)
643 Jim-Tcl commands, and the (older) original command interpreter.
646 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
647 can type a Tcl for() loop, set variables, etc.
648 Some of the commands documented in this guide are implemented
649 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
651 @item @b{Historical Note}
652 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
653 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
654 as a Git submodule, which greatly simplified upgrading Jim-Tcl
655 to benefit from new features and bugfixes in Jim-Tcl.
657 @item @b{Need a crash course in Tcl?}
658 @*@xref{Tcl Crash Course}.
663 @cindex command line options
665 @cindex directory search
667 Properly installing OpenOCD sets up your operating system to grant it access
668 to the debug adapters. On Linux, this usually involves installing a file
669 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
670 that works for many common adapters is shipped with OpenOCD in the
671 @file{contrib} directory. MS-Windows needs
672 complex and confusing driver configuration for every peripheral. Such issues
673 are unique to each operating system, and are not detailed in this User's Guide.
675 Then later you will invoke the OpenOCD server, with various options to
676 tell it how each debug session should work.
677 The @option{--help} option shows:
681 --help | -h display this help
682 --version | -v display OpenOCD version
683 --file | -f use configuration file <name>
684 --search | -s dir to search for config files and scripts
685 --debug | -d set debug level <0-3>
686 --log_output | -l redirect log output to file <name>
687 --command | -c run <command>
690 If you don't give any @option{-f} or @option{-c} options,
691 OpenOCD tries to read the configuration file @file{openocd.cfg}.
692 To specify one or more different
693 configuration files, use @option{-f} options. For example:
696 openocd -f config1.cfg -f config2.cfg -f config3.cfg
699 Configuration files and scripts are searched for in
701 @item the current directory,
702 @item any search dir specified on the command line using the @option{-s} option,
703 @item any search dir specified using the @command{add_script_search_dir} command,
704 @item @file{$HOME/.openocd} (not on Windows),
705 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
706 @item the site wide script library @file{$pkgdatadir/site} and
707 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
709 The first found file with a matching file name will be used.
712 Don't try to use configuration script names or paths which
713 include the "#" character. That character begins Tcl comments.
716 @section Simple setup, no customization
718 In the best case, you can use two scripts from one of the script
719 libraries, hook up your JTAG adapter, and start the server ... and
720 your JTAG setup will just work "out of the box". Always try to
721 start by reusing those scripts, but assume you'll need more
722 customization even if this works. @xref{OpenOCD Project Setup}.
724 If you find a script for your JTAG adapter, and for your board or
725 target, you may be able to hook up your JTAG adapter then start
726 the server with some variation of one of the following:
729 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
730 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
733 You might also need to configure which reset signals are present,
734 using @option{-c 'reset_config trst_and_srst'} or something similar.
735 If all goes well you'll see output something like
738 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
739 For bug reports, read
740 http://openocd.org/doc/doxygen/bugs.html
741 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
742 (mfg: 0x23b, part: 0xba00, ver: 0x3)
745 Seeing that "tap/device found" message, and no warnings, means
746 the JTAG communication is working. That's a key milestone, but
747 you'll probably need more project-specific setup.
749 @section What OpenOCD does as it starts
751 OpenOCD starts by processing the configuration commands provided
752 on the command line or, if there were no @option{-c command} or
753 @option{-f file.cfg} options given, in @file{openocd.cfg}.
754 @xref{configurationstage,,Configuration Stage}.
755 At the end of the configuration stage it verifies the JTAG scan
756 chain defined using those commands; your configuration should
757 ensure that this always succeeds.
758 Normally, OpenOCD then starts running as a server.
759 Alternatively, commands may be used to terminate the configuration
760 stage early, perform work (such as updating some flash memory),
761 and then shut down without acting as a server.
763 Once OpenOCD starts running as a server, it waits for connections from
764 clients (Telnet, GDB, RPC) and processes the commands issued through
767 If you are having problems, you can enable internal debug messages via
768 the @option{-d} option.
770 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
771 @option{-c} command line switch.
773 To enable debug output (when reporting problems or working on OpenOCD
774 itself), use the @option{-d} command line switch. This sets the
775 @option{debug_level} to "3", outputting the most information,
776 including debug messages. The default setting is "2", outputting only
777 informational messages, warnings and errors. You can also change this
778 setting from within a telnet or gdb session using @command{debug_level<n>}
779 (@pxref{debuglevel,,debug_level}).
781 You can redirect all output from the server to a file using the
782 @option{-l <logfile>} switch.
784 Note! OpenOCD will launch the GDB & telnet server even if it can not
785 establish a connection with the target. In general, it is possible for
786 the JTAG controller to be unresponsive until the target is set up
787 correctly via e.g. GDB monitor commands in a GDB init script.
789 @node OpenOCD Project Setup
790 @chapter OpenOCD Project Setup
792 To use OpenOCD with your development projects, you need to do more than
793 just connect the JTAG adapter hardware (dongle) to your development board
794 and start the OpenOCD server.
795 You also need to configure your OpenOCD server so that it knows
796 about your adapter and board, and helps your work.
797 You may also want to connect OpenOCD to GDB, possibly
798 using Eclipse or some other GUI.
800 @section Hooking up the JTAG Adapter
802 Today's most common case is a dongle with a JTAG cable on one side
803 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
804 and a USB cable on the other.
805 Instead of USB, some cables use Ethernet;
806 older ones may use a PC parallel port, or even a serial port.
809 @item @emph{Start with power to your target board turned off},
810 and nothing connected to your JTAG adapter.
811 If you're particularly paranoid, unplug power to the board.
812 It's important to have the ground signal properly set up,
813 unless you are using a JTAG adapter which provides
814 galvanic isolation between the target board and the
817 @item @emph{Be sure it's the right kind of JTAG connector.}
818 If your dongle has a 20-pin ARM connector, you need some kind
819 of adapter (or octopus, see below) to hook it up to
820 boards using 14-pin or 10-pin connectors ... or to 20-pin
821 connectors which don't use ARM's pinout.
823 In the same vein, make sure the voltage levels are compatible.
824 Not all JTAG adapters have the level shifters needed to work
825 with 1.2 Volt boards.
827 @item @emph{Be certain the cable is properly oriented} or you might
828 damage your board. In most cases there are only two possible
829 ways to connect the cable.
830 Connect the JTAG cable from your adapter to the board.
831 Be sure it's firmly connected.
833 In the best case, the connector is keyed to physically
834 prevent you from inserting it wrong.
835 This is most often done using a slot on the board's male connector
836 housing, which must match a key on the JTAG cable's female connector.
837 If there's no housing, then you must look carefully and
838 make sure pin 1 on the cable hooks up to pin 1 on the board.
839 Ribbon cables are frequently all grey except for a wire on one
840 edge, which is red. The red wire is pin 1.
842 Sometimes dongles provide cables where one end is an ``octopus'' of
843 color coded single-wire connectors, instead of a connector block.
844 These are great when converting from one JTAG pinout to another,
845 but are tedious to set up.
846 Use these with connector pinout diagrams to help you match up the
847 adapter signals to the right board pins.
849 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
850 A USB, parallel, or serial port connector will go to the host which
851 you are using to run OpenOCD.
852 For Ethernet, consult the documentation and your network administrator.
854 For USB-based JTAG adapters you have an easy sanity check at this point:
855 does the host operating system see the JTAG adapter? If you're running
856 Linux, try the @command{lsusb} command. If that host is an
857 MS-Windows host, you'll need to install a driver before OpenOCD works.
859 @item @emph{Connect the adapter's power supply, if needed.}
860 This step is primarily for non-USB adapters,
861 but sometimes USB adapters need extra power.
863 @item @emph{Power up the target board.}
864 Unless you just let the magic smoke escape,
865 you're now ready to set up the OpenOCD server
866 so you can use JTAG to work with that board.
870 Talk with the OpenOCD server using
871 telnet (@code{telnet localhost 4444} on many systems) or GDB.
872 @xref{GDB and OpenOCD}.
874 @section Project Directory
876 There are many ways you can configure OpenOCD and start it up.
878 A simple way to organize them all involves keeping a
879 single directory for your work with a given board.
880 When you start OpenOCD from that directory,
881 it searches there first for configuration files, scripts,
882 files accessed through semihosting,
883 and for code you upload to the target board.
884 It is also the natural place to write files,
885 such as log files and data you download from the board.
887 @section Configuration Basics
889 There are two basic ways of configuring OpenOCD, and
890 a variety of ways you can mix them.
891 Think of the difference as just being how you start the server:
894 @item Many @option{-f file} or @option{-c command} options on the command line
895 @item No options, but a @dfn{user config file}
896 in the current directory named @file{openocd.cfg}
899 Here is an example @file{openocd.cfg} file for a setup
900 using a Signalyzer FT2232-based JTAG adapter to talk to
901 a board with an Atmel AT91SAM7X256 microcontroller:
904 source [find interface/ftdi/signalyzer.cfg]
906 # GDB can also flash my flash!
907 gdb_memory_map enable
908 gdb_flash_program enable
910 source [find target/sam7x256.cfg]
913 Here is the command line equivalent of that configuration:
916 openocd -f interface/ftdi/signalyzer.cfg \
917 -c "gdb_memory_map enable" \
918 -c "gdb_flash_program enable" \
919 -f target/sam7x256.cfg
922 You could wrap such long command lines in shell scripts,
923 each supporting a different development task.
924 One might re-flash the board with a specific firmware version.
925 Another might set up a particular debugging or run-time environment.
928 At this writing (October 2009) the command line method has
929 problems with how it treats variables.
930 For example, after @option{-c "set VAR value"}, or doing the
931 same in a script, the variable @var{VAR} will have no value
932 that can be tested in a later script.
935 Here we will focus on the simpler solution: one user config
936 file, including basic configuration plus any TCL procedures
937 to simplify your work.
939 @section User Config Files
940 @cindex config file, user
941 @cindex user config file
942 @cindex config file, overview
944 A user configuration file ties together all the parts of a project
946 One of the following will match your situation best:
949 @item Ideally almost everything comes from configuration files
950 provided by someone else.
951 For example, OpenOCD distributes a @file{scripts} directory
952 (probably in @file{/usr/share/openocd/scripts} on Linux).
953 Board and tool vendors can provide these too, as can individual
954 user sites; the @option{-s} command line option lets you say
955 where to find these files. (@xref{Running}.)
956 The AT91SAM7X256 example above works this way.
958 Three main types of non-user configuration file each have their
959 own subdirectory in the @file{scripts} directory:
962 @item @b{interface} -- one for each different debug adapter;
963 @item @b{board} -- one for each different board
964 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
967 Best case: include just two files, and they handle everything else.
968 The first is an interface config file.
969 The second is board-specific, and it sets up the JTAG TAPs and
970 their GDB targets (by deferring to some @file{target.cfg} file),
971 declares all flash memory, and leaves you nothing to do except
975 source [find interface/olimex-jtag-tiny.cfg]
976 source [find board/csb337.cfg]
979 Boards with a single microcontroller often won't need more
980 than the target config file, as in the AT91SAM7X256 example.
981 That's because there is no external memory (flash, DDR RAM), and
982 the board differences are encapsulated by application code.
984 @item Maybe you don't know yet what your board looks like to JTAG.
985 Once you know the @file{interface.cfg} file to use, you may
986 need help from OpenOCD to discover what's on the board.
987 Once you find the JTAG TAPs, you can just search for appropriate
989 configuration files ... or write your own, from the bottom up.
990 @xref{autoprobing,,Autoprobing}.
992 @item You can often reuse some standard config files but
993 need to write a few new ones, probably a @file{board.cfg} file.
994 You will be using commands described later in this User's Guide,
995 and working with the guidelines in the next chapter.
997 For example, there may be configuration files for your JTAG adapter
998 and target chip, but you need a new board-specific config file
999 giving access to your particular flash chips.
1000 Or you might need to write another target chip configuration file
1001 for a new chip built around the Cortex-M3 core.
1004 When you write new configuration files, please submit
1005 them for inclusion in the next OpenOCD release.
1006 For example, a @file{board/newboard.cfg} file will help the
1007 next users of that board, and a @file{target/newcpu.cfg}
1008 will help support users of any board using that chip.
1012 You may may need to write some C code.
1013 It may be as simple as supporting a new FT2232 or parport
1014 based adapter; a bit more involved, like a NAND or NOR flash
1015 controller driver; or a big piece of work like supporting
1016 a new chip architecture.
1019 Reuse the existing config files when you can.
1020 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1021 You may find a board configuration that's a good example to follow.
1023 When you write config files, separate the reusable parts
1024 (things every user of that interface, chip, or board needs)
1025 from ones specific to your environment and debugging approach.
1029 For example, a @code{gdb-attach} event handler that invokes
1030 the @command{reset init} command will interfere with debugging
1031 early boot code, which performs some of the same actions
1032 that the @code{reset-init} event handler does.
1035 Likewise, the @command{arm9 vector_catch} command (or
1036 @cindex vector_catch
1037 its siblings @command{xscale vector_catch}
1038 and @command{cortex_m vector_catch}) can be a timesaver
1039 during some debug sessions, but don't make everyone use that either.
1040 Keep those kinds of debugging aids in your user config file,
1041 along with messaging and tracing setup.
1042 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1045 You might need to override some defaults.
1046 For example, you might need to move, shrink, or back up the target's
1047 work area if your application needs much SRAM.
1050 TCP/IP port configuration is another example of something which
1051 is environment-specific, and should only appear in
1052 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1055 @section Project-Specific Utilities
1057 A few project-specific utility
1058 routines may well speed up your work.
1059 Write them, and keep them in your project's user config file.
1061 For example, if you are making a boot loader work on a
1062 board, it's nice to be able to debug the ``after it's
1063 loaded to RAM'' parts separately from the finicky early
1064 code which sets up the DDR RAM controller and clocks.
1065 A script like this one, or a more GDB-aware sibling,
1069 proc ramboot @{ @} @{
1070 # Reset, running the target's "reset-init" scripts
1071 # to initialize clocks and the DDR RAM controller.
1072 # Leave the CPU halted.
1075 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1076 load_image u-boot.bin 0x20000000
1083 Then once that code is working you will need to make it
1084 boot from NOR flash; a different utility would help.
1085 Alternatively, some developers write to flash using GDB.
1086 (You might use a similar script if you're working with a flash
1087 based microcontroller application instead of a boot loader.)
1090 proc newboot @{ @} @{
1091 # Reset, leaving the CPU halted. The "reset-init" event
1092 # proc gives faster access to the CPU and to NOR flash;
1093 # "reset halt" would be slower.
1096 # Write standard version of U-Boot into the first two
1097 # sectors of NOR flash ... the standard version should
1098 # do the same lowlevel init as "reset-init".
1099 flash protect 0 0 1 off
1100 flash erase_sector 0 0 1
1101 flash write_bank 0 u-boot.bin 0x0
1102 flash protect 0 0 1 on
1104 # Reboot from scratch using that new boot loader.
1109 You may need more complicated utility procedures when booting
1111 That often involves an extra bootloader stage,
1112 running from on-chip SRAM to perform DDR RAM setup so it can load
1113 the main bootloader code (which won't fit into that SRAM).
1115 Other helper scripts might be used to write production system images,
1116 involving considerably more than just a three stage bootloader.
1118 @section Target Software Changes
1120 Sometimes you may want to make some small changes to the software
1121 you're developing, to help make JTAG debugging work better.
1122 For example, in C or assembly language code you might
1123 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1124 handling issues like:
1128 @item @b{Watchdog Timers}...
1129 Watchog timers are typically used to automatically reset systems if
1130 some application task doesn't periodically reset the timer. (The
1131 assumption is that the system has locked up if the task can't run.)
1132 When a JTAG debugger halts the system, that task won't be able to run
1133 and reset the timer ... potentially causing resets in the middle of
1134 your debug sessions.
1136 It's rarely a good idea to disable such watchdogs, since their usage
1137 needs to be debugged just like all other parts of your firmware.
1138 That might however be your only option.
1140 Look instead for chip-specific ways to stop the watchdog from counting
1141 while the system is in a debug halt state. It may be simplest to set
1142 that non-counting mode in your debugger startup scripts. You may however
1143 need a different approach when, for example, a motor could be physically
1144 damaged by firmware remaining inactive in a debug halt state. That might
1145 involve a type of firmware mode where that "non-counting" mode is disabled
1146 at the beginning then re-enabled at the end; a watchdog reset might fire
1147 and complicate the debug session, but hardware (or people) would be
1148 protected.@footnote{Note that many systems support a "monitor mode" debug
1149 that is a somewhat cleaner way to address such issues. You can think of
1150 it as only halting part of the system, maybe just one task,
1151 instead of the whole thing.
1152 At this writing, January 2010, OpenOCD based debugging does not support
1153 monitor mode debug, only "halt mode" debug.}
1155 @item @b{ARM Semihosting}...
1156 @cindex ARM semihosting
1157 When linked with a special runtime library provided with many
1158 toolchains@footnote{See chapter 8 "Semihosting" in
1159 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1160 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1161 The CodeSourcery EABI toolchain also includes a semihosting library.},
1162 your target code can use I/O facilities on the debug host. That library
1163 provides a small set of system calls which are handled by OpenOCD.
1164 It can let the debugger provide your system console and a file system,
1165 helping with early debugging or providing a more capable environment
1166 for sometimes-complex tasks like installing system firmware onto
1169 @item @b{ARM Wait-For-Interrupt}...
1170 Many ARM chips synchronize the JTAG clock using the core clock.
1171 Low power states which stop that core clock thus prevent JTAG access.
1172 Idle loops in tasking environments often enter those low power states
1173 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1175 You may want to @emph{disable that instruction} in source code,
1176 or otherwise prevent using that state,
1177 to ensure you can get JTAG access at any time.@footnote{As a more
1178 polite alternative, some processors have special debug-oriented
1179 registers which can be used to change various features including
1180 how the low power states are clocked while debugging.
1181 The STM32 DBGMCU_CR register is an example; at the cost of extra
1182 power consumption, JTAG can be used during low power states.}
1183 For example, the OpenOCD @command{halt} command may not
1184 work for an idle processor otherwise.
1186 @item @b{Delay after reset}...
1187 Not all chips have good support for debugger access
1188 right after reset; many LPC2xxx chips have issues here.
1189 Similarly, applications that reconfigure pins used for
1190 JTAG access as they start will also block debugger access.
1192 To work with boards like this, @emph{enable a short delay loop}
1193 the first thing after reset, before "real" startup activities.
1194 For example, one second's delay is usually more than enough
1195 time for a JTAG debugger to attach, so that
1196 early code execution can be debugged
1197 or firmware can be replaced.
1199 @item @b{Debug Communications Channel (DCC)}...
1200 Some processors include mechanisms to send messages over JTAG.
1201 Many ARM cores support these, as do some cores from other vendors.
1202 (OpenOCD may be able to use this DCC internally, speeding up some
1203 operations like writing to memory.)
1205 Your application may want to deliver various debugging messages
1206 over JTAG, by @emph{linking with a small library of code}
1207 provided with OpenOCD and using the utilities there to send
1208 various kinds of message.
1209 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1213 @section Target Hardware Setup
1215 Chip vendors often provide software development boards which
1216 are highly configurable, so that they can support all options
1217 that product boards may require. @emph{Make sure that any
1218 jumpers or switches match the system configuration you are
1221 Common issues include:
1225 @item @b{JTAG setup} ...
1226 Boards may support more than one JTAG configuration.
1227 Examples include jumpers controlling pullups versus pulldowns
1228 on the nTRST and/or nSRST signals, and choice of connectors
1229 (e.g. which of two headers on the base board,
1230 or one from a daughtercard).
1231 For some Texas Instruments boards, you may need to jumper the
1232 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1234 @item @b{Boot Modes} ...
1235 Complex chips often support multiple boot modes, controlled
1236 by external jumpers. Make sure this is set up correctly.
1237 For example many i.MX boards from NXP need to be jumpered
1238 to "ATX mode" to start booting using the on-chip ROM, when
1239 using second stage bootloader code stored in a NAND flash chip.
1241 Such explicit configuration is common, and not limited to
1242 booting from NAND. You might also need to set jumpers to
1243 start booting using code loaded from an MMC/SD card; external
1244 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1245 flash; some external host; or various other sources.
1248 @item @b{Memory Addressing} ...
1249 Boards which support multiple boot modes may also have jumpers
1250 to configure memory addressing. One board, for example, jumpers
1251 external chipselect 0 (used for booting) to address either
1252 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1253 or NAND flash. When it's jumpered to address NAND flash, that
1254 board must also be told to start booting from on-chip ROM.
1256 Your @file{board.cfg} file may also need to be told this jumper
1257 configuration, so that it can know whether to declare NOR flash
1258 using @command{flash bank} or instead declare NAND flash with
1259 @command{nand device}; and likewise which probe to perform in
1260 its @code{reset-init} handler.
1262 A closely related issue is bus width. Jumpers might need to
1263 distinguish between 8 bit or 16 bit bus access for the flash
1264 used to start booting.
1266 @item @b{Peripheral Access} ...
1267 Development boards generally provide access to every peripheral
1268 on the chip, sometimes in multiple modes (such as by providing
1269 multiple audio codec chips).
1270 This interacts with software
1271 configuration of pin multiplexing, where for example a
1272 given pin may be routed either to the MMC/SD controller
1273 or the GPIO controller. It also often interacts with
1274 configuration jumpers. One jumper may be used to route
1275 signals to an MMC/SD card slot or an expansion bus (which
1276 might in turn affect booting); others might control which
1277 audio or video codecs are used.
1281 Plus you should of course have @code{reset-init} event handlers
1282 which set up the hardware to match that jumper configuration.
1283 That includes in particular any oscillator or PLL used to clock
1284 the CPU, and any memory controllers needed to access external
1285 memory and peripherals. Without such handlers, you won't be
1286 able to access those resources without working target firmware
1287 which can do that setup ... this can be awkward when you're
1288 trying to debug that target firmware. Even if there's a ROM
1289 bootloader which handles a few issues, it rarely provides full
1290 access to all board-specific capabilities.
1293 @node Config File Guidelines
1294 @chapter Config File Guidelines
1296 This chapter is aimed at any user who needs to write a config file,
1297 including developers and integrators of OpenOCD and any user who
1298 needs to get a new board working smoothly.
1299 It provides guidelines for creating those files.
1301 You should find the following directories under
1302 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1303 them as-is where you can; or as models for new files.
1305 @item @file{interface} ...
1306 These are for debug adapters. Files that specify configuration to use
1307 specific JTAG, SWD and other adapters go here.
1308 @item @file{board} ...
1309 Think Circuit Board, PWA, PCB, they go by many names. Board files
1310 contain initialization items that are specific to a board.
1312 They reuse target configuration files, since the same
1313 microprocessor chips are used on many boards,
1314 but support for external parts varies widely. For
1315 example, the SDRAM initialization sequence for the board, or the type
1316 of external flash and what address it uses. Any initialization
1317 sequence to enable that external flash or SDRAM should be found in the
1318 board file. Boards may also contain multiple targets: two CPUs; or
1320 @item @file{target} ...
1321 Think chip. The ``target'' directory represents the JTAG TAPs
1323 which OpenOCD should control, not a board. Two common types of targets
1324 are ARM chips and FPGA or CPLD chips.
1325 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1326 the target config file defines all of them.
1327 @item @emph{more} ... browse for other library files which may be useful.
1328 For example, there are various generic and CPU-specific utilities.
1331 The @file{openocd.cfg} user config
1332 file may override features in any of the above files by
1333 setting variables before sourcing the target file, or by adding
1334 commands specific to their situation.
1336 @section Interface Config Files
1338 The user config file
1339 should be able to source one of these files with a command like this:
1342 source [find interface/FOOBAR.cfg]
1345 A preconfigured interface file should exist for every debug adapter
1346 in use today with OpenOCD.
1347 That said, perhaps some of these config files
1348 have only been used by the developer who created it.
1350 A separate chapter gives information about how to set these up.
1351 @xref{Debug Adapter Configuration}.
1352 Read the OpenOCD source code (and Developer's Guide)
1353 if you have a new kind of hardware interface
1354 and need to provide a driver for it.
1356 @section Board Config Files
1357 @cindex config file, board
1358 @cindex board config file
1360 The user config file
1361 should be able to source one of these files with a command like this:
1364 source [find board/FOOBAR.cfg]
1367 The point of a board config file is to package everything
1368 about a given board that user config files need to know.
1369 In summary the board files should contain (if present)
1372 @item One or more @command{source [find target/...cfg]} statements
1373 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1374 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1375 @item Target @code{reset} handlers for SDRAM and I/O configuration
1376 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1377 @item All things that are not ``inside a chip''
1380 Generic things inside target chips belong in target config files,
1381 not board config files. So for example a @code{reset-init} event
1382 handler should know board-specific oscillator and PLL parameters,
1383 which it passes to target-specific utility code.
1385 The most complex task of a board config file is creating such a
1386 @code{reset-init} event handler.
1387 Define those handlers last, after you verify the rest of the board
1388 configuration works.
1390 @subsection Communication Between Config files
1392 In addition to target-specific utility code, another way that
1393 board and target config files communicate is by following a
1394 convention on how to use certain variables.
1396 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1397 Thus the rule we follow in OpenOCD is this: Variables that begin with
1398 a leading underscore are temporary in nature, and can be modified and
1399 used at will within a target configuration file.
1401 Complex board config files can do the things like this,
1402 for a board with three chips:
1405 # Chip #1: PXA270 for network side, big endian
1406 set CHIPNAME network
1408 source [find target/pxa270.cfg]
1409 # on return: _TARGETNAME = network.cpu
1410 # other commands can refer to the "network.cpu" target.
1411 $_TARGETNAME configure .... events for this CPU..
1413 # Chip #2: PXA270 for video side, little endian
1416 source [find target/pxa270.cfg]
1417 # on return: _TARGETNAME = video.cpu
1418 # other commands can refer to the "video.cpu" target.
1419 $_TARGETNAME configure .... events for this CPU..
1421 # Chip #3: Xilinx FPGA for glue logic
1424 source [find target/spartan3.cfg]
1427 That example is oversimplified because it doesn't show any flash memory,
1428 or the @code{reset-init} event handlers to initialize external DRAM
1429 or (assuming it needs it) load a configuration into the FPGA.
1430 Such features are usually needed for low-level work with many boards,
1431 where ``low level'' implies that the board initialization software may
1432 not be working. (That's a common reason to need JTAG tools. Another
1433 is to enable working with microcontroller-based systems, which often
1434 have no debugging support except a JTAG connector.)
1436 Target config files may also export utility functions to board and user
1437 config files. Such functions should use name prefixes, to help avoid
1440 Board files could also accept input variables from user config files.
1441 For example, there might be a @code{J4_JUMPER} setting used to identify
1442 what kind of flash memory a development board is using, or how to set
1443 up other clocks and peripherals.
1445 @subsection Variable Naming Convention
1446 @cindex variable names
1448 Most boards have only one instance of a chip.
1449 However, it should be easy to create a board with more than
1450 one such chip (as shown above).
1451 Accordingly, we encourage these conventions for naming
1452 variables associated with different @file{target.cfg} files,
1453 to promote consistency and
1454 so that board files can override target defaults.
1456 Inputs to target config files include:
1459 @item @code{CHIPNAME} ...
1460 This gives a name to the overall chip, and is used as part of
1461 tap identifier dotted names.
1462 While the default is normally provided by the chip manufacturer,
1463 board files may need to distinguish between instances of a chip.
1464 @item @code{ENDIAN} ...
1465 By default @option{little} - although chips may hard-wire @option{big}.
1466 Chips that can't change endianness don't need to use this variable.
1467 @item @code{CPUTAPID} ...
1468 When OpenOCD examines the JTAG chain, it can be told verify the
1469 chips against the JTAG IDCODE register.
1470 The target file will hold one or more defaults, but sometimes the
1471 chip in a board will use a different ID (perhaps a newer revision).
1474 Outputs from target config files include:
1477 @item @code{_TARGETNAME} ...
1478 By convention, this variable is created by the target configuration
1479 script. The board configuration file may make use of this variable to
1480 configure things like a ``reset init'' script, or other things
1481 specific to that board and that target.
1482 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1483 @code{_TARGETNAME1}, ... etc.
1486 @subsection The reset-init Event Handler
1487 @cindex event, reset-init
1488 @cindex reset-init handler
1490 Board config files run in the OpenOCD configuration stage;
1491 they can't use TAPs or targets, since they haven't been
1493 This means you can't write memory or access chip registers;
1494 you can't even verify that a flash chip is present.
1495 That's done later in event handlers, of which the target @code{reset-init}
1496 handler is one of the most important.
1498 Except on microcontrollers, the basic job of @code{reset-init} event
1499 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1500 Microcontrollers rarely use boot loaders; they run right out of their
1501 on-chip flash and SRAM memory. But they may want to use one of these
1502 handlers too, if just for developer convenience.
1505 Because this is so very board-specific, and chip-specific, no examples
1507 Instead, look at the board config files distributed with OpenOCD.
1508 If you have a boot loader, its source code will help; so will
1509 configuration files for other JTAG tools
1510 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1513 Some of this code could probably be shared between different boards.
1514 For example, setting up a DRAM controller often doesn't differ by
1515 much except the bus width (16 bits or 32?) and memory timings, so a
1516 reusable TCL procedure loaded by the @file{target.cfg} file might take
1517 those as parameters.
1518 Similarly with oscillator, PLL, and clock setup;
1519 and disabling the watchdog.
1520 Structure the code cleanly, and provide comments to help
1521 the next developer doing such work.
1522 (@emph{You might be that next person} trying to reuse init code!)
1524 The last thing normally done in a @code{reset-init} handler is probing
1525 whatever flash memory was configured. For most chips that needs to be
1526 done while the associated target is halted, either because JTAG memory
1527 access uses the CPU or to prevent conflicting CPU access.
1529 @subsection JTAG Clock Rate
1531 Before your @code{reset-init} handler has set up
1532 the PLLs and clocking, you may need to run with
1533 a low JTAG clock rate.
1534 @xref{jtagspeed,,JTAG Speed}.
1535 Then you'd increase that rate after your handler has
1536 made it possible to use the faster JTAG clock.
1537 When the initial low speed is board-specific, for example
1538 because it depends on a board-specific oscillator speed, then
1539 you should probably set it up in the board config file;
1540 if it's target-specific, it belongs in the target config file.
1542 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1543 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1544 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1545 Consult chip documentation to determine the peak JTAG clock rate,
1546 which might be less than that.
1549 On most ARMs, JTAG clock detection is coupled to the core clock, so
1550 software using a @option{wait for interrupt} operation blocks JTAG access.
1551 Adaptive clocking provides a partial workaround, but a more complete
1552 solution just avoids using that instruction with JTAG debuggers.
1555 If both the chip and the board support adaptive clocking,
1556 use the @command{jtag_rclk}
1557 command, in case your board is used with JTAG adapter which
1558 also supports it. Otherwise use @command{adapter_khz}.
1559 Set the slow rate at the beginning of the reset sequence,
1560 and the faster rate as soon as the clocks are at full speed.
1562 @anchor{theinitboardprocedure}
1563 @subsection The init_board procedure
1564 @cindex init_board procedure
1566 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1567 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1568 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1569 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1570 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1571 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1572 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1573 Additionally ``linear'' board config file will most likely fail when target config file uses
1574 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1575 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1576 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1577 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1579 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1580 the original), allowing greater code reuse.
1583 ### board_file.cfg ###
1585 # source target file that does most of the config in init_targets
1586 source [find target/target.cfg]
1588 proc enable_fast_clock @{@} @{
1589 # enables fast on-board clock source
1590 # configures the chip to use it
1593 # initialize only board specifics - reset, clock, adapter frequency
1594 proc init_board @{@} @{
1595 reset_config trst_and_srst trst_pulls_srst
1597 $_TARGETNAME configure -event reset-init @{
1605 @section Target Config Files
1606 @cindex config file, target
1607 @cindex target config file
1609 Board config files communicate with target config files using
1610 naming conventions as described above, and may source one or
1611 more target config files like this:
1614 source [find target/FOOBAR.cfg]
1617 The point of a target config file is to package everything
1618 about a given chip that board config files need to know.
1619 In summary the target files should contain
1623 @item Add TAPs to the scan chain
1624 @item Add CPU targets (includes GDB support)
1625 @item CPU/Chip/CPU-Core specific features
1629 As a rule of thumb, a target file sets up only one chip.
1630 For a microcontroller, that will often include a single TAP,
1631 which is a CPU needing a GDB target, and its on-chip flash.
1633 More complex chips may include multiple TAPs, and the target
1634 config file may need to define them all before OpenOCD
1635 can talk to the chip.
1636 For example, some phone chips have JTAG scan chains that include
1637 an ARM core for operating system use, a DSP,
1638 another ARM core embedded in an image processing engine,
1639 and other processing engines.
1641 @subsection Default Value Boiler Plate Code
1643 All target configuration files should start with code like this,
1644 letting board config files express environment-specific
1645 differences in how things should be set up.
1648 # Boards may override chip names, perhaps based on role,
1649 # but the default should match what the vendor uses
1650 if @{ [info exists CHIPNAME] @} @{
1651 set _CHIPNAME $CHIPNAME
1653 set _CHIPNAME sam7x256
1656 # ONLY use ENDIAN with targets that can change it.
1657 if @{ [info exists ENDIAN] @} @{
1663 # TAP identifiers may change as chips mature, for example with
1664 # new revision fields (the "3" here). Pick a good default; you
1665 # can pass several such identifiers to the "jtag newtap" command.
1666 if @{ [info exists CPUTAPID ] @} @{
1667 set _CPUTAPID $CPUTAPID
1669 set _CPUTAPID 0x3f0f0f0f
1672 @c but 0x3f0f0f0f is for an str73x part ...
1674 @emph{Remember:} Board config files may include multiple target
1675 config files, or the same target file multiple times
1676 (changing at least @code{CHIPNAME}).
1678 Likewise, the target configuration file should define
1679 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1680 use it later on when defining debug targets:
1683 set _TARGETNAME $_CHIPNAME.cpu
1684 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1687 @subsection Adding TAPs to the Scan Chain
1688 After the ``defaults'' are set up,
1689 add the TAPs on each chip to the JTAG scan chain.
1690 @xref{TAP Declaration}, and the naming convention
1693 In the simplest case the chip has only one TAP,
1694 probably for a CPU or FPGA.
1695 The config file for the Atmel AT91SAM7X256
1696 looks (in part) like this:
1699 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1702 A board with two such at91sam7 chips would be able
1703 to source such a config file twice, with different
1704 values for @code{CHIPNAME}, so
1705 it adds a different TAP each time.
1707 If there are nonzero @option{-expected-id} values,
1708 OpenOCD attempts to verify the actual tap id against those values.
1709 It will issue error messages if there is mismatch, which
1710 can help to pinpoint problems in OpenOCD configurations.
1713 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1714 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1715 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1716 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1717 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1720 There are more complex examples too, with chips that have
1721 multiple TAPs. Ones worth looking at include:
1724 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1725 plus a JRC to enable them
1726 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1727 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1728 is not currently used)
1731 @subsection Add CPU targets
1733 After adding a TAP for a CPU, you should set it up so that
1734 GDB and other commands can use it.
1735 @xref{CPU Configuration}.
1736 For the at91sam7 example above, the command can look like this;
1737 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1738 to little endian, and this chip doesn't support changing that.
1741 set _TARGETNAME $_CHIPNAME.cpu
1742 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1745 Work areas are small RAM areas associated with CPU targets.
1746 They are used by OpenOCD to speed up downloads,
1747 and to download small snippets of code to program flash chips.
1748 If the chip includes a form of ``on-chip-ram'' - and many do - define
1749 a work area if you can.
1750 Again using the at91sam7 as an example, this can look like:
1753 $_TARGETNAME configure -work-area-phys 0x00200000 \
1754 -work-area-size 0x4000 -work-area-backup 0
1757 @anchor{definecputargetsworkinginsmp}
1758 @subsection Define CPU targets working in SMP
1760 After setting targets, you can define a list of targets working in SMP.
1763 set _TARGETNAME_1 $_CHIPNAME.cpu1
1764 set _TARGETNAME_2 $_CHIPNAME.cpu2
1765 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1766 -coreid 0 -dbgbase $_DAP_DBG1
1767 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1768 -coreid 1 -dbgbase $_DAP_DBG2
1769 #define 2 targets working in smp.
1770 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1772 In the above example on cortex_a, 2 cpus are working in SMP.
1773 In SMP only one GDB instance is created and :
1775 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1776 @item halt command triggers the halt of all targets in the list.
1777 @item resume command triggers the write context and the restart of all targets in the list.
1778 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1779 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1780 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1783 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1784 command have been implemented.
1786 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1787 @item cortex_a smp_off : disable SMP mode, the current target is the one
1788 displayed in the GDB session, only this target is now controlled by GDB
1789 session. This behaviour is useful during system boot up.
1790 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1797 #0 : coreid 0 is displayed to GDB ,
1798 #-> -1 : next resume triggers a real resume
1799 > cortex_a smp_gdb 1
1801 #0 :coreid 0 is displayed to GDB ,
1802 #->1 : next resume displays coreid 1 to GDB
1806 #1 :coreid 1 is displayed to GDB ,
1807 #->1 : next resume displays coreid 1 to GDB
1808 > cortex_a smp_gdb -1
1810 #1 :coreid 1 is displayed to GDB,
1811 #->-1 : next resume triggers a real resume
1815 @subsection Chip Reset Setup
1817 As a rule, you should put the @command{reset_config} command
1818 into the board file. Most things you think you know about a
1819 chip can be tweaked by the board.
1821 Some chips have specific ways the TRST and SRST signals are
1822 managed. In the unusual case that these are @emph{chip specific}
1823 and can never be changed by board wiring, they could go here.
1824 For example, some chips can't support JTAG debugging without
1827 Provide a @code{reset-assert} event handler if you can.
1828 Such a handler uses JTAG operations to reset the target,
1829 letting this target config be used in systems which don't
1830 provide the optional SRST signal, or on systems where you
1831 don't want to reset all targets at once.
1832 Such a handler might write to chip registers to force a reset,
1833 use a JRC to do that (preferable -- the target may be wedged!),
1834 or force a watchdog timer to trigger.
1835 (For Cortex-M targets, this is not necessary. The target
1836 driver knows how to use trigger an NVIC reset when SRST is
1839 Some chips need special attention during reset handling if
1840 they're going to be used with JTAG.
1841 An example might be needing to send some commands right
1842 after the target's TAP has been reset, providing a
1843 @code{reset-deassert-post} event handler that writes a chip
1844 register to report that JTAG debugging is being done.
1845 Another would be reconfiguring the watchdog so that it stops
1846 counting while the core is halted in the debugger.
1848 JTAG clocking constraints often change during reset, and in
1849 some cases target config files (rather than board config files)
1850 are the right places to handle some of those issues.
1851 For example, immediately after reset most chips run using a
1852 slower clock than they will use later.
1853 That means that after reset (and potentially, as OpenOCD
1854 first starts up) they must use a slower JTAG clock rate
1855 than they will use later.
1856 @xref{jtagspeed,,JTAG Speed}.
1858 @quotation Important
1859 When you are debugging code that runs right after chip
1860 reset, getting these issues right is critical.
1861 In particular, if you see intermittent failures when
1862 OpenOCD verifies the scan chain after reset,
1863 look at how you are setting up JTAG clocking.
1866 @anchor{theinittargetsprocedure}
1867 @subsection The init_targets procedure
1868 @cindex init_targets procedure
1870 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1871 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1872 procedure called @code{init_targets}, which will be executed when entering run stage
1873 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1874 Such procedure can be overriden by ``next level'' script (which sources the original).
1875 This concept faciliates code reuse when basic target config files provide generic configuration
1876 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1877 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1878 because sourcing them executes every initialization commands they provide.
1881 ### generic_file.cfg ###
1883 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1884 # basic initialization procedure ...
1887 proc init_targets @{@} @{
1888 # initializes generic chip with 4kB of flash and 1kB of RAM
1889 setup_my_chip MY_GENERIC_CHIP 4096 1024
1892 ### specific_file.cfg ###
1894 source [find target/generic_file.cfg]
1896 proc init_targets @{@} @{
1897 # initializes specific chip with 128kB of flash and 64kB of RAM
1898 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1902 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1903 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1905 For an example of this scheme see LPC2000 target config files.
1907 The @code{init_boards} procedure is a similar concept concerning board config files
1908 (@xref{theinitboardprocedure,,The init_board procedure}.)
1910 @anchor{theinittargeteventsprocedure}
1911 @subsection The init_target_events procedure
1912 @cindex init_target_events procedure
1914 A special procedure called @code{init_target_events} is run just after
1915 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1916 procedure}.) and before @code{init_board}
1917 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1918 to set up default target events for the targets that do not have those
1919 events already assigned.
1921 @subsection ARM Core Specific Hacks
1923 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1924 special high speed download features - enable it.
1926 If present, the MMU, the MPU and the CACHE should be disabled.
1928 Some ARM cores are equipped with trace support, which permits
1929 examination of the instruction and data bus activity. Trace
1930 activity is controlled through an ``Embedded Trace Module'' (ETM)
1931 on one of the core's scan chains. The ETM emits voluminous data
1932 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1933 If you are using an external trace port,
1934 configure it in your board config file.
1935 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1936 configure it in your target config file.
1939 etm config $_TARGETNAME 16 normal full etb
1940 etb config $_TARGETNAME $_CHIPNAME.etb
1943 @subsection Internal Flash Configuration
1945 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1947 @b{Never ever} in the ``target configuration file'' define any type of
1948 flash that is external to the chip. (For example a BOOT flash on
1949 Chip Select 0.) Such flash information goes in a board file - not
1950 the TARGET (chip) file.
1954 @item at91sam7x256 - has 256K flash YES enable it.
1955 @item str912 - has flash internal YES enable it.
1956 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1957 @item pxa270 - again - CS0 flash - it goes in the board file.
1960 @anchor{translatingconfigurationfiles}
1961 @section Translating Configuration Files
1963 If you have a configuration file for another hardware debugger
1964 or toolset (Abatron, BDI2000, BDI3000, CCS,
1965 Lauterbach, SEGGER, Macraigor, etc.), translating
1966 it into OpenOCD syntax is often quite straightforward. The most tricky
1967 part of creating a configuration script is oftentimes the reset init
1968 sequence where e.g. PLLs, DRAM and the like is set up.
1970 One trick that you can use when translating is to write small
1971 Tcl procedures to translate the syntax into OpenOCD syntax. This
1972 can avoid manual translation errors and make it easier to
1973 convert other scripts later on.
1975 Example of transforming quirky arguments to a simple search and
1979 # Lauterbach syntax(?)
1981 # Data.Set c15:0x042f %long 0x40000015
1983 # OpenOCD syntax when using procedure below.
1985 # setc15 0x01 0x00050078
1987 proc setc15 @{regs value@} @{
1990 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1992 arm mcr 15 [expr ($regs>>12)&0x7] \
1993 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1994 [expr ($regs>>8)&0x7] $value
2000 @node Server Configuration
2001 @chapter Server Configuration
2002 @cindex initialization
2003 The commands here are commonly found in the openocd.cfg file and are
2004 used to specify what TCP/IP ports are used, and how GDB should be
2007 @anchor{configurationstage}
2008 @section Configuration Stage
2009 @cindex configuration stage
2010 @cindex config command
2012 When the OpenOCD server process starts up, it enters a
2013 @emph{configuration stage} which is the only time that
2014 certain commands, @emph{configuration commands}, may be issued.
2015 Normally, configuration commands are only available
2016 inside startup scripts.
2018 In this manual, the definition of a configuration command is
2019 presented as a @emph{Config Command}, not as a @emph{Command}
2020 which may be issued interactively.
2021 The runtime @command{help} command also highlights configuration
2022 commands, and those which may be issued at any time.
2024 Those configuration commands include declaration of TAPs,
2026 the interface used for JTAG communication,
2027 and other basic setup.
2028 The server must leave the configuration stage before it
2029 may access or activate TAPs.
2030 After it leaves this stage, configuration commands may no
2033 @anchor{enteringtherunstage}
2034 @section Entering the Run Stage
2036 The first thing OpenOCD does after leaving the configuration
2037 stage is to verify that it can talk to the scan chain
2038 (list of TAPs) which has been configured.
2039 It will warn if it doesn't find TAPs it expects to find,
2040 or finds TAPs that aren't supposed to be there.
2041 You should see no errors at this point.
2042 If you see errors, resolve them by correcting the
2043 commands you used to configure the server.
2044 Common errors include using an initial JTAG speed that's too
2045 fast, and not providing the right IDCODE values for the TAPs
2048 Once OpenOCD has entered the run stage, a number of commands
2050 A number of these relate to the debug targets you may have declared.
2051 For example, the @command{mww} command will not be available until
2052 a target has been successfuly instantiated.
2053 If you want to use those commands, you may need to force
2054 entry to the run stage.
2056 @deffn {Config Command} init
2057 This command terminates the configuration stage and
2058 enters the run stage. This helps when you need to have
2059 the startup scripts manage tasks such as resetting the target,
2060 programming flash, etc. To reset the CPU upon startup, add "init" and
2061 "reset" at the end of the config script or at the end of the OpenOCD
2062 command line using the @option{-c} command line switch.
2064 If this command does not appear in any startup/configuration file
2065 OpenOCD executes the command for you after processing all
2066 configuration files and/or command line options.
2068 @b{NOTE:} This command normally occurs at or near the end of your
2069 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2070 targets ready. For example: If your openocd.cfg file needs to
2071 read/write memory on your target, @command{init} must occur before
2072 the memory read/write commands. This includes @command{nand probe}.
2075 @deffn {Overridable Procedure} jtag_init
2076 This is invoked at server startup to verify that it can talk
2077 to the scan chain (list of TAPs) which has been configured.
2079 The default implementation first tries @command{jtag arp_init},
2080 which uses only a lightweight JTAG reset before examining the
2082 If that fails, it tries again, using a harder reset
2083 from the overridable procedure @command{init_reset}.
2085 Implementations must have verified the JTAG scan chain before
2087 This is done by calling @command{jtag arp_init}
2088 (or @command{jtag arp_init-reset}).
2092 @section TCP/IP Ports
2097 The OpenOCD server accepts remote commands in several syntaxes.
2098 Each syntax uses a different TCP/IP port, which you may specify
2099 only during configuration (before those ports are opened).
2101 For reasons including security, you may wish to prevent remote
2102 access using one or more of these ports.
2103 In such cases, just specify the relevant port number as "disabled".
2104 If you disable all access through TCP/IP, you will need to
2105 use the command line @option{-pipe} option.
2107 @deffn {Command} gdb_port [number]
2109 Normally gdb listens to a TCP/IP port, but GDB can also
2110 communicate via pipes(stdin/out or named pipes). The name
2111 "gdb_port" stuck because it covers probably more than 90% of
2112 the normal use cases.
2114 No arguments reports GDB port. "pipe" means listen to stdin
2115 output to stdout, an integer is base port number, "disabled"
2116 disables the gdb server.
2118 When using "pipe", also use log_output to redirect the log
2119 output to a file so as not to flood the stdin/out pipes.
2121 The -p/--pipe option is deprecated and a warning is printed
2122 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2124 Any other string is interpreted as named pipe to listen to.
2125 Output pipe is the same name as input pipe, but with 'o' appended,
2126 e.g. /var/gdb, /var/gdbo.
2128 The GDB port for the first target will be the base port, the
2129 second target will listen on gdb_port + 1, and so on.
2130 When not specified during the configuration stage,
2131 the port @var{number} defaults to 3333.
2133 Note: when using "gdb_port pipe", increasing the default remote timeout in
2134 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2135 cause initialization to fail with "Unknown remote qXfer reply: OK".
2139 @deffn {Command} tcl_port [number]
2140 Specify or query the port used for a simplified RPC
2141 connection that can be used by clients to issue TCL commands and get the
2142 output from the Tcl engine.
2143 Intended as a machine interface.
2144 When not specified during the configuration stage,
2145 the port @var{number} defaults to 6666.
2146 When specified as "disabled", this service is not activated.
2149 @deffn {Command} telnet_port [number]
2150 Specify or query the
2151 port on which to listen for incoming telnet connections.
2152 This port is intended for interaction with one human through TCL commands.
2153 When not specified during the configuration stage,
2154 the port @var{number} defaults to 4444.
2155 When specified as "disabled", this service is not activated.
2158 @anchor{gdbconfiguration}
2159 @section GDB Configuration
2161 @cindex GDB configuration
2162 You can reconfigure some GDB behaviors if needed.
2163 The ones listed here are static and global.
2164 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2165 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2167 @anchor{gdbbreakpointoverride}
2168 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2169 Force breakpoint type for gdb @command{break} commands.
2170 This option supports GDB GUIs which don't
2171 distinguish hard versus soft breakpoints, if the default OpenOCD and
2172 GDB behaviour is not sufficient. GDB normally uses hardware
2173 breakpoints if the memory map has been set up for flash regions.
2176 @anchor{gdbflashprogram}
2177 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2178 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2179 vFlash packet is received.
2180 The default behaviour is @option{enable}.
2183 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2184 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2185 requested. GDB will then know when to set hardware breakpoints, and program flash
2186 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2187 for flash programming to work.
2188 Default behaviour is @option{enable}.
2189 @xref{gdbflashprogram,,gdb_flash_program}.
2192 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2193 Specifies whether data aborts cause an error to be reported
2194 by GDB memory read packets.
2195 The default behaviour is @option{disable};
2196 use @option{enable} see these errors reported.
2199 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2200 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2201 The default behaviour is @option{enable}.
2204 @deffn {Command} gdb_save_tdesc
2205 Saves the target descripton file to the local file system.
2207 The file name is @i{target_name}.xml.
2210 @anchor{eventpolling}
2211 @section Event Polling
2213 Hardware debuggers are parts of asynchronous systems,
2214 where significant events can happen at any time.
2215 The OpenOCD server needs to detect some of these events,
2216 so it can report them to through TCL command line
2219 Examples of such events include:
2222 @item One of the targets can stop running ... maybe it triggers
2223 a code breakpoint or data watchpoint, or halts itself.
2224 @item Messages may be sent over ``debug message'' channels ... many
2225 targets support such messages sent over JTAG,
2226 for receipt by the person debugging or tools.
2227 @item Loss of power ... some adapters can detect these events.
2228 @item Resets not issued through JTAG ... such reset sources
2229 can include button presses or other system hardware, sometimes
2230 including the target itself (perhaps through a watchdog).
2231 @item Debug instrumentation sometimes supports event triggering
2232 such as ``trace buffer full'' (so it can quickly be emptied)
2233 or other signals (to correlate with code behavior).
2236 None of those events are signaled through standard JTAG signals.
2237 However, most conventions for JTAG connectors include voltage
2238 level and system reset (SRST) signal detection.
2239 Some connectors also include instrumentation signals, which
2240 can imply events when those signals are inputs.
2242 In general, OpenOCD needs to periodically check for those events,
2243 either by looking at the status of signals on the JTAG connector
2244 or by sending synchronous ``tell me your status'' JTAG requests
2245 to the various active targets.
2246 There is a command to manage and monitor that polling,
2247 which is normally done in the background.
2249 @deffn Command poll [@option{on}|@option{off}]
2250 Poll the current target for its current state.
2251 (Also, @pxref{targetcurstate,,target curstate}.)
2252 If that target is in debug mode, architecture
2253 specific information about the current state is printed.
2254 An optional parameter
2255 allows background polling to be enabled and disabled.
2257 You could use this from the TCL command shell, or
2258 from GDB using @command{monitor poll} command.
2259 Leave background polling enabled while you're using GDB.
2262 background polling: on
2263 target state: halted
2264 target halted in ARM state due to debug-request, \
2265 current mode: Supervisor
2266 cpsr: 0x800000d3 pc: 0x11081bfc
2267 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2272 @node Debug Adapter Configuration
2273 @chapter Debug Adapter Configuration
2274 @cindex config file, interface
2275 @cindex interface config file
2277 Correctly installing OpenOCD includes making your operating system give
2278 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2279 are used to select which one is used, and to configure how it is used.
2282 Because OpenOCD started out with a focus purely on JTAG, you may find
2283 places where it wrongly presumes JTAG is the only transport protocol
2284 in use. Be aware that recent versions of OpenOCD are removing that
2285 limitation. JTAG remains more functional than most other transports.
2286 Other transports do not support boundary scan operations, or may be
2287 specific to a given chip vendor. Some might be usable only for
2288 programming flash memory, instead of also for debugging.
2291 Debug Adapters/Interfaces/Dongles are normally configured
2292 through commands in an interface configuration
2293 file which is sourced by your @file{openocd.cfg} file, or
2294 through a command line @option{-f interface/....cfg} option.
2297 source [find interface/olimex-jtag-tiny.cfg]
2301 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2302 A few cases are so simple that you only need to say what driver to use:
2309 Most adapters need a bit more configuration than that.
2312 @section Interface Configuration
2314 The interface command tells OpenOCD what type of debug adapter you are
2315 using. Depending on the type of adapter, you may need to use one or
2316 more additional commands to further identify or configure the adapter.
2318 @deffn {Config Command} {interface} name
2319 Use the interface driver @var{name} to connect to the
2323 @deffn Command {interface_list}
2324 List the debug adapter drivers that have been built into
2325 the running copy of OpenOCD.
2327 @deffn Command {interface transports} transport_name+
2328 Specifies the transports supported by this debug adapter.
2329 The adapter driver builds-in similar knowledge; use this only
2330 when external configuration (such as jumpering) changes what
2331 the hardware can support.
2336 @deffn Command {adapter_name}
2337 Returns the name of the debug adapter driver being used.
2340 @section Interface Drivers
2342 Each of the interface drivers listed here must be explicitly
2343 enabled when OpenOCD is configured, in order to be made
2344 available at run time.
2346 @deffn {Interface Driver} {amt_jtagaccel}
2347 Amontec Chameleon in its JTAG Accelerator configuration,
2348 connected to a PC's EPP mode parallel port.
2349 This defines some driver-specific commands:
2351 @deffn {Config Command} {parport_port} number
2352 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2353 the number of the @file{/dev/parport} device.
2356 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2357 Displays status of RTCK option.
2358 Optionally sets that option first.
2362 @deffn {Interface Driver} {arm-jtag-ew}
2363 Olimex ARM-JTAG-EW USB adapter
2364 This has one driver-specific command:
2366 @deffn Command {armjtagew_info}
2371 @deffn {Interface Driver} {at91rm9200}
2372 Supports bitbanged JTAG from the local system,
2373 presuming that system is an Atmel AT91rm9200
2374 and a specific set of GPIOs is used.
2375 @c command: at91rm9200_device NAME
2376 @c chooses among list of bit configs ... only one option
2379 @deffn {Interface Driver} {cmsis-dap}
2380 ARM CMSIS-DAP compliant based adapter.
2382 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2383 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2384 the driver will attempt to auto detect the CMSIS-DAP device.
2385 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2387 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2391 @deffn {Config Command} {cmsis_dap_serial} [serial]
2392 Specifies the @var{serial} of the CMSIS-DAP device to use.
2393 If not specified, serial numbers are not considered.
2396 @deffn {Command} {cmsis-dap info}
2397 Display various device information, like hardware version, firmware version, current bus status.
2401 @deffn {Interface Driver} {dummy}
2402 A dummy software-only driver for debugging.
2405 @deffn {Interface Driver} {ep93xx}
2406 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2409 @deffn {Interface Driver} {ftdi}
2410 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2411 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2413 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2414 bypassing intermediate libraries like libftdi or D2XX.
2416 Support for new FTDI based adapters can be added competely through
2417 configuration files, without the need to patch and rebuild OpenOCD.
2419 The driver uses a signal abstraction to enable Tcl configuration files to
2420 define outputs for one or several FTDI GPIO. These outputs can then be
2421 controlled using the @command{ftdi_set_signal} command. Special signal names
2422 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2423 will be used for their customary purpose. Inputs can be read using the
2424 @command{ftdi_get_signal} command.
2426 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2427 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2428 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2429 required by the protocol, to tell the adapter to drive the data output onto
2430 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2432 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2433 be controlled differently. In order to support tristateable signals such as
2434 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2435 signal. The following output buffer configurations are supported:
2438 @item Push-pull with one FTDI output as (non-)inverted data line
2439 @item Open drain with one FTDI output as (non-)inverted output-enable
2440 @item Tristate with one FTDI output as (non-)inverted data line and another
2441 FTDI output as (non-)inverted output-enable
2442 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2443 switching data and direction as necessary
2446 These interfaces have several commands, used to configure the driver
2447 before initializing the JTAG scan chain:
2449 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2450 The vendor ID and product ID of the adapter. Up to eight
2451 [@var{vid}, @var{pid}] pairs may be given, e.g.
2453 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2457 @deffn {Config Command} {ftdi_device_desc} description
2458 Provides the USB device description (the @emph{iProduct string})
2459 of the adapter. If not specified, the device description is ignored
2460 during device selection.
2463 @deffn {Config Command} {ftdi_serial} serial-number
2464 Specifies the @var{serial-number} of the adapter to use,
2465 in case the vendor provides unique IDs and more than one adapter
2466 is connected to the host.
2467 If not specified, serial numbers are not considered.
2468 (Note that USB serial numbers can be arbitrary Unicode strings,
2469 and are not restricted to containing only decimal digits.)
2472 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2473 Specifies the physical USB port of the adapter to use. The path
2474 roots at @var{bus} and walks down the physical ports, with each
2475 @var{port} option specifying a deeper level in the bus topology, the last
2476 @var{port} denoting where the target adapter is actually plugged.
2477 The USB bus topology can be queried with the command @emph{lsusb -t}.
2479 This command is only available if your libusb1 is at least version 1.0.16.
2482 @deffn {Config Command} {ftdi_channel} channel
2483 Selects the channel of the FTDI device to use for MPSSE operations. Most
2484 adapters use the default, channel 0, but there are exceptions.
2487 @deffn {Config Command} {ftdi_layout_init} data direction
2488 Specifies the initial values of the FTDI GPIO data and direction registers.
2489 Each value is a 16-bit number corresponding to the concatenation of the high
2490 and low FTDI GPIO registers. The values should be selected based on the
2491 schematics of the adapter, such that all signals are set to safe levels with
2492 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2493 and initially asserted reset signals.
2496 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2497 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2498 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2499 register bitmasks to tell the driver the connection and type of the output
2500 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2501 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2502 used with inverting data inputs and @option{-data} with non-inverting inputs.
2503 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2504 not-output-enable) input to the output buffer is connected. The options
2505 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2506 with the method @command{ftdi_get_signal}.
2508 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2509 simple open-collector transistor driver would be specified with @option{-oe}
2510 only. In that case the signal can only be set to drive low or to Hi-Z and the
2511 driver will complain if the signal is set to drive high. Which means that if
2512 it's a reset signal, @command{reset_config} must be specified as
2513 @option{srst_open_drain}, not @option{srst_push_pull}.
2515 A special case is provided when @option{-data} and @option{-oe} is set to the
2516 same bitmask. Then the FTDI pin is considered being connected straight to the
2517 target without any buffer. The FTDI pin is then switched between output and
2518 input as necessary to provide the full set of low, high and Hi-Z
2519 characteristics. In all other cases, the pins specified in a signal definition
2520 are always driven by the FTDI.
2522 If @option{-alias} or @option{-nalias} is used, the signal is created
2523 identical (or with data inverted) to an already specified signal
2527 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2528 Set a previously defined signal to the specified level.
2530 @item @option{0}, drive low
2531 @item @option{1}, drive high
2532 @item @option{z}, set to high-impedance
2536 @deffn {Command} {ftdi_get_signal} name
2537 Get the value of a previously defined signal.
2540 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2541 Configure TCK edge at which the adapter samples the value of the TDO signal
2543 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2544 peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
2545 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2546 stability at higher JTAG clocks.
2548 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2549 @item @option{falling}, sample TDO on falling edge of TCK
2553 For example adapter definitions, see the configuration files shipped in the
2554 @file{interface/ftdi} directory.
2558 @deffn {Interface Driver} {remote_bitbang}
2559 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2560 with a remote process and sends ASCII encoded bitbang requests to that process
2561 instead of directly driving JTAG.
2563 The remote_bitbang driver is useful for debugging software running on
2564 processors which are being simulated.
2566 @deffn {Config Command} {remote_bitbang_port} number
2567 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2568 sockets instead of TCP.
2571 @deffn {Config Command} {remote_bitbang_host} hostname
2572 Specifies the hostname of the remote process to connect to using TCP, or the
2573 name of the UNIX socket to use if remote_bitbang_port is 0.
2576 For example, to connect remotely via TCP to the host foobar you might have
2580 interface remote_bitbang
2581 remote_bitbang_port 3335
2582 remote_bitbang_host foobar
2585 To connect to another process running locally via UNIX sockets with socket
2589 interface remote_bitbang
2590 remote_bitbang_port 0
2591 remote_bitbang_host mysocket
2595 @deffn {Interface Driver} {usb_blaster}
2596 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2597 for FTDI chips. These interfaces have several commands, used to
2598 configure the driver before initializing the JTAG scan chain:
2600 @deffn {Config Command} {usb_blaster_device_desc} description
2601 Provides the USB device description (the @emph{iProduct string})
2602 of the FTDI FT245 device. If not
2603 specified, the FTDI default value is used. This setting is only valid
2604 if compiled with FTD2XX support.
2607 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2608 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2609 default values are used.
2610 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2611 Altera USB-Blaster (default):
2613 usb_blaster_vid_pid 0x09FB 0x6001
2615 The following VID/PID is for Kolja Waschk's USB JTAG:
2617 usb_blaster_vid_pid 0x16C0 0x06AD
2621 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2622 Sets the state or function of the unused GPIO pins on USB-Blasters
2623 (pins 6 and 8 on the female JTAG header). These pins can be used as
2624 SRST and/or TRST provided the appropriate connections are made on the
2627 For example, to use pin 6 as SRST:
2629 usb_blaster_pin pin6 s
2630 reset_config srst_only
2634 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2635 Chooses the low level access method for the adapter. If not specified,
2636 @option{ftdi} is selected unless it wasn't enabled during the
2637 configure stage. USB-Blaster II needs @option{ublast2}.
2640 @deffn {Command} {usb_blaster_firmware} @var{path}
2641 This command specifies @var{path} to access USB-Blaster II firmware
2642 image. To be used with USB-Blaster II only.
2647 @deffn {Interface Driver} {gw16012}
2648 Gateworks GW16012 JTAG programmer.
2649 This has one driver-specific command:
2651 @deffn {Config Command} {parport_port} [port_number]
2652 Display either the address of the I/O port
2653 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2654 If a parameter is provided, first switch to use that port.
2655 This is a write-once setting.
2659 @deffn {Interface Driver} {jlink}
2660 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2663 @quotation Compatibility Note
2664 SEGGER released many firmware versions for the many harware versions they
2665 produced. OpenOCD was extensively tested and intended to run on all of them,
2666 but some combinations were reported as incompatible. As a general
2667 recommendation, it is advisable to use the latest firmware version
2668 available for each hardware version. However the current V8 is a moving
2669 target, and SEGGER firmware versions released after the OpenOCD was
2670 released may not be compatible. In such cases it is recommended to
2671 revert to the last known functional version. For 0.5.0, this is from
2672 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2673 version is from "May 3 2012 18:36:22", packed with 4.46f.
2676 @deffn {Command} {jlink hwstatus}
2677 Display various hardware related information, for example target voltage and pin
2680 @deffn {Command} {jlink freemem}
2681 Display free device internal memory.
2683 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2684 Set the JTAG command version to be used. Without argument, show the actual JTAG
2687 @deffn {Command} {jlink config}
2688 Display the device configuration.
2690 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2691 Set the target power state on JTAG-pin 19. Without argument, show the target
2694 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2695 Set the MAC address of the device. Without argument, show the MAC address.
2697 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2698 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2699 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2702 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2703 Set the USB address of the device. This will also change the USB Product ID
2704 (PID) of the device. Without argument, show the USB address.
2706 @deffn {Command} {jlink config reset}
2707 Reset the current configuration.
2709 @deffn {Command} {jlink config write}
2710 Write the current configuration to the internal persistent storage.
2712 @deffn {Command} {jlink emucom write <channel> <data>}
2713 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2716 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2717 the EMUCOM channel 0x10:
2719 > jlink emucom write 0x10 aa0b23
2722 @deffn {Command} {jlink emucom read <channel> <length>}
2723 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2726 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2728 > jlink emucom read 0x0 4
2732 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2733 Set the USB address of the interface, in case more than one adapter is connected
2734 to the host. If not specified, USB addresses are not considered. Device
2735 selection via USB address is deprecated and the serial number should be used
2738 As a configuration command, it can be used only before 'init'.
2740 @deffn {Config} {jlink serial} <serial number>
2741 Set the serial number of the interface, in case more than one adapter is
2742 connected to the host. If not specified, serial numbers are not considered.
2744 As a configuration command, it can be used only before 'init'.
2748 @deffn {Interface Driver} {kitprog}
2749 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2750 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2751 families, but it is possible to use it with some other devices. If you are using
2752 this adapter with a PSoC or a PRoC, you may need to add
2753 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2754 configuration script.
2756 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2757 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2758 be used with this driver, and must either be used with the cmsis-dap driver or
2759 switched back to KitProg mode. See the Cypress KitProg User Guide for
2760 instructions on how to switch KitProg modes.
2764 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2766 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2767 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2768 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2769 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2770 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2771 SWD sequence must be sent after every target reset in order to re-establish
2772 communications with the target.
2773 @item Due in part to the limitation above, KitProg devices with firmware below
2774 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2775 communicate with PSoC 5LP devices. This is because, assuming debug is not
2776 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2777 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2778 could only be sent with an acquisition sequence.
2781 @deffn {Config Command} {kitprog_init_acquire_psoc}
2782 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2783 Please be aware that the acquisition sequence hard-resets the target.
2786 @deffn {Config Command} {kitprog_serial} serial
2787 Select a KitProg device by its @var{serial}. If left unspecified, the first
2788 device detected by OpenOCD will be used.
2791 @deffn {Command} {kitprog acquire_psoc}
2792 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2793 outside of the target-specific configuration scripts since it hard-resets the
2794 target as a side-effect.
2795 This is necessary for "reset halt" on some PSoC 4 series devices.
2798 @deffn {Command} {kitprog info}
2799 Display various adapter information, such as the hardware version, firmware
2800 version, and target voltage.
2804 @deffn {Interface Driver} {parport}
2805 Supports PC parallel port bit-banging cables:
2806 Wigglers, PLD download cable, and more.
2807 These interfaces have several commands, used to configure the driver
2808 before initializing the JTAG scan chain:
2810 @deffn {Config Command} {parport_cable} name
2811 Set the layout of the parallel port cable used to connect to the target.
2812 This is a write-once setting.
2813 Currently valid cable @var{name} values include:
2816 @item @b{altium} Altium Universal JTAG cable.
2817 @item @b{arm-jtag} Same as original wiggler except SRST and
2818 TRST connections reversed and TRST is also inverted.
2819 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2820 in configuration mode. This is only used to
2821 program the Chameleon itself, not a connected target.
2822 @item @b{dlc5} The Xilinx Parallel cable III.
2823 @item @b{flashlink} The ST Parallel cable.
2824 @item @b{lattice} Lattice ispDOWNLOAD Cable
2825 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2827 Amontec's Chameleon Programmer. The new version available from
2828 the website uses the original Wiggler layout ('@var{wiggler}')
2829 @item @b{triton} The parallel port adapter found on the
2830 ``Karo Triton 1 Development Board''.
2831 This is also the layout used by the HollyGates design
2832 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2833 @item @b{wiggler} The original Wiggler layout, also supported by
2834 several clones, such as the Olimex ARM-JTAG
2835 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2836 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2840 @deffn {Config Command} {parport_port} [port_number]
2841 Display either the address of the I/O port
2842 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2843 If a parameter is provided, first switch to use that port.
2844 This is a write-once setting.
2846 When using PPDEV to access the parallel port, use the number of the parallel port:
2847 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2848 you may encounter a problem.
2851 @deffn Command {parport_toggling_time} [nanoseconds]
2852 Displays how many nanoseconds the hardware needs to toggle TCK;
2853 the parport driver uses this value to obey the
2854 @command{adapter_khz} configuration.
2855 When the optional @var{nanoseconds} parameter is given,
2856 that setting is changed before displaying the current value.
2858 The default setting should work reasonably well on commodity PC hardware.
2859 However, you may want to calibrate for your specific hardware.
2861 To measure the toggling time with a logic analyzer or a digital storage
2862 oscilloscope, follow the procedure below:
2864 > parport_toggling_time 1000
2867 This sets the maximum JTAG clock speed of the hardware, but
2868 the actual speed probably deviates from the requested 500 kHz.
2869 Now, measure the time between the two closest spaced TCK transitions.
2870 You can use @command{runtest 1000} or something similar to generate a
2871 large set of samples.
2872 Update the setting to match your measurement:
2874 > parport_toggling_time <measured nanoseconds>
2876 Now the clock speed will be a better match for @command{adapter_khz rate}
2877 commands given in OpenOCD scripts and event handlers.
2879 You can do something similar with many digital multimeters, but note
2880 that you'll probably need to run the clock continuously for several
2881 seconds before it decides what clock rate to show. Adjust the
2882 toggling time up or down until the measured clock rate is a good
2883 match for the adapter_khz rate you specified; be conservative.
2887 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2888 This will configure the parallel driver to write a known
2889 cable-specific value to the parallel interface on exiting OpenOCD.
2892 For example, the interface configuration file for a
2893 classic ``Wiggler'' cable on LPT2 might look something like this:
2898 parport_cable wiggler
2902 @deffn {Interface Driver} {presto}
2903 ASIX PRESTO USB JTAG programmer.
2904 @deffn {Config Command} {presto_serial} serial_string
2905 Configures the USB serial number of the Presto device to use.
2909 @deffn {Interface Driver} {rlink}
2910 Raisonance RLink USB adapter
2913 @deffn {Interface Driver} {usbprog}
2914 usbprog is a freely programmable USB adapter.
2917 @deffn {Interface Driver} {vsllink}
2918 vsllink is part of Versaloon which is a versatile USB programmer.
2921 This defines quite a few driver-specific commands,
2922 which are not currently documented here.
2926 @anchor{hla_interface}
2927 @deffn {Interface Driver} {hla}
2928 This is a driver that supports multiple High Level Adapters.
2929 This type of adapter does not expose some of the lower level api's
2930 that OpenOCD would normally use to access the target.
2932 Currently supported adapters include the ST STLINK and TI ICDI.
2933 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2934 versions of firmware where serial number is reset after first use. Suggest
2935 using ST firmware update utility to upgrade STLINK firmware even if current
2936 version reported is V2.J21.S4.
2938 @deffn {Config Command} {hla_device_desc} description
2939 Currently Not Supported.
2942 @deffn {Config Command} {hla_serial} serial
2943 Specifies the serial number of the adapter.
2946 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2947 Specifies the adapter layout to use.
2950 @deffn {Config Command} {hla_vid_pid} vid pid
2951 The vendor ID and product ID of the device.
2954 @deffn {Command} {hla_command} command
2955 Execute a custom adapter-specific command. The @var{command} string is
2956 passed as is to the underlying adapter layout handler.
2960 @deffn {Interface Driver} {opendous}
2961 opendous-jtag is a freely programmable USB adapter.
2964 @deffn {Interface Driver} {ulink}
2965 This is the Keil ULINK v1 JTAG debugger.
2968 @deffn {Interface Driver} {ZY1000}
2969 This is the Zylin ZY1000 JTAG debugger.
2973 This defines some driver-specific commands,
2974 which are not currently documented here.
2977 @deffn Command power [@option{on}|@option{off}]
2978 Turn power switch to target on/off.
2979 No arguments: print status.
2982 @deffn {Interface Driver} {bcm2835gpio}
2983 This SoC is present in Raspberry Pi which is a cheap single-board computer
2984 exposing some GPIOs on its expansion header.
2986 The driver accesses memory-mapped GPIO peripheral registers directly
2987 for maximum performance, but the only possible race condition is for
2988 the pins' modes/muxing (which is highly unlikely), so it should be
2989 able to coexist nicely with both sysfs bitbanging and various
2990 peripherals' kernel drivers. The driver restores the previous
2991 configuration on exit.
2993 See @file{interface/raspberrypi-native.cfg} for a sample config and
2998 @deffn {Interface Driver} {imx_gpio}
2999 i.MX SoC is present in many community boards. Wandboard is an example
3000 of the one which is most popular.
3002 This driver is mostly the same as bcm2835gpio.
3004 See @file{interface/imx-native.cfg} for a sample config and
3010 @deffn {Interface Driver} {openjtag}
3011 OpenJTAG compatible USB adapter.
3012 This defines some driver-specific commands:
3014 @deffn {Config Command} {openjtag_variant} variant
3015 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3016 Currently valid @var{variant} values include:
3019 @item @b{standard} Standard variant (default).
3020 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3021 (see @uref{http://www.cypress.com/?rID=82870}).
3025 @deffn {Config Command} {openjtag_device_desc} string
3026 The USB device description string of the adapter.
3027 This value is only used with the standard variant.
3031 @section Transport Configuration
3033 As noted earlier, depending on the version of OpenOCD you use,
3034 and the debug adapter you are using,
3035 several transports may be available to
3036 communicate with debug targets (or perhaps to program flash memory).
3037 @deffn Command {transport list}
3038 displays the names of the transports supported by this
3042 @deffn Command {transport select} @option{transport_name}
3043 Select which of the supported transports to use in this OpenOCD session.
3045 When invoked with @option{transport_name}, attempts to select the named
3046 transport. The transport must be supported by the debug adapter
3047 hardware and by the version of OpenOCD you are using (including the
3050 If no transport has been selected and no @option{transport_name} is
3051 provided, @command{transport select} auto-selects the first transport
3052 supported by the debug adapter.
3054 @command{transport select} always returns the name of the session's selected
3058 @subsection JTAG Transport
3060 JTAG is the original transport supported by OpenOCD, and most
3061 of the OpenOCD commands support it.
3062 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3063 each of which must be explicitly declared.
3064 JTAG supports both debugging and boundary scan testing.
3065 Flash programming support is built on top of debug support.
3067 JTAG transport is selected with the command @command{transport select
3068 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3069 driver}, in which case the command is @command{transport select
3072 @subsection SWD Transport
3074 @cindex Serial Wire Debug
3075 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3076 Debug Access Point (DAP, which must be explicitly declared.
3077 (SWD uses fewer signal wires than JTAG.)
3078 SWD is debug-oriented, and does not support boundary scan testing.
3079 Flash programming support is built on top of debug support.
3080 (Some processors support both JTAG and SWD.)
3082 SWD transport is selected with the command @command{transport select
3083 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3084 driver}, in which case the command is @command{transport select
3087 @deffn Command {swd newdap} ...
3088 Declares a single DAP which uses SWD transport.
3089 Parameters are currently the same as "jtag newtap" but this is
3092 @deffn Command {swd wcr trn prescale}
3093 Updates TRN (turnaraound delay) and prescaling.fields of the
3094 Wire Control Register (WCR).
3095 No parameters: displays current settings.
3098 @subsection SPI Transport
3100 @cindex Serial Peripheral Interface
3101 The Serial Peripheral Interface (SPI) is a general purpose transport
3102 which uses four wire signaling. Some processors use it as part of a
3103 solution for flash programming.
3107 JTAG clock setup is part of system setup.
3108 It @emph{does not belong with interface setup} since any interface
3109 only knows a few of the constraints for the JTAG clock speed.
3110 Sometimes the JTAG speed is
3111 changed during the target initialization process: (1) slow at
3112 reset, (2) program the CPU clocks, (3) run fast.
3113 Both the "slow" and "fast" clock rates are functions of the
3114 oscillators used, the chip, the board design, and sometimes
3115 power management software that may be active.
3117 The speed used during reset, and the scan chain verification which
3118 follows reset, can be adjusted using a @code{reset-start}
3119 target event handler.
3120 It can then be reconfigured to a faster speed by a
3121 @code{reset-init} target event handler after it reprograms those
3122 CPU clocks, or manually (if something else, such as a boot loader,
3123 sets up those clocks).
3124 @xref{targetevents,,Target Events}.
3125 When the initial low JTAG speed is a chip characteristic, perhaps
3126 because of a required oscillator speed, provide such a handler
3127 in the target config file.
3128 When that speed is a function of a board-specific characteristic
3129 such as which speed oscillator is used, it belongs in the board
3130 config file instead.
3131 In both cases it's safest to also set the initial JTAG clock rate
3132 to that same slow speed, so that OpenOCD never starts up using a
3133 clock speed that's faster than the scan chain can support.
3137 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3140 If your system supports adaptive clocking (RTCK), configuring
3141 JTAG to use that is probably the most robust approach.
3142 However, it introduces delays to synchronize clocks; so it
3143 may not be the fastest solution.
3145 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3146 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3147 which support adaptive clocking.
3149 @deffn {Command} adapter_khz max_speed_kHz
3150 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3151 JTAG interfaces usually support a limited number of
3152 speeds. The speed actually used won't be faster
3153 than the speed specified.
3155 Chip data sheets generally include a top JTAG clock rate.
3156 The actual rate is often a function of a CPU core clock,
3157 and is normally less than that peak rate.
3158 For example, most ARM cores accept at most one sixth of the CPU clock.
3160 Speed 0 (khz) selects RTCK method.
3161 @xref{faqrtck,,FAQ RTCK}.
3162 If your system uses RTCK, you won't need to change the
3163 JTAG clocking after setup.
3164 Not all interfaces, boards, or targets support ``rtck''.
3165 If the interface device can not
3166 support it, an error is returned when you try to use RTCK.
3169 @defun jtag_rclk fallback_speed_kHz
3170 @cindex adaptive clocking
3172 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3173 If that fails (maybe the interface, board, or target doesn't
3174 support it), falls back to the specified frequency.
3176 # Fall back to 3mhz if RTCK is not supported
3181 @node Reset Configuration
3182 @chapter Reset Configuration
3183 @cindex Reset Configuration
3185 Every system configuration may require a different reset
3186 configuration. This can also be quite confusing.
3187 Resets also interact with @var{reset-init} event handlers,
3188 which do things like setting up clocks and DRAM, and
3189 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3190 They can also interact with JTAG routers.
3191 Please see the various board files for examples.
3194 To maintainers and integrators:
3195 Reset configuration touches several things at once.
3196 Normally the board configuration file
3197 should define it and assume that the JTAG adapter supports
3198 everything that's wired up to the board's JTAG connector.
3200 However, the target configuration file could also make note
3201 of something the silicon vendor has done inside the chip,
3202 which will be true for most (or all) boards using that chip.
3203 And when the JTAG adapter doesn't support everything, the
3204 user configuration file will need to override parts of
3205 the reset configuration provided by other files.
3208 @section Types of Reset
3210 There are many kinds of reset possible through JTAG, but
3211 they may not all work with a given board and adapter.
3212 That's part of why reset configuration can be error prone.
3216 @emph{System Reset} ... the @emph{SRST} hardware signal
3217 resets all chips connected to the JTAG adapter, such as processors,
3218 power management chips, and I/O controllers. Normally resets triggered
3219 with this signal behave exactly like pressing a RESET button.
3221 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3222 just the TAP controllers connected to the JTAG adapter.
3223 Such resets should not be visible to the rest of the system; resetting a
3224 device's TAP controller just puts that controller into a known state.
3226 @emph{Emulation Reset} ... many devices can be reset through JTAG
3227 commands. These resets are often distinguishable from system
3228 resets, either explicitly (a "reset reason" register says so)
3229 or implicitly (not all parts of the chip get reset).
3231 @emph{Other Resets} ... system-on-chip devices often support
3232 several other types of reset.
3233 You may need to arrange that a watchdog timer stops
3234 while debugging, preventing a watchdog reset.
3235 There may be individual module resets.
3238 In the best case, OpenOCD can hold SRST, then reset
3239 the TAPs via TRST and send commands through JTAG to halt the
3240 CPU at the reset vector before the 1st instruction is executed.
3241 Then when it finally releases the SRST signal, the system is
3242 halted under debugger control before any code has executed.
3243 This is the behavior required to support the @command{reset halt}
3244 and @command{reset init} commands; after @command{reset init} a
3245 board-specific script might do things like setting up DRAM.
3246 (@xref{resetcommand,,Reset Command}.)
3248 @anchor{srstandtrstissues}
3249 @section SRST and TRST Issues
3251 Because SRST and TRST are hardware signals, they can have a
3252 variety of system-specific constraints. Some of the most
3257 @item @emph{Signal not available} ... Some boards don't wire
3258 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3259 support such signals even if they are wired up.
3260 Use the @command{reset_config} @var{signals} options to say
3261 when either of those signals is not connected.
3262 When SRST is not available, your code might not be able to rely
3263 on controllers having been fully reset during code startup.
3264 Missing TRST is not a problem, since JTAG-level resets can
3265 be triggered using with TMS signaling.
3267 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3268 adapter will connect SRST to TRST, instead of keeping them separate.
3269 Use the @command{reset_config} @var{combination} options to say
3270 when those signals aren't properly independent.
3272 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3273 delay circuit, reset supervisor, or on-chip features can extend
3274 the effect of a JTAG adapter's reset for some time after the adapter
3275 stops issuing the reset. For example, there may be chip or board
3276 requirements that all reset pulses last for at least a
3277 certain amount of time; and reset buttons commonly have
3278 hardware debouncing.
3279 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3280 commands to say when extra delays are needed.
3282 @item @emph{Drive type} ... Reset lines often have a pullup
3283 resistor, letting the JTAG interface treat them as open-drain
3284 signals. But that's not a requirement, so the adapter may need
3285 to use push/pull output drivers.
3286 Also, with weak pullups it may be advisable to drive
3287 signals to both levels (push/pull) to minimize rise times.
3288 Use the @command{reset_config} @var{trst_type} and
3289 @var{srst_type} parameters to say how to drive reset signals.
3291 @item @emph{Special initialization} ... Targets sometimes need
3292 special JTAG initialization sequences to handle chip-specific
3293 issues (not limited to errata).
3294 For example, certain JTAG commands might need to be issued while
3295 the system as a whole is in a reset state (SRST active)
3296 but the JTAG scan chain is usable (TRST inactive).
3297 Many systems treat combined assertion of SRST and TRST as a
3298 trigger for a harder reset than SRST alone.
3299 Such custom reset handling is discussed later in this chapter.
3302 There can also be other issues.
3303 Some devices don't fully conform to the JTAG specifications.
3304 Trivial system-specific differences are common, such as
3305 SRST and TRST using slightly different names.
3306 There are also vendors who distribute key JTAG documentation for
3307 their chips only to developers who have signed a Non-Disclosure
3310 Sometimes there are chip-specific extensions like a requirement to use
3311 the normally-optional TRST signal (precluding use of JTAG adapters which
3312 don't pass TRST through), or needing extra steps to complete a TAP reset.
3314 In short, SRST and especially TRST handling may be very finicky,
3315 needing to cope with both architecture and board specific constraints.
3317 @section Commands for Handling Resets
3319 @deffn {Command} adapter_nsrst_assert_width milliseconds
3320 Minimum amount of time (in milliseconds) OpenOCD should wait
3321 after asserting nSRST (active-low system reset) before
3322 allowing it to be deasserted.
3325 @deffn {Command} adapter_nsrst_delay milliseconds
3326 How long (in milliseconds) OpenOCD should wait after deasserting
3327 nSRST (active-low system reset) before starting new JTAG operations.
3328 When a board has a reset button connected to SRST line it will
3329 probably have hardware debouncing, implying you should use this.
3332 @deffn {Command} jtag_ntrst_assert_width milliseconds
3333 Minimum amount of time (in milliseconds) OpenOCD should wait
3334 after asserting nTRST (active-low JTAG TAP reset) before
3335 allowing it to be deasserted.
3338 @deffn {Command} jtag_ntrst_delay milliseconds
3339 How long (in milliseconds) OpenOCD should wait after deasserting
3340 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3343 @deffn {Command} reset_config mode_flag ...
3344 This command displays or modifies the reset configuration
3345 of your combination of JTAG board and target in target
3346 configuration scripts.
3348 Information earlier in this section describes the kind of problems
3349 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3350 As a rule this command belongs only in board config files,
3351 describing issues like @emph{board doesn't connect TRST};
3352 or in user config files, addressing limitations derived
3353 from a particular combination of interface and board.
3354 (An unlikely example would be using a TRST-only adapter
3355 with a board that only wires up SRST.)
3357 The @var{mode_flag} options can be specified in any order, but only one
3358 of each type -- @var{signals}, @var{combination}, @var{gates},
3359 @var{trst_type}, @var{srst_type} and @var{connect_type}
3360 -- may be specified at a time.
3361 If you don't provide a new value for a given type, its previous
3362 value (perhaps the default) is unchanged.
3363 For example, this means that you don't need to say anything at all about
3364 TRST just to declare that if the JTAG adapter should want to drive SRST,
3365 it must explicitly be driven high (@option{srst_push_pull}).
3369 @var{signals} can specify which of the reset signals are connected.
3370 For example, If the JTAG interface provides SRST, but the board doesn't
3371 connect that signal properly, then OpenOCD can't use it.
3372 Possible values are @option{none} (the default), @option{trst_only},
3373 @option{srst_only} and @option{trst_and_srst}.
3376 If your board provides SRST and/or TRST through the JTAG connector,
3377 you must declare that so those signals can be used.
3381 The @var{combination} is an optional value specifying broken reset
3382 signal implementations.
3383 The default behaviour if no option given is @option{separate},
3384 indicating everything behaves normally.
3385 @option{srst_pulls_trst} states that the
3386 test logic is reset together with the reset of the system (e.g. NXP
3387 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3388 the system is reset together with the test logic (only hypothetical, I
3389 haven't seen hardware with such a bug, and can be worked around).
3390 @option{combined} implies both @option{srst_pulls_trst} and
3391 @option{trst_pulls_srst}.
3394 The @var{gates} tokens control flags that describe some cases where
3395 JTAG may be unvailable during reset.
3396 @option{srst_gates_jtag} (default)
3397 indicates that asserting SRST gates the
3398 JTAG clock. This means that no communication can happen on JTAG
3399 while SRST is asserted.
3400 Its converse is @option{srst_nogate}, indicating that JTAG commands
3401 can safely be issued while SRST is active.
3404 The @var{connect_type} tokens control flags that describe some cases where
3405 SRST is asserted while connecting to the target. @option{srst_nogate}
3406 is required to use this option.
3407 @option{connect_deassert_srst} (default)
3408 indicates that SRST will not be asserted while connecting to the target.
3409 Its converse is @option{connect_assert_srst}, indicating that SRST will
3410 be asserted before any target connection.
3411 Only some targets support this feature, STM32 and STR9 are examples.
3412 This feature is useful if you are unable to connect to your target due
3413 to incorrect options byte config or illegal program execution.
3416 The optional @var{trst_type} and @var{srst_type} parameters allow the
3417 driver mode of each reset line to be specified. These values only affect
3418 JTAG interfaces with support for different driver modes, like the Amontec
3419 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3420 relevant signal (TRST or SRST) is not connected.
3424 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3425 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3426 Most boards connect this signal to a pulldown, so the JTAG TAPs
3427 never leave reset unless they are hooked up to a JTAG adapter.
3430 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3431 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3432 Most boards connect this signal to a pullup, and allow the
3433 signal to be pulled low by various events including system
3434 powerup and pressing a reset button.
3438 @section Custom Reset Handling
3441 OpenOCD has several ways to help support the various reset
3442 mechanisms provided by chip and board vendors.
3443 The commands shown in the previous section give standard parameters.
3444 There are also @emph{event handlers} associated with TAPs or Targets.
3445 Those handlers are Tcl procedures you can provide, which are invoked
3446 at particular points in the reset sequence.
3448 @emph{When SRST is not an option} you must set
3449 up a @code{reset-assert} event handler for your target.
3450 For example, some JTAG adapters don't include the SRST signal;
3451 and some boards have multiple targets, and you won't always
3452 want to reset everything at once.
3454 After configuring those mechanisms, you might still
3455 find your board doesn't start up or reset correctly.
3456 For example, maybe it needs a slightly different sequence
3457 of SRST and/or TRST manipulations, because of quirks that
3458 the @command{reset_config} mechanism doesn't address;
3459 or asserting both might trigger a stronger reset, which
3460 needs special attention.
3462 Experiment with lower level operations, such as @command{jtag_reset}
3463 and the @command{jtag arp_*} operations shown here,
3464 to find a sequence of operations that works.
3465 @xref{JTAG Commands}.
3466 When you find a working sequence, it can be used to override
3467 @command{jtag_init}, which fires during OpenOCD startup
3468 (@pxref{configurationstage,,Configuration Stage});
3469 or @command{init_reset}, which fires during reset processing.
3471 You might also want to provide some project-specific reset
3472 schemes. For example, on a multi-target board the standard
3473 @command{reset} command would reset all targets, but you
3474 may need the ability to reset only one target at time and
3475 thus want to avoid using the board-wide SRST signal.
3477 @deffn {Overridable Procedure} init_reset mode
3478 This is invoked near the beginning of the @command{reset} command,
3479 usually to provide as much of a cold (power-up) reset as practical.
3480 By default it is also invoked from @command{jtag_init} if
3481 the scan chain does not respond to pure JTAG operations.
3482 The @var{mode} parameter is the parameter given to the
3483 low level reset command (@option{halt},
3484 @option{init}, or @option{run}), @option{setup},
3485 or potentially some other value.
3487 The default implementation just invokes @command{jtag arp_init-reset}.
3488 Replacements will normally build on low level JTAG
3489 operations such as @command{jtag_reset}.
3490 Operations here must not address individual TAPs
3491 (or their associated targets)
3492 until the JTAG scan chain has first been verified to work.
3494 Implementations must have verified the JTAG scan chain before
3496 This is done by calling @command{jtag arp_init}
3497 (or @command{jtag arp_init-reset}).
3500 @deffn Command {jtag arp_init}
3501 This validates the scan chain using just the four
3502 standard JTAG signals (TMS, TCK, TDI, TDO).
3503 It starts by issuing a JTAG-only reset.
3504 Then it performs checks to verify that the scan chain configuration
3505 matches the TAPs it can observe.
3506 Those checks include checking IDCODE values for each active TAP,
3507 and verifying the length of their instruction registers using
3508 TAP @code{-ircapture} and @code{-irmask} values.
3509 If these tests all pass, TAP @code{setup} events are
3510 issued to all TAPs with handlers for that event.
3513 @deffn Command {jtag arp_init-reset}
3514 This uses TRST and SRST to try resetting
3515 everything on the JTAG scan chain
3516 (and anything else connected to SRST).
3517 It then invokes the logic of @command{jtag arp_init}.
3521 @node TAP Declaration
3522 @chapter TAP Declaration
3523 @cindex TAP declaration
3524 @cindex TAP configuration
3526 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3527 TAPs serve many roles, including:
3530 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3531 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3532 Others do it indirectly, making a CPU do it.
3533 @item @b{Program Download} Using the same CPU support GDB uses,
3534 you can initialize a DRAM controller, download code to DRAM, and then
3535 start running that code.
3536 @item @b{Boundary Scan} Most chips support boundary scan, which
3537 helps test for board assembly problems like solder bridges
3538 and missing connections.
3541 OpenOCD must know about the active TAPs on your board(s).
3542 Setting up the TAPs is the core task of your configuration files.
3543 Once those TAPs are set up, you can pass their names to code
3544 which sets up CPUs and exports them as GDB targets,
3545 probes flash memory, performs low-level JTAG operations, and more.
3547 @section Scan Chains
3550 TAPs are part of a hardware @dfn{scan chain},
3551 which is a daisy chain of TAPs.
3552 They also need to be added to
3553 OpenOCD's software mirror of that hardware list,
3554 giving each member a name and associating other data with it.
3555 Simple scan chains, with a single TAP, are common in
3556 systems with a single microcontroller or microprocessor.
3557 More complex chips may have several TAPs internally.
3558 Very complex scan chains might have a dozen or more TAPs:
3559 several in one chip, more in the next, and connecting
3560 to other boards with their own chips and TAPs.
3562 You can display the list with the @command{scan_chain} command.
3563 (Don't confuse this with the list displayed by the @command{targets}
3564 command, presented in the next chapter.
3565 That only displays TAPs for CPUs which are configured as
3567 Here's what the scan chain might look like for a chip more than one TAP:
3570 TapName Enabled IdCode Expected IrLen IrCap IrMask
3571 -- ------------------ ------- ---------- ---------- ----- ----- ------
3572 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3573 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3574 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3577 OpenOCD can detect some of that information, but not all
3578 of it. @xref{autoprobing,,Autoprobing}.
3579 Unfortunately, those TAPs can't always be autoconfigured,
3580 because not all devices provide good support for that.
3581 JTAG doesn't require supporting IDCODE instructions, and
3582 chips with JTAG routers may not link TAPs into the chain
3583 until they are told to do so.
3585 The configuration mechanism currently supported by OpenOCD
3586 requires explicit configuration of all TAP devices using
3587 @command{jtag newtap} commands, as detailed later in this chapter.
3588 A command like this would declare one tap and name it @code{chip1.cpu}:
3591 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3594 Each target configuration file lists the TAPs provided
3596 Board configuration files combine all the targets on a board,
3598 Note that @emph{the order in which TAPs are declared is very important.}
3599 That declaration order must match the order in the JTAG scan chain,
3600 both inside a single chip and between them.
3601 @xref{faqtaporder,,FAQ TAP Order}.
3603 For example, the ST Microsystems STR912 chip has
3604 three separate TAPs@footnote{See the ST
3605 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3606 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3607 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3608 To configure those taps, @file{target/str912.cfg}
3609 includes commands something like this:
3612 jtag newtap str912 flash ... params ...
3613 jtag newtap str912 cpu ... params ...
3614 jtag newtap str912 bs ... params ...
3617 Actual config files typically use a variable such as @code{$_CHIPNAME}
3618 instead of literals like @option{str912}, to support more than one chip
3619 of each type. @xref{Config File Guidelines}.
3621 @deffn Command {jtag names}
3622 Returns the names of all current TAPs in the scan chain.
3623 Use @command{jtag cget} or @command{jtag tapisenabled}
3624 to examine attributes and state of each TAP.
3626 foreach t [jtag names] @{
3627 puts [format "TAP: %s\n" $t]
3632 @deffn Command {scan_chain}
3633 Displays the TAPs in the scan chain configuration,
3635 The set of TAPs listed by this command is fixed by
3636 exiting the OpenOCD configuration stage,
3637 but systems with a JTAG router can
3638 enable or disable TAPs dynamically.
3641 @c FIXME! "jtag cget" should be able to return all TAP
3642 @c attributes, like "$target_name cget" does for targets.
3644 @c Probably want "jtag eventlist", and a "tap-reset" event
3645 @c (on entry to RESET state).
3650 When TAP objects are declared with @command{jtag newtap},
3651 a @dfn{dotted.name} is created for the TAP, combining the
3652 name of a module (usually a chip) and a label for the TAP.
3653 For example: @code{xilinx.tap}, @code{str912.flash},
3654 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3655 Many other commands use that dotted.name to manipulate or
3656 refer to the TAP. For example, CPU configuration uses the
3657 name, as does declaration of NAND or NOR flash banks.
3659 The components of a dotted name should follow ``C'' symbol
3660 name rules: start with an alphabetic character, then numbers
3661 and underscores are OK; while others (including dots!) are not.
3663 @section TAP Declaration Commands
3665 @c shouldn't this be(come) a {Config Command}?
3666 @deffn Command {jtag newtap} chipname tapname configparams...
3667 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3668 and configured according to the various @var{configparams}.
3670 The @var{chipname} is a symbolic name for the chip.
3671 Conventionally target config files use @code{$_CHIPNAME},
3672 defaulting to the model name given by the chip vendor but
3675 @cindex TAP naming convention
3676 The @var{tapname} reflects the role of that TAP,
3677 and should follow this convention:
3680 @item @code{bs} -- For boundary scan if this is a separate TAP;
3681 @item @code{cpu} -- The main CPU of the chip, alternatively
3682 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3683 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3684 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3685 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3686 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3687 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3688 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3690 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3691 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3692 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3693 a JTAG TAP; that TAP should be named @code{sdma}.
3696 Every TAP requires at least the following @var{configparams}:
3699 @item @code{-irlen} @var{NUMBER}
3700 @*The length in bits of the
3701 instruction register, such as 4 or 5 bits.
3704 A TAP may also provide optional @var{configparams}:
3707 @item @code{-disable} (or @code{-enable})
3708 @*Use the @code{-disable} parameter to flag a TAP which is not
3709 linked into the scan chain after a reset using either TRST
3710 or the JTAG state machine's @sc{reset} state.
3711 You may use @code{-enable} to highlight the default state
3712 (the TAP is linked in).
3713 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3714 @item @code{-expected-id} @var{NUMBER}
3715 @*A non-zero @var{number} represents a 32-bit IDCODE
3716 which you expect to find when the scan chain is examined.
3717 These codes are not required by all JTAG devices.
3718 @emph{Repeat the option} as many times as required if more than one
3719 ID code could appear (for example, multiple versions).
3720 Specify @var{number} as zero to suppress warnings about IDCODE
3721 values that were found but not included in the list.
3723 Provide this value if at all possible, since it lets OpenOCD
3724 tell when the scan chain it sees isn't right. These values
3725 are provided in vendors' chip documentation, usually a technical
3726 reference manual. Sometimes you may need to probe the JTAG
3727 hardware to find these values.
3728 @xref{autoprobing,,Autoprobing}.
3729 @item @code{-ignore-version}
3730 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3731 option. When vendors put out multiple versions of a chip, or use the same
3732 JTAG-level ID for several largely-compatible chips, it may be more practical
3733 to ignore the version field than to update config files to handle all of
3734 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3735 @item @code{-ircapture} @var{NUMBER}
3736 @*The bit pattern loaded by the TAP into the JTAG shift register
3737 on entry to the @sc{ircapture} state, such as 0x01.
3738 JTAG requires the two LSBs of this value to be 01.
3739 By default, @code{-ircapture} and @code{-irmask} are set
3740 up to verify that two-bit value. You may provide
3741 additional bits if you know them, or indicate that
3742 a TAP doesn't conform to the JTAG specification.
3743 @item @code{-irmask} @var{NUMBER}
3744 @*A mask used with @code{-ircapture}
3745 to verify that instruction scans work correctly.
3746 Such scans are not used by OpenOCD except to verify that
3747 there seems to be no problems with JTAG scan chain operations.
3751 @section Other TAP commands
3753 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3754 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3755 At this writing this TAP attribute
3756 mechanism is used only for event handling.
3757 (It is not a direct analogue of the @code{cget}/@code{configure}
3758 mechanism for debugger targets.)
3759 See the next section for information about the available events.
3761 The @code{configure} subcommand assigns an event handler,
3762 a TCL string which is evaluated when the event is triggered.
3763 The @code{cget} subcommand returns that handler.
3770 OpenOCD includes two event mechanisms.
3771 The one presented here applies to all JTAG TAPs.
3772 The other applies to debugger targets,
3773 which are associated with certain TAPs.
3775 The TAP events currently defined are:
3778 @item @b{post-reset}
3779 @* The TAP has just completed a JTAG reset.
3780 The tap may still be in the JTAG @sc{reset} state.
3781 Handlers for these events might perform initialization sequences
3782 such as issuing TCK cycles, TMS sequences to ensure
3783 exit from the ARM SWD mode, and more.
3785 Because the scan chain has not yet been verified, handlers for these events
3786 @emph{should not issue commands which scan the JTAG IR or DR registers}
3787 of any particular target.
3788 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3790 @* The scan chain has been reset and verified.
3791 This handler may enable TAPs as needed.
3792 @item @b{tap-disable}
3793 @* The TAP needs to be disabled. This handler should
3794 implement @command{jtag tapdisable}
3795 by issuing the relevant JTAG commands.
3796 @item @b{tap-enable}
3797 @* The TAP needs to be enabled. This handler should
3798 implement @command{jtag tapenable}
3799 by issuing the relevant JTAG commands.
3802 If you need some action after each JTAG reset which isn't actually
3803 specific to any TAP (since you can't yet trust the scan chain's
3804 contents to be accurate), you might:
3807 jtag configure CHIP.jrc -event post-reset @{
3808 echo "JTAG Reset done"
3809 ... non-scan jtag operations to be done after reset
3814 @anchor{enablinganddisablingtaps}
3815 @section Enabling and Disabling TAPs
3816 @cindex JTAG Route Controller
3819 In some systems, a @dfn{JTAG Route Controller} (JRC)
3820 is used to enable and/or disable specific JTAG TAPs.
3821 Many ARM-based chips from Texas Instruments include
3822 an ``ICEPick'' module, which is a JRC.
3823 Such chips include DaVinci and OMAP3 processors.
3825 A given TAP may not be visible until the JRC has been
3826 told to link it into the scan chain; and if the JRC
3827 has been told to unlink that TAP, it will no longer
3829 Such routers address problems that JTAG ``bypass mode''
3833 @item The scan chain can only go as fast as its slowest TAP.
3834 @item Having many TAPs slows instruction scans, since all
3835 TAPs receive new instructions.
3836 @item TAPs in the scan chain must be powered up, which wastes
3837 power and prevents debugging some power management mechanisms.
3840 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3841 as implied by the existence of JTAG routers.
3842 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3843 does include a kind of JTAG router functionality.
3845 @c (a) currently the event handlers don't seem to be able to
3846 @c fail in a way that could lead to no-change-of-state.
3848 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3849 shown below, and is implemented using TAP event handlers.
3850 So for example, when defining a TAP for a CPU connected to
3851 a JTAG router, your @file{target.cfg} file
3852 should define TAP event handlers using
3853 code that looks something like this:
3856 jtag configure CHIP.cpu -event tap-enable @{
3857 ... jtag operations using CHIP.jrc
3859 jtag configure CHIP.cpu -event tap-disable @{
3860 ... jtag operations using CHIP.jrc
3864 Then you might want that CPU's TAP enabled almost all the time:
3867 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3870 Note how that particular setup event handler declaration
3871 uses quotes to evaluate @code{$CHIP} when the event is configured.
3872 Using brackets @{ @} would cause it to be evaluated later,
3873 at runtime, when it might have a different value.
3875 @deffn Command {jtag tapdisable} dotted.name
3876 If necessary, disables the tap
3877 by sending it a @option{tap-disable} event.
3878 Returns the string "1" if the tap
3879 specified by @var{dotted.name} is enabled,
3880 and "0" if it is disabled.
3883 @deffn Command {jtag tapenable} dotted.name
3884 If necessary, enables the tap
3885 by sending it a @option{tap-enable} event.
3886 Returns the string "1" if the tap
3887 specified by @var{dotted.name} is enabled,
3888 and "0" if it is disabled.
3891 @deffn Command {jtag tapisenabled} dotted.name
3892 Returns the string "1" if the tap
3893 specified by @var{dotted.name} is enabled,
3894 and "0" if it is disabled.
3897 Humans will find the @command{scan_chain} command more helpful
3898 for querying the state of the JTAG taps.
3902 @anchor{autoprobing}
3903 @section Autoprobing
3905 @cindex JTAG autoprobe
3907 TAP configuration is the first thing that needs to be done
3908 after interface and reset configuration. Sometimes it's
3909 hard finding out what TAPs exist, or how they are identified.
3910 Vendor documentation is not always easy to find and use.
3912 To help you get past such problems, OpenOCD has a limited
3913 @emph{autoprobing} ability to look at the scan chain, doing
3914 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3915 To use this mechanism, start the OpenOCD server with only data
3916 that configures your JTAG interface, and arranges to come up
3917 with a slow clock (many devices don't support fast JTAG clocks
3918 right when they come out of reset).
3920 For example, your @file{openocd.cfg} file might have:
3923 source [find interface/olimex-arm-usb-tiny-h.cfg]
3924 reset_config trst_and_srst
3928 When you start the server without any TAPs configured, it will
3929 attempt to autoconfigure the TAPs. There are two parts to this:
3932 @item @emph{TAP discovery} ...
3933 After a JTAG reset (sometimes a system reset may be needed too),
3934 each TAP's data registers will hold the contents of either the
3935 IDCODE or BYPASS register.
3936 If JTAG communication is working, OpenOCD will see each TAP,
3937 and report what @option{-expected-id} to use with it.
3938 @item @emph{IR Length discovery} ...
3939 Unfortunately JTAG does not provide a reliable way to find out
3940 the value of the @option{-irlen} parameter to use with a TAP
3942 If OpenOCD can discover the length of a TAP's instruction
3943 register, it will report it.
3944 Otherwise you may need to consult vendor documentation, such
3945 as chip data sheets or BSDL files.
3948 In many cases your board will have a simple scan chain with just
3949 a single device. Here's what OpenOCD reported with one board
3950 that's a bit more complex:
3954 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3955 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3956 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3957 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3958 AUTO auto0.tap - use "... -irlen 4"
3959 AUTO auto1.tap - use "... -irlen 4"
3960 AUTO auto2.tap - use "... -irlen 6"
3961 no gdb ports allocated as no target has been specified
3964 Given that information, you should be able to either find some existing
3965 config files to use, or create your own. If you create your own, you
3966 would configure from the bottom up: first a @file{target.cfg} file
3967 with these TAPs, any targets associated with them, and any on-chip
3968 resources; then a @file{board.cfg} with off-chip resources, clocking,
3971 @node CPU Configuration
3972 @chapter CPU Configuration
3975 This chapter discusses how to set up GDB debug targets for CPUs.
3976 You can also access these targets without GDB
3977 (@pxref{Architecture and Core Commands},
3978 and @ref{targetstatehandling,,Target State handling}) and
3979 through various kinds of NAND and NOR flash commands.
3980 If you have multiple CPUs you can have multiple such targets.
3982 We'll start by looking at how to examine the targets you have,
3983 then look at how to add one more target and how to configure it.
3985 @section Target List
3986 @cindex target, current
3987 @cindex target, list
3989 All targets that have been set up are part of a list,
3990 where each member has a name.
3991 That name should normally be the same as the TAP name.
3992 You can display the list with the @command{targets}
3994 This display often has only one CPU; here's what it might
3995 look like with more than one:
3997 TargetName Type Endian TapName State
3998 -- ------------------ ---------- ------ ------------------ ------------
3999 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4000 1 MyTarget cortex_m little mychip.foo tap-disabled
4003 One member of that list is the @dfn{current target}, which
4004 is implicitly referenced by many commands.
4005 It's the one marked with a @code{*} near the target name.
4006 In particular, memory addresses often refer to the address
4007 space seen by that current target.
4008 Commands like @command{mdw} (memory display words)
4009 and @command{flash erase_address} (erase NOR flash blocks)
4010 are examples; and there are many more.
4012 Several commands let you examine the list of targets:
4014 @deffn Command {target current}
4015 Returns the name of the current target.
4018 @deffn Command {target names}
4019 Lists the names of all current targets in the list.
4021 foreach t [target names] @{
4022 puts [format "Target: %s\n" $t]
4027 @c yep, "target list" would have been better.
4028 @c plus maybe "target setdefault".
4030 @deffn Command targets [name]
4031 @emph{Note: the name of this command is plural. Other target
4032 command names are singular.}
4034 With no parameter, this command displays a table of all known
4035 targets in a user friendly form.
4037 With a parameter, this command sets the current target to
4038 the given target with the given @var{name}; this is
4039 only relevant on boards which have more than one target.
4042 @section Target CPU Types
4046 Each target has a @dfn{CPU type}, as shown in the output of
4047 the @command{targets} command. You need to specify that type
4048 when calling @command{target create}.
4049 The CPU type indicates more than just the instruction set.
4050 It also indicates how that instruction set is implemented,
4051 what kind of debug support it integrates,
4052 whether it has an MMU (and if so, what kind),
4053 what core-specific commands may be available
4054 (@pxref{Architecture and Core Commands}),
4057 It's easy to see what target types are supported,
4058 since there's a command to list them.
4060 @anchor{targettypes}
4061 @deffn Command {target types}
4062 Lists all supported target types.
4063 At this writing, the supported CPU types are:
4066 @item @code{arm11} -- this is a generation of ARMv6 cores
4067 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4068 @item @code{arm7tdmi} -- this is an ARMv4 core
4069 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4070 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4071 @item @code{arm966e} -- this is an ARMv5 core
4072 @item @code{arm9tdmi} -- this is an ARMv4 core
4073 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4074 (Support for this is preliminary and incomplete.)
4075 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4076 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4077 compact Thumb2 instruction set.
4078 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4079 @item @code{dragonite} -- resembles arm966e
4080 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4081 (Support for this is still incomplete.)
4082 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4083 @item @code{feroceon} -- resembles arm926
4084 @item @code{mips_m4k} -- a MIPS core
4085 @item @code{xscale} -- this is actually an architecture,
4086 not a CPU type. It is based on the ARMv5 architecture.
4087 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4088 The current implementation supports three JTAG TAP cores:
4089 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4090 allowing access to physical memory addresses independently of CPU cores.
4092 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4093 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4094 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4096 And two debug interfaces cores:
4098 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4099 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4104 To avoid being confused by the variety of ARM based cores, remember
4105 this key point: @emph{ARM is a technology licencing company}.
4106 (See: @url{http://www.arm.com}.)
4107 The CPU name used by OpenOCD will reflect the CPU design that was
4108 licenced, not a vendor brand which incorporates that design.
4109 Name prefixes like arm7, arm9, arm11, and cortex
4110 reflect design generations;
4111 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4112 reflect an architecture version implemented by a CPU design.
4114 @anchor{targetconfiguration}
4115 @section Target Configuration
4117 Before creating a ``target'', you must have added its TAP to the scan chain.
4118 When you've added that TAP, you will have a @code{dotted.name}
4119 which is used to set up the CPU support.
4120 The chip-specific configuration file will normally configure its CPU(s)
4121 right after it adds all of the chip's TAPs to the scan chain.
4123 Although you can set up a target in one step, it's often clearer if you
4124 use shorter commands and do it in two steps: create it, then configure
4126 All operations on the target after it's created will use a new
4127 command, created as part of target creation.
4129 The two main things to configure after target creation are
4130 a work area, which usually has target-specific defaults even
4131 if the board setup code overrides them later;
4132 and event handlers (@pxref{targetevents,,Target Events}), which tend
4133 to be much more board-specific.
4134 The key steps you use might look something like this
4137 target create MyTarget cortex_m -chain-position mychip.cpu
4138 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4139 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4140 $MyTarget configure -event reset-init @{ myboard_reinit @}
4143 You should specify a working area if you can; typically it uses some
4145 Such a working area can speed up many things, including bulk
4146 writes to target memory;
4147 flash operations like checking to see if memory needs to be erased;
4148 GDB memory checksumming;
4152 On more complex chips, the work area can become
4153 inaccessible when application code
4154 (such as an operating system)
4155 enables or disables the MMU.
4156 For example, the particular MMU context used to acess the virtual
4157 address will probably matter ... and that context might not have
4158 easy access to other addresses needed.
4159 At this writing, OpenOCD doesn't have much MMU intelligence.
4162 It's often very useful to define a @code{reset-init} event handler.
4163 For systems that are normally used with a boot loader,
4164 common tasks include updating clocks and initializing memory
4166 That may be needed to let you write the boot loader into flash,
4167 in order to ``de-brick'' your board; or to load programs into
4168 external DDR memory without having run the boot loader.
4170 @deffn Command {target create} target_name type configparams...
4171 This command creates a GDB debug target that refers to a specific JTAG tap.
4172 It enters that target into a list, and creates a new
4173 command (@command{@var{target_name}}) which is used for various
4174 purposes including additional configuration.
4177 @item @var{target_name} ... is the name of the debug target.
4178 By convention this should be the same as the @emph{dotted.name}
4179 of the TAP associated with this target, which must be specified here
4180 using the @code{-chain-position @var{dotted.name}} configparam.
4182 This name is also used to create the target object command,
4183 referred to here as @command{$target_name},
4184 and in other places the target needs to be identified.
4185 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4186 @item @var{configparams} ... all parameters accepted by
4187 @command{$target_name configure} are permitted.
4188 If the target is big-endian, set it here with @code{-endian big}.
4190 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4194 @deffn Command {$target_name configure} configparams...
4195 The options accepted by this command may also be
4196 specified as parameters to @command{target create}.
4197 Their values can later be queried one at a time by
4198 using the @command{$target_name cget} command.
4200 @emph{Warning:} changing some of these after setup is dangerous.
4201 For example, moving a target from one TAP to another;
4202 and changing its endianness.
4206 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4207 used to access this target.
4209 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4210 whether the CPU uses big or little endian conventions
4212 @item @code{-event} @var{event_name} @var{event_body} --
4213 @xref{targetevents,,Target Events}.
4214 Note that this updates a list of named event handlers.
4215 Calling this twice with two different event names assigns
4216 two different handlers, but calling it twice with the
4217 same event name assigns only one handler.
4219 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4220 whether the work area gets backed up; by default,
4221 @emph{it is not backed up.}
4222 When possible, use a working_area that doesn't need to be backed up,
4223 since performing a backup slows down operations.
4224 For example, the beginning of an SRAM block is likely to
4225 be used by most build systems, but the end is often unused.
4227 @item @code{-work-area-size} @var{size} -- specify work are size,
4228 in bytes. The same size applies regardless of whether its physical
4229 or virtual address is being used.
4231 @item @code{-work-area-phys} @var{address} -- set the work area
4232 base @var{address} to be used when no MMU is active.
4234 @item @code{-work-area-virt} @var{address} -- set the work area
4235 base @var{address} to be used when an MMU is active.
4236 @emph{Do not specify a value for this except on targets with an MMU.}
4237 The value should normally correspond to a static mapping for the
4238 @code{-work-area-phys} address, set up by the current operating system.
4241 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4242 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4243 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4244 @option{embKernel}, @option{mqx}, @option{uCOS-III}
4245 @xref{gdbrtossupport,,RTOS Support}.
4247 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4248 scan and after a reset. A manual call to arp_examine is required to
4249 access the target for debugging.
4251 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4252 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4253 Use this option with systems where multiple, independent cores are connected
4254 to separate access ports of the same DAP.
4256 @item @code{-ctibase} @var{address} -- set base address of Cross-Trigger interface (CTI) connected
4257 to the target. Currently, only the @code{aarch64} target makes use of this option, where it is
4258 a mandatory configuration for the target run control.
4262 @section Other $target_name Commands
4263 @cindex object command
4265 The Tcl/Tk language has the concept of object commands,
4266 and OpenOCD adopts that same model for targets.
4268 A good Tk example is a on screen button.
4269 Once a button is created a button
4270 has a name (a path in Tk terms) and that name is useable as a first
4271 class command. For example in Tk, one can create a button and later
4272 configure it like this:
4276 button .foobar -background red -command @{ foo @}
4278 .foobar configure -foreground blue
4280 set x [.foobar cget -background]
4282 puts [format "The button is %s" $x]
4285 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4286 button, and its object commands are invoked the same way.
4289 str912.cpu mww 0x1234 0x42
4290 omap3530.cpu mww 0x5555 123
4293 The commands supported by OpenOCD target objects are:
4295 @deffn Command {$target_name arp_examine} @option{allow-defer}
4296 @deffnx Command {$target_name arp_halt}
4297 @deffnx Command {$target_name arp_poll}
4298 @deffnx Command {$target_name arp_reset}
4299 @deffnx Command {$target_name arp_waitstate}
4300 Internal OpenOCD scripts (most notably @file{startup.tcl})
4301 use these to deal with specific reset cases.
4302 They are not otherwise documented here.
4305 @deffn Command {$target_name array2mem} arrayname width address count
4306 @deffnx Command {$target_name mem2array} arrayname width address count
4307 These provide an efficient script-oriented interface to memory.
4308 The @code{array2mem} primitive writes bytes, halfwords, or words;
4309 while @code{mem2array} reads them.
4310 In both cases, the TCL side uses an array, and
4311 the target side uses raw memory.
4313 The efficiency comes from enabling the use of
4314 bulk JTAG data transfer operations.
4315 The script orientation comes from working with data
4316 values that are packaged for use by TCL scripts;
4317 @command{mdw} type primitives only print data they retrieve,
4318 and neither store nor return those values.
4321 @item @var{arrayname} ... is the name of an array variable
4322 @item @var{width} ... is 8/16/32 - indicating the memory access size
4323 @item @var{address} ... is the target memory address
4324 @item @var{count} ... is the number of elements to process
4328 @deffn Command {$target_name cget} queryparm
4329 Each configuration parameter accepted by
4330 @command{$target_name configure}
4331 can be individually queried, to return its current value.
4332 The @var{queryparm} is a parameter name
4333 accepted by that command, such as @code{-work-area-phys}.
4334 There are a few special cases:
4337 @item @code{-event} @var{event_name} -- returns the handler for the
4338 event named @var{event_name}.
4339 This is a special case because setting a handler requires
4341 @item @code{-type} -- returns the target type.
4342 This is a special case because this is set using
4343 @command{target create} and can't be changed
4344 using @command{$target_name configure}.
4347 For example, if you wanted to summarize information about
4348 all the targets you might use something like this:
4351 foreach name [target names] @{
4352 set y [$name cget -endian]
4353 set z [$name cget -type]
4354 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4360 @anchor{targetcurstate}
4361 @deffn Command {$target_name curstate}
4362 Displays the current target state:
4363 @code{debug-running},
4366 @code{running}, or @code{unknown}.
4367 (Also, @pxref{eventpolling,,Event Polling}.)
4370 @deffn Command {$target_name eventlist}
4371 Displays a table listing all event handlers
4372 currently associated with this target.
4373 @xref{targetevents,,Target Events}.
4376 @deffn Command {$target_name invoke-event} event_name
4377 Invokes the handler for the event named @var{event_name}.
4378 (This is primarily intended for use by OpenOCD framework
4379 code, for example by the reset code in @file{startup.tcl}.)
4382 @deffn Command {$target_name mdw} addr [count]
4383 @deffnx Command {$target_name mdh} addr [count]
4384 @deffnx Command {$target_name mdb} addr [count]
4385 Display contents of address @var{addr}, as
4386 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4387 or 8-bit bytes (@command{mdb}).
4388 If @var{count} is specified, displays that many units.
4389 (If you want to manipulate the data instead of displaying it,
4390 see the @code{mem2array} primitives.)
4393 @deffn Command {$target_name mww} addr word
4394 @deffnx Command {$target_name mwh} addr halfword
4395 @deffnx Command {$target_name mwb} addr byte
4396 Writes the specified @var{word} (32 bits),
4397 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4398 at the specified address @var{addr}.
4401 @anchor{targetevents}
4402 @section Target Events
4403 @cindex target events
4405 At various times, certain things can happen, or you want them to happen.
4408 @item What should happen when GDB connects? Should your target reset?
4409 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4410 @item Is using SRST appropriate (and possible) on your system?
4411 Or instead of that, do you need to issue JTAG commands to trigger reset?
4412 SRST usually resets everything on the scan chain, which can be inappropriate.
4413 @item During reset, do you need to write to certain memory locations
4414 to set up system clocks or
4415 to reconfigure the SDRAM?
4416 How about configuring the watchdog timer, or other peripherals,
4417 to stop running while you hold the core stopped for debugging?
4420 All of the above items can be addressed by target event handlers.
4421 These are set up by @command{$target_name configure -event} or
4422 @command{target create ... -event}.
4424 The programmer's model matches the @code{-command} option used in Tcl/Tk
4425 buttons and events. The two examples below act the same, but one creates
4426 and invokes a small procedure while the other inlines it.
4429 proc my_attach_proc @{ @} @{
4433 mychip.cpu configure -event gdb-attach my_attach_proc
4434 mychip.cpu configure -event gdb-attach @{
4436 # To make flash probe and gdb load to flash work
4437 # we need a reset init.
4442 The following target events are defined:
4445 @item @b{debug-halted}
4446 @* The target has halted for debug reasons (i.e.: breakpoint)
4447 @item @b{debug-resumed}
4448 @* The target has resumed (i.e.: gdb said run)
4449 @item @b{early-halted}
4450 @* Occurs early in the halt process
4451 @item @b{examine-start}
4452 @* Before target examine is called.
4453 @item @b{examine-end}
4454 @* After target examine is called with no errors.
4455 @item @b{gdb-attach}
4456 @* When GDB connects. This is before any communication with the target, so this
4457 can be used to set up the target so it is possible to probe flash. Probing flash
4458 is necessary during gdb connect if gdb load is to write the image to flash. Another
4459 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4460 depending on whether the breakpoint is in RAM or read only memory.
4461 @item @b{gdb-detach}
4462 @* When GDB disconnects
4464 @* When the target has halted and GDB is not doing anything (see early halt)
4465 @item @b{gdb-flash-erase-start}
4466 @* Before the GDB flash process tries to erase the flash (default is
4468 @item @b{gdb-flash-erase-end}
4469 @* After the GDB flash process has finished erasing the flash
4470 @item @b{gdb-flash-write-start}
4471 @* Before GDB writes to the flash
4472 @item @b{gdb-flash-write-end}
4473 @* After GDB writes to the flash (default is @code{reset halt})
4475 @* Before the target steps, gdb is trying to start/resume the target
4477 @* The target has halted
4478 @item @b{reset-assert-pre}
4479 @* Issued as part of @command{reset} processing
4480 after @command{reset_init} was triggered
4481 but before either SRST alone is re-asserted on the scan chain,
4482 or @code{reset-assert} is triggered.
4483 @item @b{reset-assert}
4484 @* Issued as part of @command{reset} processing
4485 after @command{reset-assert-pre} was triggered.
4486 When such a handler is present, cores which support this event will use
4487 it instead of asserting SRST.
4488 This support is essential for debugging with JTAG interfaces which
4489 don't include an SRST line (JTAG doesn't require SRST), and for
4490 selective reset on scan chains that have multiple targets.
4491 @item @b{reset-assert-post}
4492 @* Issued as part of @command{reset} processing
4493 after @code{reset-assert} has been triggered.
4494 or the target asserted SRST on the entire scan chain.
4495 @item @b{reset-deassert-pre}
4496 @* Issued as part of @command{reset} processing
4497 after @code{reset-assert-post} has been triggered.
4498 @item @b{reset-deassert-post}
4499 @* Issued as part of @command{reset} processing
4500 after @code{reset-deassert-pre} has been triggered
4501 and (if the target is using it) after SRST has been
4502 released on the scan chain.
4504 @* Issued as the final step in @command{reset} processing.
4506 @item @b{reset-halt-post}
4507 @* Currently not used
4508 @item @b{reset-halt-pre}
4509 @* Currently not used
4511 @item @b{reset-init}
4512 @* Used by @b{reset init} command for board-specific initialization.
4513 This event fires after @emph{reset-deassert-post}.
4515 This is where you would configure PLLs and clocking, set up DRAM so
4516 you can download programs that don't fit in on-chip SRAM, set up pin
4517 multiplexing, and so on.
4518 (You may be able to switch to a fast JTAG clock rate here, after
4519 the target clocks are fully set up.)
4520 @item @b{reset-start}
4521 @* Issued as part of @command{reset} processing
4522 before @command{reset_init} is called.
4524 This is the most robust place to use @command{jtag_rclk}
4525 or @command{adapter_khz} to switch to a low JTAG clock rate,
4526 when reset disables PLLs needed to use a fast clock.
4528 @item @b{reset-wait-pos}
4529 @* Currently not used
4530 @item @b{reset-wait-pre}
4531 @* Currently not used
4533 @item @b{resume-start}
4534 @* Before any target is resumed
4535 @item @b{resume-end}
4536 @* After all targets have resumed
4538 @* Target has resumed
4539 @item @b{trace-config}
4540 @* After target hardware trace configuration was changed
4543 @node Flash Commands
4544 @chapter Flash Commands
4546 OpenOCD has different commands for NOR and NAND flash;
4547 the ``flash'' command works with NOR flash, while
4548 the ``nand'' command works with NAND flash.
4549 This partially reflects different hardware technologies:
4550 NOR flash usually supports direct CPU instruction and data bus access,
4551 while data from a NAND flash must be copied to memory before it can be
4552 used. (SPI flash must also be copied to memory before use.)
4553 However, the documentation also uses ``flash'' as a generic term;
4554 for example, ``Put flash configuration in board-specific files''.
4558 @item Configure via the command @command{flash bank}
4559 @* Do this in a board-specific configuration file,
4560 passing parameters as needed by the driver.
4561 @item Operate on the flash via @command{flash subcommand}
4562 @* Often commands to manipulate the flash are typed by a human, or run
4563 via a script in some automated way. Common tasks include writing a
4564 boot loader, operating system, or other data.
4566 @* Flashing via GDB requires the flash be configured via ``flash
4567 bank'', and the GDB flash features be enabled.
4568 @xref{gdbconfiguration,,GDB Configuration}.
4571 Many CPUs have the ablity to ``boot'' from the first flash bank.
4572 This means that misprogramming that bank can ``brick'' a system,
4573 so that it can't boot.
4574 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4575 board by (re)installing working boot firmware.
4577 @anchor{norconfiguration}
4578 @section Flash Configuration Commands
4579 @cindex flash configuration
4581 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4582 Configures a flash bank which provides persistent storage
4583 for addresses from @math{base} to @math{base + size - 1}.
4584 These banks will often be visible to GDB through the target's memory map.
4585 In some cases, configuring a flash bank will activate extra commands;
4586 see the driver-specific documentation.
4589 @item @var{name} ... may be used to reference the flash bank
4590 in other flash commands. A number is also available.
4591 @item @var{driver} ... identifies the controller driver
4592 associated with the flash bank being declared.
4593 This is usually @code{cfi} for external flash, or else
4594 the name of a microcontroller with embedded flash memory.
4595 @xref{flashdriverlist,,Flash Driver List}.
4596 @item @var{base} ... Base address of the flash chip.
4597 @item @var{size} ... Size of the chip, in bytes.
4598 For some drivers, this value is detected from the hardware.
4599 @item @var{chip_width} ... Width of the flash chip, in bytes;
4600 ignored for most microcontroller drivers.
4601 @item @var{bus_width} ... Width of the data bus used to access the
4602 chip, in bytes; ignored for most microcontroller drivers.
4603 @item @var{target} ... Names the target used to issue
4604 commands to the flash controller.
4605 @comment Actually, it's currently a controller-specific parameter...
4606 @item @var{driver_options} ... drivers may support, or require,
4607 additional parameters. See the driver-specific documentation
4608 for more information.
4611 This command is not available after OpenOCD initialization has completed.
4612 Use it in board specific configuration files, not interactively.
4616 @comment the REAL name for this command is "ocd_flash_banks"
4617 @comment less confusing would be: "flash list" (like "nand list")
4618 @deffn Command {flash banks}
4619 Prints a one-line summary of each device that was
4620 declared using @command{flash bank}, numbered from zero.
4621 Note that this is the @emph{plural} form;
4622 the @emph{singular} form is a very different command.
4625 @deffn Command {flash list}
4626 Retrieves a list of associative arrays for each device that was
4627 declared using @command{flash bank}, numbered from zero.
4628 This returned list can be manipulated easily from within scripts.
4631 @deffn Command {flash probe} num
4632 Identify the flash, or validate the parameters of the configured flash. Operation
4633 depends on the flash type.
4634 The @var{num} parameter is a value shown by @command{flash banks}.
4635 Most flash commands will implicitly @emph{autoprobe} the bank;
4636 flash drivers can distinguish between probing and autoprobing,
4637 but most don't bother.
4640 @section Erasing, Reading, Writing to Flash
4641 @cindex flash erasing
4642 @cindex flash reading
4643 @cindex flash writing
4644 @cindex flash programming
4645 @anchor{flashprogrammingcommands}
4647 One feature distinguishing NOR flash from NAND or serial flash technologies
4648 is that for read access, it acts exactly like any other addressible memory.
4649 This means you can use normal memory read commands like @command{mdw} or
4650 @command{dump_image} with it, with no special @command{flash} subcommands.
4651 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4653 Write access works differently. Flash memory normally needs to be erased
4654 before it's written. Erasing a sector turns all of its bits to ones, and
4655 writing can turn ones into zeroes. This is why there are special commands
4656 for interactive erasing and writing, and why GDB needs to know which parts
4657 of the address space hold NOR flash memory.
4660 Most of these erase and write commands leverage the fact that NOR flash
4661 chips consume target address space. They implicitly refer to the current
4662 JTAG target, and map from an address in that target's address space
4663 back to a flash bank.
4664 @comment In May 2009, those mappings may fail if any bank associated
4665 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4666 A few commands use abstract addressing based on bank and sector numbers,
4667 and don't depend on searching the current target and its address space.
4668 Avoid confusing the two command models.
4671 Some flash chips implement software protection against accidental writes,
4672 since such buggy writes could in some cases ``brick'' a system.
4673 For such systems, erasing and writing may require sector protection to be
4675 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4676 and AT91SAM7 on-chip flash.
4677 @xref{flashprotect,,flash protect}.
4679 @deffn Command {flash erase_sector} num first last
4680 Erase sectors in bank @var{num}, starting at sector @var{first}
4681 up to and including @var{last}.
4682 Sector numbering starts at 0.
4683 Providing a @var{last} sector of @option{last}
4684 specifies "to the end of the flash bank".
4685 The @var{num} parameter is a value shown by @command{flash banks}.
4688 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4689 Erase sectors starting at @var{address} for @var{length} bytes.
4690 Unless @option{pad} is specified, @math{address} must begin a
4691 flash sector, and @math{address + length - 1} must end a sector.
4692 Specifying @option{pad} erases extra data at the beginning and/or
4693 end of the specified region, as needed to erase only full sectors.
4694 The flash bank to use is inferred from the @var{address}, and
4695 the specified length must stay within that bank.
4696 As a special case, when @var{length} is zero and @var{address} is
4697 the start of the bank, the whole flash is erased.
4698 If @option{unlock} is specified, then the flash is unprotected
4699 before erase starts.
4702 @deffn Command {flash fillw} address word length
4703 @deffnx Command {flash fillh} address halfword length
4704 @deffnx Command {flash fillb} address byte length
4705 Fills flash memory with the specified @var{word} (32 bits),
4706 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4707 starting at @var{address} and continuing
4708 for @var{length} units (word/halfword/byte).
4709 No erasure is done before writing; when needed, that must be done
4710 before issuing this command.
4711 Writes are done in blocks of up to 1024 bytes, and each write is
4712 verified by reading back the data and comparing it to what was written.
4713 The flash bank to use is inferred from the @var{address} of
4714 each block, and the specified length must stay within that bank.
4716 @comment no current checks for errors if fill blocks touch multiple banks!
4718 @deffn Command {flash write_bank} num filename offset
4719 Write the binary @file{filename} to flash bank @var{num},
4720 starting at @var{offset} bytes from the beginning of the bank.
4721 The @var{num} parameter is a value shown by @command{flash banks}.
4724 @deffn Command {flash read_bank} num filename offset length
4725 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
4726 and write the contents to the binary @file{filename}.
4727 The @var{num} parameter is a value shown by @command{flash banks}.
4730 @deffn Command {flash verify_bank} num filename [offset]
4731 Compare the contents of the binary file @var{filename} with the contents of the
4732 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
4733 start at the beginning of the flash bank. Fail if the contents do not match.
4734 The @var{num} parameter is a value shown by @command{flash banks}.
4737 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4738 Write the image @file{filename} to the current target's flash bank(s).
4739 Only loadable sections from the image are written.
4740 A relocation @var{offset} may be specified, in which case it is added
4741 to the base address for each section in the image.
4742 The file [@var{type}] can be specified
4743 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4744 @option{elf} (ELF file), @option{s19} (Motorola s19).
4745 @option{mem}, or @option{builder}.
4746 The relevant flash sectors will be erased prior to programming
4747 if the @option{erase} parameter is given. If @option{unlock} is
4748 provided, then the flash banks are unlocked before erase and
4749 program. The flash bank to use is inferred from the address of
4753 Be careful using the @option{erase} flag when the flash is holding
4754 data you want to preserve.
4755 Portions of the flash outside those described in the image's
4756 sections might be erased with no notice.
4759 When a section of the image being written does not fill out all the
4760 sectors it uses, the unwritten parts of those sectors are necessarily
4761 also erased, because sectors can't be partially erased.
4763 Data stored in sector "holes" between image sections are also affected.
4764 For example, "@command{flash write_image erase ...}" of an image with
4765 one byte at the beginning of a flash bank and one byte at the end
4766 erases the entire bank -- not just the two sectors being written.
4768 Also, when flash protection is important, you must re-apply it after
4769 it has been removed by the @option{unlock} flag.
4774 @section Other Flash commands
4775 @cindex flash protection
4777 @deffn Command {flash erase_check} num
4778 Check erase state of sectors in flash bank @var{num},
4779 and display that status.
4780 The @var{num} parameter is a value shown by @command{flash banks}.
4783 @deffn Command {flash info} num [sectors]
4784 Print info about flash bank @var{num}, a list of protection blocks
4785 and their status. Use @option{sectors} to show a list of sectors instead.
4787 The @var{num} parameter is a value shown by @command{flash banks}.
4788 This command will first query the hardware, it does not print cached
4789 and possibly stale information.
4792 @anchor{flashprotect}
4793 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4794 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
4795 in flash bank @var{num}, starting at protection block @var{first}
4796 and continuing up to and including @var{last}.
4797 Providing a @var{last} block of @option{last}
4798 specifies "to the end of the flash bank".
4799 The @var{num} parameter is a value shown by @command{flash banks}.
4800 The protection block is usually identical to a flash sector.
4801 Some devices may utilize a protection block distinct from flash sector.
4802 See @command{flash info} for a list of protection blocks.
4805 @deffn Command {flash padded_value} num value
4806 Sets the default value used for padding any image sections, This should
4807 normally match the flash bank erased value. If not specified by this
4808 comamnd or the flash driver then it defaults to 0xff.
4812 @deffn Command {program} filename [verify] [reset] [exit] [offset]
4813 This is a helper script that simplifies using OpenOCD as a standalone
4814 programmer. The only required parameter is @option{filename}, the others are optional.
4815 @xref{Flash Programming}.
4818 @anchor{flashdriverlist}
4819 @section Flash Driver List
4820 As noted above, the @command{flash bank} command requires a driver name,
4821 and allows driver-specific options and behaviors.
4822 Some drivers also activate driver-specific commands.
4824 @deffn {Flash Driver} virtual
4825 This is a special driver that maps a previously defined bank to another
4826 address. All bank settings will be copied from the master physical bank.
4828 The @var{virtual} driver defines one mandatory parameters,
4831 @item @var{master_bank} The bank that this virtual address refers to.
4834 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
4835 the flash bank defined at address 0x1fc00000. Any cmds executed on
4836 the virtual banks are actually performed on the physical banks.
4838 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
4839 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
4840 $_TARGETNAME $_FLASHNAME
4841 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
4842 $_TARGETNAME $_FLASHNAME
4846 @subsection External Flash
4848 @deffn {Flash Driver} cfi
4849 @cindex Common Flash Interface
4851 The ``Common Flash Interface'' (CFI) is the main standard for
4852 external NOR flash chips, each of which connects to a
4853 specific external chip select on the CPU.
4854 Frequently the first such chip is used to boot the system.
4855 Your board's @code{reset-init} handler might need to
4856 configure additional chip selects using other commands (like: @command{mww} to
4857 configure a bus and its timings), or
4858 perhaps configure a GPIO pin that controls the ``write protect'' pin
4860 The CFI driver can use a target-specific working area to significantly
4863 The CFI driver can accept the following optional parameters, in any order:
4866 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4867 like AM29LV010 and similar types.
4868 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4869 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
4870 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
4871 swapped when writing data values (ie. not CFI commands).
4874 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4875 wide on a sixteen bit bus:
4878 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4879 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4882 To configure one bank of 32 MBytes
4883 built from two sixteen bit (two byte) wide parts wired in parallel
4884 to create a thirty-two bit (four byte) bus with doubled throughput:
4887 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4890 @c "cfi part_id" disabled
4893 @deffn {Flash Driver} jtagspi
4894 @cindex Generic JTAG2SPI driver
4898 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
4899 SPI flash connected to them. To access this flash from the host, the device
4900 is first programmed with a special proxy bitstream that
4901 exposes the SPI flash on the device's JTAG interface. The flash can then be
4902 accessed through JTAG.
4904 Since signaling between JTAG and SPI is compatible, all that is required for
4905 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
4906 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
4907 a bitstream for several Xilinx FPGAs can be found in
4908 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
4909 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
4911 This flash bank driver requires a target on a JTAG tap and will access that
4912 tap directly. Since no support from the target is needed, the target can be a
4913 "testee" dummy. Since the target does not expose the flash memory
4914 mapping, target commands that would otherwise be expected to access the flash
4915 will not work. These include all @command{*_image} and
4916 @command{$target_name m*} commands as well as @command{program}. Equivalent
4917 functionality is available through the @command{flash write_bank},
4918 @command{flash read_bank}, and @command{flash verify_bank} commands.
4921 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
4922 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
4923 @var{USER1} instruction.
4924 @item @var{dr_length} ... is the length of the DR register. This will be 1 for
4925 @file{xilinx_bscan_spi.py} bitstreams and most other cases.
4929 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
4930 set _XILINX_USER1 0x02
4932 flash bank $_FLASHNAME spi 0x0 0 0 0 \
4933 $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH
4937 @deffn {Flash Driver} lpcspifi
4938 @cindex NXP SPI Flash Interface
4941 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4942 Flash Interface (SPIFI) peripheral that can drive and provide
4943 memory mapped access to external SPI flash devices.
4945 The lpcspifi driver initializes this interface and provides
4946 program and erase functionality for these serial flash devices.
4947 Use of this driver @b{requires} a working area of at least 1kB
4948 to be configured on the target device; more than this will
4949 significantly reduce flash programming times.
4951 The setup command only requires the @var{base} parameter. All
4952 other parameters are ignored, and the flash size and layout
4953 are configured by the driver.
4956 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4961 @deffn {Flash Driver} stmsmi
4962 @cindex STMicroelectronics Serial Memory Interface
4965 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4966 SPEAr MPU family) include a proprietary
4967 ``Serial Memory Interface'' (SMI) controller able to drive external
4969 Depending on specific device and board configuration, up to 4 external
4970 flash devices can be connected.
4972 SMI makes the flash content directly accessible in the CPU address
4973 space; each external device is mapped in a memory bank.
4974 CPU can directly read data, execute code and boot from SMI banks.
4975 Normal OpenOCD commands like @command{mdw} can be used to display
4978 The setup command only requires the @var{base} parameter in order
4979 to identify the memory bank.
4980 All other parameters are ignored. Additional information, like
4981 flash size, are detected automatically.
4984 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4989 @deffn {Flash Driver} mrvlqspi
4990 This driver supports QSPI flash controller of Marvell's Wireless
4991 Microcontroller platform.
4993 The flash size is autodetected based on the table of known JEDEC IDs
4994 hardcoded in the OpenOCD sources.
4997 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5002 @deffn {Flash Driver} ath79
5003 @cindex Atheros ath79 SPI driver
5005 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5007 On reset a SPI flash connected to the first chip select (CS0) is made
5008 directly read-accessible in the CPU address space (up to 16MBytes)
5009 and is usually used to store the bootloader and operating system.
5010 Normal OpenOCD commands like @command{mdw} can be used to display
5011 the flash content while it is in memory-mapped mode (only the first
5012 4MBytes are accessible without additional configuration on reset).
5014 The setup command only requires the @var{base} parameter in order
5015 to identify the memory bank. The actual value for the base address
5016 is not otherwise used by the driver. However the mapping is passed
5017 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5018 address should be the actual memory mapped base address. For unmapped
5019 chipselects (CS1 and CS2) care should be taken to use a base address
5020 that does not overlap with real memory regions.
5021 Additional information, like flash size, are detected automatically.
5022 An optional additional parameter sets the chipselect for the bank,
5023 with the default CS0.
5024 CS1 and CS2 require additional GPIO setup before they can be used
5025 since the alternate function must be enabled on the GPIO pin
5026 CS1/CS2 is routed to on the given SoC.
5029 flash bank $_FLASHNAME ath79 0 0 0 0 $_TARGETNAME
5031 # When using multiple chipselects the base should be different for each,
5032 # otherwise the write_image command is not able to distinguish the
5034 flash bank flash0 ath79 0x00000000 0 0 0 $_TARGETNAME cs0
5035 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5036 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5041 @subsection Internal Flash (Microcontrollers)
5043 @deffn {Flash Driver} aduc702x
5044 The ADUC702x analog microcontrollers from Analog Devices
5045 include internal flash and use ARM7TDMI cores.
5046 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5047 The setup command only requires the @var{target} argument
5048 since all devices in this family have the same memory layout.
5051 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5055 @deffn {Flash Driver} ambiqmicro
5058 All members of the Apollo microcontroller family from
5059 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5060 The host connects over USB to an FTDI interface that communicates
5061 with the target using SWD.
5063 The @var{ambiqmicro} driver reads the Chip Information Register detect
5064 the device class of the MCU.
5065 The Flash and Sram sizes directly follow device class, and are used
5066 to set up the flash banks.
5067 If this fails, the driver will use default values set to the minimum
5068 sizes of an Apollo chip.
5070 All Apollo chips have two flash banks of the same size.
5071 In all cases the first flash bank starts at location 0,
5072 and the second bank starts after the first.
5076 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5077 # Flash bank 1 - same size as bank0, starts after bank 0.
5078 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5082 Flash is programmed using custom entry points into the bootloader.
5083 This is the only way to program the flash as no flash control registers
5084 are available to the user.
5086 The @var{ambiqmicro} driver adds some additional commands:
5088 @deffn Command {ambiqmicro mass_erase} <bank>
5091 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
5094 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
5095 Program OTP is a one time operation to create write protected flash.
5096 The user writes sectors to sram starting at 0x10000010.
5097 Program OTP will write these sectors from sram to flash, and write protect
5103 @deffn {Flash Driver} at91samd
5105 All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
5106 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5107 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5109 @deffn Command {at91samd chip-erase}
5110 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5111 used to erase a chip back to its factory state and does not require the
5112 processor to be halted.
5115 @deffn Command {at91samd set-security}
5116 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5117 to the Flash and can only be undone by using the chip-erase command which
5118 erases the Flash contents and turns off the security bit. Warning: at this
5119 time, openocd will not be able to communicate with a secured chip and it is
5120 therefore not possible to chip-erase it without using another tool.
5123 at91samd set-security enable
5127 @deffn Command {at91samd eeprom}
5128 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5129 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5130 must be one of the permitted sizes according to the datasheet. Settings are
5131 written immediately but only take effect on MCU reset. EEPROM emulation
5132 requires additional firmware support and the minumum EEPROM size may not be
5133 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5134 in order to disable this feature.
5138 at91samd eeprom 1024
5142 @deffn Command {at91samd bootloader}
5143 Shows or sets the bootloader size configuration, stored in the User Row of the
5144 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5145 must be specified in bytes and it must be one of the permitted sizes according
5146 to the datasheet. Settings are written immediately but only take effect on
5147 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5151 at91samd bootloader 16384
5155 @deffn Command {at91samd dsu_reset_deassert}
5156 This command releases internal reset held by DSU
5157 and prepares reset vector catch in case of reset halt.
5158 Command is used internally in event event reset-deassert-post.
5164 @deffn {Flash Driver} at91sam3
5166 All members of the AT91SAM3 microcontroller family from
5167 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5168 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5169 that the driver was orginaly developed and tested using the
5170 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5171 the family was cribbed from the data sheet. @emph{Note to future
5172 readers/updaters: Please remove this worrysome comment after other
5173 chips are confirmed.}
5175 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5176 have one flash bank. In all cases the flash banks are at
5177 the following fixed locations:
5180 # Flash bank 0 - all chips
5181 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5182 # Flash bank 1 - only 256K chips
5183 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5186 Internally, the AT91SAM3 flash memory is organized as follows.
5187 Unlike the AT91SAM7 chips, these are not used as parameters
5188 to the @command{flash bank} command:
5191 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5192 @item @emph{Bank Size:} 128K/64K Per flash bank
5193 @item @emph{Sectors:} 16 or 8 per bank
5194 @item @emph{SectorSize:} 8K Per Sector
5195 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5198 The AT91SAM3 driver adds some additional commands:
5200 @deffn Command {at91sam3 gpnvm}
5201 @deffnx Command {at91sam3 gpnvm clear} number
5202 @deffnx Command {at91sam3 gpnvm set} number
5203 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5204 With no parameters, @command{show} or @command{show all},
5205 shows the status of all GPNVM bits.
5206 With @command{show} @var{number}, displays that bit.
5208 With @command{set} @var{number} or @command{clear} @var{number},
5209 modifies that GPNVM bit.
5212 @deffn Command {at91sam3 info}
5213 This command attempts to display information about the AT91SAM3
5214 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5215 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5216 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5217 various clock configuration registers and attempts to display how it
5218 believes the chip is configured. By default, the SLOWCLK is assumed to
5219 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5222 @deffn Command {at91sam3 slowclk} [value]
5223 This command shows/sets the slow clock frequency used in the
5224 @command{at91sam3 info} command calculations above.
5228 @deffn {Flash Driver} at91sam4
5230 All members of the AT91SAM4 microcontroller family from
5231 Atmel include internal flash and use ARM's Cortex-M4 core.
5232 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5235 @deffn {Flash Driver} at91sam4l
5237 All members of the AT91SAM4L microcontroller family from
5238 Atmel include internal flash and use ARM's Cortex-M4 core.
5239 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5241 The AT91SAM4L driver adds some additional commands:
5242 @deffn Command {at91sam4l smap_reset_deassert}
5243 This command releases internal reset held by SMAP
5244 and prepares reset vector catch in case of reset halt.
5245 Command is used internally in event event reset-deassert-post.
5249 @deffn {Flash Driver} atsamv
5251 All members of the ATSAMV, ATSAMS, and ATSAME families from
5252 Atmel include internal flash and use ARM's Cortex-M7 core.
5253 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5256 @deffn {Flash Driver} at91sam7
5257 All members of the AT91SAM7 microcontroller family from Atmel include
5258 internal flash and use ARM7TDMI cores. The driver automatically
5259 recognizes a number of these chips using the chip identification
5260 register, and autoconfigures itself.
5263 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5266 For chips which are not recognized by the controller driver, you must
5267 provide additional parameters in the following order:
5270 @item @var{chip_model} ... label used with @command{flash info}
5272 @item @var{sectors_per_bank}
5273 @item @var{pages_per_sector}
5274 @item @var{pages_size}
5275 @item @var{num_nvm_bits}
5276 @item @var{freq_khz} ... required if an external clock is provided,
5277 optional (but recommended) when the oscillator frequency is known
5280 It is recommended that you provide zeroes for all of those values
5281 except the clock frequency, so that everything except that frequency
5282 will be autoconfigured.
5283 Knowing the frequency helps ensure correct timings for flash access.
5285 The flash controller handles erases automatically on a page (128/256 byte)
5286 basis, so explicit erase commands are not necessary for flash programming.
5287 However, there is an ``EraseAll`` command that can erase an entire flash
5288 plane (of up to 256KB), and it will be used automatically when you issue
5289 @command{flash erase_sector} or @command{flash erase_address} commands.
5291 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5292 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5293 bit for the processor. Each processor has a number of such bits,
5294 used for controlling features such as brownout detection (so they
5295 are not truly general purpose).
5297 This assumes that the first flash bank (number 0) is associated with
5298 the appropriate at91sam7 target.
5303 @deffn {Flash Driver} avr
5304 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5305 @emph{The current implementation is incomplete.}
5306 @comment - defines mass_erase ... pointless given flash_erase_address
5309 @deffn {Flash Driver} efm32
5310 All members of the EFM32 microcontroller family from Energy Micro include
5311 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
5312 a number of these chips using the chip identification register, and
5313 autoconfigures itself.
5315 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5317 A special feature of efm32 controllers is that it is possible to completely disable the
5318 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
5319 this via the following command:
5323 The @var{num} parameter is a value shown by @command{flash banks}.
5324 Note that in order for this command to take effect, the target needs to be reset.
5325 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5329 @deffn {Flash Driver} fm3
5330 All members of the FM3 microcontroller family from Fujitsu
5331 include internal flash and use ARM Cortex-M3 cores.
5332 The @var{fm3} driver uses the @var{target} parameter to select the
5333 correct bank config, it can currently be one of the following:
5334 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5335 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5338 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5342 @deffn {Flash Driver} fm4
5343 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
5344 include internal flash and use ARM Cortex-M4 cores.
5345 The @var{fm4} driver uses a @var{family} parameter to select the
5346 correct bank config, it can currently be one of the following:
5347 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
5348 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
5349 with @code{x} treated as wildcard and otherwise case (and any trailing
5350 characters) ignored.
5353 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
5354 $_TARGETNAME S6E2CCAJ0A
5355 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
5356 $_TARGETNAME S6E2CCAJ0A
5358 @emph{The current implementation is incomplete. Protection is not supported,
5359 nor is Chip Erase (only Sector Erase is implemented).}
5362 @deffn {Flash Driver} kinetis
5364 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
5365 from NXP (former Freescale) include
5366 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
5367 recognizes flash size and a number of flash banks (1-4) using the chip
5368 identification register, and autoconfigures itself.
5369 Use kinetis_ke driver for KE0x devices.
5372 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
5375 @deffn Command {kinetis fcf_source} [protection|write]
5376 Select what source is used when writing to a Flash Configuration Field.
5377 @option{protection} mode builds FCF content from protection bits previously
5378 set by 'flash protect' command.
5379 This mode is default. MCU is protected from unwanted locking by immediate
5380 writing FCF after erase of relevant sector.
5381 @option{write} mode enables direct write to FCF.
5382 Protection cannot be set by 'flash protect' command. FCF is written along
5383 with the rest of a flash image.
5384 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
5387 @deffn Command {kinetis fopt} [num]
5388 Set value to write to FOPT byte of Flash Configuration Field.
5389 Used in kinetis 'fcf_source protection' mode only.
5392 @deffn Command {kinetis mdm check_security}
5393 Checks status of device security lock. Used internally in examine-end event.
5396 @deffn Command {kinetis mdm halt}
5397 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
5398 loop when connecting to an unsecured target.
5401 @deffn Command {kinetis mdm mass_erase}
5402 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
5403 back to its factory state, removing security. It does not require the processor
5404 to be halted, however the target will remain in a halted state after this
5408 @deffn Command {kinetis nvm_partition}
5409 For FlexNVM devices only (KxxDX and KxxFX).
5410 Command shows or sets data flash or EEPROM backup size in kilobytes,
5411 sets two EEPROM blocks sizes in bytes and enables/disables loading
5412 of EEPROM contents to FlexRAM during reset.
5414 For details see device reference manual, Flash Memory Module,
5415 Program Partition command.
5417 Setting is possible only once after mass_erase.
5418 Reset the device after partition setting.
5420 Show partition size:
5422 kinetis nvm_partition info
5425 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
5426 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
5428 kinetis nvm_partition dataflash 32 512 1536 on
5431 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
5432 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
5434 kinetis nvm_partition eebkp 16 1024 1024 off
5438 @deffn Command {kinetis mdm reset}
5439 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
5440 RESET pin, which can be used to reset other hardware on board.
5443 @deffn Command {kinetis disable_wdog}
5444 For Kx devices only (KLx has different COP watchdog, it is not supported).
5445 Command disables watchdog timer.
5449 @deffn {Flash Driver} kinetis_ke
5451 KE0x members of the Kinetis microcontroller family from Freescale include
5452 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
5453 the KE0x sub-family using the chip identification register, and
5454 autoconfigures itself.
5455 Use kinetis (not kinetis_ke) driver for KE1x devices.
5458 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
5461 @deffn Command {kinetis_ke mdm check_security}
5462 Checks status of device security lock. Used internally in examine-end event.
5465 @deffn Command {kinetis_ke mdm mass_erase}
5466 Issues a complete Flash erase via the MDM-AP.
5467 This can be used to erase a chip back to its factory state.
5468 Command removes security lock from a device (use of SRST highly recommended).
5469 It does not require the processor to be halted.
5472 @deffn Command {kinetis_ke disable_wdog}
5473 Command disables watchdog timer.
5477 @deffn {Flash Driver} lpc2000
5478 This is the driver to support internal flash of all members of the
5479 LPC11(x)00 and LPC1300 microcontroller families and most members of
5480 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
5481 microcontroller families from NXP.
5484 There are LPC2000 devices which are not supported by the @var{lpc2000}
5486 The LPC2888 is supported by the @var{lpc288x} driver.
5487 The LPC29xx family is supported by the @var{lpc2900} driver.
5490 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5491 which must appear in the following order:
5494 @item @var{variant} ... required, may be
5495 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5496 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5497 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
5498 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
5500 @option{lpc800} (LPC8xx)
5501 @option{lpc1100} (LPC11(x)xx and LPC13xx)
5502 @option{lpc1500} (LPC15xx)
5503 @option{lpc54100} (LPC541xx)
5504 @option{lpc4000} (LPC40xx)
5505 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
5506 LPC8xx, LPC13xx, LPC17xx and LPC40xx
5507 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5508 at which the core is running
5509 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5510 telling the driver to calculate a valid checksum for the exception vector table.
5512 If you don't provide @option{calc_checksum} when you're writing the vector
5513 table, the boot ROM will almost certainly ignore your flash image.
5514 However, if you do provide it,
5515 with most tool chains @command{verify_image} will fail.
5519 LPC flashes don't require the chip and bus width to be specified.
5522 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5523 lpc2000_v2 14765 calc_checksum
5526 @deffn {Command} {lpc2000 part_id} bank
5527 Displays the four byte part identifier associated with
5528 the specified flash @var{bank}.
5532 @deffn {Flash Driver} lpc288x
5533 The LPC2888 microcontroller from NXP needs slightly different flash
5534 support from its lpc2000 siblings.
5535 The @var{lpc288x} driver defines one mandatory parameter,
5536 the programming clock rate in Hz.
5537 LPC flashes don't require the chip and bus width to be specified.
5540 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5544 @deffn {Flash Driver} lpc2900
5545 This driver supports the LPC29xx ARM968E based microcontroller family
5548 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5549 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5550 sector layout are auto-configured by the driver.
5551 The driver has one additional mandatory parameter: The CPU clock rate
5552 (in kHz) at the time the flash operations will take place. Most of the time this
5553 will not be the crystal frequency, but a higher PLL frequency. The
5554 @code{reset-init} event handler in the board script is usually the place where
5557 The driver rejects flashless devices (currently the LPC2930).
5559 The EEPROM in LPC2900 devices is not mapped directly into the address space.
5560 It must be handled much more like NAND flash memory, and will therefore be
5561 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
5563 Sector protection in terms of the LPC2900 is handled transparently. Every time a
5564 sector needs to be erased or programmed, it is automatically unprotected.
5565 What is shown as protection status in the @code{flash info} command, is
5566 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
5567 sector from ever being erased or programmed again. As this is an irreversible
5568 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
5569 and not by the standard @code{flash protect} command.
5571 Example for a 125 MHz clock frequency:
5573 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
5576 Some @code{lpc2900}-specific commands are defined. In the following command list,
5577 the @var{bank} parameter is the bank number as obtained by the
5578 @code{flash banks} command.
5580 @deffn Command {lpc2900 signature} bank
5581 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
5582 content. This is a hardware feature of the flash block, hence the calculation is
5583 very fast. You may use this to verify the content of a programmed device against
5588 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
5592 @deffn Command {lpc2900 read_custom} bank filename
5593 Reads the 912 bytes of customer information from the flash index sector, and
5594 saves it to a file in binary format.
5597 lpc2900 read_custom 0 /path_to/customer_info.bin
5601 The index sector of the flash is a @emph{write-only} sector. It cannot be
5602 erased! In order to guard against unintentional write access, all following
5603 commands need to be preceeded by a successful call to the @code{password}
5606 @deffn Command {lpc2900 password} bank password
5607 You need to use this command right before each of the following commands:
5608 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
5609 @code{lpc2900 secure_jtag}.
5611 The password string is fixed to "I_know_what_I_am_doing".
5614 lpc2900 password 0 I_know_what_I_am_doing
5615 Potentially dangerous operation allowed in next command!
5619 @deffn Command {lpc2900 write_custom} bank filename type
5620 Writes the content of the file into the customer info space of the flash index
5621 sector. The filetype can be specified with the @var{type} field. Possible values
5622 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
5623 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
5624 contain a single section, and the contained data length must be exactly
5626 @quotation Attention
5627 This cannot be reverted! Be careful!
5631 lpc2900 write_custom 0 /path_to/customer_info.bin bin
5635 @deffn Command {lpc2900 secure_sector} bank first last
5636 Secures the sector range from @var{first} to @var{last} (including) against
5637 further program and erase operations. The sector security will be effective
5638 after the next power cycle.
5639 @quotation Attention
5640 This cannot be reverted! Be careful!
5642 Secured sectors appear as @emph{protected} in the @code{flash info} command.
5645 lpc2900 secure_sector 0 1 1
5647 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
5648 # 0: 0x00000000 (0x2000 8kB) not protected
5649 # 1: 0x00002000 (0x2000 8kB) protected
5650 # 2: 0x00004000 (0x2000 8kB) not protected
5654 @deffn Command {lpc2900 secure_jtag} bank
5655 Irreversibly disable the JTAG port. The new JTAG security setting will be
5656 effective after the next power cycle.
5657 @quotation Attention
5658 This cannot be reverted! Be careful!
5662 lpc2900 secure_jtag 0
5667 @deffn {Flash Driver} mdr
5668 This drivers handles the integrated NOR flash on Milandr Cortex-M
5669 based controllers. A known limitation is that the Info memory can't be
5670 read or verified as it's not memory mapped.
5673 flash bank <name> mdr <base> <size> \
5674 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
5678 @item @var{type} - 0 for main memory, 1 for info memory
5679 @item @var{page_count} - total number of pages
5680 @item @var{sec_count} - number of sector per page count
5685 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
5686 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
5687 0 0 $_TARGETNAME 1 1 4
5689 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
5690 0 0 $_TARGETNAME 0 32 4
5695 @deffn {Flash Driver} niietcm4
5696 This drivers handles the integrated NOR flash on NIIET Cortex-M4
5697 based controllers. Flash size and sector layout are auto-configured by the driver.
5698 Main flash memory is called "Bootflash" and has main region and info region.
5699 Info region is NOT memory mapped by default,
5700 but it can replace first part of main region if needed.
5701 Full erase, single and block writes are supported for both main and info regions.
5702 There is additional not memory mapped flash called "Userflash", which
5703 also have division into regions: main and info.
5704 Purpose of userflash - to store system and user settings.
5705 Driver has special commands to perform operations with this memmory.
5708 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
5711 Some niietcm4-specific commands are defined:
5713 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
5714 Read byte from main or info userflash region.
5717 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
5718 Write byte to main or info userflash region.
5721 @deffn Command {niietcm4 uflash_full_erase} bank
5722 Erase all userflash including info region.
5725 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
5726 Erase sectors of main or info userflash region, starting at sector first up to and including last.
5729 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
5730 Check sectors protect.
5733 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
5734 Protect sectors of main or info userflash region, starting at sector first up to and including last.
5737 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
5738 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
5741 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
5742 Configure external memory interface for boot.
5745 @deffn Command {niietcm4 service_mode_erase} bank
5746 Perform emergency erase of all flash (bootflash and userflash).
5749 @deffn Command {niietcm4 driver_info} bank
5750 Show information about flash driver.
5755 @deffn {Flash Driver} nrf51
5756 All members of the nRF51 microcontroller families from Nordic Semiconductor
5757 include internal flash and use ARM Cortex-M0 core.
5760 flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
5763 Some nrf51-specific commands are defined:
5765 @deffn Command {nrf51 mass_erase}
5766 Erases the contents of the code memory and user information
5767 configuration registers as well. It must be noted that this command
5768 works only for chips that do not have factory pre-programmed region 0
5774 @deffn {Flash Driver} ocl
5775 This driver is an implementation of the ``on chip flash loader''
5776 protocol proposed by Pavel Chromy.
5778 It is a minimalistic command-response protocol intended to be used
5779 over a DCC when communicating with an internal or external flash
5780 loader running from RAM. An example implementation for AT91SAM7x is
5781 available in @file{contrib/loaders/flash/at91sam7x/}.
5784 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
5788 @deffn {Flash Driver} pic32mx
5789 The PIC32MX microcontrollers are based on the MIPS 4K cores,
5790 and integrate flash memory.
5793 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
5794 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
5797 @comment numerous *disabled* commands are defined:
5798 @comment - chip_erase ... pointless given flash_erase_address
5799 @comment - lock, unlock ... pointless given protect on/off (yes?)
5800 @comment - pgm_word ... shouldn't bank be deduced from address??
5801 Some pic32mx-specific commands are defined:
5802 @deffn Command {pic32mx pgm_word} address value bank
5803 Programs the specified 32-bit @var{value} at the given @var{address}
5804 in the specified chip @var{bank}.
5806 @deffn Command {pic32mx unlock} bank
5807 Unlock and erase specified chip @var{bank}.
5808 This will remove any Code Protection.
5812 @deffn {Flash Driver} psoc4
5813 All members of the PSoC 41xx/42xx microcontroller family from Cypress
5814 include internal flash and use ARM Cortex-M0 cores.
5815 The driver automatically recognizes a number of these chips using
5816 the chip identification register, and autoconfigures itself.
5818 Note: Erased internal flash reads as 00.
5819 System ROM of PSoC 4 does not implement erase of a flash sector.
5822 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
5825 psoc4-specific commands
5826 @deffn Command {psoc4 flash_autoerase} num (on|off)
5827 Enables or disables autoerase mode for a flash bank.
5829 If flash_autoerase is off, use mass_erase before flash programming.
5830 Flash erase command fails if region to erase is not whole flash memory.
5832 If flash_autoerase is on, a sector is both erased and programmed in one
5833 system ROM call. Flash erase command is ignored.
5834 This mode is suitable for gdb load.
5836 The @var{num} parameter is a value shown by @command{flash banks}.
5839 @deffn Command {psoc4 mass_erase} num
5840 Erases the contents of the flash memory, protection and security lock.
5842 The @var{num} parameter is a value shown by @command{flash banks}.
5846 @deffn {Flash Driver} sim3x
5847 All members of the SiM3 microcontroller family from Silicon Laboratories
5848 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
5850 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
5851 If this failes, it will use the @var{size} parameter as the size of flash bank.
5854 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
5857 There are 2 commands defined in the @var{sim3x} driver:
5859 @deffn Command {sim3x mass_erase}
5860 Erases the complete flash. This is used to unlock the flash.
5861 And this command is only possible when using the SWD interface.
5864 @deffn Command {sim3x lock}
5865 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
5869 @deffn {Flash Driver} stellaris
5870 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
5871 families from Texas Instruments include internal flash. The driver
5872 automatically recognizes a number of these chips using the chip
5873 identification register, and autoconfigures itself.
5874 @footnote{Currently there is a @command{stellaris mass_erase} command.
5875 That seems pointless since the same effect can be had using the
5876 standard @command{flash erase_address} command.}
5879 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
5882 @deffn Command {stellaris recover}
5883 Performs the @emph{Recovering a "Locked" Device} procedure to restore
5884 the flash and its associated nonvolatile registers to their factory
5885 default values (erased). This is the only way to remove flash
5886 protection or re-enable debugging if that capability has been
5889 Note that the final "power cycle the chip" step in this procedure
5890 must be performed by hand, since OpenOCD can't do it.
5892 if more than one Stellaris chip is connected, the procedure is
5893 applied to all of them.
5898 @deffn {Flash Driver} stm32f1x
5899 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
5900 from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
5901 The driver automatically recognizes a number of these chips using
5902 the chip identification register, and autoconfigures itself.
5905 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
5908 Note that some devices have been found that have a flash size register that contains
5909 an invalid value, to workaround this issue you can override the probed value used by
5913 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
5916 If you have a target with dual flash banks then define the second bank
5917 as per the following example.
5919 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
5922 Some stm32f1x-specific commands
5923 @footnote{Currently there is a @command{stm32f1x mass_erase} command.
5924 That seems pointless since the same effect can be had using the
5925 standard @command{flash erase_address} command.}
5928 @deffn Command {stm32f1x lock} num
5929 Locks the entire stm32 device.
5930 The @var{num} parameter is a value shown by @command{flash banks}.
5933 @deffn Command {stm32f1x unlock} num
5934 Unlocks the entire stm32 device.
5935 The @var{num} parameter is a value shown by @command{flash banks}.
5938 @deffn Command {stm32f1x options_read} num
5939 Read and display the stm32 option bytes written by
5940 the @command{stm32f1x options_write} command.
5941 The @var{num} parameter is a value shown by @command{flash banks}.
5944 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
5945 Writes the stm32 option byte with the specified values.
5946 The @var{num} parameter is a value shown by @command{flash banks}.
5950 @deffn {Flash Driver} stm32f2x
5951 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from ST Microelectronics
5952 include internal flash and use ARM Cortex-M3/M4/M7 cores.
5953 The driver automatically recognizes a number of these chips using
5954 the chip identification register, and autoconfigures itself.
5956 Note that some devices have been found that have a flash size register that contains
5957 an invalid value, to workaround this issue you can override the probed value used by
5961 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
5964 Some stm32f2x-specific commands are defined:
5966 @deffn Command {stm32f2x lock} num
5967 Locks the entire stm32 device.
5968 The @var{num} parameter is a value shown by @command{flash banks}.
5971 @deffn Command {stm32f2x unlock} num
5972 Unlocks the entire stm32 device.
5973 The @var{num} parameter is a value shown by @command{flash banks}.
5976 @deffn Command {stm32f2x options_read} num
5977 Reads and displays user options and (where implemented) boot_addr0 and boot_addr1.
5978 The @var{num} parameter is a value shown by @command{flash banks}.
5981 @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
5982 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
5983 Warning: The meaning of the various bits depends on the device, always check datasheet!
5984 The @var{num} parameter is a value shown by @command{flash banks}, user_options a
5985 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, boot_addr0 and boot_addr1
5986 two halfwords (of FLASH_OPTCR1).
5990 @deffn {Flash Driver} stm32lx
5991 All members of the STM32L microcontroller families from ST Microelectronics
5992 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
5993 The driver automatically recognizes a number of these chips using
5994 the chip identification register, and autoconfigures itself.
5996 Note that some devices have been found that have a flash size register that contains
5997 an invalid value, to workaround this issue you can override the probed value used by
5998 the flash driver. If you use 0 as the bank base address, it tells the
5999 driver to autodetect the bank location assuming you're configuring the
6003 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
6006 Some stm32lx-specific commands are defined:
6008 @deffn Command {stm32lx mass_erase} num
6009 Mass erases the entire stm32lx device (all flash banks and EEPROM
6010 data). This is the only way to unlock a protected flash (unless RDP
6011 Level is 2 which can't be unlocked at all).
6012 The @var{num} parameter is a value shown by @command{flash banks}.
6016 @deffn {Flash Driver} str7x
6017 All members of the STR7 microcontroller family from ST Microelectronics
6018 include internal flash and use ARM7TDMI cores.
6019 The @var{str7x} driver defines one mandatory parameter, @var{variant},
6020 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
6023 flash bank $_FLASHNAME str7x \
6024 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
6027 @deffn Command {str7x disable_jtag} bank
6028 Activate the Debug/Readout protection mechanism
6029 for the specified flash bank.
6033 @deffn {Flash Driver} str9x
6034 Most members of the STR9 microcontroller family from ST Microelectronics
6035 include internal flash and use ARM966E cores.
6036 The str9 needs the flash controller to be configured using
6037 the @command{str9x flash_config} command prior to Flash programming.
6040 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
6041 str9x flash_config 0 4 2 0 0x80000
6044 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
6045 Configures the str9 flash controller.
6046 The @var{num} parameter is a value shown by @command{flash banks}.
6049 @item @var{bbsr} - Boot Bank Size register
6050 @item @var{nbbsr} - Non Boot Bank Size register
6051 @item @var{bbadr} - Boot Bank Start Address register
6052 @item @var{nbbadr} - Boot Bank Start Address register
6058 @deffn {Flash Driver} str9xpec
6061 Only use this driver for locking/unlocking the device or configuring the option bytes.
6062 Use the standard str9 driver for programming.
6063 Before using the flash commands the turbo mode must be enabled using the
6064 @command{str9xpec enable_turbo} command.
6066 Here is some background info to help
6067 you better understand how this driver works. OpenOCD has two flash drivers for
6071 Standard driver @option{str9x} programmed via the str9 core. Normally used for
6072 flash programming as it is faster than the @option{str9xpec} driver.
6074 Direct programming @option{str9xpec} using the flash controller. This is an
6075 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
6076 core does not need to be running to program using this flash driver. Typical use
6077 for this driver is locking/unlocking the target and programming the option bytes.
6080 Before we run any commands using the @option{str9xpec} driver we must first disable
6081 the str9 core. This example assumes the @option{str9xpec} driver has been
6082 configured for flash bank 0.
6084 # assert srst, we do not want core running
6085 # while accessing str9xpec flash driver
6087 # turn off target polling
6090 str9xpec enable_turbo 0
6092 str9xpec options_read 0
6093 # re-enable str9 core
6094 str9xpec disable_turbo 0
6098 The above example will read the str9 option bytes.
6099 When performing a unlock remember that you will not be able to halt the str9 - it
6100 has been locked. Halting the core is not required for the @option{str9xpec} driver
6101 as mentioned above, just issue the commands above manually or from a telnet prompt.
6103 Several str9xpec-specific commands are defined:
6105 @deffn Command {str9xpec disable_turbo} num
6106 Restore the str9 into JTAG chain.
6109 @deffn Command {str9xpec enable_turbo} num
6110 Enable turbo mode, will simply remove the str9 from the chain and talk
6111 directly to the embedded flash controller.
6114 @deffn Command {str9xpec lock} num
6115 Lock str9 device. The str9 will only respond to an unlock command that will
6119 @deffn Command {str9xpec part_id} num
6120 Prints the part identifier for bank @var{num}.
6123 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
6124 Configure str9 boot bank.
6127 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
6128 Configure str9 lvd source.
6131 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
6132 Configure str9 lvd threshold.
6135 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
6136 Configure str9 lvd reset warning source.
6139 @deffn Command {str9xpec options_read} num
6140 Read str9 option bytes.
6143 @deffn Command {str9xpec options_write} num
6144 Write str9 option bytes.
6147 @deffn Command {str9xpec unlock} num
6153 @deffn {Flash Driver} tms470
6154 Most members of the TMS470 microcontroller family from Texas Instruments
6155 include internal flash and use ARM7TDMI cores.
6156 This driver doesn't require the chip and bus width to be specified.
6158 Some tms470-specific commands are defined:
6160 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
6161 Saves programming keys in a register, to enable flash erase and write commands.
6164 @deffn Command {tms470 osc_mhz} clock_mhz
6165 Reports the clock speed, which is used to calculate timings.
6168 @deffn Command {tms470 plldis} (0|1)
6169 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
6174 @deffn {Flash Driver} xmc1xxx
6175 All members of the XMC1xxx microcontroller family from Infineon.
6176 This driver does not require the chip and bus width to be specified.
6179 @deffn {Flash Driver} xmc4xxx
6180 All members of the XMC4xxx microcontroller family from Infineon.
6181 This driver does not require the chip and bus width to be specified.
6183 Some xmc4xxx-specific commands are defined:
6185 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
6186 Saves flash protection passwords which are used to lock the user flash
6189 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
6190 Removes Flash write protection from the selected user bank
6195 @section NAND Flash Commands
6198 Compared to NOR or SPI flash, NAND devices are inexpensive
6199 and high density. Today's NAND chips, and multi-chip modules,
6200 commonly hold multiple GigaBytes of data.
6202 NAND chips consist of a number of ``erase blocks'' of a given
6203 size (such as 128 KBytes), each of which is divided into a
6204 number of pages (of perhaps 512 or 2048 bytes each). Each
6205 page of a NAND flash has an ``out of band'' (OOB) area to hold
6206 Error Correcting Code (ECC) and other metadata, usually 16 bytes
6207 of OOB for every 512 bytes of page data.
6209 One key characteristic of NAND flash is that its error rate
6210 is higher than that of NOR flash. In normal operation, that
6211 ECC is used to correct and detect errors. However, NAND
6212 blocks can also wear out and become unusable; those blocks
6213 are then marked "bad". NAND chips are even shipped from the
6214 manufacturer with a few bad blocks. The highest density chips
6215 use a technology (MLC) that wears out more quickly, so ECC
6216 support is increasingly important as a way to detect blocks
6217 that have begun to fail, and help to preserve data integrity
6218 with techniques such as wear leveling.
6220 Software is used to manage the ECC. Some controllers don't
6221 support ECC directly; in those cases, software ECC is used.
6222 Other controllers speed up the ECC calculations with hardware.
6223 Single-bit error correction hardware is routine. Controllers
6224 geared for newer MLC chips may correct 4 or more errors for
6225 every 512 bytes of data.
6227 You will need to make sure that any data you write using
6228 OpenOCD includes the apppropriate kind of ECC. For example,
6229 that may mean passing the @code{oob_softecc} flag when
6230 writing NAND data, or ensuring that the correct hardware
6233 The basic steps for using NAND devices include:
6235 @item Declare via the command @command{nand device}
6236 @* Do this in a board-specific configuration file,
6237 passing parameters as needed by the controller.
6238 @item Configure each device using @command{nand probe}.
6239 @* Do this only after the associated target is set up,
6240 such as in its reset-init script or in procures defined
6241 to access that device.
6242 @item Operate on the flash via @command{nand subcommand}
6243 @* Often commands to manipulate the flash are typed by a human, or run
6244 via a script in some automated way. Common task include writing a
6245 boot loader, operating system, or other data needed to initialize or
6249 @b{NOTE:} At the time this text was written, the largest NAND
6250 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
6251 This is because the variables used to hold offsets and lengths
6252 are only 32 bits wide.
6253 (Larger chips may work in some cases, unless an offset or length
6254 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
6255 Some larger devices will work, since they are actually multi-chip
6256 modules with two smaller chips and individual chipselect lines.
6258 @anchor{nandconfiguration}
6259 @subsection NAND Configuration Commands
6260 @cindex NAND configuration
6262 NAND chips must be declared in configuration scripts,
6263 plus some additional configuration that's done after
6264 OpenOCD has initialized.
6266 @deffn {Config Command} {nand device} name driver target [configparams...]
6267 Declares a NAND device, which can be read and written to
6268 after it has been configured through @command{nand probe}.
6269 In OpenOCD, devices are single chips; this is unlike some
6270 operating systems, which may manage multiple chips as if
6271 they were a single (larger) device.
6272 In some cases, configuring a device will activate extra
6273 commands; see the controller-specific documentation.
6275 @b{NOTE:} This command is not available after OpenOCD
6276 initialization has completed. Use it in board specific
6277 configuration files, not interactively.
6280 @item @var{name} ... may be used to reference the NAND bank
6281 in most other NAND commands. A number is also available.
6282 @item @var{driver} ... identifies the NAND controller driver
6283 associated with the NAND device being declared.
6284 @xref{nanddriverlist,,NAND Driver List}.
6285 @item @var{target} ... names the target used when issuing
6286 commands to the NAND controller.
6287 @comment Actually, it's currently a controller-specific parameter...
6288 @item @var{configparams} ... controllers may support, or require,
6289 additional parameters. See the controller-specific documentation
6290 for more information.
6294 @deffn Command {nand list}
6295 Prints a summary of each device declared
6296 using @command{nand device}, numbered from zero.
6297 Note that un-probed devices show no details.
6300 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6301 blocksize: 131072, blocks: 8192
6302 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6303 blocksize: 131072, blocks: 8192
6308 @deffn Command {nand probe} num
6309 Probes the specified device to determine key characteristics
6310 like its page and block sizes, and how many blocks it has.
6311 The @var{num} parameter is the value shown by @command{nand list}.
6312 You must (successfully) probe a device before you can use
6313 it with most other NAND commands.
6316 @subsection Erasing, Reading, Writing to NAND Flash
6318 @deffn Command {nand dump} num filename offset length [oob_option]
6319 @cindex NAND reading
6320 Reads binary data from the NAND device and writes it to the file,
6321 starting at the specified offset.
6322 The @var{num} parameter is the value shown by @command{nand list}.
6324 Use a complete path name for @var{filename}, so you don't depend
6325 on the directory used to start the OpenOCD server.
6327 The @var{offset} and @var{length} must be exact multiples of the
6328 device's page size. They describe a data region; the OOB data
6329 associated with each such page may also be accessed.
6331 @b{NOTE:} At the time this text was written, no error correction
6332 was done on the data that's read, unless raw access was disabled
6333 and the underlying NAND controller driver had a @code{read_page}
6334 method which handled that error correction.
6336 By default, only page data is saved to the specified file.
6337 Use an @var{oob_option} parameter to save OOB data:
6339 @item no oob_* parameter
6340 @*Output file holds only page data; OOB is discarded.
6341 @item @code{oob_raw}
6342 @*Output file interleaves page data and OOB data;
6343 the file will be longer than "length" by the size of the
6344 spare areas associated with each data page.
6345 Note that this kind of "raw" access is different from
6346 what's implied by @command{nand raw_access}, which just
6347 controls whether a hardware-aware access method is used.
6348 @item @code{oob_only}
6349 @*Output file has only raw OOB data, and will
6350 be smaller than "length" since it will contain only the
6351 spare areas associated with each data page.
6355 @deffn Command {nand erase} num [offset length]
6356 @cindex NAND erasing
6357 @cindex NAND programming
6358 Erases blocks on the specified NAND device, starting at the
6359 specified @var{offset} and continuing for @var{length} bytes.
6360 Both of those values must be exact multiples of the device's
6361 block size, and the region they specify must fit entirely in the chip.
6362 If those parameters are not specified,
6363 the whole NAND chip will be erased.
6364 The @var{num} parameter is the value shown by @command{nand list}.
6366 @b{NOTE:} This command will try to erase bad blocks, when told
6367 to do so, which will probably invalidate the manufacturer's bad
6369 For the remainder of the current server session, @command{nand info}
6370 will still report that the block ``is'' bad.
6373 @deffn Command {nand write} num filename offset [option...]
6374 @cindex NAND writing
6375 @cindex NAND programming
6376 Writes binary data from the file into the specified NAND device,
6377 starting at the specified offset. Those pages should already
6378 have been erased; you can't change zero bits to one bits.
6379 The @var{num} parameter is the value shown by @command{nand list}.
6381 Use a complete path name for @var{filename}, so you don't depend
6382 on the directory used to start the OpenOCD server.
6384 The @var{offset} must be an exact multiple of the device's page size.
6385 All data in the file will be written, assuming it doesn't run
6386 past the end of the device.
6387 Only full pages are written, and any extra space in the last
6388 page will be filled with 0xff bytes. (That includes OOB data,
6389 if that's being written.)
6391 @b{NOTE:} At the time this text was written, bad blocks are
6392 ignored. That is, this routine will not skip bad blocks,
6393 but will instead try to write them. This can cause problems.
6395 Provide at most one @var{option} parameter. With some
6396 NAND drivers, the meanings of these parameters may change
6397 if @command{nand raw_access} was used to disable hardware ECC.
6399 @item no oob_* parameter
6400 @*File has only page data, which is written.
6401 If raw acccess is in use, the OOB area will not be written.
6402 Otherwise, if the underlying NAND controller driver has
6403 a @code{write_page} routine, that routine may write the OOB
6404 with hardware-computed ECC data.
6405 @item @code{oob_only}
6406 @*File has only raw OOB data, which is written to the OOB area.
6407 Each page's data area stays untouched. @i{This can be a dangerous
6408 option}, since it can invalidate the ECC data.
6409 You may need to force raw access to use this mode.
6410 @item @code{oob_raw}
6411 @*File interleaves data and OOB data, both of which are written
6412 If raw access is enabled, the data is written first, then the
6414 Otherwise, if the underlying NAND controller driver has
6415 a @code{write_page} routine, that routine may modify the OOB
6416 before it's written, to include hardware-computed ECC data.
6417 @item @code{oob_softecc}
6418 @*File has only page data, which is written.
6419 The OOB area is filled with 0xff, except for a standard 1-bit
6420 software ECC code stored in conventional locations.
6421 You might need to force raw access to use this mode, to prevent
6422 the underlying driver from applying hardware ECC.
6423 @item @code{oob_softecc_kw}
6424 @*File has only page data, which is written.
6425 The OOB area is filled with 0xff, except for a 4-bit software ECC
6426 specific to the boot ROM in Marvell Kirkwood SoCs.
6427 You might need to force raw access to use this mode, to prevent
6428 the underlying driver from applying hardware ECC.
6432 @deffn Command {nand verify} num filename offset [option...]
6433 @cindex NAND verification
6434 @cindex NAND programming
6435 Verify the binary data in the file has been programmed to the
6436 specified NAND device, starting at the specified offset.
6437 The @var{num} parameter is the value shown by @command{nand list}.
6439 Use a complete path name for @var{filename}, so you don't depend
6440 on the directory used to start the OpenOCD server.
6442 The @var{offset} must be an exact multiple of the device's page size.
6443 All data in the file will be read and compared to the contents of the
6444 flash, assuming it doesn't run past the end of the device.
6445 As with @command{nand write}, only full pages are verified, so any extra
6446 space in the last page will be filled with 0xff bytes.
6448 The same @var{options} accepted by @command{nand write},
6449 and the file will be processed similarly to produce the buffers that
6450 can be compared against the contents produced from @command{nand dump}.
6452 @b{NOTE:} This will not work when the underlying NAND controller
6453 driver's @code{write_page} routine must update the OOB with a
6454 hardward-computed ECC before the data is written. This limitation may
6455 be removed in a future release.
6458 @subsection Other NAND commands
6459 @cindex NAND other commands
6461 @deffn Command {nand check_bad_blocks} num [offset length]
6462 Checks for manufacturer bad block markers on the specified NAND
6463 device. If no parameters are provided, checks the whole
6464 device; otherwise, starts at the specified @var{offset} and
6465 continues for @var{length} bytes.
6466 Both of those values must be exact multiples of the device's
6467 block size, and the region they specify must fit entirely in the chip.
6468 The @var{num} parameter is the value shown by @command{nand list}.
6470 @b{NOTE:} Before using this command you should force raw access
6471 with @command{nand raw_access enable} to ensure that the underlying
6472 driver will not try to apply hardware ECC.
6475 @deffn Command {nand info} num
6476 The @var{num} parameter is the value shown by @command{nand list}.
6477 This prints the one-line summary from "nand list", plus for
6478 devices which have been probed this also prints any known
6479 status for each block.
6482 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
6483 Sets or clears an flag affecting how page I/O is done.
6484 The @var{num} parameter is the value shown by @command{nand list}.
6486 This flag is cleared (disabled) by default, but changing that
6487 value won't affect all NAND devices. The key factor is whether
6488 the underlying driver provides @code{read_page} or @code{write_page}
6489 methods. If it doesn't provide those methods, the setting of
6490 this flag is irrelevant; all access is effectively ``raw''.
6492 When those methods exist, they are normally used when reading
6493 data (@command{nand dump} or reading bad block markers) or
6494 writing it (@command{nand write}). However, enabling
6495 raw access (setting the flag) prevents use of those methods,
6496 bypassing hardware ECC logic.
6497 @i{This can be a dangerous option}, since writing blocks
6498 with the wrong ECC data can cause them to be marked as bad.
6501 @anchor{nanddriverlist}
6502 @subsection NAND Driver List
6503 As noted above, the @command{nand device} command allows
6504 driver-specific options and behaviors.
6505 Some controllers also activate controller-specific commands.
6507 @deffn {NAND Driver} at91sam9
6508 This driver handles the NAND controllers found on AT91SAM9 family chips from
6509 Atmel. It takes two extra parameters: address of the NAND chip;
6510 address of the ECC controller.
6512 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
6514 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
6515 @code{read_page} methods are used to utilize the ECC hardware unless they are
6516 disabled by using the @command{nand raw_access} command. There are four
6517 additional commands that are needed to fully configure the AT91SAM9 NAND
6518 controller. Two are optional; most boards use the same wiring for ALE/CLE:
6519 @deffn Command {at91sam9 cle} num addr_line
6520 Configure the address line used for latching commands. The @var{num}
6521 parameter is the value shown by @command{nand list}.
6523 @deffn Command {at91sam9 ale} num addr_line
6524 Configure the address line used for latching addresses. The @var{num}
6525 parameter is the value shown by @command{nand list}.
6528 For the next two commands, it is assumed that the pins have already been
6529 properly configured for input or output.
6530 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
6531 Configure the RDY/nBUSY input from the NAND device. The @var{num}
6532 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6533 is the base address of the PIO controller and @var{pin} is the pin number.
6535 @deffn Command {at91sam9 ce} num pio_base_addr pin
6536 Configure the chip enable input to the NAND device. The @var{num}
6537 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6538 is the base address of the PIO controller and @var{pin} is the pin number.
6542 @deffn {NAND Driver} davinci
6543 This driver handles the NAND controllers found on DaVinci family
6544 chips from Texas Instruments.
6545 It takes three extra parameters:
6546 address of the NAND chip;
6547 hardware ECC mode to use (@option{hwecc1},
6548 @option{hwecc4}, @option{hwecc4_infix});
6549 address of the AEMIF controller on this processor.
6551 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
6553 All DaVinci processors support the single-bit ECC hardware,
6554 and newer ones also support the four-bit ECC hardware.
6555 The @code{write_page} and @code{read_page} methods are used
6556 to implement those ECC modes, unless they are disabled using
6557 the @command{nand raw_access} command.
6560 @deffn {NAND Driver} lpc3180
6561 These controllers require an extra @command{nand device}
6562 parameter: the clock rate used by the controller.
6563 @deffn Command {lpc3180 select} num [mlc|slc]
6564 Configures use of the MLC or SLC controller mode.
6565 MLC implies use of hardware ECC.
6566 The @var{num} parameter is the value shown by @command{nand list}.
6569 At this writing, this driver includes @code{write_page}
6570 and @code{read_page} methods. Using @command{nand raw_access}
6571 to disable those methods will prevent use of hardware ECC
6572 in the MLC controller mode, but won't change SLC behavior.
6574 @comment current lpc3180 code won't issue 5-byte address cycles
6576 @deffn {NAND Driver} mx3
6577 This driver handles the NAND controller in i.MX31. The mxc driver
6578 should work for this chip aswell.
6581 @deffn {NAND Driver} mxc
6582 This driver handles the NAND controller found in Freescale i.MX
6583 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
6584 The driver takes 3 extra arguments, chip (@option{mx27},
6585 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
6586 and optionally if bad block information should be swapped between
6587 main area and spare area (@option{biswap}), defaults to off.
6589 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
6591 @deffn Command {mxc biswap} bank_num [enable|disable]
6592 Turns on/off bad block information swaping from main area,
6593 without parameter query status.
6597 @deffn {NAND Driver} orion
6598 These controllers require an extra @command{nand device}
6599 parameter: the address of the controller.
6601 nand device orion 0xd8000000
6603 These controllers don't define any specialized commands.
6604 At this writing, their drivers don't include @code{write_page}
6605 or @code{read_page} methods, so @command{nand raw_access} won't
6606 change any behavior.
6609 @deffn {NAND Driver} s3c2410
6610 @deffnx {NAND Driver} s3c2412
6611 @deffnx {NAND Driver} s3c2440
6612 @deffnx {NAND Driver} s3c2443
6613 @deffnx {NAND Driver} s3c6400
6614 These S3C family controllers don't have any special
6615 @command{nand device} options, and don't define any
6616 specialized commands.
6617 At this writing, their drivers don't include @code{write_page}
6618 or @code{read_page} methods, so @command{nand raw_access} won't
6619 change any behavior.
6624 @subsection mFlash Configuration
6625 @cindex mFlash Configuration
6627 @deffn {Config Command} {mflash bank} soc base RST_pin target
6628 Configures a mflash for @var{soc} host bank at
6630 The pin number format depends on the host GPIO naming convention.
6631 Currently, the mflash driver supports s3c2440 and pxa270.
6633 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
6636 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
6639 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
6642 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
6646 @subsection mFlash commands
6647 @cindex mFlash commands
6649 @deffn Command {mflash config pll} frequency
6650 Configure mflash PLL.
6651 The @var{frequency} is the mflash input frequency, in Hz.
6652 Issuing this command will erase mflash's whole internal nand and write new pll.
6653 After this command, mflash needs power-on-reset for normal operation.
6654 If pll was newly configured, storage and boot(optional) info also need to be update.
6657 @deffn Command {mflash config boot}
6658 Configure bootable option.
6659 If bootable option is set, mflash offer the first 8 sectors
6663 @deffn Command {mflash config storage}
6664 Configure storage information.
6665 For the normal storage operation, this information must be
6669 @deffn Command {mflash dump} num filename offset size
6670 Dump @var{size} bytes, starting at @var{offset} bytes from the
6671 beginning of the bank @var{num}, to the file named @var{filename}.
6674 @deffn Command {mflash probe}
6678 @deffn Command {mflash write} num filename offset
6679 Write the binary file @var{filename} to mflash bank @var{num}, starting at
6680 @var{offset} bytes from the beginning of the bank.
6683 @node Flash Programming
6684 @chapter Flash Programming
6686 OpenOCD implements numerous ways to program the target flash, whether internal or external.
6687 Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
6688 or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
6690 @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
6691 OpenOCD will program/verify/reset the target and optionally shutdown.
6693 The script is executed as follows and by default the following actions will be peformed.
6695 @item 'init' is executed.
6696 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
6697 @item @code{flash write_image} is called to erase and write any flash using the filename given.
6698 @item @code{verify_image} is called if @option{verify} parameter is given.
6699 @item @code{reset run} is called if @option{reset} parameter is given.
6700 @item OpenOCD is shutdown if @option{exit} parameter is given.
6703 An example of usage is given below. @xref{program}.
6706 # program and verify using elf/hex/s19. verify and reset
6707 # are optional parameters
6708 openocd -f board/stm32f3discovery.cfg \
6709 -c "program filename.elf verify reset exit"
6711 # binary files need the flash address passing
6712 openocd -f board/stm32f3discovery.cfg \
6713 -c "program filename.bin exit 0x08000000"
6716 @node PLD/FPGA Commands
6717 @chapter PLD/FPGA Commands
6721 Programmable Logic Devices (PLDs) and the more flexible
6722 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
6723 OpenOCD can support programming them.
6724 Although PLDs are generally restrictive (cells are less functional, and
6725 there are no special purpose cells for memory or computational tasks),
6726 they share the same OpenOCD infrastructure.
6727 Accordingly, both are called PLDs here.
6729 @section PLD/FPGA Configuration and Commands
6731 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
6732 OpenOCD maintains a list of PLDs available for use in various commands.
6733 Also, each such PLD requires a driver.
6735 They are referenced by the number shown by the @command{pld devices} command,
6736 and new PLDs are defined by @command{pld device driver_name}.
6738 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
6739 Defines a new PLD device, supported by driver @var{driver_name},
6740 using the TAP named @var{tap_name}.
6741 The driver may make use of any @var{driver_options} to configure its
6745 @deffn {Command} {pld devices}
6746 Lists the PLDs and their numbers.
6749 @deffn {Command} {pld load} num filename
6750 Loads the file @file{filename} into the PLD identified by @var{num}.
6751 The file format must be inferred by the driver.
6754 @section PLD/FPGA Drivers, Options, and Commands
6756 Drivers may support PLD-specific options to the @command{pld device}
6757 definition command, and may also define commands usable only with
6758 that particular type of PLD.
6760 @deffn {FPGA Driver} virtex2 [no_jstart]
6761 Virtex-II is a family of FPGAs sold by Xilinx.
6762 It supports the IEEE 1532 standard for In-System Configuration (ISC).
6764 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
6765 loading the bitstream. While required for Series2, Series3, and Series6, it
6766 breaks bitstream loading on Series7.
6768 @deffn {Command} {virtex2 read_stat} num
6769 Reads and displays the Virtex-II status register (STAT)
6774 @node General Commands
6775 @chapter General Commands
6778 The commands documented in this chapter here are common commands that
6779 you, as a human, may want to type and see the output of. Configuration type
6780 commands are documented elsewhere.
6784 @item @b{Source Of Commands}
6785 @* OpenOCD commands can occur in a configuration script (discussed
6786 elsewhere) or typed manually by a human or supplied programatically,
6787 or via one of several TCP/IP Ports.
6789 @item @b{From the human}
6790 @* A human should interact with the telnet interface (default port: 4444)
6791 or via GDB (default port 3333).
6793 To issue commands from within a GDB session, use the @option{monitor}
6794 command, e.g. use @option{monitor poll} to issue the @option{poll}
6795 command. All output is relayed through the GDB session.
6797 @item @b{Machine Interface}
6798 The Tcl interface's intent is to be a machine interface. The default Tcl
6803 @section Server Commands
6805 @deffn {Command} exit
6806 Exits the current telnet session.
6809 @deffn {Command} help [string]
6810 With no parameters, prints help text for all commands.
6811 Otherwise, prints each helptext containing @var{string}.
6812 Not every command provides helptext.
6814 Configuration commands, and commands valid at any time, are
6815 explicitly noted in parenthesis.
6816 In most cases, no such restriction is listed; this indicates commands
6817 which are only available after the configuration stage has completed.
6820 @deffn Command sleep msec [@option{busy}]
6821 Wait for at least @var{msec} milliseconds before resuming.
6822 If @option{busy} is passed, busy-wait instead of sleeping.
6823 (This option is strongly discouraged.)
6824 Useful in connection with script files
6825 (@command{script} command and @command{target_name} configuration).
6828 @deffn Command shutdown [@option{error}]
6829 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
6830 other). If option @option{error} is used, OpenOCD will return a
6831 non-zero exit code to the parent process.
6835 @deffn Command debug_level [n]
6836 @cindex message level
6837 Display debug level.
6838 If @var{n} (from 0..3) is provided, then set it to that level.
6839 This affects the kind of messages sent to the server log.
6840 Level 0 is error messages only;
6841 level 1 adds warnings;
6842 level 2 adds informational messages;
6843 and level 3 adds debugging messages.
6844 The default is level 2, but that can be overridden on
6845 the command line along with the location of that log
6846 file (which is normally the server's standard output).
6850 @deffn Command echo [-n] message
6851 Logs a message at "user" priority.
6852 Output @var{message} to stdout.
6853 Option "-n" suppresses trailing newline.
6855 echo "Downloading kernel -- please wait"
6859 @deffn Command log_output [filename]
6860 Redirect logging to @var{filename};
6861 the initial log output channel is stderr.
6864 @deffn Command add_script_search_dir [directory]
6865 Add @var{directory} to the file/script search path.
6868 @deffn Command bindto [name]
6869 Specify address by name on which to listen for incoming TCP/IP connections.
6870 By default, OpenOCD will listen on all available interfaces.
6873 @anchor{targetstatehandling}
6874 @section Target State handling
6877 @cindex target initialization
6879 In this section ``target'' refers to a CPU configured as
6880 shown earlier (@pxref{CPU Configuration}).
6881 These commands, like many, implicitly refer to
6882 a current target which is used to perform the
6883 various operations. The current target may be changed
6884 by using @command{targets} command with the name of the
6885 target which should become current.
6887 @deffn Command reg [(number|name) [(value|'force')]]
6888 Access a single register by @var{number} or by its @var{name}.
6889 The target must generally be halted before access to CPU core
6890 registers is allowed. Depending on the hardware, some other
6891 registers may be accessible while the target is running.
6893 @emph{With no arguments}:
6894 list all available registers for the current target,
6895 showing number, name, size, value, and cache status.
6896 For valid entries, a value is shown; valid entries
6897 which are also dirty (and will be written back later)
6898 are flagged as such.
6900 @emph{With number/name}: display that register's value.
6901 Use @var{force} argument to read directly from the target,
6902 bypassing any internal cache.
6904 @emph{With both number/name and value}: set register's value.
6905 Writes may be held in a writeback cache internal to OpenOCD,
6906 so that setting the value marks the register as dirty instead
6907 of immediately flushing that value. Resuming CPU execution
6908 (including by single stepping) or otherwise activating the
6909 relevant module will flush such values.
6911 Cores may have surprisingly many registers in their
6912 Debug and trace infrastructure:
6917 (0) r0 (/32): 0x0000D3C2 (dirty)
6918 (1) r1 (/32): 0xFD61F31C
6921 (164) ETM_contextid_comparator_mask (/32)
6926 @deffn Command halt [ms]
6927 @deffnx Command wait_halt [ms]
6928 The @command{halt} command first sends a halt request to the target,
6929 which @command{wait_halt} doesn't.
6930 Otherwise these behave the same: wait up to @var{ms} milliseconds,
6931 or 5 seconds if there is no parameter, for the target to halt
6932 (and enter debug mode).
6933 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
6936 On ARM cores, software using the @emph{wait for interrupt} operation
6937 often blocks the JTAG access needed by a @command{halt} command.
6938 This is because that operation also puts the core into a low
6939 power mode by gating the core clock;
6940 but the core clock is needed to detect JTAG clock transitions.
6942 One partial workaround uses adaptive clocking: when the core is
6943 interrupted the operation completes, then JTAG clocks are accepted
6944 at least until the interrupt handler completes.
6945 However, this workaround is often unusable since the processor, board,
6946 and JTAG adapter must all support adaptive JTAG clocking.
6947 Also, it can't work until an interrupt is issued.
6949 A more complete workaround is to not use that operation while you
6950 work with a JTAG debugger.
6951 Tasking environments generaly have idle loops where the body is the
6952 @emph{wait for interrupt} operation.
6953 (On older cores, it is a coprocessor action;
6954 newer cores have a @option{wfi} instruction.)
6955 Such loops can just remove that operation, at the cost of higher
6956 power consumption (because the CPU is needlessly clocked).
6961 @deffn Command resume [address]
6962 Resume the target at its current code position,
6963 or the optional @var{address} if it is provided.
6964 OpenOCD will wait 5 seconds for the target to resume.
6967 @deffn Command step [address]
6968 Single-step the target at its current code position,
6969 or the optional @var{address} if it is provided.
6972 @anchor{resetcommand}
6973 @deffn Command reset
6974 @deffnx Command {reset run}
6975 @deffnx Command {reset halt}
6976 @deffnx Command {reset init}
6977 Perform as hard a reset as possible, using SRST if possible.
6978 @emph{All defined targets will be reset, and target
6979 events will fire during the reset sequence.}
6981 The optional parameter specifies what should
6982 happen after the reset.
6983 If there is no parameter, a @command{reset run} is executed.
6984 The other options will not work on all systems.
6985 @xref{Reset Configuration}.
6988 @item @b{run} Let the target run
6989 @item @b{halt} Immediately halt the target
6990 @item @b{init} Immediately halt the target, and execute the reset-init script
6994 @deffn Command soft_reset_halt
6995 Requesting target halt and executing a soft reset. This is often used
6996 when a target cannot be reset and halted. The target, after reset is
6997 released begins to execute code. OpenOCD attempts to stop the CPU and
6998 then sets the program counter back to the reset vector. Unfortunately
6999 the code that was executed may have left the hardware in an unknown
7003 @section I/O Utilities
7005 These commands are available when
7006 OpenOCD is built with @option{--enable-ioutil}.
7007 They are mainly useful on embedded targets,
7009 Hosts with operating systems have complementary tools.
7011 @emph{Note:} there are several more such commands.
7013 @deffn Command append_file filename [string]*
7014 Appends the @var{string} parameters to
7015 the text file @file{filename}.
7016 Each string except the last one is followed by one space.
7017 The last string is followed by a newline.
7020 @deffn Command cat filename
7021 Reads and displays the text file @file{filename}.
7024 @deffn Command cp src_filename dest_filename
7025 Copies contents from the file @file{src_filename}
7026 into @file{dest_filename}.
7030 @emph{No description provided.}
7034 @emph{No description provided.}
7038 @emph{No description provided.}
7041 @deffn Command meminfo
7042 Display available RAM memory on OpenOCD host.
7043 Used in OpenOCD regression testing scripts.
7047 @emph{No description provided.}
7051 @emph{No description provided.}
7054 @deffn Command rm filename
7055 @c "rm" has both normal and Jim-level versions??
7056 Unlinks the file @file{filename}.
7059 @deffn Command trunc filename
7060 Removes all data in the file @file{filename}.
7063 @anchor{memoryaccess}
7064 @section Memory access commands
7065 @cindex memory access
7067 These commands allow accesses of a specific size to the memory
7068 system. Often these are used to configure the current target in some
7069 special way. For example - one may need to write certain values to the
7070 SDRAM controller to enable SDRAM.
7073 @item Use the @command{targets} (plural) command
7074 to change the current target.
7075 @item In system level scripts these commands are deprecated.
7076 Please use their TARGET object siblings to avoid making assumptions
7077 about what TAP is the current target, or about MMU configuration.
7080 @deffn Command mdw [phys] addr [count]
7081 @deffnx Command mdh [phys] addr [count]
7082 @deffnx Command mdb [phys] addr [count]
7083 Display contents of address @var{addr}, as
7084 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
7085 or 8-bit bytes (@command{mdb}).
7086 When the current target has an MMU which is present and active,
7087 @var{addr} is interpreted as a virtual address.
7088 Otherwise, or if the optional @var{phys} flag is specified,
7089 @var{addr} is interpreted as a physical address.
7090 If @var{count} is specified, displays that many units.
7091 (If you want to manipulate the data instead of displaying it,
7092 see the @code{mem2array} primitives.)
7095 @deffn Command mww [phys] addr word
7096 @deffnx Command mwh [phys] addr halfword
7097 @deffnx Command mwb [phys] addr byte
7098 Writes the specified @var{word} (32 bits),
7099 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
7100 at the specified address @var{addr}.
7101 When the current target has an MMU which is present and active,
7102 @var{addr} is interpreted as a virtual address.
7103 Otherwise, or if the optional @var{phys} flag is specified,
7104 @var{addr} is interpreted as a physical address.
7107 @anchor{imageaccess}
7108 @section Image loading commands
7109 @cindex image loading
7110 @cindex image dumping
7112 @deffn Command {dump_image} filename address size
7113 Dump @var{size} bytes of target memory starting at @var{address} to the
7114 binary file named @var{filename}.
7117 @deffn Command {fast_load}
7118 Loads an image stored in memory by @command{fast_load_image} to the
7119 current target. Must be preceeded by fast_load_image.
7122 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
7123 Normally you should be using @command{load_image} or GDB load. However, for
7124 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
7125 host), storing the image in memory and uploading the image to the target
7126 can be a way to upload e.g. multiple debug sessions when the binary does not change.
7127 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
7128 memory, i.e. does not affect target. This approach is also useful when profiling
7129 target programming performance as I/O and target programming can easily be profiled
7133 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
7134 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
7135 The file format may optionally be specified
7136 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
7137 In addition the following arguments may be specifed:
7138 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
7139 @var{max_length} - maximum number of bytes to load.
7141 proc load_image_bin @{fname foffset address length @} @{
7142 # Load data from fname filename at foffset offset to
7143 # target at address. Load at most length bytes.
7144 load_image $fname [expr $address - $foffset] bin \
7150 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
7151 Displays image section sizes and addresses
7152 as if @var{filename} were loaded into target memory
7153 starting at @var{address} (defaults to zero).
7154 The file format may optionally be specified
7155 (@option{bin}, @option{ihex}, or @option{elf})
7158 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
7159 Verify @var{filename} against target memory starting at @var{address}.
7160 The file format may optionally be specified
7161 (@option{bin}, @option{ihex}, or @option{elf})
7162 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
7165 @deffn Command {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
7166 Verify @var{filename} against target memory starting at @var{address}.
7167 The file format may optionally be specified
7168 (@option{bin}, @option{ihex}, or @option{elf})
7169 This perform a comparison using a CRC checksum only
7173 @section Breakpoint and Watchpoint commands
7177 CPUs often make debug modules accessible through JTAG, with
7178 hardware support for a handful of code breakpoints and data
7180 In addition, CPUs almost always support software breakpoints.
7182 @deffn Command {bp} [address len [@option{hw}]]
7183 With no parameters, lists all active breakpoints.
7184 Else sets a breakpoint on code execution starting
7185 at @var{address} for @var{length} bytes.
7186 This is a software breakpoint, unless @option{hw} is specified
7187 in which case it will be a hardware breakpoint.
7189 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
7190 for similar mechanisms that do not consume hardware breakpoints.)
7193 @deffn Command {rbp} address
7194 Remove the breakpoint at @var{address}.
7197 @deffn Command {rwp} address
7198 Remove data watchpoint on @var{address}
7201 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
7202 With no parameters, lists all active watchpoints.
7203 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
7204 The watch point is an "access" watchpoint unless
7205 the @option{r} or @option{w} parameter is provided,
7206 defining it as respectively a read or write watchpoint.
7207 If a @var{value} is provided, that value is used when determining if
7208 the watchpoint should trigger. The value may be first be masked
7209 using @var{mask} to mark ``don't care'' fields.
7212 @section Misc Commands
7215 @deffn Command {profile} seconds filename [start end]
7216 Profiling samples the CPU's program counter as quickly as possible,
7217 which is useful for non-intrusive stochastic profiling.
7218 Saves up to 10000 samples in @file{filename} using ``gmon.out''
7219 format. Optional @option{start} and @option{end} parameters allow to
7220 limit the address range.
7223 @deffn Command {version}
7224 Displays a string identifying the version of this OpenOCD server.
7227 @deffn Command {virt2phys} virtual_address
7228 Requests the current target to map the specified @var{virtual_address}
7229 to its corresponding physical address, and displays the result.
7232 @node Architecture and Core Commands
7233 @chapter Architecture and Core Commands
7234 @cindex Architecture Specific Commands
7235 @cindex Core Specific Commands
7237 Most CPUs have specialized JTAG operations to support debugging.
7238 OpenOCD packages most such operations in its standard command framework.
7239 Some of those operations don't fit well in that framework, so they are
7240 exposed here as architecture or implementation (core) specific commands.
7242 @anchor{armhardwaretracing}
7243 @section ARM Hardware Tracing
7248 CPUs based on ARM cores may include standard tracing interfaces,
7249 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
7250 address and data bus trace records to a ``Trace Port''.
7254 Development-oriented boards will sometimes provide a high speed
7255 trace connector for collecting that data, when the particular CPU
7256 supports such an interface.
7257 (The standard connector is a 38-pin Mictor, with both JTAG
7258 and trace port support.)
7259 Those trace connectors are supported by higher end JTAG adapters
7260 and some logic analyzer modules; frequently those modules can
7261 buffer several megabytes of trace data.
7262 Configuring an ETM coupled to such an external trace port belongs
7263 in the board-specific configuration file.
7265 If the CPU doesn't provide an external interface, it probably
7266 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
7267 dedicated SRAM. 4KBytes is one common ETB size.
7268 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
7269 (target) configuration file, since it works the same on all boards.
7272 ETM support in OpenOCD doesn't seem to be widely used yet.
7275 ETM support may be buggy, and at least some @command{etm config}
7276 parameters should be detected by asking the ETM for them.
7278 ETM trigger events could also implement a kind of complex
7279 hardware breakpoint, much more powerful than the simple
7280 watchpoint hardware exported by EmbeddedICE modules.
7281 @emph{Such breakpoints can be triggered even when using the
7282 dummy trace port driver}.
7284 It seems like a GDB hookup should be possible,
7285 as well as tracing only during specific states
7286 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
7288 There should be GUI tools to manipulate saved trace data and help
7289 analyse it in conjunction with the source code.
7290 It's unclear how much of a common interface is shared
7291 with the current XScale trace support, or should be
7292 shared with eventual Nexus-style trace module support.
7294 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
7295 for ETM modules is available. The code should be able to
7296 work with some newer cores; but not all of them support
7297 this original style of JTAG access.
7300 @subsection ETM Configuration
7301 ETM setup is coupled with the trace port driver configuration.
7303 @deffn {Config Command} {etm config} target width mode clocking driver
7304 Declares the ETM associated with @var{target}, and associates it
7305 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
7307 Several of the parameters must reflect the trace port capabilities,
7308 which are a function of silicon capabilties (exposed later
7309 using @command{etm info}) and of what hardware is connected to
7310 that port (such as an external pod, or ETB).
7311 The @var{width} must be either 4, 8, or 16,
7312 except with ETMv3.0 and newer modules which may also
7313 support 1, 2, 24, 32, 48, and 64 bit widths.
7314 (With those versions, @command{etm info} also shows whether
7315 the selected port width and mode are supported.)
7317 The @var{mode} must be @option{normal}, @option{multiplexed},
7318 or @option{demultiplexed}.
7319 The @var{clocking} must be @option{half} or @option{full}.
7322 With ETMv3.0 and newer, the bits set with the @var{mode} and
7323 @var{clocking} parameters both control the mode.
7324 This modified mode does not map to the values supported by
7325 previous ETM modules, so this syntax is subject to change.
7329 You can see the ETM registers using the @command{reg} command.
7330 Not all possible registers are present in every ETM.
7331 Most of the registers are write-only, and are used to configure
7332 what CPU activities are traced.
7336 @deffn Command {etm info}
7337 Displays information about the current target's ETM.
7338 This includes resource counts from the @code{ETM_CONFIG} register,
7339 as well as silicon capabilities (except on rather old modules).
7340 from the @code{ETM_SYS_CONFIG} register.
7343 @deffn Command {etm status}
7344 Displays status of the current target's ETM and trace port driver:
7345 is the ETM idle, or is it collecting data?
7346 Did trace data overflow?
7350 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
7351 Displays what data that ETM will collect.
7352 If arguments are provided, first configures that data.
7353 When the configuration changes, tracing is stopped
7354 and any buffered trace data is invalidated.
7357 @item @var{type} ... describing how data accesses are traced,
7358 when they pass any ViewData filtering that that was set up.
7360 @option{none} (save nothing),
7361 @option{data} (save data),
7362 @option{address} (save addresses),
7363 @option{all} (save data and addresses)
7364 @item @var{context_id_bits} ... 0, 8, 16, or 32
7365 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
7366 cycle-accurate instruction tracing.
7367 Before ETMv3, enabling this causes much extra data to be recorded.
7368 @item @var{branch_output} ... @option{enable} or @option{disable}.
7369 Disable this unless you need to try reconstructing the instruction
7370 trace stream without an image of the code.
7374 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
7375 Displays whether ETM triggering debug entry (like a breakpoint) is
7376 enabled or disabled, after optionally modifying that configuration.
7377 The default behaviour is @option{disable}.
7378 Any change takes effect after the next @command{etm start}.
7380 By using script commands to configure ETM registers, you can make the
7381 processor enter debug state automatically when certain conditions,
7382 more complex than supported by the breakpoint hardware, happen.
7385 @subsection ETM Trace Operation
7387 After setting up the ETM, you can use it to collect data.
7388 That data can be exported to files for later analysis.
7389 It can also be parsed with OpenOCD, for basic sanity checking.
7391 To configure what is being traced, you will need to write
7392 various trace registers using @command{reg ETM_*} commands.
7393 For the definitions of these registers, read ARM publication
7394 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
7395 Be aware that most of the relevant registers are write-only,
7396 and that ETM resources are limited. There are only a handful
7397 of address comparators, data comparators, counters, and so on.
7399 Examples of scenarios you might arrange to trace include:
7402 @item Code flow within a function, @emph{excluding} subroutines
7403 it calls. Use address range comparators to enable tracing
7404 for instruction access within that function's body.
7405 @item Code flow within a function, @emph{including} subroutines
7406 it calls. Use the sequencer and address comparators to activate
7407 tracing on an ``entered function'' state, then deactivate it by
7408 exiting that state when the function's exit code is invoked.
7409 @item Code flow starting at the fifth invocation of a function,
7410 combining one of the above models with a counter.
7411 @item CPU data accesses to the registers for a particular device,
7412 using address range comparators and the ViewData logic.
7413 @item Such data accesses only during IRQ handling, combining the above
7414 model with sequencer triggers which on entry and exit to the IRQ handler.
7415 @item @emph{... more}
7418 At this writing, September 2009, there are no Tcl utility
7419 procedures to help set up any common tracing scenarios.
7421 @deffn Command {etm analyze}
7422 Reads trace data into memory, if it wasn't already present.
7423 Decodes and prints the data that was collected.
7426 @deffn Command {etm dump} filename
7427 Stores the captured trace data in @file{filename}.
7430 @deffn Command {etm image} filename [base_address] [type]
7431 Opens an image file.
7434 @deffn Command {etm load} filename
7435 Loads captured trace data from @file{filename}.
7438 @deffn Command {etm start}
7439 Starts trace data collection.
7442 @deffn Command {etm stop}
7443 Stops trace data collection.
7446 @anchor{traceportdrivers}
7447 @subsection Trace Port Drivers
7449 To use an ETM trace port it must be associated with a driver.
7451 @deffn {Trace Port Driver} dummy
7452 Use the @option{dummy} driver if you are configuring an ETM that's
7453 not connected to anything (on-chip ETB or off-chip trace connector).
7454 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
7455 any trace data collection.}
7456 @deffn {Config Command} {etm_dummy config} target
7457 Associates the ETM for @var{target} with a dummy driver.
7461 @deffn {Trace Port Driver} etb
7462 Use the @option{etb} driver if you are configuring an ETM
7463 to use on-chip ETB memory.
7464 @deffn {Config Command} {etb config} target etb_tap
7465 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
7466 You can see the ETB registers using the @command{reg} command.
7468 @deffn Command {etb trigger_percent} [percent]
7469 This displays, or optionally changes, ETB behavior after the
7470 ETM's configured @emph{trigger} event fires.
7471 It controls how much more trace data is saved after the (single)
7472 trace trigger becomes active.
7475 @item The default corresponds to @emph{trace around} usage,
7476 recording 50 percent data before the event and the rest
7478 @item The minimum value of @var{percent} is 2 percent,
7479 recording almost exclusively data before the trigger.
7480 Such extreme @emph{trace before} usage can help figure out
7481 what caused that event to happen.
7482 @item The maximum value of @var{percent} is 100 percent,
7483 recording data almost exclusively after the event.
7484 This extreme @emph{trace after} usage might help sort out
7485 how the event caused trouble.
7487 @c REVISIT allow "break" too -- enter debug mode.
7492 @deffn {Trace Port Driver} oocd_trace
7493 This driver isn't available unless OpenOCD was explicitly configured
7494 with the @option{--enable-oocd_trace} option. You probably don't want
7495 to configure it unless you've built the appropriate prototype hardware;
7496 it's @emph{proof-of-concept} software.
7498 Use the @option{oocd_trace} driver if you are configuring an ETM that's
7499 connected to an off-chip trace connector.
7501 @deffn {Config Command} {oocd_trace config} target tty
7502 Associates the ETM for @var{target} with a trace driver which
7503 collects data through the serial port @var{tty}.
7506 @deffn Command {oocd_trace resync}
7507 Re-synchronizes with the capture clock.
7510 @deffn Command {oocd_trace status}
7511 Reports whether the capture clock is locked or not.
7516 @section Generic ARM
7519 These commands should be available on all ARM processors.
7520 They are available in addition to other core-specific
7521 commands that may be available.
7523 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
7524 Displays the core_state, optionally changing it to process
7525 either @option{arm} or @option{thumb} instructions.
7526 The target may later be resumed in the currently set core_state.
7527 (Processors may also support the Jazelle state, but
7528 that is not currently supported in OpenOCD.)
7531 @deffn Command {arm disassemble} address [count [@option{thumb}]]
7533 Disassembles @var{count} instructions starting at @var{address}.
7534 If @var{count} is not specified, a single instruction is disassembled.
7535 If @option{thumb} is specified, or the low bit of the address is set,
7536 Thumb2 (mixed 16/32-bit) instructions are used;
7537 else ARM (32-bit) instructions are used.
7538 (Processors may also support the Jazelle state, but
7539 those instructions are not currently understood by OpenOCD.)
7541 Note that all Thumb instructions are Thumb2 instructions,
7542 so older processors (without Thumb2 support) will still
7543 see correct disassembly of Thumb code.
7544 Also, ThumbEE opcodes are the same as Thumb2,
7545 with a handful of exceptions.
7546 ThumbEE disassembly currently has no explicit support.
7549 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
7550 Write @var{value} to a coprocessor @var{pX} register
7551 passing parameters @var{CRn},
7552 @var{CRm}, opcodes @var{opc1} and @var{opc2},
7553 and using the MCR instruction.
7554 (Parameter sequence matches the ARM instruction, but omits
7558 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
7559 Read a coprocessor @var{pX} register passing parameters @var{CRn},
7560 @var{CRm}, opcodes @var{opc1} and @var{opc2},
7561 and the MRC instruction.
7562 Returns the result so it can be manipulated by Jim scripts.
7563 (Parameter sequence matches the ARM instruction, but omits
7567 @deffn Command {arm reg}
7568 Display a table of all banked core registers, fetching the current value from every
7569 core mode if necessary.
7572 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
7573 @cindex ARM semihosting
7574 Display status of semihosting, after optionally changing that status.
7576 Semihosting allows for code executing on an ARM target to use the
7577 I/O facilities on the host computer i.e. the system where OpenOCD
7578 is running. The target application must be linked against a library
7579 implementing the ARM semihosting convention that forwards operation
7580 requests by using a special SVC instruction that is trapped at the
7581 Supervisor Call vector by OpenOCD.
7584 @deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
7585 @cindex ARM semihosting
7586 Display status of semihosting fileio, after optionally changing that
7589 Enabling this option forwards semihosting I/O to GDB process using the
7590 File-I/O remote protocol extension. This is especially useful for
7591 interacting with remote files or displaying console messages in the
7595 @section ARMv4 and ARMv5 Architecture
7599 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
7600 and introduced core parts of the instruction set in use today.
7601 That includes the Thumb instruction set, introduced in the ARMv4T
7604 @subsection ARM7 and ARM9 specific commands
7608 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
7609 ARM9TDMI, ARM920T or ARM926EJ-S.
7610 They are available in addition to the ARM commands,
7611 and any other core-specific commands that may be available.
7613 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
7614 Displays the value of the flag controlling use of the
7615 the EmbeddedIce DBGRQ signal to force entry into debug mode,
7616 instead of breakpoints.
7617 If a boolean parameter is provided, first assigns that flag.
7620 safe for all but ARM7TDMI-S cores (like NXP LPC).
7621 This feature is enabled by default on most ARM9 cores,
7622 including ARM9TDMI, ARM920T, and ARM926EJ-S.
7625 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
7627 Displays the value of the flag controlling use of the debug communications
7628 channel (DCC) to write larger (>128 byte) amounts of memory.
7629 If a boolean parameter is provided, first assigns that flag.
7631 DCC downloads offer a huge speed increase, but might be
7632 unsafe, especially with targets running at very low speeds. This command was introduced
7633 with OpenOCD rev. 60, and requires a few bytes of working area.
7636 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
7637 Displays the value of the flag controlling use of memory writes and reads
7638 that don't check completion of the operation.
7639 If a boolean parameter is provided, first assigns that flag.
7641 This provides a huge speed increase, especially with USB JTAG
7642 cables (FT2232), but might be unsafe if used with targets running at very low
7643 speeds, like the 32kHz startup clock of an AT91RM9200.
7646 @subsection ARM720T specific commands
7649 These commands are available to ARM720T based CPUs,
7650 which are implementations of the ARMv4T architecture
7651 based on the ARM7TDMI-S integer core.
7652 They are available in addition to the ARM and ARM7/ARM9 commands.
7654 @deffn Command {arm720t cp15} opcode [value]
7655 @emph{DEPRECATED -- avoid using this.
7656 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7658 Display cp15 register returned by the ARM instruction @var{opcode};
7659 else if a @var{value} is provided, that value is written to that register.
7660 The @var{opcode} should be the value of either an MRC or MCR instruction.
7663 @subsection ARM9 specific commands
7666 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
7668 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
7670 @c 9-june-2009: tried this on arm920t, it didn't work.
7671 @c no-params always lists nothing caught, and that's how it acts.
7672 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
7673 @c versions have different rules about when they commit writes.
7675 @anchor{arm9vectorcatch}
7676 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
7677 @cindex vector_catch
7678 Vector Catch hardware provides a sort of dedicated breakpoint
7679 for hardware events such as reset, interrupt, and abort.
7680 You can use this to conserve normal breakpoint resources,
7681 so long as you're not concerned with code that branches directly
7682 to those hardware vectors.
7684 This always finishes by listing the current configuration.
7685 If parameters are provided, it first reconfigures the
7686 vector catch hardware to intercept
7687 @option{all} of the hardware vectors,
7688 @option{none} of them,
7689 or a list with one or more of the following:
7690 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
7691 @option{irq} @option{fiq}.
7694 @subsection ARM920T specific commands
7697 These commands are available to ARM920T based CPUs,
7698 which are implementations of the ARMv4T architecture
7699 built using the ARM9TDMI integer core.
7700 They are available in addition to the ARM, ARM7/ARM9,
7703 @deffn Command {arm920t cache_info}
7704 Print information about the caches found. This allows to see whether your target
7705 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
7708 @deffn Command {arm920t cp15} regnum [value]
7709 Display cp15 register @var{regnum};
7710 else if a @var{value} is provided, that value is written to that register.
7711 This uses "physical access" and the register number is as
7712 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
7713 (Not all registers can be written.)
7716 @deffn Command {arm920t cp15i} opcode [value [address]]
7717 @emph{DEPRECATED -- avoid using this.
7718 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7720 Interpreted access using ARM instruction @var{opcode}, which should
7721 be the value of either an MRC or MCR instruction
7722 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
7723 If no @var{value} is provided, the result is displayed.
7724 Else if that value is written using the specified @var{address},
7725 or using zero if no other address is provided.
7728 @deffn Command {arm920t read_cache} filename
7729 Dump the content of ICache and DCache to a file named @file{filename}.
7732 @deffn Command {arm920t read_mmu} filename
7733 Dump the content of the ITLB and DTLB to a file named @file{filename}.
7736 @subsection ARM926ej-s specific commands
7739 These commands are available to ARM926ej-s based CPUs,
7740 which are implementations of the ARMv5TEJ architecture
7741 based on the ARM9EJ-S integer core.
7742 They are available in addition to the ARM, ARM7/ARM9,
7745 The Feroceon cores also support these commands, although
7746 they are not built from ARM926ej-s designs.
7748 @deffn Command {arm926ejs cache_info}
7749 Print information about the caches found.
7752 @subsection ARM966E specific commands
7755 These commands are available to ARM966 based CPUs,
7756 which are implementations of the ARMv5TE architecture.
7757 They are available in addition to the ARM, ARM7/ARM9,
7760 @deffn Command {arm966e cp15} regnum [value]
7761 Display cp15 register @var{regnum};
7762 else if a @var{value} is provided, that value is written to that register.
7763 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
7765 There is no current control over bits 31..30 from that table,
7766 as required for BIST support.
7769 @subsection XScale specific commands
7772 Some notes about the debug implementation on the XScale CPUs:
7774 The XScale CPU provides a special debug-only mini-instruction cache
7775 (mini-IC) in which exception vectors and target-resident debug handler
7776 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
7777 must point vector 0 (the reset vector) to the entry of the debug
7778 handler. However, this means that the complete first cacheline in the
7779 mini-IC is marked valid, which makes the CPU fetch all exception
7780 handlers from the mini-IC, ignoring the code in RAM.
7782 To address this situation, OpenOCD provides the @code{xscale
7783 vector_table} command, which allows the user to explicity write
7784 individual entries to either the high or low vector table stored in
7787 It is recommended to place a pc-relative indirect branch in the vector
7788 table, and put the branch destination somewhere in memory. Doing so
7789 makes sure the code in the vector table stays constant regardless of
7790 code layout in memory:
7793 ldr pc,[pc,#0x100-8]
7794 ldr pc,[pc,#0x100-8]
7795 ldr pc,[pc,#0x100-8]
7796 ldr pc,[pc,#0x100-8]
7797 ldr pc,[pc,#0x100-8]
7798 ldr pc,[pc,#0x100-8]
7799 ldr pc,[pc,#0x100-8]
7800 ldr pc,[pc,#0x100-8]
7802 .long real_reset_vector
7803 .long real_ui_handler
7804 .long real_swi_handler
7806 .long real_data_abort
7807 .long 0 /* unused */
7808 .long real_irq_handler
7809 .long real_fiq_handler
7812 Alternatively, you may choose to keep some or all of the mini-IC
7813 vector table entries synced with those written to memory by your
7814 system software. The mini-IC can not be modified while the processor
7815 is executing, but for each vector table entry not previously defined
7816 using the @code{xscale vector_table} command, OpenOCD will copy the
7817 value from memory to the mini-IC every time execution resumes from a
7818 halt. This is done for both high and low vector tables (although the
7819 table not in use may not be mapped to valid memory, and in this case
7820 that copy operation will silently fail). This means that you will
7821 need to briefly halt execution at some strategic point during system
7822 start-up; e.g., after the software has initialized the vector table,
7823 but before exceptions are enabled. A breakpoint can be used to
7824 accomplish this once the appropriate location in the start-up code has
7825 been identified. A watchpoint over the vector table region is helpful
7826 in finding the location if you're not sure. Note that the same
7827 situation exists any time the vector table is modified by the system
7830 The debug handler must be placed somewhere in the address space using
7831 the @code{xscale debug_handler} command. The allowed locations for the
7832 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
7833 0xfffff800). The default value is 0xfe000800.
7835 XScale has resources to support two hardware breakpoints and two
7836 watchpoints. However, the following restrictions on watchpoint
7837 functionality apply: (1) the value and mask arguments to the @code{wp}
7838 command are not supported, (2) the watchpoint length must be a
7839 power of two and not less than four, and can not be greater than the
7840 watchpoint address, and (3) a watchpoint with a length greater than
7841 four consumes all the watchpoint hardware resources. This means that
7842 at any one time, you can have enabled either two watchpoints with a
7843 length of four, or one watchpoint with a length greater than four.
7845 These commands are available to XScale based CPUs,
7846 which are implementations of the ARMv5TE architecture.
7848 @deffn Command {xscale analyze_trace}
7849 Displays the contents of the trace buffer.
7852 @deffn Command {xscale cache_clean_address} address
7853 Changes the address used when cleaning the data cache.
7856 @deffn Command {xscale cache_info}
7857 Displays information about the CPU caches.
7860 @deffn Command {xscale cp15} regnum [value]
7861 Display cp15 register @var{regnum};
7862 else if a @var{value} is provided, that value is written to that register.
7865 @deffn Command {xscale debug_handler} target address
7866 Changes the address used for the specified target's debug handler.
7869 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
7870 Enables or disable the CPU's data cache.
7873 @deffn Command {xscale dump_trace} filename
7874 Dumps the raw contents of the trace buffer to @file{filename}.
7877 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
7878 Enables or disable the CPU's instruction cache.
7881 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
7882 Enables or disable the CPU's memory management unit.
7885 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
7886 Displays the trace buffer status, after optionally
7887 enabling or disabling the trace buffer
7888 and modifying how it is emptied.
7891 @deffn Command {xscale trace_image} filename [offset [type]]
7892 Opens a trace image from @file{filename}, optionally rebasing
7893 its segment addresses by @var{offset}.
7894 The image @var{type} may be one of
7895 @option{bin} (binary), @option{ihex} (Intel hex),
7896 @option{elf} (ELF file), @option{s19} (Motorola s19),
7897 @option{mem}, or @option{builder}.
7900 @anchor{xscalevectorcatch}
7901 @deffn Command {xscale vector_catch} [mask]
7902 @cindex vector_catch
7903 Display a bitmask showing the hardware vectors to catch.
7904 If the optional parameter is provided, first set the bitmask to that value.
7906 The mask bits correspond with bit 16..23 in the DCSR:
7909 0x02 Trap Undefined Instructions
7910 0x04 Trap Software Interrupt
7911 0x08 Trap Prefetch Abort
7912 0x10 Trap Data Abort
7919 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
7920 @cindex vector_table
7922 Set an entry in the mini-IC vector table. There are two tables: one for
7923 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
7924 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
7925 points to the debug handler entry and can not be overwritten.
7926 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
7928 Without arguments, the current settings are displayed.
7932 @section ARMv6 Architecture
7935 @subsection ARM11 specific commands
7938 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
7939 Displays the value of the memwrite burst-enable flag,
7940 which is enabled by default.
7941 If a boolean parameter is provided, first assigns that flag.
7942 Burst writes are only used for memory writes larger than 1 word.
7943 They improve performance by assuming that the CPU has read each data
7944 word over JTAG and completed its write before the next word arrives,
7945 instead of polling for a status flag to verify that completion.
7946 This is usually safe, because JTAG runs much slower than the CPU.
7949 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
7950 Displays the value of the memwrite error_fatal flag,
7951 which is enabled by default.
7952 If a boolean parameter is provided, first assigns that flag.
7953 When set, certain memory write errors cause earlier transfer termination.
7956 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
7957 Displays the value of the flag controlling whether
7958 IRQs are enabled during single stepping;
7959 they are disabled by default.
7960 If a boolean parameter is provided, first assigns that.
7963 @deffn Command {arm11 vcr} [value]
7964 @cindex vector_catch
7965 Displays the value of the @emph{Vector Catch Register (VCR)},
7966 coprocessor 14 register 7.
7967 If @var{value} is defined, first assigns that.
7969 Vector Catch hardware provides dedicated breakpoints
7970 for certain hardware events.
7971 The specific bit values are core-specific (as in fact is using
7972 coprocessor 14 register 7 itself) but all current ARM11
7973 cores @emph{except the ARM1176} use the same six bits.
7976 @section ARMv7 and ARMv8 Architecture
7980 @subsection ARMv7 and ARMv8 Debug Access Port (DAP) specific commands
7981 @cindex Debug Access Port
7983 These commands are specific to ARM architecture v7 and v8 Debug Access Port (DAP),
7984 included on Cortex-M and Cortex-A systems.
7985 They are available in addition to other core-specific commands that may be available.
7987 @deffn Command {dap apid} [num]
7988 Displays ID register from AP @var{num},
7989 defaulting to the currently selected AP.
7992 @deffn Command {dap apreg} ap_num reg [value]
7993 Displays content of a register @var{reg} from AP @var{ap_num}
7994 or set a new value @var{value}.
7995 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
7998 @deffn Command {dap apsel} [num]
7999 Select AP @var{num}, defaulting to 0.
8002 @deffn Command {dap baseaddr} [num]
8003 Displays debug base address from MEM-AP @var{num},
8004 defaulting to the currently selected AP.
8007 @deffn Command {dap info} [num]
8008 Displays the ROM table for MEM-AP @var{num},
8009 defaulting to the currently selected AP.
8012 @deffn Command {dap memaccess} [value]
8013 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
8014 memory bus access [0-255], giving additional time to respond to reads.
8015 If @var{value} is defined, first assigns that.
8018 @deffn Command {dap apcsw} [0 / 1]
8019 fix CSW_SPROT from register AP_REG_CSW on selected dap.
8023 @deffn Command {dap ti_be_32_quirks} [@option{enable}]
8024 Set/get quirks mode for TI TMS450/TMS570 processors
8029 @subsection ARMv7-A specific commands
8032 @deffn Command {cortex_a cache_info}
8033 display information about target caches
8036 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
8037 Work around issues with software breakpoints when the program text is
8038 mapped read-only by the operating system. This option sets the CP15 DACR
8039 to "all-manager" to bypass MMU permission checks on memory access.
8043 @deffn Command {cortex_a dbginit}
8044 Initialize core debug
8045 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8048 @deffn Command {cortex_a smp_off}
8052 @deffn Command {cortex_a smp_on}
8056 @deffn Command {cortex_a smp_gdb} [core_id]
8057 Display/set the current core displayed in GDB
8060 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
8061 Selects whether interrupts will be processed when single stepping
8064 @deffn Command {cache_config l2x} [base way]
8069 @subsection ARMv7-R specific commands
8072 @deffn Command {cortex_r dbginit}
8073 Initialize core debug
8074 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8077 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
8078 Selects whether interrupts will be processed when single stepping
8082 @subsection ARMv7-M specific commands
8090 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
8091 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
8092 @var{TRACECLKIN_freq} [@var{trace_freq}]))
8094 ARMv7-M architecture provides several modules to generate debugging
8095 information internally (ITM, DWT and ETM). Their output is directed
8096 through TPIU to be captured externally either on an SWO pin (this
8097 configuration is called SWV) or on a synchronous parallel trace port.
8099 This command configures the TPIU module of the target and, if internal
8100 capture mode is selected, starts to capture trace output by using the
8101 debugger adapter features.
8103 Some targets require additional actions to be performed in the
8104 @b{trace-config} handler for trace port to be activated.
8108 @item @option{disable} disable TPIU handling;
8109 @item @option{external} configure TPIU to let user capture trace
8110 output externally (with an additional UART or logic analyzer hardware);
8111 @item @option{internal @var{filename}} configure TPIU and debug adapter to
8112 gather trace data and append it to @var{filename} (which can be
8113 either a regular file or a named pipe);
8114 @item @option{internal -} configure TPIU and debug adapter to
8115 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
8116 @item @option{sync @var{port_width}} use synchronous parallel trace output
8117 mode, and set port width to @var{port_width};
8118 @item @option{manchester} use asynchronous SWO mode with Manchester
8120 @item @option{uart} use asynchronous SWO mode with NRZ (same as
8121 regular UART 8N1) coding;
8122 @item @var{formatter_enable} is @option{on} or @option{off} to enable
8123 or disable TPIU formatter which needs to be used when both ITM and ETM
8124 data is to be output via SWO;
8125 @item @var{TRACECLKIN_freq} this should be specified to match target's
8126 current TRACECLKIN frequency (usually the same as HCLK);
8127 @item @var{trace_freq} trace port frequency. Can be omitted in
8128 internal mode to let the adapter driver select the maximum supported
8134 @item STM32L152 board is programmed with an application that configures
8135 PLL to provide core clock with 24MHz frequency; to use ITM output it's
8138 #include <libopencm3/cm3/itm.h>
8143 (the most obvious way is to use the first stimulus port for printf,
8144 for that this ITM_STIM8 assignment can be used inside _write(); to make it
8145 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
8146 ITM_STIM_FIFOREADY));});
8147 @item An FT2232H UART is connected to the SWO pin of the board;
8148 @item Commands to configure UART for 12MHz baud rate:
8150 $ setserial /dev/ttyUSB1 spd_cust divisor 5
8151 $ stty -F /dev/ttyUSB1 38400
8153 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
8154 baud with our custom divisor to get 12MHz)
8155 @item @code{itmdump -f /dev/ttyUSB1 -d1}
8156 @item OpenOCD invocation line:
8158 openocd -f interface/stlink-v2-1.cfg \
8159 -c "transport select hla_swd" \
8160 -f target/stm32l1.cfg \
8161 -c "tpiu config external uart off 24000000 12000000"
8166 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
8167 Enable or disable trace output for ITM stimulus @var{port} (counting
8168 from 0). Port 0 is enabled on target creation automatically.
8171 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
8172 Enable or disable trace output for all ITM stimulus ports.
8175 @subsection Cortex-M specific commands
8178 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
8179 Control masking (disabling) interrupts during target step/resume.
8181 The @option{auto} option handles interrupts during stepping a way they get
8182 served but don't disturb the program flow. The step command first allows
8183 pending interrupt handlers to execute, then disables interrupts and steps over
8184 the next instruction where the core was halted. After the step interrupts
8185 are enabled again. If the interrupt handlers don't complete within 500ms,
8186 the step command leaves with the core running.
8188 Note that a free breakpoint is required for the @option{auto} option. If no
8189 breakpoint is available at the time of the step, then the step is taken
8190 with interrupts enabled, i.e. the same way the @option{off} option does.
8192 Default is @option{auto}.
8195 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
8196 @cindex vector_catch
8197 Vector Catch hardware provides dedicated breakpoints
8198 for certain hardware events.
8200 Parameters request interception of
8201 @option{all} of these hardware event vectors,
8202 @option{none} of them,
8203 or one or more of the following:
8204 @option{hard_err} for a HardFault exception;
8205 @option{mm_err} for a MemManage exception;
8206 @option{bus_err} for a BusFault exception;
8209 @option{chk_err}, or
8210 @option{nocp_err} for various UsageFault exceptions; or
8212 If NVIC setup code does not enable them,
8213 MemManage, BusFault, and UsageFault exceptions
8214 are mapped to HardFault.
8215 UsageFault checks for
8216 divide-by-zero and unaligned access
8217 must also be explicitly enabled.
8219 This finishes by listing the current vector catch configuration.
8222 @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
8223 Control reset handling. The default @option{srst} is to use srst if fitted,
8224 otherwise fallback to @option{vectreset}.
8226 @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
8227 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
8228 @item @option{vectreset} use NVIC VECTRESET to reset system.
8230 Using @option{vectreset} is a safe option for all current Cortex-M cores.
8231 This however has the disadvantage of only resetting the core, all peripherals
8232 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
8234 @xref{targetevents,,Target Events}.
8237 @subsection ARMv8-A specific commands
8241 @deffn Command {aarch64 cache_info}
8242 Display information about target caches
8245 @deffn Command {aarch64 dbginit}
8246 This command enables debugging by clearing the OS Lock and sticky power-down and reset
8247 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
8248 target code relies on. In a configuration file, the command would typically be called from a
8249 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
8250 However, normally it is not necessary to use the command at all.
8253 @deffn Command {aarch64 smp_on|smp_off}
8254 Enable and disable SMP handling. The state of SMP handling influences the way targets in an SMP group
8255 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
8256 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
8257 group. With SMP handling disabled, all targets need to be treated individually.
8260 @section Intel Architecture
8262 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
8263 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
8264 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
8265 software debug and the CLTAP is used for SoC level operations.
8266 Useful docs are here: https://communities.intel.com/community/makers/documentation
8268 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
8269 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
8270 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
8273 @subsection x86 32-bit specific commands
8274 The three main address spaces for x86 are memory, I/O and configuration space.
8275 These commands allow a user to read and write to the 64Kbyte I/O address space.
8277 @deffn Command {x86_32 idw} address
8278 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
8281 @deffn Command {x86_32 idh} address
8282 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
8285 @deffn Command {x86_32 idb} address
8286 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
8289 @deffn Command {x86_32 iww} address
8290 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
8293 @deffn Command {x86_32 iwh} address
8294 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
8297 @deffn Command {x86_32 iwb} address
8298 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
8301 @section OpenRISC Architecture
8303 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
8304 configured with any of the TAP / Debug Unit available.
8306 @subsection TAP and Debug Unit selection commands
8307 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
8308 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
8310 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
8311 Select between the Advanced Debug Interface and the classic one.
8313 An option can be passed as a second argument to the debug unit.
8315 When using the Advanced Debug Interface, option = 1 means the RTL core is
8316 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
8317 between bytes while doing read or write bursts.
8320 @subsection Registers commands
8321 @deffn Command {addreg} [name] [address] [feature] [reg_group]
8322 Add a new register in the cpu register list. This register will be
8323 included in the generated target descriptor file.
8325 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
8327 @strong{[reg_group]} can be anything. The default register list defines "system",
8328 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
8333 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
8338 @deffn Command {readgroup} (@option{group})
8339 Display all registers in @emph{group}.
8341 @emph{group} can be "system",
8342 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
8343 "timer" or any new group created with addreg command.
8346 @anchor{softwaredebugmessagesandtracing}
8347 @section Software Debug Messages and Tracing
8348 @cindex Linux-ARM DCC support
8352 OpenOCD can process certain requests from target software, when
8353 the target uses appropriate libraries.
8354 The most powerful mechanism is semihosting, but there is also
8355 a lighter weight mechanism using only the DCC channel.
8357 Currently @command{target_request debugmsgs}
8358 is supported only for @option{arm7_9} and @option{cortex_m} cores.
8359 These messages are received as part of target polling, so
8360 you need to have @command{poll on} active to receive them.
8361 They are intrusive in that they will affect program execution
8362 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
8364 See @file{libdcc} in the contrib dir for more details.
8365 In addition to sending strings, characters, and
8366 arrays of various size integers from the target,
8367 @file{libdcc} also exports a software trace point mechanism.
8368 The target being debugged may
8369 issue trace messages which include a 24-bit @dfn{trace point} number.
8370 Trace point support includes two distinct mechanisms,
8371 each supported by a command:
8374 @item @emph{History} ... A circular buffer of trace points
8375 can be set up, and then displayed at any time.
8376 This tracks where code has been, which can be invaluable in
8377 finding out how some fault was triggered.
8379 The buffer may overflow, since it collects records continuously.
8380 It may be useful to use some of the 24 bits to represent a
8381 particular event, and other bits to hold data.
8383 @item @emph{Counting} ... An array of counters can be set up,
8384 and then displayed at any time.
8385 This can help establish code coverage and identify hot spots.
8387 The array of counters is directly indexed by the trace point
8388 number, so trace points with higher numbers are not counted.
8391 Linux-ARM kernels have a ``Kernel low-level debugging
8392 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
8393 depends on CONFIG_DEBUG_LL) which uses this mechanism to
8394 deliver messages before a serial console can be activated.
8395 This is not the same format used by @file{libdcc}.
8396 Other software, such as the U-Boot boot loader, sometimes
8397 does the same thing.
8399 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
8400 Displays current handling of target DCC message requests.
8401 These messages may be sent to the debugger while the target is running.
8402 The optional @option{enable} and @option{charmsg} parameters
8403 both enable the messages, while @option{disable} disables them.
8405 With @option{charmsg} the DCC words each contain one character,
8406 as used by Linux with CONFIG_DEBUG_ICEDCC;
8407 otherwise the libdcc format is used.
8410 @deffn Command {trace history} [@option{clear}|count]
8411 With no parameter, displays all the trace points that have triggered
8412 in the order they triggered.
8413 With the parameter @option{clear}, erases all current trace history records.
8414 With a @var{count} parameter, allocates space for that many
8418 @deffn Command {trace point} [@option{clear}|identifier]
8419 With no parameter, displays all trace point identifiers and how many times
8420 they have been triggered.
8421 With the parameter @option{clear}, erases all current trace point counters.
8422 With a numeric @var{identifier} parameter, creates a new a trace point counter
8423 and associates it with that identifier.
8425 @emph{Important:} The identifier and the trace point number
8426 are not related except by this command.
8427 These trace point numbers always start at zero (from server startup,
8428 or after @command{trace point clear}) and count up from there.
8433 @chapter JTAG Commands
8434 @cindex JTAG Commands
8435 Most general purpose JTAG commands have been presented earlier.
8436 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
8437 Lower level JTAG commands, as presented here,
8438 may be needed to work with targets which require special
8439 attention during operations such as reset or initialization.
8441 To use these commands you will need to understand some
8442 of the basics of JTAG, including:
8445 @item A JTAG scan chain consists of a sequence of individual TAP
8446 devices such as a CPUs.
8447 @item Control operations involve moving each TAP through the same
8448 standard state machine (in parallel)
8449 using their shared TMS and clock signals.
8450 @item Data transfer involves shifting data through the chain of
8451 instruction or data registers of each TAP, writing new register values
8452 while the reading previous ones.
8453 @item Data register sizes are a function of the instruction active in
8454 a given TAP, while instruction register sizes are fixed for each TAP.
8455 All TAPs support a BYPASS instruction with a single bit data register.
8456 @item The way OpenOCD differentiates between TAP devices is by
8457 shifting different instructions into (and out of) their instruction
8461 @section Low Level JTAG Commands
8463 These commands are used by developers who need to access
8464 JTAG instruction or data registers, possibly controlling
8465 the order of TAP state transitions.
8466 If you're not debugging OpenOCD internals, or bringing up a
8467 new JTAG adapter or a new type of TAP device (like a CPU or
8468 JTAG router), you probably won't need to use these commands.
8469 In a debug session that doesn't use JTAG for its transport protocol,
8470 these commands are not available.
8472 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
8473 Loads the data register of @var{tap} with a series of bit fields
8474 that specify the entire register.
8475 Each field is @var{numbits} bits long with
8476 a numeric @var{value} (hexadecimal encouraged).
8477 The return value holds the original value of each
8480 For example, a 38 bit number might be specified as one
8481 field of 32 bits then one of 6 bits.
8482 @emph{For portability, never pass fields which are more
8483 than 32 bits long. Many OpenOCD implementations do not
8484 support 64-bit (or larger) integer values.}
8486 All TAPs other than @var{tap} must be in BYPASS mode.
8487 The single bit in their data registers does not matter.
8489 When @var{tap_state} is specified, the JTAG state machine is left
8491 For example @sc{drpause} might be specified, so that more
8492 instructions can be issued before re-entering the @sc{run/idle} state.
8493 If the end state is not specified, the @sc{run/idle} state is entered.
8496 OpenOCD does not record information about data register lengths,
8497 so @emph{it is important that you get the bit field lengths right}.
8498 Remember that different JTAG instructions refer to different
8499 data registers, which may have different lengths.
8500 Moreover, those lengths may not be fixed;
8501 the SCAN_N instruction can change the length of
8502 the register accessed by the INTEST instruction
8503 (by connecting a different scan chain).
8507 @deffn Command {flush_count}
8508 Returns the number of times the JTAG queue has been flushed.
8509 This may be used for performance tuning.
8511 For example, flushing a queue over USB involves a
8512 minimum latency, often several milliseconds, which does
8513 not change with the amount of data which is written.
8514 You may be able to identify performance problems by finding
8515 tasks which waste bandwidth by flushing small transfers too often,
8516 instead of batching them into larger operations.
8519 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
8520 For each @var{tap} listed, loads the instruction register
8521 with its associated numeric @var{instruction}.
8522 (The number of bits in that instruction may be displayed
8523 using the @command{scan_chain} command.)
8524 For other TAPs, a BYPASS instruction is loaded.
8526 When @var{tap_state} is specified, the JTAG state machine is left
8528 For example @sc{irpause} might be specified, so the data register
8529 can be loaded before re-entering the @sc{run/idle} state.
8530 If the end state is not specified, the @sc{run/idle} state is entered.
8533 OpenOCD currently supports only a single field for instruction
8534 register values, unlike data register values.
8535 For TAPs where the instruction register length is more than 32 bits,
8536 portable scripts currently must issue only BYPASS instructions.
8540 @deffn Command {jtag_reset} trst srst
8541 Set values of reset signals.
8542 The @var{trst} and @var{srst} parameter values may be
8543 @option{0}, indicating that reset is inactive (pulled or driven high),
8544 or @option{1}, indicating it is active (pulled or driven low).
8545 The @command{reset_config} command should already have been used
8546 to configure how the board and JTAG adapter treat these two
8547 signals, and to say if either signal is even present.
8548 @xref{Reset Configuration}.
8550 Note that TRST is specially handled.
8551 It actually signifies JTAG's @sc{reset} state.
8552 So if the board doesn't support the optional TRST signal,
8553 or it doesn't support it along with the specified SRST value,
8554 JTAG reset is triggered with TMS and TCK signals
8555 instead of the TRST signal.
8556 And no matter how that JTAG reset is triggered, once
8557 the scan chain enters @sc{reset} with TRST inactive,
8558 TAP @code{post-reset} events are delivered to all TAPs
8559 with handlers for that event.
8562 @deffn Command {pathmove} start_state [next_state ...]
8563 Start by moving to @var{start_state}, which
8564 must be one of the @emph{stable} states.
8565 Unless it is the only state given, this will often be the
8566 current state, so that no TCK transitions are needed.
8567 Then, in a series of single state transitions
8568 (conforming to the JTAG state machine) shift to
8569 each @var{next_state} in sequence, one per TCK cycle.
8570 The final state must also be stable.
8573 @deffn Command {runtest} @var{num_cycles}
8574 Move to the @sc{run/idle} state, and execute at least
8575 @var{num_cycles} of the JTAG clock (TCK).
8576 Instructions often need some time
8577 to execute before they take effect.
8580 @c tms_sequence (short|long)
8581 @c ... temporary, debug-only, other than USBprog bug workaround...
8583 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
8584 Verify values captured during @sc{ircapture} and returned
8585 during IR scans. Default is enabled, but this can be
8586 overridden by @command{verify_jtag}.
8587 This flag is ignored when validating JTAG chain configuration.
8590 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
8591 Enables verification of DR and IR scans, to help detect
8592 programming errors. For IR scans, @command{verify_ircapture}
8593 must also be enabled.
8597 @section TAP state names
8598 @cindex TAP state names
8600 The @var{tap_state} names used by OpenOCD in the @command{drscan},
8601 @command{irscan}, and @command{pathmove} commands are the same
8602 as those used in SVF boundary scan documents, except that
8603 SVF uses @sc{idle} instead of @sc{run/idle}.
8606 @item @b{RESET} ... @emph{stable} (with TMS high);
8607 acts as if TRST were pulsed
8608 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
8611 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
8612 through the data register
8614 @item @b{DRPAUSE} ... @emph{stable}; data register ready
8615 for update or more shifting
8620 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
8621 through the instruction register
8623 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
8624 for update or more shifting
8629 Note that only six of those states are fully ``stable'' in the
8630 face of TMS fixed (low except for @sc{reset})
8631 and a free-running JTAG clock. For all the
8632 others, the next TCK transition changes to a new state.
8635 @item From @sc{drshift} and @sc{irshift}, clock transitions will
8636 produce side effects by changing register contents. The values
8637 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
8638 may not be as expected.
8639 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
8640 choices after @command{drscan} or @command{irscan} commands,
8641 since they are free of JTAG side effects.
8642 @item @sc{run/idle} may have side effects that appear at non-JTAG
8643 levels, such as advancing the ARM9E-S instruction pipeline.
8644 Consult the documentation for the TAP(s) you are working with.
8647 @node Boundary Scan Commands
8648 @chapter Boundary Scan Commands
8650 One of the original purposes of JTAG was to support
8651 boundary scan based hardware testing.
8652 Although its primary focus is to support On-Chip Debugging,
8653 OpenOCD also includes some boundary scan commands.
8655 @section SVF: Serial Vector Format
8656 @cindex Serial Vector Format
8659 The Serial Vector Format, better known as @dfn{SVF}, is a
8660 way to represent JTAG test patterns in text files.
8661 In a debug session using JTAG for its transport protocol,
8662 OpenOCD supports running such test files.
8664 @deffn Command {svf} filename [@option{quiet}]
8665 This issues a JTAG reset (Test-Logic-Reset) and then
8666 runs the SVF script from @file{filename}.
8667 Unless the @option{quiet} option is specified,
8668 each command is logged before it is executed.
8671 @section XSVF: Xilinx Serial Vector Format
8672 @cindex Xilinx Serial Vector Format
8675 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
8676 binary representation of SVF which is optimized for use with
8678 In a debug session using JTAG for its transport protocol,
8679 OpenOCD supports running such test files.
8681 @quotation Important
8682 Not all XSVF commands are supported.
8685 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
8686 This issues a JTAG reset (Test-Logic-Reset) and then
8687 runs the XSVF script from @file{filename}.
8688 When a @var{tapname} is specified, the commands are directed at
8690 When @option{virt2} is specified, the @sc{xruntest} command counts
8691 are interpreted as TCK cycles instead of microseconds.
8692 Unless the @option{quiet} option is specified,
8693 messages are logged for comments and some retries.
8696 The OpenOCD sources also include two utility scripts
8697 for working with XSVF; they are not currently installed
8698 after building the software.
8699 You may find them useful:
8702 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
8703 syntax understood by the @command{xsvf} command; see notes below.
8704 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
8705 understands the OpenOCD extensions.
8708 The input format accepts a handful of non-standard extensions.
8709 These include three opcodes corresponding to SVF extensions
8710 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
8711 two opcodes supporting a more accurate translation of SVF
8712 (XTRST, XWAITSTATE).
8713 If @emph{xsvfdump} shows a file is using those opcodes, it
8714 probably will not be usable with other XSVF tools.
8717 @node Utility Commands
8718 @chapter Utility Commands
8719 @cindex Utility Commands
8721 @section RAM testing
8724 There is often a need to stress-test random access memory (RAM) for
8725 errors. OpenOCD comes with a Tcl implementation of well-known memory
8726 testing procedures allowing the detection of all sorts of issues with
8727 electrical wiring, defective chips, PCB layout and other common
8730 To use them, you usually need to initialise your RAM controller first;
8731 consult your SoC's documentation to get the recommended list of
8732 register operations and translate them to the corresponding
8733 @command{mww}/@command{mwb} commands.
8735 Load the memory testing functions with
8738 source [find tools/memtest.tcl]
8741 to get access to the following facilities:
8743 @deffn Command {memTestDataBus} address
8744 Test the data bus wiring in a memory region by performing a walking
8745 1's test at a fixed address within that region.
8748 @deffn Command {memTestAddressBus} baseaddress size
8749 Perform a walking 1's test on the relevant bits of the address and
8750 check for aliasing. This test will find single-bit address failures
8751 such as stuck-high, stuck-low, and shorted pins.
8754 @deffn Command {memTestDevice} baseaddress size
8755 Test the integrity of a physical memory device by performing an
8756 increment/decrement test over the entire region. In the process every
8757 storage bit in the device is tested as zero and as one.
8760 @deffn Command {runAllMemTests} baseaddress size
8761 Run all of the above tests over a specified memory region.
8764 @section Firmware recovery helpers
8765 @cindex Firmware recovery
8767 OpenOCD includes an easy-to-use script to facilitate mass-market
8768 devices recovery with JTAG.
8770 For quickstart instructions run:
8772 openocd -f tools/firmware-recovery.tcl -c firmware_help
8778 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
8779 be used to access files on PCs (either the developer's PC or some other PC).
8781 The way this works on the ZY1000 is to prefix a filename by
8782 "/tftp/ip/" and append the TFTP path on the TFTP
8783 server (tftpd). For example,
8786 load_image /tftp/10.0.0.96/c:\temp\abc.elf
8789 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
8790 if the file was hosted on the embedded host.
8792 In order to achieve decent performance, you must choose a TFTP server
8793 that supports a packet size bigger than the default packet size (512 bytes). There
8794 are numerous TFTP servers out there (free and commercial) and you will have to do
8795 a bit of googling to find something that fits your requirements.
8797 @node GDB and OpenOCD
8798 @chapter GDB and OpenOCD
8800 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
8801 to debug remote targets.
8802 Setting up GDB to work with OpenOCD can involve several components:
8805 @item The OpenOCD server support for GDB may need to be configured.
8806 @xref{gdbconfiguration,,GDB Configuration}.
8807 @item GDB's support for OpenOCD may need configuration,
8808 as shown in this chapter.
8809 @item If you have a GUI environment like Eclipse,
8810 that also will probably need to be configured.
8813 Of course, the version of GDB you use will need to be one which has
8814 been built to know about the target CPU you're using. It's probably
8815 part of the tool chain you're using. For example, if you are doing
8816 cross-development for ARM on an x86 PC, instead of using the native
8817 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
8818 if that's the tool chain used to compile your code.
8820 @section Connecting to GDB
8821 @cindex Connecting to GDB
8822 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
8823 instance GDB 6.3 has a known bug that produces bogus memory access
8824 errors, which has since been fixed; see
8825 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
8827 OpenOCD can communicate with GDB in two ways:
8831 A socket (TCP/IP) connection is typically started as follows:
8833 target remote localhost:3333
8835 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
8837 It is also possible to use the GDB extended remote protocol as follows:
8839 target extended-remote localhost:3333
8842 A pipe connection is typically started as follows:
8844 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
8846 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
8847 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
8848 session. log_output sends the log output to a file to ensure that the pipe is
8849 not saturated when using higher debug level outputs.
8852 To list the available OpenOCD commands type @command{monitor help} on the
8855 @section Sample GDB session startup
8857 With the remote protocol, GDB sessions start a little differently
8858 than they do when you're debugging locally.
8859 Here's an example showing how to start a debug session with a
8861 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
8862 Most programs would be written into flash (address 0) and run from there.
8865 $ arm-none-eabi-gdb example.elf
8866 (gdb) target remote localhost:3333
8867 Remote debugging using localhost:3333
8869 (gdb) monitor reset halt
8872 Loading section .vectors, size 0x100 lma 0x20000000
8873 Loading section .text, size 0x5a0 lma 0x20000100
8874 Loading section .data, size 0x18 lma 0x200006a0
8875 Start address 0x2000061c, load size 1720
8876 Transfer rate: 22 KB/sec, 573 bytes/write.
8882 You could then interrupt the GDB session to make the program break,
8883 type @command{where} to show the stack, @command{list} to show the
8884 code around the program counter, @command{step} through code,
8885 set breakpoints or watchpoints, and so on.
8887 @section Configuring GDB for OpenOCD
8889 OpenOCD supports the gdb @option{qSupported} packet, this enables information
8890 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
8891 packet size and the device's memory map.
8892 You do not need to configure the packet size by hand,
8893 and the relevant parts of the memory map should be automatically
8894 set up when you declare (NOR) flash banks.
8896 However, there are other things which GDB can't currently query.
8897 You may need to set those up by hand.
8898 As OpenOCD starts up, you will often see a line reporting
8902 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
8905 You can pass that information to GDB with these commands:
8908 set remote hardware-breakpoint-limit 6
8909 set remote hardware-watchpoint-limit 4
8912 With that particular hardware (Cortex-M3) the hardware breakpoints
8913 only work for code running from flash memory. Most other ARM systems
8914 do not have such restrictions.
8916 Another example of useful GDB configuration came from a user who
8917 found that single stepping his Cortex-M3 didn't work well with IRQs
8918 and an RTOS until he told GDB to disable the IRQs while stepping:
8922 mon cortex_m maskisr on
8924 define hookpost-step
8925 mon cortex_m maskisr off
8929 Rather than typing such commands interactively, you may prefer to
8930 save them in a file and have GDB execute them as it starts, perhaps
8931 using a @file{.gdbinit} in your project directory or starting GDB
8932 using @command{gdb -x filename}.
8934 @section Programming using GDB
8935 @cindex Programming using GDB
8936 @anchor{programmingusinggdb}
8938 By default the target memory map is sent to GDB. This can be disabled by
8939 the following OpenOCD configuration option:
8941 gdb_memory_map disable
8943 For this to function correctly a valid flash configuration must also be set
8944 in OpenOCD. For faster performance you should also configure a valid
8947 Informing GDB of the memory map of the target will enable GDB to protect any
8948 flash areas of the target and use hardware breakpoints by default. This means
8949 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
8950 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
8952 To view the configured memory map in GDB, use the GDB command @option{info mem}.
8953 All other unassigned addresses within GDB are treated as RAM.
8955 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
8956 This can be changed to the old behaviour by using the following GDB command
8958 set mem inaccessible-by-default off
8961 If @command{gdb_flash_program enable} is also used, GDB will be able to
8962 program any flash memory using the vFlash interface.
8964 GDB will look at the target memory map when a load command is given, if any
8965 areas to be programmed lie within the target flash area the vFlash packets
8968 If the target needs configuring before GDB programming, an event
8969 script can be executed:
8971 $_TARGETNAME configure -event EVENTNAME BODY
8974 To verify any flash programming the GDB command @option{compare-sections}
8976 @anchor{usingopenocdsmpwithgdb}
8977 @section Using OpenOCD SMP with GDB
8979 For SMP support following GDB serial protocol packet have been defined :
8981 @item j - smp status request
8982 @item J - smp set request
8985 OpenOCD implements :
8987 @item @option{jc} packet for reading core id displayed by
8988 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
8989 @option{E01} for target not smp.
8990 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
8991 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
8992 for target not smp or @option{OK} on success.
8995 Handling of this packet within GDB can be done :
8997 @item by the creation of an internal variable (i.e @option{_core}) by mean
8998 of function allocate_computed_value allowing following GDB command.
9001 #Jc01 packet is sent
9003 #jc packet is sent and result is affected in $
9006 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
9007 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
9010 # toggle0 : force display of coreid 0
9016 # toggle1 : force display of coreid 1
9025 @section RTOS Support
9026 @cindex RTOS Support
9027 @anchor{gdbrtossupport}
9029 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
9030 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
9032 @xref{Threads, Debugging Programs with Multiple Threads,
9033 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
9036 @* An example setup is below:
9039 $_TARGETNAME configure -rtos auto
9042 This will attempt to auto detect the RTOS within your application.
9044 Currently supported rtos's include:
9047 @item @option{ThreadX}
9048 @item @option{FreeRTOS}
9049 @item @option{linux}
9050 @item @option{ChibiOS}
9051 @item @option{embKernel}
9053 @item @option{uCOS-III}
9057 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
9058 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
9063 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
9064 @item ThreadX symbols
9065 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
9066 @item FreeRTOS symbols
9067 @c The following is taken from recent texinfo to provide compatibility
9068 @c with ancient versions that do not support @raggedright
9071 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
9072 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
9073 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
9074 uxCurrentNumberOfTasks, uxTopUsedPriority.
9080 @item ChibiOS symbols
9081 rlist, ch_debug, chSysInit.
9082 @item embKernel symbols
9083 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
9084 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
9086 _mqx_kernel_data, MQX_init_struct.
9087 @item uC/OS-III symbols
9088 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
9091 For most RTOS supported the above symbols will be exported by default. However for
9092 some, eg. FreeRTOS and uC/OS-III, extra steps must be taken.
9094 These RTOSes may require additional OpenOCD-specific file to be linked
9095 along with the project:
9099 contrib/rtos-helpers/FreeRTOS-openocd.c
9101 contrib/rtos-helpers/uCOS-III-openocd.c
9104 @node Tcl Scripting API
9105 @chapter Tcl Scripting API
9106 @cindex Tcl Scripting API
9110 Tcl commands are stateless; e.g. the @command{telnet} command has
9111 a concept of currently active target, the Tcl API proc's take this sort
9112 of state information as an argument to each proc.
9114 There are three main types of return values: single value, name value
9115 pair list and lists.
9117 Name value pair. The proc 'foo' below returns a name/value pair
9122 > set foo(you) Oyvind
9123 > set foo(mouse) Micky
9124 > set foo(duck) Donald
9136 me Duane you Oyvind mouse Micky duck Donald
9139 Thus, to get the names of the associative array is easy:
9142 foreach { name value } [set foo] {
9143 puts "Name: $name, Value: $value"
9147 Lists returned should be relatively small. Otherwise, a range
9148 should be passed in to the proc in question.
9150 @section Internal low-level Commands
9152 By "low-level," we mean commands that a human would typically not
9155 Some low-level commands need to be prefixed with "ocd_"; e.g.
9156 @command{ocd_flash_banks}
9157 is the low-level API upon which @command{flash banks} is implemented.
9160 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
9162 Read memory and return as a Tcl array for script processing
9163 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
9165 Convert a Tcl array to memory locations and write the values
9166 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
9168 Return information about the flash banks
9170 @item @b{capture} <@var{command}>
9172 Run <@var{command}> and return full log output that was produced during
9173 its execution. Example:
9176 > capture "reset init"
9181 OpenOCD commands can consist of two words, e.g. "flash banks". The
9182 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
9183 called "flash_banks".
9185 @section OpenOCD specific Global Variables
9187 Real Tcl has ::tcl_platform(), and platform::identify, and many other
9188 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
9189 holds one of the following values:
9192 @item @b{cygwin} Running under Cygwin
9193 @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
9194 @item @b{freebsd} Running under FreeBSD
9195 @item @b{openbsd} Running under OpenBSD
9196 @item @b{netbsd} Running under NetBSD
9197 @item @b{linux} Linux is the underlying operating sytem
9198 @item @b{mingw32} Running under MingW32
9199 @item @b{winxx} Built using Microsoft Visual Studio
9200 @item @b{ecos} Running under eCos
9201 @item @b{other} Unknown, none of the above.
9204 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
9207 We should add support for a variable like Tcl variable
9208 @code{tcl_platform(platform)}, it should be called
9209 @code{jim_platform} (because it
9210 is jim, not real tcl).
9213 @section Tcl RPC server
9216 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
9217 commands and receive the results.
9219 To access it, your application needs to connect to a configured TCP port
9220 (see @command{tcl_port}). Then it can pass any string to the
9221 interpreter terminating it with @code{0x1a} and wait for the return
9222 value (it will be terminated with @code{0x1a} as well). This can be
9223 repeated as many times as desired without reopening the connection.
9225 Remember that most of the OpenOCD commands need to be prefixed with
9226 @code{ocd_} to get the results back. Sometimes you might also need the
9227 @command{capture} command.
9229 See @file{contrib/rpc_examples/} for specific client implementations.
9231 @section Tcl RPC server notifications
9232 @cindex RPC Notifications
9234 Notifications are sent asynchronously to other commands being executed over
9235 the RPC server, so the port must be polled continuously.
9237 Target event, state and reset notifications are emitted as Tcl associative arrays
9238 in the following format.
9241 type target_event event [event-name]
9242 type target_state state [state-name]
9243 type target_reset mode [reset-mode]
9246 @deffn {Command} tcl_notifications [on/off]
9247 Toggle output of target notifications to the current Tcl RPC server.
9248 Only available from the Tcl RPC server.
9253 @section Tcl RPC server trace output
9254 @cindex RPC trace output
9256 Trace data is sent asynchronously to other commands being executed over
9257 the RPC server, so the port must be polled continuously.
9259 Target trace data is emitted as a Tcl associative array in the following format.
9262 type target_trace data [trace-data-hex-encoded]
9265 @deffn {Command} tcl_trace [on/off]
9266 Toggle output of target trace data to the current Tcl RPC server.
9267 Only available from the Tcl RPC server.
9270 See an example application here:
9271 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
9280 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
9282 @cindex adaptive clocking
9285 In digital circuit design it is often refered to as ``clock
9286 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
9287 operating at some speed, your CPU target is operating at another.
9288 The two clocks are not synchronised, they are ``asynchronous''
9290 In order for the two to work together they must be synchronised
9291 well enough to work; JTAG can't go ten times faster than the CPU,
9292 for example. There are 2 basic options:
9295 Use a special "adaptive clocking" circuit to change the JTAG
9296 clock rate to match what the CPU currently supports.
9298 The JTAG clock must be fixed at some speed that's enough slower than
9299 the CPU clock that all TMS and TDI transitions can be detected.
9302 @b{Does this really matter?} For some chips and some situations, this
9303 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
9304 the CPU has no difficulty keeping up with JTAG.
9305 Startup sequences are often problematic though, as are other
9306 situations where the CPU clock rate changes (perhaps to save
9309 For example, Atmel AT91SAM chips start operation from reset with
9310 a 32kHz system clock. Boot firmware may activate the main oscillator
9311 and PLL before switching to a faster clock (perhaps that 500 MHz
9313 If you're using JTAG to debug that startup sequence, you must slow
9314 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
9315 JTAG can use a faster clock.
9317 Consider also debugging a 500MHz ARM926 hand held battery powered
9318 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
9319 clock, between keystrokes unless it has work to do. When would
9320 that 5 MHz JTAG clock be usable?
9322 @b{Solution #1 - A special circuit}
9324 In order to make use of this,
9325 your CPU, board, and JTAG adapter must all support the RTCK
9326 feature. Not all of them support this; keep reading!
9328 The RTCK ("Return TCK") signal in some ARM chips is used to help with
9329 this problem. ARM has a good description of the problem described at
9330 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
9331 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
9332 work? / how does adaptive clocking work?''.
9334 The nice thing about adaptive clocking is that ``battery powered hand
9335 held device example'' - the adaptiveness works perfectly all the
9336 time. One can set a break point or halt the system in the deep power
9337 down code, slow step out until the system speeds up.
9339 Note that adaptive clocking may also need to work at the board level,
9340 when a board-level scan chain has multiple chips.
9341 Parallel clock voting schemes are good way to implement this,
9342 both within and between chips, and can easily be implemented
9344 It's not difficult to have logic fan a module's input TCK signal out
9345 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
9346 back with the right polarity before changing the output RTCK signal.
9347 Texas Instruments makes some clock voting logic available
9348 for free (with no support) in VHDL form; see
9349 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
9351 @b{Solution #2 - Always works - but may be slower}
9353 Often this is a perfectly acceptable solution.
9355 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
9356 the target clock speed. But what that ``magic division'' is varies
9357 depending on the chips on your board.
9358 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
9359 ARM11 cores use an 8:1 division.
9360 @b{Xilinx rule of thumb} is 1/12 the clock speed.
9362 Note: most full speed FT2232 based JTAG adapters are limited to a
9363 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
9364 often support faster clock rates (and adaptive clocking).
9366 You can still debug the 'low power' situations - you just need to
9367 either use a fixed and very slow JTAG clock rate ... or else
9368 manually adjust the clock speed at every step. (Adjusting is painful
9369 and tedious, and is not always practical.)
9371 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
9372 have a special debug mode in your application that does a ``high power
9373 sleep''. If you are careful - 98% of your problems can be debugged
9376 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
9377 operation in your idle loops even if you don't otherwise change the CPU
9379 That operation gates the CPU clock, and thus the JTAG clock; which
9380 prevents JTAG access. One consequence is not being able to @command{halt}
9381 cores which are executing that @emph{wait for interrupt} operation.
9383 To set the JTAG frequency use the command:
9391 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
9393 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
9394 around Windows filenames.
9407 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
9409 Make sure you have Cygwin installed, or at least a version of OpenOCD that
9410 claims to come with all the necessary DLLs. When using Cygwin, try launching
9411 OpenOCD from the Cygwin shell.
9413 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
9414 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
9415 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
9417 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
9418 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
9419 software breakpoints consume one of the two available hardware breakpoints.
9421 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
9423 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
9424 clock at the time you're programming the flash. If you've specified the crystal's
9425 frequency, make sure the PLL is disabled. If you've specified the full core speed
9426 (e.g. 60MHz), make sure the PLL is enabled.
9428 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
9429 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
9430 out while waiting for end of scan, rtck was disabled".
9432 Make sure your PC's parallel port operates in EPP mode. You might have to try several
9433 settings in your PC BIOS (ECP, EPP, and different versions of those).
9435 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
9436 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
9437 memory read caused data abort".
9439 The errors are non-fatal, and are the result of GDB trying to trace stack frames
9440 beyond the last valid frame. It might be possible to prevent this by setting up
9441 a proper "initial" stack frame, if you happen to know what exactly has to
9442 be done, feel free to add this here.
9444 @b{Simple:} In your startup code - push 8 registers of zeros onto the
9445 stack before calling main(). What GDB is doing is ``climbing'' the run
9446 time stack by reading various values on the stack using the standard
9447 call frame for the target. GDB keeps going - until one of 2 things
9448 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
9449 stackframes have been processed. By pushing zeros on the stack, GDB
9452 @b{Debugging Interrupt Service Routines} - In your ISR before you call
9453 your C code, do the same - artifically push some zeros onto the stack,
9454 remember to pop them off when the ISR is done.
9456 @b{Also note:} If you have a multi-threaded operating system, they
9457 often do not @b{in the intrest of saving memory} waste these few
9461 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
9462 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
9464 This warning doesn't indicate any serious problem, as long as you don't want to
9465 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
9466 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
9467 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
9468 independently. With this setup, it's not possible to halt the core right out of
9469 reset, everything else should work fine.
9471 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
9472 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
9473 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
9474 quit with an error message. Is there a stability issue with OpenOCD?
9476 No, this is not a stability issue concerning OpenOCD. Most users have solved
9477 this issue by simply using a self-powered USB hub, which they connect their
9478 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
9479 supply stable enough for the Amontec JTAGkey to be operated.
9481 @b{Laptops running on battery have this problem too...}
9483 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
9484 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
9485 What does that mean and what might be the reason for this?
9487 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
9488 has closed the connection to OpenOCD. This might be a GDB issue.
9490 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
9491 are described, there is a parameter for specifying the clock frequency
9492 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
9493 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
9494 specified in kilohertz. However, I do have a quartz crystal of a
9495 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
9496 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
9499 No. The clock frequency specified here must be given as an integral number.
9500 However, this clock frequency is used by the In-Application-Programming (IAP)
9501 routines of the LPC2000 family only, which seems to be very tolerant concerning
9502 the given clock frequency, so a slight difference between the specified clock
9503 frequency and the actual clock frequency will not cause any trouble.
9505 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
9507 Well, yes and no. Commands can be given in arbitrary order, yet the
9508 devices listed for the JTAG scan chain must be given in the right
9509 order (jtag newdevice), with the device closest to the TDO-Pin being
9510 listed first. In general, whenever objects of the same type exist
9511 which require an index number, then these objects must be given in the
9512 right order (jtag newtap, targets and flash banks - a target
9513 references a jtag newtap and a flash bank references a target).
9515 You can use the ``scan_chain'' command to verify and display the tap order.
9517 Also, some commands can't execute until after @command{init} has been
9518 processed. Such commands include @command{nand probe} and everything
9519 else that needs to write to controller registers, perhaps for setting
9520 up DRAM and loading it with code.
9522 @anchor{faqtaporder}
9523 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
9526 Yes; whenever you have more than one, you must declare them in
9527 the same order used by the hardware.
9529 Many newer devices have multiple JTAG TAPs. For example: ST
9530 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
9531 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
9532 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
9533 connected to the boundary scan TAP, which then connects to the
9534 Cortex-M3 TAP, which then connects to the TDO pin.
9536 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
9537 (2) The boundary scan TAP. If your board includes an additional JTAG
9538 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
9539 place it before or after the STM32 chip in the chain. For example:
9542 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
9543 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
9544 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
9545 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
9546 @item Xilinx TDO Pin -> OpenOCD TDO (input)
9549 The ``jtag device'' commands would thus be in the order shown below. Note:
9552 @item jtag newtap Xilinx tap -irlen ...
9553 @item jtag newtap stm32 cpu -irlen ...
9554 @item jtag newtap stm32 bs -irlen ...
9555 @item # Create the debug target and say where it is
9556 @item target create stm32.cpu -chain-position stm32.cpu ...
9560 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
9561 log file, I can see these error messages: Error: arm7_9_common.c:561
9562 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
9568 @node Tcl Crash Course
9569 @chapter Tcl Crash Course
9572 Not everyone knows Tcl - this is not intended to be a replacement for
9573 learning Tcl, the intent of this chapter is to give you some idea of
9574 how the Tcl scripts work.
9576 This chapter is written with two audiences in mind. (1) OpenOCD users
9577 who need to understand a bit more of how Jim-Tcl works so they can do
9578 something useful, and (2) those that want to add a new command to
9581 @section Tcl Rule #1
9582 There is a famous joke, it goes like this:
9584 @item Rule #1: The wife is always correct
9585 @item Rule #2: If you think otherwise, See Rule #1
9588 The Tcl equal is this:
9591 @item Rule #1: Everything is a string
9592 @item Rule #2: If you think otherwise, See Rule #1
9595 As in the famous joke, the consequences of Rule #1 are profound. Once
9596 you understand Rule #1, you will understand Tcl.
9598 @section Tcl Rule #1b
9599 There is a second pair of rules.
9601 @item Rule #1: Control flow does not exist. Only commands
9602 @* For example: the classic FOR loop or IF statement is not a control
9603 flow item, they are commands, there is no such thing as control flow
9605 @item Rule #2: If you think otherwise, See Rule #1
9606 @* Actually what happens is this: There are commands that by
9607 convention, act like control flow key words in other languages. One of
9608 those commands is the word ``for'', another command is ``if''.
9611 @section Per Rule #1 - All Results are strings
9612 Every Tcl command results in a string. The word ``result'' is used
9613 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
9614 Everything is a string}
9616 @section Tcl Quoting Operators
9617 In life of a Tcl script, there are two important periods of time, the
9618 difference is subtle.
9621 @item Evaluation Time
9624 The two key items here are how ``quoted things'' work in Tcl. Tcl has
9625 three primary quoting constructs, the [square-brackets] the
9626 @{curly-braces@} and ``double-quotes''
9628 By now you should know $VARIABLES always start with a $DOLLAR
9629 sign. BTW: To set a variable, you actually use the command ``set'', as
9630 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
9631 = 1'' statement, but without the equal sign.
9634 @item @b{[square-brackets]}
9635 @* @b{[square-brackets]} are command substitutions. It operates much
9636 like Unix Shell `back-ticks`. The result of a [square-bracket]
9637 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
9638 string}. These two statements are roughly identical:
9642 echo "The Date is: $X"
9645 puts "The Date is: $X"
9647 @item @b{``double-quoted-things''}
9648 @* @b{``double-quoted-things''} are just simply quoted
9649 text. $VARIABLES and [square-brackets] are expanded in place - the
9650 result however is exactly 1 string. @i{Remember Rule #1 - Everything
9654 puts "It is now \"[date]\", $x is in 1 hour"
9656 @item @b{@{Curly-Braces@}}
9657 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
9658 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
9659 'single-quote' operators in BASH shell scripts, with the added
9660 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
9661 nested 3 times@}@}@} NOTE: [date] is a bad example;
9662 at this writing, Jim/OpenOCD does not have a date command.
9665 @section Consequences of Rule 1/2/3/4
9667 The consequences of Rule 1 are profound.
9669 @subsection Tokenisation & Execution.
9671 Of course, whitespace, blank lines and #comment lines are handled in
9674 As a script is parsed, each (multi) line in the script file is
9675 tokenised and according to the quoting rules. After tokenisation, that
9676 line is immedatly executed.
9678 Multi line statements end with one or more ``still-open''
9679 @{curly-braces@} which - eventually - closes a few lines later.
9681 @subsection Command Execution
9683 Remember earlier: There are no ``control flow''
9684 statements in Tcl. Instead there are COMMANDS that simply act like
9685 control flow operators.
9687 Commands are executed like this:
9690 @item Parse the next line into (argc) and (argv[]).
9691 @item Look up (argv[0]) in a table and call its function.
9692 @item Repeat until End Of File.
9695 It sort of works like this:
9698 ReadAndParse( &argc, &argv );
9700 cmdPtr = LookupCommand( argv[0] );
9702 (*cmdPtr->Execute)( argc, argv );
9706 When the command ``proc'' is parsed (which creates a procedure
9707 function) it gets 3 parameters on the command line. @b{1} the name of
9708 the proc (function), @b{2} the list of parameters, and @b{3} the body
9709 of the function. Not the choice of words: LIST and BODY. The PROC
9710 command stores these items in a table somewhere so it can be found by
9713 @subsection The FOR command
9715 The most interesting command to look at is the FOR command. In Tcl,
9716 the FOR command is normally implemented in C. Remember, FOR is a
9717 command just like any other command.
9719 When the ascii text containing the FOR command is parsed, the parser
9720 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
9724 @item The ascii text 'for'
9725 @item The start text
9726 @item The test expression
9731 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
9732 Remember @i{Rule #1 - Everything is a string.} The key point is this:
9733 Often many of those parameters are in @{curly-braces@} - thus the
9734 variables inside are not expanded or replaced until later.
9736 Remember that every Tcl command looks like the classic ``main( argc,
9737 argv )'' function in C. In JimTCL - they actually look like this:
9741 MyCommand( Jim_Interp *interp,
9743 Jim_Obj * const *argvs );
9746 Real Tcl is nearly identical. Although the newer versions have
9747 introduced a byte-code parser and intepreter, but at the core, it
9748 still operates in the same basic way.
9750 @subsection FOR command implementation
9752 To understand Tcl it is perhaps most helpful to see the FOR
9753 command. Remember, it is a COMMAND not a control flow structure.
9755 In Tcl there are two underlying C helper functions.
9757 Remember Rule #1 - You are a string.
9759 The @b{first} helper parses and executes commands found in an ascii
9760 string. Commands can be seperated by semicolons, or newlines. While
9761 parsing, variables are expanded via the quoting rules.
9763 The @b{second} helper evaluates an ascii string as a numerical
9764 expression and returns a value.
9766 Here is an example of how the @b{FOR} command could be
9767 implemented. The pseudo code below does not show error handling.
9769 void Execute_AsciiString( void *interp, const char *string );
9771 int Evaluate_AsciiExpression( void *interp, const char *string );
9774 MyForCommand( void *interp,
9779 SetResult( interp, "WRONG number of parameters");
9783 // argv[0] = the ascii string just like C
9785 // Execute the start statement.
9786 Execute_AsciiString( interp, argv[1] );
9790 i = Evaluate_AsciiExpression(interp, argv[2]);
9795 Execute_AsciiString( interp, argv[3] );
9797 // Execute the LOOP part
9798 Execute_AsciiString( interp, argv[4] );
9802 SetResult( interp, "" );
9807 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
9808 in the same basic way.
9810 @section OpenOCD Tcl Usage
9812 @subsection source and find commands
9813 @b{Where:} In many configuration files
9814 @* Example: @b{ source [find FILENAME] }
9815 @*Remember the parsing rules
9817 @item The @command{find} command is in square brackets,
9818 and is executed with the parameter FILENAME. It should find and return
9819 the full path to a file with that name; it uses an internal search path.
9820 The RESULT is a string, which is substituted into the command line in
9821 place of the bracketed @command{find} command.
9822 (Don't try to use a FILENAME which includes the "#" character.
9823 That character begins Tcl comments.)
9824 @item The @command{source} command is executed with the resulting filename;
9825 it reads a file and executes as a script.
9827 @subsection format command
9828 @b{Where:} Generally occurs in numerous places.
9829 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
9835 puts [format "The answer: %d" [expr $x * $y]]
9838 @item The SET command creates 2 variables, X and Y.
9839 @item The double [nested] EXPR command performs math
9840 @* The EXPR command produces numerical result as a string.
9842 @item The format command is executed, producing a single string
9843 @* Refer to Rule #1.
9844 @item The PUTS command outputs the text.
9846 @subsection Body or Inlined Text
9847 @b{Where:} Various TARGET scripts.
9850 proc someproc @{@} @{
9851 ... multiple lines of stuff ...
9853 $_TARGETNAME configure -event FOO someproc
9854 #2 Good - no variables
9855 $_TARGETNAME confgure -event foo "this ; that;"
9856 #3 Good Curly Braces
9857 $_TARGETNAME configure -event FOO @{
9860 #4 DANGER DANGER DANGER
9861 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
9864 @item The $_TARGETNAME is an OpenOCD variable convention.
9865 @*@b{$_TARGETNAME} represents the last target created, the value changes
9866 each time a new target is created. Remember the parsing rules. When
9867 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
9868 the name of the target which happens to be a TARGET (object)
9870 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
9871 @*There are 4 examples:
9873 @item The TCLBODY is a simple string that happens to be a proc name
9874 @item The TCLBODY is several simple commands seperated by semicolons
9875 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
9876 @item The TCLBODY is a string with variables that get expanded.
9879 In the end, when the target event FOO occurs the TCLBODY is
9880 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
9881 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
9883 Remember the parsing rules. In case #3, @{curly-braces@} mean the
9884 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
9885 and the text is evaluated. In case #4, they are replaced before the
9886 ``Target Object Command'' is executed. This occurs at the same time
9887 $_TARGETNAME is replaced. In case #4 the date will never
9888 change. @{BTW: [date] is a bad example; at this writing,
9889 Jim/OpenOCD does not have a date command@}
9891 @subsection Global Variables
9892 @b{Where:} You might discover this when writing your own procs @* In
9893 simple terms: Inside a PROC, if you need to access a global variable
9894 you must say so. See also ``upvar''. Example:
9896 proc myproc @{ @} @{
9897 set y 0 #Local variable Y
9898 global x #Global variable X
9899 puts [format "X=%d, Y=%d" $x $y]
9902 @section Other Tcl Hacks
9903 @b{Dynamic variable creation}
9905 # Dynamically create a bunch of variables.
9906 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
9908 set vn [format "BIT%d" $x]
9912 set $vn [expr (1 << $x)]
9915 @b{Dynamic proc/command creation}
9917 # One "X" function - 5 uart functions.
9918 foreach who @{A B C D E@}
9919 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
9925 @node OpenOCD Concept Index
9926 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
9927 @comment case issue with ``Index.html'' and ``index.html''
9928 @comment Occurs when creating ``--html --no-split'' output
9929 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
9930 @unnumbered OpenOCD Concept Index
9934 @node Command and Driver Index
9935 @unnumbered Command and Driver Index