1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (OpenOCD)
27 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
45 * About:: About OpenOCD.
46 * Developers:: OpenOCD developers
47 * Building:: Building OpenOCD
48 * Running:: Running OpenOCD
49 * Configuration:: OpenOCD Configuration.
50 * Target library:: Target library
51 * Commands:: OpenOCD Commands
52 * Sample Scripts:: Sample Target Scripts
53 * GDB and OpenOCD:: Using GDB and OpenOCD
54 * TCL and OpenOCD:: Using TCL and OpenOCD
55 * TCL scripting API:: Tcl scripting API
56 * Upgrading:: Deprecated/Removed Commands
57 * FAQ:: Frequently Asked Questions
58 * License:: GNU Free Documentation License
66 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
67 and boundary-scan testing for embedded target devices. The targets are interfaced
68 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
69 connection types in the future.
71 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
72 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
73 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
74 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
76 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
77 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
78 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
84 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
85 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
86 Others interested in improving the state of free and open debug and testing technology
87 are welcome to participate.
89 Other developers have contributed support for additional targets and flashes as well
90 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
92 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
96 @cindex building OpenOCD
98 You can download the current SVN version with SVN client of your choice from the
99 following repositories:
101 (@uref{svn://svn.berlios.de/openocd/trunk})
105 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
107 Using the SVN command line client, you can use the following command to fetch the
108 latest version (make sure there is no (non-svn) directory called "openocd" in the
112 svn checkout svn://svn.berlios.de/openocd/trunk openocd
115 Building OpenOCD requires a recent version of the GNU autotools.
116 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
117 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
118 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
119 paths, resulting in obscure dependency errors (This is an observation I've gathered
120 from the logs of one user - correct me if I'm wrong).
122 You further need the appropriate driver files, if you want to build support for
123 a FTDI FT2232 based interface:
125 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
126 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
127 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
128 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
131 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
132 see contrib/libftdi for more details.
134 In general, the D2XX driver provides superior performance (several times as fast),
135 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
136 a kernel module, only a user space library.
138 To build OpenOCD (on both Linux and Cygwin), use the following commands:
142 Bootstrap generates the configure script, and prepares building on your system.
146 Configure generates the Makefiles used to build OpenOCD.
150 Make builds OpenOCD, and places the final executable in ./src/.
152 The configure script takes several options, specifying which JTAG interfaces
157 @option{--enable-parport}
159 @option{--enable-parport_ppdev}
161 @option{--enable-parport_giveio}
163 @option{--enable-amtjtagaccel}
165 @option{--enable-ft2232_ftd2xx}
166 @footnote{Using the latest D2XX drivers from FTDI and following their installation
167 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
170 @option{--enable-ft2232_libftdi}
172 @option{--with-ftd2xx=/path/to/d2xx/}
174 @option{--enable-gw16012}
176 @option{--enable-usbprog}
178 @option{--enable-presto_libftdi}
180 @option{--enable-presto_ftd2xx}
182 @option{--enable-jlink}
185 If you want to access the parallel port using the PPDEV interface you have to specify
186 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
187 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
188 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
190 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
191 absolute path containing no spaces.
193 Linux users should copy the various parts of the D2XX package to the appropriate
194 locations, i.e. /usr/include, /usr/lib.
198 @cindex running OpenOCD
200 @cindex --debug_level
203 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
204 Run with @option{--help} or @option{-h} to view the available command line switches.
206 It reads its configuration by default from the file openocd.cfg located in the current
207 working directory. This may be overwritten with the @option{-f <configfile>} command line
208 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
209 are executed in order.
211 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
213 To enable debug output (when reporting problems or working on OpenOCD itself), use
214 the @option{-d} command line switch. This sets the debug_level to "3", outputting
215 the most information, including debug messages. The default setting is "2", outputting
216 only informational messages, warnings and errors. You can also change this setting
217 from within a telnet or gdb session (@option{debug_level <n>}).
219 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
221 Search paths for config/script files can be added to OpenOCD by using
222 the @option{-s <search>} switch. The current directory and the OpenOCD target library
223 is in the search path by default.
225 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
226 with the target. In general, it is possible for the JTAG controller to be unresponsive until
227 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
230 @chapter Configuration
231 @cindex configuration
232 OpenOCD runs as a daemon, and reads it current configuration
233 by default from the file openocd.cfg in the current directory. A different configuration
234 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
236 The configuration file is used to specify on which ports the daemon listens for new
237 connections, the JTAG interface used to connect to the target, the layout of the JTAG
238 chain, the targets that should be debugged, and connected flashes.
240 @section Daemon configuration
243 @item @b{init} This command terminates the configuration stage and enters the normal
244 command mode. This can be useful to add commands to the startup scripts and commands
245 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
246 add "init" and "reset" at the end of the config script or at the end of the
247 OpenOCD command line using the @option{-c} command line switch.
249 @item @b{telnet_port} <@var{number}>
251 Port on which to listen for incoming telnet connections
252 @item @b{gdb_port} <@var{number}>
254 First port on which to listen for incoming GDB connections. The GDB port for the
255 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
256 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
258 Configures what OpenOCD will do when gdb detaches from the daeman.
259 Default behaviour is <@var{resume}>
260 @item @b{gdb_memory_map} <@var{enable|disable}>
261 @cindex gdb_memory_map
262 Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
263 requested. gdb will then know when to set hardware breakpoints, and program flash
264 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
265 for flash programming to work.
266 Default behaviour is <@var{enable}>
267 @item @b{gdb_flash_program} <@var{enable|disable}>
268 @cindex gdb_flash_program
269 Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
270 vFlash packet is received.
271 Default behaviour is <@var{enable}>
272 at item @b{tcl_port} <@var{number}>
274 Port on which to listen for incoming TCL syntax. This port is intended as
275 a simplified RPC connection that can be used by clients to issue commands
276 and get the output from the TCL engine.
279 @section JTAG interface configuration
282 @item @b{interface} <@var{name}>
284 Use the interface driver <@var{name}> to connect to the target. Currently supported
288 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
291 @item @b{amt_jtagaccel}
292 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
297 FTDI FT2232 based devices using either the open-source libftdi or the binary only
298 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
299 platform. The libftdi uses libusb, and should be portable to all systems that provide
304 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
308 ASIX PRESTO USB JTAG programmer.
312 usbprog is a freely programmable USB adapter.
316 Gateworks GW16012 JTAG programmer.
320 Segger jlink usb adapter
325 @item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
327 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
328 speed. The actual effect of this option depends on the JTAG interface used. Reset
329 speed is used during reset and post reset speed after reset. post reset speed
330 is optional, in which case the reset speed is used.
333 @item wiggler: maximum speed / @var{number}
334 @item ft2232: 6MHz / (@var{number}+1)
335 @item amt jtagaccel: 8 / 2**@var{number}
336 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
339 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
340 especially true for synthesized cores (-S).
342 @item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
344 Same as jtag_speed, except that the speed is specified in maximum kHz. If
345 the device can not support the rate asked for, or can not translate from
346 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
347 is not supported, then an error is reported.
349 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
351 The configuration of the reset signals available on the JTAG interface AND the target.
352 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
353 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
354 @option{srst_only} or @option{trst_and_srst}.
356 [@var{combination}] is an optional value specifying broken reset signal implementations.
357 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
358 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
359 that the system is reset together with the test logic (only hypothetical, I haven't
360 seen hardware with such a bug, and can be worked around).
361 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
362 The default behaviour if no option given is @option{separate}.
364 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
365 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
366 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
367 (default) and @option{srst_push_pull} for the system reset. These values only affect
368 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
370 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
372 Describes the devices that form the JTAG daisy chain, with the first device being
373 the one closest to TDO. The parameters are the length of the instruction register
374 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
375 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
376 The IDCODE instruction will in future be used to query devices for their JTAG
377 identification code. This line is the same for all ARM7 and ARM9 devices.
378 Other devices, like CPLDs, require different parameters. An example configuration
379 line for a Xilinx XC9500 CPLD would look like this:
381 jtag_device 8 0x01 0x0e3 0xfe
383 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
384 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
385 The IDCODE instruction is 0xfe.
387 @item @b{jtag_nsrst_delay} <@var{ms}>
388 @cindex jtag_nsrst_delay
389 How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
390 starting new JTAG operations.
391 @item @b{jtag_ntrst_delay} <@var{ms}>
392 @cindex jtag_ntrst_delay
393 How long (in milliseconds) OpenOCD should wait after deasserting nTRST before
394 starting new JTAG operations.
396 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
397 or on-chip features) keep a reset line asserted for some time after the external reset
401 @section parport options
404 @item @b{parport_port} <@var{number}>
406 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
407 the @file{/dev/parport} device
409 When using PPDEV to access the parallel port, use the number of the parallel port:
410 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
411 you may encounter a problem.
412 @item @b{parport_cable} <@var{name}>
413 @cindex parport_cable
414 The layout of the parallel port cable used to connect to the target.
415 Currently supported cables are
419 The original Wiggler layout, also supported by several clones, such
420 as the Olimex ARM-JTAG
421 @item @b{old_amt_wiggler}
422 @cindex old_amt_wiggler
423 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
424 version available from the website uses the original Wiggler layout ('@var{wiggler}')
427 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.
430 The Xilinx Parallel cable III.
433 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
434 This is also the layout used by the HollyGates design
435 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
438 The ST Parallel cable.
440 @item @b{parport_write_on_exit} <@var{on|off}>
441 @cindex parport_write_on_exit
442 This will configure the parallel driver to write a known value to the parallel
443 interface on exiting OpenOCD
446 @section amt_jtagaccel options
448 @item @b{parport_port} <@var{number}>
450 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
451 @file{/dev/parport} device
453 @section ft2232 options
456 @item @b{ft2232_device_desc} <@var{description}>
457 @cindex ft2232_device_desc
458 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
459 default value is used. This setting is only valid if compiled with FTD2XX support.
460 @item @b{ft2232_layout} <@var{name}>
461 @cindex ft2232_layout
462 The layout of the FT2232 GPIO signals used to control output-enables and reset
463 signals. Valid layouts are
466 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
468 Amontec JTAGkey and JTAGkey-tiny
471 @item @b{olimex-jtag}
474 American Microsystems M5960
475 @item @b{evb_lm3s811}
476 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
477 SRST signals on external connector
481 Hitex STM32 Performance Stick
483 Tin Can Tools Flyswatter
484 @item @b{turtelizer2}
485 egnite Software turtelizer2
490 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
491 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
492 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
494 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
496 @item @b{ft2232_latency} <@var{ms}>
497 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
498 ft2232_read() fails to return the expected number of bytes. This can be caused by
499 USB communication delays and has proved hard to reproduce and debug. Setting the
500 FT2232 latency timer to a larger value increases delays for short USB packages but it
501 also reduces the risk of timeouts before receiving the expected number of bytes.
502 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
505 @section ep93xx options
506 @cindex ep93xx options
507 Currently, there are no options available for the ep93xx interface.
510 @section Target configuration
513 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
516 Defines a target that should be debugged. Currently supported types are:
530 If you want to use a target board that is not on this list, see Adding a new
533 Endianess may be @option{little} or @option{big}.
536 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
537 completely independent (like the LPC2000 series), or where the JTAG interface is
538 unavailable for some time during startup (like the STR7 series), you can't use
539 @option{reset_halt} or @option{reset_init}.
541 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
542 @cindex target_script
543 Event is one of the following:
544 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
545 @option{pre_resume} or @option{gdb_program_config}.
546 @option{post_reset} and @option{reset} will produce the same results.
548 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
549 @cindex run_and_halt_time
550 The amount of time the debugger should wait after releasing reset before it asserts
551 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
553 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
554 <@var{backup}|@var{nobackup}>
556 Specifies a working area for the debugger to use. This may be used to speed-up
557 downloads to target memory and flash operations, or to perform otherwise unavailable
558 operations (some coprocessor operations on ARM7/9 systems, for example). The last
559 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
560 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
563 @subsection arm7tdmi options
564 @cindex arm7tdmi options
565 target arm7tdmi <@var{endianess}> <@var{jtag#}>
566 The arm7tdmi target definition requires at least one additional argument, specifying
567 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
568 The optional [@var{variant}] parameter has been removed in recent versions.
569 The correct feature set is determined at runtime.
571 @subsection arm720t options
572 @cindex arm720t options
573 ARM720t options are similar to ARM7TDMI options.
575 @subsection arm9tdmi options
576 @cindex arm9tdmi options
577 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
578 @option{arm920t}, @option{arm922t} and @option{arm940t}.
579 This enables the hardware single-stepping support found on these cores.
581 @subsection arm920t options
582 @cindex arm920t options
583 ARM920t options are similar to ARM9TDMI options.
585 @subsection arm966e options
586 @cindex arm966e options
587 ARM966e options are similar to ARM9TDMI options.
589 @subsection cortex_m3 options
590 @cindex cortex_m3 options
591 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
592 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
593 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
594 be detected and the normal reset behaviour used.
596 @subsection xscale options
597 @cindex xscale options
598 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
599 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
601 @section Flash configuration
602 @cindex Flash configuration
605 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
606 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
608 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
609 and <@var{bus_width}> bytes using the selected flash <driver>.
612 @subsection lpc2000 options
613 @cindex lpc2000 options
615 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
616 <@var{clock}> [@var{calc_checksum}]
617 LPC flashes don't require the chip and bus width to be specified. Additional
618 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
619 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
620 of the target this flash belongs to (first is 0), the frequency at which the core
621 is currently running (in kHz - must be an integral number), and the optional keyword
622 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
625 @subsection cfi options
628 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
630 CFI flashes require the number of the target they're connected to as an additional
631 argument. The CFI driver makes use of a working area (specified for the target)
632 to significantly speed up operation.
634 @var{chip_width} and @var{bus_width} are specified in bytes.
636 @subsection at91sam7 options
637 @cindex at91sam7 options
639 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
640 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
641 reading the chip-id and type.
643 @subsection str7 options
646 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
647 variant can be either STR71x, STR73x or STR75x.
649 @subsection str9 options
652 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
653 The str9 needs the flash controller to be configured prior to Flash programming, eg.
655 str9x flash_config 0 4 2 0 0x80000
657 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
659 @subsection str9 options (str9xpec driver)
661 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
662 Before using the flash commands the turbo mode will need enabling using str9xpec
663 @option{enable_turbo} <@var{num>.}
665 Only use this driver for locking/unlocking the device or configuring the option bytes.
666 Use the standard str9 driver for programming.
668 @subsection stellaris (LM3Sxxx) options
669 @cindex stellaris (LM3Sxxx) options
671 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
672 stellaris flash plugin only require the @var{target#}.
674 @subsection stm32x options
675 @cindex stm32x options
677 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
678 stm32x flash plugin only require the @var{target#}.
681 @chapter Target library
682 @cindex Target library
684 OpenOCD comes with a target configuration script library. These scripts can be
685 used as-is or serve as a starting point.
687 The target library is published together with the openocd executable and
688 the path to the target library is in the OpenOCD script search path.
689 Similarly there are example scripts for configuring the JTAG interface.
691 The command line below uses the example parport configuration scripts
692 that ship with OpenOCD, then configures the str710.cfg target and
693 finally issues the init and reset command. The communication speed
694 is set to 10kHz for reset and 8MHz for post reset.
698 openocd -f interface/parport.cfg -c "jtag_khz 10 8000" -f target/str710.cfg -c "init" -c "reset"
702 To list the target scripts available:
705 $ ls /usr/local/lib/openocd/target
707 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
708 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
709 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
710 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
718 OpenOCD allows user interaction through a GDB server (default: port 3333),
719 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
720 is available from both the telnet interface and a GDB session. To issue commands to the
721 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
722 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
725 The TCL interface is used as a simplified RPC mechanism that feeds all the
726 input into the TCL interpreter and returns the output from the evaluation of
732 @item @b{sleep} <@var{msec}>
734 Wait for n milliseconds before resuming. Useful in connection with script files
735 (@var{script} command and @var{target_script} configuration).
739 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
741 @item @b{debug_level} [@var{n}]
743 Display or adjust debug level to n<0-3>
745 @item @b{fast} [@var{enable/disable}]
747 Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
748 downloads and fast memory access will work if the JTAG interface isn't too fast and
749 the core doesn't run at a too low frequency. Note that this option only changes the default
750 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
753 The target specific "dangerous" optimisation tweaking options may come and go
754 as more robust and user friendly ways are found to ensure maximum throughput
755 and robustness with a minimum of configuration.
757 Typically the "fast enable" is specified first on the command line:
760 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
763 @item @b{log_output} <@var{file}>
765 Redirect logging to <file> (default: stderr)
767 @item @b{script} <@var{file}>
769 Execute commands from <file>
773 @subsection Target state handling
775 @item @b{poll} [@option{on}|@option{off}]
777 Poll the target for its current state. If the target is in debug mode, architecture
778 specific information about the current state is printed. An optional parameter
779 allows continuous polling to be enabled and disabled.
781 @item @b{halt} [@option{ms}]
783 Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
784 Default [@option{ms}] is 5 seconds if no arg given.
785 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
786 will stop OpenOCD from waiting.
788 @item @b{wait_halt} [@option{ms}]
790 Wait for the target to enter debug mode. Optional [@option{ms}] is
791 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
794 @item @b{resume} [@var{address}]
796 Resume the target at its current code position, or at an optional address.
797 OpenOCD will wait 5 seconds for the target to resume.
799 @item @b{step} [@var{address}]
801 Single-step the target at its current code position, or at an optional address.
803 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
804 |@option{run_and_init}]
806 Perform a hard-reset. The optional parameter specifies what should happen after the reset.
807 This optional parameter overrides the setting specified in the configuration file,
808 making the new behaviour the default for the @option{reset} command.
810 With no arguments a "reset run" is executed
817 Immediately halt the target (works only with certain configurations).
820 Immediately halt the target, and execute the reset script (works only with certain
822 @item @b{run_and_halt}
823 @cindex reset run_and_halt
824 Let the target run for a certain amount of time, then request a halt.
825 @item @b{run_and_init}
826 @cindex reset run_and_init
827 Let the target run for a certain amount of time, then request a halt. Execute the
828 reset script once the target enters debug mode.
832 @subsection Memory access commands
833 These commands allow accesses of a specific size to the memory system:
835 @item @b{mdw} <@var{addr}> [@var{count}]
838 @item @b{mdh} <@var{addr}> [@var{count}]
840 display memory half-words
841 @item @b{mdb} <@var{addr}> [@var{count}]
844 @item @b{mww} <@var{addr}> <@var{value}>
847 @item @b{mwh} <@var{addr}> <@var{value}>
849 write memory half-word
850 @item @b{mwb} <@var{addr}> <@var{value}>
854 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
856 Load image <@var{file}> to target memory at <@var{address}>
857 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
859 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
860 (binary) <@var{file}>.
861 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
863 Verify <@var{file}> against target memory starting at <@var{address}>.
864 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
867 @subsection Flash commands
868 @cindex Flash commands
870 @item @b{flash banks}
872 List configured flash banks
873 @item @b{flash info} <@var{num}>
875 Print info about flash bank <@option{num}>
876 @item @b{flash probe} <@var{num}>
878 Identify the flash, or validate the parameters of the configured flash. Operation
879 depends on the flash type.
880 @item @b{flash erase_check} <@var{num}>
881 @cindex flash erase_check
882 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
883 updates the erase state information displayed by @option{flash info}. That means you have
884 to issue an @option{erase_check} command after erasing or programming the device to get
886 @item @b{flash protect_check} <@var{num}>
887 @cindex flash protect_check
888 Check protection state of sectors in flash bank <num>.
889 @option{flash erase_sector} using the same syntax.
890 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
891 @cindex flash erase_sector
892 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
893 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
894 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
896 @item @b{flash erase_address} <@var{address}> <@var{length}>
897 @cindex flash erase_address
898 Erase sectors starting at <@var{address}> for <@var{length}> bytes
899 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
900 @cindex flash write_bank
901 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
902 <@option{offset}> bytes from the beginning of the bank.
903 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
904 @cindex flash write_image
905 Write the image <@var{file}> to the current target's flash bank(s). A relocation
906 [@var{offset}] can be specified and the file [@var{type}] can be specified
907 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
908 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
909 if the @option{erase} parameter is given.
910 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
911 @cindex flash protect
912 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
913 <@var{last}> of @option{flash bank} <@var{num}>.
917 @section Target Specific Commands
918 @cindex Target Specific Commands
920 @subsection AT91SAM7 specific commands
921 @cindex AT91SAM7 specific commands
922 The flash configuration is deduced from the chip identification register. The flash
923 controller handles erases automatically on a page (128/265 byte) basis so erase is
924 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
925 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
926 that can be erased separatly. Only an EraseAll command is supported by the controller
927 for each flash plane and this is called with
929 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
930 bulk erase flash planes first_plane to last_plane.
931 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
932 @cindex at91sam7 gpnvm
933 set or clear a gpnvm bit for the processor
936 @subsection STR9 specific commands
937 @cindex STR9 specific commands
938 These are flash specific commands when using the str9xpec driver.
940 @item @b{str9xpec enable_turbo} <@var{num}>
941 @cindex str9xpec enable_turbo
942 enable turbo mode, simply this will remove the str9 from the chain and talk
943 directly to the embedded flash controller.
944 @item @b{str9xpec disable_turbo} <@var{num}>
945 @cindex str9xpec disable_turbo
946 restore the str9 into jtag chain.
947 @item @b{str9xpec lock} <@var{num}>
948 @cindex str9xpec lock
949 lock str9 device. The str9 will only respond to an unlock command that will
951 @item @b{str9xpec unlock} <@var{num}>
952 @cindex str9xpec unlock
954 @item @b{str9xpec options_read} <@var{num}>
955 @cindex str9xpec options_read
956 read str9 option bytes.
957 @item @b{str9xpec options_write} <@var{num}>
958 @cindex str9xpec options_write
959 write str9 option bytes.
962 @subsection STR9 configuration
963 @cindex STR9 configuration
965 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
966 <@var{BBADR}> <@var{NBBADR}>
967 @cindex str9x flash_config
968 Configure str9 flash controller.
970 eg. str9x flash_config 0 4 2 0 0x80000
972 BBSR - Boot Bank Size register
973 NBBSR - Non Boot Bank Size register
974 BBADR - Boot Bank Start Address register
975 NBBADR - Boot Bank Start Address register
979 @subsection STR9 option byte configuration
980 @cindex STR9 option byte configuration
982 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
983 @cindex str9xpec options_cmap
984 configure str9 boot bank.
985 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
986 @cindex str9xpec options_lvdthd
987 configure str9 lvd threshold.
988 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
989 @cindex str9xpec options_lvdsel
990 configure str9 lvd source.
991 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
992 @cindex str9xpec options_lvdwarn
993 configure str9 lvd reset warning source.
996 @subsection STM32x specific commands
997 @cindex STM32x specific commands
999 These are flash specific commands when using the stm32x driver.
1001 @item @b{stm32x lock} <@var{num}>
1004 @item @b{stm32x unlock} <@var{num}>
1005 @cindex stm32x unlock
1006 unlock stm32 device.
1007 @item @b{stm32x options_read} <@var{num}>
1008 @cindex stm32x options_read
1009 read stm32 option bytes.
1010 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1011 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1012 @cindex stm32x options_write
1013 write stm32 option bytes.
1014 @item @b{stm32x mass_erase} <@var{num}>
1015 @cindex stm32x mass_erase
1016 mass erase flash memory.
1019 @subsection Stellaris specific commands
1020 @cindex Stellaris specific commands
1022 These are flash specific commands when using the Stellaris driver.
1024 @item @b{stellaris mass_erase} <@var{num}>
1025 @cindex stellaris mass_erase
1026 mass erase flash memory.
1030 @section Architecture Specific Commands
1031 @cindex Architecture Specific Commands
1033 @subsection ARMV4/5 specific commands
1034 @cindex ARMV4/5 specific commands
1036 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1037 or Intel XScale (XScale isn't supported yet).
1039 @item @b{armv4_5 reg}
1041 Display a list of all banked core registers, fetching the current value from every
1042 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1044 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1045 @cindex armv4_5 core_mode
1046 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1047 The target is resumed in the currently set @option{core_mode}.
1050 @subsection ARM7/9 specific commands
1051 @cindex ARM7/9 specific commands
1053 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1054 ARM920t or ARM926EJ-S.
1056 @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
1057 @cindex arm7_9 sw_bkpts
1058 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
1059 one of the watchpoint registers to implement software breakpoints. Disabling
1060 SW Bkpts frees that register again.
1061 @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
1062 @cindex arm7_9 force_hw_bkpts
1063 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
1064 breakpoints are turned into hardware breakpoints.
1065 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1066 @cindex arm7_9 dbgrq
1067 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1068 safe for all but ARM7TDMI--S cores (like Philips LPC).
1069 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1070 @cindex arm7_9 fast_memory_access
1071 Allow OpenOCD to read and write memory without checking completion of
1072 the operation. This provides a huge speed increase, especially with USB JTAG
1073 cables (FT2232), but might be unsafe if used with targets running at a very low
1074 speed, like the 32kHz startup clock of an AT91RM9200.
1075 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1076 @cindex arm7_9 dcc_downloads
1077 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1078 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1079 unsafe, especially with targets running at a very low speed. This command was introduced
1080 with OpenOCD rev. 60.
1083 @subsection ARM720T specific commands
1084 @cindex ARM720T specific commands
1087 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1088 @cindex arm720t cp15
1089 display/modify cp15 register <@option{num}> [@option{value}].
1090 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1091 @cindex arm720t md<bhw>_phys
1092 Display memory at physical address addr.
1093 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1094 @cindex arm720t mw<bhw>_phys
1095 Write memory at physical address addr.
1096 @item @b{arm720t virt2phys} <@var{va}>
1097 @cindex arm720t virt2phys
1098 Translate a virtual address to a physical address.
1101 @subsection ARM9TDMI specific commands
1102 @cindex ARM9TDMI specific commands
1105 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1106 @cindex arm9tdmi vector_catch
1107 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1108 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1109 @option{irq} @option{fiq}.
1111 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1114 @subsection ARM966E specific commands
1115 @cindex ARM966E specific commands
1118 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1119 @cindex arm966e cp15
1120 display/modify cp15 register <@option{num}> [@option{value}].
1123 @subsection ARM920T specific commands
1124 @cindex ARM920T specific commands
1127 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1128 @cindex arm920t cp15
1129 display/modify cp15 register <@option{num}> [@option{value}].
1130 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1131 @cindex arm920t cp15i
1132 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1133 @item @b{arm920t cache_info}
1134 @cindex arm920t cache_info
1135 Print information about the caches found. This allows you to see if your target
1136 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1137 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1138 @cindex arm920t md<bhw>_phys
1139 Display memory at physical address addr.
1140 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1141 @cindex arm920t mw<bhw>_phys
1142 Write memory at physical address addr.
1143 @item @b{arm920t read_cache} <@var{filename}>
1144 @cindex arm920t read_cache
1145 Dump the content of ICache and DCache to a file.
1146 @item @b{arm920t read_mmu} <@var{filename}>
1147 @cindex arm920t read_mmu
1148 Dump the content of the ITLB and DTLB to a file.
1149 @item @b{arm920t virt2phys} <@var{va}>
1150 @cindex arm920t virt2phys
1151 Translate a virtual address to a physical address.
1154 @subsection ARM926EJS specific commands
1155 @cindex ARM926EJS specific commands
1158 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1159 @cindex arm926ejs cp15
1160 display/modify cp15 register <@option{num}> [@option{value}].
1161 @item @b{arm926ejs cache_info}
1162 @cindex arm926ejs cache_info
1163 Print information about the caches found.
1164 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1165 @cindex arm926ejs md<bhw>_phys
1166 Display memory at physical address addr.
1167 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1168 @cindex arm926ejs mw<bhw>_phys
1169 Write memory at physical address addr.
1170 @item @b{arm926ejs virt2phys} <@var{va}>
1171 @cindex arm926ejs virt2phys
1172 Translate a virtual address to a physical address.
1176 @section Debug commands
1177 @cindex Debug commands
1178 The following commands give direct access to the core, and are most likely
1179 only useful while debugging OpenOCD.
1181 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1182 @cindex arm7_9 write_xpsr
1183 Immediately write either the current program status register (CPSR) or the saved
1184 program status register (SPSR), without changing the register cache (as displayed
1185 by the @option{reg} and @option{armv4_5 reg} commands).
1186 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1187 <@var{0=cpsr},@var{1=spsr}>
1188 @cindex arm7_9 write_xpsr_im8
1189 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1190 operation (similar to @option{write_xpsr}).
1191 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1192 @cindex arm7_9 write_core_reg
1193 Write a core register, without changing the register cache (as displayed by the
1194 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1195 encoding of the [M4:M0] bits of the PSR.
1199 @section JTAG commands
1200 @cindex JTAG commands
1202 @item @b{scan_chain}
1204 Print current scan chain configuration.
1205 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1208 @item @b{endstate} <@var{tap_state}>
1210 Finish JTAG operations in <@var{tap_state}>.
1211 @item @b{runtest} <@var{num_cycles}>
1213 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1214 @item @b{statemove} [@var{tap_state}]
1216 Move to current endstate or [@var{tap_state}]
1217 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1219 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1220 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1222 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1223 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1224 @cindex verify_ircapture
1225 Verify value captured during Capture-IR. Default is enabled.
1226 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1228 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1229 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1231 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1235 @section Target Requests
1236 @cindex Target Requests
1237 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1238 See libdcc in the contrib dir for more details.
1240 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1241 @cindex target_request debugmsgs
1242 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1245 @node Sample Scripts
1246 @chapter Sample Scripts
1249 This page shows how to use the target library.
1251 The configuration script can be divided in the following section:
1253 @item daemon configuration
1255 @item jtag scan chain
1256 @item target configuration
1257 @item flash configuration
1260 Detailed information about each section can be found at OpenOCD configuration.
1262 @section AT91R40008 example
1263 @cindex AT91R40008 example
1264 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1265 the CPU upon startup of the OpenOCD daemon.
1267 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1271 @node GDB and OpenOCD
1272 @chapter GDB and OpenOCD
1273 @cindex GDB and OpenOCD
1274 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1275 to debug remote targets.
1277 @section Connecting to gdb
1278 @cindex Connecting to gdb
1279 A connection is typically started as follows:
1281 target remote localhost:3333
1283 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1285 To see a list of available OpenOCD commands type @option{monitor help} on the
1288 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1289 to be sent by the gdb server (openocd) to gdb. Typical information includes
1290 packet size and device memory map.
1292 Previous versions of OpenOCD required the following gdb options to increase
1293 the packet size and speed up gdb communication.
1295 set remote memory-write-packet-size 1024
1296 set remote memory-write-packet-size fixed
1297 set remote memory-read-packet-size 1024
1298 set remote memory-read-packet-size fixed
1300 This is now handled in the @option{qSupported} PacketSize.
1302 @section Programming using gdb
1303 @cindex Programming using gdb
1305 By default the target memory map is sent to gdb, this can be disabled by
1306 the following OpenOCD config option:
1308 gdb_memory_map disable
1310 For this to function correctly a valid flash config must also be configured
1311 in OpenOCD. For faster performance you should also configure a valid
1314 Informing gdb of the memory map of the target will enable gdb to protect any
1315 flash area of the target and use hardware breakpoints by default. This means
1316 that the OpenOCD option @option{arm7_9 force_hw_bkpts} is not required when
1319 To view the configured memory map in gdb, use the gdb command @option{info mem}
1320 All other unasigned addresses within gdb are treated as RAM.
1322 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1323 this can be changed to the old behaviour by using the following gdb command.
1325 set mem inaccessible-by-default off
1328 If @option{gdb_flash_program enable} is also used, gdb will be able to
1329 program any flash memory using the vFlash interface.
1331 gdb will look at the target memory map when a load command is given, if any
1332 areas to be programmed lie within the target flash area the vFlash packets
1335 If the target needs configuring before gdb programming, a script can be executed.
1337 target_script 0 gdb_program_config config.script
1340 To verify any flash programming the gdb command @option{compare-sections}
1343 @node TCL and OpenOCD
1344 @chapter TCL and OpenOCD
1345 @cindex TCL and OpenOCD
1346 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1349 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1351 The command and file interfaces are fairly straightforward, while the network
1352 port is geared toward intergration with external clients. A small example
1353 of an external TCL script that can connect to openocd is shown below.
1356 # Simple tcl client to connect to openocd
1357 puts "Use empty line to exit"
1358 set fo [socket 127.0.0.1 6666]
1359 puts -nonewline stdout "> "
1361 while {[gets stdin line] >= 0} {
1362 if {$line eq {}} break
1367 puts -nonewline stdout "> "
1373 This script can easily be modified to front various GUIs or be a sub
1374 component of a larger framework for control and interaction.
1377 @node TCL scripting API
1378 @chapter TCL scripting API
1379 @cindex TCL scripting API
1382 The commands are stateless. E.g. the telnet command line has a concept
1383 of currently active target, the Tcl API proc's take this sort of state
1384 information as an argument to each proc.
1386 There are three main types of return values: single value, name value
1387 pair list and lists.
1389 Name value pair. The proc 'foo' below returns a name/value pair
1395 > set foo(you) Oyvind
1396 > set foo(mouse) Micky
1397 > set foo(duck) Donald
1405 me Duane you Oyvind mouse Micky duck Donald
1407 Thus, to get the names of the associative array is easy:
1409 foreach { name value } [set foo] {
1410 puts "Name: $name, Value: $value"
1414 Lists returned must be relatively small. Otherwise a range
1415 should be passed in to the proc in question.
1417 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
1418 is the low level API upon which "flash banks" is implemented.
1420 OpenOCD commands can consist of two words, e.g. "flash banks". The
1421 startup.tcl "unknown" proc will translate this into a tcl proc
1422 called "flash_banks".
1426 @chapter Deprecated/Removed Commands
1427 @cindex Deprecated/Removed Commands
1428 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1431 @item @b{load_binary}
1433 use @option{load_image} command with same args
1434 @item @b{dump_binary}
1436 use @option{dump_image} command with same args
1437 @item @b{flash erase}
1439 use @option{flash erase_sector} command with same args
1440 @item @b{flash write}
1442 use @option{flash write_bank} command with same args
1443 @item @b{flash write_binary}
1444 @cindex flash write_binary
1445 use @option{flash write_bank} command with same args
1446 @item @b{arm7_9 fast_writes}
1447 @cindex arm7_9 fast_writes
1448 use @option{arm7_9 fast_memory_access} command with same args
1449 @item @b{flash auto_erase}
1450 @cindex flash auto_erase
1451 use @option{flash write_image} command passing @option{erase} as the first parameter.
1458 @item OpenOCD complains about a missing cygwin1.dll.
1460 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1461 claims to come with all the necessary dlls. When using Cygwin, try launching
1462 OpenOCD from the Cygwin shell.
1464 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1465 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1466 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1468 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1469 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1470 software breakpoints consume one of the two available hardware breakpoints,
1471 and are therefore disabled by default. If your code is running from RAM, you
1472 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1473 your code resides in Flash, you can't use software breakpoints, but you can force
1474 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1476 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1477 and works sometimes fine.
1479 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1480 clock at the time you're programming the flash. If you've specified the crystal's
1481 frequency, make sure the PLL is disabled, if you've specified the full core speed
1482 (e.g. 60MHz), make sure the PLL is enabled.
1484 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1485 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1486 out while waiting for end of scan, rtck was disabled".
1488 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1489 settings in your PC BIOS (ECP, EPP, and different versions of those).
1491 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1492 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1493 memory read caused data abort".
1495 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1496 beyond the last valid frame. It might be possible to prevent this by setting up
1497 a proper "initial" stack frame, if you happen to know what exactly has to
1498 be done, feel free to add this here.
1500 @item I get the following message in the OpenOCD console (or log file):
1501 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1503 This warning doesn't indicate any serious problem, as long as you don't want to
1504 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1505 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
1506 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1507 independently. With this setup, it's not possible to halt the core right out of
1508 reset, everything else should work fine.
1510 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1511 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1512 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1513 quit with an error message. Is there a stability issue with OpenOCD?
1515 No, this is not a stability issue concerning OpenOCD. Most users have solved
1516 this issue by simply using a self-powered USB hub, which they connect their
1517 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1518 supply stable enough for the Amontec JTAGkey to be operated.
1520 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1521 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1522 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1523 What does that mean and what might be the reason for this?
1525 First of all, the reason might be the USB power supply. Try using a self-powered
1526 hub instead of a direct connection to your computer. Secondly, the error code 4
1527 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1528 chip ran into some sort of error - this points us to a USB problem.
1530 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1531 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1532 What does that mean and what might be the reason for this?
1534 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1535 has closed the connection to OpenOCD. This might be a GDB issue.
1537 @item In the configuration file in the section where flash device configurations
1538 are described, there is a parameter for specifying the clock frequency for
1539 LPC2000 internal flash devices (e.g.
1540 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1541 which must be specified in kilohertz. However, I do have a quartz crystal of a
1542 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1543 Is it possible to specify real numbers for the clock frequency?
1545 No. The clock frequency specified here must be given as an integral number.
1546 However, this clock frequency is used by the In-Application-Programming (IAP)
1547 routines of the LPC2000 family only, which seems to be very tolerant concerning
1548 the given clock frequency, so a slight difference between the specified clock
1549 frequency and the actual clock frequency will not cause any trouble.
1551 @item Do I have to keep a specific order for the commands in the configuration file?
1553 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1554 listed for the JTAG scan chain must be given in the right order (jtag_device),
1555 with the device closest to the TDO-Pin being listed first. In general,
1556 whenever objects of the same type exist which require an index number, then
1557 these objects must be given in the right order (jtag_devices, targets and flash
1558 banks - a target references a jtag_device and a flash bank references a target).
1560 @item Sometimes my debugging session terminates with an error. When I look into the
1561 log file, I can see these error messages: Error: arm7_9_common.c:561
1562 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP