1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
15 Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
17 Permission is granted to copy, distribute and/or modify this document
18 under the terms of the GNU Free Documentation License, Version 1.2 or
19 any later version published by the Free Software Foundation; with no
20 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
21 Texts. A copy of the license is included in the section entitled ``GNU
22 Free Documentation License''.
27 @title Open On-Chip Debugger (OpenOCD)
28 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
29 @subtitle @value{UPDATED}
31 @vskip 0pt plus 1filll
37 @node Top, About, , (dir)
40 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
41 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
46 * About:: About OpenOCD.
47 * Developers:: OpenOCD developers
48 * Building:: Building OpenOCD
49 * Running:: Running OpenOCD
50 * Configuration:: OpenOCD Configuration.
51 * Target library:: Target library
52 * Commands:: OpenOCD Commands
53 * Sample Scripts:: Sample Target Scripts
54 * GDB and OpenOCD:: Using GDB and OpenOCD
55 * TCL and OpenOCD:: Using TCL and OpenOCD
56 * TCL scripting API:: Tcl scripting API
57 * Upgrading:: Deprecated/Removed Commands
58 * FAQ:: Frequently Asked Questions
59 * License:: GNU Free Documentation License
67 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
68 and boundary-scan testing for embedded target devices. The targets are interfaced
69 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
70 connection types in the future.
72 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
73 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
74 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
75 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
77 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
78 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
79 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
85 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
86 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
87 Others interested in improving the state of free and open debug and testing technology
88 are welcome to participate.
90 Other developers have contributed support for additional targets and flashes as well
91 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
93 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
97 @cindex building OpenOCD
99 If you are interested in getting actual work done rather than building
100 OpenOCD, then check if your interface supplier provides binaries for
101 you. Chances are that that binary is from some SVN version that is more
102 stable than SVN trunk where bleeding edge development takes place.
105 You can download the current SVN version with SVN client of your choice from the
106 following repositories:
108 (@uref{svn://svn.berlios.de/openocd/trunk})
112 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
114 Using the SVN command line client, you can use the following command to fetch the
115 latest version (make sure there is no (non-svn) directory called "openocd" in the
119 svn checkout svn://svn.berlios.de/openocd/trunk openocd
122 Building OpenOCD requires a recent version of the GNU autotools.
123 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
124 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
125 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
126 paths, resulting in obscure dependency errors (This is an observation I've gathered
127 from the logs of one user - correct me if I'm wrong).
129 You further need the appropriate driver files, if you want to build support for
130 a FTDI FT2232 based interface:
132 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
133 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
134 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
135 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
138 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
139 see contrib/libftdi for more details.
141 In general, the D2XX driver provides superior performance (several times as fast),
142 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
143 a kernel module, only a user space library.
145 To build OpenOCD (on both Linux and Cygwin), use the following commands:
149 Bootstrap generates the configure script, and prepares building on your system.
153 Configure generates the Makefiles used to build OpenOCD.
157 Make builds OpenOCD, and places the final executable in ./src/.
159 The configure script takes several options, specifying which JTAG interfaces
164 @option{--enable-parport}
166 @option{--enable-parport_ppdev}
168 @option{--enable-parport_giveio}
170 @option{--enable-amtjtagaccel}
172 @option{--enable-ft2232_ftd2xx}
173 @footnote{Using the latest D2XX drivers from FTDI and following their installation
174 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
177 @option{--enable-ft2232_libftdi}
179 @option{--with-ftd2xx=/path/to/d2xx/}
181 @option{--enable-gw16012}
183 @option{--enable-usbprog}
185 @option{--enable-presto_libftdi}
187 @option{--enable-presto_ftd2xx}
189 @option{--enable-jlink}
192 If you want to access the parallel port using the PPDEV interface you have to specify
193 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
194 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
195 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
197 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
198 absolute path containing no spaces.
200 Linux users should copy the various parts of the D2XX package to the appropriate
201 locations, i.e. /usr/include, /usr/lib.
203 Miscellaneous configure options
207 @option{--enable-gccwarnings} - enable extra gcc warnings during build
212 @cindex running OpenOCD
214 @cindex --debug_level
217 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
218 Run with @option{--help} or @option{-h} to view the available command line switches.
220 It reads its configuration by default from the file openocd.cfg located in the current
221 working directory. This may be overwritten with the @option{-f <configfile>} command line
222 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
223 are executed in order.
225 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
227 To enable debug output (when reporting problems or working on OpenOCD itself), use
228 the @option{-d} command line switch. This sets the debug_level to "3", outputting
229 the most information, including debug messages. The default setting is "2", outputting
230 only informational messages, warnings and errors. You can also change this setting
231 from within a telnet or gdb session (@option{debug_level <n>}).
233 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
235 Search paths for config/script files can be added to OpenOCD by using
236 the @option{-s <search>} switch. The current directory and the OpenOCD target library
237 is in the search path by default.
239 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
240 with the target. In general, it is possible for the JTAG controller to be unresponsive until
241 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
244 @chapter Configuration
245 @cindex configuration
246 OpenOCD runs as a daemon, and reads it current configuration
247 by default from the file openocd.cfg in the current directory. A different configuration
248 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
250 The configuration file is used to specify on which ports the daemon listens for new
251 connections, the JTAG interface used to connect to the target, the layout of the JTAG
252 chain, the targets that should be debugged, and connected flashes.
254 @section Daemon configuration
257 @item @b{init} This command terminates the configuration stage and enters the normal
258 command mode. This can be useful to add commands to the startup scripts and commands
259 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
260 add "init" and "reset" at the end of the config script or at the end of the
261 OpenOCD command line using the @option{-c} command line switch.
263 @item @b{telnet_port} <@var{number}>
265 Port on which to listen for incoming telnet connections
266 @item @b{gdb_port} <@var{number}>
268 First port on which to listen for incoming GDB connections. The GDB port for the
269 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
270 @item @b{gdb_breakpoint_override} <@var{hard/soft/disabled}>
271 @cindex gdb_breakpoint_override
272 hard/soft/disabled - force breakpoint type for gdb 'break' commands.
273 The raison d'etre for this option is to support GDB GUI's without
274 a hard/soft breakpoint concept where the default OpenOCD and
275 GDB behaviour is not sufficient. Note that GDB will use hardware
276 breakpoints if the memory map has been set up for flash regions.
278 This option replaces older arm7_9 target commands that addressed
280 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
282 Configures what OpenOCD will do when gdb detaches from the daeman.
283 Default behaviour is <@var{resume}>
284 @item @b{gdb_memory_map} <@var{enable|disable}>
285 @cindex gdb_memory_map
286 Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
287 requested. gdb will then know when to set hardware breakpoints, and program flash
288 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
289 for flash programming to work.
290 Default behaviour is <@var{enable}>
291 @item @b{gdb_flash_program} <@var{enable|disable}>
292 @cindex gdb_flash_program
293 Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
294 vFlash packet is received.
295 Default behaviour is <@var{enable}>
296 at item @b{tcl_port} <@var{number}>
298 Port on which to listen for incoming TCL syntax. This port is intended as
299 a simplified RPC connection that can be used by clients to issue commands
300 and get the output from the TCL engine.
303 @section JTAG interface configuration
306 @item @b{interface} <@var{name}>
308 Use the interface driver <@var{name}> to connect to the target. Currently supported
312 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
315 @item @b{amt_jtagaccel}
316 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
321 FTDI FT2232 based devices using either the open-source libftdi or the binary only
322 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
323 platform. The libftdi uses libusb, and should be portable to all systems that provide
328 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
332 ASIX PRESTO USB JTAG programmer.
336 usbprog is a freely programmable USB adapter.
340 Gateworks GW16012 JTAG programmer.
344 Segger jlink usb adapter
349 @item @b{jtag_speed} <@var{reset speed}>
351 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
352 speed. The actual effect of this option depends on the JTAG interface used.
354 The speed used during reset can be adjusted using setting jtag_speed during
355 pre_reset and post_reset events.
358 @item wiggler: maximum speed / @var{number}
359 @item ft2232: 6MHz / (@var{number}+1)
360 @item amt jtagaccel: 8 / 2**@var{number}
361 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
364 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
365 especially true for synthesized cores (-S).
367 @item @b{jtag_khz} <@var{reset speed kHz}>
369 Same as jtag_speed, except that the speed is specified in maximum kHz. If
370 the device can not support the rate asked for, or can not translate from
371 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
372 is not supported, then an error is reported.
374 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
376 The configuration of the reset signals available on the JTAG interface AND the target.
377 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
378 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
379 @option{srst_only} or @option{trst_and_srst}.
381 [@var{combination}] is an optional value specifying broken reset signal implementations.
382 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
383 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
384 that the system is reset together with the test logic (only hypothetical, I haven't
385 seen hardware with such a bug, and can be worked around).
386 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
387 The default behaviour if no option given is @option{separate}.
389 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
390 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
391 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
392 (default) and @option{srst_push_pull} for the system reset. These values only affect
393 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
395 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
397 Describes the devices that form the JTAG daisy chain, with the first device being
398 the one closest to TDO. The parameters are the length of the instruction register
399 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
400 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
401 The IDCODE instruction will in future be used to query devices for their JTAG
402 identification code. This line is the same for all ARM7 and ARM9 devices.
403 Other devices, like CPLDs, require different parameters. An example configuration
404 line for a Xilinx XC9500 CPLD would look like this:
406 jtag_device 8 0x01 0x0e3 0xfe
408 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
409 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
410 The IDCODE instruction is 0xfe.
412 @item @b{jtag_nsrst_delay} <@var{ms}>
413 @cindex jtag_nsrst_delay
414 How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
415 starting new JTAG operations.
416 @item @b{jtag_ntrst_delay} <@var{ms}>
417 @cindex jtag_ntrst_delay
418 Same @b{jtag_nsrst_delay}, but for nTRST
420 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
421 or on-chip features) keep a reset line asserted for some time after the external reset
425 @section parport options
428 @item @b{parport_port} <@var{number}>
430 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
431 the @file{/dev/parport} device
433 When using PPDEV to access the parallel port, use the number of the parallel port:
434 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
435 you may encounter a problem.
436 @item @b{parport_cable} <@var{name}>
437 @cindex parport_cable
438 The layout of the parallel port cable used to connect to the target.
439 Currently supported cables are
443 The original Wiggler layout, also supported by several clones, such
444 as the Olimex ARM-JTAG
447 Same as original wiggler except an led is fitted on D5.
448 @item @b{wiggler_ntrst_inverted}
449 @cindex wiggler_ntrst_inverted
450 Same as original wiggler except TRST is inverted.
451 @item @b{old_amt_wiggler}
452 @cindex old_amt_wiggler
453 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
454 version available from the website uses the original Wiggler layout ('@var{wiggler}')
457 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
458 program the Chameleon itself, not a connected target.
461 The Xilinx Parallel cable III.
464 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
465 This is also the layout used by the HollyGates design
466 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
469 The ST Parallel cable.
472 Same as original wiggler except SRST and TRST connections reversed and
473 TRST is also inverted.
476 Altium Universal JTAG cable.
478 @item @b{parport_write_on_exit} <@var{on|off}>
479 @cindex parport_write_on_exit
480 This will configure the parallel driver to write a known value to the parallel
481 interface on exiting OpenOCD
484 @section amt_jtagaccel options
486 @item @b{parport_port} <@var{number}>
488 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
489 @file{/dev/parport} device
491 @section ft2232 options
494 @item @b{ft2232_device_desc} <@var{description}>
495 @cindex ft2232_device_desc
496 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
497 default value is used. This setting is only valid if compiled with FTD2XX support.
498 @item @b{ft2232_layout} <@var{name}>
499 @cindex ft2232_layout
500 The layout of the FT2232 GPIO signals used to control output-enables and reset
501 signals. Valid layouts are
504 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
506 Amontec JTAGkey and JTAGkey-tiny
509 @item @b{olimex-jtag}
512 American Microsystems M5960
513 @item @b{evb_lm3s811}
514 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
515 SRST signals on external connector
519 Hitex STM32 Performance Stick
521 Tin Can Tools Flyswatter
522 @item @b{turtelizer2}
523 egnite Software turtelizer2
528 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
529 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
530 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
532 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
534 @item @b{ft2232_latency} <@var{ms}>
535 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
536 ft2232_read() fails to return the expected number of bytes. This can be caused by
537 USB communication delays and has proved hard to reproduce and debug. Setting the
538 FT2232 latency timer to a larger value increases delays for short USB packages but it
539 also reduces the risk of timeouts before receiving the expected number of bytes.
540 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
543 @section ep93xx options
544 @cindex ep93xx options
545 Currently, there are no options available for the ep93xx interface.
548 @section Target configuration
551 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
554 Defines a target that should be debugged. Currently supported types are:
568 If you want to use a target board that is not on this list, see Adding a new
571 Endianess may be @option{little} or @option{big}.
573 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
574 @cindex target_script
575 Event is one of the following:
576 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
577 @option{pre_resume} or @option{gdb_program_config}.
578 @option{post_reset} and @option{reset} will produce the same results.
580 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
581 <@var{backup}|@var{nobackup}>
583 Specifies a working area for the debugger to use. This may be used to speed-up
584 downloads to target memory and flash operations, or to perform otherwise unavailable
585 operations (some coprocessor operations on ARM7/9 systems, for example). The last
586 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
587 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
590 @subsection arm7tdmi options
591 @cindex arm7tdmi options
592 target arm7tdmi <@var{endianess}> <@var{jtag#}>
593 The arm7tdmi target definition requires at least one additional argument, specifying
594 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
595 The optional [@var{variant}] parameter has been removed in recent versions.
596 The correct feature set is determined at runtime.
598 @subsection arm720t options
599 @cindex arm720t options
600 ARM720t options are similar to ARM7TDMI options.
602 @subsection arm9tdmi options
603 @cindex arm9tdmi options
604 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
605 @option{arm920t}, @option{arm922t} and @option{arm940t}.
606 This enables the hardware single-stepping support found on these cores.
608 @subsection arm920t options
609 @cindex arm920t options
610 ARM920t options are similar to ARM9TDMI options.
612 @subsection arm966e options
613 @cindex arm966e options
614 ARM966e options are similar to ARM9TDMI options.
616 @subsection cortex_m3 options
617 @cindex cortex_m3 options
618 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
619 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
620 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
621 be detected and the normal reset behaviour used.
623 @subsection xscale options
624 @cindex xscale options
625 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
626 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
628 @section Flash configuration
629 @cindex Flash configuration
632 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
633 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
635 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
636 and <@var{bus_width}> bytes using the selected flash <driver>.
639 @subsection lpc2000 options
640 @cindex lpc2000 options
642 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
643 <@var{clock}> [@var{calc_checksum}]
644 LPC flashes don't require the chip and bus width to be specified. Additional
645 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
646 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
647 of the target this flash belongs to (first is 0), the frequency at which the core
648 is currently running (in kHz - must be an integral number), and the optional keyword
649 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
652 @subsection cfi options
655 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
656 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
657 CFI flashes require the number of the target they're connected to as an additional
658 argument. The CFI driver makes use of a working area (specified for the target)
659 to significantly speed up operation.
661 @var{chip_width} and @var{bus_width} are specified in bytes.
663 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
667 @subsection at91sam7 options
668 @cindex at91sam7 options
670 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
671 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
672 reading the chip-id and type.
674 @subsection str7 options
677 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
678 variant can be either STR71x, STR73x or STR75x.
680 @subsection str9 options
683 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
684 The str9 needs the flash controller to be configured prior to Flash programming, eg.
686 str9x flash_config 0 4 2 0 0x80000
688 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
690 @subsection str9 options (str9xpec driver)
692 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
693 Before using the flash commands the turbo mode will need enabling using str9xpec
694 @option{enable_turbo} <@var{num>.}
696 Only use this driver for locking/unlocking the device or configuring the option bytes.
697 Use the standard str9 driver for programming.
699 @subsection stellaris (LM3Sxxx) options
700 @cindex stellaris (LM3Sxxx) options
702 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
703 stellaris flash plugin only require the @var{target#}.
705 @subsection stm32x options
706 @cindex stm32x options
708 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
709 stm32x flash plugin only require the @var{target#}.
711 @subsection aduc702x options
712 @cindex aduc702x options
714 @b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
715 aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
718 @chapter Target library
719 @cindex Target library
721 OpenOCD comes with a target configuration script library. These scripts can be
722 used as-is or serve as a starting point.
724 The target library is published together with the openocd executable and
725 the path to the target library is in the OpenOCD script search path.
726 Similarly there are example scripts for configuring the JTAG interface.
728 The command line below uses the example parport configuration scripts
729 that ship with OpenOCD, then configures the str710.cfg target and
730 finally issues the init and reset command. The communication speed
731 is set to 10kHz for reset and 8MHz for post reset.
735 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
739 To list the target scripts available:
742 $ ls /usr/local/lib/openocd/target
744 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
745 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
746 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
747 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
755 OpenOCD allows user interaction through a GDB server (default: port 3333),
756 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
757 is available from both the telnet interface and a GDB session. To issue commands to the
758 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
759 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
762 The TCL interface is used as a simplified RPC mechanism that feeds all the
763 input into the TCL interpreter and returns the output from the evaluation of
769 @item @b{sleep} <@var{msec}>
771 Wait for n milliseconds before resuming. Useful in connection with script files
772 (@var{script} command and @var{target_script} configuration).
776 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
778 @item @b{debug_level} [@var{n}]
780 Display or adjust debug level to n<0-3>
782 @item @b{fast} [@var{enable/disable}]
784 Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
785 downloads and fast memory access will work if the JTAG interface isn't too fast and
786 the core doesn't run at a too low frequency. Note that this option only changes the default
787 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
790 The target specific "dangerous" optimisation tweaking options may come and go
791 as more robust and user friendly ways are found to ensure maximum throughput
792 and robustness with a minimum of configuration.
794 Typically the "fast enable" is specified first on the command line:
797 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
800 @item @b{log_output} <@var{file}>
802 Redirect logging to <file> (default: stderr)
804 @item @b{script} <@var{file}>
806 Execute commands from <file>
810 @subsection Target state handling
812 @item @b{poll} [@option{on}|@option{off}]
814 Poll the target for its current state. If the target is in debug mode, architecture
815 specific information about the current state is printed. An optional parameter
816 allows continuous polling to be enabled and disabled.
818 @item @b{halt} [@option{ms}]
820 Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
821 Default [@option{ms}] is 5 seconds if no arg given.
822 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
823 will stop OpenOCD from waiting.
825 @item @b{wait_halt} [@option{ms}]
827 Wait for the target to enter debug mode. Optional [@option{ms}] is
828 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
831 @item @b{resume} [@var{address}]
833 Resume the target at its current code position, or at an optional address.
834 OpenOCD will wait 5 seconds for the target to resume.
836 @item @b{step} [@var{address}]
838 Single-step the target at its current code position, or at an optional address.
840 @item @b{reset} [@option{run}|@option{halt}|@option{init}]
842 Perform a hard-reset. The optional parameter specifies what should happen after the reset.
844 With no arguments a "reset run" is executed
851 Immediately halt the target (works only with certain configurations).
854 Immediately halt the target, and execute the reset script (works only with certain
859 @subsection Memory access commands
860 These commands allow accesses of a specific size to the memory system:
862 @item @b{mdw} <@var{addr}> [@var{count}]
865 @item @b{mdh} <@var{addr}> [@var{count}]
867 display memory half-words
868 @item @b{mdb} <@var{addr}> [@var{count}]
871 @item @b{mww} <@var{addr}> <@var{value}>
874 @item @b{mwh} <@var{addr}> <@var{value}>
876 write memory half-word
877 @item @b{mwb} <@var{addr}> <@var{value}>
881 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
883 Load image <@var{file}> to target memory at <@var{address}>
884 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
886 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
887 (binary) <@var{file}>.
888 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
890 Verify <@var{file}> against target memory starting at <@var{address}>.
891 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
894 @subsection Flash commands
895 @cindex Flash commands
897 @item @b{flash banks}
899 List configured flash banks
900 @item @b{flash info} <@var{num}>
902 Print info about flash bank <@option{num}>
903 @item @b{flash probe} <@var{num}>
905 Identify the flash, or validate the parameters of the configured flash. Operation
906 depends on the flash type.
907 @item @b{flash erase_check} <@var{num}>
908 @cindex flash erase_check
909 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
910 updates the erase state information displayed by @option{flash info}. That means you have
911 to issue an @option{erase_check} command after erasing or programming the device to get
913 @item @b{flash protect_check} <@var{num}>
914 @cindex flash protect_check
915 Check protection state of sectors in flash bank <num>.
916 @option{flash erase_sector} using the same syntax.
917 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
918 @cindex flash erase_sector
919 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
920 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
921 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
923 @item @b{flash erase_address} <@var{address}> <@var{length}>
924 @cindex flash erase_address
925 Erase sectors starting at <@var{address}> for <@var{length}> bytes
926 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
927 @cindex flash write_bank
928 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
929 <@option{offset}> bytes from the beginning of the bank.
930 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
931 @cindex flash write_image
932 Write the image <@var{file}> to the current target's flash bank(s). A relocation
933 [@var{offset}] can be specified and the file [@var{type}] can be specified
934 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
935 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
936 if the @option{erase} parameter is given.
937 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
938 @cindex flash protect
939 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
940 <@var{last}> of @option{flash bank} <@var{num}>.
944 @section Target Specific Commands
945 @cindex Target Specific Commands
947 @subsection AT91SAM7 specific commands
948 @cindex AT91SAM7 specific commands
949 The flash configuration is deduced from the chip identification register. The flash
950 controller handles erases automatically on a page (128/265 byte) basis so erase is
951 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
952 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
953 that can be erased separatly. Only an EraseAll command is supported by the controller
954 for each flash plane and this is called with
956 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
957 bulk erase flash planes first_plane to last_plane.
958 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
959 @cindex at91sam7 gpnvm
960 set or clear a gpnvm bit for the processor
963 @subsection STR9 specific commands
964 @cindex STR9 specific commands
965 These are flash specific commands when using the str9xpec driver.
967 @item @b{str9xpec enable_turbo} <@var{num}>
968 @cindex str9xpec enable_turbo
969 enable turbo mode, simply this will remove the str9 from the chain and talk
970 directly to the embedded flash controller.
971 @item @b{str9xpec disable_turbo} <@var{num}>
972 @cindex str9xpec disable_turbo
973 restore the str9 into jtag chain.
974 @item @b{str9xpec lock} <@var{num}>
975 @cindex str9xpec lock
976 lock str9 device. The str9 will only respond to an unlock command that will
978 @item @b{str9xpec unlock} <@var{num}>
979 @cindex str9xpec unlock
981 @item @b{str9xpec options_read} <@var{num}>
982 @cindex str9xpec options_read
983 read str9 option bytes.
984 @item @b{str9xpec options_write} <@var{num}>
985 @cindex str9xpec options_write
986 write str9 option bytes.
989 @subsection STR9 configuration
990 @cindex STR9 configuration
992 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
993 <@var{BBADR}> <@var{NBBADR}>
994 @cindex str9x flash_config
995 Configure str9 flash controller.
997 eg. str9x flash_config 0 4 2 0 0x80000
999 BBSR - Boot Bank Size register
1000 NBBSR - Non Boot Bank Size register
1001 BBADR - Boot Bank Start Address register
1002 NBBADR - Boot Bank Start Address register
1006 @subsection STR9 option byte configuration
1007 @cindex STR9 option byte configuration
1009 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
1010 @cindex str9xpec options_cmap
1011 configure str9 boot bank.
1012 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
1013 @cindex str9xpec options_lvdthd
1014 configure str9 lvd threshold.
1015 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
1016 @cindex str9xpec options_lvdsel
1017 configure str9 lvd source.
1018 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
1019 @cindex str9xpec options_lvdwarn
1020 configure str9 lvd reset warning source.
1023 @subsection STM32x specific commands
1024 @cindex STM32x specific commands
1026 These are flash specific commands when using the stm32x driver.
1028 @item @b{stm32x lock} <@var{num}>
1031 @item @b{stm32x unlock} <@var{num}>
1032 @cindex stm32x unlock
1033 unlock stm32 device.
1034 @item @b{stm32x options_read} <@var{num}>
1035 @cindex stm32x options_read
1036 read stm32 option bytes.
1037 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1038 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1039 @cindex stm32x options_write
1040 write stm32 option bytes.
1041 @item @b{stm32x mass_erase} <@var{num}>
1042 @cindex stm32x mass_erase
1043 mass erase flash memory.
1046 @subsection Stellaris specific commands
1047 @cindex Stellaris specific commands
1049 These are flash specific commands when using the Stellaris driver.
1051 @item @b{stellaris mass_erase} <@var{num}>
1052 @cindex stellaris mass_erase
1053 mass erase flash memory.
1057 @section Architecture Specific Commands
1058 @cindex Architecture Specific Commands
1060 @subsection ARMV4/5 specific commands
1061 @cindex ARMV4/5 specific commands
1063 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1064 or Intel XScale (XScale isn't supported yet).
1066 @item @b{armv4_5 reg}
1068 Display a list of all banked core registers, fetching the current value from every
1069 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1071 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1072 @cindex armv4_5 core_mode
1073 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1074 The target is resumed in the currently set @option{core_mode}.
1077 @subsection ARM7/9 specific commands
1078 @cindex ARM7/9 specific commands
1080 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1081 ARM920t or ARM926EJ-S.
1083 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1084 @cindex arm7_9 dbgrq
1085 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1086 safe for all but ARM7TDMI--S cores (like Philips LPC).
1087 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1088 @cindex arm7_9 fast_memory_access
1089 Allow OpenOCD to read and write memory without checking completion of
1090 the operation. This provides a huge speed increase, especially with USB JTAG
1091 cables (FT2232), but might be unsafe if used with targets running at a very low
1092 speed, like the 32kHz startup clock of an AT91RM9200.
1093 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1094 @cindex arm7_9 dcc_downloads
1095 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1096 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1097 unsafe, especially with targets running at a very low speed. This command was introduced
1098 with OpenOCD rev. 60.
1101 @subsection ARM720T specific commands
1102 @cindex ARM720T specific commands
1105 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1106 @cindex arm720t cp15
1107 display/modify cp15 register <@option{num}> [@option{value}].
1108 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1109 @cindex arm720t md<bhw>_phys
1110 Display memory at physical address addr.
1111 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1112 @cindex arm720t mw<bhw>_phys
1113 Write memory at physical address addr.
1114 @item @b{arm720t virt2phys} <@var{va}>
1115 @cindex arm720t virt2phys
1116 Translate a virtual address to a physical address.
1119 @subsection ARM9TDMI specific commands
1120 @cindex ARM9TDMI specific commands
1123 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1124 @cindex arm9tdmi vector_catch
1125 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1126 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1127 @option{irq} @option{fiq}.
1129 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1132 @subsection ARM966E specific commands
1133 @cindex ARM966E specific commands
1136 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1137 @cindex arm966e cp15
1138 display/modify cp15 register <@option{num}> [@option{value}].
1141 @subsection ARM920T specific commands
1142 @cindex ARM920T specific commands
1145 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1146 @cindex arm920t cp15
1147 display/modify cp15 register <@option{num}> [@option{value}].
1148 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1149 @cindex arm920t cp15i
1150 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1151 @item @b{arm920t cache_info}
1152 @cindex arm920t cache_info
1153 Print information about the caches found. This allows you to see if your target
1154 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1155 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1156 @cindex arm920t md<bhw>_phys
1157 Display memory at physical address addr.
1158 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1159 @cindex arm920t mw<bhw>_phys
1160 Write memory at physical address addr.
1161 @item @b{arm920t read_cache} <@var{filename}>
1162 @cindex arm920t read_cache
1163 Dump the content of ICache and DCache to a file.
1164 @item @b{arm920t read_mmu} <@var{filename}>
1165 @cindex arm920t read_mmu
1166 Dump the content of the ITLB and DTLB to a file.
1167 @item @b{arm920t virt2phys} <@var{va}>
1168 @cindex arm920t virt2phys
1169 Translate a virtual address to a physical address.
1172 @subsection ARM926EJS specific commands
1173 @cindex ARM926EJS specific commands
1176 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1177 @cindex arm926ejs cp15
1178 display/modify cp15 register <@option{num}> [@option{value}].
1179 @item @b{arm926ejs cache_info}
1180 @cindex arm926ejs cache_info
1181 Print information about the caches found.
1182 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1183 @cindex arm926ejs md<bhw>_phys
1184 Display memory at physical address addr.
1185 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1186 @cindex arm926ejs mw<bhw>_phys
1187 Write memory at physical address addr.
1188 @item @b{arm926ejs virt2phys} <@var{va}>
1189 @cindex arm926ejs virt2phys
1190 Translate a virtual address to a physical address.
1194 @section Debug commands
1195 @cindex Debug commands
1196 The following commands give direct access to the core, and are most likely
1197 only useful while debugging OpenOCD.
1199 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1200 @cindex arm7_9 write_xpsr
1201 Immediately write either the current program status register (CPSR) or the saved
1202 program status register (SPSR), without changing the register cache (as displayed
1203 by the @option{reg} and @option{armv4_5 reg} commands).
1204 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1205 <@var{0=cpsr},@var{1=spsr}>
1206 @cindex arm7_9 write_xpsr_im8
1207 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1208 operation (similar to @option{write_xpsr}).
1209 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1210 @cindex arm7_9 write_core_reg
1211 Write a core register, without changing the register cache (as displayed by the
1212 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1213 encoding of the [M4:M0] bits of the PSR.
1217 @section JTAG commands
1218 @cindex JTAG commands
1220 @item @b{scan_chain}
1222 Print current scan chain configuration.
1223 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1226 @item @b{endstate} <@var{tap_state}>
1228 Finish JTAG operations in <@var{tap_state}>.
1229 @item @b{runtest} <@var{num_cycles}>
1231 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1232 @item @b{statemove} [@var{tap_state}]
1234 Move to current endstate or [@var{tap_state}]
1235 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1237 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1238 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1240 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1241 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1242 @cindex verify_ircapture
1243 Verify value captured during Capture-IR. Default is enabled.
1244 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1246 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1247 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1249 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1253 @section Target Requests
1254 @cindex Target Requests
1255 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1256 See libdcc in the contrib dir for more details.
1258 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1259 @cindex target_request debugmsgs
1260 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1263 @node Sample Scripts
1264 @chapter Sample Scripts
1267 This page shows how to use the target library.
1269 The configuration script can be divided in the following section:
1271 @item daemon configuration
1273 @item jtag scan chain
1274 @item target configuration
1275 @item flash configuration
1278 Detailed information about each section can be found at OpenOCD configuration.
1280 @section AT91R40008 example
1281 @cindex AT91R40008 example
1282 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1283 the CPU upon startup of the OpenOCD daemon.
1285 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1289 @node GDB and OpenOCD
1290 @chapter GDB and OpenOCD
1291 @cindex GDB and OpenOCD
1292 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1293 to debug remote targets.
1295 @section Connecting to gdb
1296 @cindex Connecting to gdb
1297 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance 6.3 has a
1298 known bug where it produces bogus memory access errors, which has since
1299 been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb
1302 A connection is typically started as follows:
1304 target remote localhost:3333
1306 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1308 To see a list of available OpenOCD commands type @option{monitor help} on the
1311 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1312 to be sent by the gdb server (openocd) to gdb. Typical information includes
1313 packet size and device memory map.
1315 Previous versions of OpenOCD required the following gdb options to increase
1316 the packet size and speed up gdb communication.
1318 set remote memory-write-packet-size 1024
1319 set remote memory-write-packet-size fixed
1320 set remote memory-read-packet-size 1024
1321 set remote memory-read-packet-size fixed
1323 This is now handled in the @option{qSupported} PacketSize.
1325 @section Programming using gdb
1326 @cindex Programming using gdb
1328 By default the target memory map is sent to gdb, this can be disabled by
1329 the following OpenOCD config option:
1331 gdb_memory_map disable
1333 For this to function correctly a valid flash config must also be configured
1334 in OpenOCD. For faster performance you should also configure a valid
1337 Informing gdb of the memory map of the target will enable gdb to protect any
1338 flash area of the target and use hardware breakpoints by default. This means
1339 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
1342 To view the configured memory map in gdb, use the gdb command @option{info mem}
1343 All other unasigned addresses within gdb are treated as RAM.
1345 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1346 this can be changed to the old behaviour by using the following gdb command.
1348 set mem inaccessible-by-default off
1351 If @option{gdb_flash_program enable} is also used, gdb will be able to
1352 program any flash memory using the vFlash interface.
1354 gdb will look at the target memory map when a load command is given, if any
1355 areas to be programmed lie within the target flash area the vFlash packets
1358 If the target needs configuring before gdb programming, a script can be executed.
1360 target_script 0 gdb_program_config config.script
1363 To verify any flash programming the gdb command @option{compare-sections}
1366 @node TCL and OpenOCD
1367 @chapter TCL and OpenOCD
1368 @cindex TCL and OpenOCD
1369 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1372 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1374 The command and file interfaces are fairly straightforward, while the network
1375 port is geared toward intergration with external clients. A small example
1376 of an external TCL script that can connect to openocd is shown below.
1379 # Simple tcl client to connect to openocd
1380 puts "Use empty line to exit"
1381 set fo [socket 127.0.0.1 6666]
1382 puts -nonewline stdout "> "
1384 while {[gets stdin line] >= 0} {
1385 if {$line eq {}} break
1390 puts -nonewline stdout "> "
1396 This script can easily be modified to front various GUIs or be a sub
1397 component of a larger framework for control and interaction.
1400 @node TCL scripting API
1401 @chapter TCL scripting API
1402 @cindex TCL scripting API
1405 The commands are stateless. E.g. the telnet command line has a concept
1406 of currently active target, the Tcl API proc's take this sort of state
1407 information as an argument to each proc.
1409 There are three main types of return values: single value, name value
1410 pair list and lists.
1412 Name value pair. The proc 'foo' below returns a name/value pair
1418 > set foo(you) Oyvind
1419 > set foo(mouse) Micky
1420 > set foo(duck) Donald
1428 me Duane you Oyvind mouse Micky duck Donald
1430 Thus, to get the names of the associative array is easy:
1432 foreach { name value } [set foo] {
1433 puts "Name: $name, Value: $value"
1437 Lists returned must be relatively small. Otherwise a range
1438 should be passed in to the proc in question.
1440 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
1441 is the low level API upon which "flash banks" is implemented.
1443 OpenOCD commands can consist of two words, e.g. "flash banks". The
1444 startup.tcl "unknown" proc will translate this into a tcl proc
1445 called "flash_banks".
1449 @chapter Deprecated/Removed Commands
1450 @cindex Deprecated/Removed Commands
1451 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1454 @item @b{load_binary}
1456 use @option{load_image} command with same args
1459 @option{target} no longer take the reset_init, reset_run, run_and_halt, run_and_init. The @option{reset} command
1460 always does a @option{reset run} when passed no arguments.
1461 @item @b{dump_binary}
1463 use @option{dump_image} command with same args
1464 @item @b{flash erase}
1466 use @option{flash erase_sector} command with same args
1467 @item @b{flash write}
1469 use @option{flash write_bank} command with same args
1470 @item @b{flash write_binary}
1471 @cindex flash write_binary
1472 use @option{flash write_bank} command with same args
1473 @item @b{arm7_9 fast_writes}
1474 @cindex arm7_9 fast_writes
1475 use @option{arm7_9 fast_memory_access} command with same args
1476 @item @b{flash auto_erase}
1477 @cindex flash auto_erase
1478 use @option{flash write_image} command passing @option{erase} as the first parameter.
1479 @item @b{daemon_startup}
1480 @cindex daemon_startup
1481 this config option has been removed, simply adding @option{init} and @option{reset halt} to
1482 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
1483 and @option{target cortex_m3 little reset_halt 0}.
1484 @item @b{arm7_9 sw_bkpts}
1485 @cindex arm7_9 sw_bkpts
1486 On by default. See also @option{gdb_breakpoint_override}.
1487 @item @b{arm7_9 force_hw_bkpts}
1488 @cindex arm7_9 force_hw_bkpts
1489 Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
1490 for flash if the gdb memory map has been set up(default when flash is declared in
1491 target configuration).
1492 @item @b{run_and_halt_time}
1493 @cindex run_and_halt_time
1494 This command has been removed for simpler reset behaviour, it can be simulated with the
1507 @item OpenOCD complains about a missing cygwin1.dll.
1509 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1510 claims to come with all the necessary dlls. When using Cygwin, try launching
1511 OpenOCD from the Cygwin shell.
1513 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1514 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1515 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1517 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1518 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1519 software breakpoints consume one of the two available hardware breakpoints.
1521 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1522 and works sometimes fine.
1524 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1525 clock at the time you're programming the flash. If you've specified the crystal's
1526 frequency, make sure the PLL is disabled, if you've specified the full core speed
1527 (e.g. 60MHz), make sure the PLL is enabled.
1529 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1530 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1531 out while waiting for end of scan, rtck was disabled".
1533 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1534 settings in your PC BIOS (ECP, EPP, and different versions of those).
1536 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1537 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1538 memory read caused data abort".
1540 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1541 beyond the last valid frame. It might be possible to prevent this by setting up
1542 a proper "initial" stack frame, if you happen to know what exactly has to
1543 be done, feel free to add this here.
1545 @item I get the following message in the OpenOCD console (or log file):
1546 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1548 This warning doesn't indicate any serious problem, as long as you don't want to
1549 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1550 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
1551 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1552 independently. With this setup, it's not possible to halt the core right out of
1553 reset, everything else should work fine.
1555 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1556 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1557 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1558 quit with an error message. Is there a stability issue with OpenOCD?
1560 No, this is not a stability issue concerning OpenOCD. Most users have solved
1561 this issue by simply using a self-powered USB hub, which they connect their
1562 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1563 supply stable enough for the Amontec JTAGkey to be operated.
1565 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1566 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1567 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1568 What does that mean and what might be the reason for this?
1570 First of all, the reason might be the USB power supply. Try using a self-powered
1571 hub instead of a direct connection to your computer. Secondly, the error code 4
1572 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1573 chip ran into some sort of error - this points us to a USB problem.
1575 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1576 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1577 What does that mean and what might be the reason for this?
1579 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1580 has closed the connection to OpenOCD. This might be a GDB issue.
1582 @item In the configuration file in the section where flash device configurations
1583 are described, there is a parameter for specifying the clock frequency for
1584 LPC2000 internal flash devices (e.g.
1585 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1586 which must be specified in kilohertz. However, I do have a quartz crystal of a
1587 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1588 Is it possible to specify real numbers for the clock frequency?
1590 No. The clock frequency specified here must be given as an integral number.
1591 However, this clock frequency is used by the In-Application-Programming (IAP)
1592 routines of the LPC2000 family only, which seems to be very tolerant concerning
1593 the given clock frequency, so a slight difference between the specified clock
1594 frequency and the actual clock frequency will not cause any trouble.
1596 @item Do I have to keep a specific order for the commands in the configuration file?
1598 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1599 listed for the JTAG scan chain must be given in the right order (jtag_device),
1600 with the device closest to the TDO-Pin being listed first. In general,
1601 whenever objects of the same type exist which require an index number, then
1602 these objects must be given in the right order (jtag_devices, targets and flash
1603 banks - a target references a jtag_device and a flash bank references a target).
1605 @item Sometimes my debugging session terminates with an error. When I look into the
1606 log file, I can see these error messages: Error: arm7_9_common.c:561
1607 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP