1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
8 * OpenOCD: (openocd). Open On-Chip Debugger.
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
38 @vskip 0pt plus 1filll
45 @node Top, About, , (dir)
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
54 * About:: About OpenOCD.
55 * Developers:: OpenOCD developers
56 * Building:: Building OpenOCD
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * General Commands:: General Commands
69 * JTAG Commands:: JTAG Commands
70 * Sample Scripts:: Sample Target Scripts
72 * GDB and OpenOCD:: Using GDB and OpenOCD
73 * TCL scripting API:: Tcl scripting API
74 * Upgrading:: Deprecated/Removed Commands
75 * Target library:: Target library
76 * FAQ:: Frequently Asked Questions
77 * TCL Crash Course:: TCL Crash Course
78 * License:: GNU Free Documentation License
79 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
80 @comment case issue with ``Index.html'' and ``index.html''
81 @comment Occurs when creating ``--html --no-split'' output
82 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
83 * OpenOCD Index:: Main index.
90 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
91 in-system programming and boundary-scan testing for embedded target
94 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
95 with the JTAG (IEEE 1149.1) complient taps on your target board.
97 @b{Dongles:} OpenOCD currently many types of hardware dongles: USB
98 Based, Parallel Port Based, and other standalone boxes that run
99 OpenOCD internally. See the section titled: @xref{JTAG Hardware
102 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920t,
103 ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
104 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
105 debugged via the GDB Protocol.
107 @b{Flash Programing:} Flash writing is supported for external CFI
108 compatible flashes (Intel and AMD/Spansion command set) and several
109 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3 and
110 STM32x). Preliminary support for using the LPC3180's NAND flash
111 controller is included.
117 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
118 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
119 Others interested in improving the state of free and open debug and testing technology
120 are welcome to participate.
122 Other developers have contributed support for additional targets and flashes as well
123 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
125 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
129 @cindex building OpenOCD
131 If you are interested in getting actual work done rather than building
132 OpenOCD, then check if your interface supplier provides binaries for
133 you. Chances are that that binary is from some SVN version that is more
134 stable than SVN trunk where bleeding edge development takes place.
137 You can download the current SVN version with SVN client of your choice from the
138 following repositories:
140 (@uref{svn://svn.berlios.de/openocd/trunk})
144 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
146 Using the SVN command line client, you can use the following command to fetch the
147 latest version (make sure there is no (non-svn) directory called "openocd" in the
151 svn checkout svn://svn.berlios.de/openocd/trunk openocd
154 Building OpenOCD requires a recent version of the GNU autotools.
155 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
156 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
157 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
158 paths, resulting in obscure dependency errors (This is an observation I've gathered
159 from the logs of one user - correct me if I'm wrong).
161 You further need the appropriate driver files, if you want to build support for
162 a FTDI FT2232 based interface:
164 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
165 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
166 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
167 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
170 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
171 see contrib/libftdi for more details.
173 In general, the D2XX driver provides superior performance (several times as fast),
174 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
175 a kernel module, only a user space library.
177 To build OpenOCD (on both Linux and Cygwin), use the following commands:
181 Bootstrap generates the configure script, and prepares building on your system.
185 Configure generates the Makefiles used to build OpenOCD.
189 Make builds OpenOCD, and places the final executable in ./src/.
191 The configure script takes several options, specifying which JTAG interfaces
196 @option{--enable-parport}
198 @option{--enable-parport_ppdev}
200 @option{--enable-parport_giveio}
202 @option{--enable-amtjtagaccel}
204 @option{--enable-ft2232_ftd2xx}
205 @footnote{Using the latest D2XX drivers from FTDI and following their installation
206 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
209 @option{--enable-ft2232_libftdi}
211 @option{--with-ftd2xx=/path/to/d2xx/}
213 @option{--enable-gw16012}
215 @option{--enable-usbprog}
217 @option{--enable-presto_libftdi}
219 @option{--enable-presto_ftd2xx}
221 @option{--enable-jlink}
224 If you want to access the parallel port using the PPDEV interface you have to specify
225 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
226 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
227 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
229 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
230 absolute path containing no spaces.
232 Linux users should copy the various parts of the D2XX package to the appropriate
233 locations, i.e. /usr/include, /usr/lib.
235 Miscellaneous configure options
239 @option{--enable-gccwarnings} - enable extra gcc warnings during build
242 @node JTAG Hardware Dongles
243 @chapter JTAG Hardware Dongles
252 Defined: @b{dongle}: A small device that plugins into a computer and serves as
253 an adapter .... [snip]
255 In the OpenOCD case, this generally refers to @b{a small adapater} one
256 attaches to your computer via USB or the Parallel Printer Port. The
257 execption being the Zylin ZY1000 which is a small box you attach via
261 @section Choosing a Dongle
263 There are three things you should keep in mind when choosing a dongle.
266 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
267 @item @b{Connection} Printer Ports - Does your computer have one?
268 @item @b{Connection} Is that long printer bit-bang cable practical?
269 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
272 @section Stand alone Systems
274 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
275 dongle, but a standalone box.
277 @section USB FT2232 Based
279 There are many USB jtag dongles on the market, many of them are based
280 on a chip from ``Future Technology Devices International'' (FTDI)
281 known as the FTDI FT2232.
283 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
285 As of 28/Nov/2008, the following are supported:
289 @* Link Unknown [not easily verified]
291 @* See: @url{http://www.amontec.com/jtagkey.shtml}
293 @* Link Unknown [not easily verified]
295 @* See: @url{http://www.signalyzer.com}
296 @item @b{evb_lm3s811}
297 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
298 @item @b{olimex-jtag}
299 @* See: @url{http://www.olimex.com}
301 @* See: @url{http://www.tincantools.com}
302 @item @b{turtelizer2}
303 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
305 @* Link: @url{http://www.hitex.com/index.php?id=383}
307 @* Link Unknown [not easily verified]
310 @section USB JLINK based
311 There are several OEM versions of the Segger @b{JLINK} adapter. It is
312 an example of a micro controller based JTAG adapter, it uses an
313 AT91SAM764 internally.
316 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
317 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
318 @item @b{SEGGER JLINK}
319 @* Link: @url{http://www.segger.com/jlink.html}
321 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
322 @item @b{TODO [28/nov/2008]: Confirm if the IAR version works.}
328 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
330 @item @b{USB - Presto}
331 @* Link: @url{http://tools.asix.net/prg_presto.htm}
334 @section IBM PC Parallel Printer Port Based
336 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
337 and the MacGraigor Wiggler. There are many clones and variations of
342 @item @b{Wiggler} - There are many clones of this.
343 @* Link: @url{http://www.macraigor.com/wiggler.htm}
345 @item @b{DLC5} - From XILINX - There are many clones of this
346 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
347 produced, PDF schematics are easily found and it is easy to make.
349 @item @b{Amontec - JTAG Accelerator}
350 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
353 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
356 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
358 @item @b{Wiggler_ntrst_inverted}
359 @* Yet another variation - See the source code, src/jtag/parport.c
361 @item @b{old_amt_wiggler}
362 @* Unknown - probably not on the market today
365 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
368 @* Link: @url{http://www.amontec.com/chameleon.shtml}
374 @* From Lattice Semiconductor [link unknown]
377 @* From ST Microsystems, link:
378 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
379 Title: FlashLINK JTAG programing cable for PSD and uPSD
387 @* An EP93xx based linux machine using the GPIO pins directly.
390 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
396 @cindex running OpenOCD
398 @cindex --debug_level
402 The @option{--help} option shows:
406 --help | -h display this help
407 --version | -v display OpenOCD version
408 --file | -f use configuration file <name>
409 --search | -s dir to search for config files and scripts
410 --debug | -d set debug level <0-3>
411 --log_output | -l redirect log output to file <name>
412 --command | -c run <command>
415 By default openocd reads the file configuration file ``openocd.cfg''
416 in the current directory. To specify a different (or multiple)
417 configuration file, you can use the ``-f'' option. For example:
420 openocd -f config1.cfg -f config2.cfg -f config3.cfg
423 Once started, OpenOCD runs as a daemon, waiting for connections from
424 clients (Telnet, GDB, Other).
426 If you are having problems, you can enable internal debug messages via
429 Also it is possible to interleave commands w/config scripts using the
430 @option{-c} command line switch.
432 To enable debug output (when reporting problems or working on OpenOCD
433 itself), use the @option{-d} command line switch. This sets the
434 @option{debug_level} to "3", outputting the most information,
435 including debug messages. The default setting is "2", outputting only
436 informational messages, warnings and errors. You can also change this
437 setting from within a telnet or gdb session using @option{debug_level
438 <n>} @xref{debug_level}.
440 You can redirect all output from the daemon to a file using the
441 @option{-l <logfile>} switch.
443 Search paths for config/script files can be added to OpenOCD by using
444 the @option{-s <search>} switch. The current directory and the OpenOCD
445 target library is in the search path by default.
447 Note! OpenOCD will launch the GDB & telnet server even if it can not
448 establish a connection with the target. In general, it is possible for
449 the JTAG controller to be unresponsive until the target is set up
450 correctly via e.g. GDB monitor commands in a GDB init script.
452 @node Simple Configuration Files
453 @chapter Simple Configuration Files
454 @cindex configuration
457 There are 4 basic ways of ``configurating'' openocd to run, they are:
460 @item A small openocd.cfg file which ``sources'' other configuration files
461 @item A monolithic openocd.cfg file
462 @item Many -f filename options on the command line
463 @item Your Mixed Solution
466 @section Small configuration file method
468 This is the prefered method, it is simple and is works well for many
469 people. The developers of OpenOCD would encourage you to use this
470 method. If you create a new configuration please email new
471 configurations to the development list.
473 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
476 source [find interface/signalyzer.cfg]
478 # Change the default telnet port...
482 # GDB can also flash my flash!
483 gdb_memory_map enable
484 gdb_flash_program enable
486 source [find target/sam7x256.cfg]
489 There are many example configuration scripts you can work with. You
490 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
494 @item @b{board} - eval board level configurations
495 @item @b{interface} - specific dongle configurations
496 @item @b{target} - the target chips
497 @item @b{tcl} - helper scripts
498 @item @b{xscale} - things specific to the xscale.
501 Look first in the ``boards'' area, then the ``targets'' area. Often a board
502 configuration is a good example to work from.
504 @section Many -f filename options
505 Some believe this is a wonderful solution, others find it painful.
507 You can use a series of ``-f filename'' options on the command line,
508 OpenOCD will read each filename in sequence, for example:
511 openocd -f file1.cfg -f file2.cfg -f file2.cfg
514 You can also intermix various commands with the ``-c'' command line
517 @section Monolithic file
518 The ``Monolithic File'' dispenses with all ``source'' statements and
519 puts everything in one self contained (monolithic) file. This is not
522 Please try to ``source'' various files or use the multiple -f
525 @section Advice for you
526 Often, one uses a ``mixed approach''. Where possible, please try to
527 ``source'' common things, and if needed cut/paste parts of the
528 standard distribution configuration files as needed.
530 @b{REMEMBER:} The ``important parts'' of your configuration file are:
533 @item @b{Interface} - Defines the dongle
534 @item @b{Taps} - Defines the JTAG Taps
535 @item @b{GDB Targets} - What GDB talks to
536 @item @b{Flash Programing} - Very Helpful
539 Some key things you should look at and understand are:
542 @item The RESET configuration of your debug environment as a hole
543 @item Is there a ``work area'' that that OpenOCD can use?
544 @* For ARM - work areas mean up to 10x faster downloads.
545 @item For MMU/MPU based ARM chips (ie: ARM9 and later) will that work area still be available?
546 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
551 @node Config File Guidelines
552 @chapter Config File Guidelines
554 This section/chapter is aimed at developers and integrators of
555 OpenOCD. These are guidelines for creating new boards and new target
556 configurations as of 28/Nov/2008.
558 However, you the user of OpenOCD should be some what familiar with
559 this section as it should help explain some of the internals of what
560 you might be looking at.
562 The user should find under @t{$(INSTALLDIR)/lib/openocd} the
563 following directories:
567 @*Think JTAG Dongle. Files that configure the jtag dongle go here.
569 @* Thing Circuit Board, PWA, PCB, they go by many names. Board files
570 contain initialization items that are specific to a board - for
571 example: The SDRAM initialization sequence for the board, or the type
572 of external flash and what address it is found at. Any initialization
573 sequence to enable that external flash or sdram should be found in the
574 board file. Boards may also contain multiple targets, ie: Two cpus, or
575 a CPU and an FPGA or CPLD.
577 @* Think CHIP. The ``target'' directory represents a jtag tap (or
578 chip) OpenOCD should control, not a board. Two common types of targets
579 are ARM chips and FPGA or CPLD chips.
582 @b{If needed...} The user in their ``openocd.cfg'' file or the board
583 file might override a specific feature in any of the above files by
584 setting a variable or two before sourcing the target file. Or adding
585 various commands specific to their situation.
587 @section Interface Config Files
589 The user should be able to source one of these files via a command like this:
592 source [find interface/FOOBAR.cfg]
594 openocd -f interface/FOOBAR.cfg
597 A preconfigured interface file should exist for every interface in use
598 today, that said, perhaps some interfaces have only been used by the
599 sole developer who created it.
601 @b{FIXME/NOTE:} We need to add support for a variable like TCL variable
602 tcl_platform(platform), it should be called jim_platform (because it
603 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
604 ``cygwin'' or ``mingw''
606 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
608 @section Board Config Files
610 @b{Note: BOARD directory NEW as of 28/nov/2008}
612 The user should be able to source one of these files via a command like this:
615 source [find board/FOOBAR.cfg]
617 openocd -f board/FOOBAR.cfg
621 The board file should contain one or more @t{source [find
622 target/FOO.cfg]} statements along with any board specific things.
624 In summery the board files should contain (if present)
627 @item External flash configuration (ie: the flash on CS0)
628 @item SDRAM configuration (size, speed, etc)
629 @item Board specific IO configuration (ie: GPIO pins might disable a 2nd flash)
630 @item Multiple TARGET source statements
631 @item All things that are not ``inside a chip''
632 @item Things inside a chip go in a 'target' file
635 @section Target Config Files
637 The user should be able to source one of these files via a command like this:
640 source [find target/FOOBAR.cfg]
642 openocd -f target/FOOBAR.cfg
645 In summery the target files should contain
650 @item Reset Configuration
652 @item CPU/Chip/CPU-Core Specific features
656 @subsection Important variable names
658 By default, the end user should never need to set these
659 variables. However, if the user needs to override a setting they only
660 need to set the variable in a simple way.
664 @* This gives a name to the overall chip, and is used as part of the
665 tap identifier dotted name.
667 @* By default little - unless the chip or board is not normally used that way.
669 @* When OpenOCD examines the JTAG chain, it will attempt to identify
670 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
671 to verify the tap id number verses configuration file and may issue an
672 error or warning like this. The hope is this will help pin point
673 problem openocd configurations.
676 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
677 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
678 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
679 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
682 @item @b{_TARGETNAME}
683 @* By convention, this variable is created by the target configuration
684 script. The board configuration file may make use of this variable to
685 configure things like a ``reset init'' script, or other things
686 specific to that board and that target.
688 If the chip has 2 targets, use the names @b{_TARGETNAME0},
689 @b{_TARGETNAME1}, ... etc.
691 @b{Remember:} The ``board file'' may include multiple targets.
693 At no time should the name ``target0'' (the default target name if
694 none was specified) be used. The name ``target0'' is a hard coded name
695 - the next target on the board will be some other number.
697 The user (or board file) should reasonably be able to:
700 source [find target/FOO.cfg]
701 $_TARGETNAME configure ... FOO specific parameters
703 source [find target/BAR.cfg]
704 $_TARGETNAME configure ... BAR specific parameters
709 @subsection TCL Variables Guide Line
710 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
712 Thus the rule we follow in OpenOCD is this: Variables that begin with
713 a leading underscore are temporal in nature, and can be modified and
714 used at will within a ?TARGET? configuration file
716 @b{EXAMPLE:} The user should be able to do this:
720 # PXA270 #1 network side, big endian
721 # PXA270 #2 video side, little endian
725 source [find target/pxa270.cfg]
726 # variable: _TARGETNAME = network.cpu
727 # other commands can refer to the "network.cpu" tap.
728 $_TARGETNAME configure .... params for this cpu..
732 source [find target/pxa270.cfg]
733 # variable: _TARGETNAME = video.cpu
734 # other commands can refer to the "video.cpu" tap.
735 $_TARGETNAME configure .... params for this cpu..
739 source [find target/spartan3.cfg]
741 # Since $_TARGETNAME is temporal..
742 # these names still work!
743 network.cpu configure ... params
744 video.cpu configure ... params
748 @subsection Default Value Boiler Plate Code
750 All target configuration files should start with this (or a modified form)
754 if @{ [info exists CHIPNAME] @} @{
755 set _CHIPNAME $CHIPNAME
757 set _CHIPNAME sam7x256
760 if @{ [info exists ENDIAN] @} @{
766 if @{ [info exists CPUTAPID ] @} @{
767 set _CPUTAPID $CPUTAPID
769 set _CPUTAPID 0x3f0f0f0f
774 @subsection Creating Taps
775 After the ``defaults'' are choosen, [see above], the taps are created.
777 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
781 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
782 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
787 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
790 @item @b{Unform tap names} - See: Tap Naming Convention
791 @item @b{_TARGETNAME} is created at the end where used.
795 if @{ [info exists FLASHTAPID ] @} @{
796 set _FLASHTAPID $FLASHTAPID
798 set _FLASHTAPID 0x25966041
800 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
802 if @{ [info exists CPUTAPID ] @} @{
803 set _CPUTAPID $CPUTAPID
805 set _CPUTAPID 0x25966041
807 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
810 if @{ [info exists BSTAPID ] @} @{
811 set _BSTAPID $BSTAPID
813 set _BSTAPID 0x1457f041
815 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
817 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
820 @b{Tap Naming Convention}
822 See the command ``jtag newtap'' for detail, but in breif the names you should use are:
830 @item @b{unknownN} - it happens :-(
833 @subsection Reset Configuration
835 Some chips have specific ways the TRST and SRST signals are
836 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
837 @b{BOARD SPECIFIC} they go in the board file.
839 @subsection Work Areas
841 Work areas are small RAM areas used by OpenOCD to speed up downloads,
842 and to download small snippits of code to program flash chips.
844 If the chip includes an form of ``on-chip-ram'' - and many do - define
845 a reasonable work area and use the ``backup'' option.
847 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
848 inaccessable if/when the application code enables or disables the MMU.
850 @subsection ARM Core Specific Hacks
852 If the chip has a DCC, enable it. If the chip is an arm9 with some
853 special high speed download - enable it.
855 If the chip has an ARM ``vector catch'' feature - by defeault enable
856 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
857 user is really writing a handler for those situations - they can
858 easily disable it. Experiance has shown the ``vector catch'' is
859 helpful - for common programing errors.
861 If present, the MMU, the MPU and the CACHE should be disabled.
863 @subsection Internal Flash Configuration
865 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
867 @b{Never ever} in the ``target configuration file'' define any type of
868 flash that is external to the chip. (For example the BOOT flash on
869 Chip Select 0). The BOOT flash information goes in a board file - not
870 the TARGET (chip) file.
874 @item at91sam7x256 - has 256K flash YES enable it.
875 @item str912 - has flash internal YES enable it.
876 @item imx27 - uses boot flash on CS0 - it goes in the board file.
877 @item pxa270 - again - CS0 flash - it goes in the board file.
881 @chapter About JIM-Tcl
885 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
886 learn more about JIM here: @url{http://jim.berlios.de}
889 @item @b{JIM vrs TCL}
890 @* JIM-TCL is a stripped down version of the well known Tcl language,
891 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
892 fewer features. JIM-Tcl is a single .C file and a single .H file and
893 impliments the basic TCL command set along. In contrast: Tcl 8.6 is a
894 4.2MEG zip file containing 1540 files.
896 @item @b{Missing Features}
897 @* Our practice has been: Add/clone the Real TCL feature if/when
898 needed. We welcome JIM Tcl improvements, not bloat.
901 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
902 command interpretor today (28/nov/2008) is a mixture of (newer)
903 JIM-Tcl commands, and (older) the orginal command interpretor.
906 @* At the openocd telnet command line (or via the GDB mon command) one
907 can type a Tcl for() loop, set variables, etc.
909 @item @b{Historical Note}
910 @* JIM-Tcl was introduced to OpenOCD in Spring 2008.
912 @item @b{Need a Crash Course In TCL?}
913 @* See: @xref{TCL Crash Course}.
917 @node Daemon Configuration
918 @chapter Daemon Configuration
919 The commands here are commonly found inthe openocd.cfg file and are
920 used to specify what TCP/IP ports are used, and how GDB should be
924 This command terminates the configuration stage and
925 enters the normal command mode. This can be useful to add commands to
926 the startup scripts and commands such as resetting the target,
927 programming flash, etc. To reset the CPU upon startup, add "init" and
928 "reset" at the end of the config script or at the end of the OpenOCD
929 command line using the @option{-c} command line switch.
931 If this command does not appear in any startup/configuration file
932 OpenOCD executes the command for you after processing all
933 configuration files and/or command line options.
935 @b{NOTE:} This command normally occurs at or near the end of your
936 openocd.cfg file to force OpenOCD to ``initialize'' and make the
937 targets ready. For example: If your openocd.cfg file needs to
938 read/write memory on your target - the init command must occur before
939 the memory read/write commands.
941 @section TCP/IP Ports
943 @item @b{telnet_port} <@var{number}>
945 @*Intended for a human. Port on which to listen for incoming telnet connections.
947 @item @b{tcl_port} <@var{number}>
949 @*Intended as a machine interface. Port on which to listen for
950 incoming TCL syntax. This port is intended as a simplified RPC
951 connection that can be used by clients to issue commands and get the
952 output from the TCL engine.
954 @item @b{gdb_port} <@var{number}>
956 @*First port on which to listen for incoming GDB connections. The GDB port for the
957 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
962 @item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
963 @cindex gdb_breakpoint_override
964 @anchor{gdb_breakpoint_override}
965 @*Force breakpoint type for gdb 'break' commands.
966 The raison d'etre for this option is to support GDB GUI's without
967 a hard/soft breakpoint concept where the default OpenOCD and
968 GDB behaviour is not sufficient. Note that GDB will use hardware
969 breakpoints if the memory map has been set up for flash regions.
971 This option replaces older arm7_9 target commands that addressed
974 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
976 @*Configures what OpenOCD will do when gdb detaches from the daeman.
977 Default behaviour is <@var{resume}>
979 @item @b{gdb_memory_map} <@var{enable|disable}>
980 @cindex gdb_memory_map
981 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
982 requested. gdb will then know when to set hardware breakpoints, and program flash
983 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
984 for flash programming to work.
985 Default behaviour is <@var{enable}>
986 @xref{gdb_flash_program}.
988 @item @b{gdb_flash_program} <@var{enable|disable}>
989 @cindex gdb_flash_program
990 @anchor{gdb_flash_program}
991 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
992 vFlash packet is received.
993 Default behaviour is <@var{enable}>
994 @comment END GDB Items
997 @node Interface - Dongle Configuration
998 @chapter Interface - Dongle Configuration
999 Interface commands are normally found in an interface configuration
1000 file which is sourced by your openocd.cfg file. These commands tell
1001 OpenOCD what type of JTAG dongle you have and how to talk to it.
1002 @section Simple Complete Interface Examples
1003 @b{A Turtelizer FT2232 Based JTAG Dongle}
1007 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1008 ft2232_layout turtelizer2
1009 ft2232_vid_pid 0x0403 0xbdc8
1020 parport_cable wiggler
1023 @section Interface Conmmand
1025 The interface command tells OpenOCD what type of jtag dongle you are
1026 using. Depending upon the type of dongle, you may need to have one or
1027 more additional commands.
1031 @item @b{interface} <@var{name}>
1033 @*Use the interface driver <@var{name}> to connect to the
1034 target. Currently supported interfaces are
1039 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1041 @item @b{amt_jtagaccel}
1042 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1046 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1047 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1048 platform. The libftdi uses libusb, and should be portable to all systems that provide
1052 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1055 @* ASIX PRESTO USB JTAG programmer.
1058 @* usbprog is a freely programmable USB adapter.
1061 @* Gateworks GW16012 JTAG programmer.
1064 @* Segger jlink usb adapter
1065 @comment - End parameters
1067 @comment - End Interface
1069 @subsection parport options
1072 @item @b{parport_port} <@var{number}>
1073 @cindex parport_port
1074 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1075 the @file{/dev/parport} device
1077 When using PPDEV to access the parallel port, use the number of the parallel port:
1078 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1079 you may encounter a problem.
1080 @item @b{parport_cable} <@var{name}>
1081 @cindex parport_cable
1082 @*The layout of the parallel port cable used to connect to the target.
1083 Currently supported cables are
1087 The original Wiggler layout, also supported by several clones, such
1088 as the Olimex ARM-JTAG
1091 Same as original wiggler except an led is fitted on D5.
1092 @item @b{wiggler_ntrst_inverted}
1093 @cindex wiggler_ntrst_inverted
1094 Same as original wiggler except TRST is inverted.
1095 @item @b{old_amt_wiggler}
1096 @cindex old_amt_wiggler
1097 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1098 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1101 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1102 program the Chameleon itself, not a connected target.
1105 The Xilinx Parallel cable III.
1108 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1109 This is also the layout used by the HollyGates design
1110 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1113 The ST Parallel cable.
1116 Same as original wiggler except SRST and TRST connections reversed and
1117 TRST is also inverted.
1120 Altium Universal JTAG cable.
1122 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1123 @cindex parport_write_on_exit
1124 @*This will configure the parallel driver to write a known value to the parallel
1125 interface on exiting OpenOCD
1128 @subsection amt_jtagaccel options
1130 @item @b{parport_port} <@var{number}>
1131 @cindex parport_port
1132 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1133 @file{/dev/parport} device
1135 @subsection ft2232 options
1138 @item @b{ft2232_device_desc} <@var{description}>
1139 @cindex ft2232_device_desc
1140 @*The USB device description of the FTDI FT2232 device. If not
1141 specified, the FTDI default value is used. This setting is only valid
1142 if compiled with FTD2XX support.
1144 @b{TODO:} Confirm the following: On windows the name needs to end with
1145 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1146 this be added and when must it not be added? Why can't the code in the
1147 interface or in openocd automatically add this if needed? -- Duane.
1149 @item @b{ft2232_serial} <@var{serial-number}>
1150 @cindex ft2232_serial
1151 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1153 @item @b{ft2232_layout} <@var{name}>
1154 @cindex ft2232_layout
1155 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1156 signals. Valid layouts are
1159 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1161 Amontec JTAGkey and JTAGkey-tiny
1162 @item @b{signalyzer}
1164 @item @b{olimex-jtag}
1167 American Microsystems M5960
1168 @item @b{evb_lm3s811}
1169 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1170 SRST signals on external connector
1173 @item @b{stm32stick}
1174 Hitex STM32 Performance Stick
1175 @item @b{flyswatter}
1176 Tin Can Tools Flyswatter
1177 @item @b{turtelizer2}
1178 egnite Software turtelizer2
1183 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1184 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1185 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
1187 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1189 @item @b{ft2232_latency} <@var{ms}>
1190 @*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
1191 ft2232_read() fails to return the expected number of bytes. This can be caused by
1192 USB communication delays and has proved hard to reproduce and debug. Setting the
1193 FT2232 latency timer to a larger value increases delays for short USB packages but it
1194 also reduces the risk of timeouts before receiving the expected number of bytes.
1195 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1198 @subsection ep93xx options
1199 @cindex ep93xx options
1200 Currently, there are no options available for the ep93xx interface.
1204 @item @b{jtag_khz} <@var{reset speed kHz}>
1207 It is debatable if this command belongs here - or in a board
1208 configuration file. In fact, in some situations the jtag speed is
1209 changed during the target initialization process (ie: (1) slow at
1210 reset, (2) program the cpu clocks, (3) run fast)
1212 Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1214 Not all interfaces support ``rtck''. If the interface device can not
1215 support the rate asked for, or can not translate from kHz to
1216 jtag_speed, then an error is returned.
1218 Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
1219 especially true for synthesized cores (-S). Also see RTCK.
1221 @b{NOTE: Script writers} If the target chip requires/uses RTCK -
1222 please use the command: 'jtag_rclk FREQ'. This TCL proc (in
1223 startup.tcl) attempts to enable RTCK, if that fails it falls back to
1224 the specified frequency.
1227 # Fall back to 3mhz if RCLK is not supported
1231 @item @b{DEPRICATED} @b{jtag_speed} - please use jtag_khz above.
1233 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
1234 speed. The actual effect of this option depends on the JTAG interface used.
1236 The speed used during reset can be adjusted using setting jtag_speed during
1237 pre_reset and post_reset events.
1240 @item wiggler: maximum speed / @var{number}
1241 @item ft2232: 6MHz / (@var{number}+1)
1242 @item amt jtagaccel: 8 / 2**@var{number}
1243 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
1244 @comment end speed list.
1247 @comment END command list
1250 @node Reset Configuration
1251 @chapter Reset Configuration
1252 @cindex reset configuration
1254 Every system configuration may require a different reset
1255 configuration. This can also be quite confusing. Please see the
1256 various board files for example.
1258 @section jtag_nsrst_delay <@var{ms}>
1259 @cindex jtag_nsrst_delay
1260 @*How long (in milliseconds) OpenOCD should wait after deasserting
1261 nSRST before starting new JTAG operations.
1263 @section jtag_ntrst_delay <@var{ms}>
1264 @cindex jtag_ntrst_delay
1265 @*Same @b{jtag_nsrst_delay}, but for nTRST
1267 The jtag_n[st]rst_delay options are useful if reset circuitry (like a
1268 big resistor/capacitor, reset supervisor, or on-chip features). This
1269 keeps the signal asserted for some time after the external reset got
1272 @section reset_config
1274 @b{Note:} To maintainer types and integrators. Where exactly the
1275 ``reset configuration'' goes is a good question. It touches several
1276 things at once. In the end, if you have a board file - the board file
1277 should define it and assume 100% that the DONGLE supports
1278 anything. However, that does not mean the target should not also make
1279 not of something the silicon vendor has done inside the
1280 chip. @i{Grr.... nothing is every pretty.}
1284 @item Every JTAG Dongle is slightly different, some dongles impliment reset differently.
1285 @item Every board is also slightly different; some boards tie TRST and SRST together.
1286 @item Every chip is slightly different; some chips internally tie the two signals together.
1287 @item Some may not impliment all of the signals the same way.
1288 @item Some signals might be push-pull, others open-drain/collector.
1290 @b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
1291 reset the TAP via TRST and send commands through the JTAG tap to halt
1292 the CPU at the reset vector before the 1st instruction is executed,
1293 and finally release the SRST signal.
1294 @*Depending upon your board vendor, your chip vendor, etc, these
1295 signals may have slightly different names.
1297 OpenOCD defines these signals in these terms:
1299 @item @b{TRST} - is Tap Reset - and should reset only the TAP.
1300 @item @b{SRST} - is System Reset - typically equal to a reset push button.
1306 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
1307 @cindex reset_config
1308 @* The @t{reset_config} command tells OpenOCD the reset configuration
1309 of your combination of Dongle, Board, and Chips.
1310 If the JTAG interface provides SRST, but the target doesn't connect
1311 that signal properly, then OpenOCD can't use it. <@var{signals}> can
1312 be @option{none}, @option{trst_only}, @option{srst_only} or
1313 @option{trst_and_srst}.
1315 [@var{combination}] is an optional value specifying broken reset
1316 signal implementations. @option{srst_pulls_trst} states that the
1317 testlogic is reset together with the reset of the system (e.g. Philips
1318 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1319 the system is reset together with the test logic (only hypothetical, I
1320 haven't seen hardware with such a bug, and can be worked around).
1321 @option{combined} imples both @option{srst_pulls_trst} and
1322 @option{trst_pulls_srst}. The default behaviour if no option given is
1325 The [@var{trst_type}] and [@var{srst_type}] parameters allow the
1326 driver type of the reset lines to be specified. Possible values are
1327 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1328 test reset signal, and @option{srst_open_drain} (default) and
1329 @option{srst_push_pull} for the system reset. These values only affect
1330 JTAG interfaces with support for different drivers, like the Amontec
1331 JTAGkey and JTAGAccelerator.
1333 @comment - end command
1339 @chapter Tap Creation
1340 @cindex tap creation
1341 @cindex tap configuration
1343 In order for OpenOCD to control a target, a JTAG tap must be
1346 Commands to create taps are normally found in a configuration file and
1347 are not normally typed by a human.
1349 When a tap is created a @b{dotted.name} is created for the tap. Other
1350 commands use that dotted.name to manipulate or refer to the tap.
1354 @item @b{Debug Target} A tap can be used by a GDB debug target
1355 @item @b{Flash Programing} Some chips program the flash via JTAG
1356 @item @b{Boundry Scan} Some chips support boundry scan.
1360 @section jtag newtap
1361 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1366 @cindex tap geometry
1368 @comment START options
1371 @* is a symbolic name of the chip.
1373 @* is a symbol name of a tap present on the chip.
1374 @item @b{Required configparams}
1375 @* Every tap has 3 required configparams, and several ``optional
1376 parameters'', the required parameters are:
1377 @comment START REQUIRED
1379 @item @b{-irlen NUMBER} - the length in bits of the instruction register
1380 @item @b{-ircapture NUMBER} - the ID code capture command.
1381 @item @b{-irmask NUMBER} - the corrisponding mask for the ir register.
1382 @comment END REQUIRED
1384 An example of a FOOBAR Tap
1386 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1388 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1389 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1390 [6,4,2,0] are checked.
1392 FIXME: The IDCODE - this was not used in the old code, it should be?
1394 @item @b{Optional configparams}
1395 @comment START Optional
1397 @item @b{-expected-id NUMBER}
1398 @* By default it is zero. If non-zero represents the
1399 expected tap ID used when the Jtag Chain is examined. See below.
1402 @* By default not specified the tap is enabled. Some chips have a
1403 jtag route controller (JRC) that is used to enable and/or disable
1404 specific jtag taps. You can later enable or disable any JTAG tap via
1405 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1407 @comment END Optional
1410 @comment END OPTIONS
1413 @comment START NOTES
1415 @item @b{Technically}
1416 @* newtap is a sub command of the ``jtag'' command
1417 @item @b{Big Picture Background}
1418 @*GDB Talks to OpenOCD using the GDB protocol via
1419 tcpip. OpenOCD then uses the JTAG interface (the dongle) to
1420 control the JTAG chain on your board. Your board has one or more chips
1421 in a @i{daisy chain configuration}. Each chip may have one or more
1422 jtag taps. GDB ends up talking via OpenOCD to one of the taps.
1423 @item @b{NAME Rules}
1424 @*Names follow ``C'' symbol name rules (start with alpha ...)
1425 @item @b{TAPNAME - Conventions}
1427 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1428 @item @b{cpu} - the main cpu of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1429 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1430 @item @b{bs} - for boundary scan if this is a seperate tap.
1431 @item @b{jrc} - for jtag route controller (example: OMAP3530 found on Beagleboards)
1432 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1433 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1434 @item @b{When in doubt} - use the chip makers name in their data sheet.
1436 @item @b{DOTTED.NAME}
1437 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1438 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1439 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1440 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1441 numerous other places to refer to various taps.
1443 @* The order this command appears via the config files is
1445 @item @b{Multi Tap Example}
1446 @* This example is based on the ST Microsystems STR912. See the ST
1447 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1448 28/102, Figure 3: Jtag chaining inside the STR91xFA}.
1450 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1451 @*@b{checked: 28/nov/2008}
1453 The diagram shows the TDO pin connects to the flash tap, flash TDI
1454 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1455 tap which then connects to the TDI pin.
1459 # create tap: 'str912.flash'
1460 jtag newtap str912 flash ... params ...
1461 # create tap: 'str912.cpu'
1462 jtag newtap str912 cpu ... params ...
1463 # create tap: 'str912.bs'
1464 jtag newtap str912 bs ... params ...
1467 @item @b{Note: Deprecated} - Index Numbers
1468 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1469 feature is still present, however its use is highly discouraged and
1470 should not be counted upon.
1471 @item @b{Multiple chips}
1472 @* If your board has multiple chips, you should be
1473 able to @b{source} two configuration files, in the proper order, and
1474 have the taps created in the proper order.
1477 @comment at command level
1478 @comment DOCUMENT old command
1479 @section jtag_device - REMOVED
1481 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1485 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1486 by the ``jtag newtap'' command. The documentation remains here so that
1487 one can easily convert the old syntax to the new syntax. About the old
1488 syntax: The old syntax is positional, ie: The 4th parameter is the
1489 ``irmask'' The new syntax requires named prefixes, and supports
1490 additional options, for example ``-irmask 4'' Please refer to the
1491 @b{jtag newtap} command for deails.
1493 OLD: jtag_device 8 0x01 0x0e3 0xfe
1494 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0xe3 -irmask 0xfe
1497 @section Enable/Disable Taps
1498 @b{Note:} These commands are intended to be used as a machine/script
1499 interface. Humans might find the ``scan_chain'' command more helpful
1500 when querying the state of the JTAG taps.
1502 @b{By default, all taps are enabled}
1505 @item @b{jtag tapenable} @var{DOTTED.NAME}
1506 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1507 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1512 @cindex route controller
1514 These commands are used when your target has a JTAG Route controller
1515 that effectively adds or removes a tap from the jtag chain in a
1518 The ``standard way'' to remove a tap would be to place the tap in
1519 bypass mode. But with the advent of modern chips, this is not always a
1520 good solution. Some taps operate slowly, others operate fast, and
1521 there are other JTAG clock syncronization problems one must face. To
1522 solve that problem, the JTAG Route controller was introduced. Rather
1523 then ``bypass'' the tap, the tap is completely removed from the
1524 circuit and skipped.
1527 From OpenOCDs view point, a JTAG TAP is in one of 3 states:
1530 @item @b{Enabled - Not In ByPass} and has a variable bit length
1531 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1532 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1535 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1536 @b{Historical note:} this feature was added 28/nov/2008
1538 @b{jtag tapisenabled DOTTED.NAME}
1540 This command return 1 if the named tap is currently enabled, 0 if not.
1541 This command exists so that scripts that manipulate a JRC (like the
1542 Omap3530 has) can determine if OpenOCD thinks a tap is presently
1543 enabled, or disabled.
1546 @node Target Configuration
1547 @chapter Target Configuration
1549 This chapter discusses how to create a GDB Debug Target. Before
1550 creating a ``target'' a JTAG Tap DOTTED.NAME must exist first.
1552 @section targets [NAME]
1553 @b{Note:} This command name is PLURAL - not singular.
1555 With NO parameter, this pural @b{targets} command lists all known
1556 targets in a human friendly form.
1558 With a parameter, this pural @b{targets} command sets the current
1559 target to the given name. (ie: If there are multiple debug targets)
1564 CmdName Type Endian ChainPos State
1565 -- ---------- ---------- ---------- -------- ----------
1566 0: target0 arm7tdmi little 0 halted
1569 @section target COMMANDS
1570 @b{Note:} This command name is SINGULAR - not plural. It is used to
1571 manipulate specific targets, to create targets and other things.
1573 Once a target is created, a TARGETNAME (object) command is created;
1574 see below for details.
1576 The TARGET command accepts these sub-commands:
1578 @item @b{create} .. parameters ..
1579 @* creates a new target, See below for details.
1581 @* Lists all supported target types (perhaps some are not yet in this document).
1583 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1585 foreach t [target names] {
1586 puts [format "Target: %s\n" $t]
1590 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1591 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1592 @item @b{number} @b{NUMBER}
1593 @* Internally OpenOCD maintains a list of targets - in numerical index
1594 (0..N-1) this command returns the name of the target at index N.
1597 set thename [target number $x]
1598 puts [format "Target %d is: %s\n" $x $thename]
1601 @* Returns the number of targets known to OpenOCD (see number above)
1604 set c [target count]
1605 for { set x 0 } { $x < $c } { incr x } {
1606 # Assuming you have created this function
1607 print_target_details $x
1613 @section TARGETNAME (object) commands
1614 @b{Use:} Once a target is created, an ``object name'' that represents the
1615 target is created. By convention, the target name is identical to the
1616 tap name. In a multiple target system, one can preceed many common
1617 commands with a specific target name and effect only that target.
1619 str912.cpu mww 0x1234 0x42
1620 omap3530.cpu mww 0x5555 123
1623 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1624 good example is a on screen button, once a button is created a button
1625 has a name (a path in TK terms) and that name is useable as a 1st
1626 class command. For example in TK, one can create a button and later
1627 configure it like this:
1631 button .foobar -background red -command @{ foo @}
1633 .foobar configure -foreground blue
1635 set x [.foobar cget -background]
1637 puts [format "The button is %s" $x]
1640 In OpenOCDs terms, the ``target'' is an object just like a Tcl/Tk
1641 button. Commands avaialble as a ``target object'' are:
1643 @comment START targetobj commands.
1645 @item @b{configure} - configure the target; see Target Config/Cget Options below
1646 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
1647 @item @b{curstate} - current target state (running, halt, etc)
1649 @* Intended for a human to see/read the currently configure target events.
1650 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
1651 @comment start memory
1661 @item @b{Memory To Array, Array To Memory}
1662 @* These are aimed at a machine interface to memory
1664 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
1665 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
1667 @* @b{ARRAYNAME} is the name of an array variable
1668 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
1669 @* @b{ADDRESS} is the target memory address
1670 @* @b{COUNT} is the number of elements to process
1672 @item @b{Used during ``reset''}
1673 @* These commands are used internally by the OpenOCD scripts to deal
1674 with odd reset situations and are not documented here.
1676 @item @b{arp_examine}
1680 @item @b{arp_waitstate}
1682 @item @b{invoke-event} @b{EVENT-NAME}
1683 @* Invokes the specific event manually for the target
1686 @section Target Events
1687 At various times, certian things happen, or you want to happen.
1691 @item What should happen when GDB connects? Should your target reset?
1692 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
1693 @item During reset, do you need to write to certian memory locations to reconfigure the SDRAM?
1696 All of the above items are handled by target events.
1698 To specify an event action, either during target creation, or later
1699 via ``$_TARGETNAME configure'' see this example.
1701 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
1702 target event name, and BODY is a tcl procedure or string of commands
1705 The programers model is the: ``-command'' option used in Tcl/Tk
1706 buttons and events. Below are two identical examples, the first
1707 creates and invokes small procedure. The second inlines the procedure.
1710 proc my_attach_proc @{ @} @{
1714 mychip.cpu configure -event gdb-attach my_attach_proc
1715 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
1721 @item @b{debug-halted}
1722 @* The target has halted for debug reasons (ie: breakpoint)
1723 @item @b{debug-resumed}
1724 @* The target has resumed (ie: gdb said run)
1725 @item @b{early-halted}
1726 @* Occurs early in the halt process
1727 @item @b{examine-end}
1728 @* Currently not used (goal: when JTAG examine completes)
1729 @item @b{examine-start}
1730 @* Currently not used (goal: when JTAG examine starts)
1731 @item @b{gdb-attach}
1732 @* When GDB connects
1733 @item @b{gdb-detach}
1734 @* When GDB disconnects
1736 @* When the taret has halted and GDB is not doing anything (see early halt)
1737 @item @b{gdb-flash-erase-start}
1738 @* Before the GDB flash process tries to erase the flash
1739 @item @b{gdb-flash-erase-end}
1740 @* After the GDB flash process has finished erasing the flash
1741 @item @b{gdb-flash-write-start}
1742 @* Before GDB writes to the flash
1743 @item @b{gdb-flash-write-end}
1744 @* After GDB writes to the flash
1746 @* Before the taret steps, gdb is trying to start/resume the tarfget
1748 @* The target has halted
1749 @item @b{old-gdb_program_config}
1750 @* DO NOT USE THIS: Used internally
1751 @item @b{old-pre_resume}
1752 @* DO NOT USE THIS: Used internally
1753 @item @b{reset-assert-pre}
1754 @* Before reset is asserted on the tap.
1755 @item @b{reset-assert-post}
1756 @* Reset is now asserted on the tap.
1757 @item @b{reset-deassert-pre}
1758 @* Reset is about to be released on the tap
1759 @item @b{reset-deassert-post}
1760 @* Reset has been released on the tap
1762 @* Currently not used.
1763 @item @b{reset-halt-post}
1764 @* Currently not usd
1765 @item @b{reset-halt-pre}
1766 @* Currently not used
1767 @item @b{reset-init}
1768 @* Currently not used
1769 @item @b{reset-start}
1770 @* Currently not used
1771 @item @b{reset-wait-pos}
1772 @* Currently not used
1773 @item @b{reset-wait-pre}
1774 @* Currently not used
1775 @item @b{resume-start}
1776 @* Before any target is resumed
1777 @item @b{resume-end}
1778 @* After all targets have resumed
1782 @* Target has resumed
1786 @section target create
1788 @cindex target creation
1791 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
1793 @*This command creates a GDB debug target that refers to a specific JTAG tap.
1794 @comment START params
1797 @* Is the name of the debug target. By convention it should be the tap
1798 DOTTED.NAME, this name is also used to create the target object
1801 @* Specifies the target type, ie: arm7tdmi, or cortexM3. Currently supported targes are:
1802 @comment START types
1819 @*PARAMs are various target configure parameters, the following are manditory
1821 @comment START manditory
1823 @item @b{-endian big|little}
1824 @item @b{-chain-position DOTTED.NAME}
1825 @comment end MANDITORY
1830 @section Target Config/Cget Options
1831 These options can be specified when the target is created, or later
1832 via the configure option or to query the target via cget.
1834 @item @b{-type} - returns the target type
1835 @item @b{-event NAME BODY} see Target events
1836 @item @b{-work-area-virt [ADDRESS]} specify/set the work area
1837 @item @b{-work-area-phys [ADDRESS]} specify/set the work area
1838 @item @b{-work-area-size [ADDRESS]} specify/set the work area
1839 @item @b{-work-area-backup [0|1]} does the work area get backed up
1840 @item @b{-endian [big|little]}
1841 @item @b{-variant [NAME]} some chips have varients openocd needs to know about
1842 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
1846 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
1847 set name [target number $x]
1848 set y [$name cget -endian]
1849 set z [$name cget -type]
1850 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
1854 @section Target Varients
1857 @* Unknown (please write me)
1859 @* Unknown (please write me) (simular to arm7tdmi)
1861 @* Varients: @option{arm920t}, @option{arm922t} and @option{arm940t}
1862 This enables the hardware single-stepping support found on these
1867 @* None (this is also used as the ARM946)
1869 @* use variant <@var{-variant lm3s}> when debugging luminary lm3s targets. This will cause
1870 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
1871 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
1872 be detected and the normal reset behaviour used.
1874 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
1876 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
1878 @* Use variant @option{ejtag_srst} when debugging targets that do not
1879 provide a functional SRST line on the EJTAG connector. This causes
1880 openocd to instead use an EJTAG software reset command to reset the
1881 processor. You still need to enable @option{srst} on the reset
1882 configuration command to enable openocd hardware reset functionality.
1883 @comment END varients
1885 @section working_area - Command Removed
1886 @cindex working_area
1887 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
1888 @* This documentation remains because there are existing scripts that
1889 still use this that need to be converted.
1891 working_area target# address size backup| [virtualaddress]
1893 @* The target# is a the 0 based target numerical index.
1895 This command specifies a working area for the debugger to use. This
1896 may be used to speed-up downloads to target memory and flash
1897 operations, or to perform otherwise unavailable operations (some
1898 coprocessor operations on ARM7/9 systems, for example). The last
1899 parameter decides whether the memory should be preserved
1900 (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If
1901 possible, use a working_area that doesn't need to be backed up, as
1902 performing a backup slows down operation.
1904 @node Flash Configuration
1905 @chapter Flash Programing
1906 @cindex Flash Configuration
1908 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
1909 flash that a micro may boot from. Perhaps you the reader would like to
1910 contribute support for this.
1914 @item Configure via the command @b{flash bank}
1915 @* Normally this is done in a configuration file.
1916 @item Operate on the flash via @b{flash SOMECOMMAND}
1917 @* Often commands to manipulate the flash are typed by a human, or run
1918 via a script in some automated way. For example: To program the boot
1919 flash on your board.
1921 @* Flashing via GDB requires the flash be configured via ``flash
1922 bank'', and the GDB flash features be enabled. See the Daemon
1923 configuration section for more details.
1926 @section Flash commands
1927 @cindex Flash commands
1928 @subsection flash banks
1931 @*List configured flash banks
1932 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
1933 @subsection flash info
1934 @b{flash info} <@var{num}>
1936 @*Print info about flash bank <@option{num}>
1937 @subsection flash probe
1938 @b{flash probe} <@var{num}>
1940 @*Identify the flash, or validate the parameters of the configured flash. Operation
1941 depends on the flash type.
1942 @subsection flash erase_check
1943 @b{flash erase_check} <@var{num}>
1944 @cindex flash erase_check
1945 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
1946 updates the erase state information displayed by @option{flash info}. That means you have
1947 to issue an @option{erase_check} command after erasing or programming the device to get
1948 updated information.
1949 @subsection flash protect_check
1950 @b{flash protect_check} <@var{num}>
1951 @cindex flash protect_check
1952 @*Check protection state of sectors in flash bank <num>.
1953 @option{flash erase_sector} using the same syntax.
1954 @subsection fash erase_sector
1955 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
1956 @cindex flash erase_sector
1957 @anchor{flash erase_sector}
1958 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
1959 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
1960 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
1962 @subsection flash erase_address
1963 @b{flash erase_address} <@var{address}> <@var{length}>
1964 @cindex flash erase_address
1965 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
1966 @subsection flash write_bank
1967 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
1968 @cindex flash write_bank
1969 @anchor{flash write_bank}
1970 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
1971 <@option{offset}> bytes from the beginning of the bank.
1972 @subsection flash write_image
1973 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
1974 @cindex flash write_image
1975 @anchor{flash write_image}
1976 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
1977 [@var{offset}] can be specified and the file [@var{type}] can be specified
1978 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
1979 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
1980 if the @option{erase} parameter is given.
1981 @subsection flash protect
1982 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
1983 @cindex flash protect
1984 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
1985 <@var{last}> of @option{flash bank} <@var{num}>.
1987 @subsection mFlash commands
1988 @cindex mFlash commands
1990 @item @b{mflash probe}
1991 @cindex mflash probe
1993 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
1994 @cindex mflash write
1995 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
1996 <@var{offset}> bytes from the beginning of the bank.
1997 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
1999 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2003 @section flash bank command
2004 The @b{flash bank} command is used to configure one or more flash chips (or banks in openocd terms)
2007 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2008 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
2011 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2012 and <@var{bus_width}> bytes using the selected flash <driver>.
2014 @subsection External Flash - cfi options
2016 CFI flash are external flash chips - often they are connected to a
2017 specific chip select on the micro. By default at hard reset most
2018 micros have the ablity to ``boot'' from some flash chip - typically
2019 attached to the chips CS0 pin.
2021 For other chip selects: OpenOCD does not know how to configure, or
2022 access a specific chip select. Instead you the human might need to via
2023 other commands (like: mww) configure additional chip selects, or
2024 perhaps configure a GPIO pin that controls the ``write protect'' pin
2027 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2028 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
2029 @*CFI flashes require the number of the target they're connected to as an additional
2030 argument. The CFI driver makes use of a working area (specified for the target)
2031 to significantly speed up operation.
2033 @var{chip_width} and @var{bus_width} are specified in bytes.
2035 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
2039 @subsection Internal Flash (Micro Controllers)
2040 @subsubsection lpc2000 options
2041 @cindex lpc2000 options
2043 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
2044 <@var{clock}> [@var{calc_checksum}]
2045 @*LPC flashes don't require the chip and bus width to be specified. Additional
2046 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2047 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
2048 of the target this flash belongs to (first is 0), the frequency at which the core
2049 is currently running (in kHz - must be an integral number), and the optional keyword
2050 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2054 @subsubsection at91sam7 options
2055 @cindex at91sam7 options
2057 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
2058 @*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
2059 reading the chip-id and type.
2061 @subsubsection str7 options
2062 @cindex str7 options
2064 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
2065 @*variant can be either STR71x, STR73x or STR75x.
2067 @subsubsection str9 options
2068 @cindex str9 options
2070 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2071 @*The str9 needs the flash controller to be configured prior to Flash programming, eg.
2073 str9x flash_config 0 4 2 0 0x80000
2075 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2077 @subsubsection str9 options (str9xpec driver)
2079 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2080 @*Before using the flash commands the turbo mode will need enabling using str9xpec
2081 @option{enable_turbo} <@var{num>.}
2083 Only use this driver for locking/unlocking the device or configuring the option bytes.
2084 Use the standard str9 driver for programming.
2086 @subsubsection stellaris (LM3Sxxx) options
2087 @cindex stellaris (LM3Sxxx) options
2089 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2090 @*stellaris flash plugin only require the @var{target#}.
2092 @subsubsection stm32x options
2093 @cindex stm32x options
2095 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2096 @*stm32x flash plugin only require the @var{target#}.
2098 @subsubsection aduc702x options
2099 @cindex aduc702x options
2101 @b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2102 @*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
2104 @subsection mFlash configuration
2105 @cindex mFlash configuration
2106 @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
2107 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
2109 @*Configures a mflash for <@var{soc}> host bank at
2110 <@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
2111 order. Pin number format is dependent on host GPIO calling convention.
2112 If WP or DPD pin was not used, write -1. Currently, mflash bank
2113 support s3c2440 and pxa270.
2115 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
2117 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
2119 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
2121 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
2124 @section Micro Controller Specific Flash Commands
2126 @subsection AT91SAM7 specific commands
2127 @cindex AT91SAM7 specific commands
2128 The flash configuration is deduced from the chip identification register. The flash
2129 controller handles erases automatically on a page (128/265 byte) basis so erase is
2130 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2131 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2132 that can be erased separatly. Only an EraseAll command is supported by the controller
2133 for each flash plane and this is called with
2135 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2136 @*bulk erase flash planes first_plane to last_plane.
2137 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2138 @cindex at91sam7 gpnvm
2139 @*set or clear a gpnvm bit for the processor
2142 @subsection STR9 specific commands
2143 @cindex STR9 specific commands
2144 These are flash specific commands when using the str9xpec driver.
2146 @item @b{str9xpec enable_turbo} <@var{num}>
2147 @cindex str9xpec enable_turbo
2148 @*enable turbo mode, simply this will remove the str9 from the chain and talk
2149 directly to the embedded flash controller.
2150 @item @b{str9xpec disable_turbo} <@var{num}>
2151 @cindex str9xpec disable_turbo
2152 @*restore the str9 into jtag chain.
2153 @item @b{str9xpec lock} <@var{num}>
2154 @cindex str9xpec lock
2155 @*lock str9 device. The str9 will only respond to an unlock command that will
2157 @item @b{str9xpec unlock} <@var{num}>
2158 @cindex str9xpec unlock
2159 @*unlock str9 device.
2160 @item @b{str9xpec options_read} <@var{num}>
2161 @cindex str9xpec options_read
2162 @*read str9 option bytes.
2163 @item @b{str9xpec options_write} <@var{num}>
2164 @cindex str9xpec options_write
2165 @*write str9 option bytes.
2168 @subsection STR9 configuration
2169 @cindex STR9 configuration
2171 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2172 <@var{BBADR}> <@var{NBBADR}>
2173 @cindex str9x flash_config
2174 @*Configure str9 flash controller.
2176 eg. str9x flash_config 0 4 2 0 0x80000
2178 BBSR - Boot Bank Size register
2179 NBBSR - Non Boot Bank Size register
2180 BBADR - Boot Bank Start Address register
2181 NBBADR - Boot Bank Start Address register
2185 @subsection STR9 option byte configuration
2186 @cindex STR9 option byte configuration
2188 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2189 @cindex str9xpec options_cmap
2190 @*configure str9 boot bank.
2191 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2192 @cindex str9xpec options_lvdthd
2193 @*configure str9 lvd threshold.
2194 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2195 @cindex str9xpec options_lvdsel
2196 @*configure str9 lvd source.
2197 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2198 @cindex str9xpec options_lvdwarn
2199 @*configure str9 lvd reset warning source.
2202 @subsection STM32x specific commands
2203 @cindex STM32x specific commands
2205 These are flash specific commands when using the stm32x driver.
2207 @item @b{stm32x lock} <@var{num}>
2209 @*lock stm32 device.
2210 @item @b{stm32x unlock} <@var{num}>
2211 @cindex stm32x unlock
2212 @*unlock stm32 device.
2213 @item @b{stm32x options_read} <@var{num}>
2214 @cindex stm32x options_read
2215 @*read stm32 option bytes.
2216 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2217 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2218 @cindex stm32x options_write
2219 @*write stm32 option bytes.
2220 @item @b{stm32x mass_erase} <@var{num}>
2221 @cindex stm32x mass_erase
2222 @*mass erase flash memory.
2225 @subsection Stellaris specific commands
2226 @cindex Stellaris specific commands
2228 These are flash specific commands when using the Stellaris driver.
2230 @item @b{stellaris mass_erase} <@var{num}>
2231 @cindex stellaris mass_erase
2232 @*mass erase flash memory.
2236 @node General Commands
2237 @chapter General Commands
2240 The commands documented in this chapter here are common commands that
2241 you a human may want to type and see the output of. Configuration type
2242 commands are documented elsewhere.
2246 @item @b{Source Of Commands}
2247 @* OpenOCD commands can occur in a configuration script (discussed
2248 elsewhere) or typed manually by a human or supplied programatically,
2249 or via one of several Tcp/Ip Ports.
2251 @item @b{From the human}
2252 @* A human should interact with the Telnet interface (default port: 4444,
2253 or via GDB, default port 3333)
2255 To issue commands from within a GDB session, use the @option{monitor}
2256 command, e.g. use @option{monitor poll} to issue the @option{poll}
2257 command. All output is relayed through the GDB session.
2259 @item @b{Machine Interface}
2260 The TCL interface intent is to be a machine interface. The default TCL
2265 @section Daemon Commands
2268 @b{sleep} <@var{msec}>
2270 @*Wait for n milliseconds before resuming. Useful in connection with script files
2271 (@var{script} command and @var{target_script} configuration).
2276 @*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
2278 @subsection debug_level [@var{n}]
2280 @anchor{debug_level}
2281 @*Display or adjust debug level to n<0-3>
2283 @subsection fast [@var{enable|disable}]
2285 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
2286 downloads and fast memory access will work if the JTAG interface isn't too fast and
2287 the core doesn't run at a too low frequency. Note that this option only changes the default
2288 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
2291 The target specific "dangerous" optimisation tweaking options may come and go
2292 as more robust and user friendly ways are found to ensure maximum throughput
2293 and robustness with a minimum of configuration.
2295 Typically the "fast enable" is specified first on the command line:
2298 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
2301 @subsection log_output <@var{file}>
2303 @*Redirect logging to <file> (default: stderr)
2305 @subsection script <@var{file}>
2307 @*Execute commands from <file>
2308 Also see: ``source [find FILENAME]''
2310 @section Target state handling
2311 @subsection power <@var{on}|@var{off}>
2313 @*Turn power switch to target on/off.
2314 No arguments: print status.
2315 Not all interfaces support this.
2317 @subsection reg [@option{#}|@option{name}] [value]
2319 @*Access a single register by its number[@option{#}] or by its [@option{name}].
2320 No arguments: list all available registers for the current target.
2321 Number or name argument: display a register
2322 Number or name and value arguments: set register value
2324 @subsection poll [@option{on}|@option{off}]
2326 @*Poll the target for its current state. If the target is in debug mode, architecture
2327 specific information about the current state is printed. An optional parameter
2328 allows continuous polling to be enabled and disabled.
2330 @subsection halt [@option{ms}]
2332 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
2333 Default [@option{ms}] is 5 seconds if no arg given.
2334 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
2335 will stop OpenOCD from waiting.
2337 @subsection wait_halt [@option{ms}]
2339 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
2340 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
2343 @subsection resume [@var{address}]
2345 @*Resume the target at its current code position, or at an optional address.
2346 OpenOCD will wait 5 seconds for the target to resume.
2348 @subsection step [@var{address}]
2350 @*Single-step the target at its current code position, or at an optional address.
2352 @subsection reset [@option{run}|@option{halt}|@option{init}]
2354 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
2356 With no arguments a "reset run" is executed
2360 @*Let the target run.
2363 @*Immediately halt the target (works only with certain configurations).
2366 @*Immediately halt the target, and execute the reset script (works only with certain
2370 @subsection soft_reset_halt
2372 @*Requesting target halt and executing a soft reset. This often used
2373 when a target cannot be reset and halted. The target, after reset is
2374 released begins to execute code. OpenOCD attempts to stop the CPU and
2375 then sets the Program counter back at the reset vector. Unfortunatlly
2376 that code that was executed may have left hardware in an unknown
2380 @section Memory access commands
2382 display available ram memory.
2383 @subsection Memory Peek/Poke type commands
2384 These commands allow accesses of a specific size to the memory
2385 system. Often these are used to configure the current target in some
2386 special way. For example - one may need to write certian values to the
2387 SDRAM controller to enable SDRAM.
2390 @item To change the current target see the ``targets'' (plural) command
2391 @item In system level scripts these commands are depricated, please use the TARGET object versions.
2395 @item @b{mdw} <@var{addr}> [@var{count}]
2397 @*display memory words (32bit)
2398 @item @b{mdh} <@var{addr}> [@var{count}]
2400 @*display memory half-words (16bit)
2401 @item @b{mdb} <@var{addr}> [@var{count}]
2403 @*display memory bytes (8bit)
2404 @item @b{mww} <@var{addr}> <@var{value}>
2406 @*write memory word (32bit)
2407 @item @b{mwh} <@var{addr}> <@var{value}>
2409 @*write memory half-word (16bit)
2410 @item @b{mwb} <@var{addr}> <@var{value}>
2412 @*write memory byte (8bit)
2415 @section Image Loading Commands
2416 @subsection load_image
2417 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2420 @*Load image <@var{file}> to target memory at <@var{address}>
2421 @subsection fast_load_image
2422 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2423 @cindex fast_load_image
2424 @anchor{fast_load_image}
2425 @*Normally you should be using @b{load_image} or GDB load. However, for
2426 testing purposes or when IO overhead is significant(OpenOCD running on embedded
2427 host), then storing the image in memory and uploading the image to the target
2428 can be a way to upload e.g. multiple debug sessions when the binary does not change.
2429 Arguments as @b{load_image}, but image is stored in OpenOCD host
2430 memory, i.e. does not affect target. This approach is also useful when profiling
2431 target programming performance as IO and target programming can easily be profiled
2433 @subsection fast_load
2437 @*Loads image stored in memory by @b{fast_load_image} to current target. Must be preceeded by fast_load_image.
2438 @subsection dump_image
2439 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
2442 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
2443 (binary) <@var{file}>.
2444 @subsection verify_image
2445 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2446 @cindex verify_image
2447 @*Verify <@var{file}> against target memory starting at <@var{address}>.
2448 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
2451 @section Breakpoint commands
2452 @cindex Breakpoint commands
2454 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
2456 @*set breakpoint <address> <length> [hw]
2457 @item @b{rbp} <@var{addr}>
2459 @*remove breakpoint <adress>
2460 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
2462 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
2463 @item @b{rwp} <@var{addr}>
2465 @*remove watchpoint <adress>
2468 @section Misc Commands
2469 @cindex Other Target Commands
2471 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
2473 Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.
2476 @section Target Specific Commands
2477 @cindex Target Specific Commands
2481 @section Architecture Specific Commands
2482 @cindex Architecture Specific Commands
2484 @subsection ARMV4/5 specific commands
2485 @cindex ARMV4/5 specific commands
2487 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
2488 or Intel XScale (XScale isn't supported yet).
2490 @item @b{armv4_5 reg}
2492 @*Display a list of all banked core registers, fetching the current value from every
2493 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
2495 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
2496 @cindex armv4_5 core_mode
2497 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
2498 The target is resumed in the currently set @option{core_mode}.
2501 @subsection ARM7/9 specific commands
2502 @cindex ARM7/9 specific commands
2504 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
2505 ARM920t or ARM926EJ-S.
2507 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
2508 @cindex arm7_9 dbgrq
2509 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
2510 safe for all but ARM7TDMI--S cores (like Philips LPC).
2511 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
2512 @cindex arm7_9 fast_memory_access
2513 @anchor{arm7_9 fast_memory_access}
2514 @*Allow OpenOCD to read and write memory without checking completion of
2515 the operation. This provides a huge speed increase, especially with USB JTAG
2516 cables (FT2232), but might be unsafe if used with targets running at a very low
2517 speed, like the 32kHz startup clock of an AT91RM9200.
2518 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
2519 @cindex arm7_9 dcc_downloads
2520 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
2521 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
2522 unsafe, especially with targets running at a very low speed. This command was introduced
2523 with OpenOCD rev. 60.
2526 @subsection ARM720T specific commands
2527 @cindex ARM720T specific commands
2530 @item @b{arm720t cp15} <@var{num}> [@var{value}]
2531 @cindex arm720t cp15
2532 @*display/modify cp15 register <@option{num}> [@option{value}].
2533 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
2534 @cindex arm720t md<bhw>_phys
2535 @*Display memory at physical address addr.
2536 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
2537 @cindex arm720t mw<bhw>_phys
2538 @*Write memory at physical address addr.
2539 @item @b{arm720t virt2phys} <@var{va}>
2540 @cindex arm720t virt2phys
2541 @*Translate a virtual address to a physical address.
2544 @subsection ARM9TDMI specific commands
2545 @cindex ARM9TDMI specific commands
2548 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
2549 @cindex arm9tdmi vector_catch
2550 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
2551 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
2552 @option{irq} @option{fiq}.
2554 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
2557 @subsection ARM966E specific commands
2558 @cindex ARM966E specific commands
2561 @item @b{arm966e cp15} <@var{num}> [@var{value}]
2562 @cindex arm966e cp15
2563 @*display/modify cp15 register <@option{num}> [@option{value}].
2566 @subsection ARM920T specific commands
2567 @cindex ARM920T specific commands
2570 @item @b{arm920t cp15} <@var{num}> [@var{value}]
2571 @cindex arm920t cp15
2572 @*display/modify cp15 register <@option{num}> [@option{value}].
2573 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
2574 @cindex arm920t cp15i
2575 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
2576 @item @b{arm920t cache_info}
2577 @cindex arm920t cache_info
2578 @*Print information about the caches found. This allows you to see if your target
2579 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
2580 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
2581 @cindex arm920t md<bhw>_phys
2582 @*Display memory at physical address addr.
2583 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
2584 @cindex arm920t mw<bhw>_phys
2585 @*Write memory at physical address addr.
2586 @item @b{arm920t read_cache} <@var{filename}>
2587 @cindex arm920t read_cache
2588 @*Dump the content of ICache and DCache to a file.
2589 @item @b{arm920t read_mmu} <@var{filename}>
2590 @cindex arm920t read_mmu
2591 @*Dump the content of the ITLB and DTLB to a file.
2592 @item @b{arm920t virt2phys} <@var{va}>
2593 @cindex arm920t virt2phys
2594 @*Translate a virtual address to a physical address.
2597 @subsection ARM926EJS specific commands
2598 @cindex ARM926EJS specific commands
2601 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
2602 @cindex arm926ejs cp15
2603 @*display/modify cp15 register <@option{num}> [@option{value}].
2604 @item @b{arm926ejs cache_info}
2605 @cindex arm926ejs cache_info
2606 @*Print information about the caches found.
2607 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
2608 @cindex arm926ejs md<bhw>_phys
2609 @*Display memory at physical address addr.
2610 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
2611 @cindex arm926ejs mw<bhw>_phys
2612 @*Write memory at physical address addr.
2613 @item @b{arm926ejs virt2phys} <@var{va}>
2614 @cindex arm926ejs virt2phys
2615 @*Translate a virtual address to a physical address.
2618 @subsection CORTEX_M3 specific commands
2619 @cindex CORTEX_M3 specific commands
2622 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
2623 @cindex cortex_m3 maskisr
2624 @*Enable masking (disabling) interrupts during target step/resume.
2628 @section Debug commands
2629 @cindex Debug commands
2630 The following commands give direct access to the core, and are most likely
2631 only useful while debugging OpenOCD.
2633 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
2634 @cindex arm7_9 write_xpsr
2635 @*Immediately write either the current program status register (CPSR) or the saved
2636 program status register (SPSR), without changing the register cache (as displayed
2637 by the @option{reg} and @option{armv4_5 reg} commands).
2638 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
2639 <@var{0=cpsr},@var{1=spsr}>
2640 @cindex arm7_9 write_xpsr_im8
2641 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
2642 operation (similar to @option{write_xpsr}).
2643 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
2644 @cindex arm7_9 write_core_reg
2645 @*Write a core register, without changing the register cache (as displayed by the
2646 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
2647 encoding of the [M4:M0] bits of the PSR.
2650 @section Target Requests
2651 @cindex Target Requests
2652 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
2653 See libdcc in the contrib dir for more details.
2655 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
2656 @cindex target_request debugmsgs
2657 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
2661 @chapter JTAG Commands
2662 @cindex JTAG commands
2663 Generally most people will not use the bulk of these commands. They
2664 are mostly used by the OpenOCD developers or those who need to
2665 directly manipulate the JTAG taps.
2667 In general these commands control JTAG taps at a very low level. For
2668 example if you need to control a JTAG Route Controller (ie: the
2669 OMAP3530 on the Beagle Board has one) you might use these commands in
2670 a script or an event procedure.
2673 @item @b{scan_chain}
2675 @*Print current scan chain configuration.
2676 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
2678 @*Toggle reset lines.
2679 @item @b{endstate} <@var{tap_state}>
2681 @*Finish JTAG operations in <@var{tap_state}>.
2682 @item @b{runtest} <@var{num_cycles}>
2684 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
2685 @item @b{statemove} [@var{tap_state}]
2687 @*Move to current endstate or [@var{tap_state}]
2688 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
2690 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
2691 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
2693 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
2694 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
2695 @cindex verify_ircapture
2696 @*Verify value captured during Capture-IR. Default is enabled.
2697 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
2699 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
2700 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
2702 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
2709 If OpenOCD runs on an embedded host(as ZY1000 does), then tftp can
2710 be used to access files on PCs(either developer PC or some other PC).
2712 The way this works on the ZY1000 is to prefix a filename by
2713 "/tftp/ip/" and append the tftp path on the tftp
2714 server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
2715 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
2716 if the file was hosted on the embedded host.
2718 In order to achieve decent performance, you must choose a tftp server
2719 that supports a packet size bigger than the default packet size(512 bytes). There
2720 are numerous tftp servers out there(free and commercial) and you will have to do
2721 a bit of googling to find something that fits your requirements.
2723 @node Sample Scripts
2724 @chapter Sample Scripts
2727 This page shows how to use the target library.
2729 The configuration script can be divided in the following section:
2731 @item daemon configuration
2733 @item jtag scan chain
2734 @item target configuration
2735 @item flash configuration
2738 Detailed information about each section can be found at OpenOCD configuration.
2740 @section AT91R40008 example
2741 @cindex AT91R40008 example
2742 To start OpenOCD with a target script for the AT91R40008 CPU and reset
2743 the CPU upon startup of the OpenOCD daemon.
2745 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
2749 @node GDB and OpenOCD
2750 @chapter GDB and OpenOCD
2751 @cindex GDB and OpenOCD
2752 OpenOCD complies with the remote gdbserver protocol, and as such can be used
2753 to debug remote targets.
2755 @section Connecting to gdb
2756 @cindex Connecting to gdb
2757 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
2758 instance 6.3 has a known bug where it produces bogus memory access
2759 errors, which has since been fixed: look up 1836 in
2760 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
2763 A connection is typically started as follows:
2765 target remote localhost:3333
2767 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
2769 To see a list of available OpenOCD commands type @option{monitor help} on the
2772 OpenOCD supports the gdb @option{qSupported} packet, this enables information
2773 to be sent by the gdb server (openocd) to gdb. Typical information includes
2774 packet size and device memory map.
2776 Previous versions of OpenOCD required the following gdb options to increase
2777 the packet size and speed up gdb communication.
2779 set remote memory-write-packet-size 1024
2780 set remote memory-write-packet-size fixed
2781 set remote memory-read-packet-size 1024
2782 set remote memory-read-packet-size fixed
2784 This is now handled in the @option{qSupported} PacketSize.
2786 @section Programming using gdb
2787 @cindex Programming using gdb
2789 By default the target memory map is sent to gdb, this can be disabled by
2790 the following OpenOCD config option:
2792 gdb_memory_map disable
2794 For this to function correctly a valid flash config must also be configured
2795 in OpenOCD. For faster performance you should also configure a valid
2798 Informing gdb of the memory map of the target will enable gdb to protect any
2799 flash area of the target and use hardware breakpoints by default. This means
2800 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
2801 using a memory map. @xref{gdb_breakpoint_override}.
2803 To view the configured memory map in gdb, use the gdb command @option{info mem}
2804 All other unasigned addresses within gdb are treated as RAM.
2806 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
2807 this can be changed to the old behaviour by using the following gdb command.
2809 set mem inaccessible-by-default off
2812 If @option{gdb_flash_program enable} is also used, gdb will be able to
2813 program any flash memory using the vFlash interface.
2815 gdb will look at the target memory map when a load command is given, if any
2816 areas to be programmed lie within the target flash area the vFlash packets
2819 If the target needs configuring before gdb programming, an event
2820 script can be executed.
2822 $_TARGETNAME configure -event EVENTNAME BODY
2825 To verify any flash programming the gdb command @option{compare-sections}
2828 @node TCL scripting API
2829 @chapter TCL scripting API
2830 @cindex TCL scripting API
2833 The commands are stateless. E.g. the telnet command line has a concept
2834 of currently active target, the Tcl API proc's take this sort of state
2835 information as an argument to each proc.
2837 There are three main types of return values: single value, name value
2838 pair list and lists.
2840 Name value pair. The proc 'foo' below returns a name/value pair
2846 > set foo(you) Oyvind
2847 > set foo(mouse) Micky
2848 > set foo(duck) Donald
2856 me Duane you Oyvind mouse Micky duck Donald
2858 Thus, to get the names of the associative array is easy:
2860 foreach { name value } [set foo] {
2861 puts "Name: $name, Value: $value"
2865 Lists returned must be relatively small. Otherwise a range
2866 should be passed in to the proc in question.
2868 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
2869 is the low level API upon which "flash banks" is implemented.
2872 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2874 Read memory and return as a TCL array for script processing
2875 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2877 Convert a TCL array to memory locations and write the values
2878 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
2880 Return information about the flash banks
2883 OpenOCD commands can consist of two words, e.g. "flash banks". The
2884 startup.tcl "unknown" proc will translate this into a tcl proc
2885 called "flash_banks".
2889 @chapter Deprecated/Removed Commands
2890 @cindex Deprecated/Removed Commands
2891 Certain OpenOCD commands have been deprecated/removed during the various revisions.
2894 @item @b{arm7_9 fast_writes}
2895 @cindex arm7_9 fast_writes
2896 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
2897 @item @b{arm7_9 force_hw_bkpts}
2898 @cindex arm7_9 force_hw_bkpts
2899 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
2900 for flash if the gdb memory map has been set up(default when flash is declared in
2901 target configuration). @xref{gdb_breakpoint_override}.
2902 @item @b{arm7_9 sw_bkpts}
2903 @cindex arm7_9 sw_bkpts
2904 @*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
2905 @item @b{daemon_startup}
2906 @cindex daemon_startup
2907 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
2908 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
2909 and @option{target cortex_m3 little reset_halt 0}.
2910 @item @b{dump_binary}
2912 @*use @option{dump_image} command with same args. @xref{dump_image}.
2913 @item @b{flash erase}
2915 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
2916 @item @b{flash write}
2918 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2919 @item @b{flash write_binary}
2920 @cindex flash write_binary
2921 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2922 @item @b{flash auto_erase}
2923 @cindex flash auto_erase
2924 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
2925 @item @b{load_binary}
2927 @*use @option{load_image} command with same args. @xref{load_image}.
2928 @item @b{run_and_halt_time}
2929 @cindex run_and_halt_time
2930 @*This command has been removed for simpler reset behaviour, it can be simulated with the
2937 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
2939 @*use the create subcommand of @option{target}.
2940 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
2941 @cindex target_script
2942 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
2943 @item @b{working_area}
2944 @cindex working_area
2945 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
2952 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
2954 @cindex adaptive clocking
2957 In digital circuit design it is often refered to as ``clock
2958 syncronization'' the JTAG interface uses one clock (TCK or TCLK)
2959 operating at some speed, your target is operating at another. The two
2960 clocks are not syncronized, they are ``asynchronous''
2962 In order for the two to work together they must syncronize. Otherwise
2963 the two systems will get out of sync with each other and nothing will
2964 work. There are 2 basic options. @b{1.} use a special circuit or
2965 @b{2.} one clock must be some multile slower the the other.
2967 @b{Does this really matter?} For some chips and some situations, this
2968 is a non-issue (ie: A 500mhz ARM926) but for others - for example some
2969 ATMEL SAM7 and SAM9 chips start operation from reset at 32khz -
2970 program/enable the oscillators and eventually the main clock. It is in
2971 those critical times you must slow the jtag clock to sometimes 1 to
2974 Imagine debugging that 500mhz arm926 hand held battery powered device
2975 that ``deep sleeps'' at 32khz between every keystroke. It can be
2978 @b{Solution #1 - A special circuit}
2980 In order to make use of this your jtag dongle must support the RTCK
2981 feature. Not all dongles support this - keep reading!
2983 The RTCK signal often found in some ARM chips is used to help with
2984 this problem. ARM has a good description of the problem described at
2985 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
2986 28/nov/2008]. Link title: ``How does the jtag synchronisation logic
2987 work? / how does adaptive clocking working?''.
2989 The nice thing about adaptive clocking is that ``battery powered hand
2990 held device example'' - the adaptiveness works perfectly all the
2991 time. One can set a break point or halt the system in the deep power
2992 down code, slow step out until the system speeds up.
2994 @b{Solution #2 - Always works - but is slower}
2996 Often this is a perfectly acceptable solution.
2998 In the most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
2999 the target clock speed. But what is that ``magic division'' it varies
3000 depending upon the chips on your board. @b{ARM Rule of thumb} Most ARM
3001 based systems require an 8:1 division. @b{Xilinx Rule of thumb} is
3002 1/12 the clock speed.
3004 Note: Many FTDI2232C based JTAG dongles are limited to 6mhz.
3006 You can still debug the 'lower power' situations - you just need to
3007 manually adjust the clock speed at every step. While painful and
3008 teadious, it is not always practical.
3010 It is however easy to ``code your way around it'' - ie: Cheat a little
3011 have a special debug mode in your application that does a ``high power
3012 sleep''. If you are careful - 98% of your problems can be debugged
3015 To set the JTAG frequency use the command:
3023 @item @b{Win32 Pathnames} Why does not backslashes in paths under Windows doesn't work?
3025 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3026 around Windows filenames.
3039 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3041 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3042 claims to come with all the necessary dlls. When using Cygwin, try launching
3043 OpenOCD from the Cygwin shell.
3045 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3046 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3047 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3049 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3050 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
3051 software breakpoints consume one of the two available hardware breakpoints.
3053 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
3054 and works sometimes fine.
3056 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3057 clock at the time you're programming the flash. If you've specified the crystal's
3058 frequency, make sure the PLL is disabled, if you've specified the full core speed
3059 (e.g. 60MHz), make sure the PLL is enabled.
3061 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3062 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3063 out while waiting for end of scan, rtck was disabled".
3065 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3066 settings in your PC BIOS (ECP, EPP, and different versions of those).
3068 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3069 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3070 memory read caused data abort".
3072 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3073 beyond the last valid frame. It might be possible to prevent this by setting up
3074 a proper "initial" stack frame, if you happen to know what exactly has to
3075 be done, feel free to add this here.
3077 @b{Simple:} In your startup code - push 8 registers of ZEROs onto the
3078 stack before calling main(). What GDB is doing is ``climbing'' the run
3079 time stack by reading various values on the stack using the standard
3080 call frame for the target. GDB keeps going - until one of 2 things
3081 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3082 stackframes have been processed. By pushing ZEROs on the stack, GDB
3085 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3086 your C code, do the same, artifically push some zeros on to the stack,
3087 remember to pop them off when the ISR is done.
3089 @b{Also note:} If you have a multi-threaded operating system, they
3090 often do not @b{in the intrest of saving memory} waste these few
3094 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3095 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3097 This warning doesn't indicate any serious problem, as long as you don't want to
3098 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3099 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3100 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3101 independently. With this setup, it's not possible to halt the core right out of
3102 reset, everything else should work fine.
3104 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3105 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3106 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3107 quit with an error message. Is there a stability issue with OpenOCD?
3109 No, this is not a stability issue concerning OpenOCD. Most users have solved
3110 this issue by simply using a self-powered USB hub, which they connect their
3111 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3112 supply stable enough for the Amontec JTAGkey to be operated.
3114 @b{Laptops running on battery have this problem too...}
3116 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3117 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3118 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3119 What does that mean and what might be the reason for this?
3121 First of all, the reason might be the USB power supply. Try using a self-powered
3122 hub instead of a direct connection to your computer. Secondly, the error code 4
3123 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3124 chip ran into some sort of error - this points us to a USB problem.
3126 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3127 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3128 What does that mean and what might be the reason for this?
3130 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3131 has closed the connection to OpenOCD. This might be a GDB issue.
3133 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3134 are described, there is a parameter for specifying the clock frequency
3135 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
3136 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
3137 specified in kilohertz. However, I do have a quartz crystal of a
3138 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
3139 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
3142 No. The clock frequency specified here must be given as an integral number.
3143 However, this clock frequency is used by the In-Application-Programming (IAP)
3144 routines of the LPC2000 family only, which seems to be very tolerant concerning
3145 the given clock frequency, so a slight difference between the specified clock
3146 frequency and the actual clock frequency will not cause any trouble.
3148 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
3150 Well, yes and no. Commands can be given in arbitrary order, yet the
3151 devices listed for the JTAG scan chain must be given in the right
3152 order (jtag newdevice), with the device closest to the TDO-Pin being
3153 listed first. In general, whenever objects of the same type exist
3154 which require an index number, then these objects must be given in the
3155 right order (jtag newtap, targets and flash banks - a target
3156 references a jtag newtap and a flash bank references a target).
3158 You can use the ``scan_chain'' command to verify and display the tap order.
3160 @item @b{JTAG Tap Order} JTAG Tap Order - Command Order
3162 Many newer devices have multiple JTAG taps. For example: ST
3163 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
3164 ``cortexM3'' tap. Example: The STM32 reference manual, Document ID:
3165 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
3166 connected to the Boundary Scan Tap, which then connects to the
3167 CortexM3 Tap, which then connects to the TDO pin.
3169 Thus, the proper order for the STM32 chip is: (1) The CortexM3, then
3170 (2) The Boundary Scan Tap. If your board includes an additional JTAG
3171 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
3172 place it before or after the stm32 chip in the chain. For example:
3175 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
3176 @item STM32 BS TDO (output) -> STM32 CortexM3 TDI (input)
3177 @item STM32 CortexM3 TDO (output) -> SM32 TDO Pin
3178 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
3179 @item Xilinx TDO Pin -> OpenOCD TDO (input)
3182 The ``jtag device'' commands would thus be in the order shown below. Note
3185 @item jtag newtap Xilinx tap -irlen ...
3186 @item jtag newtap stm32 cpu -irlen ...
3187 @item jtag newtap stm32 bs -irlen ...
3188 @item # Create the debug target and say where it is
3189 @item target create stm32.cpu -chain-position stm32.cpu ...
3193 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
3194 log file, I can see these error messages: Error: arm7_9_common.c:561
3195 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
3201 @node TCL Crash Course
3202 @chapter TCL Crash Course
3205 Not everyone knows TCL - this is not intended to be a replacement for
3206 learning TCL, the intent of this chapter is to give you some idea of
3207 how the TCL Scripts work.
3209 This chapter is written with two audiences in mind. (1) OpenOCD users
3210 who need to understand a bit more of how JIM-Tcl works so they can do
3211 something useful, and (2) those that want to add a new command to
3214 @section TCL Rule #1
3215 There is a famous joke, it goes like this:
3217 @item Rule #1: The wife is aways correct
3218 @item Rule #2: If you think otherwise, See Rule #1
3221 The TCL equal is this:
3224 @item Rule #1: Everything is a string
3225 @item Rule #2: If you think otherwise, See Rule #1
3228 As in the famous joke, the consiquences of Rule #1 are profound. Once
3229 you understand Rule #1, you will understand TCL.
3231 @section TCL Rule #1b
3232 There is a second pair of rules.
3234 @item Rule #1: Control flow does not exist. Only commands
3235 @* For example: the classic FOR loop or IF statement is not a control
3236 flow item, they are commands, there is no such thing as control flow
3238 @item Rule #2: If you think otherwise, See Rule #1
3239 @* Actually what happens is this: There are commands that by
3240 convention, act like control flow key words in other languages. One of
3241 those commands is the word ``for'', another command is ``if''.
3244 @section Per Rule #1 - All Results are strings
3245 Every TCL command results in a string. The word ``result'' is used
3246 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
3247 Everything is a string}
3249 @section TCL Quoting Operators
3250 In life of a TCL script, there are two important periods of time, the
3251 difference is subtle.
3254 @item Evaluation Time
3257 The two key items here are how ``quoted things'' work in TCL. TCL has
3258 three primary quoting constructs, the [square-brackets] the
3259 @{curly-braces@} and ``double-quotes''
3261 By now you should know $VARIABLES always start with a $DOLLAR
3262 sign. BTW, to set a variable, you actually use the command ``set'', as
3263 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
3264 = 1'' statement, but without the equal sign.
3267 @item @b{[square-brackets]}
3268 @* @b{[square-brackets]} are command subsitution. It operates much
3269 like Unix Shell `back-ticks`. The result of a [square-bracket]
3270 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
3271 string}. These two statments are roughly identical.
3275 echo "The Date is: $X"
3278 puts "The Date is: $X"
3280 @item @b{``double-quoted-things''}
3281 @* @b{``double-quoted-things''} are just simply quoted
3282 text. $VARIABLES and [square-brackets] are expanded in place - the
3283 result however is exactly 1 string. @i{Remember Rule #1 - Everything
3287 puts "It is now \"[date]\", $x is in 1 hour"
3289 @item @b{@{Curly-Braces@}}
3290 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
3291 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
3292 'single-quote' operators in BASH shell scripts, with the added
3293 feature: @{curly-braces@} nest, single quotes can not. @{@{@{this is
3294 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
3295 28/nov/2008, Jim/OpenOCD does not have a date command.
3298 @section Consiquences of Rule 1/2/3/4
3300 The consiquences of Rule 1 is profound.
3302 @subsection Tokenizing & Execution.
3304 Of course, whitespace, blank lines and #comment lines are handled in
3307 As a script is parsed, each (multi) line in the script file is
3308 tokenized and according to the quoting rules. After tokenizing, that
3309 line is immedatly executed.
3311 Multi line statements end with one or more ``still-open''
3312 @{curly-braces@} which - eventually - a few lines later closes.
3314 @subsection Command Execution
3316 Remember earlier: There is no such thing as ``control flow''
3317 statements in TCL. Instead there are COMMANDS that simpily act like
3318 control flow operators.
3320 Commands are executed like this:
3323 @item Parse the next line into (argc) and (argv[]).
3324 @item Look up (argv[0]) in a table and call its function.
3325 @item Repeat until End Of File.
3328 It sort of works like this:
3331 ReadAndParse( &argc, &argv );
3333 cmdPtr = LookupCommand( argv[0] );
3335 (*cmdPtr->Execute)( argc, argv );
3339 When the command ``proc'' is parsed (which creates a procedure
3340 function) it gets 3 parameters on the command line. @b{1} the name of
3341 the proc (function), @b{2} the list of parameters, and @b{3} the body
3342 of the function. Not the choice of words: LIST and BODY. The PROC
3343 command stores these items in a table somewhere so it can be found by
3346 @subsection The FOR Command
3348 The most interesting command to look at is the FOR command. In TCL,
3349 the FOR command is normally implimented in C. Remember, FOR is a
3350 command just like any other command.
3352 When the ascii text containing the FOR command is parsed, the parser
3353 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
3357 @item The ascii text 'for'
3358 @item The start text
3359 @item The test expression
3364 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
3365 Remember @i{Rule #1 - Everything is a string.} The key point is this:
3366 Often many of those parameters are in @{curly-braces@} - thus the
3367 variables inside are not expanded or replaced until later.
3369 Remember that every TCL command looks like the classic ``main( argc,
3370 argv )'' function in C. In JimTCL - they actually look like this:
3374 MyCommand( Jim_Interp *interp,
3376 Jim_Obj * const *argvs );
3379 Real TCL is nearly identical. Although the newer versions have
3380 introduced a byte-code parser and intepreter, but at the core, it
3381 still operates in the same basic way.
3383 @subsection FOR Command Implimentation
3385 To understand TCL it is perhaps most helpful to see the FOR
3386 command. Remember, it is a COMMAND not a control flow structure.
3388 In TCL there are two underying C helper functions.
3390 Remember Rule #1 - You are a string.
3392 The @b{first} helper parses and executes commands found in an ascii
3393 string. Commands can be seperated by semi-colons, or newlines. While
3394 parsing, variables are expanded per the quoting rules
3396 The @b{second} helper evaluates an ascii string as a numerical
3397 expression and returns a value.
3399 Here is an example of how the @b{FOR} command could be
3400 implimented. The pseudo code below does not show error handling.
3402 void Execute_AsciiString( void *interp, const char *string );
3404 int Evaluate_AsciiExpression( void *interp, const char *string );
3407 MyForCommand( void *interp,
3412 SetResult( interp, "WRONG number of parameters");
3416 // argv[0] = the ascii string just like C
3418 // Execute the start statement.
3419 Execute_AsciiString( interp, argv[1] );
3423 i = Evaluate_AsciiExpression(interp, argv[2]);
3428 Execute_AsciiString( interp, argv[3] );
3430 // Execute the LOOP part
3431 Execute_AsciiString( interp, argv[4] );
3435 SetResult( interp, "" );
3440 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
3441 in the same basic way.
3443 @section OpenOCD TCL Usage
3445 @subsection source and find commands
3446 @b{Where:} In many configuration files
3447 @* Example: @b{ source [find FILENAME] }
3448 @*Remember the parsing rules
3450 @item The FIND command is in square brackets.
3451 @* The FIND command is executed with the parameter FILENAME. It should
3452 find the full path to the named file. The RESULT is a string, which is
3453 subsituted on the orginal command line.
3454 @item The command source is executed with the resulting filename.
3455 @* SOURCE reads a file and executes as a script.
3457 @subsection format command
3458 @b{Where:} Generally occurs in numerous places.
3459 @* TCL no command like @b{printf()}, intead it has @b{format}, which is really more like
3465 puts [format "The answer: %d" [expr $x * $y]]
3468 @item The SET command creates 2 variables, X and Y.
3469 @item The double [nested] EXPR command performs math
3470 @* The EXPR command produces numerical result as a string.
3472 @item The format command is executed, producing a single string
3473 @* Refer to Rule #1.
3474 @item The PUTS command outputs the text.
3476 @subsection Body Or Inlined Text
3477 @b{Where:} Various TARGET scripts.
3480 proc someproc @{@} @{
3481 ... multiple lines of stuff ...
3483 $_TARGETNAME configure -event FOO someproc
3484 #2 Good - no variables
3485 $_TARGETNAME confgure -event foo "this ; that;"
3486 #3 Good Curly Braces
3487 $_TARGETNAME configure -event FOO @{
3490 #4 DANGER DANGER DANGER
3491 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
3494 @item The $_TARGETNAME is an OpenOCD variable convention.
3495 @*@b{$_TARGETNAME} represents the last target created, the value changes
3496 each time a new target is created. Remember the parsing rules. When
3497 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
3498 the name of the target which happens to be a TARGET (object)
3500 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
3501 @*There are 4 examples:
3503 @item The TCLBODY is a simple string that happens to be a proc name
3504 @item The TCLBODY is several simple commands semi-colon seperated
3505 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
3506 @item The TCLBODY is a string with variables that get expanded.
3509 In the end, when the target event FOO occurs the TCLBODY is
3510 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
3511 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
3513 Remember the parsing rules. In case #3, @{curly-braces@} mean the
3514 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
3515 and the text is evaluated. In case #4, they are replaced before the
3516 ``Target Object Command'' is executed. This occurs at the same time
3517 $_TARGETNAME is replaced. In case #4 the date will never
3518 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
3519 Jim/OpenOCD does not have a date command@}
3521 @subsection Global Variables
3522 @b{Where:} You might discover this when writing your own procs @* In
3523 simple terms: Inside a PROC, if you need to access a global variable
3524 you must say so. Also see ``upvar''. Example:
3526 proc myproc @{ @} @{
3527 set y 0 #Local variable Y
3528 global x #Global variable X
3529 puts [format "X=%d, Y=%d" $x $y]
3532 @section Other Tcl Hacks
3533 @b{Dynamic Variable Creation}
3535 # Dynamically create a bunch of variables.
3536 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
3538 set vn [format "BIT%d" $x]
3542 set $vn [expr (1 << $x)]
3545 @b{Dynamic Proc/Command Creation}
3547 # One "X" function - 5 uart functions.
3548 foreach who @{A B C D E@}
3549 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
3553 @node Target library
3554 @chapter Target library
3555 @cindex Target library
3557 OpenOCD comes with a target configuration script library. These scripts can be
3558 used as-is or serve as a starting point.
3560 The target library is published together with the openocd executable and
3561 the path to the target library is in the OpenOCD script search path.
3562 Similarly there are example scripts for configuring the JTAG interface.
3564 The command line below uses the example parport configuration scripts
3565 that ship with OpenOCD, then configures the str710.cfg target and
3566 finally issues the init and reset command. The communication speed
3567 is set to 10kHz for reset and 8MHz for post reset.
3571 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
3575 To list the target scripts available:
3578 $ ls /usr/local/lib/openocd/target
3580 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
3581 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
3582 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
3583 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
3591 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
3592 @comment case issue with ``Index.html'' and ``index.html''
3593 @comment Occurs when creating ``--html --no-split'' output
3594 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
3595 @unnumbered OpenOCD Index