1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.org/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.org/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
208 @chapter OpenOCD Developer Resources
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD Git Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
224 @uref{git://git.code.sf.net/p/openocd/code}
228 @uref{http://git.code.sf.net/p/openocd/code}
230 You may prefer to use a mirror and the HTTP protocol:
232 @uref{http://repo.or.cz/r/openocd.git}
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
240 @uref{http://repo.or.cz/w/openocd.git}
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
250 @section Doxygen Developer Manual
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
263 @section Gerrit Review System
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 @uref{https://review.openocd.org/}
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
282 @section OpenOCD Developer Mailing List
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289 @section OpenOCD Bug Tracker
291 The OpenOCD Bug Tracker is hosted on SourceForge:
293 @uref{http://bugs.openocd.org/}
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
312 @section Choosing a Dongle
314 There are several things you should keep in mind when choosing a dongle.
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
331 @section USB FT2232 Based
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
406 @section USB-JTAG / Altera USB-Blaster compatibles
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
522 @section IBM PC Parallel Printer Port Based
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
588 @* A Texas Instruments AM335x-based board (e.g. BeagleBone Black) using the GPIO pins of the expansion headers.
591 @* A JTAG driver acting as a client for the JTAG VPI server interface.
592 @* Link: @url{http://github.com/fjullien/jtag_vpi}
595 @* A driver for Cadence virtual Debug Interface to emulated or simulated targets.
596 It implements a client connecting to the vdebug server, which in turn communicates
597 with the emulated or simulated RTL model through a transactor. The driver supports
598 JTAG and DAP-level transports.
601 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
602 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
603 interface of a hardware model written in SystemVerilog, for example, on an
604 emulation model of target hardware.
606 @item @b{xlnx_pcie_xvc}
607 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
610 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
613 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
614 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
616 @item @b{esp_usb_jtag}
617 @* A JTAG driver to communicate with builtin debug modules of Espressif ESP32-C3 and ESP32-S3 chips using OpenOCD.
622 @chapter About Jim-Tcl
626 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
627 This programming language provides a simple and extensible
630 All commands presented in this Guide are extensions to Jim-Tcl.
631 You can use them as simple commands, without needing to learn
632 much of anything about Tcl.
633 Alternatively, you can write Tcl programs with them.
635 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
636 There is an active and responsive community, get on the mailing list
637 if you have any questions. Jim-Tcl maintainers also lurk on the
638 OpenOCD mailing list.
641 @item @b{Jim vs. Tcl}
642 @* Jim-Tcl is a stripped down version of the well known Tcl language,
643 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
644 fewer features. Jim-Tcl is several dozens of .C files and .H files and
645 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
646 4.2 MB .zip file containing 1540 files.
648 @item @b{Missing Features}
649 @* Our practice has been: Add/clone the real Tcl feature if/when
650 needed. We welcome Jim-Tcl improvements, not bloat. Also there
651 are a large number of optional Jim-Tcl features that are not
655 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
656 command interpreter today is a mixture of (newer)
657 Jim-Tcl commands, and the (older) original command interpreter.
660 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
661 can type a Tcl for() loop, set variables, etc.
662 Some of the commands documented in this guide are implemented
663 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
665 @item @b{Historical Note}
666 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
667 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
668 as a Git submodule, which greatly simplified upgrading Jim-Tcl
669 to benefit from new features and bugfixes in Jim-Tcl.
671 @item @b{Need a crash course in Tcl?}
672 @*@xref{Tcl Crash Course}.
677 @cindex command line options
679 @cindex directory search
681 Properly installing OpenOCD sets up your operating system to grant it access
682 to the debug adapters. On Linux, this usually involves installing a file
683 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
684 that works for many common adapters is shipped with OpenOCD in the
685 @file{contrib} directory. MS-Windows needs
686 complex and confusing driver configuration for every peripheral. Such issues
687 are unique to each operating system, and are not detailed in this User's Guide.
689 Then later you will invoke the OpenOCD server, with various options to
690 tell it how each debug session should work.
691 The @option{--help} option shows:
695 --help | -h display this help
696 --version | -v display OpenOCD version
697 --file | -f use configuration file <name>
698 --search | -s dir to search for config files and scripts
699 --debug | -d set debug level to 3
700 | -d<n> set debug level to <level>
701 --log_output | -l redirect log output to file <name>
702 --command | -c run <command>
705 If you don't give any @option{-f} or @option{-c} options,
706 OpenOCD tries to read the configuration file @file{openocd.cfg}.
707 To specify one or more different
708 configuration files, use @option{-f} options. For example:
711 openocd -f config1.cfg -f config2.cfg -f config3.cfg
714 Configuration files and scripts are searched for in
716 @item the current directory,
717 @item any search dir specified on the command line using the @option{-s} option,
718 @item any search dir specified using the @command{add_script_search_dir} command,
719 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
720 @item @file{%APPDATA%/OpenOCD} (only on Windows),
721 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
722 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
723 @item @file{$HOME/.openocd},
724 @item the site wide script library @file{$pkgdatadir/site} and
725 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
727 The first found file with a matching file name will be used.
730 Don't try to use configuration script names or paths which
731 include the "#" character. That character begins Tcl comments.
734 @section Simple setup, no customization
736 In the best case, you can use two scripts from one of the script
737 libraries, hook up your JTAG adapter, and start the server ... and
738 your JTAG setup will just work "out of the box". Always try to
739 start by reusing those scripts, but assume you'll need more
740 customization even if this works. @xref{OpenOCD Project Setup}.
742 If you find a script for your JTAG adapter, and for your board or
743 target, you may be able to hook up your JTAG adapter then start
744 the server with some variation of one of the following:
747 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
748 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
751 You might also need to configure which reset signals are present,
752 using @option{-c 'reset_config trst_and_srst'} or something similar.
753 If all goes well you'll see output something like
756 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
757 For bug reports, read
758 http://openocd.org/doc/doxygen/bugs.html
759 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
760 (mfg: 0x23b, part: 0xba00, ver: 0x3)
763 Seeing that "tap/device found" message, and no warnings, means
764 the JTAG communication is working. That's a key milestone, but
765 you'll probably need more project-specific setup.
767 @section What OpenOCD does as it starts
769 OpenOCD starts by processing the configuration commands provided
770 on the command line or, if there were no @option{-c command} or
771 @option{-f file.cfg} options given, in @file{openocd.cfg}.
772 @xref{configurationstage,,Configuration Stage}.
773 At the end of the configuration stage it verifies the JTAG scan
774 chain defined using those commands; your configuration should
775 ensure that this always succeeds.
776 Normally, OpenOCD then starts running as a server.
777 Alternatively, commands may be used to terminate the configuration
778 stage early, perform work (such as updating some flash memory),
779 and then shut down without acting as a server.
781 Once OpenOCD starts running as a server, it waits for connections from
782 clients (Telnet, GDB, RPC) and processes the commands issued through
785 If you are having problems, you can enable internal debug messages via
786 the @option{-d} option.
788 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
789 @option{-c} command line switch.
791 To enable debug output (when reporting problems or working on OpenOCD
792 itself), use the @option{-d} command line switch. This sets the
793 @option{debug_level} to "3", outputting the most information,
794 including debug messages. The default setting is "2", outputting only
795 informational messages, warnings and errors. You can also change this
796 setting from within a telnet or gdb session using @command{debug_level<n>}
797 (@pxref{debuglevel,,debug_level}).
799 You can redirect all output from the server to a file using the
800 @option{-l <logfile>} switch.
802 Note! OpenOCD will launch the GDB & telnet server even if it can not
803 establish a connection with the target. In general, it is possible for
804 the JTAG controller to be unresponsive until the target is set up
805 correctly via e.g. GDB monitor commands in a GDB init script.
807 @node OpenOCD Project Setup
808 @chapter OpenOCD Project Setup
810 To use OpenOCD with your development projects, you need to do more than
811 just connect the JTAG adapter hardware (dongle) to your development board
812 and start the OpenOCD server.
813 You also need to configure your OpenOCD server so that it knows
814 about your adapter and board, and helps your work.
815 You may also want to connect OpenOCD to GDB, possibly
816 using Eclipse or some other GUI.
818 @section Hooking up the JTAG Adapter
820 Today's most common case is a dongle with a JTAG cable on one side
821 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
822 and a USB cable on the other.
823 Instead of USB, some dongles use Ethernet;
824 older ones may use a PC parallel port, or even a serial port.
827 @item @emph{Start with power to your target board turned off},
828 and nothing connected to your JTAG adapter.
829 If you're particularly paranoid, unplug power to the board.
830 It's important to have the ground signal properly set up,
831 unless you are using a JTAG adapter which provides
832 galvanic isolation between the target board and the
835 @item @emph{Be sure it's the right kind of JTAG connector.}
836 If your dongle has a 20-pin ARM connector, you need some kind
837 of adapter (or octopus, see below) to hook it up to
838 boards using 14-pin or 10-pin connectors ... or to 20-pin
839 connectors which don't use ARM's pinout.
841 In the same vein, make sure the voltage levels are compatible.
842 Not all JTAG adapters have the level shifters needed to work
843 with 1.2 Volt boards.
845 @item @emph{Be certain the cable is properly oriented} or you might
846 damage your board. In most cases there are only two possible
847 ways to connect the cable.
848 Connect the JTAG cable from your adapter to the board.
849 Be sure it's firmly connected.
851 In the best case, the connector is keyed to physically
852 prevent you from inserting it wrong.
853 This is most often done using a slot on the board's male connector
854 housing, which must match a key on the JTAG cable's female connector.
855 If there's no housing, then you must look carefully and
856 make sure pin 1 on the cable hooks up to pin 1 on the board.
857 Ribbon cables are frequently all grey except for a wire on one
858 edge, which is red. The red wire is pin 1.
860 Sometimes dongles provide cables where one end is an ``octopus'' of
861 color coded single-wire connectors, instead of a connector block.
862 These are great when converting from one JTAG pinout to another,
863 but are tedious to set up.
864 Use these with connector pinout diagrams to help you match up the
865 adapter signals to the right board pins.
867 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
868 A USB, parallel, or serial port connector will go to the host which
869 you are using to run OpenOCD.
870 For Ethernet, consult the documentation and your network administrator.
872 For USB-based JTAG adapters you have an easy sanity check at this point:
873 does the host operating system see the JTAG adapter? If you're running
874 Linux, try the @command{lsusb} command. If that host is an
875 MS-Windows host, you'll need to install a driver before OpenOCD works.
877 @item @emph{Connect the adapter's power supply, if needed.}
878 This step is primarily for non-USB adapters,
879 but sometimes USB adapters need extra power.
881 @item @emph{Power up the target board.}
882 Unless you just let the magic smoke escape,
883 you're now ready to set up the OpenOCD server
884 so you can use JTAG to work with that board.
888 Talk with the OpenOCD server using
889 telnet (@code{telnet localhost 4444} on many systems) or GDB.
890 @xref{GDB and OpenOCD}.
892 @section Project Directory
894 There are many ways you can configure OpenOCD and start it up.
896 A simple way to organize them all involves keeping a
897 single directory for your work with a given board.
898 When you start OpenOCD from that directory,
899 it searches there first for configuration files, scripts,
900 files accessed through semihosting,
901 and for code you upload to the target board.
902 It is also the natural place to write files,
903 such as log files and data you download from the board.
905 @section Configuration Basics
907 There are two basic ways of configuring OpenOCD, and
908 a variety of ways you can mix them.
909 Think of the difference as just being how you start the server:
912 @item Many @option{-f file} or @option{-c command} options on the command line
913 @item No options, but a @dfn{user config file}
914 in the current directory named @file{openocd.cfg}
917 Here is an example @file{openocd.cfg} file for a setup
918 using a Signalyzer FT2232-based JTAG adapter to talk to
919 a board with an Atmel AT91SAM7X256 microcontroller:
922 source [find interface/ftdi/signalyzer.cfg]
924 # GDB can also flash my flash!
925 gdb_memory_map enable
926 gdb_flash_program enable
928 source [find target/sam7x256.cfg]
931 Here is the command line equivalent of that configuration:
934 openocd -f interface/ftdi/signalyzer.cfg \
935 -c "gdb_memory_map enable" \
936 -c "gdb_flash_program enable" \
937 -f target/sam7x256.cfg
940 You could wrap such long command lines in shell scripts,
941 each supporting a different development task.
942 One might re-flash the board with a specific firmware version.
943 Another might set up a particular debugging or run-time environment.
946 At this writing (October 2009) the command line method has
947 problems with how it treats variables.
948 For example, after @option{-c "set VAR value"}, or doing the
949 same in a script, the variable @var{VAR} will have no value
950 that can be tested in a later script.
953 Here we will focus on the simpler solution: one user config
954 file, including basic configuration plus any TCL procedures
955 to simplify your work.
957 @section User Config Files
958 @cindex config file, user
959 @cindex user config file
960 @cindex config file, overview
962 A user configuration file ties together all the parts of a project
964 One of the following will match your situation best:
967 @item Ideally almost everything comes from configuration files
968 provided by someone else.
969 For example, OpenOCD distributes a @file{scripts} directory
970 (probably in @file{/usr/share/openocd/scripts} on Linux).
971 Board and tool vendors can provide these too, as can individual
972 user sites; the @option{-s} command line option lets you say
973 where to find these files. (@xref{Running}.)
974 The AT91SAM7X256 example above works this way.
976 Three main types of non-user configuration file each have their
977 own subdirectory in the @file{scripts} directory:
980 @item @b{interface} -- one for each different debug adapter;
981 @item @b{board} -- one for each different board
982 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
985 Best case: include just two files, and they handle everything else.
986 The first is an interface config file.
987 The second is board-specific, and it sets up the JTAG TAPs and
988 their GDB targets (by deferring to some @file{target.cfg} file),
989 declares all flash memory, and leaves you nothing to do except
993 source [find interface/olimex-jtag-tiny.cfg]
994 source [find board/csb337.cfg]
997 Boards with a single microcontroller often won't need more
998 than the target config file, as in the AT91SAM7X256 example.
999 That's because there is no external memory (flash, DDR RAM), and
1000 the board differences are encapsulated by application code.
1002 @item Maybe you don't know yet what your board looks like to JTAG.
1003 Once you know the @file{interface.cfg} file to use, you may
1004 need help from OpenOCD to discover what's on the board.
1005 Once you find the JTAG TAPs, you can just search for appropriate
1007 configuration files ... or write your own, from the bottom up.
1008 @xref{autoprobing,,Autoprobing}.
1010 @item You can often reuse some standard config files but
1011 need to write a few new ones, probably a @file{board.cfg} file.
1012 You will be using commands described later in this User's Guide,
1013 and working with the guidelines in the next chapter.
1015 For example, there may be configuration files for your JTAG adapter
1016 and target chip, but you need a new board-specific config file
1017 giving access to your particular flash chips.
1018 Or you might need to write another target chip configuration file
1019 for a new chip built around the Cortex-M3 core.
1022 When you write new configuration files, please submit
1023 them for inclusion in the next OpenOCD release.
1024 For example, a @file{board/newboard.cfg} file will help the
1025 next users of that board, and a @file{target/newcpu.cfg}
1026 will help support users of any board using that chip.
1030 You may need to write some C code.
1031 It may be as simple as supporting a new FT2232 or parport
1032 based adapter; a bit more involved, like a NAND or NOR flash
1033 controller driver; or a big piece of work like supporting
1034 a new chip architecture.
1037 Reuse the existing config files when you can.
1038 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1039 You may find a board configuration that's a good example to follow.
1041 When you write config files, separate the reusable parts
1042 (things every user of that interface, chip, or board needs)
1043 from ones specific to your environment and debugging approach.
1047 For example, a @code{gdb-attach} event handler that invokes
1048 the @command{reset init} command will interfere with debugging
1049 early boot code, which performs some of the same actions
1050 that the @code{reset-init} event handler does.
1053 Likewise, the @command{arm9 vector_catch} command (or
1054 @cindex vector_catch
1055 its siblings @command{xscale vector_catch}
1056 and @command{cortex_m vector_catch}) can be a time-saver
1057 during some debug sessions, but don't make everyone use that either.
1058 Keep those kinds of debugging aids in your user config file,
1059 along with messaging and tracing setup.
1060 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1063 You might need to override some defaults.
1064 For example, you might need to move, shrink, or back up the target's
1065 work area if your application needs much SRAM.
1068 TCP/IP port configuration is another example of something which
1069 is environment-specific, and should only appear in
1070 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1073 @section Project-Specific Utilities
1075 A few project-specific utility
1076 routines may well speed up your work.
1077 Write them, and keep them in your project's user config file.
1079 For example, if you are making a boot loader work on a
1080 board, it's nice to be able to debug the ``after it's
1081 loaded to RAM'' parts separately from the finicky early
1082 code which sets up the DDR RAM controller and clocks.
1083 A script like this one, or a more GDB-aware sibling,
1087 proc ramboot @{ @} @{
1088 # Reset, running the target's "reset-init" scripts
1089 # to initialize clocks and the DDR RAM controller.
1090 # Leave the CPU halted.
1093 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1094 load_image u-boot.bin 0x20000000
1101 Then once that code is working you will need to make it
1102 boot from NOR flash; a different utility would help.
1103 Alternatively, some developers write to flash using GDB.
1104 (You might use a similar script if you're working with a flash
1105 based microcontroller application instead of a boot loader.)
1108 proc newboot @{ @} @{
1109 # Reset, leaving the CPU halted. The "reset-init" event
1110 # proc gives faster access to the CPU and to NOR flash;
1111 # "reset halt" would be slower.
1114 # Write standard version of U-Boot into the first two
1115 # sectors of NOR flash ... the standard version should
1116 # do the same lowlevel init as "reset-init".
1117 flash protect 0 0 1 off
1118 flash erase_sector 0 0 1
1119 flash write_bank 0 u-boot.bin 0x0
1120 flash protect 0 0 1 on
1122 # Reboot from scratch using that new boot loader.
1127 You may need more complicated utility procedures when booting
1129 That often involves an extra bootloader stage,
1130 running from on-chip SRAM to perform DDR RAM setup so it can load
1131 the main bootloader code (which won't fit into that SRAM).
1133 Other helper scripts might be used to write production system images,
1134 involving considerably more than just a three stage bootloader.
1136 @section Target Software Changes
1138 Sometimes you may want to make some small changes to the software
1139 you're developing, to help make JTAG debugging work better.
1140 For example, in C or assembly language code you might
1141 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1142 handling issues like:
1146 @item @b{Watchdog Timers}...
1147 Watchdog timers are typically used to automatically reset systems if
1148 some application task doesn't periodically reset the timer. (The
1149 assumption is that the system has locked up if the task can't run.)
1150 When a JTAG debugger halts the system, that task won't be able to run
1151 and reset the timer ... potentially causing resets in the middle of
1152 your debug sessions.
1154 It's rarely a good idea to disable such watchdogs, since their usage
1155 needs to be debugged just like all other parts of your firmware.
1156 That might however be your only option.
1158 Look instead for chip-specific ways to stop the watchdog from counting
1159 while the system is in a debug halt state. It may be simplest to set
1160 that non-counting mode in your debugger startup scripts. You may however
1161 need a different approach when, for example, a motor could be physically
1162 damaged by firmware remaining inactive in a debug halt state. That might
1163 involve a type of firmware mode where that "non-counting" mode is disabled
1164 at the beginning then re-enabled at the end; a watchdog reset might fire
1165 and complicate the debug session, but hardware (or people) would be
1166 protected.@footnote{Note that many systems support a "monitor mode" debug
1167 that is a somewhat cleaner way to address such issues. You can think of
1168 it as only halting part of the system, maybe just one task,
1169 instead of the whole thing.
1170 At this writing, January 2010, OpenOCD based debugging does not support
1171 monitor mode debug, only "halt mode" debug.}
1173 @item @b{ARM Semihosting}...
1174 @cindex ARM semihosting
1175 When linked with a special runtime library provided with many
1176 toolchains@footnote{See chapter 8 "Semihosting" in
1177 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1178 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1179 The CodeSourcery EABI toolchain also includes a semihosting library.},
1180 your target code can use I/O facilities on the debug host. That library
1181 provides a small set of system calls which are handled by OpenOCD.
1182 It can let the debugger provide your system console and a file system,
1183 helping with early debugging or providing a more capable environment
1184 for sometimes-complex tasks like installing system firmware onto
1187 @item @b{ARM Wait-For-Interrupt}...
1188 Many ARM chips synchronize the JTAG clock using the core clock.
1189 Low power states which stop that core clock thus prevent JTAG access.
1190 Idle loops in tasking environments often enter those low power states
1191 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1193 You may want to @emph{disable that instruction} in source code,
1194 or otherwise prevent using that state,
1195 to ensure you can get JTAG access at any time.@footnote{As a more
1196 polite alternative, some processors have special debug-oriented
1197 registers which can be used to change various features including
1198 how the low power states are clocked while debugging.
1199 The STM32 DBGMCU_CR register is an example; at the cost of extra
1200 power consumption, JTAG can be used during low power states.}
1201 For example, the OpenOCD @command{halt} command may not
1202 work for an idle processor otherwise.
1204 @item @b{Delay after reset}...
1205 Not all chips have good support for debugger access
1206 right after reset; many LPC2xxx chips have issues here.
1207 Similarly, applications that reconfigure pins used for
1208 JTAG access as they start will also block debugger access.
1210 To work with boards like this, @emph{enable a short delay loop}
1211 the first thing after reset, before "real" startup activities.
1212 For example, one second's delay is usually more than enough
1213 time for a JTAG debugger to attach, so that
1214 early code execution can be debugged
1215 or firmware can be replaced.
1217 @item @b{Debug Communications Channel (DCC)}...
1218 Some processors include mechanisms to send messages over JTAG.
1219 Many ARM cores support these, as do some cores from other vendors.
1220 (OpenOCD may be able to use this DCC internally, speeding up some
1221 operations like writing to memory.)
1223 Your application may want to deliver various debugging messages
1224 over JTAG, by @emph{linking with a small library of code}
1225 provided with OpenOCD and using the utilities there to send
1226 various kinds of message.
1227 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1231 @section Target Hardware Setup
1233 Chip vendors often provide software development boards which
1234 are highly configurable, so that they can support all options
1235 that product boards may require. @emph{Make sure that any
1236 jumpers or switches match the system configuration you are
1239 Common issues include:
1243 @item @b{JTAG setup} ...
1244 Boards may support more than one JTAG configuration.
1245 Examples include jumpers controlling pullups versus pulldowns
1246 on the nTRST and/or nSRST signals, and choice of connectors
1247 (e.g. which of two headers on the base board,
1248 or one from a daughtercard).
1249 For some Texas Instruments boards, you may need to jumper the
1250 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1252 @item @b{Boot Modes} ...
1253 Complex chips often support multiple boot modes, controlled
1254 by external jumpers. Make sure this is set up correctly.
1255 For example many i.MX boards from NXP need to be jumpered
1256 to "ATX mode" to start booting using the on-chip ROM, when
1257 using second stage bootloader code stored in a NAND flash chip.
1259 Such explicit configuration is common, and not limited to
1260 booting from NAND. You might also need to set jumpers to
1261 start booting using code loaded from an MMC/SD card; external
1262 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1263 flash; some external host; or various other sources.
1266 @item @b{Memory Addressing} ...
1267 Boards which support multiple boot modes may also have jumpers
1268 to configure memory addressing. One board, for example, jumpers
1269 external chipselect 0 (used for booting) to address either
1270 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1271 or NAND flash. When it's jumpered to address NAND flash, that
1272 board must also be told to start booting from on-chip ROM.
1274 Your @file{board.cfg} file may also need to be told this jumper
1275 configuration, so that it can know whether to declare NOR flash
1276 using @command{flash bank} or instead declare NAND flash with
1277 @command{nand device}; and likewise which probe to perform in
1278 its @code{reset-init} handler.
1280 A closely related issue is bus width. Jumpers might need to
1281 distinguish between 8 bit or 16 bit bus access for the flash
1282 used to start booting.
1284 @item @b{Peripheral Access} ...
1285 Development boards generally provide access to every peripheral
1286 on the chip, sometimes in multiple modes (such as by providing
1287 multiple audio codec chips).
1288 This interacts with software
1289 configuration of pin multiplexing, where for example a
1290 given pin may be routed either to the MMC/SD controller
1291 or the GPIO controller. It also often interacts with
1292 configuration jumpers. One jumper may be used to route
1293 signals to an MMC/SD card slot or an expansion bus (which
1294 might in turn affect booting); others might control which
1295 audio or video codecs are used.
1299 Plus you should of course have @code{reset-init} event handlers
1300 which set up the hardware to match that jumper configuration.
1301 That includes in particular any oscillator or PLL used to clock
1302 the CPU, and any memory controllers needed to access external
1303 memory and peripherals. Without such handlers, you won't be
1304 able to access those resources without working target firmware
1305 which can do that setup ... this can be awkward when you're
1306 trying to debug that target firmware. Even if there's a ROM
1307 bootloader which handles a few issues, it rarely provides full
1308 access to all board-specific capabilities.
1311 @node Config File Guidelines
1312 @chapter Config File Guidelines
1314 This chapter is aimed at any user who needs to write a config file,
1315 including developers and integrators of OpenOCD and any user who
1316 needs to get a new board working smoothly.
1317 It provides guidelines for creating those files.
1319 You should find the following directories under
1320 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1321 them as-is where you can; or as models for new files.
1323 @item @file{interface} ...
1324 These are for debug adapters. Files that specify configuration to use
1325 specific JTAG, SWD and other adapters go here.
1326 @item @file{board} ...
1327 Think Circuit Board, PWA, PCB, they go by many names. Board files
1328 contain initialization items that are specific to a board.
1330 They reuse target configuration files, since the same
1331 microprocessor chips are used on many boards,
1332 but support for external parts varies widely. For
1333 example, the SDRAM initialization sequence for the board, or the type
1334 of external flash and what address it uses. Any initialization
1335 sequence to enable that external flash or SDRAM should be found in the
1336 board file. Boards may also contain multiple targets: two CPUs; or
1338 @item @file{target} ...
1339 Think chip. The ``target'' directory represents the JTAG TAPs
1341 which OpenOCD should control, not a board. Two common types of targets
1342 are ARM chips and FPGA or CPLD chips.
1343 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1344 the target config file defines all of them.
1345 @item @emph{more} ... browse for other library files which may be useful.
1346 For example, there are various generic and CPU-specific utilities.
1349 The @file{openocd.cfg} user config
1350 file may override features in any of the above files by
1351 setting variables before sourcing the target file, or by adding
1352 commands specific to their situation.
1354 @section Interface Config Files
1356 The user config file
1357 should be able to source one of these files with a command like this:
1360 source [find interface/FOOBAR.cfg]
1363 A preconfigured interface file should exist for every debug adapter
1364 in use today with OpenOCD.
1365 That said, perhaps some of these config files
1366 have only been used by the developer who created it.
1368 A separate chapter gives information about how to set these up.
1369 @xref{Debug Adapter Configuration}.
1370 Read the OpenOCD source code (and Developer's Guide)
1371 if you have a new kind of hardware interface
1372 and need to provide a driver for it.
1374 @deffn {Command} {find} 'filename'
1375 Prints full path to @var{filename} according to OpenOCD search rules.
1378 @deffn {Command} {ocd_find} 'filename'
1379 Prints full path to @var{filename} according to OpenOCD search rules. This
1380 is a low level function used by the @command{find}. Usually you want
1381 to use @command{find}, instead.
1384 @section Board Config Files
1385 @cindex config file, board
1386 @cindex board config file
1388 The user config file
1389 should be able to source one of these files with a command like this:
1392 source [find board/FOOBAR.cfg]
1395 The point of a board config file is to package everything
1396 about a given board that user config files need to know.
1397 In summary the board files should contain (if present)
1400 @item One or more @command{source [find target/...cfg]} statements
1401 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1402 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1403 @item Target @code{reset} handlers for SDRAM and I/O configuration
1404 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1405 @item All things that are not ``inside a chip''
1408 Generic things inside target chips belong in target config files,
1409 not board config files. So for example a @code{reset-init} event
1410 handler should know board-specific oscillator and PLL parameters,
1411 which it passes to target-specific utility code.
1413 The most complex task of a board config file is creating such a
1414 @code{reset-init} event handler.
1415 Define those handlers last, after you verify the rest of the board
1416 configuration works.
1418 @subsection Communication Between Config files
1420 In addition to target-specific utility code, another way that
1421 board and target config files communicate is by following a
1422 convention on how to use certain variables.
1424 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1425 Thus the rule we follow in OpenOCD is this: Variables that begin with
1426 a leading underscore are temporary in nature, and can be modified and
1427 used at will within a target configuration file.
1429 Complex board config files can do the things like this,
1430 for a board with three chips:
1433 # Chip #1: PXA270 for network side, big endian
1434 set CHIPNAME network
1436 source [find target/pxa270.cfg]
1437 # on return: _TARGETNAME = network.cpu
1438 # other commands can refer to the "network.cpu" target.
1439 $_TARGETNAME configure .... events for this CPU..
1441 # Chip #2: PXA270 for video side, little endian
1444 source [find target/pxa270.cfg]
1445 # on return: _TARGETNAME = video.cpu
1446 # other commands can refer to the "video.cpu" target.
1447 $_TARGETNAME configure .... events for this CPU..
1449 # Chip #3: Xilinx FPGA for glue logic
1452 source [find target/spartan3.cfg]
1455 That example is oversimplified because it doesn't show any flash memory,
1456 or the @code{reset-init} event handlers to initialize external DRAM
1457 or (assuming it needs it) load a configuration into the FPGA.
1458 Such features are usually needed for low-level work with many boards,
1459 where ``low level'' implies that the board initialization software may
1460 not be working. (That's a common reason to need JTAG tools. Another
1461 is to enable working with microcontroller-based systems, which often
1462 have no debugging support except a JTAG connector.)
1464 Target config files may also export utility functions to board and user
1465 config files. Such functions should use name prefixes, to help avoid
1468 Board files could also accept input variables from user config files.
1469 For example, there might be a @code{J4_JUMPER} setting used to identify
1470 what kind of flash memory a development board is using, or how to set
1471 up other clocks and peripherals.
1473 @subsection Variable Naming Convention
1474 @cindex variable names
1476 Most boards have only one instance of a chip.
1477 However, it should be easy to create a board with more than
1478 one such chip (as shown above).
1479 Accordingly, we encourage these conventions for naming
1480 variables associated with different @file{target.cfg} files,
1481 to promote consistency and
1482 so that board files can override target defaults.
1484 Inputs to target config files include:
1487 @item @code{CHIPNAME} ...
1488 This gives a name to the overall chip, and is used as part of
1489 tap identifier dotted names.
1490 While the default is normally provided by the chip manufacturer,
1491 board files may need to distinguish between instances of a chip.
1492 @item @code{ENDIAN} ...
1493 By default @option{little} - although chips may hard-wire @option{big}.
1494 Chips that can't change endianness don't need to use this variable.
1495 @item @code{CPUTAPID} ...
1496 When OpenOCD examines the JTAG chain, it can be told verify the
1497 chips against the JTAG IDCODE register.
1498 The target file will hold one or more defaults, but sometimes the
1499 chip in a board will use a different ID (perhaps a newer revision).
1502 Outputs from target config files include:
1505 @item @code{_TARGETNAME} ...
1506 By convention, this variable is created by the target configuration
1507 script. The board configuration file may make use of this variable to
1508 configure things like a ``reset init'' script, or other things
1509 specific to that board and that target.
1510 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1511 @code{_TARGETNAME1}, ... etc.
1514 @subsection The reset-init Event Handler
1515 @cindex event, reset-init
1516 @cindex reset-init handler
1518 Board config files run in the OpenOCD configuration stage;
1519 they can't use TAPs or targets, since they haven't been
1521 This means you can't write memory or access chip registers;
1522 you can't even verify that a flash chip is present.
1523 That's done later in event handlers, of which the target @code{reset-init}
1524 handler is one of the most important.
1526 Except on microcontrollers, the basic job of @code{reset-init} event
1527 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1528 Microcontrollers rarely use boot loaders; they run right out of their
1529 on-chip flash and SRAM memory. But they may want to use one of these
1530 handlers too, if just for developer convenience.
1533 Because this is so very board-specific, and chip-specific, no examples
1535 Instead, look at the board config files distributed with OpenOCD.
1536 If you have a boot loader, its source code will help; so will
1537 configuration files for other JTAG tools
1538 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1541 Some of this code could probably be shared between different boards.
1542 For example, setting up a DRAM controller often doesn't differ by
1543 much except the bus width (16 bits or 32?) and memory timings, so a
1544 reusable TCL procedure loaded by the @file{target.cfg} file might take
1545 those as parameters.
1546 Similarly with oscillator, PLL, and clock setup;
1547 and disabling the watchdog.
1548 Structure the code cleanly, and provide comments to help
1549 the next developer doing such work.
1550 (@emph{You might be that next person} trying to reuse init code!)
1552 The last thing normally done in a @code{reset-init} handler is probing
1553 whatever flash memory was configured. For most chips that needs to be
1554 done while the associated target is halted, either because JTAG memory
1555 access uses the CPU or to prevent conflicting CPU access.
1557 @subsection JTAG Clock Rate
1559 Before your @code{reset-init} handler has set up
1560 the PLLs and clocking, you may need to run with
1561 a low JTAG clock rate.
1562 @xref{jtagspeed,,JTAG Speed}.
1563 Then you'd increase that rate after your handler has
1564 made it possible to use the faster JTAG clock.
1565 When the initial low speed is board-specific, for example
1566 because it depends on a board-specific oscillator speed, then
1567 you should probably set it up in the board config file;
1568 if it's target-specific, it belongs in the target config file.
1570 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1571 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1572 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1573 Consult chip documentation to determine the peak JTAG clock rate,
1574 which might be less than that.
1577 On most ARMs, JTAG clock detection is coupled to the core clock, so
1578 software using a @option{wait for interrupt} operation blocks JTAG access.
1579 Adaptive clocking provides a partial workaround, but a more complete
1580 solution just avoids using that instruction with JTAG debuggers.
1583 If both the chip and the board support adaptive clocking,
1584 use the @command{jtag_rclk}
1585 command, in case your board is used with JTAG adapter which
1586 also supports it. Otherwise use @command{adapter speed}.
1587 Set the slow rate at the beginning of the reset sequence,
1588 and the faster rate as soon as the clocks are at full speed.
1590 @anchor{theinitboardprocedure}
1591 @subsection The init_board procedure
1592 @cindex init_board procedure
1594 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1595 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1596 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1597 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1598 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1599 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1600 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1601 Additionally ``linear'' board config file will most likely fail when target config file uses
1602 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1603 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1604 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1605 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1607 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1608 the original), allowing greater code reuse.
1611 ### board_file.cfg ###
1613 # source target file that does most of the config in init_targets
1614 source [find target/target.cfg]
1616 proc enable_fast_clock @{@} @{
1617 # enables fast on-board clock source
1618 # configures the chip to use it
1621 # initialize only board specifics - reset, clock, adapter frequency
1622 proc init_board @{@} @{
1623 reset_config trst_and_srst trst_pulls_srst
1625 $_TARGETNAME configure -event reset-start @{
1629 $_TARGETNAME configure -event reset-init @{
1636 @section Target Config Files
1637 @cindex config file, target
1638 @cindex target config file
1640 Board config files communicate with target config files using
1641 naming conventions as described above, and may source one or
1642 more target config files like this:
1645 source [find target/FOOBAR.cfg]
1648 The point of a target config file is to package everything
1649 about a given chip that board config files need to know.
1650 In summary the target files should contain
1654 @item Add TAPs to the scan chain
1655 @item Add CPU targets (includes GDB support)
1656 @item CPU/Chip/CPU-Core specific features
1660 As a rule of thumb, a target file sets up only one chip.
1661 For a microcontroller, that will often include a single TAP,
1662 which is a CPU needing a GDB target, and its on-chip flash.
1664 More complex chips may include multiple TAPs, and the target
1665 config file may need to define them all before OpenOCD
1666 can talk to the chip.
1667 For example, some phone chips have JTAG scan chains that include
1668 an ARM core for operating system use, a DSP,
1669 another ARM core embedded in an image processing engine,
1670 and other processing engines.
1672 @subsection Default Value Boiler Plate Code
1674 All target configuration files should start with code like this,
1675 letting board config files express environment-specific
1676 differences in how things should be set up.
1679 # Boards may override chip names, perhaps based on role,
1680 # but the default should match what the vendor uses
1681 if @{ [info exists CHIPNAME] @} @{
1682 set _CHIPNAME $CHIPNAME
1684 set _CHIPNAME sam7x256
1687 # ONLY use ENDIAN with targets that can change it.
1688 if @{ [info exists ENDIAN] @} @{
1694 # TAP identifiers may change as chips mature, for example with
1695 # new revision fields (the "3" here). Pick a good default; you
1696 # can pass several such identifiers to the "jtag newtap" command.
1697 if @{ [info exists CPUTAPID ] @} @{
1698 set _CPUTAPID $CPUTAPID
1700 set _CPUTAPID 0x3f0f0f0f
1703 @c but 0x3f0f0f0f is for an str73x part ...
1705 @emph{Remember:} Board config files may include multiple target
1706 config files, or the same target file multiple times
1707 (changing at least @code{CHIPNAME}).
1709 Likewise, the target configuration file should define
1710 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1711 use it later on when defining debug targets:
1714 set _TARGETNAME $_CHIPNAME.cpu
1715 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1718 @subsection Adding TAPs to the Scan Chain
1719 After the ``defaults'' are set up,
1720 add the TAPs on each chip to the JTAG scan chain.
1721 @xref{TAP Declaration}, and the naming convention
1724 In the simplest case the chip has only one TAP,
1725 probably for a CPU or FPGA.
1726 The config file for the Atmel AT91SAM7X256
1727 looks (in part) like this:
1730 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1733 A board with two such at91sam7 chips would be able
1734 to source such a config file twice, with different
1735 values for @code{CHIPNAME}, so
1736 it adds a different TAP each time.
1738 If there are nonzero @option{-expected-id} values,
1739 OpenOCD attempts to verify the actual tap id against those values.
1740 It will issue error messages if there is mismatch, which
1741 can help to pinpoint problems in OpenOCD configurations.
1744 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1745 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1746 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1747 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1748 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1751 There are more complex examples too, with chips that have
1752 multiple TAPs. Ones worth looking at include:
1755 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1756 plus a JRC to enable them
1757 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1758 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1759 is not currently used)
1762 @subsection Add CPU targets
1764 After adding a TAP for a CPU, you should set it up so that
1765 GDB and other commands can use it.
1766 @xref{CPU Configuration}.
1767 For the at91sam7 example above, the command can look like this;
1768 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1769 to little endian, and this chip doesn't support changing that.
1772 set _TARGETNAME $_CHIPNAME.cpu
1773 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1776 Work areas are small RAM areas associated with CPU targets.
1777 They are used by OpenOCD to speed up downloads,
1778 and to download small snippets of code to program flash chips.
1779 If the chip includes a form of ``on-chip-ram'' - and many do - define
1780 a work area if you can.
1781 Again using the at91sam7 as an example, this can look like:
1784 $_TARGETNAME configure -work-area-phys 0x00200000 \
1785 -work-area-size 0x4000 -work-area-backup 0
1788 @anchor{definecputargetsworkinginsmp}
1789 @subsection Define CPU targets working in SMP
1791 After setting targets, you can define a list of targets working in SMP.
1794 set _TARGETNAME_1 $_CHIPNAME.cpu1
1795 set _TARGETNAME_2 $_CHIPNAME.cpu2
1796 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1797 -coreid 0 -dbgbase $_DAP_DBG1
1798 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1799 -coreid 1 -dbgbase $_DAP_DBG2
1800 #define 2 targets working in smp.
1801 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1803 In the above example on cortex_a, 2 cpus are working in SMP.
1804 In SMP only one GDB instance is created and :
1806 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1807 @item halt command triggers the halt of all targets in the list.
1808 @item resume command triggers the write context and the restart of all targets in the list.
1809 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1810 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1811 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1814 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1815 command have been implemented.
1817 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1818 @item cortex_a smp off : disable SMP mode, the current target is the one
1819 displayed in the GDB session, only this target is now controlled by GDB
1820 session. This behaviour is useful during system boot up.
1821 @item cortex_a smp : display current SMP mode.
1822 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1829 #0 : coreid 0 is displayed to GDB ,
1830 #-> -1 : next resume triggers a real resume
1831 > cortex_a smp_gdb 1
1833 #0 :coreid 0 is displayed to GDB ,
1834 #->1 : next resume displays coreid 1 to GDB
1838 #1 :coreid 1 is displayed to GDB ,
1839 #->1 : next resume displays coreid 1 to GDB
1840 > cortex_a smp_gdb -1
1842 #1 :coreid 1 is displayed to GDB,
1843 #->-1 : next resume triggers a real resume
1847 @subsection Chip Reset Setup
1849 As a rule, you should put the @command{reset_config} command
1850 into the board file. Most things you think you know about a
1851 chip can be tweaked by the board.
1853 Some chips have specific ways the TRST and SRST signals are
1854 managed. In the unusual case that these are @emph{chip specific}
1855 and can never be changed by board wiring, they could go here.
1856 For example, some chips can't support JTAG debugging without
1859 Provide a @code{reset-assert} event handler if you can.
1860 Such a handler uses JTAG operations to reset the target,
1861 letting this target config be used in systems which don't
1862 provide the optional SRST signal, or on systems where you
1863 don't want to reset all targets at once.
1864 Such a handler might write to chip registers to force a reset,
1865 use a JRC to do that (preferable -- the target may be wedged!),
1866 or force a watchdog timer to trigger.
1867 (For Cortex-M targets, this is not necessary. The target
1868 driver knows how to use trigger an NVIC reset when SRST is
1871 Some chips need special attention during reset handling if
1872 they're going to be used with JTAG.
1873 An example might be needing to send some commands right
1874 after the target's TAP has been reset, providing a
1875 @code{reset-deassert-post} event handler that writes a chip
1876 register to report that JTAG debugging is being done.
1877 Another would be reconfiguring the watchdog so that it stops
1878 counting while the core is halted in the debugger.
1880 JTAG clocking constraints often change during reset, and in
1881 some cases target config files (rather than board config files)
1882 are the right places to handle some of those issues.
1883 For example, immediately after reset most chips run using a
1884 slower clock than they will use later.
1885 That means that after reset (and potentially, as OpenOCD
1886 first starts up) they must use a slower JTAG clock rate
1887 than they will use later.
1888 @xref{jtagspeed,,JTAG Speed}.
1890 @quotation Important
1891 When you are debugging code that runs right after chip
1892 reset, getting these issues right is critical.
1893 In particular, if you see intermittent failures when
1894 OpenOCD verifies the scan chain after reset,
1895 look at how you are setting up JTAG clocking.
1898 @anchor{theinittargetsprocedure}
1899 @subsection The init_targets procedure
1900 @cindex init_targets procedure
1902 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1903 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1904 procedure called @code{init_targets}, which will be executed when entering run stage
1905 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1906 Such procedure can be overridden by ``next level'' script (which sources the original).
1907 This concept facilitates code reuse when basic target config files provide generic configuration
1908 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1909 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1910 because sourcing them executes every initialization commands they provide.
1913 ### generic_file.cfg ###
1915 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1916 # basic initialization procedure ...
1919 proc init_targets @{@} @{
1920 # initializes generic chip with 4kB of flash and 1kB of RAM
1921 setup_my_chip MY_GENERIC_CHIP 4096 1024
1924 ### specific_file.cfg ###
1926 source [find target/generic_file.cfg]
1928 proc init_targets @{@} @{
1929 # initializes specific chip with 128kB of flash and 64kB of RAM
1930 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1934 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1935 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1937 For an example of this scheme see LPC2000 target config files.
1939 The @code{init_boards} procedure is a similar concept concerning board config files
1940 (@xref{theinitboardprocedure,,The init_board procedure}.)
1942 @anchor{theinittargeteventsprocedure}
1943 @subsection The init_target_events procedure
1944 @cindex init_target_events procedure
1946 A special procedure called @code{init_target_events} is run just after
1947 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1948 procedure}.) and before @code{init_board}
1949 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1950 to set up default target events for the targets that do not have those
1951 events already assigned.
1953 @subsection ARM Core Specific Hacks
1955 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1956 special high speed download features - enable it.
1958 If present, the MMU, the MPU and the CACHE should be disabled.
1960 Some ARM cores are equipped with trace support, which permits
1961 examination of the instruction and data bus activity. Trace
1962 activity is controlled through an ``Embedded Trace Module'' (ETM)
1963 on one of the core's scan chains. The ETM emits voluminous data
1964 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1965 If you are using an external trace port,
1966 configure it in your board config file.
1967 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1968 configure it in your target config file.
1971 etm config $_TARGETNAME 16 normal full etb
1972 etb config $_TARGETNAME $_CHIPNAME.etb
1975 @subsection Internal Flash Configuration
1977 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1979 @b{Never ever} in the ``target configuration file'' define any type of
1980 flash that is external to the chip. (For example a BOOT flash on
1981 Chip Select 0.) Such flash information goes in a board file - not
1982 the TARGET (chip) file.
1986 @item at91sam7x256 - has 256K flash YES enable it.
1987 @item str912 - has flash internal YES enable it.
1988 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1989 @item pxa270 - again - CS0 flash - it goes in the board file.
1992 @anchor{translatingconfigurationfiles}
1993 @section Translating Configuration Files
1995 If you have a configuration file for another hardware debugger
1996 or toolset (Abatron, BDI2000, BDI3000, CCS,
1997 Lauterbach, SEGGER, Macraigor, etc.), translating
1998 it into OpenOCD syntax is often quite straightforward. The most tricky
1999 part of creating a configuration script is oftentimes the reset init
2000 sequence where e.g. PLLs, DRAM and the like is set up.
2002 One trick that you can use when translating is to write small
2003 Tcl procedures to translate the syntax into OpenOCD syntax. This
2004 can avoid manual translation errors and make it easier to
2005 convert other scripts later on.
2007 Example of transforming quirky arguments to a simple search and
2011 # Lauterbach syntax(?)
2013 # Data.Set c15:0x042f %long 0x40000015
2015 # OpenOCD syntax when using procedure below.
2017 # setc15 0x01 0x00050078
2019 proc setc15 @{regs value@} @{
2022 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2024 arm mcr 15 [expr @{($regs >> 12) & 0x7@}] \
2025 [expr @{($regs >> 0) & 0xf@}] [expr @{($regs >> 4) & 0xf@}] \
2026 [expr @{($regs >> 8) & 0x7@}] $value
2032 @node Server Configuration
2033 @chapter Server Configuration
2034 @cindex initialization
2035 The commands here are commonly found in the openocd.cfg file and are
2036 used to specify what TCP/IP ports are used, and how GDB should be
2039 @anchor{configurationstage}
2040 @section Configuration Stage
2041 @cindex configuration stage
2042 @cindex config command
2044 When the OpenOCD server process starts up, it enters a
2045 @emph{configuration stage} which is the only time that
2046 certain commands, @emph{configuration commands}, may be issued.
2047 Normally, configuration commands are only available
2048 inside startup scripts.
2050 In this manual, the definition of a configuration command is
2051 presented as a @emph{Config Command}, not as a @emph{Command}
2052 which may be issued interactively.
2053 The runtime @command{help} command also highlights configuration
2054 commands, and those which may be issued at any time.
2056 Those configuration commands include declaration of TAPs,
2058 the interface used for JTAG communication,
2059 and other basic setup.
2060 The server must leave the configuration stage before it
2061 may access or activate TAPs.
2062 After it leaves this stage, configuration commands may no
2065 @deffn {Command} {command mode} [command_name]
2066 Returns the command modes allowed by a command: 'any', 'config', or
2067 'exec'. If no command is specified, returns the current command
2068 mode. Returns 'unknown' if an unknown command is given. Command can be
2069 multiple tokens. (command valid any time)
2071 In this document, the modes are described as stages, 'config' and
2072 'exec' mode correspond configuration stage and run stage. 'any' means
2073 the command can be executed in either
2074 stages. @xref{configurationstage,,Configuration Stage}, and
2075 @xref{enteringtherunstage,,Entering the Run Stage}.
2078 @anchor{enteringtherunstage}
2079 @section Entering the Run Stage
2081 The first thing OpenOCD does after leaving the configuration
2082 stage is to verify that it can talk to the scan chain
2083 (list of TAPs) which has been configured.
2084 It will warn if it doesn't find TAPs it expects to find,
2085 or finds TAPs that aren't supposed to be there.
2086 You should see no errors at this point.
2087 If you see errors, resolve them by correcting the
2088 commands you used to configure the server.
2089 Common errors include using an initial JTAG speed that's too
2090 fast, and not providing the right IDCODE values for the TAPs
2093 Once OpenOCD has entered the run stage, a number of commands
2095 A number of these relate to the debug targets you may have declared.
2096 For example, the @command{mww} command will not be available until
2097 a target has been successfully instantiated.
2098 If you want to use those commands, you may need to force
2099 entry to the run stage.
2101 @deffn {Config Command} {init}
2102 This command terminates the configuration stage and
2103 enters the run stage. This helps when you need to have
2104 the startup scripts manage tasks such as resetting the target,
2105 programming flash, etc. To reset the CPU upon startup, add "init" and
2106 "reset" at the end of the config script or at the end of the OpenOCD
2107 command line using the @option{-c} command line switch.
2109 If this command does not appear in any startup/configuration file
2110 OpenOCD executes the command for you after processing all
2111 configuration files and/or command line options.
2113 @b{NOTE:} This command normally occurs near the end of your
2114 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2115 targets ready. For example: If your openocd.cfg file needs to
2116 read/write memory on your target, @command{init} must occur before
2117 the memory read/write commands. This includes @command{nand probe}.
2119 @command{init} calls the following internal OpenOCD commands to initialize
2120 corresponding subsystems:
2121 @deffn {Config Command} {target init}
2122 @deffnx {Command} {transport init}
2123 @deffnx {Command} {dap init}
2124 @deffnx {Config Command} {flash init}
2125 @deffnx {Config Command} {nand init}
2126 @deffnx {Config Command} {pld init}
2127 @deffnx {Command} {tpiu init}
2130 At last, @command{init} executes all the commands that are specified in
2131 the TCL list @var{post_init_commands}. The commands are executed in the
2132 same order they occupy in the list. If one of the commands fails, then
2133 the error is propagated and OpenOCD fails too.
2135 lappend post_init_commands @{echo "OpenOCD successfully initialized."@}
2136 lappend post_init_commands @{echo "Have fun with OpenOCD !"@}
2140 @deffn {Config Command} {noinit}
2141 Prevent OpenOCD from implicit @command{init} call at the end of startup.
2142 Allows issuing configuration commands over telnet or Tcl connection.
2143 When you are done with configuration use @command{init} to enter
2147 @deffn {Overridable Procedure} {jtag_init}
2148 This is invoked at server startup to verify that it can talk
2149 to the scan chain (list of TAPs) which has been configured.
2151 The default implementation first tries @command{jtag arp_init},
2152 which uses only a lightweight JTAG reset before examining the
2154 If that fails, it tries again, using a harder reset
2155 from the overridable procedure @command{init_reset}.
2157 Implementations must have verified the JTAG scan chain before
2159 This is done by calling @command{jtag arp_init}
2160 (or @command{jtag arp_init-reset}).
2164 @section TCP/IP Ports
2169 The OpenOCD server accepts remote commands in several syntaxes.
2170 Each syntax uses a different TCP/IP port, which you may specify
2171 only during configuration (before those ports are opened).
2173 For reasons including security, you may wish to prevent remote
2174 access using one or more of these ports.
2175 In such cases, just specify the relevant port number as "disabled".
2176 If you disable all access through TCP/IP, you will need to
2177 use the command line @option{-pipe} option.
2180 @deffn {Config Command} {gdb_port} [number]
2182 Normally gdb listens to a TCP/IP port, but GDB can also
2183 communicate via pipes(stdin/out or named pipes). The name
2184 "gdb_port" stuck because it covers probably more than 90% of
2185 the normal use cases.
2187 No arguments reports GDB port. "pipe" means listen to stdin
2188 output to stdout, an integer is base port number, "disabled"
2189 disables the gdb server.
2191 When using "pipe", also use log_output to redirect the log
2192 output to a file so as not to flood the stdin/out pipes.
2194 Any other string is interpreted as named pipe to listen to.
2195 Output pipe is the same name as input pipe, but with 'o' appended,
2196 e.g. /var/gdb, /var/gdbo.
2198 The GDB port for the first target will be the base port, the
2199 second target will listen on gdb_port + 1, and so on.
2200 When not specified during the configuration stage,
2201 the port @var{number} defaults to 3333.
2202 When @var{number} is not a numeric value, incrementing it to compute
2203 the next port number does not work. In this case, specify the proper
2204 @var{number} for each target by using the option @code{-gdb-port} of the
2205 commands @command{target create} or @command{$target_name configure}.
2206 @xref{gdbportoverride,,option -gdb-port}.
2208 Note: when using "gdb_port pipe", increasing the default remote timeout in
2209 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2210 cause initialization to fail with "Unknown remote qXfer reply: OK".
2213 @deffn {Config Command} {tcl_port} [number]
2214 Specify or query the port used for a simplified RPC
2215 connection that can be used by clients to issue TCL commands and get the
2216 output from the Tcl engine.
2217 Intended as a machine interface.
2218 When not specified during the configuration stage,
2219 the port @var{number} defaults to 6666.
2220 When specified as "disabled", this service is not activated.
2223 @deffn {Config Command} {telnet_port} [number]
2224 Specify or query the
2225 port on which to listen for incoming telnet connections.
2226 This port is intended for interaction with one human through TCL commands.
2227 When not specified during the configuration stage,
2228 the port @var{number} defaults to 4444.
2229 When specified as "disabled", this service is not activated.
2232 @anchor{gdbconfiguration}
2233 @section GDB Configuration
2235 @cindex GDB configuration
2236 You can reconfigure some GDB behaviors if needed.
2237 The ones listed here are static and global.
2238 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2239 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2241 @anchor{gdbbreakpointoverride}
2242 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2243 Force breakpoint type for gdb @command{break} commands.
2244 This option supports GDB GUIs which don't
2245 distinguish hard versus soft breakpoints, if the default OpenOCD and
2246 GDB behaviour is not sufficient. GDB normally uses hardware
2247 breakpoints if the memory map has been set up for flash regions.
2250 @anchor{gdbflashprogram}
2251 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2252 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2253 vFlash packet is received.
2254 The default behaviour is @option{enable}.
2257 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2258 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2259 requested. GDB will then know when to set hardware breakpoints, and program flash
2260 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2261 for flash programming to work.
2262 Default behaviour is @option{enable}.
2263 @xref{gdbflashprogram,,gdb_flash_program}.
2266 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2267 Specifies whether data aborts cause an error to be reported
2268 by GDB memory read packets.
2269 The default behaviour is @option{disable};
2270 use @option{enable} see these errors reported.
2273 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2274 Specifies whether register accesses requested by GDB register read/write
2275 packets report errors or not.
2276 The default behaviour is @option{disable};
2277 use @option{enable} see these errors reported.
2280 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2281 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2282 The default behaviour is @option{enable}.
2285 @deffn {Command} {gdb_save_tdesc}
2286 Saves the target description file to the local file system.
2288 The file name is @i{target_name}.xml.
2291 @anchor{eventpolling}
2292 @section Event Polling
2294 Hardware debuggers are parts of asynchronous systems,
2295 where significant events can happen at any time.
2296 The OpenOCD server needs to detect some of these events,
2297 so it can report them to through TCL command line
2300 Examples of such events include:
2303 @item One of the targets can stop running ... maybe it triggers
2304 a code breakpoint or data watchpoint, or halts itself.
2305 @item Messages may be sent over ``debug message'' channels ... many
2306 targets support such messages sent over JTAG,
2307 for receipt by the person debugging or tools.
2308 @item Loss of power ... some adapters can detect these events.
2309 @item Resets not issued through JTAG ... such reset sources
2310 can include button presses or other system hardware, sometimes
2311 including the target itself (perhaps through a watchdog).
2312 @item Debug instrumentation sometimes supports event triggering
2313 such as ``trace buffer full'' (so it can quickly be emptied)
2314 or other signals (to correlate with code behavior).
2317 None of those events are signaled through standard JTAG signals.
2318 However, most conventions for JTAG connectors include voltage
2319 level and system reset (SRST) signal detection.
2320 Some connectors also include instrumentation signals, which
2321 can imply events when those signals are inputs.
2323 In general, OpenOCD needs to periodically check for those events,
2324 either by looking at the status of signals on the JTAG connector
2325 or by sending synchronous ``tell me your status'' JTAG requests
2326 to the various active targets.
2327 There is a command to manage and monitor that polling,
2328 which is normally done in the background.
2330 @deffn {Command} {poll} [@option{on}|@option{off}]
2331 Poll the current target for its current state.
2332 (Also, @pxref{targetcurstate,,target curstate}.)
2333 If that target is in debug mode, architecture
2334 specific information about the current state is printed.
2335 An optional parameter
2336 allows background polling to be enabled and disabled.
2338 You could use this from the TCL command shell, or
2339 from GDB using @command{monitor poll} command.
2340 Leave background polling enabled while you're using GDB.
2343 background polling: on
2344 target state: halted
2345 target halted in ARM state due to debug-request, \
2346 current mode: Supervisor
2347 cpsr: 0x800000d3 pc: 0x11081bfc
2348 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2353 @node Debug Adapter Configuration
2354 @chapter Debug Adapter Configuration
2355 @cindex config file, interface
2356 @cindex interface config file
2358 Correctly installing OpenOCD includes making your operating system give
2359 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2360 are used to select which one is used, and to configure how it is used.
2363 Because OpenOCD started out with a focus purely on JTAG, you may find
2364 places where it wrongly presumes JTAG is the only transport protocol
2365 in use. Be aware that recent versions of OpenOCD are removing that
2366 limitation. JTAG remains more functional than most other transports.
2367 Other transports do not support boundary scan operations, or may be
2368 specific to a given chip vendor. Some might be usable only for
2369 programming flash memory, instead of also for debugging.
2372 Debug Adapters/Interfaces/Dongles are normally configured
2373 through commands in an interface configuration
2374 file which is sourced by your @file{openocd.cfg} file, or
2375 through a command line @option{-f interface/....cfg} option.
2378 source [find interface/olimex-jtag-tiny.cfg]
2382 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2383 A few cases are so simple that you only need to say what driver to use:
2387 adapter driver jlink
2390 Most adapters need a bit more configuration than that.
2393 @section Adapter Configuration
2395 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2396 using. Depending on the type of adapter, you may need to use one or
2397 more additional commands to further identify or configure the adapter.
2399 @deffn {Config Command} {adapter driver} name
2400 Use the adapter driver @var{name} to connect to the
2404 @deffn {Command} {adapter list}
2405 List the debug adapter drivers that have been built into
2406 the running copy of OpenOCD.
2408 @deffn {Config Command} {adapter transports} transport_name+
2409 Specifies the transports supported by this debug adapter.
2410 The adapter driver builds-in similar knowledge; use this only
2411 when external configuration (such as jumpering) changes what
2412 the hardware can support.
2415 @anchor{adapter gpio}
2416 @deffn {Config Command} {adapter gpio [ @
2417 @option{tdo} | @option{tdi} | @option{tms} | @option{tck} | @option{trst} | @
2418 @option{swdio} | @option{swdio_dir} | @option{swclk} | @option{srst} | @
2421 gpio_number | @option{-chip} chip_number | @
2422 @option{-active-high} | @option{-active-low} | @
2423 @option{-push-pull} | @option{-open-drain} | @option{-open-source} | @
2424 @option{-pull-none} | @option{-pull-up} | @option{-pull-down} | @
2425 @option{-init-inactive} | @option{-init-active} | @option{-init-input} @
2428 Define the GPIO mapping that the adapter will use. The following signals can be
2432 @item @option{tdo}, @option{tdi}, @option{tms}, @option{tck}, @option{trst}:
2433 JTAG transport signals
2434 @item @option{swdio}, @option{swclk}: SWD transport signals
2435 @item @option{swdio_dir}: optional swdio buffer control signal
2436 @item @option{srst}: system reset signal
2437 @item @option{led}: optional activity led
2441 Some adapters require that the GPIO chip number is set in addition to the GPIO
2442 number. The configuration options enable signals to be defined as active-high or
2443 active-low. The output drive mode can be set to push-pull, open-drain or
2444 open-source. Most adapters will have to emulate open-drain or open-source drive
2445 modes by switching between an input and output. Input and output signals can be
2446 instructed to use a pull-up or pull-down resistor, assuming it is supported by
2447 the adaptor driver and hardware. The initial state of outputs may also be set,
2448 "active" state means 1 for active-high outputs and 0 for active-low outputs.
2449 Bidirectional signals may also be initialized as an input. If the swdio signal
2450 is buffered the buffer direction can be controlled with the swdio_dir signal;
2451 the active state means that the buffer should be set as an output with respect
2452 to the adapter. The command options are cumulative with later commands able to
2453 override settings defined by earlier ones. The two commands @command{gpio led 7
2454 -active-high} and @command{gpio led -chip 1 -active-low} sent sequentially are
2455 equivalent to issuing the single command @command{gpio led 7 -chip 1
2456 -active-low}. It is not permissible to set the drive mode or initial state for
2457 signals which are inputs. The drive mode for the srst and trst signals must be
2458 set with the @command{adapter reset_config} command. It is not permissible to
2459 set the initial state of swdio_dir as it is derived from the initial state of
2460 swdio. The command @command{adapter gpio} prints the current configuration for
2461 all GPIOs while the command @command{adapter gpio gpio_name} prints the current
2462 configuration for gpio_name. Not all adapters support this generic GPIO mapping,
2463 some require their own commands to define the GPIOs used. Adapters that support
2464 the generic mapping may not support all of the listed options.
2467 @deffn {Command} {adapter name}
2468 Returns the name of the debug adapter driver being used.
2471 @anchor{adapter_usb_location}
2472 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2473 Displays or specifies the physical USB port of the adapter to use. The path
2474 roots at @var{bus} and walks down the physical ports, with each
2475 @var{port} option specifying a deeper level in the bus topology, the last
2476 @var{port} denoting where the target adapter is actually plugged.
2477 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2479 This command is only available if your libusb1 is at least version 1.0.16.
2482 @deffn {Config Command} {adapter serial} serial_string
2483 Specifies the @var{serial_string} of the adapter to use.
2484 If this command is not specified, serial strings are not checked.
2485 Only the following adapter drivers use the serial string from this command:
2486 aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
2487 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
2490 @section Interface Drivers
2492 Each of the interface drivers listed here must be explicitly
2493 enabled when OpenOCD is configured, in order to be made
2494 available at run time.
2496 @deffn {Interface Driver} {amt_jtagaccel}
2497 Amontec Chameleon in its JTAG Accelerator configuration,
2498 connected to a PC's EPP mode parallel port.
2499 This defines some driver-specific commands:
2501 @deffn {Config Command} {parport port} number
2502 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2503 the number of the @file{/dev/parport} device.
2506 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2507 Displays status of RTCK option.
2508 Optionally sets that option first.
2512 @deffn {Interface Driver} {arm-jtag-ew}
2513 Olimex ARM-JTAG-EW USB adapter
2514 This has one driver-specific command:
2516 @deffn {Command} {armjtagew_info}
2521 @deffn {Interface Driver} {at91rm9200}
2522 Supports bitbanged JTAG from the local system,
2523 presuming that system is an Atmel AT91rm9200
2524 and a specific set of GPIOs is used.
2525 @c command: at91rm9200_device NAME
2526 @c chooses among list of bit configs ... only one option
2529 @deffn {Interface Driver} {cmsis-dap}
2530 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2533 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2534 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2535 the driver will attempt to auto detect the CMSIS-DAP device.
2536 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2538 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2542 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2543 Specifies how to communicate with the adapter:
2546 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2547 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2548 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2549 This is the default if @command{cmsis_dap_backend} is not specified.
2553 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2554 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2555 In most cases need not to be specified and interfaces are searched by
2556 interface string or for user class interface.
2559 @deffn {Command} {cmsis-dap info}
2560 Display various device information, like hardware version, firmware version, current bus status.
2563 @deffn {Command} {cmsis-dap cmd} number number ...
2564 Execute an arbitrary CMSIS-DAP command. Use for adapter testing or for handling
2565 of an adapter vendor specific command from a Tcl script.
2567 Take given numbers as bytes, assemble a CMSIS-DAP protocol command packet
2568 from them and send it to the adapter. The first 4 bytes of the adapter response
2570 See @url{https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Commands__gr.html}
2574 @deffn {Interface Driver} {dummy}
2575 A dummy software-only driver for debugging.
2578 @deffn {Interface Driver} {ep93xx}
2579 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2582 @deffn {Interface Driver} {ftdi}
2583 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2584 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2586 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2587 bypassing intermediate libraries like libftdi.
2589 Support for new FTDI based adapters can be added completely through
2590 configuration files, without the need to patch and rebuild OpenOCD.
2592 The driver uses a signal abstraction to enable Tcl configuration files to
2593 define outputs for one or several FTDI GPIO. These outputs can then be
2594 controlled using the @command{ftdi set_signal} command. Special signal names
2595 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2596 will be used for their customary purpose. Inputs can be read using the
2597 @command{ftdi get_signal} command.
2599 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2600 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2601 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2602 required by the protocol, to tell the adapter to drive the data output onto
2603 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2605 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2606 be controlled differently. In order to support tristateable signals such as
2607 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2608 signal. The following output buffer configurations are supported:
2611 @item Push-pull with one FTDI output as (non-)inverted data line
2612 @item Open drain with one FTDI output as (non-)inverted output-enable
2613 @item Tristate with one FTDI output as (non-)inverted data line and another
2614 FTDI output as (non-)inverted output-enable
2615 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2616 switching data and direction as necessary
2619 These interfaces have several commands, used to configure the driver
2620 before initializing the JTAG scan chain:
2622 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2623 The vendor ID and product ID of the adapter. Up to eight
2624 [@var{vid}, @var{pid}] pairs may be given, e.g.
2626 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2630 @deffn {Config Command} {ftdi device_desc} description
2631 Provides the USB device description (the @emph{iProduct string})
2632 of the adapter. If not specified, the device description is ignored
2633 during device selection.
2636 @deffn {Config Command} {ftdi channel} channel
2637 Selects the channel of the FTDI device to use for MPSSE operations. Most
2638 adapters use the default, channel 0, but there are exceptions.
2641 @deffn {Config Command} {ftdi layout_init} data direction
2642 Specifies the initial values of the FTDI GPIO data and direction registers.
2643 Each value is a 16-bit number corresponding to the concatenation of the high
2644 and low FTDI GPIO registers. The values should be selected based on the
2645 schematics of the adapter, such that all signals are set to safe levels with
2646 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2647 and initially asserted reset signals.
2650 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2651 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2652 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2653 register bitmasks to tell the driver the connection and type of the output
2654 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2655 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2656 used with inverting data inputs and @option{-data} with non-inverting inputs.
2657 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2658 not-output-enable) input to the output buffer is connected. The options
2659 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2660 with the method @command{ftdi get_signal}.
2662 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2663 simple open-collector transistor driver would be specified with @option{-oe}
2664 only. In that case the signal can only be set to drive low or to Hi-Z and the
2665 driver will complain if the signal is set to drive high. Which means that if
2666 it's a reset signal, @command{reset_config} must be specified as
2667 @option{srst_open_drain}, not @option{srst_push_pull}.
2669 A special case is provided when @option{-data} and @option{-oe} is set to the
2670 same bitmask. Then the FTDI pin is considered being connected straight to the
2671 target without any buffer. The FTDI pin is then switched between output and
2672 input as necessary to provide the full set of low, high and Hi-Z
2673 characteristics. In all other cases, the pins specified in a signal definition
2674 are always driven by the FTDI.
2676 If @option{-alias} or @option{-nalias} is used, the signal is created
2677 identical (or with data inverted) to an already specified signal
2681 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2682 Set a previously defined signal to the specified level.
2684 @item @option{0}, drive low
2685 @item @option{1}, drive high
2686 @item @option{z}, set to high-impedance
2690 @deffn {Command} {ftdi get_signal} name
2691 Get the value of a previously defined signal.
2694 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2695 Configure TCK edge at which the adapter samples the value of the TDO signal
2697 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2698 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2699 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2700 stability at higher JTAG clocks.
2702 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2703 @item @option{falling}, sample TDO on falling edge of TCK
2707 For example adapter definitions, see the configuration files shipped in the
2708 @file{interface/ftdi} directory.
2712 @deffn {Interface Driver} {ft232r}
2713 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2714 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2715 It currently doesn't support using CBUS pins as GPIO.
2717 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2724 @item DCD(10) - SRST
2727 User can change default pinout by supplying configuration
2728 commands with GPIO numbers or RS232 signal names.
2729 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2730 They differ from physical pin numbers.
2731 For details see actual FTDI chip datasheets.
2732 Every JTAG line must be configured to unique GPIO number
2733 different than any other JTAG line, even those lines
2734 that are sometimes not used like TRST or SRST.
2748 These interfaces have several commands, used to configure the driver
2749 before initializing the JTAG scan chain:
2751 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2752 The vendor ID and product ID of the adapter. If not specified, default
2753 0x0403:0x6001 is used.
2756 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2757 Set four JTAG GPIO numbers at once.
2758 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2761 @deffn {Config Command} {ft232r tck_num} @var{tck}
2762 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2765 @deffn {Config Command} {ft232r tms_num} @var{tms}
2766 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2769 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2770 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2773 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2774 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2777 @deffn {Config Command} {ft232r trst_num} @var{trst}
2778 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2781 @deffn {Config Command} {ft232r srst_num} @var{srst}
2782 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2785 @deffn {Config Command} {ft232r restore_serial} @var{word}
2786 Restore serial port after JTAG. This USB bitmode control word
2787 (16-bit) will be sent before quit. Lower byte should
2788 set GPIO direction register to a "sane" state:
2789 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2790 byte is usually 0 to disable bitbang mode.
2791 When kernel driver reattaches, serial port should continue to work.
2792 Value 0xFFFF disables sending control word and serial port,
2793 then kernel driver will not reattach.
2794 If not specified, default 0xFFFF is used.
2799 @deffn {Interface Driver} {remote_bitbang}
2800 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2801 with a remote process and sends ASCII encoded bitbang requests to that process
2802 instead of directly driving JTAG.
2804 The remote_bitbang driver is useful for debugging software running on
2805 processors which are being simulated.
2807 @deffn {Config Command} {remote_bitbang port} number
2808 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2809 sockets instead of TCP.
2812 @deffn {Config Command} {remote_bitbang host} hostname
2813 Specifies the hostname of the remote process to connect to using TCP, or the
2814 name of the UNIX socket to use if remote_bitbang port is 0.
2817 For example, to connect remotely via TCP to the host foobar you might have
2821 adapter driver remote_bitbang
2822 remote_bitbang port 3335
2823 remote_bitbang host foobar
2826 To connect to another process running locally via UNIX sockets with socket
2830 adapter driver remote_bitbang
2831 remote_bitbang port 0
2832 remote_bitbang host mysocket
2836 @deffn {Interface Driver} {usb_blaster}
2837 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2838 for FTDI chips. These interfaces have several commands, used to
2839 configure the driver before initializing the JTAG scan chain:
2841 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2842 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2843 default values are used.
2844 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2845 Altera USB-Blaster (default):
2847 usb_blaster vid_pid 0x09FB 0x6001
2849 The following VID/PID is for Kolja Waschk's USB JTAG:
2851 usb_blaster vid_pid 0x16C0 0x06AD
2855 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2856 Sets the state or function of the unused GPIO pins on USB-Blasters
2857 (pins 6 and 8 on the female JTAG header). These pins can be used as
2858 SRST and/or TRST provided the appropriate connections are made on the
2861 For example, to use pin 6 as SRST:
2863 usb_blaster pin pin6 s
2864 reset_config srst_only
2868 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2869 Chooses the low level access method for the adapter. If not specified,
2870 @option{ftdi} is selected unless it wasn't enabled during the
2871 configure stage. USB-Blaster II needs @option{ublast2}.
2874 @deffn {Config Command} {usb_blaster firmware} @var{path}
2875 This command specifies @var{path} to access USB-Blaster II firmware
2876 image. To be used with USB-Blaster II only.
2881 @deffn {Interface Driver} {gw16012}
2882 Gateworks GW16012 JTAG programmer.
2883 This has one driver-specific command:
2885 @deffn {Config Command} {parport port} [port_number]
2886 Display either the address of the I/O port
2887 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2888 If a parameter is provided, first switch to use that port.
2889 This is a write-once setting.
2893 @deffn {Interface Driver} {jlink}
2894 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2897 @quotation Compatibility Note
2898 SEGGER released many firmware versions for the many hardware versions they
2899 produced. OpenOCD was extensively tested and intended to run on all of them,
2900 but some combinations were reported as incompatible. As a general
2901 recommendation, it is advisable to use the latest firmware version
2902 available for each hardware version. However the current V8 is a moving
2903 target, and SEGGER firmware versions released after the OpenOCD was
2904 released may not be compatible. In such cases it is recommended to
2905 revert to the last known functional version. For 0.5.0, this is from
2906 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2907 version is from "May 3 2012 18:36:22", packed with 4.46f.
2910 @deffn {Command} {jlink hwstatus}
2911 Display various hardware related information, for example target voltage and pin
2914 @deffn {Command} {jlink freemem}
2915 Display free device internal memory.
2917 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2918 Set the JTAG command version to be used. Without argument, show the actual JTAG
2921 @deffn {Command} {jlink config}
2922 Display the device configuration.
2924 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2925 Set the target power state on JTAG-pin 19. Without argument, show the target
2928 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2929 Set the MAC address of the device. Without argument, show the MAC address.
2931 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2932 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2933 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2936 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2937 Set the USB address of the device. This will also change the USB Product ID
2938 (PID) of the device. Without argument, show the USB address.
2940 @deffn {Command} {jlink config reset}
2941 Reset the current configuration.
2943 @deffn {Command} {jlink config write}
2944 Write the current configuration to the internal persistent storage.
2946 @deffn {Command} {jlink emucom write} <channel> <data>
2947 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2950 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2951 the EMUCOM channel 0x10:
2953 > jlink emucom write 0x10 aa0b23
2956 @deffn {Command} {jlink emucom read} <channel> <length>
2957 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2960 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2962 > jlink emucom read 0x0 4
2966 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2967 Set the USB address of the interface, in case more than one adapter is connected
2968 to the host. If not specified, USB addresses are not considered. Device
2969 selection via USB address is not always unambiguous. It is recommended to use
2970 the serial number instead, if possible.
2972 As a configuration command, it can be used only before 'init'.
2976 @deffn {Interface Driver} {kitprog}
2977 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2978 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2979 families, but it is possible to use it with some other devices. If you are using
2980 this adapter with a PSoC or a PRoC, you may need to add
2981 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2982 configuration script.
2984 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2985 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2986 be used with this driver, and must either be used with the cmsis-dap driver or
2987 switched back to KitProg mode. See the Cypress KitProg User Guide for
2988 instructions on how to switch KitProg modes.
2992 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2994 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2995 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2996 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2997 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2998 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2999 SWD sequence must be sent after every target reset in order to re-establish
3000 communications with the target.
3001 @item Due in part to the limitation above, KitProg devices with firmware below
3002 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
3003 communicate with PSoC 5LP devices. This is because, assuming debug is not
3004 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
3005 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
3006 could only be sent with an acquisition sequence.
3009 @deffn {Config Command} {kitprog_init_acquire_psoc}
3010 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
3011 Please be aware that the acquisition sequence hard-resets the target.
3014 @deffn {Command} {kitprog acquire_psoc}
3015 Run a PSoC acquisition sequence immediately. Typically, this should not be used
3016 outside of the target-specific configuration scripts since it hard-resets the
3017 target as a side-effect.
3018 This is necessary for "reset halt" on some PSoC 4 series devices.
3021 @deffn {Command} {kitprog info}
3022 Display various adapter information, such as the hardware version, firmware
3023 version, and target voltage.
3027 @deffn {Interface Driver} {parport}
3028 Supports PC parallel port bit-banging cables:
3029 Wigglers, PLD download cable, and more.
3030 These interfaces have several commands, used to configure the driver
3031 before initializing the JTAG scan chain:
3033 @deffn {Config Command} {parport cable} name
3034 Set the layout of the parallel port cable used to connect to the target.
3035 This is a write-once setting.
3036 Currently valid cable @var{name} values include:
3039 @item @b{altium} Altium Universal JTAG cable.
3040 @item @b{arm-jtag} Same as original wiggler except SRST and
3041 TRST connections reversed and TRST is also inverted.
3042 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
3043 in configuration mode. This is only used to
3044 program the Chameleon itself, not a connected target.
3045 @item @b{dlc5} The Xilinx Parallel cable III.
3046 @item @b{flashlink} The ST Parallel cable.
3047 @item @b{lattice} Lattice ispDOWNLOAD Cable
3048 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
3050 Amontec's Chameleon Programmer. The new version available from
3051 the website uses the original Wiggler layout ('@var{wiggler}')
3052 @item @b{triton} The parallel port adapter found on the
3053 ``Karo Triton 1 Development Board''.
3054 This is also the layout used by the HollyGates design
3055 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
3056 @item @b{wiggler} The original Wiggler layout, also supported by
3057 several clones, such as the Olimex ARM-JTAG
3058 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
3059 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
3063 @deffn {Config Command} {parport port} [port_number]
3064 Display either the address of the I/O port
3065 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
3066 If a parameter is provided, first switch to use that port.
3067 This is a write-once setting.
3069 When using PPDEV to access the parallel port, use the number of the parallel port:
3070 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
3071 you may encounter a problem.
3074 @deffn {Config Command} {parport toggling_time} [nanoseconds]
3075 Displays how many nanoseconds the hardware needs to toggle TCK;
3076 the parport driver uses this value to obey the
3077 @command{adapter speed} configuration.
3078 When the optional @var{nanoseconds} parameter is given,
3079 that setting is changed before displaying the current value.
3081 The default setting should work reasonably well on commodity PC hardware.
3082 However, you may want to calibrate for your specific hardware.
3084 To measure the toggling time with a logic analyzer or a digital storage
3085 oscilloscope, follow the procedure below:
3087 > parport toggling_time 1000
3090 This sets the maximum JTAG clock speed of the hardware, but
3091 the actual speed probably deviates from the requested 500 kHz.
3092 Now, measure the time between the two closest spaced TCK transitions.
3093 You can use @command{runtest 1000} or something similar to generate a
3094 large set of samples.
3095 Update the setting to match your measurement:
3097 > parport toggling_time <measured nanoseconds>
3099 Now the clock speed will be a better match for @command{adapter speed}
3100 command given in OpenOCD scripts and event handlers.
3102 You can do something similar with many digital multimeters, but note
3103 that you'll probably need to run the clock continuously for several
3104 seconds before it decides what clock rate to show. Adjust the
3105 toggling time up or down until the measured clock rate is a good
3106 match with the rate you specified in the @command{adapter speed} command;
3111 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3112 This will configure the parallel driver to write a known
3113 cable-specific value to the parallel interface on exiting OpenOCD.
3116 For example, the interface configuration file for a
3117 classic ``Wiggler'' cable on LPT2 might look something like this:
3120 adapter driver parport
3122 parport cable wiggler
3126 @deffn {Interface Driver} {presto}
3127 ASIX PRESTO USB JTAG programmer.
3130 @deffn {Interface Driver} {rlink}
3131 Raisonance RLink USB adapter
3134 @deffn {Interface Driver} {usbprog}
3135 usbprog is a freely programmable USB adapter.
3138 @deffn {Interface Driver} {vsllink}
3139 vsllink is part of Versaloon which is a versatile USB programmer.
3142 This defines quite a few driver-specific commands,
3143 which are not currently documented here.
3147 @anchor{hla_interface}
3148 @deffn {Interface Driver} {hla}
3149 This is a driver that supports multiple High Level Adapters.
3150 This type of adapter does not expose some of the lower level api's
3151 that OpenOCD would normally use to access the target.
3153 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3154 and Nuvoton Nu-Link.
3155 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3156 versions of firmware where serial number is reset after first use. Suggest
3157 using ST firmware update utility to upgrade ST-LINK firmware even if current
3158 version reported is V2.J21.S4.
3160 @deffn {Config Command} {hla_device_desc} description
3161 Currently Not Supported.
3164 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3165 Specifies the adapter layout to use.
3168 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3169 Pairs of vendor IDs and product IDs of the device.
3172 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3173 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3174 'shared' mode using ST-Link TCP server (the default port is 7184).
3176 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3177 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3178 ST-LINK server software module}.
3181 @deffn {Command} {hla_command} command
3182 Execute a custom adapter-specific command. The @var{command} string is
3183 passed as is to the underlying adapter layout handler.
3187 @anchor{st_link_dap_interface}
3188 @deffn {Interface Driver} {st-link}
3189 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3190 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3191 directly access the arm ADIv5 DAP.
3193 The new API provide access to multiple AP on the same DAP, but the
3194 maximum number of the AP port is limited by the specific firmware version
3195 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3196 An error is returned for any AP number above the maximum allowed value.
3198 @emph{Note:} Either these same adapters and their older versions are
3199 also supported by @ref{hla_interface, the hla interface driver}.
3201 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3202 Choose between 'exclusive' USB communication (the default backend) or
3203 'shared' mode using ST-Link TCP server (the default port is 7184).
3205 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3206 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3207 ST-LINK server software module}.
3209 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3212 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3213 Pairs of vendor IDs and product IDs of the device.
3216 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3217 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3218 and receives @var{rx_n} bytes.
3220 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3221 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3222 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3223 the target's supply voltage.
3225 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3226 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3228 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3230 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3231 > set n [expr @{[lindex $a 4] + 256 * [lindex $a 5]@}]
3232 > set d [expr @{[lindex $a 0] + 256 * [lindex $a 1]@}]
3233 > echo [expr @{2 * 1.2 * $n / $d@}]
3239 @deffn {Interface Driver} {opendous}
3240 opendous-jtag is a freely programmable USB adapter.
3243 @deffn {Interface Driver} {ulink}
3244 This is the Keil ULINK v1 JTAG debugger.
3247 @deffn {Interface Driver} {xds110}
3248 The XDS110 is included as the embedded debug probe on many Texas Instruments
3249 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3250 debug probe with the added capability to supply power to the target board. The
3251 following commands are supported by the XDS110 driver:
3253 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3254 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3255 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3256 can be set to any value in the range 1800 to 3600 millivolts.
3259 @deffn {Command} {xds110 info}
3260 Displays information about the connected XDS110 debug probe (e.g. firmware
3265 @deffn {Interface Driver} {xlnx_pcie_xvc}
3266 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3267 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3268 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3269 exposed via extended capability registers in the PCI Express configuration space.
3271 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3273 @deffn {Config Command} {xlnx_pcie_xvc config} device
3274 Specifies the PCI Express device via parameter @var{device} to use.
3276 The correct value for @var{device} can be obtained by looking at the output
3277 of lscpi -D (first column) for the corresponding device.
3279 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3284 @deffn {Interface Driver} {bcm2835gpio}
3285 This SoC is present in Raspberry Pi which is a cheap single-board computer
3286 exposing some GPIOs on its expansion header.
3288 The driver accesses memory-mapped GPIO peripheral registers directly
3289 for maximum performance, but the only possible race condition is for
3290 the pins' modes/muxing (which is highly unlikely), so it should be
3291 able to coexist nicely with both sysfs bitbanging and various
3292 peripherals' kernel drivers. The driver restores the previous
3293 configuration on exit.
3295 GPIO numbers >= 32 can't be used for performance reasons.
3297 See @file{interface/raspberrypi-native.cfg} for a sample config and
3300 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3301 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3302 Must be specified to enable JTAG transport. These pins can also be specified
3306 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3307 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3308 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3311 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3312 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3313 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3316 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3317 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3318 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3321 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3322 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3323 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3326 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3327 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3328 specified to enable SWD transport. These pins can also be specified individually.
3331 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3332 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3333 specified using the configuration command @command{bcm2835gpio swd_nums}.
3336 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3337 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3338 specified using the configuration command @command{bcm2835gpio swd_nums}.
3341 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3342 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3343 to control the direction of an external buffer on the SWDIO pin (set=output
3344 mode, clear=input mode). If not specified, this feature is disabled.
3347 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3348 Set SRST GPIO number. Must be specified to enable SRST.
3351 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3352 Set TRST GPIO number. Must be specified to enable TRST.
3355 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3356 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3357 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3360 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3361 Set the peripheral base register address to access GPIOs. For the RPi1, use
3362 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3363 list can be found in the
3364 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3369 @deffn {Interface Driver} {imx_gpio}
3370 i.MX SoC is present in many community boards. Wandboard is an example
3371 of the one which is most popular.
3373 This driver is mostly the same as bcm2835gpio.
3375 See @file{interface/imx-native.cfg} for a sample config and
3381 @deffn {Interface Driver} {am335xgpio} The AM335x SoC is present in BeagleBone
3382 Black and BeagleBone Green single-board computers which expose some of the GPIOs
3383 on the two expansion headers.
3385 For maximum performance the driver accesses memory-mapped GPIO peripheral
3386 registers directly. The memory mapping requires read and write permission to
3387 kernel memory; if /dev/gpiomem exists it will be used, otherwise /dev/mem will
3388 be used. The driver restores the GPIO state on exit.
3390 All four GPIO ports are available. GPIO configuration is handled by the generic
3391 command @ref{adapter gpio, @command{adapter gpio}}.
3393 @deffn {Config Command} {am335xgpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3394 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified
3395 speed_coeff defaults to 600000 and speed_offset defaults to 575.
3398 See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
3403 @deffn {Interface Driver} {linuxgpiod}
3404 Linux provides userspace access to GPIO through libgpiod since Linux kernel
3405 version v4.6. The driver emulates either JTAG or SWD transport through
3406 bitbanging. There are no driver-specific commands, all GPIO configuration is
3407 handled by the generic command @ref{adapter gpio, @command{adapter gpio}}. This
3408 driver supports the resistor pull options provided by the @command{adapter gpio}
3409 command but the underlying hardware may not be able to support them.
3411 See @file{interface/dln-2-gpiod.cfg} for a sample configuration file.
3415 @deffn {Interface Driver} {sysfsgpio}
3416 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3417 Prefer using @b{linuxgpiod}, instead.
3419 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3423 @deffn {Interface Driver} {openjtag}
3424 OpenJTAG compatible USB adapter.
3425 This defines some driver-specific commands:
3427 @deffn {Config Command} {openjtag variant} variant
3428 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3429 Currently valid @var{variant} values include:
3432 @item @b{standard} Standard variant (default).
3433 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3434 (see @uref{http://www.cypress.com/?rID=82870}).
3438 @deffn {Config Command} {openjtag device_desc} string
3439 The USB device description string of the adapter.
3440 This value is only used with the standard variant.
3445 @deffn {Interface Driver} {vdebug}
3446 Cadence Virtual Debug Interface driver.
3448 @deffn {Config Command} {vdebug server} host:port
3449 Specifies the host and TCP port number where the vdebug server runs.
3452 @deffn {Config Command} {vdebug batching} value
3453 Specifies the batching method for the vdebug request. Possible values are
3455 1 or wr to batch write transactions together (default)
3456 2 or rw to batch both read and write transactions
3459 @deffn {Config Command} {vdebug polling} min max
3460 Takes two values, representing the polling interval in ms. Lower values mean faster
3461 debugger responsiveness, but lower emulation performance. The minimum should be
3462 around 10, maximum should not exceed 1000, which is the default gdb and keepalive
3466 @deffn {Config Command} {vdebug bfm_path} path clk_period
3467 Specifies the hierarchical path and input clk period of the vdebug BFM in the design.
3468 The hierarchical path uses Verilog notation top.inst.inst
3469 The clock period must include the unit, for instance 40ns.
3472 @deffn {Config Command} {vdebug mem_path} path base size
3473 Specifies the hierarchical path to the design memory instance for backdoor access.
3474 Up to 4 memories can be specified. The hierarchical path uses Verilog notation.
3475 The base specifies start address in the design address space, size its size in bytes.
3476 Both values can use hexadecimal notation with prefix 0x.
3480 @deffn {Interface Driver} {jtag_dpi}
3481 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3482 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3483 DPI server interface.
3485 @deffn {Config Command} {jtag_dpi set_port} port
3486 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3489 @deffn {Config Command} {jtag_dpi set_address} address
3490 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3495 @deffn {Interface Driver} {buspirate}
3497 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3498 It uses a simple data protocol over a serial port connection.
3500 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3501 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3503 @deffn {Config Command} {buspirate port} serial_port
3504 Specify the serial port's filename. For example:
3506 buspirate port /dev/ttyUSB0
3510 @deffn {Config Command} {buspirate speed} (normal|fast)
3511 Set the communication speed to 115k (normal) or 1M (fast). For example:
3513 buspirate speed normal
3517 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3518 Set the Bus Pirate output mode.
3520 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3521 @item In open drain mode, you will then need to enable the pull-ups.
3525 buspirate mode normal
3529 @deffn {Config Command} {buspirate pullup} (0|1)
3530 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3531 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3538 @deffn {Config Command} {buspirate vreg} (0|1)
3539 Whether to enable (1) or disable (0) the built-in voltage regulator,
3540 which can be used to supply power to a test circuit through
3541 I/O header pins +3V3 and +5V. For example:
3547 @deffn {Command} {buspirate led} (0|1)
3548 Turns the Bus Pirate's LED on (1) or off (0). For example:
3556 @deffn {Interface Driver} {esp_usb_jtag}
3557 Espressif JTAG driver to communicate with ESP32-C3, ESP32-S3 chips and ESP USB Bridge board using OpenOCD.
3558 These chips have built-in JTAG circuitry and can be debugged without any additional hardware.
3559 Only an USB cable connected to the D+/D- pins is necessary.
3561 @deffn {Config Command} {espusbjtag tdo}
3562 Returns the current state of the TDO line
3565 @deffn {Config Command} {espusbjtag setio} setio
3566 Manually set the status of the output lines with the order of (tdi tms tck trst srst)
3568 espusbjtag setio 0 1 0 1 0
3572 @deffn {Config Command} {espusbjtag vid_pid} vid_pid
3573 Set vendor ID and product ID for the ESP usb jtag driver
3575 espusbjtag vid_pid 0x303a 0x1001
3579 @deffn {Config Command} {espusbjtag caps_descriptor} caps_descriptor
3580 Set the jtag descriptor to read capabilities of ESP usb jtag driver
3582 espusbjtag caps_descriptor 0x2000
3586 @deffn {Config Command} {espusbjtag chip_id} chip_id
3587 Set chip id to transfer to the ESP USB bridge board
3589 espusbjtag chip_id 1
3595 @section Transport Configuration
3597 As noted earlier, depending on the version of OpenOCD you use,
3598 and the debug adapter you are using,
3599 several transports may be available to
3600 communicate with debug targets (or perhaps to program flash memory).
3601 @deffn {Command} {transport list}
3602 displays the names of the transports supported by this
3606 @deffn {Command} {transport select} @option{transport_name}
3607 Select which of the supported transports to use in this OpenOCD session.
3609 When invoked with @option{transport_name}, attempts to select the named
3610 transport. The transport must be supported by the debug adapter
3611 hardware and by the version of OpenOCD you are using (including the
3614 If no transport has been selected and no @option{transport_name} is
3615 provided, @command{transport select} auto-selects the first transport
3616 supported by the debug adapter.
3618 @command{transport select} always returns the name of the session's selected
3622 @subsection JTAG Transport
3624 JTAG is the original transport supported by OpenOCD, and most
3625 of the OpenOCD commands support it.
3626 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3627 each of which must be explicitly declared.
3628 JTAG supports both debugging and boundary scan testing.
3629 Flash programming support is built on top of debug support.
3631 JTAG transport is selected with the command @command{transport select
3632 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3633 driver} (in which case the command is @command{transport select hla_jtag})
3634 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3635 the command is @command{transport select dapdirect_jtag}).
3637 @subsection SWD Transport
3639 @cindex Serial Wire Debug
3640 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3641 Debug Access Point (DAP, which must be explicitly declared.
3642 (SWD uses fewer signal wires than JTAG.)
3643 SWD is debug-oriented, and does not support boundary scan testing.
3644 Flash programming support is built on top of debug support.
3645 (Some processors support both JTAG and SWD.)
3647 SWD transport is selected with the command @command{transport select
3648 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3649 driver} (in which case the command is @command{transport select hla_swd})
3650 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3651 the command is @command{transport select dapdirect_swd}).
3653 @deffn {Config Command} {swd newdap} ...
3654 Declares a single DAP which uses SWD transport.
3655 Parameters are currently the same as "jtag newtap" but this is
3659 @cindex SWD multi-drop
3660 The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop extension
3661 of SWD protocol: two or more devices can be connected to one SWD adapter.
3662 SWD transport works in multi-drop mode if @ref{dap_create,DAP} is configured
3663 with both @code{-dp-id} and @code{-instance-id} parameters regardless how many
3666 Not all adapters and adapter drivers support SWD multi-drop. Only the following
3667 adapter drivers are SWD multi-drop capable:
3668 cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
3670 @subsection SPI Transport
3672 @cindex Serial Peripheral Interface
3673 The Serial Peripheral Interface (SPI) is a general purpose transport
3674 which uses four wire signaling. Some processors use it as part of a
3675 solution for flash programming.
3677 @anchor{swimtransport}
3678 @subsection SWIM Transport
3680 @cindex Single Wire Interface Module
3681 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3682 by the STMicroelectronics MCU family STM8 and documented in the
3683 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3685 SWIM does not support boundary scan testing nor multiple cores.
3687 The SWIM transport is selected with the command @command{transport select swim}.
3689 The concept of TAPs does not fit in the protocol since SWIM does not implement
3690 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3691 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3692 The TAP definition must precede the target definition command
3693 @command{target create target_name stm8 -chain-position basename.tap_type}.
3697 JTAG clock setup is part of system setup.
3698 It @emph{does not belong with interface setup} since any interface
3699 only knows a few of the constraints for the JTAG clock speed.
3700 Sometimes the JTAG speed is
3701 changed during the target initialization process: (1) slow at
3702 reset, (2) program the CPU clocks, (3) run fast.
3703 Both the "slow" and "fast" clock rates are functions of the
3704 oscillators used, the chip, the board design, and sometimes
3705 power management software that may be active.
3707 The speed used during reset, and the scan chain verification which
3708 follows reset, can be adjusted using a @code{reset-start}
3709 target event handler.
3710 It can then be reconfigured to a faster speed by a
3711 @code{reset-init} target event handler after it reprograms those
3712 CPU clocks, or manually (if something else, such as a boot loader,
3713 sets up those clocks).
3714 @xref{targetevents,,Target Events}.
3715 When the initial low JTAG speed is a chip characteristic, perhaps
3716 because of a required oscillator speed, provide such a handler
3717 in the target config file.
3718 When that speed is a function of a board-specific characteristic
3719 such as which speed oscillator is used, it belongs in the board
3720 config file instead.
3721 In both cases it's safest to also set the initial JTAG clock rate
3722 to that same slow speed, so that OpenOCD never starts up using a
3723 clock speed that's faster than the scan chain can support.
3727 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3730 If your system supports adaptive clocking (RTCK), configuring
3731 JTAG to use that is probably the most robust approach.
3732 However, it introduces delays to synchronize clocks; so it
3733 may not be the fastest solution.
3735 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3736 instead of @command{adapter speed}, but only for (ARM) cores and boards
3737 which support adaptive clocking.
3739 @deffn {Command} {adapter speed} max_speed_kHz
3740 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3741 JTAG interfaces usually support a limited number of
3742 speeds. The speed actually used won't be faster
3743 than the speed specified.
3745 Chip data sheets generally include a top JTAG clock rate.
3746 The actual rate is often a function of a CPU core clock,
3747 and is normally less than that peak rate.
3748 For example, most ARM cores accept at most one sixth of the CPU clock.
3750 Speed 0 (khz) selects RTCK method.
3751 @xref{faqrtck,,FAQ RTCK}.
3752 If your system uses RTCK, you won't need to change the
3753 JTAG clocking after setup.
3754 Not all interfaces, boards, or targets support ``rtck''.
3755 If the interface device can not
3756 support it, an error is returned when you try to use RTCK.
3759 @defun jtag_rclk fallback_speed_kHz
3760 @cindex adaptive clocking
3762 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3763 If that fails (maybe the interface, board, or target doesn't
3764 support it), falls back to the specified frequency.
3766 # Fall back to 3mhz if RTCK is not supported
3771 @node Reset Configuration
3772 @chapter Reset Configuration
3773 @cindex Reset Configuration
3775 Every system configuration may require a different reset
3776 configuration. This can also be quite confusing.
3777 Resets also interact with @var{reset-init} event handlers,
3778 which do things like setting up clocks and DRAM, and
3779 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3780 They can also interact with JTAG routers.
3781 Please see the various board files for examples.
3784 To maintainers and integrators:
3785 Reset configuration touches several things at once.
3786 Normally the board configuration file
3787 should define it and assume that the JTAG adapter supports
3788 everything that's wired up to the board's JTAG connector.
3790 However, the target configuration file could also make note
3791 of something the silicon vendor has done inside the chip,
3792 which will be true for most (or all) boards using that chip.
3793 And when the JTAG adapter doesn't support everything, the
3794 user configuration file will need to override parts of
3795 the reset configuration provided by other files.
3798 @section Types of Reset
3800 There are many kinds of reset possible through JTAG, but
3801 they may not all work with a given board and adapter.
3802 That's part of why reset configuration can be error prone.
3806 @emph{System Reset} ... the @emph{SRST} hardware signal
3807 resets all chips connected to the JTAG adapter, such as processors,
3808 power management chips, and I/O controllers. Normally resets triggered
3809 with this signal behave exactly like pressing a RESET button.
3811 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3812 just the TAP controllers connected to the JTAG adapter.
3813 Such resets should not be visible to the rest of the system; resetting a
3814 device's TAP controller just puts that controller into a known state.
3816 @emph{Emulation Reset} ... many devices can be reset through JTAG
3817 commands. These resets are often distinguishable from system
3818 resets, either explicitly (a "reset reason" register says so)
3819 or implicitly (not all parts of the chip get reset).
3821 @emph{Other Resets} ... system-on-chip devices often support
3822 several other types of reset.
3823 You may need to arrange that a watchdog timer stops
3824 while debugging, preventing a watchdog reset.
3825 There may be individual module resets.
3828 In the best case, OpenOCD can hold SRST, then reset
3829 the TAPs via TRST and send commands through JTAG to halt the
3830 CPU at the reset vector before the 1st instruction is executed.
3831 Then when it finally releases the SRST signal, the system is
3832 halted under debugger control before any code has executed.
3833 This is the behavior required to support the @command{reset halt}
3834 and @command{reset init} commands; after @command{reset init} a
3835 board-specific script might do things like setting up DRAM.
3836 (@xref{resetcommand,,Reset Command}.)
3838 @anchor{srstandtrstissues}
3839 @section SRST and TRST Issues
3841 Because SRST and TRST are hardware signals, they can have a
3842 variety of system-specific constraints. Some of the most
3847 @item @emph{Signal not available} ... Some boards don't wire
3848 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3849 support such signals even if they are wired up.
3850 Use the @command{reset_config} @var{signals} options to say
3851 when either of those signals is not connected.
3852 When SRST is not available, your code might not be able to rely
3853 on controllers having been fully reset during code startup.
3854 Missing TRST is not a problem, since JTAG-level resets can
3855 be triggered using with TMS signaling.
3857 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3858 adapter will connect SRST to TRST, instead of keeping them separate.
3859 Use the @command{reset_config} @var{combination} options to say
3860 when those signals aren't properly independent.
3862 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3863 delay circuit, reset supervisor, or on-chip features can extend
3864 the effect of a JTAG adapter's reset for some time after the adapter
3865 stops issuing the reset. For example, there may be chip or board
3866 requirements that all reset pulses last for at least a
3867 certain amount of time; and reset buttons commonly have
3868 hardware debouncing.
3869 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3870 commands to say when extra delays are needed.
3872 @item @emph{Drive type} ... Reset lines often have a pullup
3873 resistor, letting the JTAG interface treat them as open-drain
3874 signals. But that's not a requirement, so the adapter may need
3875 to use push/pull output drivers.
3876 Also, with weak pullups it may be advisable to drive
3877 signals to both levels (push/pull) to minimize rise times.
3878 Use the @command{reset_config} @var{trst_type} and
3879 @var{srst_type} parameters to say how to drive reset signals.
3881 @item @emph{Special initialization} ... Targets sometimes need
3882 special JTAG initialization sequences to handle chip-specific
3883 issues (not limited to errata).
3884 For example, certain JTAG commands might need to be issued while
3885 the system as a whole is in a reset state (SRST active)
3886 but the JTAG scan chain is usable (TRST inactive).
3887 Many systems treat combined assertion of SRST and TRST as a
3888 trigger for a harder reset than SRST alone.
3889 Such custom reset handling is discussed later in this chapter.
3892 There can also be other issues.
3893 Some devices don't fully conform to the JTAG specifications.
3894 Trivial system-specific differences are common, such as
3895 SRST and TRST using slightly different names.
3896 There are also vendors who distribute key JTAG documentation for
3897 their chips only to developers who have signed a Non-Disclosure
3900 Sometimes there are chip-specific extensions like a requirement to use
3901 the normally-optional TRST signal (precluding use of JTAG adapters which
3902 don't pass TRST through), or needing extra steps to complete a TAP reset.
3904 In short, SRST and especially TRST handling may be very finicky,
3905 needing to cope with both architecture and board specific constraints.
3907 @section Commands for Handling Resets
3909 @deffn {Command} {adapter srst pulse_width} milliseconds
3910 Minimum amount of time (in milliseconds) OpenOCD should wait
3911 after asserting nSRST (active-low system reset) before
3912 allowing it to be deasserted.
3915 @deffn {Command} {adapter srst delay} milliseconds
3916 How long (in milliseconds) OpenOCD should wait after deasserting
3917 nSRST (active-low system reset) before starting new JTAG operations.
3918 When a board has a reset button connected to SRST line it will
3919 probably have hardware debouncing, implying you should use this.
3922 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
3923 Minimum amount of time (in milliseconds) OpenOCD should wait
3924 after asserting nTRST (active-low JTAG TAP reset) before
3925 allowing it to be deasserted.
3928 @deffn {Command} {jtag_ntrst_delay} milliseconds
3929 How long (in milliseconds) OpenOCD should wait after deasserting
3930 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3933 @anchor{reset_config}
3934 @deffn {Command} {reset_config} mode_flag ...
3935 This command displays or modifies the reset configuration
3936 of your combination of JTAG board and target in target
3937 configuration scripts.
3939 Information earlier in this section describes the kind of problems
3940 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3941 As a rule this command belongs only in board config files,
3942 describing issues like @emph{board doesn't connect TRST};
3943 or in user config files, addressing limitations derived
3944 from a particular combination of interface and board.
3945 (An unlikely example would be using a TRST-only adapter
3946 with a board that only wires up SRST.)
3948 The @var{mode_flag} options can be specified in any order, but only one
3949 of each type -- @var{signals}, @var{combination}, @var{gates},
3950 @var{trst_type}, @var{srst_type} and @var{connect_type}
3951 -- may be specified at a time.
3952 If you don't provide a new value for a given type, its previous
3953 value (perhaps the default) is unchanged.
3954 For example, this means that you don't need to say anything at all about
3955 TRST just to declare that if the JTAG adapter should want to drive SRST,
3956 it must explicitly be driven high (@option{srst_push_pull}).
3960 @var{signals} can specify which of the reset signals are connected.
3961 For example, If the JTAG interface provides SRST, but the board doesn't
3962 connect that signal properly, then OpenOCD can't use it.
3963 Possible values are @option{none} (the default), @option{trst_only},
3964 @option{srst_only} and @option{trst_and_srst}.
3967 If your board provides SRST and/or TRST through the JTAG connector,
3968 you must declare that so those signals can be used.
3972 The @var{combination} is an optional value specifying broken reset
3973 signal implementations.
3974 The default behaviour if no option given is @option{separate},
3975 indicating everything behaves normally.
3976 @option{srst_pulls_trst} states that the
3977 test logic is reset together with the reset of the system (e.g. NXP
3978 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3979 the system is reset together with the test logic (only hypothetical, I
3980 haven't seen hardware with such a bug, and can be worked around).
3981 @option{combined} implies both @option{srst_pulls_trst} and
3982 @option{trst_pulls_srst}.
3985 The @var{gates} tokens control flags that describe some cases where
3986 JTAG may be unavailable during reset.
3987 @option{srst_gates_jtag} (default)
3988 indicates that asserting SRST gates the
3989 JTAG clock. This means that no communication can happen on JTAG
3990 while SRST is asserted.
3991 Its converse is @option{srst_nogate}, indicating that JTAG commands
3992 can safely be issued while SRST is active.
3995 The @var{connect_type} tokens control flags that describe some cases where
3996 SRST is asserted while connecting to the target. @option{srst_nogate}
3997 is required to use this option.
3998 @option{connect_deassert_srst} (default)
3999 indicates that SRST will not be asserted while connecting to the target.
4000 Its converse is @option{connect_assert_srst}, indicating that SRST will
4001 be asserted before any target connection.
4002 Only some targets support this feature, STM32 and STR9 are examples.
4003 This feature is useful if you are unable to connect to your target due
4004 to incorrect options byte config or illegal program execution.
4007 The optional @var{trst_type} and @var{srst_type} parameters allow the
4008 driver mode of each reset line to be specified. These values only affect
4009 JTAG interfaces with support for different driver modes, like the Amontec
4010 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
4011 relevant signal (TRST or SRST) is not connected.
4015 Possible @var{trst_type} driver modes for the test reset signal (TRST)
4016 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
4017 Most boards connect this signal to a pulldown, so the JTAG TAPs
4018 never leave reset unless they are hooked up to a JTAG adapter.
4021 Possible @var{srst_type} driver modes for the system reset signal (SRST)
4022 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
4023 Most boards connect this signal to a pullup, and allow the
4024 signal to be pulled low by various events including system
4025 power-up and pressing a reset button.
4029 @section Custom Reset Handling
4032 OpenOCD has several ways to help support the various reset
4033 mechanisms provided by chip and board vendors.
4034 The commands shown in the previous section give standard parameters.
4035 There are also @emph{event handlers} associated with TAPs or Targets.
4036 Those handlers are Tcl procedures you can provide, which are invoked
4037 at particular points in the reset sequence.
4039 @emph{When SRST is not an option} you must set
4040 up a @code{reset-assert} event handler for your target.
4041 For example, some JTAG adapters don't include the SRST signal;
4042 and some boards have multiple targets, and you won't always
4043 want to reset everything at once.
4045 After configuring those mechanisms, you might still
4046 find your board doesn't start up or reset correctly.
4047 For example, maybe it needs a slightly different sequence
4048 of SRST and/or TRST manipulations, because of quirks that
4049 the @command{reset_config} mechanism doesn't address;
4050 or asserting both might trigger a stronger reset, which
4051 needs special attention.
4053 Experiment with lower level operations, such as
4054 @command{adapter assert}, @command{adapter deassert}
4055 and the @command{jtag arp_*} operations shown here,
4056 to find a sequence of operations that works.
4057 @xref{JTAG Commands}.
4058 When you find a working sequence, it can be used to override
4059 @command{jtag_init}, which fires during OpenOCD startup
4060 (@pxref{configurationstage,,Configuration Stage});
4061 or @command{init_reset}, which fires during reset processing.
4063 You might also want to provide some project-specific reset
4064 schemes. For example, on a multi-target board the standard
4065 @command{reset} command would reset all targets, but you
4066 may need the ability to reset only one target at time and
4067 thus want to avoid using the board-wide SRST signal.
4069 @deffn {Overridable Procedure} {init_reset} mode
4070 This is invoked near the beginning of the @command{reset} command,
4071 usually to provide as much of a cold (power-up) reset as practical.
4072 By default it is also invoked from @command{jtag_init} if
4073 the scan chain does not respond to pure JTAG operations.
4074 The @var{mode} parameter is the parameter given to the
4075 low level reset command (@option{halt},
4076 @option{init}, or @option{run}), @option{setup},
4077 or potentially some other value.
4079 The default implementation just invokes @command{jtag arp_init-reset}.
4080 Replacements will normally build on low level JTAG
4081 operations such as @command{adapter assert} and @command{adapter deassert}.
4082 Operations here must not address individual TAPs
4083 (or their associated targets)
4084 until the JTAG scan chain has first been verified to work.
4086 Implementations must have verified the JTAG scan chain before
4088 This is done by calling @command{jtag arp_init}
4089 (or @command{jtag arp_init-reset}).
4092 @deffn {Command} {jtag arp_init}
4093 This validates the scan chain using just the four
4094 standard JTAG signals (TMS, TCK, TDI, TDO).
4095 It starts by issuing a JTAG-only reset.
4096 Then it performs checks to verify that the scan chain configuration
4097 matches the TAPs it can observe.
4098 Those checks include checking IDCODE values for each active TAP,
4099 and verifying the length of their instruction registers using
4100 TAP @code{-ircapture} and @code{-irmask} values.
4101 If these tests all pass, TAP @code{setup} events are
4102 issued to all TAPs with handlers for that event.
4105 @deffn {Command} {jtag arp_init-reset}
4106 This uses TRST and SRST to try resetting
4107 everything on the JTAG scan chain
4108 (and anything else connected to SRST).
4109 It then invokes the logic of @command{jtag arp_init}.
4113 @node TAP Declaration
4114 @chapter TAP Declaration
4115 @cindex TAP declaration
4116 @cindex TAP configuration
4118 @emph{Test Access Ports} (TAPs) are the core of JTAG.
4119 TAPs serve many roles, including:
4122 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
4123 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
4124 Others do it indirectly, making a CPU do it.
4125 @item @b{Program Download} Using the same CPU support GDB uses,
4126 you can initialize a DRAM controller, download code to DRAM, and then
4127 start running that code.
4128 @item @b{Boundary Scan} Most chips support boundary scan, which
4129 helps test for board assembly problems like solder bridges
4130 and missing connections.
4133 OpenOCD must know about the active TAPs on your board(s).
4134 Setting up the TAPs is the core task of your configuration files.
4135 Once those TAPs are set up, you can pass their names to code
4136 which sets up CPUs and exports them as GDB targets,
4137 probes flash memory, performs low-level JTAG operations, and more.
4139 @section Scan Chains
4142 TAPs are part of a hardware @dfn{scan chain},
4143 which is a daisy chain of TAPs.
4144 They also need to be added to
4145 OpenOCD's software mirror of that hardware list,
4146 giving each member a name and associating other data with it.
4147 Simple scan chains, with a single TAP, are common in
4148 systems with a single microcontroller or microprocessor.
4149 More complex chips may have several TAPs internally.
4150 Very complex scan chains might have a dozen or more TAPs:
4151 several in one chip, more in the next, and connecting
4152 to other boards with their own chips and TAPs.
4154 You can display the list with the @command{scan_chain} command.
4155 (Don't confuse this with the list displayed by the @command{targets}
4156 command, presented in the next chapter.
4157 That only displays TAPs for CPUs which are configured as
4159 Here's what the scan chain might look like for a chip more than one TAP:
4162 TapName Enabled IdCode Expected IrLen IrCap IrMask
4163 -- ------------------ ------- ---------- ---------- ----- ----- ------
4164 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
4165 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
4166 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
4169 OpenOCD can detect some of that information, but not all
4170 of it. @xref{autoprobing,,Autoprobing}.
4171 Unfortunately, those TAPs can't always be autoconfigured,
4172 because not all devices provide good support for that.
4173 JTAG doesn't require supporting IDCODE instructions, and
4174 chips with JTAG routers may not link TAPs into the chain
4175 until they are told to do so.
4177 The configuration mechanism currently supported by OpenOCD
4178 requires explicit configuration of all TAP devices using
4179 @command{jtag newtap} commands, as detailed later in this chapter.
4180 A command like this would declare one tap and name it @code{chip1.cpu}:
4183 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
4186 Each target configuration file lists the TAPs provided
4188 Board configuration files combine all the targets on a board,
4190 Note that @emph{the order in which TAPs are declared is very important.}
4191 That declaration order must match the order in the JTAG scan chain,
4192 both inside a single chip and between them.
4193 @xref{faqtaporder,,FAQ TAP Order}.
4195 For example, the STMicroelectronics STR912 chip has
4196 three separate TAPs@footnote{See the ST
4197 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
4198 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
4199 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
4200 To configure those taps, @file{target/str912.cfg}
4201 includes commands something like this:
4204 jtag newtap str912 flash ... params ...
4205 jtag newtap str912 cpu ... params ...
4206 jtag newtap str912 bs ... params ...
4209 Actual config files typically use a variable such as @code{$_CHIPNAME}
4210 instead of literals like @option{str912}, to support more than one chip
4211 of each type. @xref{Config File Guidelines}.
4213 @deffn {Command} {jtag names}
4214 Returns the names of all current TAPs in the scan chain.
4215 Use @command{jtag cget} or @command{jtag tapisenabled}
4216 to examine attributes and state of each TAP.
4218 foreach t [jtag names] @{
4219 puts [format "TAP: %s\n" $t]
4224 @deffn {Command} {scan_chain}
4225 Displays the TAPs in the scan chain configuration,
4227 The set of TAPs listed by this command is fixed by
4228 exiting the OpenOCD configuration stage,
4229 but systems with a JTAG router can
4230 enable or disable TAPs dynamically.
4233 @c FIXME! "jtag cget" should be able to return all TAP
4234 @c attributes, like "$target_name cget" does for targets.
4236 @c Probably want "jtag eventlist", and a "tap-reset" event
4237 @c (on entry to RESET state).
4242 When TAP objects are declared with @command{jtag newtap},
4243 a @dfn{dotted.name} is created for the TAP, combining the
4244 name of a module (usually a chip) and a label for the TAP.
4245 For example: @code{xilinx.tap}, @code{str912.flash},
4246 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4247 Many other commands use that dotted.name to manipulate or
4248 refer to the TAP. For example, CPU configuration uses the
4249 name, as does declaration of NAND or NOR flash banks.
4251 The components of a dotted name should follow ``C'' symbol
4252 name rules: start with an alphabetic character, then numbers
4253 and underscores are OK; while others (including dots!) are not.
4255 @section TAP Declaration Commands
4257 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4258 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4259 and configured according to the various @var{configparams}.
4261 The @var{chipname} is a symbolic name for the chip.
4262 Conventionally target config files use @code{$_CHIPNAME},
4263 defaulting to the model name given by the chip vendor but
4266 @cindex TAP naming convention
4267 The @var{tapname} reflects the role of that TAP,
4268 and should follow this convention:
4271 @item @code{bs} -- For boundary scan if this is a separate TAP;
4272 @item @code{cpu} -- The main CPU of the chip, alternatively
4273 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4274 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4275 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4276 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4277 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4278 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4279 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4281 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4282 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4283 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4284 a JTAG TAP; that TAP should be named @code{sdma}.
4287 Every TAP requires at least the following @var{configparams}:
4290 @item @code{-irlen} @var{NUMBER}
4291 @*The length in bits of the
4292 instruction register, such as 4 or 5 bits.
4295 A TAP may also provide optional @var{configparams}:
4298 @item @code{-disable} (or @code{-enable})
4299 @*Use the @code{-disable} parameter to flag a TAP which is not
4300 linked into the scan chain after a reset using either TRST
4301 or the JTAG state machine's @sc{reset} state.
4302 You may use @code{-enable} to highlight the default state
4303 (the TAP is linked in).
4304 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4305 @item @code{-expected-id} @var{NUMBER}
4306 @*A non-zero @var{number} represents a 32-bit IDCODE
4307 which you expect to find when the scan chain is examined.
4308 These codes are not required by all JTAG devices.
4309 @emph{Repeat the option} as many times as required if more than one
4310 ID code could appear (for example, multiple versions).
4311 Specify @var{number} as zero to suppress warnings about IDCODE
4312 values that were found but not included in the list.
4314 Provide this value if at all possible, since it lets OpenOCD
4315 tell when the scan chain it sees isn't right. These values
4316 are provided in vendors' chip documentation, usually a technical
4317 reference manual. Sometimes you may need to probe the JTAG
4318 hardware to find these values.
4319 @xref{autoprobing,,Autoprobing}.
4320 @item @code{-ignore-version}
4321 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4322 option. When vendors put out multiple versions of a chip, or use the same
4323 JTAG-level ID for several largely-compatible chips, it may be more practical
4324 to ignore the version field than to update config files to handle all of
4325 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4326 @item @code{-ignore-bypass}
4327 @*Specify this to ignore the 'bypass' bit of the idcode. Some vendor put
4328 an invalid idcode regarding this bit. Specify this to ignore this bit and
4329 to not consider this tap in bypass mode.
4330 @item @code{-ircapture} @var{NUMBER}
4331 @*The bit pattern loaded by the TAP into the JTAG shift register
4332 on entry to the @sc{ircapture} state, such as 0x01.
4333 JTAG requires the two LSBs of this value to be 01.
4334 By default, @code{-ircapture} and @code{-irmask} are set
4335 up to verify that two-bit value. You may provide
4336 additional bits if you know them, or indicate that
4337 a TAP doesn't conform to the JTAG specification.
4338 @item @code{-irmask} @var{NUMBER}
4339 @*A mask used with @code{-ircapture}
4340 to verify that instruction scans work correctly.
4341 Such scans are not used by OpenOCD except to verify that
4342 there seems to be no problems with JTAG scan chain operations.
4343 @item @code{-ignore-syspwrupack}
4344 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4345 register during initial examination and when checking the sticky error bit.
4346 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4347 devices do not set the ack bit until sometime later.
4351 @section Other TAP commands
4353 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4354 Get the value of the IDCODE found in hardware.
4357 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4358 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4359 At this writing this TAP attribute
4360 mechanism is limited and used mostly for event handling.
4361 (It is not a direct analogue of the @code{cget}/@code{configure}
4362 mechanism for debugger targets.)
4363 See the next section for information about the available events.
4365 The @code{configure} subcommand assigns an event handler,
4366 a TCL string which is evaluated when the event is triggered.
4367 The @code{cget} subcommand returns that handler.
4374 OpenOCD includes two event mechanisms.
4375 The one presented here applies to all JTAG TAPs.
4376 The other applies to debugger targets,
4377 which are associated with certain TAPs.
4379 The TAP events currently defined are:
4382 @item @b{post-reset}
4383 @* The TAP has just completed a JTAG reset.
4384 The tap may still be in the JTAG @sc{reset} state.
4385 Handlers for these events might perform initialization sequences
4386 such as issuing TCK cycles, TMS sequences to ensure
4387 exit from the ARM SWD mode, and more.
4389 Because the scan chain has not yet been verified, handlers for these events
4390 @emph{should not issue commands which scan the JTAG IR or DR registers}
4391 of any particular target.
4392 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4394 @* The scan chain has been reset and verified.
4395 This handler may enable TAPs as needed.
4396 @item @b{tap-disable}
4397 @* The TAP needs to be disabled. This handler should
4398 implement @command{jtag tapdisable}
4399 by issuing the relevant JTAG commands.
4400 @item @b{tap-enable}
4401 @* The TAP needs to be enabled. This handler should
4402 implement @command{jtag tapenable}
4403 by issuing the relevant JTAG commands.
4406 If you need some action after each JTAG reset which isn't actually
4407 specific to any TAP (since you can't yet trust the scan chain's
4408 contents to be accurate), you might:
4411 jtag configure CHIP.jrc -event post-reset @{
4412 echo "JTAG Reset done"
4413 ... non-scan jtag operations to be done after reset
4418 @anchor{enablinganddisablingtaps}
4419 @section Enabling and Disabling TAPs
4420 @cindex JTAG Route Controller
4423 In some systems, a @dfn{JTAG Route Controller} (JRC)
4424 is used to enable and/or disable specific JTAG TAPs.
4425 Many ARM-based chips from Texas Instruments include
4426 an ``ICEPick'' module, which is a JRC.
4427 Such chips include DaVinci and OMAP3 processors.
4429 A given TAP may not be visible until the JRC has been
4430 told to link it into the scan chain; and if the JRC
4431 has been told to unlink that TAP, it will no longer
4433 Such routers address problems that JTAG ``bypass mode''
4437 @item The scan chain can only go as fast as its slowest TAP.
4438 @item Having many TAPs slows instruction scans, since all
4439 TAPs receive new instructions.
4440 @item TAPs in the scan chain must be powered up, which wastes
4441 power and prevents debugging some power management mechanisms.
4444 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4445 as implied by the existence of JTAG routers.
4446 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4447 does include a kind of JTAG router functionality.
4449 @c (a) currently the event handlers don't seem to be able to
4450 @c fail in a way that could lead to no-change-of-state.
4452 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4453 shown below, and is implemented using TAP event handlers.
4454 So for example, when defining a TAP for a CPU connected to
4455 a JTAG router, your @file{target.cfg} file
4456 should define TAP event handlers using
4457 code that looks something like this:
4460 jtag configure CHIP.cpu -event tap-enable @{
4461 ... jtag operations using CHIP.jrc
4463 jtag configure CHIP.cpu -event tap-disable @{
4464 ... jtag operations using CHIP.jrc
4468 Then you might want that CPU's TAP enabled almost all the time:
4471 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4474 Note how that particular setup event handler declaration
4475 uses quotes to evaluate @code{$CHIP} when the event is configured.
4476 Using brackets @{ @} would cause it to be evaluated later,
4477 at runtime, when it might have a different value.
4479 @deffn {Command} {jtag tapdisable} dotted.name
4480 If necessary, disables the tap
4481 by sending it a @option{tap-disable} event.
4482 Returns the string "1" if the tap
4483 specified by @var{dotted.name} is enabled,
4484 and "0" if it is disabled.
4487 @deffn {Command} {jtag tapenable} dotted.name
4488 If necessary, enables the tap
4489 by sending it a @option{tap-enable} event.
4490 Returns the string "1" if the tap
4491 specified by @var{dotted.name} is enabled,
4492 and "0" if it is disabled.
4495 @deffn {Command} {jtag tapisenabled} dotted.name
4496 Returns the string "1" if the tap
4497 specified by @var{dotted.name} is enabled,
4498 and "0" if it is disabled.
4501 Humans will find the @command{scan_chain} command more helpful
4502 for querying the state of the JTAG taps.
4506 @anchor{autoprobing}
4507 @section Autoprobing
4509 @cindex JTAG autoprobe
4511 TAP configuration is the first thing that needs to be done
4512 after interface and reset configuration. Sometimes it's
4513 hard finding out what TAPs exist, or how they are identified.
4514 Vendor documentation is not always easy to find and use.
4516 To help you get past such problems, OpenOCD has a limited
4517 @emph{autoprobing} ability to look at the scan chain, doing
4518 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4519 To use this mechanism, start the OpenOCD server with only data
4520 that configures your JTAG interface, and arranges to come up
4521 with a slow clock (many devices don't support fast JTAG clocks
4522 right when they come out of reset).
4524 For example, your @file{openocd.cfg} file might have:
4527 source [find interface/olimex-arm-usb-tiny-h.cfg]
4528 reset_config trst_and_srst
4532 When you start the server without any TAPs configured, it will
4533 attempt to autoconfigure the TAPs. There are two parts to this:
4536 @item @emph{TAP discovery} ...
4537 After a JTAG reset (sometimes a system reset may be needed too),
4538 each TAP's data registers will hold the contents of either the
4539 IDCODE or BYPASS register.
4540 If JTAG communication is working, OpenOCD will see each TAP,
4541 and report what @option{-expected-id} to use with it.
4542 @item @emph{IR Length discovery} ...
4543 Unfortunately JTAG does not provide a reliable way to find out
4544 the value of the @option{-irlen} parameter to use with a TAP
4546 If OpenOCD can discover the length of a TAP's instruction
4547 register, it will report it.
4548 Otherwise you may need to consult vendor documentation, such
4549 as chip data sheets or BSDL files.
4552 In many cases your board will have a simple scan chain with just
4553 a single device. Here's what OpenOCD reported with one board
4554 that's a bit more complex:
4558 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4559 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4560 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4561 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4562 AUTO auto0.tap - use "... -irlen 4"
4563 AUTO auto1.tap - use "... -irlen 4"
4564 AUTO auto2.tap - use "... -irlen 6"
4565 no gdb ports allocated as no target has been specified
4568 Given that information, you should be able to either find some existing
4569 config files to use, or create your own. If you create your own, you
4570 would configure from the bottom up: first a @file{target.cfg} file
4571 with these TAPs, any targets associated with them, and any on-chip
4572 resources; then a @file{board.cfg} with off-chip resources, clocking,
4575 @anchor{dapdeclaration}
4576 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4577 @cindex DAP declaration
4579 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4580 no longer implicitly created together with the target. It must be
4581 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4582 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4583 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4585 The @command{dap} command group supports the following sub-commands:
4588 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4589 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4590 @var{dotted.name}. This also creates a new command (@command{dap_name})
4591 which is used for various purposes including additional configuration.
4592 There can only be one DAP for each JTAG tap in the system.
4594 A DAP may also provide optional @var{configparams}:
4598 Specify that it's an ADIv5 DAP. This is the default if not specified.
4600 Specify that it's an ADIv6 DAP.
4601 @item @code{-ignore-syspwrupack}
4602 Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4603 register during initial examination and when checking the sticky error bit.
4604 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4605 devices do not set the ack bit until sometime later.
4607 @item @code{-dp-id} @var{number}
4608 @*Debug port identification number for SWD DPv2 multidrop.
4609 The @var{number} is written to bits 0..27 of DP TARGETSEL during DP selection.
4610 To find the id number of a single connected device read DP TARGETID:
4611 @code{device.dap dpreg 0x24}
4612 Use bits 0..27 of TARGETID.
4614 @item @code{-instance-id} @var{number}
4615 @*Instance identification number for SWD DPv2 multidrop.
4616 The @var{number} is written to bits 28..31 of DP TARGETSEL during DP selection.
4617 To find the instance number of a single connected device read DP DLPIDR:
4618 @code{device.dap dpreg 0x34}
4619 The instance number is in bits 28..31 of DLPIDR value.
4623 @deffn {Command} {dap names}
4624 This command returns a list of all registered DAP objects. It it useful mainly
4628 @deffn {Command} {dap info} [@var{num}|@option{root}]
4629 Displays the ROM table for MEM-AP @var{num},
4630 defaulting to the currently selected AP of the currently selected target.
4631 On ADIv5 DAP @var{num} is the numeric index of the AP.
4632 On ADIv6 DAP @var{num} is the base address of the AP.
4633 With ADIv6 only, @option{root} specifies the root ROM table.
4636 @deffn {Command} {dap init}
4637 Initialize all registered DAPs. This command is used internally
4638 during initialization. It can be issued at any time after the
4639 initialization, too.
4642 The following commands exist as subcommands of DAP instances:
4644 @deffn {Command} {$dap_name info} [@var{num}|@option{root}]
4645 Displays the ROM table for MEM-AP @var{num},
4646 defaulting to the currently selected AP.
4647 On ADIv5 DAP @var{num} is the numeric index of the AP.
4648 On ADIv6 DAP @var{num} is the base address of the AP.
4649 With ADIv6 only, @option{root} specifies the root ROM table.
4652 @deffn {Command} {$dap_name apid} [num]
4653 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4654 On ADIv5 DAP @var{num} is the numeric index of the AP.
4655 On ADIv6 DAP @var{num} is the base address of the AP.
4658 @anchor{DAP subcommand apreg}
4659 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4660 Displays content of a register @var{reg} from AP @var{ap_num}
4661 or set a new value @var{value}.
4662 On ADIv5 DAP @var{ap_num} is the numeric index of the AP.
4663 On ADIv6 DAP @var{ap_num} is the base address of the AP.
4664 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4667 @deffn {Command} {$dap_name apsel} [num]
4668 Select AP @var{num}, defaulting to 0.
4669 On ADIv5 DAP @var{num} is the numeric index of the AP.
4670 On ADIv6 DAP @var{num} is the base address of the AP.
4673 @deffn {Command} {$dap_name dpreg} reg [value]
4674 Displays the content of DP register at address @var{reg}, or set it to a new
4677 In case of SWD, @var{reg} is a value in packed format
4678 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4679 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4681 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4682 background activity by OpenOCD while you are operating at such low-level.
4685 @deffn {Command} {$dap_name baseaddr} [num]
4686 Displays debug base address from MEM-AP @var{num},
4687 defaulting to the currently selected AP.
4688 On ADIv5 DAP @var{num} is the numeric index of the AP.
4689 On ADIv6 DAP @var{num} is the base address of the AP.
4692 @deffn {Command} {$dap_name memaccess} [value]
4693 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4694 memory bus access [0-255], giving additional time to respond to reads.
4695 If @var{value} is defined, first assigns that.
4698 @deffn {Command} {$dap_name apcsw} [value [mask]]
4699 Displays or changes CSW bit pattern for MEM-AP transfers.
4701 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4702 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4703 and the result is written to the real CSW register. All bits except dynamically
4704 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4705 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4708 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4709 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4712 kx.dap apcsw 0x2000000
4715 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4716 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4717 and leaves the rest of the pattern intact. It configures memory access through
4718 DCache on Cortex-M7.
4720 set CSW_HPROT3_CACHEABLE [expr @{1 << 27@}]
4721 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4724 Another example clears SPROT bit and leaves the rest of pattern intact:
4726 set CSW_SPROT [expr @{1 << 30@}]
4727 samv.dap apcsw 0 $CSW_SPROT
4730 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4731 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4733 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4734 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4735 example with a proper dap name:
4737 xxx.dap apcsw default
4741 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4742 Set/get quirks mode for TI TMS450/TMS570 processors
4746 @deffn {Config Command} {$dap_name nu_npcx_quirks} [@option{enable}]
4747 Set/get quirks mode for Nuvoton NPCX/NPCD MCU families
4751 @node CPU Configuration
4752 @chapter CPU Configuration
4755 This chapter discusses how to set up GDB debug targets for CPUs.
4756 You can also access these targets without GDB
4757 (@pxref{Architecture and Core Commands},
4758 and @ref{targetstatehandling,,Target State handling}) and
4759 through various kinds of NAND and NOR flash commands.
4760 If you have multiple CPUs you can have multiple such targets.
4762 We'll start by looking at how to examine the targets you have,
4763 then look at how to add one more target and how to configure it.
4765 @section Target List
4766 @cindex target, current
4767 @cindex target, list
4769 All targets that have been set up are part of a list,
4770 where each member has a name.
4771 That name should normally be the same as the TAP name.
4772 You can display the list with the @command{targets}
4774 This display often has only one CPU; here's what it might
4775 look like with more than one:
4777 TargetName Type Endian TapName State
4778 -- ------------------ ---------- ------ ------------------ ------------
4779 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4780 1 MyTarget cortex_m little mychip.foo tap-disabled
4783 One member of that list is the @dfn{current target}, which
4784 is implicitly referenced by many commands.
4785 It's the one marked with a @code{*} near the target name.
4786 In particular, memory addresses often refer to the address
4787 space seen by that current target.
4788 Commands like @command{mdw} (memory display words)
4789 and @command{flash erase_address} (erase NOR flash blocks)
4790 are examples; and there are many more.
4792 Several commands let you examine the list of targets:
4794 @deffn {Command} {target current}
4795 Returns the name of the current target.
4798 @deffn {Command} {target names}
4799 Lists the names of all current targets in the list.
4801 foreach t [target names] @{
4802 puts [format "Target: %s\n" $t]
4807 @c yep, "target list" would have been better.
4808 @c plus maybe "target setdefault".
4810 @deffn {Command} {targets} [name]
4811 @emph{Note: the name of this command is plural. Other target
4812 command names are singular.}
4814 With no parameter, this command displays a table of all known
4815 targets in a user friendly form.
4817 With a parameter, this command sets the current target to
4818 the given target with the given @var{name}; this is
4819 only relevant on boards which have more than one target.
4822 @section Target CPU Types
4826 Each target has a @dfn{CPU type}, as shown in the output of
4827 the @command{targets} command. You need to specify that type
4828 when calling @command{target create}.
4829 The CPU type indicates more than just the instruction set.
4830 It also indicates how that instruction set is implemented,
4831 what kind of debug support it integrates,
4832 whether it has an MMU (and if so, what kind),
4833 what core-specific commands may be available
4834 (@pxref{Architecture and Core Commands}),
4837 It's easy to see what target types are supported,
4838 since there's a command to list them.
4840 @anchor{targettypes}
4841 @deffn {Command} {target types}
4842 Lists all supported target types.
4843 At this writing, the supported CPU types are:
4846 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4847 @item @code{arm11} -- this is a generation of ARMv6 cores.
4848 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4849 @item @code{arm7tdmi} -- this is an ARMv4 core.
4850 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4851 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4852 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4853 @item @code{arm966e} -- this is an ARMv5 core.
4854 @item @code{arm9tdmi} -- this is an ARMv4 core.
4855 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4856 (Support for this is preliminary and incomplete.)
4857 @item @code{avr32_ap7k} -- this an AVR32 core.
4858 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4859 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4860 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4861 @item @code{cortex_r4} -- this is an ARMv7-R core.
4862 @item @code{dragonite} -- resembles arm966e.
4863 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4864 (Support for this is still incomplete.)
4865 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4866 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4867 The current implementation supports eSi-32xx cores.
4868 @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
4869 @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
4870 @item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
4871 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4872 @item @code{feroceon} -- resembles arm926.
4873 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4874 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4875 allowing access to physical memory addresses independently of CPU cores.
4876 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4877 a CPU, through which bus read and write cycles can be generated; it may be
4878 useful for working with non-CPU hardware behind an AP or during development of
4879 support for new CPUs.
4880 It's possible to connect a GDB client to this target (the GDB port has to be
4881 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4882 be emulated to comply to GDB remote protocol.
4883 @item @code{mips_m4k} -- a MIPS core.
4884 @item @code{mips_mips64} -- a MIPS64 core.
4885 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core (deprecated; would be removed in v0.13.0).
4886 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core (deprecated; would be removed in v0.13.0).
4887 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core (deprecated; would be removed in v0.13.0).
4888 @item @code{or1k} -- this is an OpenRISC 1000 core.
4889 The current implementation supports three JTAG TAP cores:
4891 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4892 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4893 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4895 And two debug interfaces cores:
4897 @item @code{Advanced debug interface}
4898 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4899 @item @code{SoC Debug Interface}
4900 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4902 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4903 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4904 @item @code{riscv} -- a RISC-V core.
4905 @item @code{stm8} -- implements an STM8 core.
4906 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4907 @item @code{xscale} -- this is actually an architecture,
4908 not a CPU type. It is based on the ARMv5 architecture.
4909 @item @code{xtensa} -- this is a generic Cadence/Tensilica Xtensa core.
4913 To avoid being confused by the variety of ARM based cores, remember
4914 this key point: @emph{ARM is a technology licencing company}.
4915 (See: @url{http://www.arm.com}.)
4916 The CPU name used by OpenOCD will reflect the CPU design that was
4917 licensed, not a vendor brand which incorporates that design.
4918 Name prefixes like arm7, arm9, arm11, and cortex
4919 reflect design generations;
4920 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4921 reflect an architecture version implemented by a CPU design.
4923 @anchor{targetconfiguration}
4924 @section Target Configuration
4926 Before creating a ``target'', you must have added its TAP to the scan chain.
4927 When you've added that TAP, you will have a @code{dotted.name}
4928 which is used to set up the CPU support.
4929 The chip-specific configuration file will normally configure its CPU(s)
4930 right after it adds all of the chip's TAPs to the scan chain.
4932 Although you can set up a target in one step, it's often clearer if you
4933 use shorter commands and do it in two steps: create it, then configure
4935 All operations on the target after it's created will use a new
4936 command, created as part of target creation.
4938 The two main things to configure after target creation are
4939 a work area, which usually has target-specific defaults even
4940 if the board setup code overrides them later;
4941 and event handlers (@pxref{targetevents,,Target Events}), which tend
4942 to be much more board-specific.
4943 The key steps you use might look something like this
4946 dap create mychip.dap -chain-position mychip.cpu
4947 target create MyTarget cortex_m -dap mychip.dap
4948 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4949 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4950 MyTarget configure -event reset-init @{ myboard_reinit @}
4953 You should specify a working area if you can; typically it uses some
4955 Such a working area can speed up many things, including bulk
4956 writes to target memory;
4957 flash operations like checking to see if memory needs to be erased;
4958 GDB memory checksumming;
4962 On more complex chips, the work area can become
4963 inaccessible when application code
4964 (such as an operating system)
4965 enables or disables the MMU.
4966 For example, the particular MMU context used to access the virtual
4967 address will probably matter ... and that context might not have
4968 easy access to other addresses needed.
4969 At this writing, OpenOCD doesn't have much MMU intelligence.
4972 It's often very useful to define a @code{reset-init} event handler.
4973 For systems that are normally used with a boot loader,
4974 common tasks include updating clocks and initializing memory
4976 That may be needed to let you write the boot loader into flash,
4977 in order to ``de-brick'' your board; or to load programs into
4978 external DDR memory without having run the boot loader.
4980 @deffn {Config Command} {target create} target_name type configparams...
4981 This command creates a GDB debug target that refers to a specific JTAG tap.
4982 It enters that target into a list, and creates a new
4983 command (@command{@var{target_name}}) which is used for various
4984 purposes including additional configuration.
4987 @item @var{target_name} ... is the name of the debug target.
4988 By convention this should be the same as the @emph{dotted.name}
4989 of the TAP associated with this target, which must be specified here
4990 using the @code{-chain-position @var{dotted.name}} configparam.
4992 This name is also used to create the target object command,
4993 referred to here as @command{$target_name},
4994 and in other places the target needs to be identified.
4995 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4996 @item @var{configparams} ... all parameters accepted by
4997 @command{$target_name configure} are permitted.
4998 If the target is big-endian, set it here with @code{-endian big}.
5000 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
5001 @code{-dap @var{dap_name}} here.
5005 @deffn {Command} {$target_name configure} configparams...
5006 The options accepted by this command may also be
5007 specified as parameters to @command{target create}.
5008 Their values can later be queried one at a time by
5009 using the @command{$target_name cget} command.
5011 @emph{Warning:} changing some of these after setup is dangerous.
5012 For example, moving a target from one TAP to another;
5013 and changing its endianness.
5017 @item @code{-chain-position} @var{dotted.name} -- names the TAP
5018 used to access this target.
5020 @item @code{-dap} @var{dap_name} -- names the DAP used to access
5021 this target. @xref{dapdeclaration,,DAP declaration}, on how to
5022 create and manage DAP instances.
5024 @item @code{-endian} (@option{big}|@option{little}) -- specifies
5025 whether the CPU uses big or little endian conventions
5027 @item @code{-event} @var{event_name} @var{event_body} --
5028 @xref{targetevents,,Target Events}.
5029 Note that this updates a list of named event handlers.
5030 Calling this twice with two different event names assigns
5031 two different handlers, but calling it twice with the
5032 same event name assigns only one handler.
5034 Current target is temporarily overridden to the event issuing target
5035 before handler code starts and switched back after handler is done.
5037 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
5038 whether the work area gets backed up; by default,
5039 @emph{it is not backed up.}
5040 When possible, use a working_area that doesn't need to be backed up,
5041 since performing a backup slows down operations.
5042 For example, the beginning of an SRAM block is likely to
5043 be used by most build systems, but the end is often unused.
5045 @item @code{-work-area-size} @var{size} -- specify work are size,
5046 in bytes. The same size applies regardless of whether its physical
5047 or virtual address is being used.
5049 @item @code{-work-area-phys} @var{address} -- set the work area
5050 base @var{address} to be used when no MMU is active.
5052 @item @code{-work-area-virt} @var{address} -- set the work area
5053 base @var{address} to be used when an MMU is active.
5054 @emph{Do not specify a value for this except on targets with an MMU.}
5055 The value should normally correspond to a static mapping for the
5056 @code{-work-area-phys} address, set up by the current operating system.
5059 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
5060 @var{rtos_type} can be one of @option{auto}, @option{none}, @option{eCos},
5061 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
5062 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
5063 @option{RIOT}, @option{Zephyr}
5064 @xref{gdbrtossupport,,RTOS Support}.
5066 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
5067 scan and after a reset. A manual call to arp_examine is required to
5068 access the target for debugging.
5070 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target.
5071 On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the target is connected to.
5072 On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the target is connected to.
5073 Use this option with systems where multiple, independent cores are connected
5074 to separate access ports of the same DAP.
5076 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
5077 to the target. Currently, only the @code{aarch64} target makes use of this option,
5078 where it is a mandatory configuration for the target run control.
5079 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
5080 for instruction on how to declare and control a CTI instance.
5082 @anchor{gdbportoverride}
5083 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
5084 possible values of the parameter @var{number}, which are not only numeric values.
5085 Use this option to override, for this target only, the global parameter set with
5086 command @command{gdb_port}.
5087 @xref{gdb_port,,command gdb_port}.
5089 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
5090 number of GDB connections that are allowed for the target. Default is 1.
5091 A negative value for @var{number} means unlimited connections.
5092 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
5096 @section Other $target_name Commands
5097 @cindex object command
5099 The Tcl/Tk language has the concept of object commands,
5100 and OpenOCD adopts that same model for targets.
5102 A good Tk example is a on screen button.
5103 Once a button is created a button
5104 has a name (a path in Tk terms) and that name is useable as a first
5105 class command. For example in Tk, one can create a button and later
5106 configure it like this:
5110 button .foobar -background red -command @{ foo @}
5112 .foobar configure -foreground blue
5114 set x [.foobar cget -background]
5116 puts [format "The button is %s" $x]
5119 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
5120 button, and its object commands are invoked the same way.
5123 str912.cpu mww 0x1234 0x42
5124 omap3530.cpu mww 0x5555 123
5127 The commands supported by OpenOCD target objects are:
5129 @deffn {Command} {$target_name arp_examine} @option{allow-defer}
5130 @deffnx {Command} {$target_name arp_halt}
5131 @deffnx {Command} {$target_name arp_poll}
5132 @deffnx {Command} {$target_name arp_reset}
5133 @deffnx {Command} {$target_name arp_waitstate}
5134 Internal OpenOCD scripts (most notably @file{startup.tcl})
5135 use these to deal with specific reset cases.
5136 They are not otherwise documented here.
5139 @deffn {Command} {$target_name set_reg} dict
5140 Set register values of the target.
5143 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
5146 For example, the following command sets the value 0 to the program counter (pc)
5147 register and 0x1000 to the stack pointer (sp) register:
5150 set_reg @{pc 0 sp 0x1000@}
5154 @deffn {Command} {$target_name get_reg} [-force] list
5155 Get register values from the target and return them as Tcl dictionary with pairs
5156 of register names and values.
5157 If option "-force" is set, the register values are read directly from the
5158 target, bypassing any caching.
5161 @item @var{list} ... List of register names
5164 For example, the following command retrieves the values from the program
5165 counter (pc) and stack pointer (sp) register:
5172 @deffn {Command} {$target_name write_memory} address width data ['phys']
5173 This function provides an efficient way to write to the target memory from a Tcl
5177 @item @var{address} ... target memory address
5178 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5179 @item @var{data} ... Tcl list with the elements to write
5180 @item ['phys'] ... treat the memory address as physical instead of virtual address
5183 For example, the following command writes two 32 bit words into the target
5184 memory at address 0x20000000:
5187 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
5191 @deffn {Command} {$target_name read_memory} address width count ['phys']
5192 This function provides an efficient way to read the target memory from a Tcl
5194 A Tcl list containing the requested memory elements is returned by this function.
5197 @item @var{address} ... target memory address
5198 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5199 @item @var{count} ... number of elements to read
5200 @item ['phys'] ... treat the memory address as physical instead of virtual address
5203 For example, the following command reads two 32 bit words from the target
5204 memory at address 0x20000000:
5207 read_memory 0x20000000 32 2
5211 @deffn {Command} {$target_name cget} queryparm
5212 Each configuration parameter accepted by
5213 @command{$target_name configure}
5214 can be individually queried, to return its current value.
5215 The @var{queryparm} is a parameter name
5216 accepted by that command, such as @code{-work-area-phys}.
5217 There are a few special cases:
5220 @item @code{-event} @var{event_name} -- returns the handler for the
5221 event named @var{event_name}.
5222 This is a special case because setting a handler requires
5224 @item @code{-type} -- returns the target type.
5225 This is a special case because this is set using
5226 @command{target create} and can't be changed
5227 using @command{$target_name configure}.
5230 For example, if you wanted to summarize information about
5231 all the targets you might use something like this:
5234 foreach name [target names] @{
5235 set y [$name cget -endian]
5236 set z [$name cget -type]
5237 puts [format "Chip %d is %s, Endian: %s, type: %s" \
5243 @anchor{targetcurstate}
5244 @deffn {Command} {$target_name curstate}
5245 Displays the current target state:
5246 @code{debug-running},
5249 @code{running}, or @code{unknown}.
5250 (Also, @pxref{eventpolling,,Event Polling}.)
5253 @deffn {Command} {$target_name eventlist}
5254 Displays a table listing all event handlers
5255 currently associated with this target.
5256 @xref{targetevents,,Target Events}.
5259 @deffn {Command} {$target_name invoke-event} event_name
5260 Invokes the handler for the event named @var{event_name}.
5261 (This is primarily intended for use by OpenOCD framework
5262 code, for example by the reset code in @file{startup.tcl}.)
5265 @deffn {Command} {$target_name mdd} [phys] addr [count]
5266 @deffnx {Command} {$target_name mdw} [phys] addr [count]
5267 @deffnx {Command} {$target_name mdh} [phys] addr [count]
5268 @deffnx {Command} {$target_name mdb} [phys] addr [count]
5269 Display contents of address @var{addr}, as
5270 64-bit doublewords (@command{mdd}),
5271 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5272 or 8-bit bytes (@command{mdb}).
5273 When the current target has an MMU which is present and active,
5274 @var{addr} is interpreted as a virtual address.
5275 Otherwise, or if the optional @var{phys} flag is specified,
5276 @var{addr} is interpreted as a physical address.
5277 If @var{count} is specified, displays that many units.
5278 (If you want to process the data instead of displaying it,
5279 see the @code{read_memory} primitives.)
5282 @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
5283 @deffnx {Command} {$target_name mww} [phys] addr word [count]
5284 @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
5285 @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
5286 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
5287 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
5288 at the specified address @var{addr}.
5289 When the current target has an MMU which is present and active,
5290 @var{addr} is interpreted as a virtual address.
5291 Otherwise, or if the optional @var{phys} flag is specified,
5292 @var{addr} is interpreted as a physical address.
5293 If @var{count} is specified, fills that many units of consecutive address.
5296 @anchor{targetevents}
5297 @section Target Events
5298 @cindex target events
5300 At various times, certain things can happen, or you want them to happen.
5303 @item What should happen when GDB connects? Should your target reset?
5304 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
5305 @item Is using SRST appropriate (and possible) on your system?
5306 Or instead of that, do you need to issue JTAG commands to trigger reset?
5307 SRST usually resets everything on the scan chain, which can be inappropriate.
5308 @item During reset, do you need to write to certain memory locations
5309 to set up system clocks or
5310 to reconfigure the SDRAM?
5311 How about configuring the watchdog timer, or other peripherals,
5312 to stop running while you hold the core stopped for debugging?
5315 All of the above items can be addressed by target event handlers.
5316 These are set up by @command{$target_name configure -event} or
5317 @command{target create ... -event}.
5319 The programmer's model matches the @code{-command} option used in Tcl/Tk
5320 buttons and events. The two examples below act the same, but one creates
5321 and invokes a small procedure while the other inlines it.
5324 proc my_init_proc @{ @} @{
5325 echo "Disabling watchdog..."
5326 mww 0xfffffd44 0x00008000
5328 mychip.cpu configure -event reset-init my_init_proc
5329 mychip.cpu configure -event reset-init @{
5330 echo "Disabling watchdog..."
5331 mww 0xfffffd44 0x00008000
5335 The following target events are defined:
5338 @item @b{debug-halted}
5339 @* The target has halted for debug reasons (i.e.: breakpoint)
5340 @item @b{debug-resumed}
5341 @* The target has resumed (i.e.: GDB said run)
5342 @item @b{early-halted}
5343 @* Occurs early in the halt process
5344 @item @b{examine-start}
5345 @* Before target examine is called.
5346 @item @b{examine-end}
5347 @* After target examine is called with no errors.
5348 @item @b{examine-fail}
5349 @* After target examine fails.
5350 @item @b{gdb-attach}
5351 @* When GDB connects. Issued before any GDB communication with the target
5352 starts. GDB expects the target is halted during attachment.
5353 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
5354 connect GDB to running target.
5355 The event can be also used to set up the target so it is possible to probe flash.
5356 Probing flash is necessary during GDB connect if you want to use
5357 @pxref{programmingusinggdb,,programming using GDB}.
5358 Another use of the flash memory map is for GDB to automatically choose
5359 hardware or software breakpoints depending on whether the breakpoint
5360 is in RAM or read only memory.
5361 Default is @code{halt}
5362 @item @b{gdb-detach}
5363 @* When GDB disconnects
5365 @* When the target has halted and GDB is not doing anything (see early halt)
5366 @item @b{gdb-flash-erase-start}
5367 @* Before the GDB flash process tries to erase the flash (default is
5369 @item @b{gdb-flash-erase-end}
5370 @* After the GDB flash process has finished erasing the flash
5371 @item @b{gdb-flash-write-start}
5372 @* Before GDB writes to the flash
5373 @item @b{gdb-flash-write-end}
5374 @* After GDB writes to the flash (default is @code{reset halt})
5376 @* Before the target steps, GDB is trying to start/resume the target
5378 @* The target has halted
5379 @item @b{reset-assert-pre}
5380 @* Issued as part of @command{reset} processing
5381 after @command{reset-start} was triggered
5382 but before either SRST alone is asserted on the scan chain,
5383 or @code{reset-assert} is triggered.
5384 @item @b{reset-assert}
5385 @* Issued as part of @command{reset} processing
5386 after @command{reset-assert-pre} was triggered.
5387 When such a handler is present, cores which support this event will use
5388 it instead of asserting SRST.
5389 This support is essential for debugging with JTAG interfaces which
5390 don't include an SRST line (JTAG doesn't require SRST), and for
5391 selective reset on scan chains that have multiple targets.
5392 @item @b{reset-assert-post}
5393 @* Issued as part of @command{reset} processing
5394 after @code{reset-assert} has been triggered.
5395 or the target asserted SRST on the entire scan chain.
5396 @item @b{reset-deassert-pre}
5397 @* Issued as part of @command{reset} processing
5398 after @code{reset-assert-post} has been triggered.
5399 @item @b{reset-deassert-post}
5400 @* Issued as part of @command{reset} processing
5401 after @code{reset-deassert-pre} has been triggered
5402 and (if the target is using it) after SRST has been
5403 released on the scan chain.
5405 @* Issued as the final step in @command{reset} processing.
5406 @item @b{reset-init}
5407 @* Used by @b{reset init} command for board-specific initialization.
5408 This event fires after @emph{reset-deassert-post}.
5410 This is where you would configure PLLs and clocking, set up DRAM so
5411 you can download programs that don't fit in on-chip SRAM, set up pin
5412 multiplexing, and so on.
5413 (You may be able to switch to a fast JTAG clock rate here, after
5414 the target clocks are fully set up.)
5415 @item @b{reset-start}
5416 @* Issued as the first step in @command{reset} processing
5417 before @command{reset-assert-pre} is called.
5419 This is the most robust place to use @command{jtag_rclk}
5420 or @command{adapter speed} to switch to a low JTAG clock rate,
5421 when reset disables PLLs needed to use a fast clock.
5422 @item @b{resume-start}
5423 @* Before any target is resumed
5424 @item @b{resume-end}
5425 @* After all targets have resumed
5427 @* Target has resumed
5428 @item @b{step-start}
5429 @* Before a target is single-stepped
5431 @* After single-step has completed
5432 @item @b{trace-config}
5433 @* After target hardware trace configuration was changed
5434 @item @b{semihosting-user-cmd-0x100}
5435 @* The target made a semihosting call with user-defined operation number 0x100
5436 @item @b{semihosting-user-cmd-0x101}
5437 @* The target made a semihosting call with user-defined operation number 0x101
5438 @item @b{semihosting-user-cmd-0x102}
5439 @* The target made a semihosting call with user-defined operation number 0x102
5440 @item @b{semihosting-user-cmd-0x103}
5441 @* The target made a semihosting call with user-defined operation number 0x103
5442 @item @b{semihosting-user-cmd-0x104}
5443 @* The target made a semihosting call with user-defined operation number 0x104
5444 @item @b{semihosting-user-cmd-0x105}
5445 @* The target made a semihosting call with user-defined operation number 0x105
5446 @item @b{semihosting-user-cmd-0x106}
5447 @* The target made a semihosting call with user-defined operation number 0x106
5448 @item @b{semihosting-user-cmd-0x107}
5449 @* The target made a semihosting call with user-defined operation number 0x107
5453 OpenOCD events are not supposed to be preempt by another event, but this
5454 is not enforced in current code. Only the target event @b{resumed} is
5455 executed with polling disabled; this avoids polling to trigger the event
5456 @b{halted}, reversing the logical order of execution of their handlers.
5457 Future versions of OpenOCD will prevent the event preemption and will
5458 disable the schedule of polling during the event execution. Do not rely
5459 on polling in any event handler; this means, don't expect the status of
5460 a core to change during the execution of the handler. The event handler
5461 will have to enable polling or use @command{$target_name arp_poll} to
5462 check if the core has changed status.
5465 @node Flash Commands
5466 @chapter Flash Commands
5468 OpenOCD has different commands for NOR and NAND flash;
5469 the ``flash'' command works with NOR flash, while
5470 the ``nand'' command works with NAND flash.
5471 This partially reflects different hardware technologies:
5472 NOR flash usually supports direct CPU instruction and data bus access,
5473 while data from a NAND flash must be copied to memory before it can be
5474 used. (SPI flash must also be copied to memory before use.)
5475 However, the documentation also uses ``flash'' as a generic term;
5476 for example, ``Put flash configuration in board-specific files''.
5480 @item Configure via the command @command{flash bank}
5481 @* Do this in a board-specific configuration file,
5482 passing parameters as needed by the driver.
5483 @item Operate on the flash via @command{flash subcommand}
5484 @* Often commands to manipulate the flash are typed by a human, or run
5485 via a script in some automated way. Common tasks include writing a
5486 boot loader, operating system, or other data.
5488 @* Flashing via GDB requires the flash be configured via ``flash
5489 bank'', and the GDB flash features be enabled.
5490 @xref{gdbconfiguration,,GDB Configuration}.
5493 Many CPUs have the ability to ``boot'' from the first flash bank.
5494 This means that misprogramming that bank can ``brick'' a system,
5495 so that it can't boot.
5496 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5497 board by (re)installing working boot firmware.
5499 @anchor{norconfiguration}
5500 @section Flash Configuration Commands
5501 @cindex flash configuration
5503 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5504 Configures a flash bank which provides persistent storage
5505 for addresses from @math{base} to @math{base + size - 1}.
5506 These banks will often be visible to GDB through the target's memory map.
5507 In some cases, configuring a flash bank will activate extra commands;
5508 see the driver-specific documentation.
5511 @item @var{name} ... may be used to reference the flash bank
5512 in other flash commands. A number is also available.
5513 @item @var{driver} ... identifies the controller driver
5514 associated with the flash bank being declared.
5515 This is usually @code{cfi} for external flash, or else
5516 the name of a microcontroller with embedded flash memory.
5517 @xref{flashdriverlist,,Flash Driver List}.
5518 @item @var{base} ... Base address of the flash chip.
5519 @item @var{size} ... Size of the chip, in bytes.
5520 For some drivers, this value is detected from the hardware.
5521 @item @var{chip_width} ... Width of the flash chip, in bytes;
5522 ignored for most microcontroller drivers.
5523 @item @var{bus_width} ... Width of the data bus used to access the
5524 chip, in bytes; ignored for most microcontroller drivers.
5525 @item @var{target} ... Names the target used to issue
5526 commands to the flash controller.
5527 @comment Actually, it's currently a controller-specific parameter...
5528 @item @var{driver_options} ... drivers may support, or require,
5529 additional parameters. See the driver-specific documentation
5530 for more information.
5533 This command is not available after OpenOCD initialization has completed.
5534 Use it in board specific configuration files, not interactively.
5538 @comment less confusing would be: "flash list" (like "nand list")
5539 @deffn {Command} {flash banks}
5540 Prints a one-line summary of each device that was
5541 declared using @command{flash bank}, numbered from zero.
5542 Note that this is the @emph{plural} form;
5543 the @emph{singular} form is a very different command.
5546 @deffn {Command} {flash list}
5547 Retrieves a list of associative arrays for each device that was
5548 declared using @command{flash bank}, numbered from zero.
5549 This returned list can be manipulated easily from within scripts.
5552 @deffn {Command} {flash probe} num
5553 Identify the flash, or validate the parameters of the configured flash. Operation
5554 depends on the flash type.
5555 The @var{num} parameter is a value shown by @command{flash banks}.
5556 Most flash commands will implicitly @emph{autoprobe} the bank;
5557 flash drivers can distinguish between probing and autoprobing,
5558 but most don't bother.
5561 @section Preparing a Target before Flash Programming
5563 The target device should be in well defined state before the flash programming
5566 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5567 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5568 until the programming session is finished.
5570 If you use @ref{programmingusinggdb,,Programming using GDB},
5571 the target is prepared automatically in the event gdb-flash-erase-start
5573 The jimtcl script @command{program} calls @command{reset init} explicitly.
5575 @section Erasing, Reading, Writing to Flash
5576 @cindex flash erasing
5577 @cindex flash reading
5578 @cindex flash writing
5579 @cindex flash programming
5580 @anchor{flashprogrammingcommands}
5582 One feature distinguishing NOR flash from NAND or serial flash technologies
5583 is that for read access, it acts exactly like any other addressable memory.
5584 This means you can use normal memory read commands like @command{mdw} or
5585 @command{dump_image} with it, with no special @command{flash} subcommands.
5586 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5588 Write access works differently. Flash memory normally needs to be erased
5589 before it's written. Erasing a sector turns all of its bits to ones, and
5590 writing can turn ones into zeroes. This is why there are special commands
5591 for interactive erasing and writing, and why GDB needs to know which parts
5592 of the address space hold NOR flash memory.
5595 Most of these erase and write commands leverage the fact that NOR flash
5596 chips consume target address space. They implicitly refer to the current
5597 JTAG target, and map from an address in that target's address space
5598 back to a flash bank.
5599 @comment In May 2009, those mappings may fail if any bank associated
5600 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5601 A few commands use abstract addressing based on bank and sector numbers,
5602 and don't depend on searching the current target and its address space.
5603 Avoid confusing the two command models.
5606 Some flash chips implement software protection against accidental writes,
5607 since such buggy writes could in some cases ``brick'' a system.
5608 For such systems, erasing and writing may require sector protection to be
5610 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5611 and AT91SAM7 on-chip flash.
5612 @xref{flashprotect,,flash protect}.
5614 @deffn {Command} {flash erase_sector} num first last
5615 Erase sectors in bank @var{num}, starting at sector @var{first}
5616 up to and including @var{last}.
5617 Sector numbering starts at 0.
5618 Providing a @var{last} sector of @option{last}
5619 specifies "to the end of the flash bank".
5620 The @var{num} parameter is a value shown by @command{flash banks}.
5623 @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
5624 Erase sectors starting at @var{address} for @var{length} bytes.
5625 Unless @option{pad} is specified, @math{address} must begin a
5626 flash sector, and @math{address + length - 1} must end a sector.
5627 Specifying @option{pad} erases extra data at the beginning and/or
5628 end of the specified region, as needed to erase only full sectors.
5629 The flash bank to use is inferred from the @var{address}, and
5630 the specified length must stay within that bank.
5631 As a special case, when @var{length} is zero and @var{address} is
5632 the start of the bank, the whole flash is erased.
5633 If @option{unlock} is specified, then the flash is unprotected
5634 before erase starts.
5637 @deffn {Command} {flash filld} address double-word length
5638 @deffnx {Command} {flash fillw} address word length
5639 @deffnx {Command} {flash fillh} address halfword length
5640 @deffnx {Command} {flash fillb} address byte length
5641 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5642 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5643 starting at @var{address} and continuing
5644 for @var{length} units (word/halfword/byte).
5645 No erasure is done before writing; when needed, that must be done
5646 before issuing this command.
5647 Writes are done in blocks of up to 1024 bytes, and each write is
5648 verified by reading back the data and comparing it to what was written.
5649 The flash bank to use is inferred from the @var{address} of
5650 each block, and the specified length must stay within that bank.
5652 @comment no current checks for errors if fill blocks touch multiple banks!
5654 @deffn {Command} {flash mdw} addr [count]
5655 @deffnx {Command} {flash mdh} addr [count]
5656 @deffnx {Command} {flash mdb} addr [count]
5657 Display contents of address @var{addr}, as
5658 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5659 or 8-bit bytes (@command{mdb}).
5660 If @var{count} is specified, displays that many units.
5661 Reads from flash using the flash driver, therefore it enables reading
5662 from a bank not mapped in target address space.
5663 The flash bank to use is inferred from the @var{address} of
5664 each block, and the specified length must stay within that bank.
5667 @deffn {Command} {flash write_bank} num filename [offset]
5668 Write the binary @file{filename} to flash bank @var{num},
5669 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5670 is omitted, start at the beginning of the flash bank.
5671 The @var{num} parameter is a value shown by @command{flash banks}.
5674 @deffn {Command} {flash read_bank} num filename [offset [length]]
5675 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5676 and write the contents to the binary @file{filename}. If @var{offset} is
5677 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5678 read the remaining bytes from the flash bank.
5679 The @var{num} parameter is a value shown by @command{flash banks}.
5682 @deffn {Command} {flash verify_bank} num filename [offset]
5683 Compare the contents of the binary file @var{filename} with the contents of the
5684 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5685 start at the beginning of the flash bank. Fail if the contents do not match.
5686 The @var{num} parameter is a value shown by @command{flash banks}.
5689 @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
5690 Write the image @file{filename} to the current target's flash bank(s).
5691 Only loadable sections from the image are written.
5692 A relocation @var{offset} may be specified, in which case it is added
5693 to the base address for each section in the image.
5694 The file [@var{type}] can be specified
5695 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5696 @option{elf} (ELF file), @option{s19} (Motorola s19).
5697 @option{mem}, or @option{builder}.
5698 The relevant flash sectors will be erased prior to programming
5699 if the @option{erase} parameter is given. If @option{unlock} is
5700 provided, then the flash banks are unlocked before erase and
5701 program. The flash bank to use is inferred from the address of
5705 Be careful using the @option{erase} flag when the flash is holding
5706 data you want to preserve.
5707 Portions of the flash outside those described in the image's
5708 sections might be erased with no notice.
5711 When a section of the image being written does not fill out all the
5712 sectors it uses, the unwritten parts of those sectors are necessarily
5713 also erased, because sectors can't be partially erased.
5715 Data stored in sector "holes" between image sections are also affected.
5716 For example, "@command{flash write_image erase ...}" of an image with
5717 one byte at the beginning of a flash bank and one byte at the end
5718 erases the entire bank -- not just the two sectors being written.
5720 Also, when flash protection is important, you must re-apply it after
5721 it has been removed by the @option{unlock} flag.
5726 @deffn {Command} {flash verify_image} filename [offset] [type]
5727 Verify the image @file{filename} to the current target's flash bank(s).
5728 Parameters follow the description of 'flash write_image'.
5729 In contrast to the 'verify_image' command, for banks with specific
5730 verify method, that one is used instead of the usual target's read
5731 memory methods. This is necessary for flash banks not readable by
5732 ordinary memory reads.
5733 This command gives only an overall good/bad result for each bank, not
5734 addresses of individual failed bytes as it's intended only as quick
5735 check for successful programming.
5738 @section Other Flash commands
5739 @cindex flash protection
5741 @deffn {Command} {flash erase_check} num
5742 Check erase state of sectors in flash bank @var{num},
5743 and display that status.
5744 The @var{num} parameter is a value shown by @command{flash banks}.
5747 @deffn {Command} {flash info} num [sectors]
5748 Print info about flash bank @var{num}, a list of protection blocks
5749 and their status. Use @option{sectors} to show a list of sectors instead.
5751 The @var{num} parameter is a value shown by @command{flash banks}.
5752 This command will first query the hardware, it does not print cached
5753 and possibly stale information.
5756 @anchor{flashprotect}
5757 @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
5758 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5759 in flash bank @var{num}, starting at protection block @var{first}
5760 and continuing up to and including @var{last}.
5761 Providing a @var{last} block of @option{last}
5762 specifies "to the end of the flash bank".
5763 The @var{num} parameter is a value shown by @command{flash banks}.
5764 The protection block is usually identical to a flash sector.
5765 Some devices may utilize a protection block distinct from flash sector.
5766 See @command{flash info} for a list of protection blocks.
5769 @deffn {Command} {flash padded_value} num value
5770 Sets the default value used for padding any image sections, This should
5771 normally match the flash bank erased value. If not specified by this
5772 command or the flash driver then it defaults to 0xff.
5776 @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
5777 This is a helper script that simplifies using OpenOCD as a standalone
5778 programmer. The only required parameter is @option{filename}, the others are optional.
5779 @xref{Flash Programming}.
5782 @anchor{flashdriverlist}
5783 @section Flash Driver List
5784 As noted above, the @command{flash bank} command requires a driver name,
5785 and allows driver-specific options and behaviors.
5786 Some drivers also activate driver-specific commands.
5788 @deffn {Flash Driver} {virtual}
5789 This is a special driver that maps a previously defined bank to another
5790 address. All bank settings will be copied from the master physical bank.
5792 The @var{virtual} driver defines one mandatory parameters,
5795 @item @var{master_bank} The bank that this virtual address refers to.
5798 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5799 the flash bank defined at address 0x1fc00000. Any command executed on
5800 the virtual banks is actually performed on the physical banks.
5802 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5803 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5804 $_TARGETNAME $_FLASHNAME
5805 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5806 $_TARGETNAME $_FLASHNAME
5810 @subsection External Flash
5812 @deffn {Flash Driver} {cfi}
5813 @cindex Common Flash Interface
5815 The ``Common Flash Interface'' (CFI) is the main standard for
5816 external NOR flash chips, each of which connects to a
5817 specific external chip select on the CPU.
5818 Frequently the first such chip is used to boot the system.
5819 Your board's @code{reset-init} handler might need to
5820 configure additional chip selects using other commands (like: @command{mww} to
5821 configure a bus and its timings), or
5822 perhaps configure a GPIO pin that controls the ``write protect'' pin
5824 The CFI driver can use a target-specific working area to significantly
5827 The CFI driver can accept the following optional parameters, in any order:
5830 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5831 like AM29LV010 and similar types.
5832 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5833 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5834 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5835 swapped when writing data values (i.e. not CFI commands).
5838 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5839 wide on a sixteen bit bus:
5842 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5843 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5846 To configure one bank of 32 MBytes
5847 built from two sixteen bit (two byte) wide parts wired in parallel
5848 to create a thirty-two bit (four byte) bus with doubled throughput:
5851 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5854 @c "cfi part_id" disabled
5857 @deffn {Flash Driver} {jtagspi}
5858 @cindex Generic JTAG2SPI driver
5862 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5863 SPI flash connected to them. To access this flash from the host, the device
5864 is first programmed with a special proxy bitstream that
5865 exposes the SPI flash on the device's JTAG interface. The flash can then be
5866 accessed through JTAG.
5868 Since signaling between JTAG and SPI is compatible, all that is required for
5869 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5870 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5871 a bitstream for several Xilinx FPGAs can be found in
5872 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5873 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5875 This flash bank driver requires a target on a JTAG tap and will access that
5876 tap directly. Since no support from the target is needed, the target can be a
5877 "testee" dummy. Since the target does not expose the flash memory
5878 mapping, target commands that would otherwise be expected to access the flash
5879 will not work. These include all @command{*_image} and
5880 @command{$target_name m*} commands as well as @command{program}. Equivalent
5881 functionality is available through the @command{flash write_bank},
5882 @command{flash read_bank}, and @command{flash verify_bank} commands.
5884 According to device size, 1- to 4-byte addresses are sent. However, some
5885 flash chips additionally have to be switched to 4-byte addresses by an extra
5889 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5890 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5891 @var{USER1} instruction.
5895 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5896 set _XILINX_USER1 0x02
5897 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5898 $_TARGETNAME $_XILINX_USER1
5901 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5902 Sets flash parameters: @var{name} human readable string, @var{total_size}
5903 size in bytes, @var{page_size} is write page size. @var{read_cmd} and @var{pprg_cmd}
5904 are commands for read and page program, respectively. @var{mass_erase_cmd},
5905 @var{sector_size} and @var{sector_erase_cmd} are optional.
5907 jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
5911 @deffn Command {jtagspi cmd} bank_id resp_num cmd_byte ...
5912 Sends command @var{cmd_byte} and at most 20 following bytes and reads
5913 @var{resp_num} bytes afterwards. E.g. for 'Enter 4-byte address mode'
5915 jtagspi cmd 0 0 0xB7
5919 @deffn Command {jtagspi always_4byte} bank_id [ on | off ]
5920 Some devices use 4-byte addresses for all commands except the legacy 0x03 read
5921 regardless of device size. This command controls the corresponding hack.
5925 @deffn {Flash Driver} {xcf}
5926 @cindex Xilinx Platform flash driver
5928 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5929 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5930 only difference is special registers controlling its FPGA specific behavior.
5931 They must be properly configured for successful FPGA loading using
5932 additional @var{xcf} driver command:
5934 @deffn {Command} {xcf ccb} <bank_id>
5935 command accepts additional parameters:
5937 @item @var{external|internal} ... selects clock source.
5938 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5939 @item @var{slave|master} ... selects slave of master mode for flash device.
5940 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5944 xcf ccb 0 external parallel slave 40
5946 All of them must be specified even if clock frequency is pointless
5947 in slave mode. If only bank id specified than command prints current
5948 CCB register value. Note: there is no need to write this register
5949 every time you erase/program data sectors because it stores in
5953 @deffn {Command} {xcf configure} <bank_id>
5954 Initiates FPGA loading procedure. Useful if your board has no "configure"
5961 Additional driver notes:
5963 @item Only single revision supported.
5964 @item Driver automatically detects need of bit reverse, but
5965 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5966 (Intel hex) file types supported.
5967 @item For additional info check xapp972.pdf and ug380.pdf.
5971 @deffn {Flash Driver} {lpcspifi}
5972 @cindex NXP SPI Flash Interface
5975 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5976 Flash Interface (SPIFI) peripheral that can drive and provide
5977 memory mapped access to external SPI flash devices.
5979 The lpcspifi driver initializes this interface and provides
5980 program and erase functionality for these serial flash devices.
5981 Use of this driver @b{requires} a working area of at least 1kB
5982 to be configured on the target device; more than this will
5983 significantly reduce flash programming times.
5985 The setup command only requires the @var{base} parameter. All
5986 other parameters are ignored, and the flash size and layout
5987 are configured by the driver.
5990 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5995 @deffn {Flash Driver} {stmsmi}
5996 @cindex STMicroelectronics Serial Memory Interface
5999 Some devices from STMicroelectronics (e.g. STR75x MCU family,
6000 SPEAr MPU family) include a proprietary
6001 ``Serial Memory Interface'' (SMI) controller able to drive external
6003 Depending on specific device and board configuration, up to 4 external
6004 flash devices can be connected.
6006 SMI makes the flash content directly accessible in the CPU address
6007 space; each external device is mapped in a memory bank.
6008 CPU can directly read data, execute code and boot from SMI banks.
6009 Normal OpenOCD commands like @command{mdw} can be used to display
6012 The setup command only requires the @var{base} parameter in order
6013 to identify the memory bank.
6014 All other parameters are ignored. Additional information, like
6015 flash size, are detected automatically.
6018 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
6023 @deffn {Flash Driver} {stmqspi}
6024 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
6028 Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
6029 (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
6030 controller able to drive one or even two (dual mode) external SPI flash devices.
6031 The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
6032 Currently only the regular command mode is supported, whereas the HyperFlash
6035 QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
6036 space; in case of dual mode both devices must be of the same type and are
6037 mapped in the same memory bank (even and odd addresses interleaved).
6038 CPU can directly read data, execute code (but not boot) from QuadSPI bank.
6040 The 'flash bank' command only requires the @var{base} parameter and the extra
6041 parameter @var{io_base} in order to identify the memory bank. Both are fixed
6042 by hardware, see datasheet or RM. All other parameters are ignored.
6044 The controller must be initialized after each reset and properly configured
6045 for memory-mapped read operation for the particular flash chip(s), for the full
6046 list of available register settings cf. the controller's RM. This setup is quite
6047 board specific (that's why booting from this memory is not possible). The
6048 flash driver infers all parameters from current controller register values when
6049 'flash probe @var{bank_id}' is executed.
6051 Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
6052 but only after proper controller initialization as described above. However,
6053 due to a silicon bug in some devices, attempting to access the very last word
6056 It is possible to use two (even different) flash chips alternatingly, if individual
6057 bank chip selects are available. For some package variants, this is not the case
6058 due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
6059 and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
6060 change, so the address spaces of both devices will overlap. In dual flash mode
6061 both chips must be identical regarding size and most other properties.
6063 Block or sector protection internal to the flash chip is not handled by this
6064 driver at all, but can be dealt with manually by the 'cmd' command, see below.
6065 The sector protection via 'flash protect' command etc. is completely internal to
6066 openocd, intended only to prevent accidental erase or overwrite and it does not
6067 persist across openocd invocations.
6069 OpenOCD contains a hardcoded list of flash devices with their properties,
6070 these are auto-detected. If a device is not included in this list, SFDP discovery
6071 is attempted. If this fails or gives inappropriate results, manual setting is
6072 required (see 'set' command).
6075 flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
6076 $_TARGETNAME 0xA0001000
6077 flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
6078 $_TARGETNAME 0xA0001400
6081 There are three specific commands
6082 @deffn {Command} {stmqspi mass_erase} bank_id
6083 Clears sector protections and performs a mass erase. Works only if there is no
6084 chip specific write protection engaged.
6087 @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
6088 Set flash parameters: @var{name} human readable string, @var{total_size} size
6089 in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
6090 are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
6091 @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
6092 and @var{sector_erase_cmd} are optional.
6094 This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
6095 which don't support an id command.
6097 In dual mode parameters of both chips are set identically. The parameters refer to
6098 a single chip, so the whole bank gets twice the specified capacity etc.
6101 @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
6102 If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
6103 bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
6104 sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
6105 i.e. the total number of bytes (including cmd_byte) must be odd.
6107 If @var{resp_num} is not zero, cmd and at most four following data bytes are
6108 sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
6109 are read interleaved from both chips starting with chip 1. In this case
6110 @var{resp_num} must be even.
6112 Note the hardware dictated subtle difference of those two cases in dual-flash mode.
6114 To check basic communication settings, issue
6116 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
6117 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
6119 for single flash mode or
6121 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
6122 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
6124 for dual flash mode. This should return the status register contents.
6126 In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
6127 complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
6128 need a dummy address, e.g.
6130 stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
6132 should return the status register contents.
6138 @deffn {Flash Driver} {mrvlqspi}
6139 This driver supports QSPI flash controller of Marvell's Wireless
6140 Microcontroller platform.
6142 The flash size is autodetected based on the table of known JEDEC IDs
6143 hardcoded in the OpenOCD sources.
6146 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
6151 @deffn {Flash Driver} {ath79}
6152 @cindex Atheros ath79 SPI driver
6154 Members of ATH79 SoC family from Atheros include a SPI interface with 3
6156 On reset a SPI flash connected to the first chip select (CS0) is made
6157 directly read-accessible in the CPU address space (up to 16MBytes)
6158 and is usually used to store the bootloader and operating system.
6159 Normal OpenOCD commands like @command{mdw} can be used to display
6160 the flash content while it is in memory-mapped mode (only the first
6161 4MBytes are accessible without additional configuration on reset).
6163 The setup command only requires the @var{base} parameter in order
6164 to identify the memory bank. The actual value for the base address
6165 is not otherwise used by the driver. However the mapping is passed
6166 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
6167 address should be the actual memory mapped base address. For unmapped
6168 chipselects (CS1 and CS2) care should be taken to use a base address
6169 that does not overlap with real memory regions.
6170 Additional information, like flash size, are detected automatically.
6171 An optional additional parameter sets the chipselect for the bank,
6172 with the default CS0.
6173 CS1 and CS2 require additional GPIO setup before they can be used
6174 since the alternate function must be enabled on the GPIO pin
6175 CS1/CS2 is routed to on the given SoC.
6178 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
6180 # When using multiple chipselects the base should be different
6181 # for each, otherwise the write_image command is not able to
6182 # distinguish the banks.
6183 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
6184 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
6185 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
6190 @deffn {Flash Driver} {fespi}
6191 @cindex Freedom E SPI
6194 SiFive's Freedom E SPI controller, used in HiFive and other boards.
6197 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
6201 @subsection Internal Flash (Microcontrollers)
6203 @deffn {Flash Driver} {aduc702x}
6204 The ADUC702x analog microcontrollers from Analog Devices
6205 include internal flash and use ARM7TDMI cores.
6206 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
6207 The setup command only requires the @var{target} argument
6208 since all devices in this family have the same memory layout.
6211 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
6215 @deffn {Flash Driver} {ambiqmicro}
6218 All members of the Apollo microcontroller family from
6219 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
6220 The host connects over USB to an FTDI interface that communicates
6221 with the target using SWD.
6223 The @var{ambiqmicro} driver reads the Chip Information Register detect
6224 the device class of the MCU.
6225 The Flash and SRAM sizes directly follow device class, and are used
6226 to set up the flash banks.
6227 If this fails, the driver will use default values set to the minimum
6228 sizes of an Apollo chip.
6230 All Apollo chips have two flash banks of the same size.
6231 In all cases the first flash bank starts at location 0,
6232 and the second bank starts after the first.
6236 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
6237 # Flash bank 1 - same size as bank0, starts after bank 0.
6238 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
6242 Flash is programmed using custom entry points into the bootloader.
6243 This is the only way to program the flash as no flash control registers
6244 are available to the user.
6246 The @var{ambiqmicro} driver adds some additional commands:
6248 @deffn {Command} {ambiqmicro mass_erase} <bank>
6251 @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
6254 @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
6255 Program OTP is a one time operation to create write protected flash.
6256 The user writes sectors to SRAM starting at 0x10000010.
6257 Program OTP will write these sectors from SRAM to flash, and write protect
6263 @deffn {Flash Driver} {at91samd}
6265 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
6266 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
6268 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
6270 The devices have one flash bank:
6273 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
6276 @deffn {Command} {at91samd chip-erase}
6277 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6278 used to erase a chip back to its factory state and does not require the
6279 processor to be halted.
6282 @deffn {Command} {at91samd set-security}
6283 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
6284 to the Flash and can only be undone by using the chip-erase command which
6285 erases the Flash contents and turns off the security bit. Warning: at this
6286 time, openocd will not be able to communicate with a secured chip and it is
6287 therefore not possible to chip-erase it without using another tool.
6290 at91samd set-security enable
6294 @deffn {Command} {at91samd eeprom}
6295 Shows or sets the EEPROM emulation size configuration, stored in the User Row
6296 of the Flash. When setting, the EEPROM size must be specified in bytes and it
6297 must be one of the permitted sizes according to the datasheet. Settings are
6298 written immediately but only take effect on MCU reset. EEPROM emulation
6299 requires additional firmware support and the minimum EEPROM size may not be
6300 the same as the minimum that the hardware supports. Set the EEPROM size to 0
6301 in order to disable this feature.
6305 at91samd eeprom 1024
6309 @deffn {Command} {at91samd bootloader}
6310 Shows or sets the bootloader size configuration, stored in the User Row of the
6311 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6312 must be specified in bytes and it must be one of the permitted sizes according
6313 to the datasheet. Settings are written immediately but only take effect on
6314 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
6318 at91samd bootloader 16384
6322 @deffn {Command} {at91samd dsu_reset_deassert}
6323 This command releases internal reset held by DSU
6324 and prepares reset vector catch in case of reset halt.
6325 Command is used internally in event reset-deassert-post.
6328 @deffn {Command} {at91samd nvmuserrow}
6329 Writes or reads the entire 64 bit wide NVM user row register which is located at
6330 0x804000. This register includes various fuses lock-bits and factory calibration
6331 data. Reading the register is done by invoking this command without any
6332 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
6333 is the register value to be written and the second one is an optional changemask.
6334 Every bit which value in changemask is 0 will stay unchanged. The lock- and
6335 reserved-bits are masked out and cannot be changed.
6339 >at91samd nvmuserrow
6340 NVMUSERROW: 0xFFFFFC5DD8E0C788
6341 # Write 0xFFFFFC5DD8E0C788 to user row
6342 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
6343 # Write 0x12300 to user row but leave other bits and low
6345 >at91samd nvmuserrow 0x12345 0xFFF00
6352 @deffn {Flash Driver} {at91sam3}
6354 All members of the AT91SAM3 microcontroller family from
6355 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
6356 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
6357 that the driver was orginaly developed and tested using the
6358 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
6359 the family was cribbed from the data sheet. @emph{Note to future
6360 readers/updaters: Please remove this worrisome comment after other
6361 chips are confirmed.}
6363 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
6364 have one flash bank. In all cases the flash banks are at
6365 the following fixed locations:
6368 # Flash bank 0 - all chips
6369 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
6370 # Flash bank 1 - only 256K chips
6371 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
6374 Internally, the AT91SAM3 flash memory is organized as follows.
6375 Unlike the AT91SAM7 chips, these are not used as parameters
6376 to the @command{flash bank} command:
6379 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
6380 @item @emph{Bank Size:} 128K/64K Per flash bank
6381 @item @emph{Sectors:} 16 or 8 per bank
6382 @item @emph{SectorSize:} 8K Per Sector
6383 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
6386 The AT91SAM3 driver adds some additional commands:
6388 @deffn {Command} {at91sam3 gpnvm}
6389 @deffnx {Command} {at91sam3 gpnvm clear} number
6390 @deffnx {Command} {at91sam3 gpnvm set} number
6391 @deffnx {Command} {at91sam3 gpnvm show} [@option{all}|number]
6392 With no parameters, @command{show} or @command{show all},
6393 shows the status of all GPNVM bits.
6394 With @command{show} @var{number}, displays that bit.
6396 With @command{set} @var{number} or @command{clear} @var{number},
6397 modifies that GPNVM bit.
6400 @deffn {Command} {at91sam3 info}
6401 This command attempts to display information about the AT91SAM3
6402 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
6403 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
6404 document id: doc6430A] and decodes the values. @emph{Second} it reads the
6405 various clock configuration registers and attempts to display how it
6406 believes the chip is configured. By default, the SLOWCLK is assumed to
6407 be 32768 Hz, see the command @command{at91sam3 slowclk}.
6410 @deffn {Command} {at91sam3 slowclk} [value]
6411 This command shows/sets the slow clock frequency used in the
6412 @command{at91sam3 info} command calculations above.
6416 @deffn {Flash Driver} {at91sam4}
6418 All members of the AT91SAM4 microcontroller family from
6419 Atmel include internal flash and use ARM's Cortex-M4 core.
6420 This driver uses the same command names/syntax as @xref{at91sam3}.
6423 @deffn {Flash Driver} {at91sam4l}
6425 All members of the AT91SAM4L microcontroller family from
6426 Atmel include internal flash and use ARM's Cortex-M4 core.
6427 This driver uses the same command names/syntax as @xref{at91sam3}.
6429 The AT91SAM4L driver adds some additional commands:
6430 @deffn {Command} {at91sam4l smap_reset_deassert}
6431 This command releases internal reset held by SMAP
6432 and prepares reset vector catch in case of reset halt.
6433 Command is used internally in event reset-deassert-post.
6438 @deffn {Flash Driver} {atsame5}
6440 All members of the SAM E54, E53, E51 and D51 microcontroller
6441 families from Microchip (former Atmel) include internal flash
6442 and use ARM's Cortex-M4 core.
6444 The devices have two ECC flash banks with a swapping feature.
6445 This driver handles both banks together as it were one.
6446 Bank swapping is not supported yet.
6449 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
6452 @deffn {Command} {atsame5 bootloader}
6453 Shows or sets the bootloader size configuration, stored in the User Page of the
6454 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6455 must be specified in bytes. The nearest bigger protection size is used.
6456 Settings are written immediately but only take effect on MCU reset.
6457 Setting the bootloader size to 0 disables bootloader protection.
6461 atsame5 bootloader 16384
6465 @deffn {Command} {atsame5 chip-erase}
6466 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6467 used to erase a chip back to its factory state and does not require the
6468 processor to be halted.
6471 @deffn {Command} {atsame5 dsu_reset_deassert}
6472 This command releases internal reset held by DSU
6473 and prepares reset vector catch in case of reset halt.
6474 Command is used internally in event reset-deassert-post.
6477 @deffn {Command} {atsame5 userpage}
6478 Writes or reads the first 64 bits of NVM User Page which is located at
6479 0x804000. This field includes various fuses.
6480 Reading is done by invoking this command without any arguments.
6481 Writing is possible by giving 1 or 2 hex values. The first argument
6482 is the value to be written and the second one is an optional bit mask
6483 (a zero bit in the mask means the bit stays unchanged).
6484 The reserved fields are always masked out and cannot be changed.
6489 USER PAGE: 0xAEECFF80FE9A9239
6491 >atsame5 userpage 0xAEECFF80FE9A9239
6492 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
6493 # bits unchanged (setup SmartEEPROM of virtual size 8192
6495 >atsame5 userpage 0x4200000000 0x7f00000000
6501 @deffn {Flash Driver} {atsamv}
6503 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
6504 Atmel include internal flash and use ARM's Cortex-M7 core.
6505 This driver uses the same command names/syntax as @xref{at91sam3}.
6508 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
6511 @deffn {Command} {atsamv gpnvm} [@option{show} [@option{all}|number]]
6512 @deffnx {Command} {atsamv gpnvm} (@option{clr}|@option{set}) number
6513 With no parameters, @option{show} or @option{show all},
6514 shows the status of all GPNVM bits.
6515 With @option{show} @var{number}, displays that bit.
6517 With @option{set} @var{number} or @option{clear} @var{number},
6518 modifies that GPNVM bit.
6523 @deffn {Flash Driver} {at91sam7}
6524 All members of the AT91SAM7 microcontroller family from Atmel include
6525 internal flash and use ARM7TDMI cores. The driver automatically
6526 recognizes a number of these chips using the chip identification
6527 register, and autoconfigures itself.
6530 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
6533 For chips which are not recognized by the controller driver, you must
6534 provide additional parameters in the following order:
6537 @item @var{chip_model} ... label used with @command{flash info}
6539 @item @var{sectors_per_bank}
6540 @item @var{pages_per_sector}
6541 @item @var{pages_size}
6542 @item @var{num_nvm_bits}
6543 @item @var{freq_khz} ... required if an external clock is provided,
6544 optional (but recommended) when the oscillator frequency is known
6547 It is recommended that you provide zeroes for all of those values
6548 except the clock frequency, so that everything except that frequency
6549 will be autoconfigured.
6550 Knowing the frequency helps ensure correct timings for flash access.
6552 The flash controller handles erases automatically on a page (128/256 byte)
6553 basis, so explicit erase commands are not necessary for flash programming.
6554 However, there is an ``EraseAll`` command that can erase an entire flash
6555 plane (of up to 256KB), and it will be used automatically when you issue
6556 @command{flash erase_sector} or @command{flash erase_address} commands.
6558 @deffn {Command} {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
6559 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
6560 bit for the processor. Each processor has a number of such bits,
6561 used for controlling features such as brownout detection (so they
6562 are not truly general purpose).
6564 This assumes that the first flash bank (number 0) is associated with
6565 the appropriate at91sam7 target.
6570 @deffn {Flash Driver} {avr}
6571 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
6572 @emph{The current implementation is incomplete.}
6573 @comment - defines mass_erase ... pointless given flash_erase_address
6576 @deffn {Flash Driver} {bluenrg-x}
6577 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
6578 The driver automatically recognizes these chips using
6579 the chip identification registers, and autoconfigures itself.
6582 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
6585 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
6586 each single sector one by one.
6589 flash erase_sector 0 0 last # It will perform a mass erase
6592 Triggering a mass erase is also useful when users want to disable readout protection.
6595 @deffn {Flash Driver} {cc26xx}
6596 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
6597 Instruments include internal flash. The cc26xx flash driver supports both the
6598 CC13xx and CC26xx family of devices. The driver automatically recognizes the
6599 specific version's flash parameters and autoconfigures itself. The flash bank
6600 starts at address 0.
6603 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
6607 @deffn {Flash Driver} {cc3220sf}
6608 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
6609 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
6610 supports the internal flash. The serial flash on SimpleLink boards is
6611 programmed via the bootloader over a UART connection. Security features of
6612 the CC3220SF may erase the internal flash during power on reset. Refer to
6613 documentation at @url{www.ti.com/cc3220sf} for details on security features
6614 and programming the serial flash.
6617 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
6621 @deffn {Flash Driver} {efm32}
6622 All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs)
6623 include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically
6624 recognizes a number of these chips using the chip identification register, and
6625 autoconfigures itself.
6627 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
6629 It supports writing to the user data page, as well as the portion of the lockbits page
6630 past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs
6631 bootloader/AppLoader system for encryption keys. Setting protection on these pages is
6632 currently not supported.
6634 flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
6635 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
6638 A special feature of efm32 controllers is that it is possible to completely disable the
6639 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
6640 this via the following command:
6644 The @var{num} parameter is a value shown by @command{flash banks}.
6645 Note that in order for this command to take effect, the target needs to be reset.
6646 @emph{The current implementation is incomplete. Unprotecting flash pages is not
6650 @deffn {Flash Driver} {esirisc}
6651 Members of the eSi-RISC family may optionally include internal flash programmed
6652 via the eSi-TSMC Flash interface. Additional parameters are required to
6653 configure the driver: @option{cfg_address} is the base address of the
6654 configuration register interface, @option{clock_hz} is the expected clock
6655 frequency, and @option{wait_states} is the number of configured read wait states.
6658 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6659 $_TARGETNAME cfg_address clock_hz wait_states
6662 @deffn {Command} {esirisc flash mass_erase} bank_id
6663 Erase all pages in data memory for the bank identified by @option{bank_id}.
6666 @deffn {Command} {esirisc flash ref_erase} bank_id
6667 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6668 is an uncommon operation.}
6672 @deffn {Flash Driver} {fm3}
6673 All members of the FM3 microcontroller family from Fujitsu
6674 include internal flash and use ARM Cortex-M3 cores.
6675 The @var{fm3} driver uses the @var{target} parameter to select the
6676 correct bank config, it can currently be one of the following:
6677 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6678 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6681 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6685 @deffn {Flash Driver} {fm4}
6686 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6687 include internal flash and use ARM Cortex-M4 cores.
6688 The @var{fm4} driver uses a @var{family} parameter to select the
6689 correct bank config, it can currently be one of the following:
6690 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6691 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6692 with @code{x} treated as wildcard and otherwise case (and any trailing
6693 characters) ignored.
6696 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6697 $_TARGETNAME S6E2CCAJ0A
6698 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6699 $_TARGETNAME S6E2CCAJ0A
6701 @emph{The current implementation is incomplete. Protection is not supported,
6702 nor is Chip Erase (only Sector Erase is implemented).}
6705 @deffn {Flash Driver} {kinetis}
6707 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
6708 from NXP (former Freescale) include
6709 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
6710 recognizes flash size and a number of flash banks (1-4) using the chip
6711 identification register, and autoconfigures itself.
6712 Use kinetis_ke driver for KE0x and KEAx devices.
6714 The @var{kinetis} driver defines option:
6716 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
6720 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6723 @deffn {Config Command} {kinetis create_banks}
6724 Configuration command enables automatic creation of additional flash banks
6725 based on real flash layout of device. Banks are created during device probe.
6726 Use 'flash probe 0' to force probe.
6729 @deffn {Command} {kinetis fcf_source} [protection|write]
6730 Select what source is used when writing to a Flash Configuration Field.
6731 @option{protection} mode builds FCF content from protection bits previously
6732 set by 'flash protect' command.
6733 This mode is default. MCU is protected from unwanted locking by immediate
6734 writing FCF after erase of relevant sector.
6735 @option{write} mode enables direct write to FCF.
6736 Protection cannot be set by 'flash protect' command. FCF is written along
6737 with the rest of a flash image.
6738 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6741 @deffn {Command} {kinetis fopt} [num]
6742 Set value to write to FOPT byte of Flash Configuration Field.
6743 Used in kinetis 'fcf_source protection' mode only.
6746 @deffn {Command} {kinetis mdm check_security}
6747 Checks status of device security lock. Used internally in examine-end
6748 and examine-fail event.
6751 @deffn {Command} {kinetis mdm halt}
6752 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6753 loop when connecting to an unsecured target.
6756 @deffn {Command} {kinetis mdm mass_erase}
6757 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6758 back to its factory state, removing security. It does not require the processor
6759 to be halted, however the target will remain in a halted state after this
6763 @deffn {Command} {kinetis nvm_partition}
6764 For FlexNVM devices only (KxxDX and KxxFX).
6765 Command shows or sets data flash or EEPROM backup size in kilobytes,
6766 sets two EEPROM blocks sizes in bytes and enables/disables loading
6767 of EEPROM contents to FlexRAM during reset.
6769 For details see device reference manual, Flash Memory Module,
6770 Program Partition command.
6772 Setting is possible only once after mass_erase.
6773 Reset the device after partition setting.
6775 Show partition size:
6777 kinetis nvm_partition info
6780 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6781 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6783 kinetis nvm_partition dataflash 32 512 1536 on
6786 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6787 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6789 kinetis nvm_partition eebkp 16 1024 1024 off
6793 @deffn {Command} {kinetis mdm reset}
6794 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6795 RESET pin, which can be used to reset other hardware on board.
6798 @deffn {Command} {kinetis disable_wdog}
6799 For Kx devices only (KLx has different COP watchdog, it is not supported).
6800 Command disables watchdog timer.
6804 @deffn {Flash Driver} {kinetis_ke}
6806 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6807 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6808 the KE0x sub-family using the chip identification register, and
6809 autoconfigures itself.
6810 Use kinetis (not kinetis_ke) driver for KE1x devices.
6813 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6816 @deffn {Command} {kinetis_ke mdm check_security}
6817 Checks status of device security lock. Used internally in examine-end event.
6820 @deffn {Command} {kinetis_ke mdm mass_erase}
6821 Issues a complete Flash erase via the MDM-AP.
6822 This can be used to erase a chip back to its factory state.
6823 Command removes security lock from a device (use of SRST highly recommended).
6824 It does not require the processor to be halted.
6827 @deffn {Command} {kinetis_ke disable_wdog}
6828 Command disables watchdog timer.
6832 @deffn {Flash Driver} {lpc2000}
6833 This is the driver to support internal flash of all members of the
6834 LPC11(x)00 and LPC1300 microcontroller families and most members of
6835 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6836 LPC8Nxx and NHS31xx microcontroller families from NXP.
6839 There are LPC2000 devices which are not supported by the @var{lpc2000}
6841 The LPC2888 is supported by the @var{lpc288x} driver.
6842 The LPC29xx family is supported by the @var{lpc2900} driver.
6845 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6846 which must appear in the following order:
6849 @item @var{variant} ... required, may be
6850 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6851 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6852 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6853 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6855 @option{lpc800} (LPC8xx)
6856 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6857 @option{lpc1500} (LPC15xx)
6858 @option{lpc54100} (LPC541xx)
6859 @option{lpc4000} (LPC40xx)
6860 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6861 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6862 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6863 at which the core is running
6864 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6865 telling the driver to calculate a valid checksum for the exception vector table.
6867 If you don't provide @option{calc_checksum} when you're writing the vector
6868 table, the boot ROM will almost certainly ignore your flash image.
6869 However, if you do provide it,
6870 with most tool chains @command{verify_image} will fail.
6872 @item @option{iap_entry} ... optional telling the driver to use a different
6873 ROM IAP entry point.
6876 LPC flashes don't require the chip and bus width to be specified.
6879 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6880 lpc2000_v2 14765 calc_checksum
6883 @deffn {Command} {lpc2000 part_id} bank
6884 Displays the four byte part identifier associated with
6885 the specified flash @var{bank}.
6889 @deffn {Flash Driver} {lpc288x}
6890 The LPC2888 microcontroller from NXP needs slightly different flash
6891 support from its lpc2000 siblings.
6892 The @var{lpc288x} driver defines one mandatory parameter,
6893 the programming clock rate in Hz.
6894 LPC flashes don't require the chip and bus width to be specified.
6897 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6901 @deffn {Flash Driver} {lpc2900}
6902 This driver supports the LPC29xx ARM968E based microcontroller family
6905 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6906 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6907 sector layout are auto-configured by the driver.
6908 The driver has one additional mandatory parameter: The CPU clock rate
6909 (in kHz) at the time the flash operations will take place. Most of the time this
6910 will not be the crystal frequency, but a higher PLL frequency. The
6911 @code{reset-init} event handler in the board script is usually the place where
6914 The driver rejects flashless devices (currently the LPC2930).
6916 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6917 It must be handled much more like NAND flash memory, and will therefore be
6918 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6920 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6921 sector needs to be erased or programmed, it is automatically unprotected.
6922 What is shown as protection status in the @code{flash info} command, is
6923 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6924 sector from ever being erased or programmed again. As this is an irreversible
6925 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6926 and not by the standard @code{flash protect} command.
6928 Example for a 125 MHz clock frequency:
6930 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6933 Some @code{lpc2900}-specific commands are defined. In the following command list,
6934 the @var{bank} parameter is the bank number as obtained by the
6935 @code{flash banks} command.
6937 @deffn {Command} {lpc2900 signature} bank
6938 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6939 content. This is a hardware feature of the flash block, hence the calculation is
6940 very fast. You may use this to verify the content of a programmed device against
6945 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6949 @deffn {Command} {lpc2900 read_custom} bank filename
6950 Reads the 912 bytes of customer information from the flash index sector, and
6951 saves it to a file in binary format.
6954 lpc2900 read_custom 0 /path_to/customer_info.bin
6958 The index sector of the flash is a @emph{write-only} sector. It cannot be
6959 erased! In order to guard against unintentional write access, all following
6960 commands need to be preceded by a successful call to the @code{password}
6963 @deffn {Command} {lpc2900 password} bank password
6964 You need to use this command right before each of the following commands:
6965 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6966 @code{lpc2900 secure_jtag}.
6968 The password string is fixed to "I_know_what_I_am_doing".
6971 lpc2900 password 0 I_know_what_I_am_doing
6972 Potentially dangerous operation allowed in next command!
6976 @deffn {Command} {lpc2900 write_custom} bank filename type
6977 Writes the content of the file into the customer info space of the flash index
6978 sector. The filetype can be specified with the @var{type} field. Possible values
6979 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6980 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6981 contain a single section, and the contained data length must be exactly
6983 @quotation Attention
6984 This cannot be reverted! Be careful!
6988 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6992 @deffn {Command} {lpc2900 secure_sector} bank first last
6993 Secures the sector range from @var{first} to @var{last} (including) against
6994 further program and erase operations. The sector security will be effective
6995 after the next power cycle.
6996 @quotation Attention
6997 This cannot be reverted! Be careful!
6999 Secured sectors appear as @emph{protected} in the @code{flash info} command.
7002 lpc2900 secure_sector 0 1 1
7004 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
7005 # 0: 0x00000000 (0x2000 8kB) not protected
7006 # 1: 0x00002000 (0x2000 8kB) protected
7007 # 2: 0x00004000 (0x2000 8kB) not protected
7011 @deffn {Command} {lpc2900 secure_jtag} bank
7012 Irreversibly disable the JTAG port. The new JTAG security setting will be
7013 effective after the next power cycle.
7014 @quotation Attention
7015 This cannot be reverted! Be careful!
7019 lpc2900 secure_jtag 0
7024 @deffn {Flash Driver} {mdr}
7025 This drivers handles the integrated NOR flash on Milandr Cortex-M
7026 based controllers. A known limitation is that the Info memory can't be
7027 read or verified as it's not memory mapped.
7030 flash bank <name> mdr <base> <size> \
7031 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
7035 @item @var{type} - 0 for main memory, 1 for info memory
7036 @item @var{page_count} - total number of pages
7037 @item @var{sec_count} - number of sector per page count
7042 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
7043 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
7044 0 0 $_TARGETNAME 1 1 4
7046 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
7047 0 0 $_TARGETNAME 0 32 4
7052 @deffn {Flash Driver} {msp432}
7053 All versions of the SimpleLink MSP432 microcontrollers from Texas
7054 Instruments include internal flash. The msp432 flash driver automatically
7055 recognizes the specific version's flash parameters and autoconfigures itself.
7056 Main program flash starts at address 0. The information flash region on
7057 MSP432P4 versions starts at address 0x200000.
7060 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
7063 @deffn {Command} {msp432 mass_erase} bank_id [main|all]
7064 Performs a complete erase of flash. By default, @command{mass_erase} will erase
7065 only the main program flash.
7067 On MSP432P4 versions, using @command{mass_erase all} will erase both the
7068 main program and information flash regions. To also erase the BSL in information
7069 flash, the user must first use the @command{bsl} command.
7072 @deffn {Command} {msp432 bsl} bank_id [unlock|lock]
7073 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
7074 region in information flash so that flash commands can erase or write the BSL.
7075 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
7077 To erase and program the BSL:
7080 flash erase_address 0x202000 0x2000
7081 flash write_image bsl.bin 0x202000
7087 @deffn {Flash Driver} {niietcm4}
7088 This drivers handles the integrated NOR flash on NIIET Cortex-M4
7089 based controllers. Flash size and sector layout are auto-configured by the driver.
7090 Main flash memory is called "Bootflash" and has main region and info region.
7091 Info region is NOT memory mapped by default,
7092 but it can replace first part of main region if needed.
7093 Full erase, single and block writes are supported for both main and info regions.
7094 There is additional not memory mapped flash called "Userflash", which
7095 also have division into regions: main and info.
7096 Purpose of userflash - to store system and user settings.
7097 Driver has special commands to perform operations with this memory.
7100 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
7103 Some niietcm4-specific commands are defined:
7105 @deffn {Command} {niietcm4 uflash_read_byte} bank ('main'|'info') address
7106 Read byte from main or info userflash region.
7109 @deffn {Command} {niietcm4 uflash_write_byte} bank ('main'|'info') address value
7110 Write byte to main or info userflash region.
7113 @deffn {Command} {niietcm4 uflash_full_erase} bank
7114 Erase all userflash including info region.
7117 @deffn {Command} {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
7118 Erase sectors of main or info userflash region, starting at sector first up to and including last.
7121 @deffn {Command} {niietcm4 uflash_protect_check} bank ('main'|'info')
7122 Check sectors protect.
7125 @deffn {Command} {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
7126 Protect sectors of main or info userflash region, starting at sector first up to and including last.
7129 @deffn {Command} {niietcm4 bflash_info_remap} bank ('on'|'off')
7130 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
7133 @deffn {Command} {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
7134 Configure external memory interface for boot.
7137 @deffn {Command} {niietcm4 service_mode_erase} bank
7138 Perform emergency erase of all flash (bootflash and userflash).
7141 @deffn {Command} {niietcm4 driver_info} bank
7142 Show information about flash driver.
7147 @deffn {Flash Driver} {npcx}
7148 All versions of the NPCX microcontroller families from Nuvoton include internal
7149 flash. The NPCX flash driver supports the NPCX family of devices. The driver
7150 automatically recognizes the specific version's flash parameters and
7151 autoconfigures itself. The flash bank starts at address 0x64000000.
7154 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
7158 @deffn {Flash Driver} {nrf5}
7159 All members of the nRF51 microcontroller families from Nordic Semiconductor
7160 include internal flash and use ARM Cortex-M0 core. nRF52 family powered
7161 by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported
7162 including BPROT flash protection scheme. nRF52833 and nRF52840 devices are
7163 supported with the exception of security extensions (flash access control list
7167 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
7170 Some nrf5-specific commands are defined:
7172 @deffn {Command} {nrf5 mass_erase}
7173 Erases the contents of the code memory and user information
7174 configuration registers as well. It must be noted that this command
7175 works only for chips that do not have factory pre-programmed region 0
7179 @deffn {Command} {nrf5 info}
7180 Decodes and shows information from FICR and UICR registers.
7185 @deffn {Flash Driver} {ocl}
7186 This driver is an implementation of the ``on chip flash loader''
7187 protocol proposed by Pavel Chromy.
7189 It is a minimalistic command-response protocol intended to be used
7190 over a DCC when communicating with an internal or external flash
7191 loader running from RAM. An example implementation for AT91SAM7x is
7192 available in @file{contrib/loaders/flash/at91sam7x/}.
7195 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
7199 @deffn {Flash Driver} {pic32mx}
7200 The PIC32MX microcontrollers are based on the MIPS 4K cores,
7201 and integrate flash memory.
7204 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
7205 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
7208 @comment numerous *disabled* commands are defined:
7209 @comment - chip_erase ... pointless given flash_erase_address
7210 @comment - lock, unlock ... pointless given protect on/off (yes?)
7211 @comment - pgm_word ... shouldn't bank be deduced from address??
7212 Some pic32mx-specific commands are defined:
7213 @deffn {Command} {pic32mx pgm_word} address value bank
7214 Programs the specified 32-bit @var{value} at the given @var{address}
7215 in the specified chip @var{bank}.
7217 @deffn {Command} {pic32mx unlock} bank
7218 Unlock and erase specified chip @var{bank}.
7219 This will remove any Code Protection.
7223 @deffn {Flash Driver} {psoc4}
7224 All members of the PSoC 41xx/42xx microcontroller family from Cypress
7225 include internal flash and use ARM Cortex-M0 cores.
7226 The driver automatically recognizes a number of these chips using
7227 the chip identification register, and autoconfigures itself.
7229 Note: Erased internal flash reads as 00.
7230 System ROM of PSoC 4 does not implement erase of a flash sector.
7233 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
7236 psoc4-specific commands
7237 @deffn {Command} {psoc4 flash_autoerase} num (on|off)
7238 Enables or disables autoerase mode for a flash bank.
7240 If flash_autoerase is off, use mass_erase before flash programming.
7241 Flash erase command fails if region to erase is not whole flash memory.
7243 If flash_autoerase is on, a sector is both erased and programmed in one
7244 system ROM call. Flash erase command is ignored.
7245 This mode is suitable for gdb load.
7247 The @var{num} parameter is a value shown by @command{flash banks}.
7250 @deffn {Command} {psoc4 mass_erase} num
7251 Erases the contents of the flash memory, protection and security lock.
7253 The @var{num} parameter is a value shown by @command{flash banks}.
7257 @deffn {Flash Driver} {psoc5lp}
7258 All members of the PSoC 5LP microcontroller family from Cypress
7259 include internal program flash and use ARM Cortex-M3 cores.
7260 The driver probes for a number of these chips and autoconfigures itself,
7261 apart from the base address.
7264 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
7267 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
7268 @quotation Attention
7269 If flash operations are performed in ECC-disabled mode, they will also affect
7270 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
7271 then also erase the corresponding 2k data bytes in the 0x48000000 area.
7272 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
7275 Commands defined in the @var{psoc5lp} driver:
7277 @deffn {Command} {psoc5lp mass_erase}
7278 Erases all flash data and ECC/configuration bytes, all flash protection rows,
7279 and all row latches in all flash arrays on the device.
7283 @deffn {Flash Driver} {psoc5lp_eeprom}
7284 All members of the PSoC 5LP microcontroller family from Cypress
7285 include internal EEPROM and use ARM Cortex-M3 cores.
7286 The driver probes for a number of these chips and autoconfigures itself,
7287 apart from the base address.
7290 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
7295 @deffn {Flash Driver} {psoc5lp_nvl}
7296 All members of the PSoC 5LP microcontroller family from Cypress
7297 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
7298 The driver probes for a number of these chips and autoconfigures itself.
7301 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
7304 PSoC 5LP chips have multiple NV Latches:
7307 @item Device Configuration NV Latch - 4 bytes
7308 @item Write Once (WO) NV Latch - 4 bytes
7311 @b{Note:} This driver only implements the Device Configuration NVL.
7313 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
7314 @quotation Attention
7315 Switching ECC mode via write to Device Configuration NVL will require a reset
7316 after successful write.
7320 @deffn {Flash Driver} {psoc6}
7321 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
7322 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
7323 the same Flash/RAM/MMIO address space.
7325 Flash in PSoC6 is split into three regions:
7327 @item Main Flash - this is the main storage for user application.
7328 Total size varies among devices, sector size: 256 kBytes, row size:
7329 512 bytes. Supports erase operation on individual rows.
7330 @item Work Flash - intended to be used as storage for user data
7331 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
7332 row size: 512 bytes.
7333 @item Supervisory Flash - special region which contains device-specific
7334 service data. This region does not support erase operation. Only few rows can
7335 be programmed by the user, most of the rows are read only. Programming
7336 operation will erase row automatically.
7339 All three flash regions are supported by the driver. Flash geometry is detected
7340 automatically by parsing data in SPCIF_GEOMETRY register.
7342 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
7345 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
7347 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
7349 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
7351 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
7353 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
7355 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
7358 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
7360 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
7362 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
7364 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
7366 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
7368 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
7372 psoc6-specific commands
7373 @deffn {Command} {psoc6 reset_halt}
7374 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
7375 When invoked for CM0+ target, it will set break point at application entry point
7376 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
7377 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
7378 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
7381 @deffn {Command} {psoc6 mass_erase} num
7382 Erases the contents given flash bank. The @var{num} parameter is a value shown
7383 by @command{flash banks}.
7384 Note: only Main and Work flash regions support Erase operation.
7388 @deffn {Flash Driver} {rp2040}
7389 Supports RP2040 "Raspberry Pi Pico" microcontroller.
7390 RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
7391 Flash/RAM/MMIO address space. Non-volatile storage is achieved with an
7392 external QSPI flash; a Boot ROM provides helper functions.
7395 flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
7399 @deffn {Flash Driver} {rsl10}
7400 Supports Onsemi RSL10 microcontroller flash memory. Uses functions
7401 stored in ROM to control flash memory interface.
7404 flash bank $_FLASHNAME rsl10 $_FLASHBASE $_FLASHSIZE 0 0 $_TARGETNAME
7407 @deffn {Command} {rsl10 lock} key1 key2 key3 key4
7408 Writes @var{key1 key2 key3 key4} words to @var{0x81044 0x81048 0x8104c
7409 0x8050}. Locks debug port by writing @var{0x4C6F634B} to @var{0x81040}.
7411 To unlock use the @command{rsl10 unlock key1 key2 key3 key4} command.
7414 @deffn {Command} {rsl10 unlock} key1 key2 key3 key4
7415 Unlocks debug port, by writing @var{key1 key2 key3 key4} words to
7416 registers through DAP, and clears @var{0x81040} address in flash to 0x1.
7419 @deffn {Command} {rsl10 mass_erase}
7420 Erases all unprotected flash sectors.
7424 @deffn {Flash Driver} {sim3x}
7425 All members of the SiM3 microcontroller family from Silicon Laboratories
7426 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
7428 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
7429 If this fails, it will use the @var{size} parameter as the size of flash bank.
7432 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
7435 There are 2 commands defined in the @var{sim3x} driver:
7437 @deffn {Command} {sim3x mass_erase}
7438 Erases the complete flash. This is used to unlock the flash.
7439 And this command is only possible when using the SWD interface.
7442 @deffn {Command} {sim3x lock}
7443 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
7447 @deffn {Flash Driver} {stellaris}
7448 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
7449 families from Texas Instruments include internal flash. The driver
7450 automatically recognizes a number of these chips using the chip
7451 identification register, and autoconfigures itself.
7454 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
7457 @deffn {Command} {stellaris recover}
7458 Performs the @emph{Recovering a "Locked" Device} procedure to restore
7459 the flash and its associated nonvolatile registers to their factory
7460 default values (erased). This is the only way to remove flash
7461 protection or re-enable debugging if that capability has been
7464 Note that the final "power cycle the chip" step in this procedure
7465 must be performed by hand, since OpenOCD can't do it.
7467 if more than one Stellaris chip is connected, the procedure is
7468 applied to all of them.
7473 @deffn {Flash Driver} {stm32f1x}
7474 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
7475 from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
7476 families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
7477 The driver also works with GD32VF103 powered by RISC-V core.
7478 The driver automatically recognizes a number of these chips using
7479 the chip identification register, and autoconfigures itself.
7482 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
7485 Note that some devices have been found that have a flash size register that contains
7486 an invalid value, to workaround this issue you can override the probed value used by
7490 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
7493 If you have a target with dual flash banks then define the second bank
7494 as per the following example.
7496 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
7499 Some stm32f1x-specific commands are defined:
7501 @deffn {Command} {stm32f1x lock} num
7502 Locks the entire stm32 device against reading.
7503 The @var{num} parameter is a value shown by @command{flash banks}.
7506 @deffn {Command} {stm32f1x unlock} num
7507 Unlocks the entire stm32 device for reading. This command will cause
7508 a mass erase of the entire stm32 device if previously locked.
7509 The @var{num} parameter is a value shown by @command{flash banks}.
7512 @deffn {Command} {stm32f1x mass_erase} num
7513 Mass erases the entire stm32 device.
7514 The @var{num} parameter is a value shown by @command{flash banks}.
7517 @deffn {Command} {stm32f1x options_read} num
7518 Reads and displays active stm32 option bytes loaded during POR
7519 or upon executing the @command{stm32f1x options_load} command.
7520 The @var{num} parameter is a value shown by @command{flash banks}.
7523 @deffn {Command} {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
7524 Writes the stm32 option byte with the specified values.
7525 The @var{num} parameter is a value shown by @command{flash banks}.
7526 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
7529 @deffn {Command} {stm32f1x options_load} num
7530 Generates a special kind of reset to re-load the stm32 option bytes written
7531 by the @command{stm32f1x options_write} or @command{flash protect} commands
7532 without having to power cycle the target. Not applicable to stm32f1x devices.
7533 The @var{num} parameter is a value shown by @command{flash banks}.
7537 @deffn {Flash Driver} {stm32f2x}
7538 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
7539 include internal flash and use ARM Cortex-M3/M4/M7 cores.
7540 The driver automatically recognizes a number of these chips using
7541 the chip identification register, and autoconfigures itself.
7544 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
7547 If you use OTP (One-Time Programmable) memory define it as a second bank
7548 as per the following example.
7550 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
7553 @deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
7554 Enables or disables OTP write commands for bank @var{num}.
7555 The @var{num} parameter is a value shown by @command{flash banks}.
7558 Note that some devices have been found that have a flash size register that contains
7559 an invalid value, to workaround this issue you can override the probed value used by
7563 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
7566 Some stm32f2x-specific commands are defined:
7568 @deffn {Command} {stm32f2x lock} num
7569 Locks the entire stm32 device.
7570 The @var{num} parameter is a value shown by @command{flash banks}.
7573 @deffn {Command} {stm32f2x unlock} num
7574 Unlocks the entire stm32 device.
7575 The @var{num} parameter is a value shown by @command{flash banks}.
7578 @deffn {Command} {stm32f2x mass_erase} num
7579 Mass erases the entire stm32f2x device.
7580 The @var{num} parameter is a value shown by @command{flash banks}.
7583 @deffn {Command} {stm32f2x options_read} num
7584 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
7585 The @var{num} parameter is a value shown by @command{flash banks}.
7588 @deffn {Command} {stm32f2x options_write} num user_options boot_addr0 boot_addr1
7589 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
7590 Warning: The meaning of the various bits depends on the device, always check datasheet!
7591 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
7592 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
7593 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
7596 @deffn {Command} {stm32f2x optcr2_write} num optcr2
7597 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
7598 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
7602 @deffn {Flash Driver} {stm32h7x}
7603 All members of the STM32H7 microcontroller families from STMicroelectronics
7604 include internal flash and use ARM Cortex-M7 core.
7605 The driver automatically recognizes a number of these chips using
7606 the chip identification register, and autoconfigures itself.
7609 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
7612 Note that some devices have been found that have a flash size register that contains
7613 an invalid value, to workaround this issue you can override the probed value used by
7617 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
7620 Some stm32h7x-specific commands are defined:
7622 @deffn {Command} {stm32h7x lock} num
7623 Locks the entire stm32 device.
7624 The @var{num} parameter is a value shown by @command{flash banks}.
7627 @deffn {Command} {stm32h7x unlock} num
7628 Unlocks the entire stm32 device.
7629 The @var{num} parameter is a value shown by @command{flash banks}.
7632 @deffn {Command} {stm32h7x mass_erase} num
7633 Mass erases the entire stm32h7x device.
7634 The @var{num} parameter is a value shown by @command{flash banks}.
7637 @deffn {Command} {stm32h7x option_read} num reg_offset
7638 Reads an option byte register from the stm32h7x device.
7639 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7640 is the register offset of the option byte to read from the used bank registers' base.
7641 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
7646 stm32h7x option_read 0 0x1c
7648 stm32h7x option_read 0 0x38
7650 stm32h7x option_read 1 0x38
7654 @deffn {Command} {stm32h7x option_write} num reg_offset value [reg_mask]
7655 Writes an option byte register of the stm32h7x device.
7656 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7657 is the register offset of the option byte to write from the used bank register base,
7658 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
7663 # swap bank 1 and bank 2 in dual bank devices
7664 # by setting SWAP_BANK_OPT bit in OPTSR_PRG
7665 stm32h7x option_write 0 0x20 0x8000000 0x8000000
7670 @deffn {Flash Driver} {stm32lx}
7671 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
7672 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
7673 The driver automatically recognizes a number of these chips using
7674 the chip identification register, and autoconfigures itself.
7677 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
7680 Note that some devices have been found that have a flash size register that contains
7681 an invalid value, to workaround this issue you can override the probed value used by
7682 the flash driver. If you use 0 as the bank base address, it tells the
7683 driver to autodetect the bank location assuming you're configuring the
7687 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
7690 Some stm32lx-specific commands are defined:
7692 @deffn {Command} {stm32lx lock} num
7693 Locks the entire stm32 device.
7694 The @var{num} parameter is a value shown by @command{flash banks}.
7697 @deffn {Command} {stm32lx unlock} num
7698 Unlocks the entire stm32 device.
7699 The @var{num} parameter is a value shown by @command{flash banks}.
7702 @deffn {Command} {stm32lx mass_erase} num
7703 Mass erases the entire stm32lx device (all flash banks and EEPROM
7704 data). This is the only way to unlock a protected flash (unless RDP
7705 Level is 2 which can't be unlocked at all).
7706 The @var{num} parameter is a value shown by @command{flash banks}.
7710 @deffn {Flash Driver} {stm32l4x}
7711 All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
7712 microcontroller families from STMicroelectronics include internal flash
7713 and use ARM Cortex-M0+, M4 and M33 cores.
7714 The driver automatically recognizes a number of these chips using
7715 the chip identification register, and autoconfigures itself.
7718 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7721 If you use OTP (One-Time Programmable) memory define it as a second bank
7722 as per the following example.
7724 flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
7727 @deffn {Command} {stm32l4x otp} num (@option{enable}|@option{disable}|@option{show})
7728 Enables or disables OTP write commands for bank @var{num}.
7729 The @var{num} parameter is a value shown by @command{flash banks}.
7732 Note that some devices have been found that have a flash size register that contains
7733 an invalid value, to workaround this issue you can override the probed value used by
7734 the flash driver. However, specifying a wrong value might lead to a completely
7735 wrong flash layout, so this feature must be used carefully.
7738 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7741 Some stm32l4x-specific commands are defined:
7743 @deffn {Command} {stm32l4x lock} num
7744 Locks the entire stm32 device.
7745 The @var{num} parameter is a value shown by @command{flash banks}.
7747 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7750 @deffn {Command} {stm32l4x unlock} num
7751 Unlocks the entire stm32 device.
7752 The @var{num} parameter is a value shown by @command{flash banks}.
7754 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7757 @deffn {Command} {stm32l4x mass_erase} num
7758 Mass erases the entire stm32l4x device.
7759 The @var{num} parameter is a value shown by @command{flash banks}.
7762 @deffn {Command} {stm32l4x option_read} num reg_offset
7763 Reads an option byte register from the stm32l4x device.
7764 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7765 is the register offset of the Option byte to read.
7767 For example to read the FLASH_OPTR register:
7769 stm32l4x option_read 0 0x20
7770 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
7771 # Option Register (for STM32WBx): <0x58004020> = ...
7772 # The correct flash base address will be used automatically
7775 The above example will read out the FLASH_OPTR register which contains the RDP
7776 option byte, Watchdog configuration, BOR level etc.
7779 @deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
7780 Write an option byte register of the stm32l4x device.
7781 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7782 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
7783 to apply when writing the register (only bits with a '1' will be touched).
7785 @emph{Note:} To apply the option bytes change immediately, use @command{stm32l4x option_load}.
7787 For example to write the WRP1AR option bytes:
7789 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
7792 The above example will write the WRP1AR option register configuring the Write protection
7793 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
7794 This will effectively write protect all sectors in flash bank 1.
7797 @deffn {Command} {stm32l4x wrp_info} num [device_bank]
7798 List the protected areas using WRP.
7799 The @var{num} parameter is a value shown by @command{flash banks}.
7800 @var{device_bank} parameter is optional, possible values 'bank1' or 'bank2',
7801 if not specified, the command will display the whole flash protected areas.
7803 @b{Note:} @var{device_bank} is different from banks created using @code{flash bank}.
7804 Devices supported in this flash driver, can have main flash memory organized
7805 in single or dual-banks mode.
7806 Thus the usage of @var{device_bank} is meaningful only in dual-bank mode, to get
7807 write protected areas in a specific @var{device_bank}
7811 @deffn {Command} {stm32l4x option_load} num
7812 Forces a re-load of the option byte registers. Will cause a system reset of the device.
7813 The @var{num} parameter is a value shown by @command{flash banks}.
7816 @deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
7817 Enables or disables Global TrustZone Security, using the TZEN option bit.
7818 If neither @option{enabled} nor @option{disable} are specified, the command will display
7819 the TrustZone status.
7820 @emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
7821 @emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
7825 @deffn {Flash Driver} {str7x}
7826 All members of the STR7 microcontroller family from STMicroelectronics
7827 include internal flash and use ARM7TDMI cores.
7828 The @var{str7x} driver defines one mandatory parameter, @var{variant},
7829 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
7832 flash bank $_FLASHNAME str7x \
7833 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
7836 @deffn {Command} {str7x disable_jtag} bank
7837 Activate the Debug/Readout protection mechanism
7838 for the specified flash bank.
7842 @deffn {Flash Driver} {str9x}
7843 Most members of the STR9 microcontroller family from STMicroelectronics
7844 include internal flash and use ARM966E cores.
7845 The str9 needs the flash controller to be configured using
7846 the @command{str9x flash_config} command prior to Flash programming.
7849 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
7850 str9x flash_config 0 4 2 0 0x80000
7853 @deffn {Command} {str9x flash_config} num bbsr nbbsr bbadr nbbadr
7854 Configures the str9 flash controller.
7855 The @var{num} parameter is a value shown by @command{flash banks}.
7858 @item @var{bbsr} - Boot Bank Size register
7859 @item @var{nbbsr} - Non Boot Bank Size register
7860 @item @var{bbadr} - Boot Bank Start Address register
7861 @item @var{nbbadr} - Boot Bank Start Address register
7867 @deffn {Flash Driver} {str9xpec}
7870 Only use this driver for locking/unlocking the device or configuring the option bytes.
7871 Use the standard str9 driver for programming.
7872 Before using the flash commands the turbo mode must be enabled using the
7873 @command{str9xpec enable_turbo} command.
7875 Here is some background info to help
7876 you better understand how this driver works. OpenOCD has two flash drivers for
7880 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7881 flash programming as it is faster than the @option{str9xpec} driver.
7883 Direct programming @option{str9xpec} using the flash controller. This is an
7884 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7885 core does not need to be running to program using this flash driver. Typical use
7886 for this driver is locking/unlocking the target and programming the option bytes.
7889 Before we run any commands using the @option{str9xpec} driver we must first disable
7890 the str9 core. This example assumes the @option{str9xpec} driver has been
7891 configured for flash bank 0.
7893 # assert srst, we do not want core running
7894 # while accessing str9xpec flash driver
7896 # turn off target polling
7899 str9xpec enable_turbo 0
7901 str9xpec options_read 0
7902 # re-enable str9 core
7903 str9xpec disable_turbo 0
7907 The above example will read the str9 option bytes.
7908 When performing a unlock remember that you will not be able to halt the str9 - it
7909 has been locked. Halting the core is not required for the @option{str9xpec} driver
7910 as mentioned above, just issue the commands above manually or from a telnet prompt.
7912 Several str9xpec-specific commands are defined:
7914 @deffn {Command} {str9xpec disable_turbo} num
7915 Restore the str9 into JTAG chain.
7918 @deffn {Command} {str9xpec enable_turbo} num
7919 Enable turbo mode, will simply remove the str9 from the chain and talk
7920 directly to the embedded flash controller.
7923 @deffn {Command} {str9xpec lock} num
7924 Lock str9 device. The str9 will only respond to an unlock command that will
7928 @deffn {Command} {str9xpec part_id} num
7929 Prints the part identifier for bank @var{num}.
7932 @deffn {Command} {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7933 Configure str9 boot bank.
7936 @deffn {Command} {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
7937 Configure str9 lvd source.
7940 @deffn {Command} {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
7941 Configure str9 lvd threshold.
7944 @deffn {Command} {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
7945 Configure str9 lvd reset warning source.
7948 @deffn {Command} {str9xpec options_read} num
7949 Read str9 option bytes.
7952 @deffn {Command} {str9xpec options_write} num
7953 Write str9 option bytes.
7956 @deffn {Command} {str9xpec unlock} num
7962 @deffn {Flash Driver} {swm050}
7964 All members of the swm050 microcontroller family from Foshan Synwit Tech.
7967 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
7970 One swm050-specific command is defined:
7972 @deffn {Command} {swm050 mass_erase} bank_id
7973 Erases the entire flash bank.
7979 @deffn {Flash Driver} {tms470}
7980 Most members of the TMS470 microcontroller family from Texas Instruments
7981 include internal flash and use ARM7TDMI cores.
7982 This driver doesn't require the chip and bus width to be specified.
7984 Some tms470-specific commands are defined:
7986 @deffn {Command} {tms470 flash_keyset} key0 key1 key2 key3
7987 Saves programming keys in a register, to enable flash erase and write commands.
7990 @deffn {Command} {tms470 osc_megahertz} clock_mhz
7991 Reports the clock speed, which is used to calculate timings.
7994 @deffn {Command} {tms470 plldis} (0|1)
7995 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
8000 @deffn {Flash Driver} {w600}
8001 W60x series Wi-Fi SoC from WinnerMicro
8002 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
8003 The @var{w600} driver uses the @var{target} parameter to select the
8004 correct bank config.
8007 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
8011 @deffn {Flash Driver} {xmc1xxx}
8012 All members of the XMC1xxx microcontroller family from Infineon.
8013 This driver does not require the chip and bus width to be specified.
8016 @deffn {Flash Driver} {xmc4xxx}
8017 All members of the XMC4xxx microcontroller family from Infineon.
8018 This driver does not require the chip and bus width to be specified.
8020 Some xmc4xxx-specific commands are defined:
8022 @deffn {Command} {xmc4xxx flash_password} bank_id passwd1 passwd2
8023 Saves flash protection passwords which are used to lock the user flash
8026 @deffn {Command} {xmc4xxx flash_unprotect} bank_id user_level[0-1]
8027 Removes Flash write protection from the selected user bank
8032 @section NAND Flash Commands
8035 Compared to NOR or SPI flash, NAND devices are inexpensive
8036 and high density. Today's NAND chips, and multi-chip modules,
8037 commonly hold multiple GigaBytes of data.
8039 NAND chips consist of a number of ``erase blocks'' of a given
8040 size (such as 128 KBytes), each of which is divided into a
8041 number of pages (of perhaps 512 or 2048 bytes each). Each
8042 page of a NAND flash has an ``out of band'' (OOB) area to hold
8043 Error Correcting Code (ECC) and other metadata, usually 16 bytes
8044 of OOB for every 512 bytes of page data.
8046 One key characteristic of NAND flash is that its error rate
8047 is higher than that of NOR flash. In normal operation, that
8048 ECC is used to correct and detect errors. However, NAND
8049 blocks can also wear out and become unusable; those blocks
8050 are then marked "bad". NAND chips are even shipped from the
8051 manufacturer with a few bad blocks. The highest density chips
8052 use a technology (MLC) that wears out more quickly, so ECC
8053 support is increasingly important as a way to detect blocks
8054 that have begun to fail, and help to preserve data integrity
8055 with techniques such as wear leveling.
8057 Software is used to manage the ECC. Some controllers don't
8058 support ECC directly; in those cases, software ECC is used.
8059 Other controllers speed up the ECC calculations with hardware.
8060 Single-bit error correction hardware is routine. Controllers
8061 geared for newer MLC chips may correct 4 or more errors for
8062 every 512 bytes of data.
8064 You will need to make sure that any data you write using
8065 OpenOCD includes the appropriate kind of ECC. For example,
8066 that may mean passing the @code{oob_softecc} flag when
8067 writing NAND data, or ensuring that the correct hardware
8070 The basic steps for using NAND devices include:
8072 @item Declare via the command @command{nand device}
8073 @* Do this in a board-specific configuration file,
8074 passing parameters as needed by the controller.
8075 @item Configure each device using @command{nand probe}.
8076 @* Do this only after the associated target is set up,
8077 such as in its reset-init script or in procures defined
8078 to access that device.
8079 @item Operate on the flash via @command{nand subcommand}
8080 @* Often commands to manipulate the flash are typed by a human, or run
8081 via a script in some automated way. Common task include writing a
8082 boot loader, operating system, or other data needed to initialize or
8086 @b{NOTE:} At the time this text was written, the largest NAND
8087 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
8088 This is because the variables used to hold offsets and lengths
8089 are only 32 bits wide.
8090 (Larger chips may work in some cases, unless an offset or length
8091 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
8092 Some larger devices will work, since they are actually multi-chip
8093 modules with two smaller chips and individual chipselect lines.
8095 @anchor{nandconfiguration}
8096 @subsection NAND Configuration Commands
8097 @cindex NAND configuration
8099 NAND chips must be declared in configuration scripts,
8100 plus some additional configuration that's done after
8101 OpenOCD has initialized.
8103 @deffn {Config Command} {nand device} name driver target [configparams...]
8104 Declares a NAND device, which can be read and written to
8105 after it has been configured through @command{nand probe}.
8106 In OpenOCD, devices are single chips; this is unlike some
8107 operating systems, which may manage multiple chips as if
8108 they were a single (larger) device.
8109 In some cases, configuring a device will activate extra
8110 commands; see the controller-specific documentation.
8112 @b{NOTE:} This command is not available after OpenOCD
8113 initialization has completed. Use it in board specific
8114 configuration files, not interactively.
8117 @item @var{name} ... may be used to reference the NAND bank
8118 in most other NAND commands. A number is also available.
8119 @item @var{driver} ... identifies the NAND controller driver
8120 associated with the NAND device being declared.
8121 @xref{nanddriverlist,,NAND Driver List}.
8122 @item @var{target} ... names the target used when issuing
8123 commands to the NAND controller.
8124 @comment Actually, it's currently a controller-specific parameter...
8125 @item @var{configparams} ... controllers may support, or require,
8126 additional parameters. See the controller-specific documentation
8127 for more information.
8131 @deffn {Command} {nand list}
8132 Prints a summary of each device declared
8133 using @command{nand device}, numbered from zero.
8134 Note that un-probed devices show no details.
8137 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
8138 blocksize: 131072, blocks: 8192
8139 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
8140 blocksize: 131072, blocks: 8192
8145 @deffn {Command} {nand probe} num
8146 Probes the specified device to determine key characteristics
8147 like its page and block sizes, and how many blocks it has.
8148 The @var{num} parameter is the value shown by @command{nand list}.
8149 You must (successfully) probe a device before you can use
8150 it with most other NAND commands.
8153 @subsection Erasing, Reading, Writing to NAND Flash
8155 @deffn {Command} {nand dump} num filename offset length [oob_option]
8156 @cindex NAND reading
8157 Reads binary data from the NAND device and writes it to the file,
8158 starting at the specified offset.
8159 The @var{num} parameter is the value shown by @command{nand list}.
8161 Use a complete path name for @var{filename}, so you don't depend
8162 on the directory used to start the OpenOCD server.
8164 The @var{offset} and @var{length} must be exact multiples of the
8165 device's page size. They describe a data region; the OOB data
8166 associated with each such page may also be accessed.
8168 @b{NOTE:} At the time this text was written, no error correction
8169 was done on the data that's read, unless raw access was disabled
8170 and the underlying NAND controller driver had a @code{read_page}
8171 method which handled that error correction.
8173 By default, only page data is saved to the specified file.
8174 Use an @var{oob_option} parameter to save OOB data:
8176 @item no oob_* parameter
8177 @*Output file holds only page data; OOB is discarded.
8178 @item @code{oob_raw}
8179 @*Output file interleaves page data and OOB data;
8180 the file will be longer than "length" by the size of the
8181 spare areas associated with each data page.
8182 Note that this kind of "raw" access is different from
8183 what's implied by @command{nand raw_access}, which just
8184 controls whether a hardware-aware access method is used.
8185 @item @code{oob_only}
8186 @*Output file has only raw OOB data, and will
8187 be smaller than "length" since it will contain only the
8188 spare areas associated with each data page.
8192 @deffn {Command} {nand erase} num [offset length]
8193 @cindex NAND erasing
8194 @cindex NAND programming
8195 Erases blocks on the specified NAND device, starting at the
8196 specified @var{offset} and continuing for @var{length} bytes.
8197 Both of those values must be exact multiples of the device's
8198 block size, and the region they specify must fit entirely in the chip.
8199 If those parameters are not specified,
8200 the whole NAND chip will be erased.
8201 The @var{num} parameter is the value shown by @command{nand list}.
8203 @b{NOTE:} This command will try to erase bad blocks, when told
8204 to do so, which will probably invalidate the manufacturer's bad
8206 For the remainder of the current server session, @command{nand info}
8207 will still report that the block ``is'' bad.
8210 @deffn {Command} {nand write} num filename offset [option...]
8211 @cindex NAND writing
8212 @cindex NAND programming
8213 Writes binary data from the file into the specified NAND device,
8214 starting at the specified offset. Those pages should already
8215 have been erased; you can't change zero bits to one bits.
8216 The @var{num} parameter is the value shown by @command{nand list}.
8218 Use a complete path name for @var{filename}, so you don't depend
8219 on the directory used to start the OpenOCD server.
8221 The @var{offset} must be an exact multiple of the device's page size.
8222 All data in the file will be written, assuming it doesn't run
8223 past the end of the device.
8224 Only full pages are written, and any extra space in the last
8225 page will be filled with 0xff bytes. (That includes OOB data,
8226 if that's being written.)
8228 @b{NOTE:} At the time this text was written, bad blocks are
8229 ignored. That is, this routine will not skip bad blocks,
8230 but will instead try to write them. This can cause problems.
8232 Provide at most one @var{option} parameter. With some
8233 NAND drivers, the meanings of these parameters may change
8234 if @command{nand raw_access} was used to disable hardware ECC.
8236 @item no oob_* parameter
8237 @*File has only page data, which is written.
8238 If raw access is in use, the OOB area will not be written.
8239 Otherwise, if the underlying NAND controller driver has
8240 a @code{write_page} routine, that routine may write the OOB
8241 with hardware-computed ECC data.
8242 @item @code{oob_only}
8243 @*File has only raw OOB data, which is written to the OOB area.
8244 Each page's data area stays untouched. @i{This can be a dangerous
8245 option}, since it can invalidate the ECC data.
8246 You may need to force raw access to use this mode.
8247 @item @code{oob_raw}
8248 @*File interleaves data and OOB data, both of which are written
8249 If raw access is enabled, the data is written first, then the
8251 Otherwise, if the underlying NAND controller driver has
8252 a @code{write_page} routine, that routine may modify the OOB
8253 before it's written, to include hardware-computed ECC data.
8254 @item @code{oob_softecc}
8255 @*File has only page data, which is written.
8256 The OOB area is filled with 0xff, except for a standard 1-bit
8257 software ECC code stored in conventional locations.
8258 You might need to force raw access to use this mode, to prevent
8259 the underlying driver from applying hardware ECC.
8260 @item @code{oob_softecc_kw}
8261 @*File has only page data, which is written.
8262 The OOB area is filled with 0xff, except for a 4-bit software ECC
8263 specific to the boot ROM in Marvell Kirkwood SoCs.
8264 You might need to force raw access to use this mode, to prevent
8265 the underlying driver from applying hardware ECC.
8269 @deffn {Command} {nand verify} num filename offset [option...]
8270 @cindex NAND verification
8271 @cindex NAND programming
8272 Verify the binary data in the file has been programmed to the
8273 specified NAND device, starting at the specified offset.
8274 The @var{num} parameter is the value shown by @command{nand list}.
8276 Use a complete path name for @var{filename}, so you don't depend
8277 on the directory used to start the OpenOCD server.
8279 The @var{offset} must be an exact multiple of the device's page size.
8280 All data in the file will be read and compared to the contents of the
8281 flash, assuming it doesn't run past the end of the device.
8282 As with @command{nand write}, only full pages are verified, so any extra
8283 space in the last page will be filled with 0xff bytes.
8285 The same @var{options} accepted by @command{nand write},
8286 and the file will be processed similarly to produce the buffers that
8287 can be compared against the contents produced from @command{nand dump}.
8289 @b{NOTE:} This will not work when the underlying NAND controller
8290 driver's @code{write_page} routine must update the OOB with a
8291 hardware-computed ECC before the data is written. This limitation may
8292 be removed in a future release.
8295 @subsection Other NAND commands
8296 @cindex NAND other commands
8298 @deffn {Command} {nand check_bad_blocks} num [offset length]
8299 Checks for manufacturer bad block markers on the specified NAND
8300 device. If no parameters are provided, checks the whole
8301 device; otherwise, starts at the specified @var{offset} and
8302 continues for @var{length} bytes.
8303 Both of those values must be exact multiples of the device's
8304 block size, and the region they specify must fit entirely in the chip.
8305 The @var{num} parameter is the value shown by @command{nand list}.
8307 @b{NOTE:} Before using this command you should force raw access
8308 with @command{nand raw_access enable} to ensure that the underlying
8309 driver will not try to apply hardware ECC.
8312 @deffn {Command} {nand info} num
8313 The @var{num} parameter is the value shown by @command{nand list}.
8314 This prints the one-line summary from "nand list", plus for
8315 devices which have been probed this also prints any known
8316 status for each block.
8319 @deffn {Command} {nand raw_access} num (@option{enable}|@option{disable})
8320 Sets or clears an flag affecting how page I/O is done.
8321 The @var{num} parameter is the value shown by @command{nand list}.
8323 This flag is cleared (disabled) by default, but changing that
8324 value won't affect all NAND devices. The key factor is whether
8325 the underlying driver provides @code{read_page} or @code{write_page}
8326 methods. If it doesn't provide those methods, the setting of
8327 this flag is irrelevant; all access is effectively ``raw''.
8329 When those methods exist, they are normally used when reading
8330 data (@command{nand dump} or reading bad block markers) or
8331 writing it (@command{nand write}). However, enabling
8332 raw access (setting the flag) prevents use of those methods,
8333 bypassing hardware ECC logic.
8334 @i{This can be a dangerous option}, since writing blocks
8335 with the wrong ECC data can cause them to be marked as bad.
8338 @anchor{nanddriverlist}
8339 @subsection NAND Driver List
8340 As noted above, the @command{nand device} command allows
8341 driver-specific options and behaviors.
8342 Some controllers also activate controller-specific commands.
8344 @deffn {NAND Driver} {at91sam9}
8345 This driver handles the NAND controllers found on AT91SAM9 family chips from
8346 Atmel. It takes two extra parameters: address of the NAND chip;
8347 address of the ECC controller.
8349 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
8351 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
8352 @code{read_page} methods are used to utilize the ECC hardware unless they are
8353 disabled by using the @command{nand raw_access} command. There are four
8354 additional commands that are needed to fully configure the AT91SAM9 NAND
8355 controller. Two are optional; most boards use the same wiring for ALE/CLE:
8356 @deffn {Config Command} {at91sam9 cle} num addr_line
8357 Configure the address line used for latching commands. The @var{num}
8358 parameter is the value shown by @command{nand list}.
8360 @deffn {Config Command} {at91sam9 ale} num addr_line
8361 Configure the address line used for latching addresses. The @var{num}
8362 parameter is the value shown by @command{nand list}.
8365 For the next two commands, it is assumed that the pins have already been
8366 properly configured for input or output.
8367 @deffn {Config Command} {at91sam9 rdy_busy} num pio_base_addr pin
8368 Configure the RDY/nBUSY input from the NAND device. The @var{num}
8369 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8370 is the base address of the PIO controller and @var{pin} is the pin number.
8372 @deffn {Config Command} {at91sam9 ce} num pio_base_addr pin
8373 Configure the chip enable input to the NAND device. The @var{num}
8374 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8375 is the base address of the PIO controller and @var{pin} is the pin number.
8379 @deffn {NAND Driver} {davinci}
8380 This driver handles the NAND controllers found on DaVinci family
8381 chips from Texas Instruments.
8382 It takes three extra parameters:
8383 address of the NAND chip;
8384 hardware ECC mode to use (@option{hwecc1},
8385 @option{hwecc4}, @option{hwecc4_infix});
8386 address of the AEMIF controller on this processor.
8388 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
8390 All DaVinci processors support the single-bit ECC hardware,
8391 and newer ones also support the four-bit ECC hardware.
8392 The @code{write_page} and @code{read_page} methods are used
8393 to implement those ECC modes, unless they are disabled using
8394 the @command{nand raw_access} command.
8397 @deffn {NAND Driver} {lpc3180}
8398 These controllers require an extra @command{nand device}
8399 parameter: the clock rate used by the controller.
8400 @deffn {Command} {lpc3180 select} num [mlc|slc]
8401 Configures use of the MLC or SLC controller mode.
8402 MLC implies use of hardware ECC.
8403 The @var{num} parameter is the value shown by @command{nand list}.
8406 At this writing, this driver includes @code{write_page}
8407 and @code{read_page} methods. Using @command{nand raw_access}
8408 to disable those methods will prevent use of hardware ECC
8409 in the MLC controller mode, but won't change SLC behavior.
8411 @comment current lpc3180 code won't issue 5-byte address cycles
8413 @deffn {NAND Driver} {mx3}
8414 This driver handles the NAND controller in i.MX31. The mxc driver
8415 should work for this chip as well.
8418 @deffn {NAND Driver} {mxc}
8419 This driver handles the NAND controller found in Freescale i.MX
8420 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
8421 The driver takes 3 extra arguments, chip (@option{mx27},
8422 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
8423 and optionally if bad block information should be swapped between
8424 main area and spare area (@option{biswap}), defaults to off.
8426 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
8428 @deffn {Command} {mxc biswap} bank_num [enable|disable]
8429 Turns on/off bad block information swapping from main area,
8430 without parameter query status.
8434 @deffn {NAND Driver} {orion}
8435 These controllers require an extra @command{nand device}
8436 parameter: the address of the controller.
8438 nand device orion 0xd8000000
8440 These controllers don't define any specialized commands.
8441 At this writing, their drivers don't include @code{write_page}
8442 or @code{read_page} methods, so @command{nand raw_access} won't
8443 change any behavior.
8446 @deffn {NAND Driver} {s3c2410}
8447 @deffnx {NAND Driver} {s3c2412}
8448 @deffnx {NAND Driver} {s3c2440}
8449 @deffnx {NAND Driver} {s3c2443}
8450 @deffnx {NAND Driver} {s3c6400}
8451 These S3C family controllers don't have any special
8452 @command{nand device} options, and don't define any
8453 specialized commands.
8454 At this writing, their drivers don't include @code{write_page}
8455 or @code{read_page} methods, so @command{nand raw_access} won't
8456 change any behavior.
8459 @node Flash Programming
8460 @chapter Flash Programming
8462 OpenOCD implements numerous ways to program the target flash, whether internal or external.
8463 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
8464 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
8466 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
8467 OpenOCD will program/verify/reset the target and optionally shutdown.
8469 The script is executed as follows and by default the following actions will be performed.
8471 @item 'init' is executed.
8472 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
8473 @item @code{flash write_image} is called to erase and write any flash using the filename given.
8474 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
8475 @item @code{verify_image} is called if @option{verify} parameter is given.
8476 @item @code{reset run} is called if @option{reset} parameter is given.
8477 @item OpenOCD is shutdown if @option{exit} parameter is given.
8480 An example of usage is given below. @xref{program}.
8483 # program and verify using elf/hex/s19. verify and reset
8484 # are optional parameters
8485 openocd -f board/stm32f3discovery.cfg \
8486 -c "program filename.elf verify reset exit"
8488 # binary files need the flash address passing
8489 openocd -f board/stm32f3discovery.cfg \
8490 -c "program filename.bin exit 0x08000000"
8493 @node PLD/FPGA Commands
8494 @chapter PLD/FPGA Commands
8498 Programmable Logic Devices (PLDs) and the more flexible
8499 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
8500 OpenOCD can support programming them.
8501 Although PLDs are generally restrictive (cells are less functional, and
8502 there are no special purpose cells for memory or computational tasks),
8503 they share the same OpenOCD infrastructure.
8504 Accordingly, both are called PLDs here.
8506 @section PLD/FPGA Configuration and Commands
8508 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
8509 OpenOCD maintains a list of PLDs available for use in various commands.
8510 Also, each such PLD requires a driver.
8512 They are referenced by the number shown by the @command{pld devices} command,
8513 and new PLDs are defined by @command{pld device driver_name}.
8515 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
8516 Defines a new PLD device, supported by driver @var{driver_name},
8517 using the TAP named @var{tap_name}.
8518 The driver may make use of any @var{driver_options} to configure its
8522 @deffn {Command} {pld devices}
8523 Lists the PLDs and their numbers.
8526 @deffn {Command} {pld load} num filename
8527 Loads the file @file{filename} into the PLD identified by @var{num}.
8528 The file format must be inferred by the driver.
8531 @section PLD/FPGA Drivers, Options, and Commands
8533 Drivers may support PLD-specific options to the @command{pld device}
8534 definition command, and may also define commands usable only with
8535 that particular type of PLD.
8537 @deffn {FPGA Driver} {virtex2} [no_jstart]
8538 Virtex-II is a family of FPGAs sold by Xilinx.
8539 It supports the IEEE 1532 standard for In-System Configuration (ISC).
8541 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
8542 loading the bitstream. While required for Series2, Series3, and Series6, it
8543 breaks bitstream loading on Series7.
8545 @deffn {Command} {virtex2 read_stat} num
8546 Reads and displays the Virtex-II status register (STAT)
8551 @node General Commands
8552 @chapter General Commands
8555 The commands documented in this chapter here are common commands that
8556 you, as a human, may want to type and see the output of. Configuration type
8557 commands are documented elsewhere.
8561 @item @b{Source Of Commands}
8562 @* OpenOCD commands can occur in a configuration script (discussed
8563 elsewhere) or typed manually by a human or supplied programmatically,
8564 or via one of several TCP/IP Ports.
8566 @item @b{From the human}
8567 @* A human should interact with the telnet interface (default port: 4444)
8568 or via GDB (default port 3333).
8570 To issue commands from within a GDB session, use the @option{monitor}
8571 command, e.g. use @option{monitor poll} to issue the @option{poll}
8572 command. All output is relayed through the GDB session.
8574 @item @b{Machine Interface}
8575 The Tcl interface's intent is to be a machine interface. The default Tcl
8580 @section Server Commands
8582 @deffn {Command} {exit}
8583 Exits the current telnet session.
8586 @deffn {Command} {help} [string]
8587 With no parameters, prints help text for all commands.
8588 Otherwise, prints each helptext containing @var{string}.
8589 Not every command provides helptext.
8591 Configuration commands, and commands valid at any time, are
8592 explicitly noted in parenthesis.
8593 In most cases, no such restriction is listed; this indicates commands
8594 which are only available after the configuration stage has completed.
8597 @deffn {Command} {usage} [string]
8598 With no parameters, prints usage text for all commands. Otherwise,
8599 prints all usage text of which command, help text, and usage text
8600 containing @var{string}.
8601 Not every command provides helptext.
8604 @deffn {Command} {sleep} msec [@option{busy}]
8605 Wait for at least @var{msec} milliseconds before resuming.
8606 If @option{busy} is passed, busy-wait instead of sleeping.
8607 (This option is strongly discouraged.)
8608 Useful in connection with script files
8609 (@command{script} command and @command{target_name} configuration).
8612 @deffn {Command} {shutdown} [@option{error}]
8613 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
8614 other). If option @option{error} is used, OpenOCD will return a
8615 non-zero exit code to the parent process.
8617 If user types CTRL-C or kills OpenOCD, the command @command{shutdown}
8618 will be automatically executed to cause OpenOCD to exit.
8620 It is possible to specify, in the TCL list @var{pre_shutdown_commands} , a
8621 set of commands to be automatically executed before @command{shutdown} , e.g.:
8623 lappend pre_shutdown_commands @{echo "Goodbye, my friend ..."@}
8624 lappend pre_shutdown_commands @{echo "see you soon !"@}
8626 The commands in the list will be executed (in the same order they occupy
8627 in the list) before OpenOCD exits. If one of the commands in the list
8628 fails, then the remaining commands are not executed anymore while OpenOCD
8629 will proceed to quit.
8633 @deffn {Command} {debug_level} [n]
8634 @cindex message level
8635 Display debug level.
8636 If @var{n} (from 0..4) is provided, then set it to that level.
8637 This affects the kind of messages sent to the server log.
8638 Level 0 is error messages only;
8639 level 1 adds warnings;
8640 level 2 adds informational messages;
8641 level 3 adds debugging messages;
8642 and level 4 adds verbose low-level debug messages.
8643 The default is level 2, but that can be overridden on
8644 the command line along with the location of that log
8645 file (which is normally the server's standard output).
8649 @deffn {Command} {echo} [-n] message
8650 Logs a message at "user" priority.
8651 Option "-n" suppresses trailing newline.
8653 echo "Downloading kernel -- please wait"
8657 @deffn {Command} {log_output} [filename | "default"]
8658 Redirect logging to @var{filename} or set it back to default output;
8659 the default log output channel is stderr.
8662 @deffn {Command} {add_script_search_dir} [directory]
8663 Add @var{directory} to the file/script search path.
8666 @deffn {Config Command} {bindto} [@var{name}]
8667 Specify hostname or IPv4 address on which to listen for incoming
8668 TCP/IP connections. By default, OpenOCD will listen on the loopback
8669 interface only. If your network environment is safe, @code{bindto
8670 0.0.0.0} can be used to cover all available interfaces.
8673 @anchor{targetstatehandling}
8674 @section Target State handling
8677 @cindex target initialization
8679 In this section ``target'' refers to a CPU configured as
8680 shown earlier (@pxref{CPU Configuration}).
8681 These commands, like many, implicitly refer to
8682 a current target which is used to perform the
8683 various operations. The current target may be changed
8684 by using @command{targets} command with the name of the
8685 target which should become current.
8687 @deffn {Command} {reg} [(number|name) [(value|'force')]]
8688 Access a single register by @var{number} or by its @var{name}.
8689 The target must generally be halted before access to CPU core
8690 registers is allowed. Depending on the hardware, some other
8691 registers may be accessible while the target is running.
8693 @emph{With no arguments}:
8694 list all available registers for the current target,
8695 showing number, name, size, value, and cache status.
8696 For valid entries, a value is shown; valid entries
8697 which are also dirty (and will be written back later)
8698 are flagged as such.
8700 @emph{With number/name}: display that register's value.
8701 Use @var{force} argument to read directly from the target,
8702 bypassing any internal cache.
8704 @emph{With both number/name and value}: set register's value.
8705 Writes may be held in a writeback cache internal to OpenOCD,
8706 so that setting the value marks the register as dirty instead
8707 of immediately flushing that value. Resuming CPU execution
8708 (including by single stepping) or otherwise activating the
8709 relevant module will flush such values.
8711 Cores may have surprisingly many registers in their
8712 Debug and trace infrastructure:
8717 (0) r0 (/32): 0x0000D3C2 (dirty)
8718 (1) r1 (/32): 0xFD61F31C
8721 (164) ETM_contextid_comparator_mask (/32)
8726 @deffn {Command} {set_reg} dict
8727 Set register values of the target.
8730 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
8733 For example, the following command sets the value 0 to the program counter (pc)
8734 register and 0x1000 to the stack pointer (sp) register:
8737 set_reg @{pc 0 sp 0x1000@}
8741 @deffn {Command} {get_reg} [-force] list
8742 Get register values from the target and return them as Tcl dictionary with pairs
8743 of register names and values.
8744 If option "-force" is set, the register values are read directly from the
8745 target, bypassing any caching.
8748 @item @var{list} ... List of register names
8751 For example, the following command retrieves the values from the program
8752 counter (pc) and stack pointer (sp) register:
8759 @deffn {Command} {write_memory} address width data ['phys']
8760 This function provides an efficient way to write to the target memory from a Tcl
8764 @item @var{address} ... target memory address
8765 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
8766 @item @var{data} ... Tcl list with the elements to write
8767 @item ['phys'] ... treat the memory address as physical instead of virtual address
8770 For example, the following command writes two 32 bit words into the target
8771 memory at address 0x20000000:
8774 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
8778 @deffn {Command} {read_memory} address width count ['phys']
8779 This function provides an efficient way to read the target memory from a Tcl
8781 A Tcl list containing the requested memory elements is returned by this function.
8784 @item @var{address} ... target memory address
8785 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
8786 @item @var{count} ... number of elements to read
8787 @item ['phys'] ... treat the memory address as physical instead of virtual address
8790 For example, the following command reads two 32 bit words from the target
8791 memory at address 0x20000000:
8794 read_memory 0x20000000 32 2
8798 @deffn {Command} {halt} [ms]
8799 @deffnx {Command} {wait_halt} [ms]
8800 The @command{halt} command first sends a halt request to the target,
8801 which @command{wait_halt} doesn't.
8802 Otherwise these behave the same: wait up to @var{ms} milliseconds,
8803 or 5 seconds if there is no parameter, for the target to halt
8804 (and enter debug mode).
8805 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
8808 On ARM cores, software using the @emph{wait for interrupt} operation
8809 often blocks the JTAG access needed by a @command{halt} command.
8810 This is because that operation also puts the core into a low
8811 power mode by gating the core clock;
8812 but the core clock is needed to detect JTAG clock transitions.
8814 One partial workaround uses adaptive clocking: when the core is
8815 interrupted the operation completes, then JTAG clocks are accepted
8816 at least until the interrupt handler completes.
8817 However, this workaround is often unusable since the processor, board,
8818 and JTAG adapter must all support adaptive JTAG clocking.
8819 Also, it can't work until an interrupt is issued.
8821 A more complete workaround is to not use that operation while you
8822 work with a JTAG debugger.
8823 Tasking environments generally have idle loops where the body is the
8824 @emph{wait for interrupt} operation.
8825 (On older cores, it is a coprocessor action;
8826 newer cores have a @option{wfi} instruction.)
8827 Such loops can just remove that operation, at the cost of higher
8828 power consumption (because the CPU is needlessly clocked).
8833 @deffn {Command} {resume} [address]
8834 Resume the target at its current code position,
8835 or the optional @var{address} if it is provided.
8836 OpenOCD will wait 5 seconds for the target to resume.
8839 @deffn {Command} {step} [address]
8840 Single-step the target at its current code position,
8841 or the optional @var{address} if it is provided.
8844 @anchor{resetcommand}
8845 @deffn {Command} {reset}
8846 @deffnx {Command} {reset run}
8847 @deffnx {Command} {reset halt}
8848 @deffnx {Command} {reset init}
8849 Perform as hard a reset as possible, using SRST if possible.
8850 @emph{All defined targets will be reset, and target
8851 events will fire during the reset sequence.}
8853 The optional parameter specifies what should
8854 happen after the reset.
8855 If there is no parameter, a @command{reset run} is executed.
8856 The other options will not work on all systems.
8857 @xref{Reset Configuration}.
8860 @item @b{run} Let the target run
8861 @item @b{halt} Immediately halt the target
8862 @item @b{init} Immediately halt the target, and execute the reset-init script
8866 @deffn {Command} {soft_reset_halt}
8867 Requesting target halt and executing a soft reset. This is often used
8868 when a target cannot be reset and halted. The target, after reset is
8869 released begins to execute code. OpenOCD attempts to stop the CPU and
8870 then sets the program counter back to the reset vector. Unfortunately
8871 the code that was executed may have left the hardware in an unknown
8875 @deffn {Command} {adapter assert} [signal [assert|deassert signal]]
8876 @deffnx {Command} {adapter deassert} [signal [assert|deassert signal]]
8877 Set values of reset signals.
8878 Without parameters returns current status of the signals.
8879 The @var{signal} parameter values may be
8880 @option{srst}, indicating that srst signal is to be asserted or deasserted,
8881 @option{trst}, indicating that trst signal is to be asserted or deasserted.
8883 The @command{reset_config} command should already have been used
8884 to configure how the board and the adapter treat these two
8885 signals, and to say if either signal is even present.
8886 @xref{Reset Configuration}.
8887 Trying to assert a signal that is not present triggers an error.
8888 If a signal is present on the adapter and not specified in the command,
8889 the signal will not be modified.
8892 TRST is specially handled.
8893 It actually signifies JTAG's @sc{reset} state.
8894 So if the board doesn't support the optional TRST signal,
8895 or it doesn't support it along with the specified SRST value,
8896 JTAG reset is triggered with TMS and TCK signals
8897 instead of the TRST signal.
8898 And no matter how that JTAG reset is triggered, once
8899 the scan chain enters @sc{reset} with TRST inactive,
8900 TAP @code{post-reset} events are delivered to all TAPs
8901 with handlers for that event.
8905 @anchor{memoryaccess}
8906 @section Memory access commands
8907 @cindex memory access
8909 These commands allow accesses of a specific size to the memory
8910 system. Often these are used to configure the current target in some
8911 special way. For example - one may need to write certain values to the
8912 SDRAM controller to enable SDRAM.
8915 @item Use the @command{targets} (plural) command
8916 to change the current target.
8917 @item In system level scripts these commands are deprecated.
8918 Please use their TARGET object siblings to avoid making assumptions
8919 about what TAP is the current target, or about MMU configuration.
8922 @deffn {Command} {mdd} [phys] addr [count]
8923 @deffnx {Command} {mdw} [phys] addr [count]
8924 @deffnx {Command} {mdh} [phys] addr [count]
8925 @deffnx {Command} {mdb} [phys] addr [count]
8926 Display contents of address @var{addr}, as
8927 64-bit doublewords (@command{mdd}),
8928 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8929 or 8-bit bytes (@command{mdb}).
8930 When the current target has an MMU which is present and active,
8931 @var{addr} is interpreted as a virtual address.
8932 Otherwise, or if the optional @var{phys} flag is specified,
8933 @var{addr} is interpreted as a physical address.
8934 If @var{count} is specified, displays that many units.
8935 (If you want to process the data instead of displaying it,
8936 see the @code{read_memory} primitives.)
8939 @deffn {Command} {mwd} [phys] addr doubleword [count]
8940 @deffnx {Command} {mww} [phys] addr word [count]
8941 @deffnx {Command} {mwh} [phys] addr halfword [count]
8942 @deffnx {Command} {mwb} [phys] addr byte [count]
8943 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
8944 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
8945 at the specified address @var{addr}.
8946 When the current target has an MMU which is present and active,
8947 @var{addr} is interpreted as a virtual address.
8948 Otherwise, or if the optional @var{phys} flag is specified,
8949 @var{addr} is interpreted as a physical address.
8950 If @var{count} is specified, fills that many units of consecutive address.
8953 @anchor{imageaccess}
8954 @section Image loading commands
8955 @cindex image loading
8956 @cindex image dumping
8958 @deffn {Command} {dump_image} filename address size
8959 Dump @var{size} bytes of target memory starting at @var{address} to the
8960 binary file named @var{filename}.
8963 @deffn {Command} {fast_load}
8964 Loads an image stored in memory by @command{fast_load_image} to the
8965 current target. Must be preceded by fast_load_image.
8968 @deffn {Command} {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
8969 Normally you should be using @command{load_image} or GDB load. However, for
8970 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
8971 host), storing the image in memory and uploading the image to the target
8972 can be a way to upload e.g. multiple debug sessions when the binary does not change.
8973 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
8974 memory, i.e. does not affect target. This approach is also useful when profiling
8975 target programming performance as I/O and target programming can easily be profiled
8979 @deffn {Command} {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
8980 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
8981 The file format may optionally be specified
8982 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
8983 In addition the following arguments may be specified:
8984 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
8985 @var{max_length} - maximum number of bytes to load.
8987 proc load_image_bin @{fname foffset address length @} @{
8988 # Load data from fname filename at foffset offset to
8989 # target at address. Load at most length bytes.
8990 load_image $fname [expr @{$address - $foffset@}] bin \
8996 @deffn {Command} {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
8997 Displays image section sizes and addresses
8998 as if @var{filename} were loaded into target memory
8999 starting at @var{address} (defaults to zero).
9000 The file format may optionally be specified
9001 (@option{bin}, @option{ihex}, or @option{elf})
9004 @deffn {Command} {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
9005 Verify @var{filename} against target memory starting at @var{address}.
9006 The file format may optionally be specified
9007 (@option{bin}, @option{ihex}, or @option{elf})
9008 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
9011 @deffn {Command} {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
9012 Verify @var{filename} against target memory starting at @var{address}.
9013 The file format may optionally be specified
9014 (@option{bin}, @option{ihex}, or @option{elf})
9015 This perform a comparison using a CRC checksum only
9019 @section Breakpoint and Watchpoint commands
9023 CPUs often make debug modules accessible through JTAG, with
9024 hardware support for a handful of code breakpoints and data
9026 In addition, CPUs almost always support software breakpoints.
9028 @deffn {Command} {bp} [address len [@option{hw}]]
9029 With no parameters, lists all active breakpoints.
9030 Else sets a breakpoint on code execution starting
9031 at @var{address} for @var{length} bytes.
9032 This is a software breakpoint, unless @option{hw} is specified
9033 in which case it will be a hardware breakpoint.
9035 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
9036 for similar mechanisms that do not consume hardware breakpoints.)
9039 @deffn {Command} {rbp} @option{all} | address
9040 Remove the breakpoint at @var{address} or all breakpoints.
9043 @deffn {Command} {rwp} address
9044 Remove data watchpoint on @var{address}
9047 @deffn {Command} {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
9048 With no parameters, lists all active watchpoints.
9049 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
9050 The watch point is an "access" watchpoint unless
9051 the @option{r} or @option{w} parameter is provided,
9052 defining it as respectively a read or write watchpoint.
9053 If a @var{value} is provided, that value is used when determining if
9054 the watchpoint should trigger. The value may be first be masked
9055 using @var{mask} to mark ``don't care'' fields.
9059 @section Real Time Transfer (RTT)
9061 Real Time Transfer (RTT) is an interface specified by SEGGER based on basic
9062 memory reads and writes to transfer data bidirectionally between target and host.
9063 The specification is independent of the target architecture.
9064 Every target that supports so called "background memory access", which means
9065 that the target memory can be accessed by the debugger while the target is
9066 running, can be used.
9067 This interface is especially of interest for targets without
9068 Serial Wire Output (SWO), such as ARM Cortex-M0, or where semihosting is not
9069 applicable because of real-time constraints.
9072 The current implementation supports only single target devices.
9075 The data transfer between host and target device is organized through
9076 unidirectional up/down-channels for target-to-host and host-to-target
9077 communication, respectively.
9080 The current implementation does not respect channel buffer flags.
9081 They are used to determine what happens when writing to a full buffer, for
9085 Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
9086 assigned to each channel to make them accessible to an unlimited number
9087 of TCP/IP connections.
9089 @deffn {Command} {rtt setup} address size ID
9090 Configure RTT for the currently selected target.
9091 Once RTT is started, OpenOCD searches for a control block with the
9092 identifier @var{ID} starting at the memory address @var{address} within the next
9096 @deffn {Command} {rtt start}
9098 If the control block location is not known, OpenOCD starts searching for it.
9101 @deffn {Command} {rtt stop}
9105 @deffn {Command} {rtt polling_interval} [interval]
9106 Display the polling interval.
9107 If @var{interval} is provided, set the polling interval.
9108 The polling interval determines (in milliseconds) how often the up-channels are
9109 checked for new data.
9112 @deffn {Command} {rtt channels}
9113 Display a list of all channels and their properties.
9116 @deffn {Command} {rtt channellist}
9117 Return a list of all channels and their properties as Tcl list.
9118 The list can be manipulated easily from within scripts.
9121 @deffn {Command} {rtt server start} port channel
9122 Start a TCP server on @var{port} for the channel @var{channel}.
9125 @deffn {Command} {rtt server stop} port
9126 Stop the TCP sever with port @var{port}.
9129 The following example shows how to setup RTT using the SEGGER RTT implementation
9130 on the target device.
9135 rtt setup 0x20000000 2048 "SEGGER RTT"
9138 rtt server start 9090 0
9141 In this example, OpenOCD searches the control block with the ID "SEGGER RTT"
9142 starting at 0x20000000 for 2048 bytes. The RTT channel 0 is exposed through the
9146 @section Misc Commands
9149 @deffn {Command} {profile} seconds filename [start end]
9150 Profiling samples the CPU's program counter as quickly as possible,
9151 which is useful for non-intrusive stochastic profiling.
9152 Saves up to 10000 samples in @file{filename} using ``gmon.out''
9153 format. Optional @option{start} and @option{end} parameters allow to
9154 limit the address range.
9157 @deffn {Command} {version}
9158 Displays a string identifying the version of this OpenOCD server.
9161 @deffn {Command} {virt2phys} virtual_address
9162 Requests the current target to map the specified @var{virtual_address}
9163 to its corresponding physical address, and displays the result.
9166 @deffn {Command} {add_help_text} 'command_name' 'help-string'
9167 Add or replace help text on the given @var{command_name}.
9170 @deffn {Command} {add_usage_text} 'command_name' 'help-string'
9171 Add or replace usage text on the given @var{command_name}.
9174 @node Architecture and Core Commands
9175 @chapter Architecture and Core Commands
9176 @cindex Architecture Specific Commands
9177 @cindex Core Specific Commands
9179 Most CPUs have specialized JTAG operations to support debugging.
9180 OpenOCD packages most such operations in its standard command framework.
9181 Some of those operations don't fit well in that framework, so they are
9182 exposed here as architecture or implementation (core) specific commands.
9184 @anchor{armhardwaretracing}
9185 @section ARM Hardware Tracing
9190 CPUs based on ARM cores may include standard tracing interfaces,
9191 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
9192 address and data bus trace records to a ``Trace Port''.
9196 Development-oriented boards will sometimes provide a high speed
9197 trace connector for collecting that data, when the particular CPU
9198 supports such an interface.
9199 (The standard connector is a 38-pin Mictor, with both JTAG
9200 and trace port support.)
9201 Those trace connectors are supported by higher end JTAG adapters
9202 and some logic analyzer modules; frequently those modules can
9203 buffer several megabytes of trace data.
9204 Configuring an ETM coupled to such an external trace port belongs
9205 in the board-specific configuration file.
9207 If the CPU doesn't provide an external interface, it probably
9208 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
9209 dedicated SRAM. 4KBytes is one common ETB size.
9210 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
9211 (target) configuration file, since it works the same on all boards.
9214 ETM support in OpenOCD doesn't seem to be widely used yet.
9217 ETM support may be buggy, and at least some @command{etm config}
9218 parameters should be detected by asking the ETM for them.
9220 ETM trigger events could also implement a kind of complex
9221 hardware breakpoint, much more powerful than the simple
9222 watchpoint hardware exported by EmbeddedICE modules.
9223 @emph{Such breakpoints can be triggered even when using the
9224 dummy trace port driver}.
9226 It seems like a GDB hookup should be possible,
9227 as well as tracing only during specific states
9228 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
9230 There should be GUI tools to manipulate saved trace data and help
9231 analyse it in conjunction with the source code.
9232 It's unclear how much of a common interface is shared
9233 with the current XScale trace support, or should be
9234 shared with eventual Nexus-style trace module support.
9236 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
9237 for ETM modules is available. The code should be able to
9238 work with some newer cores; but not all of them support
9239 this original style of JTAG access.
9242 @subsection ETM Configuration
9243 ETM setup is coupled with the trace port driver configuration.
9245 @deffn {Config Command} {etm config} target width mode clocking driver
9246 Declares the ETM associated with @var{target}, and associates it
9247 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
9249 Several of the parameters must reflect the trace port capabilities,
9250 which are a function of silicon capabilities (exposed later
9251 using @command{etm info}) and of what hardware is connected to
9252 that port (such as an external pod, or ETB).
9253 The @var{width} must be either 4, 8, or 16,
9254 except with ETMv3.0 and newer modules which may also
9255 support 1, 2, 24, 32, 48, and 64 bit widths.
9256 (With those versions, @command{etm info} also shows whether
9257 the selected port width and mode are supported.)
9259 The @var{mode} must be @option{normal}, @option{multiplexed},
9260 or @option{demultiplexed}.
9261 The @var{clocking} must be @option{half} or @option{full}.
9264 With ETMv3.0 and newer, the bits set with the @var{mode} and
9265 @var{clocking} parameters both control the mode.
9266 This modified mode does not map to the values supported by
9267 previous ETM modules, so this syntax is subject to change.
9271 You can see the ETM registers using the @command{reg} command.
9272 Not all possible registers are present in every ETM.
9273 Most of the registers are write-only, and are used to configure
9274 what CPU activities are traced.
9278 @deffn {Command} {etm info}
9279 Displays information about the current target's ETM.
9280 This includes resource counts from the @code{ETM_CONFIG} register,
9281 as well as silicon capabilities (except on rather old modules).
9282 from the @code{ETM_SYS_CONFIG} register.
9285 @deffn {Command} {etm status}
9286 Displays status of the current target's ETM and trace port driver:
9287 is the ETM idle, or is it collecting data?
9288 Did trace data overflow?
9292 @deffn {Command} {etm tracemode} [type context_id_bits cycle_accurate branch_output]
9293 Displays what data that ETM will collect.
9294 If arguments are provided, first configures that data.
9295 When the configuration changes, tracing is stopped
9296 and any buffered trace data is invalidated.
9299 @item @var{type} ... describing how data accesses are traced,
9300 when they pass any ViewData filtering that was set up.
9302 @option{none} (save nothing),
9303 @option{data} (save data),
9304 @option{address} (save addresses),
9305 @option{all} (save data and addresses)
9306 @item @var{context_id_bits} ... 0, 8, 16, or 32
9307 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
9308 cycle-accurate instruction tracing.
9309 Before ETMv3, enabling this causes much extra data to be recorded.
9310 @item @var{branch_output} ... @option{enable} or @option{disable}.
9311 Disable this unless you need to try reconstructing the instruction
9312 trace stream without an image of the code.
9316 @deffn {Command} {etm trigger_debug} (@option{enable}|@option{disable})
9317 Displays whether ETM triggering debug entry (like a breakpoint) is
9318 enabled or disabled, after optionally modifying that configuration.
9319 The default behaviour is @option{disable}.
9320 Any change takes effect after the next @command{etm start}.
9322 By using script commands to configure ETM registers, you can make the
9323 processor enter debug state automatically when certain conditions,
9324 more complex than supported by the breakpoint hardware, happen.
9327 @subsection ETM Trace Operation
9329 After setting up the ETM, you can use it to collect data.
9330 That data can be exported to files for later analysis.
9331 It can also be parsed with OpenOCD, for basic sanity checking.
9333 To configure what is being traced, you will need to write
9334 various trace registers using @command{reg ETM_*} commands.
9335 For the definitions of these registers, read ARM publication
9336 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
9337 Be aware that most of the relevant registers are write-only,
9338 and that ETM resources are limited. There are only a handful
9339 of address comparators, data comparators, counters, and so on.
9341 Examples of scenarios you might arrange to trace include:
9344 @item Code flow within a function, @emph{excluding} subroutines
9345 it calls. Use address range comparators to enable tracing
9346 for instruction access within that function's body.
9347 @item Code flow within a function, @emph{including} subroutines
9348 it calls. Use the sequencer and address comparators to activate
9349 tracing on an ``entered function'' state, then deactivate it by
9350 exiting that state when the function's exit code is invoked.
9351 @item Code flow starting at the fifth invocation of a function,
9352 combining one of the above models with a counter.
9353 @item CPU data accesses to the registers for a particular device,
9354 using address range comparators and the ViewData logic.
9355 @item Such data accesses only during IRQ handling, combining the above
9356 model with sequencer triggers which on entry and exit to the IRQ handler.
9357 @item @emph{... more}
9360 At this writing, September 2009, there are no Tcl utility
9361 procedures to help set up any common tracing scenarios.
9363 @deffn {Command} {etm analyze}
9364 Reads trace data into memory, if it wasn't already present.
9365 Decodes and prints the data that was collected.
9368 @deffn {Command} {etm dump} filename
9369 Stores the captured trace data in @file{filename}.
9372 @deffn {Command} {etm image} filename [base_address] [type]
9373 Opens an image file.
9376 @deffn {Command} {etm load} filename
9377 Loads captured trace data from @file{filename}.
9380 @deffn {Command} {etm start}
9381 Starts trace data collection.
9384 @deffn {Command} {etm stop}
9385 Stops trace data collection.
9388 @anchor{traceportdrivers}
9389 @subsection Trace Port Drivers
9391 To use an ETM trace port it must be associated with a driver.
9393 @deffn {Trace Port Driver} {dummy}
9394 Use the @option{dummy} driver if you are configuring an ETM that's
9395 not connected to anything (on-chip ETB or off-chip trace connector).
9396 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
9397 any trace data collection.}
9398 @deffn {Config Command} {etm_dummy config} target
9399 Associates the ETM for @var{target} with a dummy driver.
9403 @deffn {Trace Port Driver} {etb}
9404 Use the @option{etb} driver if you are configuring an ETM
9405 to use on-chip ETB memory.
9406 @deffn {Config Command} {etb config} target etb_tap
9407 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
9408 You can see the ETB registers using the @command{reg} command.
9410 @deffn {Command} {etb trigger_percent} [percent]
9411 This displays, or optionally changes, ETB behavior after the
9412 ETM's configured @emph{trigger} event fires.
9413 It controls how much more trace data is saved after the (single)
9414 trace trigger becomes active.
9417 @item The default corresponds to @emph{trace around} usage,
9418 recording 50 percent data before the event and the rest
9420 @item The minimum value of @var{percent} is 2 percent,
9421 recording almost exclusively data before the trigger.
9422 Such extreme @emph{trace before} usage can help figure out
9423 what caused that event to happen.
9424 @item The maximum value of @var{percent} is 100 percent,
9425 recording data almost exclusively after the event.
9426 This extreme @emph{trace after} usage might help sort out
9427 how the event caused trouble.
9429 @c REVISIT allow "break" too -- enter debug mode.
9434 @anchor{armcrosstrigger}
9435 @section ARM Cross-Trigger Interface
9438 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
9439 that connects event sources like tracing components or CPU cores with each
9440 other through a common trigger matrix (CTM). For ARMv8 architecture, a
9441 CTI is mandatory for core run control and each core has an individual
9442 CTI instance attached to it. OpenOCD has limited support for CTI using
9443 the @emph{cti} group of commands.
9445 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
9446 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
9448 On ADIv5 DAP @var{apn} is the numeric index of the DAP AP the CTI is connected to.
9449 On ADIv6 DAP @var{apn} is the base address of the DAP AP the CTI is connected to.
9450 The @var{base_address} must match the base address of the CTI
9451 on the respective MEM-AP. All arguments are mandatory. This creates a
9452 new command @command{$cti_name} which is used for various purposes
9453 including additional configuration.
9456 @deffn {Command} {$cti_name enable} @option{on|off}
9457 Enable (@option{on}) or disable (@option{off}) the CTI.
9460 @deffn {Command} {$cti_name dump}
9461 Displays a register dump of the CTI.
9464 @deffn {Command} {$cti_name write} @var{reg_name} @var{value}
9465 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
9468 @deffn {Command} {$cti_name read} @var{reg_name}
9469 Print the value read from the CTI register with the symbolic name @var{reg_name}.
9472 @deffn {Command} {$cti_name ack} @var{event}
9473 Acknowledge a CTI @var{event}.
9476 @deffn {Command} {$cti_name channel} @var{channel_number} @var{operation}
9477 Perform a specific channel operation, the possible operations are:
9478 gate, ungate, set, clear and pulse
9481 @deffn {Command} {$cti_name testmode} @option{on|off}
9482 Enable (@option{on}) or disable (@option{off}) the integration test mode
9486 @deffn {Command} {cti names}
9487 Prints a list of names of all CTI objects created. This command is mainly
9488 useful in TCL scripting.
9491 @section Generic ARM
9494 These commands should be available on all ARM processors.
9495 They are available in addition to other core-specific
9496 commands that may be available.
9498 @deffn {Command} {arm core_state} [@option{arm}|@option{thumb}]
9499 Displays the core_state, optionally changing it to process
9500 either @option{arm} or @option{thumb} instructions.
9501 The target may later be resumed in the currently set core_state.
9502 (Processors may also support the Jazelle state, but
9503 that is not currently supported in OpenOCD.)
9506 @deffn {Command} {arm disassemble} address [count [@option{thumb}]]
9508 Disassembles @var{count} instructions starting at @var{address}.
9509 If @var{count} is not specified, a single instruction is disassembled.
9510 If @option{thumb} is specified, or the low bit of the address is set,
9511 Thumb2 (mixed 16/32-bit) instructions are used;
9512 else ARM (32-bit) instructions are used.
9513 (Processors may also support the Jazelle state, but
9514 those instructions are not currently understood by OpenOCD.)
9516 Note that all Thumb instructions are Thumb2 instructions,
9517 so older processors (without Thumb2 support) will still
9518 see correct disassembly of Thumb code.
9519 Also, ThumbEE opcodes are the same as Thumb2,
9520 with a handful of exceptions.
9521 ThumbEE disassembly currently has no explicit support.
9524 @deffn {Command} {arm mcr} pX op1 CRn CRm op2 value
9525 Write @var{value} to a coprocessor @var{pX} register
9526 passing parameters @var{CRn},
9527 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9528 and using the MCR instruction.
9529 (Parameter sequence matches the ARM instruction, but omits
9533 @deffn {Command} {arm mrc} pX coproc op1 CRn CRm op2
9534 Read a coprocessor @var{pX} register passing parameters @var{CRn},
9535 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9536 and the MRC instruction.
9537 Returns the result so it can be manipulated by Jim scripts.
9538 (Parameter sequence matches the ARM instruction, but omits
9542 @deffn {Command} {arm reg}
9543 Display a table of all banked core registers, fetching the current value from every
9544 core mode if necessary.
9547 @deffn {Command} {arm semihosting} [@option{enable}|@option{disable}]
9548 @cindex ARM semihosting
9549 Display status of semihosting, after optionally changing that status.
9551 Semihosting allows for code executing on an ARM target to use the
9552 I/O facilities on the host computer i.e. the system where OpenOCD
9553 is running. The target application must be linked against a library
9554 implementing the ARM semihosting convention that forwards operation
9555 requests by using a special SVC instruction that is trapped at the
9556 Supervisor Call vector by OpenOCD.
9559 @deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port>
9560 [@option{debug}|@option{stdio}|@option{all})
9561 @cindex ARM semihosting
9562 Redirect semihosting messages to a specified TCP port.
9564 This command redirects debug (READC, WRITEC and WRITE0) and stdio (READ, WRITE)
9565 semihosting operations to the specified TCP port.
9566 The command allows to select which type of operations to redirect (debug, stdio, all (default)).
9567 Note: for stdio operations, only I/O from/to ':tt' file descriptors are redirected.
9570 @deffn {Command} {arm semihosting_cmdline} [@option{enable}|@option{disable}]
9571 @cindex ARM semihosting
9572 Set the command line to be passed to the debugger.
9575 arm semihosting_cmdline argv0 argv1 argv2 ...
9578 This option lets one set the command line arguments to be passed to
9579 the program. The first argument (argv0) is the program name in a
9580 standard C environment (argv[0]). Depending on the program (not much
9581 programs look at argv[0]), argv0 is ignored and can be any string.
9584 @deffn {Command} {arm semihosting_fileio} [@option{enable}|@option{disable}]
9585 @cindex ARM semihosting
9586 Display status of semihosting fileio, after optionally changing that
9589 Enabling this option forwards semihosting I/O to GDB process using the
9590 File-I/O remote protocol extension. This is especially useful for
9591 interacting with remote files or displaying console messages in the
9595 @deffn {Command} {arm semihosting_resexit} [@option{enable}|@option{disable}]
9596 @cindex ARM semihosting
9597 Enable resumable SEMIHOSTING_SYS_EXIT.
9599 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
9600 things are simple, the openocd process calls exit() and passes
9601 the value returned by the target.
9603 When SEMIHOSTING_SYS_EXIT is called during a debug session,
9604 by default execution returns to the debugger, leaving the
9605 debugger in a HALT state, similar to the state entered when
9606 encountering a break.
9608 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
9609 return normally, as any semihosting call, and do not break
9611 The standard allows this to happen, but the condition
9612 to trigger it is a bit obscure ("by performing an RDI_Execute
9613 request or equivalent").
9615 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
9616 this option (default: disabled).
9619 @deffn {Command} {arm semihosting_read_user_param}
9620 @cindex ARM semihosting
9621 Read parameter of the semihosting call from the target. Usable in
9622 semihosting-user-cmd-0x10* event handlers, returning a string.
9624 When the target makes semihosting call with operation number from range 0x100-
9625 0x107, an optional string parameter can be passed to the server. This parameter
9626 is valid during the run of the event handlers and is accessible with this
9630 @deffn {Command} {arm semihosting_basedir} [dir]
9631 @cindex ARM semihosting
9632 Set the base directory for semihosting I/O, either an absolute path or a path relative to OpenOCD working directory.
9633 Use "." for the current directory.
9636 @section ARMv4 and ARMv5 Architecture
9640 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
9641 and introduced core parts of the instruction set in use today.
9642 That includes the Thumb instruction set, introduced in the ARMv4T
9645 @subsection ARM7 and ARM9 specific commands
9649 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
9650 ARM9TDMI, ARM920T or ARM926EJ-S.
9651 They are available in addition to the ARM commands,
9652 and any other core-specific commands that may be available.
9654 @deffn {Command} {arm7_9 dbgrq} [@option{enable}|@option{disable}]
9655 Displays the value of the flag controlling use of the
9656 EmbeddedIce DBGRQ signal to force entry into debug mode,
9657 instead of breakpoints.
9658 If a boolean parameter is provided, first assigns that flag.
9661 safe for all but ARM7TDMI-S cores (like NXP LPC).
9662 This feature is enabled by default on most ARM9 cores,
9663 including ARM9TDMI, ARM920T, and ARM926EJ-S.
9666 @deffn {Command} {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
9668 Displays the value of the flag controlling use of the debug communications
9669 channel (DCC) to write larger (>128 byte) amounts of memory.
9670 If a boolean parameter is provided, first assigns that flag.
9672 DCC downloads offer a huge speed increase, but might be
9673 unsafe, especially with targets running at very low speeds. This command was introduced
9674 with OpenOCD rev. 60, and requires a few bytes of working area.
9677 @deffn {Command} {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
9678 Displays the value of the flag controlling use of memory writes and reads
9679 that don't check completion of the operation.
9680 If a boolean parameter is provided, first assigns that flag.
9682 This provides a huge speed increase, especially with USB JTAG
9683 cables (FT2232), but might be unsafe if used with targets running at very low
9684 speeds, like the 32kHz startup clock of an AT91RM9200.
9687 @subsection ARM9 specific commands
9690 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
9692 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
9694 @c 9-june-2009: tried this on arm920t, it didn't work.
9695 @c no-params always lists nothing caught, and that's how it acts.
9696 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
9697 @c versions have different rules about when they commit writes.
9699 @anchor{arm9vectorcatch}
9700 @deffn {Command} {arm9 vector_catch} [@option{all}|@option{none}|list]
9701 @cindex vector_catch
9702 Vector Catch hardware provides a sort of dedicated breakpoint
9703 for hardware events such as reset, interrupt, and abort.
9704 You can use this to conserve normal breakpoint resources,
9705 so long as you're not concerned with code that branches directly
9706 to those hardware vectors.
9708 This always finishes by listing the current configuration.
9709 If parameters are provided, it first reconfigures the
9710 vector catch hardware to intercept
9711 @option{all} of the hardware vectors,
9712 @option{none} of them,
9713 or a list with one or more of the following:
9714 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
9715 @option{irq} @option{fiq}.
9718 @subsection ARM920T specific commands
9721 These commands are available to ARM920T based CPUs,
9722 which are implementations of the ARMv4T architecture
9723 built using the ARM9TDMI integer core.
9724 They are available in addition to the ARM, ARM7/ARM9,
9727 @deffn {Command} {arm920t cache_info}
9728 Print information about the caches found. This allows to see whether your target
9729 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
9732 @deffn {Command} {arm920t cp15} regnum [value]
9733 Display cp15 register @var{regnum};
9734 else if a @var{value} is provided, that value is written to that register.
9735 This uses "physical access" and the register number is as
9736 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
9737 (Not all registers can be written.)
9740 @deffn {Command} {arm920t read_cache} filename
9741 Dump the content of ICache and DCache to a file named @file{filename}.
9744 @deffn {Command} {arm920t read_mmu} filename
9745 Dump the content of the ITLB and DTLB to a file named @file{filename}.
9748 @subsection ARM926ej-s specific commands
9751 These commands are available to ARM926ej-s based CPUs,
9752 which are implementations of the ARMv5TEJ architecture
9753 based on the ARM9EJ-S integer core.
9754 They are available in addition to the ARM, ARM7/ARM9,
9757 The Feroceon cores also support these commands, although
9758 they are not built from ARM926ej-s designs.
9760 @deffn {Command} {arm926ejs cache_info}
9761 Print information about the caches found.
9764 @subsection ARM966E specific commands
9767 These commands are available to ARM966 based CPUs,
9768 which are implementations of the ARMv5TE architecture.
9769 They are available in addition to the ARM, ARM7/ARM9,
9772 @deffn {Command} {arm966e cp15} regnum [value]
9773 Display cp15 register @var{regnum};
9774 else if a @var{value} is provided, that value is written to that register.
9775 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
9777 There is no current control over bits 31..30 from that table,
9778 as required for BIST support.
9781 @subsection XScale specific commands
9784 Some notes about the debug implementation on the XScale CPUs:
9786 The XScale CPU provides a special debug-only mini-instruction cache
9787 (mini-IC) in which exception vectors and target-resident debug handler
9788 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
9789 must point vector 0 (the reset vector) to the entry of the debug
9790 handler. However, this means that the complete first cacheline in the
9791 mini-IC is marked valid, which makes the CPU fetch all exception
9792 handlers from the mini-IC, ignoring the code in RAM.
9794 To address this situation, OpenOCD provides the @code{xscale
9795 vector_table} command, which allows the user to explicitly write
9796 individual entries to either the high or low vector table stored in
9799 It is recommended to place a pc-relative indirect branch in the vector
9800 table, and put the branch destination somewhere in memory. Doing so
9801 makes sure the code in the vector table stays constant regardless of
9802 code layout in memory:
9805 ldr pc,[pc,#0x100-8]
9806 ldr pc,[pc,#0x100-8]
9807 ldr pc,[pc,#0x100-8]
9808 ldr pc,[pc,#0x100-8]
9809 ldr pc,[pc,#0x100-8]
9810 ldr pc,[pc,#0x100-8]
9811 ldr pc,[pc,#0x100-8]
9812 ldr pc,[pc,#0x100-8]
9814 .long real_reset_vector
9815 .long real_ui_handler
9816 .long real_swi_handler
9818 .long real_data_abort
9819 .long 0 /* unused */
9820 .long real_irq_handler
9821 .long real_fiq_handler
9824 Alternatively, you may choose to keep some or all of the mini-IC
9825 vector table entries synced with those written to memory by your
9826 system software. The mini-IC can not be modified while the processor
9827 is executing, but for each vector table entry not previously defined
9828 using the @code{xscale vector_table} command, OpenOCD will copy the
9829 value from memory to the mini-IC every time execution resumes from a
9830 halt. This is done for both high and low vector tables (although the
9831 table not in use may not be mapped to valid memory, and in this case
9832 that copy operation will silently fail). This means that you will
9833 need to briefly halt execution at some strategic point during system
9834 start-up; e.g., after the software has initialized the vector table,
9835 but before exceptions are enabled. A breakpoint can be used to
9836 accomplish this once the appropriate location in the start-up code has
9837 been identified. A watchpoint over the vector table region is helpful
9838 in finding the location if you're not sure. Note that the same
9839 situation exists any time the vector table is modified by the system
9842 The debug handler must be placed somewhere in the address space using
9843 the @code{xscale debug_handler} command. The allowed locations for the
9844 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
9845 0xfffff800). The default value is 0xfe000800.
9847 XScale has resources to support two hardware breakpoints and two
9848 watchpoints. However, the following restrictions on watchpoint
9849 functionality apply: (1) the value and mask arguments to the @code{wp}
9850 command are not supported, (2) the watchpoint length must be a
9851 power of two and not less than four, and can not be greater than the
9852 watchpoint address, and (3) a watchpoint with a length greater than
9853 four consumes all the watchpoint hardware resources. This means that
9854 at any one time, you can have enabled either two watchpoints with a
9855 length of four, or one watchpoint with a length greater than four.
9857 These commands are available to XScale based CPUs,
9858 which are implementations of the ARMv5TE architecture.
9860 @deffn {Command} {xscale analyze_trace}
9861 Displays the contents of the trace buffer.
9864 @deffn {Command} {xscale cache_clean_address} address
9865 Changes the address used when cleaning the data cache.
9868 @deffn {Command} {xscale cache_info}
9869 Displays information about the CPU caches.
9872 @deffn {Command} {xscale cp15} regnum [value]
9873 Display cp15 register @var{regnum};
9874 else if a @var{value} is provided, that value is written to that register.
9877 @deffn {Command} {xscale debug_handler} target address
9878 Changes the address used for the specified target's debug handler.
9881 @deffn {Command} {xscale dcache} [@option{enable}|@option{disable}]
9882 Enables or disable the CPU's data cache.
9885 @deffn {Command} {xscale dump_trace} filename
9886 Dumps the raw contents of the trace buffer to @file{filename}.
9889 @deffn {Command} {xscale icache} [@option{enable}|@option{disable}]
9890 Enables or disable the CPU's instruction cache.
9893 @deffn {Command} {xscale mmu} [@option{enable}|@option{disable}]
9894 Enables or disable the CPU's memory management unit.
9897 @deffn {Command} {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
9898 Displays the trace buffer status, after optionally
9899 enabling or disabling the trace buffer
9900 and modifying how it is emptied.
9903 @deffn {Command} {xscale trace_image} filename [offset [type]]
9904 Opens a trace image from @file{filename}, optionally rebasing
9905 its segment addresses by @var{offset}.
9906 The image @var{type} may be one of
9907 @option{bin} (binary), @option{ihex} (Intel hex),
9908 @option{elf} (ELF file), @option{s19} (Motorola s19),
9909 @option{mem}, or @option{builder}.
9912 @anchor{xscalevectorcatch}
9913 @deffn {Command} {xscale vector_catch} [mask]
9914 @cindex vector_catch
9915 Display a bitmask showing the hardware vectors to catch.
9916 If the optional parameter is provided, first set the bitmask to that value.
9918 The mask bits correspond with bit 16..23 in the DCSR:
9921 0x02 Trap Undefined Instructions
9922 0x04 Trap Software Interrupt
9923 0x08 Trap Prefetch Abort
9924 0x10 Trap Data Abort
9931 @deffn {Command} {xscale vector_table} [(@option{low}|@option{high}) index value]
9932 @cindex vector_table
9934 Set an entry in the mini-IC vector table. There are two tables: one for
9935 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
9936 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
9937 points to the debug handler entry and can not be overwritten.
9938 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
9940 Without arguments, the current settings are displayed.
9944 @section ARMv6 Architecture
9947 @subsection ARM11 specific commands
9950 @deffn {Command} {arm11 memwrite burst} [@option{enable}|@option{disable}]
9951 Displays the value of the memwrite burst-enable flag,
9952 which is enabled by default.
9953 If a boolean parameter is provided, first assigns that flag.
9954 Burst writes are only used for memory writes larger than 1 word.
9955 They improve performance by assuming that the CPU has read each data
9956 word over JTAG and completed its write before the next word arrives,
9957 instead of polling for a status flag to verify that completion.
9958 This is usually safe, because JTAG runs much slower than the CPU.
9961 @deffn {Command} {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
9962 Displays the value of the memwrite error_fatal flag,
9963 which is enabled by default.
9964 If a boolean parameter is provided, first assigns that flag.
9965 When set, certain memory write errors cause earlier transfer termination.
9968 @deffn {Command} {arm11 step_irq_enable} [@option{enable}|@option{disable}]
9969 Displays the value of the flag controlling whether
9970 IRQs are enabled during single stepping;
9971 they are disabled by default.
9972 If a boolean parameter is provided, first assigns that.
9975 @deffn {Command} {arm11 vcr} [value]
9976 @cindex vector_catch
9977 Displays the value of the @emph{Vector Catch Register (VCR)},
9978 coprocessor 14 register 7.
9979 If @var{value} is defined, first assigns that.
9981 Vector Catch hardware provides dedicated breakpoints
9982 for certain hardware events.
9983 The specific bit values are core-specific (as in fact is using
9984 coprocessor 14 register 7 itself) but all current ARM11
9985 cores @emph{except the ARM1176} use the same six bits.
9988 @section ARMv7 and ARMv8 Architecture
9992 @subsection ARMv7-A specific commands
9995 @deffn {Command} {cortex_a cache_info}
9996 display information about target caches
9999 @deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
10000 Work around issues with software breakpoints when the program text is
10001 mapped read-only by the operating system. This option sets the CP15 DACR
10002 to "all-manager" to bypass MMU permission checks on memory access.
10006 @deffn {Command} {cortex_a dbginit}
10007 Initialize core debug
10008 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
10011 @deffn {Command} {cortex_a smp} [on|off]
10012 Display/set the current SMP mode
10015 @deffn {Command} {cortex_a smp_gdb} [core_id]
10016 Display/set the current core displayed in GDB
10019 @deffn {Command} {cortex_a maskisr} [@option{on}|@option{off}]
10020 Selects whether interrupts will be processed when single stepping
10023 @deffn {Command} {cache_config l2x} [base way]
10024 configure l2x cache
10027 @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
10028 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
10029 memory location @var{address}. When dumping the table from @var{address}, print at most
10030 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
10031 possible (4096) entries are printed.
10034 @subsection ARMv7-R specific commands
10037 @deffn {Command} {cortex_r4 dbginit}
10038 Initialize core debug
10039 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
10042 @deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
10043 Selects whether interrupts will be processed when single stepping
10047 @subsection ARM CoreSight TPIU and SWO specific commands
10053 ARM CoreSight provides several modules to generate debugging
10054 information internally (ITM, DWT and ETM). Their output is directed
10055 through TPIU or SWO modules to be captured externally either on an SWO pin (this
10056 configuration is called SWV) or on a synchronous parallel trace port.
10058 ARM CoreSight provides independent HW blocks named TPIU and SWO each with its
10059 own functionality. Embedded in Cortex-M3 and M4, ARM provides an optional HW
10060 block that includes both TPIU and SWO functionalities and is again named TPIU,
10061 which causes quite some confusion.
10062 The registers map of all the TPIU and SWO implementations allows using a single
10063 driver that detects at runtime the features available.
10065 The @command{tpiu} is used for either TPIU or SWO.
10066 A convenient alias @command{swo} is available to help distinguish, in scripts,
10067 the commands for SWO from the commands for TPIU.
10069 @deffn {Command} {swo} ...
10070 Alias of @command{tpiu ...}. Can be used in scripts to distinguish the commands
10071 for SWO from the commands for TPIU.
10074 @deffn {Command} {tpiu create} tpiu_name configparams...
10075 Creates a TPIU or a SWO object. The two commands are equivalent.
10076 Add the object in a list and add new commands (@command{@var{tpiu_name}})
10077 which are used for various purposes including additional configuration.
10080 @item @var{tpiu_name} -- the name of the TPIU or SWO object.
10081 This name is also used to create the object's command, referred to here
10082 as @command{$tpiu_name}, and in other places where the TPIU or SWO needs to be identified.
10083 @item @var{configparams} -- all parameters accepted by @command{$tpiu_name configure} are permitted.
10085 You @emph{must} set here the AP and MEM_AP base_address through @code{-dap @var{dap_name}},
10086 @code{-ap-num @var{ap_number}} and @code{-baseaddr @var{base_address}}.
10090 @deffn {Command} {tpiu names}
10091 Lists all the TPIU or SWO objects created so far. The two commands are equivalent.
10094 @deffn {Command} {tpiu init}
10095 Initialize all registered TPIU and SWO. The two commands are equivalent.
10096 These commands are used internally during initialization. They can be issued
10097 at any time after the initialization, too.
10100 @deffn {Command} {$tpiu_name cget} queryparm
10101 Each configuration parameter accepted by @command{$tpiu_name configure} can be
10102 individually queried, to return its current value.
10103 The @var{queryparm} is a parameter name accepted by that command, such as @code{-dap}.
10106 @deffn {Command} {$tpiu_name configure} configparams...
10107 The options accepted by this command may also be specified as parameters
10108 to @command{tpiu create}. Their values can later be queried one at a time by
10109 using the @command{$tpiu_name cget} command.
10112 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
10113 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
10115 @item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU.
10116 On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
10117 On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the TPIU is connected to.
10119 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
10120 to access the TPIU in the DAP AP memory space.
10122 @item @code{-protocol} (@option{sync}|@option{uart}|@option{manchester}) -- sets the
10123 protocol used for trace data:
10125 @item @option{sync} -- synchronous parallel trace output mode, using @var{port_width}
10126 data bits (default);
10127 @item @option{uart} -- use asynchronous SWO mode with NRZ (same as regular UART 8N1) coding;
10128 @item @option{manchester} -- use asynchronous SWO mode with Manchester coding.
10131 @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler,
10132 a TCL string which is evaluated when the event is triggered. The events
10133 @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable}
10134 are defined for TPIU/SWO.
10135 A typical use case for the event @code{pre-enable} is to enable the trace clock
10138 @item @code{-output} (@option{external}|@option{:}@var{port}|@var{filename}|@option{-}) -- specifies
10139 the destination of the trace data:
10141 @item @option{external} -- configure TPIU/SWO to let user capture trace
10142 output externally, either with an additional UART or with a logic analyzer (default);
10143 @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data
10144 and forward it to @command{tcl_trace} command;
10145 @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather
10146 trace data, open a TCP server at port @var{port} and send the trace data to
10147 each connected client;
10148 @item @var{filename} -- configure TPIU/SWO and debug adapter to
10149 gather trace data and append it to @var{filename}, which can be
10150 either a regular file or a named pipe.
10153 @item @code{-traceclk} @var{TRACECLKIN_freq} -- mandatory parameter.
10154 Specifies the frequency in Hz of the trace clock. For the TPIU embedded in
10155 Cortex-M3 or M4, this is usually the same frequency as HCLK. For protocol
10156 @option{sync} this is twice the frequency of the pin data rate.
10158 @item @code{-pin-freq} @var{trace_freq} -- specifies the expected data rate
10159 in Hz of the SWO pin. Parameter used only on protocols @option{uart} and
10160 @option{manchester}. Can be omitted to let the adapter driver select the
10161 maximum supported rate automatically.
10163 @item @code{-port-width} @var{port_width} -- sets to @var{port_width} the width
10164 of the synchronous parallel port used for trace output. Parameter used only on
10165 protocol @option{sync}. If not specified, default value is @var{1}.
10167 @item @code{-formatter} (@option{0}|@option{1}) -- specifies if the formatter
10168 should be enabled. Parameter used only on protocol @option{sync}. If not specified,
10169 default value is @var{0}.
10173 @deffn {Command} {$tpiu_name enable}
10174 Uses the parameters specified by the previous @command{$tpiu_name configure}
10175 to configure and enable the TPIU or the SWO.
10176 If required, the adapter is also configured and enabled to receive the trace
10178 This command can be used before @command{init}, but it will take effect only
10179 after the @command{init}.
10182 @deffn {Command} {$tpiu_name disable}
10183 Disable the TPIU or the SWO, terminating the receiving of the trace data.
10190 @item STM32L152 board is programmed with an application that configures
10191 PLL to provide core clock with 24MHz frequency; to use ITM output it's
10194 #include <libopencm3/cm3/itm.h>
10199 (the most obvious way is to use the first stimulus port for printf,
10200 for that this ITM_STIM8 assignment can be used inside _write(); to make it
10201 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
10202 ITM_STIM_FIFOREADY));});
10203 @item An FT2232H UART is connected to the SWO pin of the board;
10204 @item Commands to configure UART for 12MHz baud rate:
10206 $ setserial /dev/ttyUSB1 spd_cust divisor 5
10207 $ stty -F /dev/ttyUSB1 38400
10209 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
10210 baud with our custom divisor to get 12MHz)
10211 @item @code{itmdump -f /dev/ttyUSB1 -d1}
10212 @item OpenOCD invocation line:
10214 openocd -f interface/stlink.cfg \
10215 -c "transport select hla_swd" \
10216 -f target/stm32l1.cfg \
10217 -c "stm32l1.tpiu configure -protocol uart" \
10218 -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
10219 -c "stm32l1.tpiu enable"
10223 @subsection ARMv7-M specific commands
10230 @deffn {Command} {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
10231 Enable or disable trace output for ITM stimulus @var{port} (counting
10232 from 0). Port 0 is enabled on target creation automatically.
10235 @deffn {Command} {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
10236 Enable or disable trace output for all ITM stimulus ports.
10239 @subsection Cortex-M specific commands
10242 @deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
10243 Control masking (disabling) interrupts during target step/resume.
10245 The @option{auto} option handles interrupts during stepping in a way that they
10246 get served but don't disturb the program flow. The step command first allows
10247 pending interrupt handlers to execute, then disables interrupts and steps over
10248 the next instruction where the core was halted. After the step interrupts
10249 are enabled again. If the interrupt handlers don't complete within 500ms,
10250 the step command leaves with the core running.
10252 The @option{steponly} option disables interrupts during single-stepping but
10253 enables them during normal execution. This can be used as a partial workaround
10254 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
10255 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
10257 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
10258 option. If no breakpoint is available at the time of the step, then the step
10259 is taken with interrupts enabled, i.e. the same way the @option{off} option
10262 Default is @option{auto}.
10265 @deffn {Command} {cortex_m vector_catch} [@option{all}|@option{none}|list]
10266 @cindex vector_catch
10267 Vector Catch hardware provides dedicated breakpoints
10268 for certain hardware events.
10270 Parameters request interception of
10271 @option{all} of these hardware event vectors,
10272 @option{none} of them,
10273 or one or more of the following:
10274 @option{hard_err} for a HardFault exception;
10275 @option{mm_err} for a MemManage exception;
10276 @option{bus_err} for a BusFault exception;
10278 @option{state_err},
10279 @option{chk_err}, or
10280 @option{nocp_err} for various UsageFault exceptions; or
10282 If NVIC setup code does not enable them,
10283 MemManage, BusFault, and UsageFault exceptions
10284 are mapped to HardFault.
10285 UsageFault checks for
10286 divide-by-zero and unaligned access
10287 must also be explicitly enabled.
10289 This finishes by listing the current vector catch configuration.
10292 @deffn {Command} {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
10293 Control reset handling if hardware srst is not fitted
10294 @xref{reset_config,,reset_config}.
10297 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
10298 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
10301 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
10302 This however has the disadvantage of only resetting the core, all peripherals
10303 are unaffected. A solution would be to use a @code{reset-init} event handler
10304 to manually reset the peripherals.
10305 @xref{targetevents,,Target Events}.
10307 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
10311 @subsection ARMv8-A specific commands
10315 @deffn {Command} {aarch64 cache_info}
10316 Display information about target caches
10319 @deffn {Command} {aarch64 dbginit}
10320 This command enables debugging by clearing the OS Lock and sticky power-down and reset
10321 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
10322 target code relies on. In a configuration file, the command would typically be called from a
10323 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
10324 However, normally it is not necessary to use the command at all.
10327 @deffn {Command} {aarch64 disassemble} address [count]
10328 @cindex disassemble
10329 Disassembles @var{count} instructions starting at @var{address}.
10330 If @var{count} is not specified, a single instruction is disassembled.
10333 @deffn {Command} {aarch64 smp} [on|off]
10334 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
10335 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
10336 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
10337 group. With SMP handling disabled, all targets need to be treated individually.
10340 @deffn {Command} {aarch64 maskisr} [@option{on}|@option{off}]
10341 Selects whether interrupts will be processed when single stepping. The default configuration is
10345 @deffn {Command} {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
10346 Cause @command{$target_name} to halt when an exception is taken. Any combination of
10347 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
10348 @command{$target_name} will halt before taking the exception. In order to resume
10349 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
10350 Issuing the command without options prints the current configuration.
10353 @section EnSilica eSi-RISC Architecture
10355 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
10356 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
10358 @subsection eSi-RISC Configuration
10360 @deffn {Command} {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
10361 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
10362 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
10365 @deffn {Command} {esirisc hwdc} (@option{all}|@option{none}|mask ...)
10366 Configure hardware debug control. The HWDC register controls which exceptions return
10367 control back to the debugger. Possible masks are @option{all}, @option{none},
10368 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
10369 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
10372 @subsection eSi-RISC Operation
10374 @deffn {Command} {esirisc flush_caches}
10375 Flush instruction and data caches. This command requires that the target is halted
10376 when the command is issued and configured with an instruction or data cache.
10379 @subsection eSi-Trace Configuration
10381 eSi-RISC targets may be configured with support for instruction tracing. Trace
10382 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
10383 is typically employed to move trace data off-device using a high-speed
10384 peripheral (eg. SPI). Collected trace data is encoded in one of three different
10385 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
10386 fifo} must be issued along with @command{esirisc trace format} before trace data
10389 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
10390 needed, collected trace data can be dumped to a file and processed by external
10394 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
10395 for this issue is to configure DMA to copy trace data to an in-memory buffer,
10396 which can then be passed to the @command{esirisc trace analyze} and
10397 @command{esirisc trace dump} commands.
10399 It is possible to corrupt trace data when using a FIFO if the peripheral
10400 responsible for draining data from the FIFO is not fast enough. This can be
10401 managed by enabling flow control, however this can impact timing-sensitive
10402 software operation on the CPU.
10405 @deffn {Command} {esirisc trace buffer} address size [@option{wrap}]
10406 Configure trace buffer using the provided address and size. If the @option{wrap}
10407 option is specified, trace collection will continue once the end of the buffer
10408 is reached. By default, wrap is disabled.
10411 @deffn {Command} {esirisc trace fifo} address
10412 Configure trace FIFO using the provided address.
10415 @deffn {Command} {esirisc trace flow_control} (@option{enable}|@option{disable})
10416 Enable or disable stalling the CPU to collect trace data. By default, flow
10417 control is disabled.
10420 @deffn {Command} {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
10421 Configure trace format and number of PC bits to be captured. @option{pc_bits}
10422 must be within 1 and 31 as the LSB is not collected. If external tooling is used
10423 to analyze collected trace data, these values must match.
10425 Supported trace formats:
10427 @item @option{full} capture full trace data, allowing execution history and
10428 timing to be determined.
10429 @item @option{branch} capture taken branch instructions and branch target
10431 @item @option{icache} capture instruction cache misses.
10435 @deffn {Command} {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
10436 Configure trigger start condition using the provided start data and mask. A
10437 brief description of each condition is provided below; for more detail on how
10438 these values are used, see the eSi-RISC Architecture Manual.
10440 Supported conditions:
10442 @item @option{none} manual tracing (see @command{esirisc trace start}).
10443 @item @option{pc} start tracing if the PC matches start data and mask.
10444 @item @option{load} start tracing if the effective address of a load
10445 instruction matches start data and mask.
10446 @item @option{store} start tracing if the effective address of a store
10447 instruction matches start data and mask.
10448 @item @option{exception} start tracing if the EID of an exception matches start
10450 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
10451 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
10452 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
10453 @item @option{high} start tracing when an external signal is a logical high.
10454 @item @option{low} start tracing when an external signal is a logical low.
10458 @deffn {Command} {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
10459 Configure trigger stop condition using the provided stop data and mask. A brief
10460 description of each condition is provided below; for more detail on how these
10461 values are used, see the eSi-RISC Architecture Manual.
10463 Supported conditions:
10465 @item @option{none} manual tracing (see @command{esirisc trace stop}).
10466 @item @option{pc} stop tracing if the PC matches stop data and mask.
10467 @item @option{load} stop tracing if the effective address of a load
10468 instruction matches stop data and mask.
10469 @item @option{store} stop tracing if the effective address of a store
10470 instruction matches stop data and mask.
10471 @item @option{exception} stop tracing if the EID of an exception matches stop
10473 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
10474 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
10475 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
10479 @deffn {Command} {esirisc trace trigger delay} (@option{trigger}) [cycles]
10480 Configure trigger start/stop delay in clock cycles.
10482 Supported triggers:
10484 @item @option{none} no delay to start or stop collection.
10485 @item @option{start} delay @option{cycles} after trigger to start collection.
10486 @item @option{stop} delay @option{cycles} after trigger to stop collection.
10487 @item @option{both} delay @option{cycles} after both triggers to start or stop
10492 @subsection eSi-Trace Operation
10494 @deffn {Command} {esirisc trace init}
10495 Initialize trace collection. This command must be called any time the
10496 configuration changes. If a trace buffer has been configured, the contents will
10497 be overwritten when trace collection starts.
10500 @deffn {Command} {esirisc trace info}
10501 Display trace configuration.
10504 @deffn {Command} {esirisc trace status}
10505 Display trace collection status.
10508 @deffn {Command} {esirisc trace start}
10509 Start manual trace collection.
10512 @deffn {Command} {esirisc trace stop}
10513 Stop manual trace collection.
10516 @deffn {Command} {esirisc trace analyze} [address size]
10517 Analyze collected trace data. This command may only be used if a trace buffer
10518 has been configured. If a trace FIFO has been configured, trace data must be
10519 copied to an in-memory buffer identified by the @option{address} and
10520 @option{size} options using DMA.
10523 @deffn {Command} {esirisc trace dump} [address size] @file{filename}
10524 Dump collected trace data to file. This command may only be used if a trace
10525 buffer has been configured. If a trace FIFO has been configured, trace data must
10526 be copied to an in-memory buffer identified by the @option{address} and
10527 @option{size} options using DMA.
10530 @section Intel Architecture
10532 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
10533 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
10534 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
10535 software debug and the CLTAP is used for SoC level operations.
10536 Useful docs are here: https://communities.intel.com/community/makers/documentation
10538 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
10539 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
10540 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
10543 @subsection x86 32-bit specific commands
10544 The three main address spaces for x86 are memory, I/O and configuration space.
10545 These commands allow a user to read and write to the 64Kbyte I/O address space.
10547 @deffn {Command} {x86_32 idw} address
10548 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
10551 @deffn {Command} {x86_32 idh} address
10552 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
10555 @deffn {Command} {x86_32 idb} address
10556 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
10559 @deffn {Command} {x86_32 iww} address
10560 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
10563 @deffn {Command} {x86_32 iwh} address
10564 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
10567 @deffn {Command} {x86_32 iwb} address
10568 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
10571 @section OpenRISC Architecture
10573 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
10574 configured with any of the TAP / Debug Unit available.
10576 @subsection TAP and Debug Unit selection commands
10577 @deffn {Command} {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
10578 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
10580 @deffn {Command} {du_select} (@option{adv}|@option{mohor}) [option]
10581 Select between the Advanced Debug Interface and the classic one.
10583 An option can be passed as a second argument to the debug unit.
10585 When using the Advanced Debug Interface, option = 1 means the RTL core is
10586 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
10587 between bytes while doing read or write bursts.
10590 @subsection Registers commands
10591 @deffn {Command} {addreg} [name] [address] [feature] [reg_group]
10592 Add a new register in the cpu register list. This register will be
10593 included in the generated target descriptor file.
10595 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
10597 @strong{[reg_group]} can be anything. The default register list defines "system",
10598 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
10599 and "timer" groups.
10603 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
10608 @section RISC-V Architecture
10610 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
10611 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
10612 harts. (It's possible to increase this limit to 1024 by changing
10613 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
10614 Debug Specification, but there is also support for legacy targets that
10615 implement version 0.11.
10617 @subsection RISC-V Terminology
10619 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
10620 another hart, or may be a separate core. RISC-V treats those the same, and
10621 OpenOCD exposes each hart as a separate core.
10623 @subsection Vector Registers
10625 For harts that implement the vector extension, OpenOCD provides access to the
10626 relevant CSRs, as well as the vector registers (v0-v31). The size of each
10627 vector register is dependent on the value of vlenb. RISC-V allows each vector
10628 register to be divided into selected-width elements, and this division can be
10629 changed at run-time. Because OpenOCD cannot update register definitions at
10630 run-time, it exposes each vector register to gdb as a union of fields of
10631 vectors so that users can easily access individual bytes, shorts, words,
10632 longs, and quads inside each vector register. It is left to gdb or
10633 higher-level debuggers to present this data in a more intuitive format.
10635 In the XML register description, the vector registers (when vlenb=16) look as
10639 <feature name="org.gnu.gdb.riscv.vector">
10640 <vector id="bytes" type="uint8" count="16"/>
10641 <vector id="shorts" type="uint16" count="8"/>
10642 <vector id="words" type="uint32" count="4"/>
10643 <vector id="longs" type="uint64" count="2"/>
10644 <vector id="quads" type="uint128" count="1"/>
10645 <union id="riscv_vector">
10646 <field name="b" type="bytes"/>
10647 <field name="s" type="shorts"/>
10648 <field name="w" type="words"/>
10649 <field name="l" type="longs"/>
10650 <field name="q" type="quads"/>
10652 <reg name="v0" bitsize="128" regnum="4162" save-restore="no"
10653 type="riscv_vector" group="vector"/>
10655 <reg name="v31" bitsize="128" regnum="4193" save-restore="no"
10656 type="riscv_vector" group="vector"/>
10660 @subsection RISC-V Debug Configuration Commands
10662 @deffn {Config Command} {riscv expose_csrs} n[-m|=name] [...]
10663 Configure which CSRs to expose in addition to the standard ones. The CSRs to expose
10664 can be specified as individual register numbers or register ranges (inclusive). For the
10665 individually listed CSRs, a human-readable name can optionally be set using the @code{n=name}
10666 syntax, which will get @code{csr_} prepended to it. If no name is provided, the register will be
10667 named @code{csr<n>}.
10669 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
10670 and then only if the corresponding extension appears to be implemented. This
10671 command can be used if OpenOCD gets this wrong, or if the target implements custom
10675 # Expose a single RISC-V CSR number 128 under the name "csr128":
10676 $_TARGETNAME expose_csrs 128
10678 # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
10679 $_TARGETNAME expose_csrs 128-132
10681 # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
10682 $_TARGETNAME expose_csrs 1996=myregister
10686 @deffn {Config Command} {riscv expose_custom} n[-m|=name] [...]
10687 The RISC-V Debug Specification allows targets to expose custom registers
10688 through abstract commands. (See Section 3.5.1.1 in that document.) This command
10689 configures individual registers or register ranges (inclusive) that shall be exposed.
10690 Number 0 indicates the first custom register, whose abstract command number is 0xc000.
10691 For individually listed registers, a human-readable name can be optionally provided
10692 using the @code{n=name} syntax, which will get @code{custom_} prepended to it. If no
10693 name is provided, the register will be named @code{custom<n>}.
10696 # Expose one RISC-V custom register with number 0xc010 (0xc000 + 16)
10697 # under the name "custom16":
10698 $_TARGETNAME expose_custom 16
10700 # Expose a range of RISC-V custom registers with numbers 0xc010 .. 0xc018
10701 # (0xc000+16 .. 0xc000+24) under the names "custom16" through "custom24":
10702 $_TARGETNAME expose_custom 16-24
10704 # Expose one RISC-V custom register with number 0xc020 (0xc000 + 32) under
10705 # user-defined name "custom_myregister":
10706 $_TARGETNAME expose_custom 32=myregister
10710 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
10711 Set the wall-clock timeout (in seconds) for individual commands. The default
10712 should work fine for all but the slowest targets (eg. simulators).
10715 @deffn {Command} {riscv set_reset_timeout_sec} [seconds]
10716 Set the maximum time to wait for a hart to come out of reset after reset is
10720 @deffn {Command} {riscv set_scratch_ram} none|[address]
10721 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
10722 This is used to access 64-bit floating point registers on 32-bit targets.
10725 @deffn Command {riscv set_mem_access} method1 [method2] [method3]
10726 Specify which RISC-V memory access method(s) shall be used, and in which order
10727 of priority. At least one method must be specified.
10729 Available methods are:
10731 @item @code{progbuf} - Use RISC-V Debug Program Buffer to access memory.
10732 @item @code{sysbus} - Access memory via RISC-V Debug System Bus interface.
10733 @item @code{abstract} - Access memory via RISC-V Debug abstract commands.
10736 By default, all memory access methods are enabled in the following order:
10737 @code{progbuf sysbus abstract}.
10739 This command can be used to change the memory access methods if the default
10740 behavior is not suitable for a particular target.
10743 @deffn {Command} {riscv set_enable_virtual} on|off
10744 When on, memory accesses are performed on physical or virtual memory depending
10745 on the current system configuration. When off (default), all memory accessses are performed
10746 on physical memory.
10749 @deffn {Command} {riscv set_enable_virt2phys} on|off
10750 When on (default), memory accesses are performed on physical or virtual memory
10751 depending on the current satp configuration. When off, all memory accessses are
10752 performed on physical memory.
10755 @deffn {Command} {riscv resume_order} normal|reversed
10756 Some software assumes all harts are executing nearly continuously. Such
10757 software may be sensitive to the order that harts are resumed in. On harts
10758 that don't support hasel, this option allows the user to choose the order the
10759 harts are resumed in. If you are using this option, it's probably masking a
10760 race condition problem in your code.
10762 Normal order is from lowest hart index to highest. This is the default
10763 behavior. Reversed order is from highest hart index to lowest.
10766 @deffn {Command} {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
10767 Set the IR value for the specified JTAG register. This is useful, for
10768 example, when using the existing JTAG interface on a Xilinx FPGA by
10769 way of BSCANE2 primitives that only permit a limited selection of IR
10772 When utilizing version 0.11 of the RISC-V Debug Specification,
10773 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
10774 and DBUS registers, respectively.
10777 @deffn {Command} {riscv use_bscan_tunnel} value
10778 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
10779 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
10782 @deffn {Command} {riscv set_ebreakm} on|off
10783 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
10784 OpenOCD. When off, they generate a breakpoint exception handled internally.
10787 @deffn {Command} {riscv set_ebreaks} on|off
10788 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
10789 OpenOCD. When off, they generate a breakpoint exception handled internally.
10792 @deffn {Command} {riscv set_ebreaku} on|off
10793 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
10794 OpenOCD. When off, they generate a breakpoint exception handled internally.
10797 @subsection RISC-V Authentication Commands
10799 The following commands can be used to authenticate to a RISC-V system. Eg. a
10800 trivial challenge-response protocol could be implemented as follows in a
10801 configuration file, immediately following @command{init}:
10803 set challenge [riscv authdata_read]
10804 riscv authdata_write [expr @{$challenge + 1@}]
10807 @deffn {Command} {riscv authdata_read}
10808 Return the 32-bit value read from authdata.
10811 @deffn {Command} {riscv authdata_write} value
10812 Write the 32-bit value to authdata.
10815 @subsection RISC-V DMI Commands
10817 The following commands allow direct access to the Debug Module Interface, which
10818 can be used to interact with custom debug features.
10820 @deffn {Command} {riscv dmi_read} address
10821 Perform a 32-bit DMI read at address, returning the value.
10824 @deffn {Command} {riscv dmi_write} address value
10825 Perform a 32-bit DMI write of value at address.
10828 @section ARC Architecture
10831 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
10832 designers can optimize for a wide range of uses, from deeply embedded to
10833 high-performance host applications in a variety of market segments. See more
10834 at: @url{http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx}.
10835 OpenOCD currently supports ARC EM processors.
10836 There is a set ARC-specific OpenOCD commands that allow low-level
10837 access to the core and provide necessary support for ARC extensibility and
10838 configurability capabilities. ARC processors has much more configuration
10839 capabilities than most of the other processors and in addition there is an
10840 extension interface that allows SoC designers to add custom registers and
10841 instructions. For the OpenOCD that mostly means that set of core and AUX
10842 registers in target will vary and is not fixed for a particular processor
10843 model. To enable extensibility several TCL commands are provided that allow to
10844 describe those optional registers in OpenOCD configuration files. Moreover
10845 those commands allow for a dynamic target features discovery.
10848 @subsection General ARC commands
10850 @deffn {Config Command} {arc add-reg} configparams
10852 Add a new register to processor target. By default newly created register is
10853 marked as not existing. @var{configparams} must have following required
10858 @item @code{-name} name
10859 @*Name of a register.
10861 @item @code{-num} number
10862 @*Architectural register number: core register number or AUX register number.
10864 @item @code{-feature} XML_feature
10865 @*Name of GDB XML target description feature.
10869 @var{configparams} may have following optional arguments:
10873 @item @code{-gdbnum} number
10874 @*GDB register number. It is recommended to not assign GDB register number
10875 manually, because there would be a risk that two register will have same
10876 number. When register GDB number is not set with this option, then register
10877 will get a previous register number + 1. This option is required only for those
10878 registers that must be at particular address expected by GDB.
10881 @*This option specifies that register is a core registers. If not - this is an
10882 AUX register. AUX registers and core registers reside in different address
10886 @*This options specifies that register is a BCR register. BCR means Build
10887 Configuration Registers - this is a special type of AUX registers that are read
10888 only and non-volatile, that is - they never change their value. Therefore OpenOCD
10889 never invalidates values of those registers in internal caches. Because BCR is a
10890 type of AUX registers, this option cannot be used with @code{-core}.
10892 @item @code{-type} type_name
10893 @*Name of type of this register. This can be either one of the basic GDB types,
10894 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
10897 @* If specified then this is a "general" register. General registers are always
10898 read by OpenOCD on context save (when core has just been halted) and is always
10899 transferred to GDB client in a response to g-packet. Contrary to this,
10900 non-general registers are read and sent to GDB client on-demand. In general it
10901 is not recommended to apply this option to custom registers.
10907 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
10908 Adds new register type of ``flags'' class. ``Flags'' types can contain only
10909 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
10912 @anchor{add-reg-type-struct}
10913 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
10914 Adds new register type of ``struct'' class. ``Struct'' types can contain either
10915 bit-fields or fields of other types, however at the moment only bit fields are
10916 supported. Structure bit field definition looks like @code{-bitfield name
10920 @deffn {Command} {arc get-reg-field} reg-name field-name
10921 Returns value of bit-field in a register. Register must be ``struct'' register
10922 type, @xref{add-reg-type-struct}. command definition.
10925 @deffn {Command} {arc set-reg-exists} reg-names...
10926 Specify that some register exists. Any amount of names can be passed
10927 as an argument for a single command invocation.
10930 @subsection ARC JTAG commands
10932 @deffn {Command} {arc jtag set-aux-reg} regnum value
10933 This command writes value to AUX register via its number. This command access
10934 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10935 therefore it is unsafe to use if that register can be operated by other means.
10939 @deffn {Command} {arc jtag set-core-reg} regnum value
10940 This command is similar to @command{arc jtag set-aux-reg} but is for core
10944 @deffn {Command} {arc jtag get-aux-reg} regnum
10945 This command returns the value storded in AUX register via its number. This commands access
10946 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10947 therefore it is unsafe to use if that register can be operated by other means.
10951 @deffn {Command} {arc jtag get-core-reg} regnum
10952 This command is similar to @command{arc jtag get-aux-reg} but is for core
10956 @section STM8 Architecture
10957 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
10958 STMicroelectronics, based on a proprietary 8-bit core architecture.
10960 OpenOCD supports debugging STM8 through the STMicroelectronics debug
10961 protocol SWIM, @pxref{swimtransport,,SWIM}.
10963 @section Xtensa Architecture
10965 Xtensa is a highly-customizable, user-extensible microprocessor and DSP
10966 architecture for complex embedded systems provided by Cadence Design
10967 Systems, Inc. See the
10968 @uref{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html, Tensilica IP}
10969 website for additional information and documentation.
10971 OpenOCD supports generic Xtensa processor implementations which can be customized by
10972 providing a core-specific configuration file which describes every enabled
10973 Xtensa architecture option, e.g. number of address registers, exceptions, reduced
10974 size instructions support, memory banks configuration etc. OpenOCD also supports SMP
10975 configurations for Xtensa processors with any number of cores and allows configuring
10976 their debug interconnect (termed "break/stall networks"), which control how debug
10977 signals are distributed among cores. Xtensa "break networks" are compatible with
10978 ARM's Cross Trigger Interface (CTI). OpenOCD implements both generic Xtensa targets
10979 as well as several Espressif Xtensa-based chips from the
10980 @uref{https://www.espressif.com/en/products/socs, ESP32 family}.
10982 OCD sessions for Xtensa processor and DSP targets are accessed via the Xtensa
10983 Debug Module (XDM), which provides external connectivity either through a
10984 traditional JTAG interface or an ARM DAP interface. If used, the DAP interface
10985 can control Xtensa targets through JTAG or SWD probes.
10987 @subsection Xtensa Core Configuration
10989 Due to the high level of configurability in Xtensa cores, the Xtensa target
10990 configuration comprises two categories:
10993 @item Base Xtensa support common to all core configurations, and
10994 @item Core-specific support as configured for individual cores.
10997 All common Xtensa support is built into the OpenOCD Xtensa target layer and
10998 is enabled through a combination of TCL scripts: the target-specific
10999 @file{target/xtensa.cfg} and a board-specific @file{board/xtensa-*.cfg},
11000 similar to other target architectures.
11002 Importantly, core-specific configuration information must be provided by
11003 the user, and takes the form of an @file{xtensa-core-XXX.cfg} TCL script that
11004 defines the core's configurable features through a series of Xtensa
11005 configuration commands (detailed below).
11007 This core-specific @file{xtensa-core-XXX.cfg} file is typically either:
11010 @item Located within the Xtensa core configuration build as
11011 @file{src/config/xtensa-core-openocd.cfg}, or
11012 @item Generated by running the command @code{xt-gdb --dump-oocd-config}
11013 from the Xtensa processor tool-chain's command-line tools.
11016 NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware
11017 connected to OpenOCD.
11019 Some example Xtensa configurations are bundled with OpenOCD for reference:
11021 @item Cadence Palladium VDebug emulation target. The user can combine their
11022 @file{xtensa-core-XXX.cfg} with the provided
11023 @file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design.
11024 @item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are
11025 @file{board/xtensa-rt685-jlink.cfg} and @file{board/xtensa-core-nxp_rt600.cfg}.
11026 Additional information is provided by
11027 @uref{https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK,
11031 @subsection Xtensa Configuration Commands
11033 @deffn {Command} {xtensa xtdef} (@option{LX}|@option{NX})
11034 Configure the Xtensa target architecture. Currently, Xtensa support is limited
11035 to LX6, LX7, and NX cores.
11038 @deffn {Command} {xtensa xtopt} option value
11039 Configure Xtensa target options that are relevant to the debug subsystem.
11040 @var{option} is one of: @option{arnum}, @option{windowed},
11041 @option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints},
11042 @option{excmlevel}, @option{intlevels}, @option{debuglevel},
11043 @option{ibreaknum}, or @option{dbreaknum}. @var{value} is an integer with
11044 the exact range determined by each particular option.
11046 NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while
11047 others may be common to both but have different valid ranges.
11050 @deffn {Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
11051 Configure Xtensa target memory. Memory type determines access rights,
11052 where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
11053 @var{bytes} are both integers, typically hexadecimal and decimal, respectively.
11056 @deffn {Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
11057 Configure Xtensa processor cache. All parameters are required except for
11058 the optional @option{writeback} parameter; all are integers.
11061 @deffn {Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
11062 Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict access
11063 and/or control cacheability of specific address ranges, but are lighter-weight
11064 than a full traditional MMU. All parameters are required; all are integers.
11067 @deffn {Command} {xtensa xtmmu} numirefillentries numdrefillentries
11068 (Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU). Both
11069 parameters are required; both are integers.
11072 @deffn {Command} {xtensa xtregs} numregs
11073 Configure the total number of registers for the Xtensa core. Configuration
11074 logic expects to subsequently process this number of @code{xtensa xtreg}
11075 definitions. @var{numregs} is an integer.
11078 @deffn {Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
11079 Configure the type of register map used by GDB to access the Xtensa core.
11080 Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while
11081 Espressif tools expect @option{contiguous} mapping. Contiguous mapping takes an
11082 additional, optional integer parameter @option{numgregs}, which specifies the number
11083 of general registers used in handling g/G packets.
11086 @deffn {Command} {xtensa xtreg} name offset
11087 Configure an Xtensa core register. All core registers are 32 bits wide,
11088 while TIE and user registers may have variable widths. @var{name} is a
11089 character string identifier while @var{offset} is a hexadecimal integer.
11092 @subsection Xtensa Operation Commands
11094 @deffn {Command} {xtensa maskisr} (@option{on}|@option{off})
11095 (Xtensa-LX only) Mask or unmask Xtensa interrupts during instruction step.
11096 When masked, an interrupt that occurs during a step operation is handled and
11097 its ISR is executed, with the user's debug session returning after potentially
11098 executing many instructions. When unmasked, a triggered interrupt will result
11099 in execution progressing the requested number of instructions into the relevant
11103 @deffn {Command} {xtensa set_permissive} (0|1)
11104 By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
11105 When set to (1), skips access controls and address range check before read/write memory.
11108 @deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
11109 Configures debug signals connection ("break network") for currently selected core.
11111 @item @code{none} - Core's "break/stall network" is disconnected. Core is not affected by any debug
11112 signal from other cores.
11113 @item @code{breakinout} - Core's "break network" is fully connected (break inputs and outputs are enabled).
11114 Core will receive debug break signals from other cores and send such signals to them. For example when another core
11115 is stopped due to breakpoint hit this core will be stopped too and vice versa.
11116 @item @code{runstall} - Core's "stall network" is fully connected (stall inputs and outputs are enabled).
11117 This feature is not well implemented and tested yet.
11118 @item @code{BreakIn} - Core's "break-in" signal is enabled.
11119 Core will receive debug break signals from other cores. For example when another core is
11120 stopped due to breakpoint hit this core will be stopped too.
11121 @item @code{BreakOut} - Core's "break-out" signal is enabled.
11122 Core will send debug break signal to other cores. For example when this core is
11123 stopped due to breakpoint hit other cores with enabled break-in signals will be stopped too.
11124 @item @code{RunStallIn} - Core's "runstall-in" signal is enabled.
11125 This feature is not well implemented and tested yet.
11126 @item @code{DebugModeOut} - Core's "debugmode-out" signal is enabled.
11127 This feature is not well implemented and tested yet.
11131 @deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes>
11132 Execute arbitrary instruction(s) provided as an ascii string. The string represents an integer
11133 number of instruction bytes, thus its length must be even.
11136 @subsection Xtensa Performance Monitor Configuration
11138 @deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
11139 Enable and start performance counter.
11141 @item @code{counter_id} - Counter ID (0-1).
11142 @item @code{select} - Selects performance metric to be counted by the counter,
11143 e.g. 0 - CPU cycles, 2 - retired instructions.
11144 @item @code{mask} - Selects input subsets to be counted (counter will
11145 increment only once even if more than one condition corresponding to a mask bit occurs).
11146 @item @code{kernelcnt} - 0 - count events with "CINTLEVEL <= tracelevel",
11147 1 - count events with "CINTLEVEL > tracelevel".
11148 @item @code{tracelevel} - Compares this value to "CINTLEVEL" when deciding
11153 @deffn {Command} {xtensa perfmon_dump} (counter_id)
11154 Dump performance counter value. If no argument specified, dumps all counters.
11157 @subsection Xtensa Trace Configuration
11159 @deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
11160 Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
11161 This command also allows to specify the amount of data to capture after stop trigger activation.
11163 @item @code{pcval} - PC value which will trigger trace data collection stop.
11164 @item @code{maskbitcount} - PC value mask.
11165 @item @code{n} - Maximum number of instructions/words to capture after trace stop trigger.
11169 @deffn {Command} {xtensa tracestop}
11170 Stop current trace as started by the tracestart command.
11173 @deffn {Command} {xtensa tracedump} <outfile>
11174 Dump trace memory to a file.
11177 @anchor{softwaredebugmessagesandtracing}
11178 @section Software Debug Messages and Tracing
11179 @cindex Linux-ARM DCC support
11183 OpenOCD can process certain requests from target software, when
11184 the target uses appropriate libraries.
11185 The most powerful mechanism is semihosting, but there is also
11186 a lighter weight mechanism using only the DCC channel.
11188 Currently @command{target_request debugmsgs}
11189 is supported only for @option{arm7_9} and @option{cortex_m} cores.
11190 These messages are received as part of target polling, so
11191 you need to have @command{poll on} active to receive them.
11192 They are intrusive in that they will affect program execution
11193 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
11195 See @file{libdcc} in the contrib dir for more details.
11196 In addition to sending strings, characters, and
11197 arrays of various size integers from the target,
11198 @file{libdcc} also exports a software trace point mechanism.
11199 The target being debugged may
11200 issue trace messages which include a 24-bit @dfn{trace point} number.
11201 Trace point support includes two distinct mechanisms,
11202 each supported by a command:
11205 @item @emph{History} ... A circular buffer of trace points
11206 can be set up, and then displayed at any time.
11207 This tracks where code has been, which can be invaluable in
11208 finding out how some fault was triggered.
11210 The buffer may overflow, since it collects records continuously.
11211 It may be useful to use some of the 24 bits to represent a
11212 particular event, and other bits to hold data.
11214 @item @emph{Counting} ... An array of counters can be set up,
11215 and then displayed at any time.
11216 This can help establish code coverage and identify hot spots.
11218 The array of counters is directly indexed by the trace point
11219 number, so trace points with higher numbers are not counted.
11222 Linux-ARM kernels have a ``Kernel low-level debugging
11223 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
11224 depends on CONFIG_DEBUG_LL) which uses this mechanism to
11225 deliver messages before a serial console can be activated.
11226 This is not the same format used by @file{libdcc}.
11227 Other software, such as the U-Boot boot loader, sometimes
11228 does the same thing.
11230 @deffn {Command} {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
11231 Displays current handling of target DCC message requests.
11232 These messages may be sent to the debugger while the target is running.
11233 The optional @option{enable} and @option{charmsg} parameters
11234 both enable the messages, while @option{disable} disables them.
11236 With @option{charmsg} the DCC words each contain one character,
11237 as used by Linux with CONFIG_DEBUG_ICEDCC;
11238 otherwise the libdcc format is used.
11241 @deffn {Command} {trace history} [@option{clear}|count]
11242 With no parameter, displays all the trace points that have triggered
11243 in the order they triggered.
11244 With the parameter @option{clear}, erases all current trace history records.
11245 With a @var{count} parameter, allocates space for that many
11249 @deffn {Command} {trace point} [@option{clear}|identifier]
11250 With no parameter, displays all trace point identifiers and how many times
11251 they have been triggered.
11252 With the parameter @option{clear}, erases all current trace point counters.
11253 With a numeric @var{identifier} parameter, creates a new a trace point counter
11254 and associates it with that identifier.
11256 @emph{Important:} The identifier and the trace point number
11257 are not related except by this command.
11258 These trace point numbers always start at zero (from server startup,
11259 or after @command{trace point clear}) and count up from there.
11263 @node JTAG Commands
11264 @chapter JTAG Commands
11265 @cindex JTAG Commands
11266 Most general purpose JTAG commands have been presented earlier.
11267 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
11268 Lower level JTAG commands, as presented here,
11269 may be needed to work with targets which require special
11270 attention during operations such as reset or initialization.
11272 To use these commands you will need to understand some
11273 of the basics of JTAG, including:
11276 @item A JTAG scan chain consists of a sequence of individual TAP
11277 devices such as a CPUs.
11278 @item Control operations involve moving each TAP through the same
11279 standard state machine (in parallel)
11280 using their shared TMS and clock signals.
11281 @item Data transfer involves shifting data through the chain of
11282 instruction or data registers of each TAP, writing new register values
11283 while the reading previous ones.
11284 @item Data register sizes are a function of the instruction active in
11285 a given TAP, while instruction register sizes are fixed for each TAP.
11286 All TAPs support a BYPASS instruction with a single bit data register.
11287 @item The way OpenOCD differentiates between TAP devices is by
11288 shifting different instructions into (and out of) their instruction
11292 @section Low Level JTAG Commands
11294 These commands are used by developers who need to access
11295 JTAG instruction or data registers, possibly controlling
11296 the order of TAP state transitions.
11297 If you're not debugging OpenOCD internals, or bringing up a
11298 new JTAG adapter or a new type of TAP device (like a CPU or
11299 JTAG router), you probably won't need to use these commands.
11300 In a debug session that doesn't use JTAG for its transport protocol,
11301 these commands are not available.
11303 @deffn {Command} {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
11304 Loads the data register of @var{tap} with a series of bit fields
11305 that specify the entire register.
11306 Each field is @var{numbits} bits long with
11307 a numeric @var{value} (hexadecimal encouraged).
11308 The return value holds the original value of each
11311 For example, a 38 bit number might be specified as one
11312 field of 32 bits then one of 6 bits.
11313 @emph{For portability, never pass fields which are more
11314 than 32 bits long. Many OpenOCD implementations do not
11315 support 64-bit (or larger) integer values.}
11317 All TAPs other than @var{tap} must be in BYPASS mode.
11318 The single bit in their data registers does not matter.
11320 When @var{tap_state} is specified, the JTAG state machine is left
11322 For example @sc{drpause} might be specified, so that more
11323 instructions can be issued before re-entering the @sc{run/idle} state.
11324 If the end state is not specified, the @sc{run/idle} state is entered.
11327 OpenOCD does not record information about data register lengths,
11328 so @emph{it is important that you get the bit field lengths right}.
11329 Remember that different JTAG instructions refer to different
11330 data registers, which may have different lengths.
11331 Moreover, those lengths may not be fixed;
11332 the SCAN_N instruction can change the length of
11333 the register accessed by the INTEST instruction
11334 (by connecting a different scan chain).
11338 @deffn {Command} {flush_count}
11339 Returns the number of times the JTAG queue has been flushed.
11340 This may be used for performance tuning.
11342 For example, flushing a queue over USB involves a
11343 minimum latency, often several milliseconds, which does
11344 not change with the amount of data which is written.
11345 You may be able to identify performance problems by finding
11346 tasks which waste bandwidth by flushing small transfers too often,
11347 instead of batching them into larger operations.
11350 @deffn {Command} {irscan} [tap instruction]+ [@option{-endstate} tap_state]
11351 For each @var{tap} listed, loads the instruction register
11352 with its associated numeric @var{instruction}.
11353 (The number of bits in that instruction may be displayed
11354 using the @command{scan_chain} command.)
11355 For other TAPs, a BYPASS instruction is loaded.
11357 When @var{tap_state} is specified, the JTAG state machine is left
11359 For example @sc{irpause} might be specified, so the data register
11360 can be loaded before re-entering the @sc{run/idle} state.
11361 If the end state is not specified, the @sc{run/idle} state is entered.
11364 OpenOCD currently supports only a single field for instruction
11365 register values, unlike data register values.
11366 For TAPs where the instruction register length is more than 32 bits,
11367 portable scripts currently must issue only BYPASS instructions.
11371 @deffn {Command} {pathmove} start_state [next_state ...]
11372 Start by moving to @var{start_state}, which
11373 must be one of the @emph{stable} states.
11374 Unless it is the only state given, this will often be the
11375 current state, so that no TCK transitions are needed.
11376 Then, in a series of single state transitions
11377 (conforming to the JTAG state machine) shift to
11378 each @var{next_state} in sequence, one per TCK cycle.
11379 The final state must also be stable.
11382 @deffn {Command} {runtest} @var{num_cycles}
11383 Move to the @sc{run/idle} state, and execute at least
11384 @var{num_cycles} of the JTAG clock (TCK).
11385 Instructions often need some time
11386 to execute before they take effect.
11389 @c tms_sequence (short|long)
11390 @c ... temporary, debug-only, other than USBprog bug workaround...
11392 @deffn {Command} {verify_ircapture} (@option{enable}|@option{disable})
11393 Verify values captured during @sc{ircapture} and returned
11394 during IR scans. Default is enabled, but this can be
11395 overridden by @command{verify_jtag}.
11396 This flag is ignored when validating JTAG chain configuration.
11399 @deffn {Command} {verify_jtag} (@option{enable}|@option{disable})
11400 Enables verification of DR and IR scans, to help detect
11401 programming errors. For IR scans, @command{verify_ircapture}
11402 must also be enabled.
11403 Default is enabled.
11406 @section TAP state names
11407 @cindex TAP state names
11409 The @var{tap_state} names used by OpenOCD in the @command{drscan},
11410 @command{irscan}, and @command{pathmove} commands are the same
11411 as those used in SVF boundary scan documents, except that
11412 SVF uses @sc{idle} instead of @sc{run/idle}.
11415 @item @b{RESET} ... @emph{stable} (with TMS high);
11416 acts as if TRST were pulsed
11417 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
11419 @item @b{DRCAPTURE}
11420 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
11421 through the data register
11423 @item @b{DRPAUSE} ... @emph{stable}; data register ready
11424 for update or more shifting
11428 @item @b{IRCAPTURE}
11429 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
11430 through the instruction register
11432 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
11433 for update or more shifting
11438 Note that only six of those states are fully ``stable'' in the
11439 face of TMS fixed (low except for @sc{reset})
11440 and a free-running JTAG clock. For all the
11441 others, the next TCK transition changes to a new state.
11444 @item From @sc{drshift} and @sc{irshift}, clock transitions will
11445 produce side effects by changing register contents. The values
11446 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
11447 may not be as expected.
11448 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
11449 choices after @command{drscan} or @command{irscan} commands,
11450 since they are free of JTAG side effects.
11451 @item @sc{run/idle} may have side effects that appear at non-JTAG
11452 levels, such as advancing the ARM9E-S instruction pipeline.
11453 Consult the documentation for the TAP(s) you are working with.
11456 @node Boundary Scan Commands
11457 @chapter Boundary Scan Commands
11459 One of the original purposes of JTAG was to support
11460 boundary scan based hardware testing.
11461 Although its primary focus is to support On-Chip Debugging,
11462 OpenOCD also includes some boundary scan commands.
11464 @section SVF: Serial Vector Format
11465 @cindex Serial Vector Format
11468 The Serial Vector Format, better known as @dfn{SVF}, is a
11469 way to represent JTAG test patterns in text files.
11470 In a debug session using JTAG for its transport protocol,
11471 OpenOCD supports running such test files.
11473 @deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
11474 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
11475 This issues a JTAG reset (Test-Logic-Reset) and then
11476 runs the SVF script from @file{filename}.
11478 Arguments can be specified in any order; the optional dash doesn't
11479 affect their semantics.
11483 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
11484 specified by the SVF file with HIR, TIR, HDR and TDR commands;
11485 instead, calculate them automatically according to the current JTAG
11486 chain configuration, targeting @var{tapname};
11487 @item @option{[-]quiet} do not log every command before execution;
11488 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
11489 on the real interface;
11490 @item @option{[-]progress} enable progress indication;
11491 @item @option{[-]ignore_error} continue execution despite TDO check
11496 @section XSVF: Xilinx Serial Vector Format
11497 @cindex Xilinx Serial Vector Format
11500 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
11501 binary representation of SVF which is optimized for use with
11503 In a debug session using JTAG for its transport protocol,
11504 OpenOCD supports running such test files.
11506 @quotation Important
11507 Not all XSVF commands are supported.
11510 @deffn {Command} {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
11511 This issues a JTAG reset (Test-Logic-Reset) and then
11512 runs the XSVF script from @file{filename}.
11513 When a @var{tapname} is specified, the commands are directed at
11515 When @option{virt2} is specified, the @sc{xruntest} command counts
11516 are interpreted as TCK cycles instead of microseconds.
11517 Unless the @option{quiet} option is specified,
11518 messages are logged for comments and some retries.
11521 The OpenOCD sources also include two utility scripts
11522 for working with XSVF; they are not currently installed
11523 after building the software.
11524 You may find them useful:
11527 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
11528 syntax understood by the @command{xsvf} command; see notes below.
11529 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
11530 understands the OpenOCD extensions.
11533 The input format accepts a handful of non-standard extensions.
11534 These include three opcodes corresponding to SVF extensions
11535 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
11536 two opcodes supporting a more accurate translation of SVF
11537 (XTRST, XWAITSTATE).
11538 If @emph{xsvfdump} shows a file is using those opcodes, it
11539 probably will not be usable with other XSVF tools.
11542 @section IPDBG: JTAG-Host server
11543 @cindex IPDBG JTAG-Host server
11546 IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary
11547 waveform generator. These are synthesize-able hardware descriptions of
11548 logic circuits in addition to software for control, visualization and further analysis.
11549 In a session using JTAG for its transport protocol, OpenOCD supports the function
11550 of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the
11551 control-software. For more details see @url{http://ipdbg.org}.
11553 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}]
11554 Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order.
11558 @item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start).
11559 @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}.
11560 @item @option{-hub @var{ir_value}} states that the JTAG hub is
11561 reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}.
11562 @item @option{-port @var{number}} tcp port number where the JTAG-Host is listening.
11563 @item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub.
11564 @item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a
11565 specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an
11566 access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second
11567 parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to
11568 shift data through vir can be configured.
11574 ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4
11576 Starts a server listening on tcp-port 4242 which connects to tool 4.
11577 The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board).
11580 ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1
11582 Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1).
11583 The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5).
11585 @node Utility Commands
11586 @chapter Utility Commands
11587 @cindex Utility Commands
11589 @section RAM testing
11590 @cindex RAM testing
11592 There is often a need to stress-test random access memory (RAM) for
11593 errors. OpenOCD comes with a Tcl implementation of well-known memory
11594 testing procedures allowing the detection of all sorts of issues with
11595 electrical wiring, defective chips, PCB layout and other common
11598 To use them, you usually need to initialise your RAM controller first;
11599 consult your SoC's documentation to get the recommended list of
11600 register operations and translate them to the corresponding
11601 @command{mww}/@command{mwb} commands.
11603 Load the memory testing functions with
11606 source [find tools/memtest.tcl]
11609 to get access to the following facilities:
11611 @deffn {Command} {memTestDataBus} address
11612 Test the data bus wiring in a memory region by performing a walking
11613 1's test at a fixed address within that region.
11616 @deffn {Command} {memTestAddressBus} baseaddress size
11617 Perform a walking 1's test on the relevant bits of the address and
11618 check for aliasing. This test will find single-bit address failures
11619 such as stuck-high, stuck-low, and shorted pins.
11622 @deffn {Command} {memTestDevice} baseaddress size
11623 Test the integrity of a physical memory device by performing an
11624 increment/decrement test over the entire region. In the process every
11625 storage bit in the device is tested as zero and as one.
11628 @deffn {Command} {runAllMemTests} baseaddress size
11629 Run all of the above tests over a specified memory region.
11632 @section Firmware recovery helpers
11633 @cindex Firmware recovery
11635 OpenOCD includes an easy-to-use script to facilitate mass-market
11636 devices recovery with JTAG.
11638 For quickstart instructions run:
11640 openocd -f tools/firmware-recovery.tcl -c firmware_help
11643 @node GDB and OpenOCD
11644 @chapter GDB and OpenOCD
11646 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
11647 to debug remote targets.
11648 Setting up GDB to work with OpenOCD can involve several components:
11651 @item The OpenOCD server support for GDB may need to be configured.
11652 @xref{gdbconfiguration,,GDB Configuration}.
11653 @item GDB's support for OpenOCD may need configuration,
11654 as shown in this chapter.
11655 @item If you have a GUI environment like Eclipse,
11656 that also will probably need to be configured.
11659 Of course, the version of GDB you use will need to be one which has
11660 been built to know about the target CPU you're using. It's probably
11661 part of the tool chain you're using. For example, if you are doing
11662 cross-development for ARM on an x86 PC, instead of using the native
11663 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
11664 if that's the tool chain used to compile your code.
11666 @section Connecting to GDB
11667 @cindex Connecting to GDB
11668 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
11669 instance GDB 6.3 has a known bug that produces bogus memory access
11670 errors, which has since been fixed; see
11671 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
11673 OpenOCD can communicate with GDB in two ways:
11677 A socket (TCP/IP) connection is typically started as follows:
11679 target extended-remote localhost:3333
11681 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
11683 The extended remote protocol is a super-set of the remote protocol and should
11684 be the preferred choice. More details are available in GDB documentation
11685 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
11687 To speed-up typing, any GDB command can be abbreviated, including the extended
11688 remote command above that becomes:
11693 @b{Note:} If any backward compatibility issue requires using the old remote
11694 protocol in place of the extended remote one, the former protocol is still
11695 available through the command:
11697 target remote localhost:3333
11701 A pipe connection is typically started as follows:
11703 target extended-remote | \
11704 openocd -c "gdb_port pipe; log_output openocd.log"
11706 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
11707 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
11708 session. log_output sends the log output to a file to ensure that the pipe is
11709 not saturated when using higher debug level outputs.
11712 To list the available OpenOCD commands type @command{monitor help} on the
11715 @section Sample GDB session startup
11717 With the remote protocol, GDB sessions start a little differently
11718 than they do when you're debugging locally.
11719 Here's an example showing how to start a debug session with a
11721 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
11722 Most programs would be written into flash (address 0) and run from there.
11725 $ arm-none-eabi-gdb example.elf
11726 (gdb) target extended-remote localhost:3333
11727 Remote debugging using localhost:3333
11729 (gdb) monitor reset halt
11732 Loading section .vectors, size 0x100 lma 0x20000000
11733 Loading section .text, size 0x5a0 lma 0x20000100
11734 Loading section .data, size 0x18 lma 0x200006a0
11735 Start address 0x2000061c, load size 1720
11736 Transfer rate: 22 KB/sec, 573 bytes/write.
11742 You could then interrupt the GDB session to make the program break,
11743 type @command{where} to show the stack, @command{list} to show the
11744 code around the program counter, @command{step} through code,
11745 set breakpoints or watchpoints, and so on.
11747 @section Configuring GDB for OpenOCD
11749 OpenOCD supports the gdb @option{qSupported} packet, this enables information
11750 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
11751 packet size and the device's memory map.
11752 You do not need to configure the packet size by hand,
11753 and the relevant parts of the memory map should be automatically
11754 set up when you declare (NOR) flash banks.
11756 However, there are other things which GDB can't currently query.
11757 You may need to set those up by hand.
11758 As OpenOCD starts up, you will often see a line reporting
11762 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
11765 You can pass that information to GDB with these commands:
11768 set remote hardware-breakpoint-limit 6
11769 set remote hardware-watchpoint-limit 4
11772 With that particular hardware (Cortex-M3) the hardware breakpoints
11773 only work for code running from flash memory. Most other ARM systems
11774 do not have such restrictions.
11776 Rather than typing such commands interactively, you may prefer to
11777 save them in a file and have GDB execute them as it starts, perhaps
11778 using a @file{.gdbinit} in your project directory or starting GDB
11779 using @command{gdb -x filename}.
11781 @section Programming using GDB
11782 @cindex Programming using GDB
11783 @anchor{programmingusinggdb}
11785 By default the target memory map is sent to GDB. This can be disabled by
11786 the following OpenOCD configuration option:
11788 gdb_memory_map disable
11790 For this to function correctly a valid flash configuration must also be set
11791 in OpenOCD. For faster performance you should also configure a valid
11794 Informing GDB of the memory map of the target will enable GDB to protect any
11795 flash areas of the target and use hardware breakpoints by default. This means
11796 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
11797 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
11799 To view the configured memory map in GDB, use the GDB command @option{info mem}.
11800 All other unassigned addresses within GDB are treated as RAM.
11802 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
11803 This can be changed to the old behaviour by using the following GDB command
11805 set mem inaccessible-by-default off
11808 If @command{gdb_flash_program enable} is also used, GDB will be able to
11809 program any flash memory using the vFlash interface.
11811 GDB will look at the target memory map when a load command is given, if any
11812 areas to be programmed lie within the target flash area the vFlash packets
11815 If the target needs configuring before GDB programming, set target
11816 event gdb-flash-erase-start:
11818 $_TARGETNAME configure -event gdb-flash-erase-start BODY
11820 @xref{targetevents,,Target Events}, for other GDB programming related events.
11822 To verify any flash programming the GDB command @option{compare-sections}
11825 @section Using GDB as a non-intrusive memory inspector
11826 @cindex Using GDB as a non-intrusive memory inspector
11827 @anchor{gdbmeminspect}
11829 If your project controls more than a blinking LED, let's say a heavy industrial
11830 robot or an experimental nuclear reactor, stopping the controlling process
11831 just because you want to attach GDB is not a good option.
11833 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
11834 Though there is a possible setup where the target does not get stopped
11835 and GDB treats it as it were running.
11836 If the target supports background access to memory while it is running,
11837 you can use GDB in this mode to inspect memory (mainly global variables)
11838 without any intrusion of the target process.
11840 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
11841 Place following command after target configuration:
11843 $_TARGETNAME configure -event gdb-attach @{@}
11846 If any of installed flash banks does not support probe on running target,
11847 switch off gdb_memory_map:
11849 gdb_memory_map disable
11852 Ensure GDB is configured without interrupt-on-connect.
11853 Some GDB versions set it by default, some does not.
11855 set remote interrupt-on-connect off
11858 If you switched gdb_memory_map off, you may want to setup GDB memory map
11859 manually or issue @command{set mem inaccessible-by-default off}
11861 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
11862 of a running target. Do not use GDB commands @command{continue},
11863 @command{step} or @command{next} as they synchronize GDB with your target
11864 and GDB would require stopping the target to get the prompt back.
11866 Do not use this mode under an IDE like Eclipse as it caches values of
11867 previously shown variables.
11869 It's also possible to connect more than one GDB to the same target by the
11870 target's configuration option @code{-gdb-max-connections}. This allows, for
11871 example, one GDB to run a script that continuously polls a set of variables
11872 while other GDB can be used interactively. Be extremely careful in this case,
11873 because the two GDB can easily get out-of-sync.
11875 @section RTOS Support
11876 @cindex RTOS Support
11877 @anchor{gdbrtossupport}
11879 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
11880 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
11882 @xref{Threads, Debugging Programs with Multiple Threads,
11883 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
11886 @* An example setup is below:
11889 $_TARGETNAME configure -rtos auto
11892 This will attempt to auto detect the RTOS within your application.
11894 Currently supported rtos's include:
11896 @item @option{eCos}
11897 @item @option{ThreadX}
11898 @item @option{FreeRTOS}
11899 @item @option{linux}
11900 @item @option{ChibiOS}
11901 @item @option{embKernel}
11903 @item @option{uCOS-III}
11904 @item @option{nuttx}
11905 @item @option{RIOT}
11906 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
11907 @item @option{Zephyr}
11910 At any time, it's possible to drop the selected RTOS using:
11912 $_TARGETNAME configure -rtos none
11915 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
11916 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
11920 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
11921 @item ThreadX symbols
11922 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
11923 @item FreeRTOS symbols
11925 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
11926 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
11927 uxCurrentNumberOfTasks, uxTopUsedPriority.
11929 @item linux symbols
11931 @item ChibiOS symbols
11932 rlist, ch_debug, chSysInit.
11933 @item embKernel symbols
11934 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
11935 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
11937 _mqx_kernel_data, MQX_init_struct.
11938 @item uC/OS-III symbols
11939 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
11940 @item nuttx symbols
11941 g_readytorun, g_tasklisttable.
11944 sched_threads, sched_num_threads, sched_active_pid, max_threads,
11947 @item Zephyr symbols
11948 _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
11951 For most RTOS supported the above symbols will be exported by default. However for
11952 some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken.
11954 Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols
11955 with information needed in order to build the list of threads.
11957 FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked
11958 along with the project:
11962 contrib/rtos-helpers/FreeRTOS-openocd.c
11964 contrib/rtos-helpers/uCOS-III-openocd.c
11967 @anchor{usingopenocdsmpwithgdb}
11968 @section Using OpenOCD SMP with GDB
11972 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
11973 ("hardware threads") in an SMP system as threads to GDB. With this extension,
11974 GDB can be used to inspect the state of an SMP system in a natural way.
11975 After halting the system, using the GDB command @command{info threads} will
11976 list the context of each active CPU core in the system. GDB's @command{thread}
11977 command can be used to switch the view to a different CPU core.
11978 The @command{step} and @command{stepi} commands can be used to step a specific core
11979 while other cores are free-running or remain halted, depending on the
11980 scheduler-locking mode configured in GDB.
11982 @node Tcl Scripting API
11983 @chapter Tcl Scripting API
11984 @cindex Tcl Scripting API
11985 @cindex Tcl scripts
11988 Tcl commands are stateless; e.g. the @command{telnet} command has
11989 a concept of currently active target, the Tcl API proc's take this sort
11990 of state information as an argument to each proc.
11992 There are three main types of return values: single value, name value
11993 pair list and lists.
11995 Name value pair. The proc 'foo' below returns a name/value pair
11999 > set foo(me) Duane
12000 > set foo(you) Oyvind
12001 > set foo(mouse) Micky
12002 > set foo(duck) Donald
12014 me Duane you Oyvind mouse Micky duck Donald
12017 Thus, to get the names of the associative array is easy:
12020 foreach { name value } [set foo] {
12021 puts "Name: $name, Value: $value"
12025 Lists returned should be relatively small. Otherwise, a range
12026 should be passed in to the proc in question.
12028 @section Internal low-level Commands
12030 By "low-level", we mean commands that a human would typically not
12034 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
12036 Return information about the flash banks
12038 @item @b{capture} <@var{command}>
12040 Run <@var{command}> and return full log output that was produced during
12041 its execution. Example:
12044 > capture "reset init"
12049 OpenOCD commands can consist of two words, e.g. "flash banks". The
12050 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
12051 called "flash_banks".
12053 @section Tcl RPC server
12056 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
12057 commands and receive the results.
12059 To access it, your application needs to connect to a configured TCP port
12060 (see @command{tcl_port}). Then it can pass any string to the
12061 interpreter terminating it with @code{0x1a} and wait for the return
12062 value (it will be terminated with @code{0x1a} as well). This can be
12063 repeated as many times as desired without reopening the connection.
12065 It is not needed anymore to prefix the OpenOCD commands with
12066 @code{ocd_} to get the results back. But sometimes you might need the
12067 @command{capture} command.
12069 See @file{contrib/rpc_examples/} for specific client implementations.
12071 @section Tcl RPC server notifications
12072 @cindex RPC Notifications
12074 Notifications are sent asynchronously to other commands being executed over
12075 the RPC server, so the port must be polled continuously.
12077 Target event, state and reset notifications are emitted as Tcl associative arrays
12078 in the following format.
12081 type target_event event [event-name]
12082 type target_state state [state-name]
12083 type target_reset mode [reset-mode]
12086 @deffn {Command} {tcl_notifications} [on/off]
12087 Toggle output of target notifications to the current Tcl RPC server.
12088 Only available from the Tcl RPC server.
12093 @section Tcl RPC server trace output
12094 @cindex RPC trace output
12096 Trace data is sent asynchronously to other commands being executed over
12097 the RPC server, so the port must be polled continuously.
12099 Target trace data is emitted as a Tcl associative array in the following format.
12102 type target_trace data [trace-data-hex-encoded]
12105 @deffn {Command} {tcl_trace} [on/off]
12106 Toggle output of target trace data to the current Tcl RPC server.
12107 Only available from the Tcl RPC server.
12110 See an example application here:
12111 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
12120 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
12122 @cindex adaptive clocking
12125 In digital circuit design it is often referred to as ``clock
12126 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
12127 operating at some speed, your CPU target is operating at another.
12128 The two clocks are not synchronised, they are ``asynchronous''
12130 In order for the two to work together they must be synchronised
12131 well enough to work; JTAG can't go ten times faster than the CPU,
12132 for example. There are 2 basic options:
12135 Use a special "adaptive clocking" circuit to change the JTAG
12136 clock rate to match what the CPU currently supports.
12138 The JTAG clock must be fixed at some speed that's enough slower than
12139 the CPU clock that all TMS and TDI transitions can be detected.
12142 @b{Does this really matter?} For some chips and some situations, this
12143 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
12144 the CPU has no difficulty keeping up with JTAG.
12145 Startup sequences are often problematic though, as are other
12146 situations where the CPU clock rate changes (perhaps to save
12149 For example, Atmel AT91SAM chips start operation from reset with
12150 a 32kHz system clock. Boot firmware may activate the main oscillator
12151 and PLL before switching to a faster clock (perhaps that 500 MHz
12153 If you're using JTAG to debug that startup sequence, you must slow
12154 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
12155 JTAG can use a faster clock.
12157 Consider also debugging a 500MHz ARM926 hand held battery powered
12158 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
12159 clock, between keystrokes unless it has work to do. When would
12160 that 5 MHz JTAG clock be usable?
12162 @b{Solution #1 - A special circuit}
12164 In order to make use of this,
12165 your CPU, board, and JTAG adapter must all support the RTCK
12166 feature. Not all of them support this; keep reading!
12168 The RTCK ("Return TCK") signal in some ARM chips is used to help with
12169 this problem. ARM has a good description of the problem described at
12170 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
12171 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
12172 work? / how does adaptive clocking work?''.
12174 The nice thing about adaptive clocking is that ``battery powered hand
12175 held device example'' - the adaptiveness works perfectly all the
12176 time. One can set a break point or halt the system in the deep power
12177 down code, slow step out until the system speeds up.
12179 Note that adaptive clocking may also need to work at the board level,
12180 when a board-level scan chain has multiple chips.
12181 Parallel clock voting schemes are good way to implement this,
12182 both within and between chips, and can easily be implemented
12184 It's not difficult to have logic fan a module's input TCK signal out
12185 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
12186 back with the right polarity before changing the output RTCK signal.
12187 Texas Instruments makes some clock voting logic available
12188 for free (with no support) in VHDL form; see
12189 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
12191 @b{Solution #2 - Always works - but may be slower}
12193 Often this is a perfectly acceptable solution.
12195 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
12196 the target clock speed. But what that ``magic division'' is varies
12197 depending on the chips on your board.
12198 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
12199 ARM11 cores use an 8:1 division.
12200 @b{Xilinx rule of thumb} is 1/12 the clock speed.
12202 Note: most full speed FT2232 based JTAG adapters are limited to a
12203 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
12204 often support faster clock rates (and adaptive clocking).
12206 You can still debug the 'low power' situations - you just need to
12207 either use a fixed and very slow JTAG clock rate ... or else
12208 manually adjust the clock speed at every step. (Adjusting is painful
12209 and tedious, and is not always practical.)
12211 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
12212 have a special debug mode in your application that does a ``high power
12213 sleep''. If you are careful - 98% of your problems can be debugged
12216 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
12217 operation in your idle loops even if you don't otherwise change the CPU
12219 That operation gates the CPU clock, and thus the JTAG clock; which
12220 prevents JTAG access. One consequence is not being able to @command{halt}
12221 cores which are executing that @emph{wait for interrupt} operation.
12223 To set the JTAG frequency use the command:
12226 # Example: 1.234MHz
12231 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
12233 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
12234 around Windows filenames.
12247 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
12249 Make sure you have Cygwin installed, or at least a version of OpenOCD that
12250 claims to come with all the necessary DLLs. When using Cygwin, try launching
12251 OpenOCD from the Cygwin shell.
12253 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
12254 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
12255 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
12257 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
12258 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
12259 software breakpoints consume one of the two available hardware breakpoints.
12261 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
12263 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
12264 clock at the time you're programming the flash. If you've specified the crystal's
12265 frequency, make sure the PLL is disabled. If you've specified the full core speed
12266 (e.g. 60MHz), make sure the PLL is enabled.
12268 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
12269 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
12270 out while waiting for end of scan, rtck was disabled".
12272 Make sure your PC's parallel port operates in EPP mode. You might have to try several
12273 settings in your PC BIOS (ECP, EPP, and different versions of those).
12275 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
12276 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
12277 memory read caused data abort".
12279 The errors are non-fatal, and are the result of GDB trying to trace stack frames
12280 beyond the last valid frame. It might be possible to prevent this by setting up
12281 a proper "initial" stack frame, if you happen to know what exactly has to
12282 be done, feel free to add this here.
12284 @b{Simple:} In your startup code - push 8 registers of zeros onto the
12285 stack before calling main(). What GDB is doing is ``climbing'' the run
12286 time stack by reading various values on the stack using the standard
12287 call frame for the target. GDB keeps going - until one of 2 things
12288 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
12289 stackframes have been processed. By pushing zeros on the stack, GDB
12292 @b{Debugging Interrupt Service Routines} - In your ISR before you call
12293 your C code, do the same - artificially push some zeros onto the stack,
12294 remember to pop them off when the ISR is done.
12296 @b{Also note:} If you have a multi-threaded operating system, they
12297 often do not @b{in the interest of saving memory} waste these few
12301 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
12302 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
12304 This warning doesn't indicate any serious problem, as long as you don't want to
12305 debug your core right out of reset. Your .cfg file specified @option{reset_config
12306 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
12307 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
12308 independently. With this setup, it's not possible to halt the core right out of
12309 reset, everything else should work fine.
12311 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
12312 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
12313 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
12314 quit with an error message. Is there a stability issue with OpenOCD?
12316 No, this is not a stability issue concerning OpenOCD. Most users have solved
12317 this issue by simply using a self-powered USB hub, which they connect their
12318 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
12319 supply stable enough for the Amontec JTAGkey to be operated.
12321 @b{Laptops running on battery have this problem too...}
12323 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
12324 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
12325 What does that mean and what might be the reason for this?
12327 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
12328 has closed the connection to OpenOCD. This might be a GDB issue.
12330 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
12331 are described, there is a parameter for specifying the clock frequency
12332 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
12333 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
12334 specified in kilohertz. However, I do have a quartz crystal of a
12335 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
12336 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
12339 No. The clock frequency specified here must be given as an integral number.
12340 However, this clock frequency is used by the In-Application-Programming (IAP)
12341 routines of the LPC2000 family only, which seems to be very tolerant concerning
12342 the given clock frequency, so a slight difference between the specified clock
12343 frequency and the actual clock frequency will not cause any trouble.
12345 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
12347 Well, yes and no. Commands can be given in arbitrary order, yet the
12348 devices listed for the JTAG scan chain must be given in the right
12349 order (jtag newdevice), with the device closest to the TDO-Pin being
12350 listed first. In general, whenever objects of the same type exist
12351 which require an index number, then these objects must be given in the
12352 right order (jtag newtap, targets and flash banks - a target
12353 references a jtag newtap and a flash bank references a target).
12355 You can use the ``scan_chain'' command to verify and display the tap order.
12357 Also, some commands can't execute until after @command{init} has been
12358 processed. Such commands include @command{nand probe} and everything
12359 else that needs to write to controller registers, perhaps for setting
12360 up DRAM and loading it with code.
12362 @anchor{faqtaporder}
12363 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
12366 Yes; whenever you have more than one, you must declare them in
12367 the same order used by the hardware.
12369 Many newer devices have multiple JTAG TAPs. For example:
12370 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
12371 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
12372 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
12373 connected to the boundary scan TAP, which then connects to the
12374 Cortex-M3 TAP, which then connects to the TDO pin.
12376 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
12377 (2) The boundary scan TAP. If your board includes an additional JTAG
12378 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
12379 place it before or after the STM32 chip in the chain. For example:
12382 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
12383 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
12384 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
12385 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
12386 @item Xilinx TDO Pin -> OpenOCD TDO (input)
12389 The ``jtag device'' commands would thus be in the order shown below. Note:
12392 @item jtag newtap Xilinx tap -irlen ...
12393 @item jtag newtap stm32 cpu -irlen ...
12394 @item jtag newtap stm32 bs -irlen ...
12395 @item # Create the debug target and say where it is
12396 @item target create stm32.cpu -chain-position stm32.cpu ...
12400 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
12401 log file, I can see these error messages: Error: arm7_9_common.c:561
12402 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
12408 @node Tcl Crash Course
12409 @chapter Tcl Crash Course
12412 Not everyone knows Tcl - this is not intended to be a replacement for
12413 learning Tcl, the intent of this chapter is to give you some idea of
12414 how the Tcl scripts work.
12416 This chapter is written with two audiences in mind. (1) OpenOCD users
12417 who need to understand a bit more of how Jim-Tcl works so they can do
12418 something useful, and (2) those that want to add a new command to
12421 @section Tcl Rule #1
12422 There is a famous joke, it goes like this:
12424 @item Rule #1: The wife is always correct
12425 @item Rule #2: If you think otherwise, See Rule #1
12428 The Tcl equal is this:
12431 @item Rule #1: Everything is a string
12432 @item Rule #2: If you think otherwise, See Rule #1
12435 As in the famous joke, the consequences of Rule #1 are profound. Once
12436 you understand Rule #1, you will understand Tcl.
12438 @section Tcl Rule #1b
12439 There is a second pair of rules.
12441 @item Rule #1: Control flow does not exist. Only commands
12442 @* For example: the classic FOR loop or IF statement is not a control
12443 flow item, they are commands, there is no such thing as control flow
12445 @item Rule #2: If you think otherwise, See Rule #1
12446 @* Actually what happens is this: There are commands that by
12447 convention, act like control flow key words in other languages. One of
12448 those commands is the word ``for'', another command is ``if''.
12451 @section Per Rule #1 - All Results are strings
12452 Every Tcl command results in a string. The word ``result'' is used
12453 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
12454 Everything is a string}
12456 @section Tcl Quoting Operators
12457 In life of a Tcl script, there are two important periods of time, the
12458 difference is subtle.
12461 @item Evaluation Time
12464 The two key items here are how ``quoted things'' work in Tcl. Tcl has
12465 three primary quoting constructs, the [square-brackets] the
12466 @{curly-braces@} and ``double-quotes''
12468 By now you should know $VARIABLES always start with a $DOLLAR
12469 sign. BTW: To set a variable, you actually use the command ``set'', as
12470 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
12471 = 1'' statement, but without the equal sign.
12474 @item @b{[square-brackets]}
12475 @* @b{[square-brackets]} are command substitutions. It operates much
12476 like Unix Shell `back-ticks`. The result of a [square-bracket]
12477 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
12478 string}. These two statements are roughly identical:
12482 echo "The Date is: $X"
12485 puts "The Date is: $X"
12487 @item @b{``double-quoted-things''}
12488 @* @b{``double-quoted-things''} are just simply quoted
12489 text. $VARIABLES and [square-brackets] are expanded in place - the
12490 result however is exactly 1 string. @i{Remember Rule #1 - Everything
12494 puts "It is now \"[date]\", $x is in 1 hour"
12496 @item @b{@{Curly-Braces@}}
12497 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
12498 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
12499 'single-quote' operators in BASH shell scripts, with the added
12500 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
12501 nested 3 times@}@}@} NOTE: [date] is a bad example;
12502 at this writing, Jim/OpenOCD does not have a date command.
12505 @section Consequences of Rule 1/2/3/4
12507 The consequences of Rule 1 are profound.
12509 @subsection Tokenisation & Execution.
12511 Of course, whitespace, blank lines and #comment lines are handled in
12514 As a script is parsed, each (multi) line in the script file is
12515 tokenised and according to the quoting rules. After tokenisation, that
12516 line is immediately executed.
12518 Multi line statements end with one or more ``still-open''
12519 @{curly-braces@} which - eventually - closes a few lines later.
12521 @subsection Command Execution
12523 Remember earlier: There are no ``control flow''
12524 statements in Tcl. Instead there are COMMANDS that simply act like
12525 control flow operators.
12527 Commands are executed like this:
12530 @item Parse the next line into (argc) and (argv[]).
12531 @item Look up (argv[0]) in a table and call its function.
12532 @item Repeat until End Of File.
12535 It sort of works like this:
12538 ReadAndParse( &argc, &argv );
12540 cmdPtr = LookupCommand( argv[0] );
12542 (*cmdPtr->Execute)( argc, argv );
12546 When the command ``proc'' is parsed (which creates a procedure
12547 function) it gets 3 parameters on the command line. @b{1} the name of
12548 the proc (function), @b{2} the list of parameters, and @b{3} the body
12549 of the function. Note the choice of words: LIST and BODY. The PROC
12550 command stores these items in a table somewhere so it can be found by
12551 ``LookupCommand()''
12553 @subsection The FOR command
12555 The most interesting command to look at is the FOR command. In Tcl,
12556 the FOR command is normally implemented in C. Remember, FOR is a
12557 command just like any other command.
12559 When the ascii text containing the FOR command is parsed, the parser
12560 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
12564 @item The ascii text 'for'
12565 @item The start text
12566 @item The test expression
12567 @item The next text
12568 @item The body text
12571 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
12572 Remember @i{Rule #1 - Everything is a string.} The key point is this:
12573 Often many of those parameters are in @{curly-braces@} - thus the
12574 variables inside are not expanded or replaced until later.
12576 Remember that every Tcl command looks like the classic ``main( argc,
12577 argv )'' function in C. In JimTCL - they actually look like this:
12581 MyCommand( Jim_Interp *interp,
12583 Jim_Obj * const *argvs );
12586 Real Tcl is nearly identical. Although the newer versions have
12587 introduced a byte-code parser and interpreter, but at the core, it
12588 still operates in the same basic way.
12590 @subsection FOR command implementation
12592 To understand Tcl it is perhaps most helpful to see the FOR
12593 command. Remember, it is a COMMAND not a control flow structure.
12595 In Tcl there are two underlying C helper functions.
12597 Remember Rule #1 - You are a string.
12599 The @b{first} helper parses and executes commands found in an ascii
12600 string. Commands can be separated by semicolons, or newlines. While
12601 parsing, variables are expanded via the quoting rules.
12603 The @b{second} helper evaluates an ascii string as a numerical
12604 expression and returns a value.
12606 Here is an example of how the @b{FOR} command could be
12607 implemented. The pseudo code below does not show error handling.
12609 void Execute_AsciiString( void *interp, const char *string );
12611 int Evaluate_AsciiExpression( void *interp, const char *string );
12614 MyForCommand( void *interp,
12619 SetResult( interp, "WRONG number of parameters");
12623 // argv[0] = the ascii string just like C
12625 // Execute the start statement.
12626 Execute_AsciiString( interp, argv[1] );
12628 // Top of loop test
12630 i = Evaluate_AsciiExpression(interp, argv[2]);
12634 // Execute the body
12635 Execute_AsciiString( interp, argv[3] );
12637 // Execute the LOOP part
12638 Execute_AsciiString( interp, argv[4] );
12642 SetResult( interp, "" );
12647 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
12648 in the same basic way.
12650 @section OpenOCD Tcl Usage
12652 @subsection source and find commands
12653 @b{Where:} In many configuration files
12654 @* Example: @b{ source [find FILENAME] }
12655 @*Remember the parsing rules
12657 @item The @command{find} command is in square brackets,
12658 and is executed with the parameter FILENAME. It should find and return
12659 the full path to a file with that name; it uses an internal search path.
12660 The RESULT is a string, which is substituted into the command line in
12661 place of the bracketed @command{find} command.
12662 (Don't try to use a FILENAME which includes the "#" character.
12663 That character begins Tcl comments.)
12664 @item The @command{source} command is executed with the resulting filename;
12665 it reads a file and executes as a script.
12667 @subsection format command
12668 @b{Where:} Generally occurs in numerous places.
12669 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
12675 puts [format "The answer: %d" [expr @{$x * $y@}]]
12678 @item The SET command creates 2 variables, X and Y.
12679 @item The double [nested] EXPR command performs math
12680 @* The EXPR command produces numerical result as a string.
12681 @* Refer to Rule #1
12682 @item The format command is executed, producing a single string
12683 @* Refer to Rule #1.
12684 @item The PUTS command outputs the text.
12686 @subsection Body or Inlined Text
12687 @b{Where:} Various TARGET scripts.
12690 proc someproc @{@} @{
12691 ... multiple lines of stuff ...
12693 $_TARGETNAME configure -event FOO someproc
12694 #2 Good - no variables
12695 $_TARGETNAME configure -event foo "this ; that;"
12696 #3 Good Curly Braces
12697 $_TARGETNAME configure -event FOO @{
12698 puts "Time: [date]"
12700 #4 DANGER DANGER DANGER
12701 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
12704 @item The $_TARGETNAME is an OpenOCD variable convention.
12705 @*@b{$_TARGETNAME} represents the last target created, the value changes
12706 each time a new target is created. Remember the parsing rules. When
12707 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
12708 the name of the target which happens to be a TARGET (object)
12710 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
12711 @*There are 4 examples:
12713 @item The TCLBODY is a simple string that happens to be a proc name
12714 @item The TCLBODY is several simple commands separated by semicolons
12715 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
12716 @item The TCLBODY is a string with variables that get expanded.
12719 In the end, when the target event FOO occurs the TCLBODY is
12720 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
12721 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
12723 Remember the parsing rules. In case #3, @{curly-braces@} mean the
12724 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
12725 and the text is evaluated. In case #4, they are replaced before the
12726 ``Target Object Command'' is executed. This occurs at the same time
12727 $_TARGETNAME is replaced. In case #4 the date will never
12728 change. @{BTW: [date] is a bad example; at this writing,
12729 Jim/OpenOCD does not have a date command@}
12731 @subsection Global Variables
12732 @b{Where:} You might discover this when writing your own procs @* In
12733 simple terms: Inside a PROC, if you need to access a global variable
12734 you must say so. See also ``upvar''. Example:
12736 proc myproc @{ @} @{
12737 set y 0 #Local variable Y
12738 global x #Global variable X
12739 puts [format "X=%d, Y=%d" $x $y]
12742 @section Other Tcl Hacks
12743 @b{Dynamic variable creation}
12745 # Dynamically create a bunch of variables.
12746 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr @{$x + 1@}]@} @{
12748 set vn [format "BIT%d" $x]
12752 set $vn [expr @{1 << $x@}]
12755 @b{Dynamic proc/command creation}
12757 # One "X" function - 5 uart functions.
12758 foreach who @{A B C D E@}
12759 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
12764 @appendix The GNU Free Documentation License.
12767 @node OpenOCD Concept Index
12768 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
12769 @comment case issue with ``Index.html'' and ``index.html''
12770 @comment Occurs when creating ``--html --no-split'' output
12771 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
12772 @unnumbered OpenOCD Concept Index
12776 @node Command and Driver Index
12777 @unnumbered Command and Driver Index