1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.org/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.org/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
208 @chapter OpenOCD Developer Resources
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD Git Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
224 @uref{git://git.code.sf.net/p/openocd/code}
228 @uref{http://git.code.sf.net/p/openocd/code}
230 You may prefer to use a mirror and the HTTP protocol:
232 @uref{http://repo.or.cz/r/openocd.git}
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
240 @uref{http://repo.or.cz/w/openocd.git}
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
250 @section Doxygen Developer Manual
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
263 @section Gerrit Review System
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 @uref{https://review.openocd.org/}
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
282 @section OpenOCD Developer Mailing List
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289 @section OpenOCD Bug Tracker
291 The OpenOCD Bug Tracker is hosted on SourceForge:
293 @uref{http://bugs.openocd.org/}
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
312 @section Choosing a Dongle
314 There are several things you should keep in mind when choosing a dongle.
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
331 @section USB FT2232 Based
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
406 @section USB-JTAG / Altera USB-Blaster compatibles
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
522 @section IBM PC Parallel Printer Port Based
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
588 @* A JTAG driver acting as a client for the JTAG VPI server interface.
589 @* Link: @url{http://github.com/fjullien/jtag_vpi}
592 @* A driver for Cadence virtual Debug Interface to emulated or simulated targets.
593 It implements a client connecting to the vdebug server, which in turn communicates
594 with the emulated or simulated RTL model through a transactor. The current version
595 supports only JTAG as a transport, but other virtual transports, like DAP are planned.
598 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
599 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
600 interface of a hardware model written in SystemVerilog, for example, on an
601 emulation model of target hardware.
603 @item @b{xlnx_pcie_xvc}
604 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
607 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
610 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
611 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
616 @chapter About Jim-Tcl
620 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
621 This programming language provides a simple and extensible
624 All commands presented in this Guide are extensions to Jim-Tcl.
625 You can use them as simple commands, without needing to learn
626 much of anything about Tcl.
627 Alternatively, you can write Tcl programs with them.
629 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
630 There is an active and responsive community, get on the mailing list
631 if you have any questions. Jim-Tcl maintainers also lurk on the
632 OpenOCD mailing list.
635 @item @b{Jim vs. Tcl}
636 @* Jim-Tcl is a stripped down version of the well known Tcl language,
637 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
638 fewer features. Jim-Tcl is several dozens of .C files and .H files and
639 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
640 4.2 MB .zip file containing 1540 files.
642 @item @b{Missing Features}
643 @* Our practice has been: Add/clone the real Tcl feature if/when
644 needed. We welcome Jim-Tcl improvements, not bloat. Also there
645 are a large number of optional Jim-Tcl features that are not
649 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
650 command interpreter today is a mixture of (newer)
651 Jim-Tcl commands, and the (older) original command interpreter.
654 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
655 can type a Tcl for() loop, set variables, etc.
656 Some of the commands documented in this guide are implemented
657 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
659 @item @b{Historical Note}
660 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
661 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
662 as a Git submodule, which greatly simplified upgrading Jim-Tcl
663 to benefit from new features and bugfixes in Jim-Tcl.
665 @item @b{Need a crash course in Tcl?}
666 @*@xref{Tcl Crash Course}.
671 @cindex command line options
673 @cindex directory search
675 Properly installing OpenOCD sets up your operating system to grant it access
676 to the debug adapters. On Linux, this usually involves installing a file
677 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
678 that works for many common adapters is shipped with OpenOCD in the
679 @file{contrib} directory. MS-Windows needs
680 complex and confusing driver configuration for every peripheral. Such issues
681 are unique to each operating system, and are not detailed in this User's Guide.
683 Then later you will invoke the OpenOCD server, with various options to
684 tell it how each debug session should work.
685 The @option{--help} option shows:
689 --help | -h display this help
690 --version | -v display OpenOCD version
691 --file | -f use configuration file <name>
692 --search | -s dir to search for config files and scripts
693 --debug | -d set debug level to 3
694 | -d<n> set debug level to <level>
695 --log_output | -l redirect log output to file <name>
696 --command | -c run <command>
699 If you don't give any @option{-f} or @option{-c} options,
700 OpenOCD tries to read the configuration file @file{openocd.cfg}.
701 To specify one or more different
702 configuration files, use @option{-f} options. For example:
705 openocd -f config1.cfg -f config2.cfg -f config3.cfg
708 Configuration files and scripts are searched for in
710 @item the current directory,
711 @item any search dir specified on the command line using the @option{-s} option,
712 @item any search dir specified using the @command{add_script_search_dir} command,
713 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
714 @item @file{%APPDATA%/OpenOCD} (only on Windows),
715 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
716 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
717 @item @file{$HOME/.openocd},
718 @item the site wide script library @file{$pkgdatadir/site} and
719 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
721 The first found file with a matching file name will be used.
724 Don't try to use configuration script names or paths which
725 include the "#" character. That character begins Tcl comments.
728 @section Simple setup, no customization
730 In the best case, you can use two scripts from one of the script
731 libraries, hook up your JTAG adapter, and start the server ... and
732 your JTAG setup will just work "out of the box". Always try to
733 start by reusing those scripts, but assume you'll need more
734 customization even if this works. @xref{OpenOCD Project Setup}.
736 If you find a script for your JTAG adapter, and for your board or
737 target, you may be able to hook up your JTAG adapter then start
738 the server with some variation of one of the following:
741 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
742 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
745 You might also need to configure which reset signals are present,
746 using @option{-c 'reset_config trst_and_srst'} or something similar.
747 If all goes well you'll see output something like
750 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
751 For bug reports, read
752 http://openocd.org/doc/doxygen/bugs.html
753 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
754 (mfg: 0x23b, part: 0xba00, ver: 0x3)
757 Seeing that "tap/device found" message, and no warnings, means
758 the JTAG communication is working. That's a key milestone, but
759 you'll probably need more project-specific setup.
761 @section What OpenOCD does as it starts
763 OpenOCD starts by processing the configuration commands provided
764 on the command line or, if there were no @option{-c command} or
765 @option{-f file.cfg} options given, in @file{openocd.cfg}.
766 @xref{configurationstage,,Configuration Stage}.
767 At the end of the configuration stage it verifies the JTAG scan
768 chain defined using those commands; your configuration should
769 ensure that this always succeeds.
770 Normally, OpenOCD then starts running as a server.
771 Alternatively, commands may be used to terminate the configuration
772 stage early, perform work (such as updating some flash memory),
773 and then shut down without acting as a server.
775 Once OpenOCD starts running as a server, it waits for connections from
776 clients (Telnet, GDB, RPC) and processes the commands issued through
779 If you are having problems, you can enable internal debug messages via
780 the @option{-d} option.
782 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
783 @option{-c} command line switch.
785 To enable debug output (when reporting problems or working on OpenOCD
786 itself), use the @option{-d} command line switch. This sets the
787 @option{debug_level} to "3", outputting the most information,
788 including debug messages. The default setting is "2", outputting only
789 informational messages, warnings and errors. You can also change this
790 setting from within a telnet or gdb session using @command{debug_level<n>}
791 (@pxref{debuglevel,,debug_level}).
793 You can redirect all output from the server to a file using the
794 @option{-l <logfile>} switch.
796 Note! OpenOCD will launch the GDB & telnet server even if it can not
797 establish a connection with the target. In general, it is possible for
798 the JTAG controller to be unresponsive until the target is set up
799 correctly via e.g. GDB monitor commands in a GDB init script.
801 @node OpenOCD Project Setup
802 @chapter OpenOCD Project Setup
804 To use OpenOCD with your development projects, you need to do more than
805 just connect the JTAG adapter hardware (dongle) to your development board
806 and start the OpenOCD server.
807 You also need to configure your OpenOCD server so that it knows
808 about your adapter and board, and helps your work.
809 You may also want to connect OpenOCD to GDB, possibly
810 using Eclipse or some other GUI.
812 @section Hooking up the JTAG Adapter
814 Today's most common case is a dongle with a JTAG cable on one side
815 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
816 and a USB cable on the other.
817 Instead of USB, some dongles use Ethernet;
818 older ones may use a PC parallel port, or even a serial port.
821 @item @emph{Start with power to your target board turned off},
822 and nothing connected to your JTAG adapter.
823 If you're particularly paranoid, unplug power to the board.
824 It's important to have the ground signal properly set up,
825 unless you are using a JTAG adapter which provides
826 galvanic isolation between the target board and the
829 @item @emph{Be sure it's the right kind of JTAG connector.}
830 If your dongle has a 20-pin ARM connector, you need some kind
831 of adapter (or octopus, see below) to hook it up to
832 boards using 14-pin or 10-pin connectors ... or to 20-pin
833 connectors which don't use ARM's pinout.
835 In the same vein, make sure the voltage levels are compatible.
836 Not all JTAG adapters have the level shifters needed to work
837 with 1.2 Volt boards.
839 @item @emph{Be certain the cable is properly oriented} or you might
840 damage your board. In most cases there are only two possible
841 ways to connect the cable.
842 Connect the JTAG cable from your adapter to the board.
843 Be sure it's firmly connected.
845 In the best case, the connector is keyed to physically
846 prevent you from inserting it wrong.
847 This is most often done using a slot on the board's male connector
848 housing, which must match a key on the JTAG cable's female connector.
849 If there's no housing, then you must look carefully and
850 make sure pin 1 on the cable hooks up to pin 1 on the board.
851 Ribbon cables are frequently all grey except for a wire on one
852 edge, which is red. The red wire is pin 1.
854 Sometimes dongles provide cables where one end is an ``octopus'' of
855 color coded single-wire connectors, instead of a connector block.
856 These are great when converting from one JTAG pinout to another,
857 but are tedious to set up.
858 Use these with connector pinout diagrams to help you match up the
859 adapter signals to the right board pins.
861 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
862 A USB, parallel, or serial port connector will go to the host which
863 you are using to run OpenOCD.
864 For Ethernet, consult the documentation and your network administrator.
866 For USB-based JTAG adapters you have an easy sanity check at this point:
867 does the host operating system see the JTAG adapter? If you're running
868 Linux, try the @command{lsusb} command. If that host is an
869 MS-Windows host, you'll need to install a driver before OpenOCD works.
871 @item @emph{Connect the adapter's power supply, if needed.}
872 This step is primarily for non-USB adapters,
873 but sometimes USB adapters need extra power.
875 @item @emph{Power up the target board.}
876 Unless you just let the magic smoke escape,
877 you're now ready to set up the OpenOCD server
878 so you can use JTAG to work with that board.
882 Talk with the OpenOCD server using
883 telnet (@code{telnet localhost 4444} on many systems) or GDB.
884 @xref{GDB and OpenOCD}.
886 @section Project Directory
888 There are many ways you can configure OpenOCD and start it up.
890 A simple way to organize them all involves keeping a
891 single directory for your work with a given board.
892 When you start OpenOCD from that directory,
893 it searches there first for configuration files, scripts,
894 files accessed through semihosting,
895 and for code you upload to the target board.
896 It is also the natural place to write files,
897 such as log files and data you download from the board.
899 @section Configuration Basics
901 There are two basic ways of configuring OpenOCD, and
902 a variety of ways you can mix them.
903 Think of the difference as just being how you start the server:
906 @item Many @option{-f file} or @option{-c command} options on the command line
907 @item No options, but a @dfn{user config file}
908 in the current directory named @file{openocd.cfg}
911 Here is an example @file{openocd.cfg} file for a setup
912 using a Signalyzer FT2232-based JTAG adapter to talk to
913 a board with an Atmel AT91SAM7X256 microcontroller:
916 source [find interface/ftdi/signalyzer.cfg]
918 # GDB can also flash my flash!
919 gdb_memory_map enable
920 gdb_flash_program enable
922 source [find target/sam7x256.cfg]
925 Here is the command line equivalent of that configuration:
928 openocd -f interface/ftdi/signalyzer.cfg \
929 -c "gdb_memory_map enable" \
930 -c "gdb_flash_program enable" \
931 -f target/sam7x256.cfg
934 You could wrap such long command lines in shell scripts,
935 each supporting a different development task.
936 One might re-flash the board with a specific firmware version.
937 Another might set up a particular debugging or run-time environment.
940 At this writing (October 2009) the command line method has
941 problems with how it treats variables.
942 For example, after @option{-c "set VAR value"}, or doing the
943 same in a script, the variable @var{VAR} will have no value
944 that can be tested in a later script.
947 Here we will focus on the simpler solution: one user config
948 file, including basic configuration plus any TCL procedures
949 to simplify your work.
951 @section User Config Files
952 @cindex config file, user
953 @cindex user config file
954 @cindex config file, overview
956 A user configuration file ties together all the parts of a project
958 One of the following will match your situation best:
961 @item Ideally almost everything comes from configuration files
962 provided by someone else.
963 For example, OpenOCD distributes a @file{scripts} directory
964 (probably in @file{/usr/share/openocd/scripts} on Linux).
965 Board and tool vendors can provide these too, as can individual
966 user sites; the @option{-s} command line option lets you say
967 where to find these files. (@xref{Running}.)
968 The AT91SAM7X256 example above works this way.
970 Three main types of non-user configuration file each have their
971 own subdirectory in the @file{scripts} directory:
974 @item @b{interface} -- one for each different debug adapter;
975 @item @b{board} -- one for each different board
976 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
979 Best case: include just two files, and they handle everything else.
980 The first is an interface config file.
981 The second is board-specific, and it sets up the JTAG TAPs and
982 their GDB targets (by deferring to some @file{target.cfg} file),
983 declares all flash memory, and leaves you nothing to do except
987 source [find interface/olimex-jtag-tiny.cfg]
988 source [find board/csb337.cfg]
991 Boards with a single microcontroller often won't need more
992 than the target config file, as in the AT91SAM7X256 example.
993 That's because there is no external memory (flash, DDR RAM), and
994 the board differences are encapsulated by application code.
996 @item Maybe you don't know yet what your board looks like to JTAG.
997 Once you know the @file{interface.cfg} file to use, you may
998 need help from OpenOCD to discover what's on the board.
999 Once you find the JTAG TAPs, you can just search for appropriate
1001 configuration files ... or write your own, from the bottom up.
1002 @xref{autoprobing,,Autoprobing}.
1004 @item You can often reuse some standard config files but
1005 need to write a few new ones, probably a @file{board.cfg} file.
1006 You will be using commands described later in this User's Guide,
1007 and working with the guidelines in the next chapter.
1009 For example, there may be configuration files for your JTAG adapter
1010 and target chip, but you need a new board-specific config file
1011 giving access to your particular flash chips.
1012 Or you might need to write another target chip configuration file
1013 for a new chip built around the Cortex-M3 core.
1016 When you write new configuration files, please submit
1017 them for inclusion in the next OpenOCD release.
1018 For example, a @file{board/newboard.cfg} file will help the
1019 next users of that board, and a @file{target/newcpu.cfg}
1020 will help support users of any board using that chip.
1024 You may need to write some C code.
1025 It may be as simple as supporting a new FT2232 or parport
1026 based adapter; a bit more involved, like a NAND or NOR flash
1027 controller driver; or a big piece of work like supporting
1028 a new chip architecture.
1031 Reuse the existing config files when you can.
1032 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1033 You may find a board configuration that's a good example to follow.
1035 When you write config files, separate the reusable parts
1036 (things every user of that interface, chip, or board needs)
1037 from ones specific to your environment and debugging approach.
1041 For example, a @code{gdb-attach} event handler that invokes
1042 the @command{reset init} command will interfere with debugging
1043 early boot code, which performs some of the same actions
1044 that the @code{reset-init} event handler does.
1047 Likewise, the @command{arm9 vector_catch} command (or
1048 @cindex vector_catch
1049 its siblings @command{xscale vector_catch}
1050 and @command{cortex_m vector_catch}) can be a time-saver
1051 during some debug sessions, but don't make everyone use that either.
1052 Keep those kinds of debugging aids in your user config file,
1053 along with messaging and tracing setup.
1054 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1057 You might need to override some defaults.
1058 For example, you might need to move, shrink, or back up the target's
1059 work area if your application needs much SRAM.
1062 TCP/IP port configuration is another example of something which
1063 is environment-specific, and should only appear in
1064 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1067 @section Project-Specific Utilities
1069 A few project-specific utility
1070 routines may well speed up your work.
1071 Write them, and keep them in your project's user config file.
1073 For example, if you are making a boot loader work on a
1074 board, it's nice to be able to debug the ``after it's
1075 loaded to RAM'' parts separately from the finicky early
1076 code which sets up the DDR RAM controller and clocks.
1077 A script like this one, or a more GDB-aware sibling,
1081 proc ramboot @{ @} @{
1082 # Reset, running the target's "reset-init" scripts
1083 # to initialize clocks and the DDR RAM controller.
1084 # Leave the CPU halted.
1087 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1088 load_image u-boot.bin 0x20000000
1095 Then once that code is working you will need to make it
1096 boot from NOR flash; a different utility would help.
1097 Alternatively, some developers write to flash using GDB.
1098 (You might use a similar script if you're working with a flash
1099 based microcontroller application instead of a boot loader.)
1102 proc newboot @{ @} @{
1103 # Reset, leaving the CPU halted. The "reset-init" event
1104 # proc gives faster access to the CPU and to NOR flash;
1105 # "reset halt" would be slower.
1108 # Write standard version of U-Boot into the first two
1109 # sectors of NOR flash ... the standard version should
1110 # do the same lowlevel init as "reset-init".
1111 flash protect 0 0 1 off
1112 flash erase_sector 0 0 1
1113 flash write_bank 0 u-boot.bin 0x0
1114 flash protect 0 0 1 on
1116 # Reboot from scratch using that new boot loader.
1121 You may need more complicated utility procedures when booting
1123 That often involves an extra bootloader stage,
1124 running from on-chip SRAM to perform DDR RAM setup so it can load
1125 the main bootloader code (which won't fit into that SRAM).
1127 Other helper scripts might be used to write production system images,
1128 involving considerably more than just a three stage bootloader.
1130 @section Target Software Changes
1132 Sometimes you may want to make some small changes to the software
1133 you're developing, to help make JTAG debugging work better.
1134 For example, in C or assembly language code you might
1135 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1136 handling issues like:
1140 @item @b{Watchdog Timers}...
1141 Watchdog timers are typically used to automatically reset systems if
1142 some application task doesn't periodically reset the timer. (The
1143 assumption is that the system has locked up if the task can't run.)
1144 When a JTAG debugger halts the system, that task won't be able to run
1145 and reset the timer ... potentially causing resets in the middle of
1146 your debug sessions.
1148 It's rarely a good idea to disable such watchdogs, since their usage
1149 needs to be debugged just like all other parts of your firmware.
1150 That might however be your only option.
1152 Look instead for chip-specific ways to stop the watchdog from counting
1153 while the system is in a debug halt state. It may be simplest to set
1154 that non-counting mode in your debugger startup scripts. You may however
1155 need a different approach when, for example, a motor could be physically
1156 damaged by firmware remaining inactive in a debug halt state. That might
1157 involve a type of firmware mode where that "non-counting" mode is disabled
1158 at the beginning then re-enabled at the end; a watchdog reset might fire
1159 and complicate the debug session, but hardware (or people) would be
1160 protected.@footnote{Note that many systems support a "monitor mode" debug
1161 that is a somewhat cleaner way to address such issues. You can think of
1162 it as only halting part of the system, maybe just one task,
1163 instead of the whole thing.
1164 At this writing, January 2010, OpenOCD based debugging does not support
1165 monitor mode debug, only "halt mode" debug.}
1167 @item @b{ARM Semihosting}...
1168 @cindex ARM semihosting
1169 When linked with a special runtime library provided with many
1170 toolchains@footnote{See chapter 8 "Semihosting" in
1171 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1172 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1173 The CodeSourcery EABI toolchain also includes a semihosting library.},
1174 your target code can use I/O facilities on the debug host. That library
1175 provides a small set of system calls which are handled by OpenOCD.
1176 It can let the debugger provide your system console and a file system,
1177 helping with early debugging or providing a more capable environment
1178 for sometimes-complex tasks like installing system firmware onto
1181 @item @b{ARM Wait-For-Interrupt}...
1182 Many ARM chips synchronize the JTAG clock using the core clock.
1183 Low power states which stop that core clock thus prevent JTAG access.
1184 Idle loops in tasking environments often enter those low power states
1185 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1187 You may want to @emph{disable that instruction} in source code,
1188 or otherwise prevent using that state,
1189 to ensure you can get JTAG access at any time.@footnote{As a more
1190 polite alternative, some processors have special debug-oriented
1191 registers which can be used to change various features including
1192 how the low power states are clocked while debugging.
1193 The STM32 DBGMCU_CR register is an example; at the cost of extra
1194 power consumption, JTAG can be used during low power states.}
1195 For example, the OpenOCD @command{halt} command may not
1196 work for an idle processor otherwise.
1198 @item @b{Delay after reset}...
1199 Not all chips have good support for debugger access
1200 right after reset; many LPC2xxx chips have issues here.
1201 Similarly, applications that reconfigure pins used for
1202 JTAG access as they start will also block debugger access.
1204 To work with boards like this, @emph{enable a short delay loop}
1205 the first thing after reset, before "real" startup activities.
1206 For example, one second's delay is usually more than enough
1207 time for a JTAG debugger to attach, so that
1208 early code execution can be debugged
1209 or firmware can be replaced.
1211 @item @b{Debug Communications Channel (DCC)}...
1212 Some processors include mechanisms to send messages over JTAG.
1213 Many ARM cores support these, as do some cores from other vendors.
1214 (OpenOCD may be able to use this DCC internally, speeding up some
1215 operations like writing to memory.)
1217 Your application may want to deliver various debugging messages
1218 over JTAG, by @emph{linking with a small library of code}
1219 provided with OpenOCD and using the utilities there to send
1220 various kinds of message.
1221 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1225 @section Target Hardware Setup
1227 Chip vendors often provide software development boards which
1228 are highly configurable, so that they can support all options
1229 that product boards may require. @emph{Make sure that any
1230 jumpers or switches match the system configuration you are
1233 Common issues include:
1237 @item @b{JTAG setup} ...
1238 Boards may support more than one JTAG configuration.
1239 Examples include jumpers controlling pullups versus pulldowns
1240 on the nTRST and/or nSRST signals, and choice of connectors
1241 (e.g. which of two headers on the base board,
1242 or one from a daughtercard).
1243 For some Texas Instruments boards, you may need to jumper the
1244 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1246 @item @b{Boot Modes} ...
1247 Complex chips often support multiple boot modes, controlled
1248 by external jumpers. Make sure this is set up correctly.
1249 For example many i.MX boards from NXP need to be jumpered
1250 to "ATX mode" to start booting using the on-chip ROM, when
1251 using second stage bootloader code stored in a NAND flash chip.
1253 Such explicit configuration is common, and not limited to
1254 booting from NAND. You might also need to set jumpers to
1255 start booting using code loaded from an MMC/SD card; external
1256 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1257 flash; some external host; or various other sources.
1260 @item @b{Memory Addressing} ...
1261 Boards which support multiple boot modes may also have jumpers
1262 to configure memory addressing. One board, for example, jumpers
1263 external chipselect 0 (used for booting) to address either
1264 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1265 or NAND flash. When it's jumpered to address NAND flash, that
1266 board must also be told to start booting from on-chip ROM.
1268 Your @file{board.cfg} file may also need to be told this jumper
1269 configuration, so that it can know whether to declare NOR flash
1270 using @command{flash bank} or instead declare NAND flash with
1271 @command{nand device}; and likewise which probe to perform in
1272 its @code{reset-init} handler.
1274 A closely related issue is bus width. Jumpers might need to
1275 distinguish between 8 bit or 16 bit bus access for the flash
1276 used to start booting.
1278 @item @b{Peripheral Access} ...
1279 Development boards generally provide access to every peripheral
1280 on the chip, sometimes in multiple modes (such as by providing
1281 multiple audio codec chips).
1282 This interacts with software
1283 configuration of pin multiplexing, where for example a
1284 given pin may be routed either to the MMC/SD controller
1285 or the GPIO controller. It also often interacts with
1286 configuration jumpers. One jumper may be used to route
1287 signals to an MMC/SD card slot or an expansion bus (which
1288 might in turn affect booting); others might control which
1289 audio or video codecs are used.
1293 Plus you should of course have @code{reset-init} event handlers
1294 which set up the hardware to match that jumper configuration.
1295 That includes in particular any oscillator or PLL used to clock
1296 the CPU, and any memory controllers needed to access external
1297 memory and peripherals. Without such handlers, you won't be
1298 able to access those resources without working target firmware
1299 which can do that setup ... this can be awkward when you're
1300 trying to debug that target firmware. Even if there's a ROM
1301 bootloader which handles a few issues, it rarely provides full
1302 access to all board-specific capabilities.
1305 @node Config File Guidelines
1306 @chapter Config File Guidelines
1308 This chapter is aimed at any user who needs to write a config file,
1309 including developers and integrators of OpenOCD and any user who
1310 needs to get a new board working smoothly.
1311 It provides guidelines for creating those files.
1313 You should find the following directories under
1314 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1315 them as-is where you can; or as models for new files.
1317 @item @file{interface} ...
1318 These are for debug adapters. Files that specify configuration to use
1319 specific JTAG, SWD and other adapters go here.
1320 @item @file{board} ...
1321 Think Circuit Board, PWA, PCB, they go by many names. Board files
1322 contain initialization items that are specific to a board.
1324 They reuse target configuration files, since the same
1325 microprocessor chips are used on many boards,
1326 but support for external parts varies widely. For
1327 example, the SDRAM initialization sequence for the board, or the type
1328 of external flash and what address it uses. Any initialization
1329 sequence to enable that external flash or SDRAM should be found in the
1330 board file. Boards may also contain multiple targets: two CPUs; or
1332 @item @file{target} ...
1333 Think chip. The ``target'' directory represents the JTAG TAPs
1335 which OpenOCD should control, not a board. Two common types of targets
1336 are ARM chips and FPGA or CPLD chips.
1337 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1338 the target config file defines all of them.
1339 @item @emph{more} ... browse for other library files which may be useful.
1340 For example, there are various generic and CPU-specific utilities.
1343 The @file{openocd.cfg} user config
1344 file may override features in any of the above files by
1345 setting variables before sourcing the target file, or by adding
1346 commands specific to their situation.
1348 @section Interface Config Files
1350 The user config file
1351 should be able to source one of these files with a command like this:
1354 source [find interface/FOOBAR.cfg]
1357 A preconfigured interface file should exist for every debug adapter
1358 in use today with OpenOCD.
1359 That said, perhaps some of these config files
1360 have only been used by the developer who created it.
1362 A separate chapter gives information about how to set these up.
1363 @xref{Debug Adapter Configuration}.
1364 Read the OpenOCD source code (and Developer's Guide)
1365 if you have a new kind of hardware interface
1366 and need to provide a driver for it.
1368 @deffn {Command} {find} 'filename'
1369 Prints full path to @var{filename} according to OpenOCD search rules.
1372 @deffn {Command} {ocd_find} 'filename'
1373 Prints full path to @var{filename} according to OpenOCD search rules. This
1374 is a low level function used by the @command{find}. Usually you want
1375 to use @command{find}, instead.
1378 @section Board Config Files
1379 @cindex config file, board
1380 @cindex board config file
1382 The user config file
1383 should be able to source one of these files with a command like this:
1386 source [find board/FOOBAR.cfg]
1389 The point of a board config file is to package everything
1390 about a given board that user config files need to know.
1391 In summary the board files should contain (if present)
1394 @item One or more @command{source [find target/...cfg]} statements
1395 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1396 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1397 @item Target @code{reset} handlers for SDRAM and I/O configuration
1398 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1399 @item All things that are not ``inside a chip''
1402 Generic things inside target chips belong in target config files,
1403 not board config files. So for example a @code{reset-init} event
1404 handler should know board-specific oscillator and PLL parameters,
1405 which it passes to target-specific utility code.
1407 The most complex task of a board config file is creating such a
1408 @code{reset-init} event handler.
1409 Define those handlers last, after you verify the rest of the board
1410 configuration works.
1412 @subsection Communication Between Config files
1414 In addition to target-specific utility code, another way that
1415 board and target config files communicate is by following a
1416 convention on how to use certain variables.
1418 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1419 Thus the rule we follow in OpenOCD is this: Variables that begin with
1420 a leading underscore are temporary in nature, and can be modified and
1421 used at will within a target configuration file.
1423 Complex board config files can do the things like this,
1424 for a board with three chips:
1427 # Chip #1: PXA270 for network side, big endian
1428 set CHIPNAME network
1430 source [find target/pxa270.cfg]
1431 # on return: _TARGETNAME = network.cpu
1432 # other commands can refer to the "network.cpu" target.
1433 $_TARGETNAME configure .... events for this CPU..
1435 # Chip #2: PXA270 for video side, little endian
1438 source [find target/pxa270.cfg]
1439 # on return: _TARGETNAME = video.cpu
1440 # other commands can refer to the "video.cpu" target.
1441 $_TARGETNAME configure .... events for this CPU..
1443 # Chip #3: Xilinx FPGA for glue logic
1446 source [find target/spartan3.cfg]
1449 That example is oversimplified because it doesn't show any flash memory,
1450 or the @code{reset-init} event handlers to initialize external DRAM
1451 or (assuming it needs it) load a configuration into the FPGA.
1452 Such features are usually needed for low-level work with many boards,
1453 where ``low level'' implies that the board initialization software may
1454 not be working. (That's a common reason to need JTAG tools. Another
1455 is to enable working with microcontroller-based systems, which often
1456 have no debugging support except a JTAG connector.)
1458 Target config files may also export utility functions to board and user
1459 config files. Such functions should use name prefixes, to help avoid
1462 Board files could also accept input variables from user config files.
1463 For example, there might be a @code{J4_JUMPER} setting used to identify
1464 what kind of flash memory a development board is using, or how to set
1465 up other clocks and peripherals.
1467 @subsection Variable Naming Convention
1468 @cindex variable names
1470 Most boards have only one instance of a chip.
1471 However, it should be easy to create a board with more than
1472 one such chip (as shown above).
1473 Accordingly, we encourage these conventions for naming
1474 variables associated with different @file{target.cfg} files,
1475 to promote consistency and
1476 so that board files can override target defaults.
1478 Inputs to target config files include:
1481 @item @code{CHIPNAME} ...
1482 This gives a name to the overall chip, and is used as part of
1483 tap identifier dotted names.
1484 While the default is normally provided by the chip manufacturer,
1485 board files may need to distinguish between instances of a chip.
1486 @item @code{ENDIAN} ...
1487 By default @option{little} - although chips may hard-wire @option{big}.
1488 Chips that can't change endianness don't need to use this variable.
1489 @item @code{CPUTAPID} ...
1490 When OpenOCD examines the JTAG chain, it can be told verify the
1491 chips against the JTAG IDCODE register.
1492 The target file will hold one or more defaults, but sometimes the
1493 chip in a board will use a different ID (perhaps a newer revision).
1496 Outputs from target config files include:
1499 @item @code{_TARGETNAME} ...
1500 By convention, this variable is created by the target configuration
1501 script. The board configuration file may make use of this variable to
1502 configure things like a ``reset init'' script, or other things
1503 specific to that board and that target.
1504 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1505 @code{_TARGETNAME1}, ... etc.
1508 @subsection The reset-init Event Handler
1509 @cindex event, reset-init
1510 @cindex reset-init handler
1512 Board config files run in the OpenOCD configuration stage;
1513 they can't use TAPs or targets, since they haven't been
1515 This means you can't write memory or access chip registers;
1516 you can't even verify that a flash chip is present.
1517 That's done later in event handlers, of which the target @code{reset-init}
1518 handler is one of the most important.
1520 Except on microcontrollers, the basic job of @code{reset-init} event
1521 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1522 Microcontrollers rarely use boot loaders; they run right out of their
1523 on-chip flash and SRAM memory. But they may want to use one of these
1524 handlers too, if just for developer convenience.
1527 Because this is so very board-specific, and chip-specific, no examples
1529 Instead, look at the board config files distributed with OpenOCD.
1530 If you have a boot loader, its source code will help; so will
1531 configuration files for other JTAG tools
1532 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1535 Some of this code could probably be shared between different boards.
1536 For example, setting up a DRAM controller often doesn't differ by
1537 much except the bus width (16 bits or 32?) and memory timings, so a
1538 reusable TCL procedure loaded by the @file{target.cfg} file might take
1539 those as parameters.
1540 Similarly with oscillator, PLL, and clock setup;
1541 and disabling the watchdog.
1542 Structure the code cleanly, and provide comments to help
1543 the next developer doing such work.
1544 (@emph{You might be that next person} trying to reuse init code!)
1546 The last thing normally done in a @code{reset-init} handler is probing
1547 whatever flash memory was configured. For most chips that needs to be
1548 done while the associated target is halted, either because JTAG memory
1549 access uses the CPU or to prevent conflicting CPU access.
1551 @subsection JTAG Clock Rate
1553 Before your @code{reset-init} handler has set up
1554 the PLLs and clocking, you may need to run with
1555 a low JTAG clock rate.
1556 @xref{jtagspeed,,JTAG Speed}.
1557 Then you'd increase that rate after your handler has
1558 made it possible to use the faster JTAG clock.
1559 When the initial low speed is board-specific, for example
1560 because it depends on a board-specific oscillator speed, then
1561 you should probably set it up in the board config file;
1562 if it's target-specific, it belongs in the target config file.
1564 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1565 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1566 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1567 Consult chip documentation to determine the peak JTAG clock rate,
1568 which might be less than that.
1571 On most ARMs, JTAG clock detection is coupled to the core clock, so
1572 software using a @option{wait for interrupt} operation blocks JTAG access.
1573 Adaptive clocking provides a partial workaround, but a more complete
1574 solution just avoids using that instruction with JTAG debuggers.
1577 If both the chip and the board support adaptive clocking,
1578 use the @command{jtag_rclk}
1579 command, in case your board is used with JTAG adapter which
1580 also supports it. Otherwise use @command{adapter speed}.
1581 Set the slow rate at the beginning of the reset sequence,
1582 and the faster rate as soon as the clocks are at full speed.
1584 @anchor{theinitboardprocedure}
1585 @subsection The init_board procedure
1586 @cindex init_board procedure
1588 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1589 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1590 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1591 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1592 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1593 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1594 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1595 Additionally ``linear'' board config file will most likely fail when target config file uses
1596 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1597 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1598 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1599 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1601 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1602 the original), allowing greater code reuse.
1605 ### board_file.cfg ###
1607 # source target file that does most of the config in init_targets
1608 source [find target/target.cfg]
1610 proc enable_fast_clock @{@} @{
1611 # enables fast on-board clock source
1612 # configures the chip to use it
1615 # initialize only board specifics - reset, clock, adapter frequency
1616 proc init_board @{@} @{
1617 reset_config trst_and_srst trst_pulls_srst
1619 $_TARGETNAME configure -event reset-start @{
1623 $_TARGETNAME configure -event reset-init @{
1630 @section Target Config Files
1631 @cindex config file, target
1632 @cindex target config file
1634 Board config files communicate with target config files using
1635 naming conventions as described above, and may source one or
1636 more target config files like this:
1639 source [find target/FOOBAR.cfg]
1642 The point of a target config file is to package everything
1643 about a given chip that board config files need to know.
1644 In summary the target files should contain
1648 @item Add TAPs to the scan chain
1649 @item Add CPU targets (includes GDB support)
1650 @item CPU/Chip/CPU-Core specific features
1654 As a rule of thumb, a target file sets up only one chip.
1655 For a microcontroller, that will often include a single TAP,
1656 which is a CPU needing a GDB target, and its on-chip flash.
1658 More complex chips may include multiple TAPs, and the target
1659 config file may need to define them all before OpenOCD
1660 can talk to the chip.
1661 For example, some phone chips have JTAG scan chains that include
1662 an ARM core for operating system use, a DSP,
1663 another ARM core embedded in an image processing engine,
1664 and other processing engines.
1666 @subsection Default Value Boiler Plate Code
1668 All target configuration files should start with code like this,
1669 letting board config files express environment-specific
1670 differences in how things should be set up.
1673 # Boards may override chip names, perhaps based on role,
1674 # but the default should match what the vendor uses
1675 if @{ [info exists CHIPNAME] @} @{
1676 set _CHIPNAME $CHIPNAME
1678 set _CHIPNAME sam7x256
1681 # ONLY use ENDIAN with targets that can change it.
1682 if @{ [info exists ENDIAN] @} @{
1688 # TAP identifiers may change as chips mature, for example with
1689 # new revision fields (the "3" here). Pick a good default; you
1690 # can pass several such identifiers to the "jtag newtap" command.
1691 if @{ [info exists CPUTAPID ] @} @{
1692 set _CPUTAPID $CPUTAPID
1694 set _CPUTAPID 0x3f0f0f0f
1697 @c but 0x3f0f0f0f is for an str73x part ...
1699 @emph{Remember:} Board config files may include multiple target
1700 config files, or the same target file multiple times
1701 (changing at least @code{CHIPNAME}).
1703 Likewise, the target configuration file should define
1704 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1705 use it later on when defining debug targets:
1708 set _TARGETNAME $_CHIPNAME.cpu
1709 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1712 @subsection Adding TAPs to the Scan Chain
1713 After the ``defaults'' are set up,
1714 add the TAPs on each chip to the JTAG scan chain.
1715 @xref{TAP Declaration}, and the naming convention
1718 In the simplest case the chip has only one TAP,
1719 probably for a CPU or FPGA.
1720 The config file for the Atmel AT91SAM7X256
1721 looks (in part) like this:
1724 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1727 A board with two such at91sam7 chips would be able
1728 to source such a config file twice, with different
1729 values for @code{CHIPNAME}, so
1730 it adds a different TAP each time.
1732 If there are nonzero @option{-expected-id} values,
1733 OpenOCD attempts to verify the actual tap id against those values.
1734 It will issue error messages if there is mismatch, which
1735 can help to pinpoint problems in OpenOCD configurations.
1738 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1739 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1740 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1741 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1742 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1745 There are more complex examples too, with chips that have
1746 multiple TAPs. Ones worth looking at include:
1749 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1750 plus a JRC to enable them
1751 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1752 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1753 is not currently used)
1756 @subsection Add CPU targets
1758 After adding a TAP for a CPU, you should set it up so that
1759 GDB and other commands can use it.
1760 @xref{CPU Configuration}.
1761 For the at91sam7 example above, the command can look like this;
1762 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1763 to little endian, and this chip doesn't support changing that.
1766 set _TARGETNAME $_CHIPNAME.cpu
1767 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1770 Work areas are small RAM areas associated with CPU targets.
1771 They are used by OpenOCD to speed up downloads,
1772 and to download small snippets of code to program flash chips.
1773 If the chip includes a form of ``on-chip-ram'' - and many do - define
1774 a work area if you can.
1775 Again using the at91sam7 as an example, this can look like:
1778 $_TARGETNAME configure -work-area-phys 0x00200000 \
1779 -work-area-size 0x4000 -work-area-backup 0
1782 @anchor{definecputargetsworkinginsmp}
1783 @subsection Define CPU targets working in SMP
1785 After setting targets, you can define a list of targets working in SMP.
1788 set _TARGETNAME_1 $_CHIPNAME.cpu1
1789 set _TARGETNAME_2 $_CHIPNAME.cpu2
1790 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1791 -coreid 0 -dbgbase $_DAP_DBG1
1792 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1793 -coreid 1 -dbgbase $_DAP_DBG2
1794 #define 2 targets working in smp.
1795 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1797 In the above example on cortex_a, 2 cpus are working in SMP.
1798 In SMP only one GDB instance is created and :
1800 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1801 @item halt command triggers the halt of all targets in the list.
1802 @item resume command triggers the write context and the restart of all targets in the list.
1803 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1804 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1805 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1808 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1809 command have been implemented.
1811 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1812 @item cortex_a smp off : disable SMP mode, the current target is the one
1813 displayed in the GDB session, only this target is now controlled by GDB
1814 session. This behaviour is useful during system boot up.
1815 @item cortex_a smp : display current SMP mode.
1816 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1823 #0 : coreid 0 is displayed to GDB ,
1824 #-> -1 : next resume triggers a real resume
1825 > cortex_a smp_gdb 1
1827 #0 :coreid 0 is displayed to GDB ,
1828 #->1 : next resume displays coreid 1 to GDB
1832 #1 :coreid 1 is displayed to GDB ,
1833 #->1 : next resume displays coreid 1 to GDB
1834 > cortex_a smp_gdb -1
1836 #1 :coreid 1 is displayed to GDB,
1837 #->-1 : next resume triggers a real resume
1841 @subsection Chip Reset Setup
1843 As a rule, you should put the @command{reset_config} command
1844 into the board file. Most things you think you know about a
1845 chip can be tweaked by the board.
1847 Some chips have specific ways the TRST and SRST signals are
1848 managed. In the unusual case that these are @emph{chip specific}
1849 and can never be changed by board wiring, they could go here.
1850 For example, some chips can't support JTAG debugging without
1853 Provide a @code{reset-assert} event handler if you can.
1854 Such a handler uses JTAG operations to reset the target,
1855 letting this target config be used in systems which don't
1856 provide the optional SRST signal, or on systems where you
1857 don't want to reset all targets at once.
1858 Such a handler might write to chip registers to force a reset,
1859 use a JRC to do that (preferable -- the target may be wedged!),
1860 or force a watchdog timer to trigger.
1861 (For Cortex-M targets, this is not necessary. The target
1862 driver knows how to use trigger an NVIC reset when SRST is
1865 Some chips need special attention during reset handling if
1866 they're going to be used with JTAG.
1867 An example might be needing to send some commands right
1868 after the target's TAP has been reset, providing a
1869 @code{reset-deassert-post} event handler that writes a chip
1870 register to report that JTAG debugging is being done.
1871 Another would be reconfiguring the watchdog so that it stops
1872 counting while the core is halted in the debugger.
1874 JTAG clocking constraints often change during reset, and in
1875 some cases target config files (rather than board config files)
1876 are the right places to handle some of those issues.
1877 For example, immediately after reset most chips run using a
1878 slower clock than they will use later.
1879 That means that after reset (and potentially, as OpenOCD
1880 first starts up) they must use a slower JTAG clock rate
1881 than they will use later.
1882 @xref{jtagspeed,,JTAG Speed}.
1884 @quotation Important
1885 When you are debugging code that runs right after chip
1886 reset, getting these issues right is critical.
1887 In particular, if you see intermittent failures when
1888 OpenOCD verifies the scan chain after reset,
1889 look at how you are setting up JTAG clocking.
1892 @anchor{theinittargetsprocedure}
1893 @subsection The init_targets procedure
1894 @cindex init_targets procedure
1896 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1897 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1898 procedure called @code{init_targets}, which will be executed when entering run stage
1899 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1900 Such procedure can be overridden by ``next level'' script (which sources the original).
1901 This concept facilitates code reuse when basic target config files provide generic configuration
1902 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1903 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1904 because sourcing them executes every initialization commands they provide.
1907 ### generic_file.cfg ###
1909 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1910 # basic initialization procedure ...
1913 proc init_targets @{@} @{
1914 # initializes generic chip with 4kB of flash and 1kB of RAM
1915 setup_my_chip MY_GENERIC_CHIP 4096 1024
1918 ### specific_file.cfg ###
1920 source [find target/generic_file.cfg]
1922 proc init_targets @{@} @{
1923 # initializes specific chip with 128kB of flash and 64kB of RAM
1924 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1928 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1929 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1931 For an example of this scheme see LPC2000 target config files.
1933 The @code{init_boards} procedure is a similar concept concerning board config files
1934 (@xref{theinitboardprocedure,,The init_board procedure}.)
1936 @anchor{theinittargeteventsprocedure}
1937 @subsection The init_target_events procedure
1938 @cindex init_target_events procedure
1940 A special procedure called @code{init_target_events} is run just after
1941 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1942 procedure}.) and before @code{init_board}
1943 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1944 to set up default target events for the targets that do not have those
1945 events already assigned.
1947 @subsection ARM Core Specific Hacks
1949 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1950 special high speed download features - enable it.
1952 If present, the MMU, the MPU and the CACHE should be disabled.
1954 Some ARM cores are equipped with trace support, which permits
1955 examination of the instruction and data bus activity. Trace
1956 activity is controlled through an ``Embedded Trace Module'' (ETM)
1957 on one of the core's scan chains. The ETM emits voluminous data
1958 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1959 If you are using an external trace port,
1960 configure it in your board config file.
1961 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1962 configure it in your target config file.
1965 etm config $_TARGETNAME 16 normal full etb
1966 etb config $_TARGETNAME $_CHIPNAME.etb
1969 @subsection Internal Flash Configuration
1971 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1973 @b{Never ever} in the ``target configuration file'' define any type of
1974 flash that is external to the chip. (For example a BOOT flash on
1975 Chip Select 0.) Such flash information goes in a board file - not
1976 the TARGET (chip) file.
1980 @item at91sam7x256 - has 256K flash YES enable it.
1981 @item str912 - has flash internal YES enable it.
1982 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1983 @item pxa270 - again - CS0 flash - it goes in the board file.
1986 @anchor{translatingconfigurationfiles}
1987 @section Translating Configuration Files
1989 If you have a configuration file for another hardware debugger
1990 or toolset (Abatron, BDI2000, BDI3000, CCS,
1991 Lauterbach, SEGGER, Macraigor, etc.), translating
1992 it into OpenOCD syntax is often quite straightforward. The most tricky
1993 part of creating a configuration script is oftentimes the reset init
1994 sequence where e.g. PLLs, DRAM and the like is set up.
1996 One trick that you can use when translating is to write small
1997 Tcl procedures to translate the syntax into OpenOCD syntax. This
1998 can avoid manual translation errors and make it easier to
1999 convert other scripts later on.
2001 Example of transforming quirky arguments to a simple search and
2005 # Lauterbach syntax(?)
2007 # Data.Set c15:0x042f %long 0x40000015
2009 # OpenOCD syntax when using procedure below.
2011 # setc15 0x01 0x00050078
2013 proc setc15 @{regs value@} @{
2016 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2018 arm mcr 15 [expr @{($regs >> 12) & 0x7@}] \
2019 [expr @{($regs >> 0) & 0xf@}] [expr @{($regs >> 4) & 0xf@}] \
2020 [expr @{($regs >> 8) & 0x7@}] $value
2026 @node Server Configuration
2027 @chapter Server Configuration
2028 @cindex initialization
2029 The commands here are commonly found in the openocd.cfg file and are
2030 used to specify what TCP/IP ports are used, and how GDB should be
2033 @anchor{configurationstage}
2034 @section Configuration Stage
2035 @cindex configuration stage
2036 @cindex config command
2038 When the OpenOCD server process starts up, it enters a
2039 @emph{configuration stage} which is the only time that
2040 certain commands, @emph{configuration commands}, may be issued.
2041 Normally, configuration commands are only available
2042 inside startup scripts.
2044 In this manual, the definition of a configuration command is
2045 presented as a @emph{Config Command}, not as a @emph{Command}
2046 which may be issued interactively.
2047 The runtime @command{help} command also highlights configuration
2048 commands, and those which may be issued at any time.
2050 Those configuration commands include declaration of TAPs,
2052 the interface used for JTAG communication,
2053 and other basic setup.
2054 The server must leave the configuration stage before it
2055 may access or activate TAPs.
2056 After it leaves this stage, configuration commands may no
2059 @deffn {Command} {command mode} [command_name]
2060 Returns the command modes allowed by a command: 'any', 'config', or
2061 'exec'. If no command is specified, returns the current command
2062 mode. Returns 'unknown' if an unknown command is given. Command can be
2063 multiple tokens. (command valid any time)
2065 In this document, the modes are described as stages, 'config' and
2066 'exec' mode correspond configuration stage and run stage. 'any' means
2067 the command can be executed in either
2068 stages. @xref{configurationstage,,Configuration Stage}, and
2069 @xref{enteringtherunstage,,Entering the Run Stage}.
2072 @anchor{enteringtherunstage}
2073 @section Entering the Run Stage
2075 The first thing OpenOCD does after leaving the configuration
2076 stage is to verify that it can talk to the scan chain
2077 (list of TAPs) which has been configured.
2078 It will warn if it doesn't find TAPs it expects to find,
2079 or finds TAPs that aren't supposed to be there.
2080 You should see no errors at this point.
2081 If you see errors, resolve them by correcting the
2082 commands you used to configure the server.
2083 Common errors include using an initial JTAG speed that's too
2084 fast, and not providing the right IDCODE values for the TAPs
2087 Once OpenOCD has entered the run stage, a number of commands
2089 A number of these relate to the debug targets you may have declared.
2090 For example, the @command{mww} command will not be available until
2091 a target has been successfully instantiated.
2092 If you want to use those commands, you may need to force
2093 entry to the run stage.
2095 @deffn {Config Command} {init}
2096 This command terminates the configuration stage and
2097 enters the run stage. This helps when you need to have
2098 the startup scripts manage tasks such as resetting the target,
2099 programming flash, etc. To reset the CPU upon startup, add "init" and
2100 "reset" at the end of the config script or at the end of the OpenOCD
2101 command line using the @option{-c} command line switch.
2103 If this command does not appear in any startup/configuration file
2104 OpenOCD executes the command for you after processing all
2105 configuration files and/or command line options.
2107 @b{NOTE:} This command normally occurs near the end of your
2108 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2109 targets ready. For example: If your openocd.cfg file needs to
2110 read/write memory on your target, @command{init} must occur before
2111 the memory read/write commands. This includes @command{nand probe}.
2113 @command{init} calls the following internal OpenOCD commands to initialize
2114 corresponding subsystems:
2115 @deffn {Config Command} {target init}
2116 @deffnx {Command} {transport init}
2117 @deffnx {Command} {dap init}
2118 @deffnx {Config Command} {flash init}
2119 @deffnx {Config Command} {nand init}
2120 @deffnx {Config Command} {pld init}
2121 @deffnx {Command} {tpiu init}
2125 @deffn {Config Command} {noinit}
2126 Prevent OpenOCD from implicit @command{init} call at the end of startup.
2127 Allows issuing configuration commands over telnet or Tcl connection.
2128 When you are done with configuration use @command{init} to enter
2132 @deffn {Overridable Procedure} {jtag_init}
2133 This is invoked at server startup to verify that it can talk
2134 to the scan chain (list of TAPs) which has been configured.
2136 The default implementation first tries @command{jtag arp_init},
2137 which uses only a lightweight JTAG reset before examining the
2139 If that fails, it tries again, using a harder reset
2140 from the overridable procedure @command{init_reset}.
2142 Implementations must have verified the JTAG scan chain before
2144 This is done by calling @command{jtag arp_init}
2145 (or @command{jtag arp_init-reset}).
2149 @section TCP/IP Ports
2154 The OpenOCD server accepts remote commands in several syntaxes.
2155 Each syntax uses a different TCP/IP port, which you may specify
2156 only during configuration (before those ports are opened).
2158 For reasons including security, you may wish to prevent remote
2159 access using one or more of these ports.
2160 In such cases, just specify the relevant port number as "disabled".
2161 If you disable all access through TCP/IP, you will need to
2162 use the command line @option{-pipe} option.
2165 @deffn {Config Command} {gdb_port} [number]
2167 Normally gdb listens to a TCP/IP port, but GDB can also
2168 communicate via pipes(stdin/out or named pipes). The name
2169 "gdb_port" stuck because it covers probably more than 90% of
2170 the normal use cases.
2172 No arguments reports GDB port. "pipe" means listen to stdin
2173 output to stdout, an integer is base port number, "disabled"
2174 disables the gdb server.
2176 When using "pipe", also use log_output to redirect the log
2177 output to a file so as not to flood the stdin/out pipes.
2179 Any other string is interpreted as named pipe to listen to.
2180 Output pipe is the same name as input pipe, but with 'o' appended,
2181 e.g. /var/gdb, /var/gdbo.
2183 The GDB port for the first target will be the base port, the
2184 second target will listen on gdb_port + 1, and so on.
2185 When not specified during the configuration stage,
2186 the port @var{number} defaults to 3333.
2187 When @var{number} is not a numeric value, incrementing it to compute
2188 the next port number does not work. In this case, specify the proper
2189 @var{number} for each target by using the option @code{-gdb-port} of the
2190 commands @command{target create} or @command{$target_name configure}.
2191 @xref{gdbportoverride,,option -gdb-port}.
2193 Note: when using "gdb_port pipe", increasing the default remote timeout in
2194 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2195 cause initialization to fail with "Unknown remote qXfer reply: OK".
2198 @deffn {Config Command} {tcl_port} [number]
2199 Specify or query the port used for a simplified RPC
2200 connection that can be used by clients to issue TCL commands and get the
2201 output from the Tcl engine.
2202 Intended as a machine interface.
2203 When not specified during the configuration stage,
2204 the port @var{number} defaults to 6666.
2205 When specified as "disabled", this service is not activated.
2208 @deffn {Config Command} {telnet_port} [number]
2209 Specify or query the
2210 port on which to listen for incoming telnet connections.
2211 This port is intended for interaction with one human through TCL commands.
2212 When not specified during the configuration stage,
2213 the port @var{number} defaults to 4444.
2214 When specified as "disabled", this service is not activated.
2217 @anchor{gdbconfiguration}
2218 @section GDB Configuration
2220 @cindex GDB configuration
2221 You can reconfigure some GDB behaviors if needed.
2222 The ones listed here are static and global.
2223 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2224 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2226 @anchor{gdbbreakpointoverride}
2227 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2228 Force breakpoint type for gdb @command{break} commands.
2229 This option supports GDB GUIs which don't
2230 distinguish hard versus soft breakpoints, if the default OpenOCD and
2231 GDB behaviour is not sufficient. GDB normally uses hardware
2232 breakpoints if the memory map has been set up for flash regions.
2235 @anchor{gdbflashprogram}
2236 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2237 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2238 vFlash packet is received.
2239 The default behaviour is @option{enable}.
2242 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2243 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2244 requested. GDB will then know when to set hardware breakpoints, and program flash
2245 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2246 for flash programming to work.
2247 Default behaviour is @option{enable}.
2248 @xref{gdbflashprogram,,gdb_flash_program}.
2251 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2252 Specifies whether data aborts cause an error to be reported
2253 by GDB memory read packets.
2254 The default behaviour is @option{disable};
2255 use @option{enable} see these errors reported.
2258 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2259 Specifies whether register accesses requested by GDB register read/write
2260 packets report errors or not.
2261 The default behaviour is @option{disable};
2262 use @option{enable} see these errors reported.
2265 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2266 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2267 The default behaviour is @option{enable}.
2270 @deffn {Command} {gdb_save_tdesc}
2271 Saves the target description file to the local file system.
2273 The file name is @i{target_name}.xml.
2276 @anchor{eventpolling}
2277 @section Event Polling
2279 Hardware debuggers are parts of asynchronous systems,
2280 where significant events can happen at any time.
2281 The OpenOCD server needs to detect some of these events,
2282 so it can report them to through TCL command line
2285 Examples of such events include:
2288 @item One of the targets can stop running ... maybe it triggers
2289 a code breakpoint or data watchpoint, or halts itself.
2290 @item Messages may be sent over ``debug message'' channels ... many
2291 targets support such messages sent over JTAG,
2292 for receipt by the person debugging or tools.
2293 @item Loss of power ... some adapters can detect these events.
2294 @item Resets not issued through JTAG ... such reset sources
2295 can include button presses or other system hardware, sometimes
2296 including the target itself (perhaps through a watchdog).
2297 @item Debug instrumentation sometimes supports event triggering
2298 such as ``trace buffer full'' (so it can quickly be emptied)
2299 or other signals (to correlate with code behavior).
2302 None of those events are signaled through standard JTAG signals.
2303 However, most conventions for JTAG connectors include voltage
2304 level and system reset (SRST) signal detection.
2305 Some connectors also include instrumentation signals, which
2306 can imply events when those signals are inputs.
2308 In general, OpenOCD needs to periodically check for those events,
2309 either by looking at the status of signals on the JTAG connector
2310 or by sending synchronous ``tell me your status'' JTAG requests
2311 to the various active targets.
2312 There is a command to manage and monitor that polling,
2313 which is normally done in the background.
2315 @deffn {Command} {poll} [@option{on}|@option{off}]
2316 Poll the current target for its current state.
2317 (Also, @pxref{targetcurstate,,target curstate}.)
2318 If that target is in debug mode, architecture
2319 specific information about the current state is printed.
2320 An optional parameter
2321 allows background polling to be enabled and disabled.
2323 You could use this from the TCL command shell, or
2324 from GDB using @command{monitor poll} command.
2325 Leave background polling enabled while you're using GDB.
2328 background polling: on
2329 target state: halted
2330 target halted in ARM state due to debug-request, \
2331 current mode: Supervisor
2332 cpsr: 0x800000d3 pc: 0x11081bfc
2333 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2338 @node Debug Adapter Configuration
2339 @chapter Debug Adapter Configuration
2340 @cindex config file, interface
2341 @cindex interface config file
2343 Correctly installing OpenOCD includes making your operating system give
2344 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2345 are used to select which one is used, and to configure how it is used.
2348 Because OpenOCD started out with a focus purely on JTAG, you may find
2349 places where it wrongly presumes JTAG is the only transport protocol
2350 in use. Be aware that recent versions of OpenOCD are removing that
2351 limitation. JTAG remains more functional than most other transports.
2352 Other transports do not support boundary scan operations, or may be
2353 specific to a given chip vendor. Some might be usable only for
2354 programming flash memory, instead of also for debugging.
2357 Debug Adapters/Interfaces/Dongles are normally configured
2358 through commands in an interface configuration
2359 file which is sourced by your @file{openocd.cfg} file, or
2360 through a command line @option{-f interface/....cfg} option.
2363 source [find interface/olimex-jtag-tiny.cfg]
2367 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2368 A few cases are so simple that you only need to say what driver to use:
2372 adapter driver jlink
2375 Most adapters need a bit more configuration than that.
2378 @section Adapter Configuration
2380 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2381 using. Depending on the type of adapter, you may need to use one or
2382 more additional commands to further identify or configure the adapter.
2384 @deffn {Config Command} {adapter driver} name
2385 Use the adapter driver @var{name} to connect to the
2389 @deffn {Command} {adapter list}
2390 List the debug adapter drivers that have been built into
2391 the running copy of OpenOCD.
2393 @deffn {Config Command} {adapter transports} transport_name+
2394 Specifies the transports supported by this debug adapter.
2395 The adapter driver builds-in similar knowledge; use this only
2396 when external configuration (such as jumpering) changes what
2397 the hardware can support.
2402 @deffn {Command} {adapter name}
2403 Returns the name of the debug adapter driver being used.
2406 @anchor{adapter_usb_location}
2407 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2408 Displays or specifies the physical USB port of the adapter to use. The path
2409 roots at @var{bus} and walks down the physical ports, with each
2410 @var{port} option specifying a deeper level in the bus topology, the last
2411 @var{port} denoting where the target adapter is actually plugged.
2412 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2414 This command is only available if your libusb1 is at least version 1.0.16.
2417 @deffn {Config Command} {adapter serial} serial_string
2418 Specifies the @var{serial_string} of the adapter to use.
2419 If this command is not specified, serial strings are not checked.
2420 Only the following adapter drivers use the serial string from this command:
2421 aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
2422 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
2425 @section Interface Drivers
2427 Each of the interface drivers listed here must be explicitly
2428 enabled when OpenOCD is configured, in order to be made
2429 available at run time.
2431 @deffn {Interface Driver} {amt_jtagaccel}
2432 Amontec Chameleon in its JTAG Accelerator configuration,
2433 connected to a PC's EPP mode parallel port.
2434 This defines some driver-specific commands:
2436 @deffn {Config Command} {parport port} number
2437 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2438 the number of the @file{/dev/parport} device.
2441 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2442 Displays status of RTCK option.
2443 Optionally sets that option first.
2447 @deffn {Interface Driver} {arm-jtag-ew}
2448 Olimex ARM-JTAG-EW USB adapter
2449 This has one driver-specific command:
2451 @deffn {Command} {armjtagew_info}
2456 @deffn {Interface Driver} {at91rm9200}
2457 Supports bitbanged JTAG from the local system,
2458 presuming that system is an Atmel AT91rm9200
2459 and a specific set of GPIOs is used.
2460 @c command: at91rm9200_device NAME
2461 @c chooses among list of bit configs ... only one option
2464 @deffn {Interface Driver} {cmsis-dap}
2465 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2468 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2469 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2470 the driver will attempt to auto detect the CMSIS-DAP device.
2471 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2473 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2477 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2478 Specifies how to communicate with the adapter:
2481 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2482 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2483 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2484 This is the default if @command{cmsis_dap_backend} is not specified.
2488 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2489 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2490 In most cases need not to be specified and interfaces are searched by
2491 interface string or for user class interface.
2494 @deffn {Command} {cmsis-dap info}
2495 Display various device information, like hardware version, firmware version, current bus status.
2498 @deffn {Command} {cmsis-dap cmd} number number ...
2499 Execute an arbitrary CMSIS-DAP command. Use for adapter testing or for handling
2500 of an adapter vendor specific command from a Tcl script.
2502 Take given numbers as bytes, assemble a CMSIS-DAP protocol command packet
2503 from them and send it to the adapter. The first 4 bytes of the adapter response
2505 See @url{https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Commands__gr.html}
2509 @deffn {Interface Driver} {dummy}
2510 A dummy software-only driver for debugging.
2513 @deffn {Interface Driver} {ep93xx}
2514 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2517 @deffn {Interface Driver} {ftdi}
2518 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2519 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2521 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2522 bypassing intermediate libraries like libftdi.
2524 Support for new FTDI based adapters can be added completely through
2525 configuration files, without the need to patch and rebuild OpenOCD.
2527 The driver uses a signal abstraction to enable Tcl configuration files to
2528 define outputs for one or several FTDI GPIO. These outputs can then be
2529 controlled using the @command{ftdi set_signal} command. Special signal names
2530 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2531 will be used for their customary purpose. Inputs can be read using the
2532 @command{ftdi get_signal} command.
2534 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2535 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2536 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2537 required by the protocol, to tell the adapter to drive the data output onto
2538 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2540 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2541 be controlled differently. In order to support tristateable signals such as
2542 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2543 signal. The following output buffer configurations are supported:
2546 @item Push-pull with one FTDI output as (non-)inverted data line
2547 @item Open drain with one FTDI output as (non-)inverted output-enable
2548 @item Tristate with one FTDI output as (non-)inverted data line and another
2549 FTDI output as (non-)inverted output-enable
2550 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2551 switching data and direction as necessary
2554 These interfaces have several commands, used to configure the driver
2555 before initializing the JTAG scan chain:
2557 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2558 The vendor ID and product ID of the adapter. Up to eight
2559 [@var{vid}, @var{pid}] pairs may be given, e.g.
2561 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2565 @deffn {Config Command} {ftdi device_desc} description
2566 Provides the USB device description (the @emph{iProduct string})
2567 of the adapter. If not specified, the device description is ignored
2568 during device selection.
2571 @deffn {Config Command} {ftdi channel} channel
2572 Selects the channel of the FTDI device to use for MPSSE operations. Most
2573 adapters use the default, channel 0, but there are exceptions.
2576 @deffn {Config Command} {ftdi layout_init} data direction
2577 Specifies the initial values of the FTDI GPIO data and direction registers.
2578 Each value is a 16-bit number corresponding to the concatenation of the high
2579 and low FTDI GPIO registers. The values should be selected based on the
2580 schematics of the adapter, such that all signals are set to safe levels with
2581 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2582 and initially asserted reset signals.
2585 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2586 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2587 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2588 register bitmasks to tell the driver the connection and type of the output
2589 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2590 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2591 used with inverting data inputs and @option{-data} with non-inverting inputs.
2592 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2593 not-output-enable) input to the output buffer is connected. The options
2594 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2595 with the method @command{ftdi get_signal}.
2597 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2598 simple open-collector transistor driver would be specified with @option{-oe}
2599 only. In that case the signal can only be set to drive low or to Hi-Z and the
2600 driver will complain if the signal is set to drive high. Which means that if
2601 it's a reset signal, @command{reset_config} must be specified as
2602 @option{srst_open_drain}, not @option{srst_push_pull}.
2604 A special case is provided when @option{-data} and @option{-oe} is set to the
2605 same bitmask. Then the FTDI pin is considered being connected straight to the
2606 target without any buffer. The FTDI pin is then switched between output and
2607 input as necessary to provide the full set of low, high and Hi-Z
2608 characteristics. In all other cases, the pins specified in a signal definition
2609 are always driven by the FTDI.
2611 If @option{-alias} or @option{-nalias} is used, the signal is created
2612 identical (or with data inverted) to an already specified signal
2616 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2617 Set a previously defined signal to the specified level.
2619 @item @option{0}, drive low
2620 @item @option{1}, drive high
2621 @item @option{z}, set to high-impedance
2625 @deffn {Command} {ftdi get_signal} name
2626 Get the value of a previously defined signal.
2629 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2630 Configure TCK edge at which the adapter samples the value of the TDO signal
2632 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2633 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2634 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2635 stability at higher JTAG clocks.
2637 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2638 @item @option{falling}, sample TDO on falling edge of TCK
2642 For example adapter definitions, see the configuration files shipped in the
2643 @file{interface/ftdi} directory.
2647 @deffn {Interface Driver} {ft232r}
2648 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2649 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2650 It currently doesn't support using CBUS pins as GPIO.
2652 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2659 @item DCD(10) - SRST
2662 User can change default pinout by supplying configuration
2663 commands with GPIO numbers or RS232 signal names.
2664 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2665 They differ from physical pin numbers.
2666 For details see actual FTDI chip datasheets.
2667 Every JTAG line must be configured to unique GPIO number
2668 different than any other JTAG line, even those lines
2669 that are sometimes not used like TRST or SRST.
2683 These interfaces have several commands, used to configure the driver
2684 before initializing the JTAG scan chain:
2686 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2687 The vendor ID and product ID of the adapter. If not specified, default
2688 0x0403:0x6001 is used.
2691 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2692 Set four JTAG GPIO numbers at once.
2693 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2696 @deffn {Config Command} {ft232r tck_num} @var{tck}
2697 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2700 @deffn {Config Command} {ft232r tms_num} @var{tms}
2701 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2704 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2705 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2708 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2709 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2712 @deffn {Config Command} {ft232r trst_num} @var{trst}
2713 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2716 @deffn {Config Command} {ft232r srst_num} @var{srst}
2717 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2720 @deffn {Config Command} {ft232r restore_serial} @var{word}
2721 Restore serial port after JTAG. This USB bitmode control word
2722 (16-bit) will be sent before quit. Lower byte should
2723 set GPIO direction register to a "sane" state:
2724 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2725 byte is usually 0 to disable bitbang mode.
2726 When kernel driver reattaches, serial port should continue to work.
2727 Value 0xFFFF disables sending control word and serial port,
2728 then kernel driver will not reattach.
2729 If not specified, default 0xFFFF is used.
2734 @deffn {Interface Driver} {remote_bitbang}
2735 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2736 with a remote process and sends ASCII encoded bitbang requests to that process
2737 instead of directly driving JTAG.
2739 The remote_bitbang driver is useful for debugging software running on
2740 processors which are being simulated.
2742 @deffn {Config Command} {remote_bitbang port} number
2743 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2744 sockets instead of TCP.
2747 @deffn {Config Command} {remote_bitbang host} hostname
2748 Specifies the hostname of the remote process to connect to using TCP, or the
2749 name of the UNIX socket to use if remote_bitbang port is 0.
2752 For example, to connect remotely via TCP to the host foobar you might have
2756 adapter driver remote_bitbang
2757 remote_bitbang port 3335
2758 remote_bitbang host foobar
2761 To connect to another process running locally via UNIX sockets with socket
2765 adapter driver remote_bitbang
2766 remote_bitbang port 0
2767 remote_bitbang host mysocket
2771 @deffn {Interface Driver} {usb_blaster}
2772 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2773 for FTDI chips. These interfaces have several commands, used to
2774 configure the driver before initializing the JTAG scan chain:
2776 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2777 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2778 default values are used.
2779 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2780 Altera USB-Blaster (default):
2782 usb_blaster vid_pid 0x09FB 0x6001
2784 The following VID/PID is for Kolja Waschk's USB JTAG:
2786 usb_blaster vid_pid 0x16C0 0x06AD
2790 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2791 Sets the state or function of the unused GPIO pins on USB-Blasters
2792 (pins 6 and 8 on the female JTAG header). These pins can be used as
2793 SRST and/or TRST provided the appropriate connections are made on the
2796 For example, to use pin 6 as SRST:
2798 usb_blaster pin pin6 s
2799 reset_config srst_only
2803 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2804 Chooses the low level access method for the adapter. If not specified,
2805 @option{ftdi} is selected unless it wasn't enabled during the
2806 configure stage. USB-Blaster II needs @option{ublast2}.
2809 @deffn {Config Command} {usb_blaster firmware} @var{path}
2810 This command specifies @var{path} to access USB-Blaster II firmware
2811 image. To be used with USB-Blaster II only.
2816 @deffn {Interface Driver} {gw16012}
2817 Gateworks GW16012 JTAG programmer.
2818 This has one driver-specific command:
2820 @deffn {Config Command} {parport port} [port_number]
2821 Display either the address of the I/O port
2822 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2823 If a parameter is provided, first switch to use that port.
2824 This is a write-once setting.
2828 @deffn {Interface Driver} {jlink}
2829 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2832 @quotation Compatibility Note
2833 SEGGER released many firmware versions for the many hardware versions they
2834 produced. OpenOCD was extensively tested and intended to run on all of them,
2835 but some combinations were reported as incompatible. As a general
2836 recommendation, it is advisable to use the latest firmware version
2837 available for each hardware version. However the current V8 is a moving
2838 target, and SEGGER firmware versions released after the OpenOCD was
2839 released may not be compatible. In such cases it is recommended to
2840 revert to the last known functional version. For 0.5.0, this is from
2841 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2842 version is from "May 3 2012 18:36:22", packed with 4.46f.
2845 @deffn {Command} {jlink hwstatus}
2846 Display various hardware related information, for example target voltage and pin
2849 @deffn {Command} {jlink freemem}
2850 Display free device internal memory.
2852 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2853 Set the JTAG command version to be used. Without argument, show the actual JTAG
2856 @deffn {Command} {jlink config}
2857 Display the device configuration.
2859 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2860 Set the target power state on JTAG-pin 19. Without argument, show the target
2863 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2864 Set the MAC address of the device. Without argument, show the MAC address.
2866 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2867 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2868 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2871 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2872 Set the USB address of the device. This will also change the USB Product ID
2873 (PID) of the device. Without argument, show the USB address.
2875 @deffn {Command} {jlink config reset}
2876 Reset the current configuration.
2878 @deffn {Command} {jlink config write}
2879 Write the current configuration to the internal persistent storage.
2881 @deffn {Command} {jlink emucom write} <channel> <data>
2882 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2885 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2886 the EMUCOM channel 0x10:
2888 > jlink emucom write 0x10 aa0b23
2891 @deffn {Command} {jlink emucom read} <channel> <length>
2892 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2895 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2897 > jlink emucom read 0x0 4
2901 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2902 Set the USB address of the interface, in case more than one adapter is connected
2903 to the host. If not specified, USB addresses are not considered. Device
2904 selection via USB address is not always unambiguous. It is recommended to use
2905 the serial number instead, if possible.
2907 As a configuration command, it can be used only before 'init'.
2911 @deffn {Interface Driver} {kitprog}
2912 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2913 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2914 families, but it is possible to use it with some other devices. If you are using
2915 this adapter with a PSoC or a PRoC, you may need to add
2916 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2917 configuration script.
2919 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2920 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2921 be used with this driver, and must either be used with the cmsis-dap driver or
2922 switched back to KitProg mode. See the Cypress KitProg User Guide for
2923 instructions on how to switch KitProg modes.
2927 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2929 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2930 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2931 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2932 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2933 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2934 SWD sequence must be sent after every target reset in order to re-establish
2935 communications with the target.
2936 @item Due in part to the limitation above, KitProg devices with firmware below
2937 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2938 communicate with PSoC 5LP devices. This is because, assuming debug is not
2939 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2940 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2941 could only be sent with an acquisition sequence.
2944 @deffn {Config Command} {kitprog_init_acquire_psoc}
2945 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2946 Please be aware that the acquisition sequence hard-resets the target.
2949 @deffn {Command} {kitprog acquire_psoc}
2950 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2951 outside of the target-specific configuration scripts since it hard-resets the
2952 target as a side-effect.
2953 This is necessary for "reset halt" on some PSoC 4 series devices.
2956 @deffn {Command} {kitprog info}
2957 Display various adapter information, such as the hardware version, firmware
2958 version, and target voltage.
2962 @deffn {Interface Driver} {parport}
2963 Supports PC parallel port bit-banging cables:
2964 Wigglers, PLD download cable, and more.
2965 These interfaces have several commands, used to configure the driver
2966 before initializing the JTAG scan chain:
2968 @deffn {Config Command} {parport cable} name
2969 Set the layout of the parallel port cable used to connect to the target.
2970 This is a write-once setting.
2971 Currently valid cable @var{name} values include:
2974 @item @b{altium} Altium Universal JTAG cable.
2975 @item @b{arm-jtag} Same as original wiggler except SRST and
2976 TRST connections reversed and TRST is also inverted.
2977 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2978 in configuration mode. This is only used to
2979 program the Chameleon itself, not a connected target.
2980 @item @b{dlc5} The Xilinx Parallel cable III.
2981 @item @b{flashlink} The ST Parallel cable.
2982 @item @b{lattice} Lattice ispDOWNLOAD Cable
2983 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2985 Amontec's Chameleon Programmer. The new version available from
2986 the website uses the original Wiggler layout ('@var{wiggler}')
2987 @item @b{triton} The parallel port adapter found on the
2988 ``Karo Triton 1 Development Board''.
2989 This is also the layout used by the HollyGates design
2990 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2991 @item @b{wiggler} The original Wiggler layout, also supported by
2992 several clones, such as the Olimex ARM-JTAG
2993 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2994 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2998 @deffn {Config Command} {parport port} [port_number]
2999 Display either the address of the I/O port
3000 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
3001 If a parameter is provided, first switch to use that port.
3002 This is a write-once setting.
3004 When using PPDEV to access the parallel port, use the number of the parallel port:
3005 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
3006 you may encounter a problem.
3009 @deffn {Config Command} {parport toggling_time} [nanoseconds]
3010 Displays how many nanoseconds the hardware needs to toggle TCK;
3011 the parport driver uses this value to obey the
3012 @command{adapter speed} configuration.
3013 When the optional @var{nanoseconds} parameter is given,
3014 that setting is changed before displaying the current value.
3016 The default setting should work reasonably well on commodity PC hardware.
3017 However, you may want to calibrate for your specific hardware.
3019 To measure the toggling time with a logic analyzer or a digital storage
3020 oscilloscope, follow the procedure below:
3022 > parport toggling_time 1000
3025 This sets the maximum JTAG clock speed of the hardware, but
3026 the actual speed probably deviates from the requested 500 kHz.
3027 Now, measure the time between the two closest spaced TCK transitions.
3028 You can use @command{runtest 1000} or something similar to generate a
3029 large set of samples.
3030 Update the setting to match your measurement:
3032 > parport toggling_time <measured nanoseconds>
3034 Now the clock speed will be a better match for @command{adapter speed}
3035 command given in OpenOCD scripts and event handlers.
3037 You can do something similar with many digital multimeters, but note
3038 that you'll probably need to run the clock continuously for several
3039 seconds before it decides what clock rate to show. Adjust the
3040 toggling time up or down until the measured clock rate is a good
3041 match with the rate you specified in the @command{adapter speed} command;
3046 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3047 This will configure the parallel driver to write a known
3048 cable-specific value to the parallel interface on exiting OpenOCD.
3051 For example, the interface configuration file for a
3052 classic ``Wiggler'' cable on LPT2 might look something like this:
3055 adapter driver parport
3057 parport cable wiggler
3061 @deffn {Interface Driver} {presto}
3062 ASIX PRESTO USB JTAG programmer.
3065 @deffn {Interface Driver} {rlink}
3066 Raisonance RLink USB adapter
3069 @deffn {Interface Driver} {usbprog}
3070 usbprog is a freely programmable USB adapter.
3073 @deffn {Interface Driver} {vsllink}
3074 vsllink is part of Versaloon which is a versatile USB programmer.
3077 This defines quite a few driver-specific commands,
3078 which are not currently documented here.
3082 @anchor{hla_interface}
3083 @deffn {Interface Driver} {hla}
3084 This is a driver that supports multiple High Level Adapters.
3085 This type of adapter does not expose some of the lower level api's
3086 that OpenOCD would normally use to access the target.
3088 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3089 and Nuvoton Nu-Link.
3090 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3091 versions of firmware where serial number is reset after first use. Suggest
3092 using ST firmware update utility to upgrade ST-LINK firmware even if current
3093 version reported is V2.J21.S4.
3095 @deffn {Config Command} {hla_device_desc} description
3096 Currently Not Supported.
3099 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3100 Specifies the adapter layout to use.
3103 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3104 Pairs of vendor IDs and product IDs of the device.
3107 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3108 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3109 'shared' mode using ST-Link TCP server (the default port is 7184).
3111 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3112 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3113 ST-LINK server software module}.
3116 @deffn {Command} {hla_command} command
3117 Execute a custom adapter-specific command. The @var{command} string is
3118 passed as is to the underlying adapter layout handler.
3122 @anchor{st_link_dap_interface}
3123 @deffn {Interface Driver} {st-link}
3124 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3125 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3126 directly access the arm ADIv5 DAP.
3128 The new API provide access to multiple AP on the same DAP, but the
3129 maximum number of the AP port is limited by the specific firmware version
3130 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3131 An error is returned for any AP number above the maximum allowed value.
3133 @emph{Note:} Either these same adapters and their older versions are
3134 also supported by @ref{hla_interface, the hla interface driver}.
3136 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3137 Choose between 'exclusive' USB communication (the default backend) or
3138 'shared' mode using ST-Link TCP server (the default port is 7184).
3140 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3141 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3142 ST-LINK server software module}.
3144 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3147 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3148 Pairs of vendor IDs and product IDs of the device.
3151 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3152 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3153 and receives @var{rx_n} bytes.
3155 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3156 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3157 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3158 the target's supply voltage.
3160 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3161 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3163 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3165 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3166 > set n [expr @{[lindex $a 4] + 256 * [lindex $a 5]@}]
3167 > set d [expr @{[lindex $a 0] + 256 * [lindex $a 1]@}]
3168 > echo [expr @{2 * 1.2 * $n / $d@}]
3174 @deffn {Interface Driver} {opendous}
3175 opendous-jtag is a freely programmable USB adapter.
3178 @deffn {Interface Driver} {ulink}
3179 This is the Keil ULINK v1 JTAG debugger.
3182 @deffn {Interface Driver} {xds110}
3183 The XDS110 is included as the embedded debug probe on many Texas Instruments
3184 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3185 debug probe with the added capability to supply power to the target board. The
3186 following commands are supported by the XDS110 driver:
3188 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3189 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3190 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3191 can be set to any value in the range 1800 to 3600 millivolts.
3194 @deffn {Command} {xds110 info}
3195 Displays information about the connected XDS110 debug probe (e.g. firmware
3200 @deffn {Interface Driver} {xlnx_pcie_xvc}
3201 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3202 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3203 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3204 exposed via extended capability registers in the PCI Express configuration space.
3206 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3208 @deffn {Config Command} {xlnx_pcie_xvc config} device
3209 Specifies the PCI Express device via parameter @var{device} to use.
3211 The correct value for @var{device} can be obtained by looking at the output
3212 of lscpi -D (first column) for the corresponding device.
3214 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3219 @deffn {Interface Driver} {bcm2835gpio}
3220 This SoC is present in Raspberry Pi which is a cheap single-board computer
3221 exposing some GPIOs on its expansion header.
3223 The driver accesses memory-mapped GPIO peripheral registers directly
3224 for maximum performance, but the only possible race condition is for
3225 the pins' modes/muxing (which is highly unlikely), so it should be
3226 able to coexist nicely with both sysfs bitbanging and various
3227 peripherals' kernel drivers. The driver restores the previous
3228 configuration on exit.
3230 GPIO numbers >= 32 can't be used for performance reasons.
3232 See @file{interface/raspberrypi-native.cfg} for a sample config and
3235 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3236 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3237 Must be specified to enable JTAG transport. These pins can also be specified
3241 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3242 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3243 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3246 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3247 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3248 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3251 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3252 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3253 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3256 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3257 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3258 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3261 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3262 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3263 specified to enable SWD transport. These pins can also be specified individually.
3266 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3267 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3268 specified using the configuration command @command{bcm2835gpio swd_nums}.
3271 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3272 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3273 specified using the configuration command @command{bcm2835gpio swd_nums}.
3276 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3277 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3278 to control the direction of an external buffer on the SWDIO pin (set=output
3279 mode, clear=input mode). If not specified, this feature is disabled.
3282 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3283 Set SRST GPIO number. Must be specified to enable SRST.
3286 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3287 Set TRST GPIO number. Must be specified to enable TRST.
3290 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3291 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3292 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3295 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3296 Set the peripheral base register address to access GPIOs. For the RPi1, use
3297 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3298 list can be found in the
3299 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3304 @deffn {Interface Driver} {imx_gpio}
3305 i.MX SoC is present in many community boards. Wandboard is an example
3306 of the one which is most popular.
3308 This driver is mostly the same as bcm2835gpio.
3310 See @file{interface/imx-native.cfg} for a sample config and
3316 @deffn {Interface Driver} {linuxgpiod}
3317 Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
3318 The driver emulates either JTAG and SWD transport through bitbanging.
3320 See @file{interface/dln-2-gpiod.cfg} for a sample config.
3324 @deffn {Interface Driver} {sysfsgpio}
3325 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3326 Prefer using @b{linuxgpiod}, instead.
3328 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3332 @deffn {Interface Driver} {openjtag}
3333 OpenJTAG compatible USB adapter.
3334 This defines some driver-specific commands:
3336 @deffn {Config Command} {openjtag variant} variant
3337 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3338 Currently valid @var{variant} values include:
3341 @item @b{standard} Standard variant (default).
3342 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3343 (see @uref{http://www.cypress.com/?rID=82870}).
3347 @deffn {Config Command} {openjtag device_desc} string
3348 The USB device description string of the adapter.
3349 This value is only used with the standard variant.
3354 @deffn {Interface Driver} {vdebug}
3355 Cadence Virtual Debug Interface driver.
3357 @deffn {Config Command} {vdebug server} host:port
3358 Specifies the host and TCP port number where the vdebug server runs.
3361 @deffn {Config Command} {vdebug batching} value
3362 Specifies the batching method for the vdebug request. Possible values are
3364 1 or wr to batch write transactions together (default)
3365 2 or rw to batch both read and write transactions
3368 @deffn {Config Command} {vdebug polling} min max
3369 Takes two values, representing the polling interval in ms. Lower values mean faster
3370 debugger responsiveness, but lower emulation performance. The minimum should be
3371 around 10, maximum should not exceed 1000, which is the default gdb and keepalive
3375 @deffn {Config Command} {vdebug bfm_path} path clk_period
3376 Specifies the hierarchical path and input clk period of the vdebug BFM in the design.
3377 The hierarchical path uses Verilog notation top.inst.inst
3378 The clock period must include the unit, for instance 40ns.
3381 @deffn {Config Command} {vdebug mem_path} path base size
3382 Specifies the hierarchical path to the design memory instance for backdoor access.
3383 Up to 4 memories can be specified. The hierarchical path uses Verilog notation.
3384 The base specifies start address in the design address space, size its size in bytes.
3385 Both values can use hexadecimal notation with prefix 0x.
3389 @deffn {Interface Driver} {jtag_dpi}
3390 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3391 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3392 DPI server interface.
3394 @deffn {Config Command} {jtag_dpi set_port} port
3395 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3398 @deffn {Config Command} {jtag_dpi set_address} address
3399 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3404 @deffn {Interface Driver} {buspirate}
3406 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3407 It uses a simple data protocol over a serial port connection.
3409 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3410 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3412 @deffn {Config Command} {buspirate port} serial_port
3413 Specify the serial port's filename. For example:
3415 buspirate port /dev/ttyUSB0
3419 @deffn {Config Command} {buspirate speed} (normal|fast)
3420 Set the communication speed to 115k (normal) or 1M (fast). For example:
3422 buspirate speed normal
3426 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3427 Set the Bus Pirate output mode.
3429 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3430 @item In open drain mode, you will then need to enable the pull-ups.
3434 buspirate mode normal
3438 @deffn {Config Command} {buspirate pullup} (0|1)
3439 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3440 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3447 @deffn {Config Command} {buspirate vreg} (0|1)
3448 Whether to enable (1) or disable (0) the built-in voltage regulator,
3449 which can be used to supply power to a test circuit through
3450 I/O header pins +3V3 and +5V. For example:
3456 @deffn {Command} {buspirate led} (0|1)
3457 Turns the Bus Pirate's LED on (1) or off (0). For example:
3466 @section Transport Configuration
3468 As noted earlier, depending on the version of OpenOCD you use,
3469 and the debug adapter you are using,
3470 several transports may be available to
3471 communicate with debug targets (or perhaps to program flash memory).
3472 @deffn {Command} {transport list}
3473 displays the names of the transports supported by this
3477 @deffn {Command} {transport select} @option{transport_name}
3478 Select which of the supported transports to use in this OpenOCD session.
3480 When invoked with @option{transport_name}, attempts to select the named
3481 transport. The transport must be supported by the debug adapter
3482 hardware and by the version of OpenOCD you are using (including the
3485 If no transport has been selected and no @option{transport_name} is
3486 provided, @command{transport select} auto-selects the first transport
3487 supported by the debug adapter.
3489 @command{transport select} always returns the name of the session's selected
3493 @subsection JTAG Transport
3495 JTAG is the original transport supported by OpenOCD, and most
3496 of the OpenOCD commands support it.
3497 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3498 each of which must be explicitly declared.
3499 JTAG supports both debugging and boundary scan testing.
3500 Flash programming support is built on top of debug support.
3502 JTAG transport is selected with the command @command{transport select
3503 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3504 driver} (in which case the command is @command{transport select hla_jtag})
3505 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3506 the command is @command{transport select dapdirect_jtag}).
3508 @subsection SWD Transport
3510 @cindex Serial Wire Debug
3511 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3512 Debug Access Point (DAP, which must be explicitly declared.
3513 (SWD uses fewer signal wires than JTAG.)
3514 SWD is debug-oriented, and does not support boundary scan testing.
3515 Flash programming support is built on top of debug support.
3516 (Some processors support both JTAG and SWD.)
3518 SWD transport is selected with the command @command{transport select
3519 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3520 driver} (in which case the command is @command{transport select hla_swd})
3521 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3522 the command is @command{transport select dapdirect_swd}).
3524 @deffn {Config Command} {swd newdap} ...
3525 Declares a single DAP which uses SWD transport.
3526 Parameters are currently the same as "jtag newtap" but this is
3530 @cindex SWD multi-drop
3531 The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop extension
3532 of SWD protocol: two or more devices can be connected to one SWD adapter.
3533 SWD transport works in multi-drop mode if @ref{dap_create,DAP} is configured
3534 with both @code{-dp-id} and @code{-instance-id} parameters regardless how many
3537 Not all adapters and adapter drivers support SWD multi-drop. Only the following
3538 adapter drivers are SWD multi-drop capable:
3539 cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
3541 @subsection SPI Transport
3543 @cindex Serial Peripheral Interface
3544 The Serial Peripheral Interface (SPI) is a general purpose transport
3545 which uses four wire signaling. Some processors use it as part of a
3546 solution for flash programming.
3548 @anchor{swimtransport}
3549 @subsection SWIM Transport
3551 @cindex Single Wire Interface Module
3552 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3553 by the STMicroelectronics MCU family STM8 and documented in the
3554 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3556 SWIM does not support boundary scan testing nor multiple cores.
3558 The SWIM transport is selected with the command @command{transport select swim}.
3560 The concept of TAPs does not fit in the protocol since SWIM does not implement
3561 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3562 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3563 The TAP definition must precede the target definition command
3564 @command{target create target_name stm8 -chain-position basename.tap_type}.
3568 JTAG clock setup is part of system setup.
3569 It @emph{does not belong with interface setup} since any interface
3570 only knows a few of the constraints for the JTAG clock speed.
3571 Sometimes the JTAG speed is
3572 changed during the target initialization process: (1) slow at
3573 reset, (2) program the CPU clocks, (3) run fast.
3574 Both the "slow" and "fast" clock rates are functions of the
3575 oscillators used, the chip, the board design, and sometimes
3576 power management software that may be active.
3578 The speed used during reset, and the scan chain verification which
3579 follows reset, can be adjusted using a @code{reset-start}
3580 target event handler.
3581 It can then be reconfigured to a faster speed by a
3582 @code{reset-init} target event handler after it reprograms those
3583 CPU clocks, or manually (if something else, such as a boot loader,
3584 sets up those clocks).
3585 @xref{targetevents,,Target Events}.
3586 When the initial low JTAG speed is a chip characteristic, perhaps
3587 because of a required oscillator speed, provide such a handler
3588 in the target config file.
3589 When that speed is a function of a board-specific characteristic
3590 such as which speed oscillator is used, it belongs in the board
3591 config file instead.
3592 In both cases it's safest to also set the initial JTAG clock rate
3593 to that same slow speed, so that OpenOCD never starts up using a
3594 clock speed that's faster than the scan chain can support.
3598 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3601 If your system supports adaptive clocking (RTCK), configuring
3602 JTAG to use that is probably the most robust approach.
3603 However, it introduces delays to synchronize clocks; so it
3604 may not be the fastest solution.
3606 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3607 instead of @command{adapter speed}, but only for (ARM) cores and boards
3608 which support adaptive clocking.
3610 @deffn {Command} {adapter speed} max_speed_kHz
3611 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3612 JTAG interfaces usually support a limited number of
3613 speeds. The speed actually used won't be faster
3614 than the speed specified.
3616 Chip data sheets generally include a top JTAG clock rate.
3617 The actual rate is often a function of a CPU core clock,
3618 and is normally less than that peak rate.
3619 For example, most ARM cores accept at most one sixth of the CPU clock.
3621 Speed 0 (khz) selects RTCK method.
3622 @xref{faqrtck,,FAQ RTCK}.
3623 If your system uses RTCK, you won't need to change the
3624 JTAG clocking after setup.
3625 Not all interfaces, boards, or targets support ``rtck''.
3626 If the interface device can not
3627 support it, an error is returned when you try to use RTCK.
3630 @defun jtag_rclk fallback_speed_kHz
3631 @cindex adaptive clocking
3633 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3634 If that fails (maybe the interface, board, or target doesn't
3635 support it), falls back to the specified frequency.
3637 # Fall back to 3mhz if RTCK is not supported
3642 @node Reset Configuration
3643 @chapter Reset Configuration
3644 @cindex Reset Configuration
3646 Every system configuration may require a different reset
3647 configuration. This can also be quite confusing.
3648 Resets also interact with @var{reset-init} event handlers,
3649 which do things like setting up clocks and DRAM, and
3650 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3651 They can also interact with JTAG routers.
3652 Please see the various board files for examples.
3655 To maintainers and integrators:
3656 Reset configuration touches several things at once.
3657 Normally the board configuration file
3658 should define it and assume that the JTAG adapter supports
3659 everything that's wired up to the board's JTAG connector.
3661 However, the target configuration file could also make note
3662 of something the silicon vendor has done inside the chip,
3663 which will be true for most (or all) boards using that chip.
3664 And when the JTAG adapter doesn't support everything, the
3665 user configuration file will need to override parts of
3666 the reset configuration provided by other files.
3669 @section Types of Reset
3671 There are many kinds of reset possible through JTAG, but
3672 they may not all work with a given board and adapter.
3673 That's part of why reset configuration can be error prone.
3677 @emph{System Reset} ... the @emph{SRST} hardware signal
3678 resets all chips connected to the JTAG adapter, such as processors,
3679 power management chips, and I/O controllers. Normally resets triggered
3680 with this signal behave exactly like pressing a RESET button.
3682 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3683 just the TAP controllers connected to the JTAG adapter.
3684 Such resets should not be visible to the rest of the system; resetting a
3685 device's TAP controller just puts that controller into a known state.
3687 @emph{Emulation Reset} ... many devices can be reset through JTAG
3688 commands. These resets are often distinguishable from system
3689 resets, either explicitly (a "reset reason" register says so)
3690 or implicitly (not all parts of the chip get reset).
3692 @emph{Other Resets} ... system-on-chip devices often support
3693 several other types of reset.
3694 You may need to arrange that a watchdog timer stops
3695 while debugging, preventing a watchdog reset.
3696 There may be individual module resets.
3699 In the best case, OpenOCD can hold SRST, then reset
3700 the TAPs via TRST and send commands through JTAG to halt the
3701 CPU at the reset vector before the 1st instruction is executed.
3702 Then when it finally releases the SRST signal, the system is
3703 halted under debugger control before any code has executed.
3704 This is the behavior required to support the @command{reset halt}
3705 and @command{reset init} commands; after @command{reset init} a
3706 board-specific script might do things like setting up DRAM.
3707 (@xref{resetcommand,,Reset Command}.)
3709 @anchor{srstandtrstissues}
3710 @section SRST and TRST Issues
3712 Because SRST and TRST are hardware signals, they can have a
3713 variety of system-specific constraints. Some of the most
3718 @item @emph{Signal not available} ... Some boards don't wire
3719 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3720 support such signals even if they are wired up.
3721 Use the @command{reset_config} @var{signals} options to say
3722 when either of those signals is not connected.
3723 When SRST is not available, your code might not be able to rely
3724 on controllers having been fully reset during code startup.
3725 Missing TRST is not a problem, since JTAG-level resets can
3726 be triggered using with TMS signaling.
3728 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3729 adapter will connect SRST to TRST, instead of keeping them separate.
3730 Use the @command{reset_config} @var{combination} options to say
3731 when those signals aren't properly independent.
3733 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3734 delay circuit, reset supervisor, or on-chip features can extend
3735 the effect of a JTAG adapter's reset for some time after the adapter
3736 stops issuing the reset. For example, there may be chip or board
3737 requirements that all reset pulses last for at least a
3738 certain amount of time; and reset buttons commonly have
3739 hardware debouncing.
3740 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3741 commands to say when extra delays are needed.
3743 @item @emph{Drive type} ... Reset lines often have a pullup
3744 resistor, letting the JTAG interface treat them as open-drain
3745 signals. But that's not a requirement, so the adapter may need
3746 to use push/pull output drivers.
3747 Also, with weak pullups it may be advisable to drive
3748 signals to both levels (push/pull) to minimize rise times.
3749 Use the @command{reset_config} @var{trst_type} and
3750 @var{srst_type} parameters to say how to drive reset signals.
3752 @item @emph{Special initialization} ... Targets sometimes need
3753 special JTAG initialization sequences to handle chip-specific
3754 issues (not limited to errata).
3755 For example, certain JTAG commands might need to be issued while
3756 the system as a whole is in a reset state (SRST active)
3757 but the JTAG scan chain is usable (TRST inactive).
3758 Many systems treat combined assertion of SRST and TRST as a
3759 trigger for a harder reset than SRST alone.
3760 Such custom reset handling is discussed later in this chapter.
3763 There can also be other issues.
3764 Some devices don't fully conform to the JTAG specifications.
3765 Trivial system-specific differences are common, such as
3766 SRST and TRST using slightly different names.
3767 There are also vendors who distribute key JTAG documentation for
3768 their chips only to developers who have signed a Non-Disclosure
3771 Sometimes there are chip-specific extensions like a requirement to use
3772 the normally-optional TRST signal (precluding use of JTAG adapters which
3773 don't pass TRST through), or needing extra steps to complete a TAP reset.
3775 In short, SRST and especially TRST handling may be very finicky,
3776 needing to cope with both architecture and board specific constraints.
3778 @section Commands for Handling Resets
3780 @deffn {Command} {adapter srst pulse_width} milliseconds
3781 Minimum amount of time (in milliseconds) OpenOCD should wait
3782 after asserting nSRST (active-low system reset) before
3783 allowing it to be deasserted.
3786 @deffn {Command} {adapter srst delay} milliseconds
3787 How long (in milliseconds) OpenOCD should wait after deasserting
3788 nSRST (active-low system reset) before starting new JTAG operations.
3789 When a board has a reset button connected to SRST line it will
3790 probably have hardware debouncing, implying you should use this.
3793 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
3794 Minimum amount of time (in milliseconds) OpenOCD should wait
3795 after asserting nTRST (active-low JTAG TAP reset) before
3796 allowing it to be deasserted.
3799 @deffn {Command} {jtag_ntrst_delay} milliseconds
3800 How long (in milliseconds) OpenOCD should wait after deasserting
3801 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3804 @anchor{reset_config}
3805 @deffn {Command} {reset_config} mode_flag ...
3806 This command displays or modifies the reset configuration
3807 of your combination of JTAG board and target in target
3808 configuration scripts.
3810 Information earlier in this section describes the kind of problems
3811 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3812 As a rule this command belongs only in board config files,
3813 describing issues like @emph{board doesn't connect TRST};
3814 or in user config files, addressing limitations derived
3815 from a particular combination of interface and board.
3816 (An unlikely example would be using a TRST-only adapter
3817 with a board that only wires up SRST.)
3819 The @var{mode_flag} options can be specified in any order, but only one
3820 of each type -- @var{signals}, @var{combination}, @var{gates},
3821 @var{trst_type}, @var{srst_type} and @var{connect_type}
3822 -- may be specified at a time.
3823 If you don't provide a new value for a given type, its previous
3824 value (perhaps the default) is unchanged.
3825 For example, this means that you don't need to say anything at all about
3826 TRST just to declare that if the JTAG adapter should want to drive SRST,
3827 it must explicitly be driven high (@option{srst_push_pull}).
3831 @var{signals} can specify which of the reset signals are connected.
3832 For example, If the JTAG interface provides SRST, but the board doesn't
3833 connect that signal properly, then OpenOCD can't use it.
3834 Possible values are @option{none} (the default), @option{trst_only},
3835 @option{srst_only} and @option{trst_and_srst}.
3838 If your board provides SRST and/or TRST through the JTAG connector,
3839 you must declare that so those signals can be used.
3843 The @var{combination} is an optional value specifying broken reset
3844 signal implementations.
3845 The default behaviour if no option given is @option{separate},
3846 indicating everything behaves normally.
3847 @option{srst_pulls_trst} states that the
3848 test logic is reset together with the reset of the system (e.g. NXP
3849 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3850 the system is reset together with the test logic (only hypothetical, I
3851 haven't seen hardware with such a bug, and can be worked around).
3852 @option{combined} implies both @option{srst_pulls_trst} and
3853 @option{trst_pulls_srst}.
3856 The @var{gates} tokens control flags that describe some cases where
3857 JTAG may be unavailable during reset.
3858 @option{srst_gates_jtag} (default)
3859 indicates that asserting SRST gates the
3860 JTAG clock. This means that no communication can happen on JTAG
3861 while SRST is asserted.
3862 Its converse is @option{srst_nogate}, indicating that JTAG commands
3863 can safely be issued while SRST is active.
3866 The @var{connect_type} tokens control flags that describe some cases where
3867 SRST is asserted while connecting to the target. @option{srst_nogate}
3868 is required to use this option.
3869 @option{connect_deassert_srst} (default)
3870 indicates that SRST will not be asserted while connecting to the target.
3871 Its converse is @option{connect_assert_srst}, indicating that SRST will
3872 be asserted before any target connection.
3873 Only some targets support this feature, STM32 and STR9 are examples.
3874 This feature is useful if you are unable to connect to your target due
3875 to incorrect options byte config or illegal program execution.
3878 The optional @var{trst_type} and @var{srst_type} parameters allow the
3879 driver mode of each reset line to be specified. These values only affect
3880 JTAG interfaces with support for different driver modes, like the Amontec
3881 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3882 relevant signal (TRST or SRST) is not connected.
3886 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3887 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3888 Most boards connect this signal to a pulldown, so the JTAG TAPs
3889 never leave reset unless they are hooked up to a JTAG adapter.
3892 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3893 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3894 Most boards connect this signal to a pullup, and allow the
3895 signal to be pulled low by various events including system
3896 power-up and pressing a reset button.
3900 @section Custom Reset Handling
3903 OpenOCD has several ways to help support the various reset
3904 mechanisms provided by chip and board vendors.
3905 The commands shown in the previous section give standard parameters.
3906 There are also @emph{event handlers} associated with TAPs or Targets.
3907 Those handlers are Tcl procedures you can provide, which are invoked
3908 at particular points in the reset sequence.
3910 @emph{When SRST is not an option} you must set
3911 up a @code{reset-assert} event handler for your target.
3912 For example, some JTAG adapters don't include the SRST signal;
3913 and some boards have multiple targets, and you won't always
3914 want to reset everything at once.
3916 After configuring those mechanisms, you might still
3917 find your board doesn't start up or reset correctly.
3918 For example, maybe it needs a slightly different sequence
3919 of SRST and/or TRST manipulations, because of quirks that
3920 the @command{reset_config} mechanism doesn't address;
3921 or asserting both might trigger a stronger reset, which
3922 needs special attention.
3924 Experiment with lower level operations, such as
3925 @command{adapter assert}, @command{adapter deassert}
3926 and the @command{jtag arp_*} operations shown here,
3927 to find a sequence of operations that works.
3928 @xref{JTAG Commands}.
3929 When you find a working sequence, it can be used to override
3930 @command{jtag_init}, which fires during OpenOCD startup
3931 (@pxref{configurationstage,,Configuration Stage});
3932 or @command{init_reset}, which fires during reset processing.
3934 You might also want to provide some project-specific reset
3935 schemes. For example, on a multi-target board the standard
3936 @command{reset} command would reset all targets, but you
3937 may need the ability to reset only one target at time and
3938 thus want to avoid using the board-wide SRST signal.
3940 @deffn {Overridable Procedure} {init_reset} mode
3941 This is invoked near the beginning of the @command{reset} command,
3942 usually to provide as much of a cold (power-up) reset as practical.
3943 By default it is also invoked from @command{jtag_init} if
3944 the scan chain does not respond to pure JTAG operations.
3945 The @var{mode} parameter is the parameter given to the
3946 low level reset command (@option{halt},
3947 @option{init}, or @option{run}), @option{setup},
3948 or potentially some other value.
3950 The default implementation just invokes @command{jtag arp_init-reset}.
3951 Replacements will normally build on low level JTAG
3952 operations such as @command{adapter assert} and @command{adapter deassert}.
3953 Operations here must not address individual TAPs
3954 (or their associated targets)
3955 until the JTAG scan chain has first been verified to work.
3957 Implementations must have verified the JTAG scan chain before
3959 This is done by calling @command{jtag arp_init}
3960 (or @command{jtag arp_init-reset}).
3963 @deffn {Command} {jtag arp_init}
3964 This validates the scan chain using just the four
3965 standard JTAG signals (TMS, TCK, TDI, TDO).
3966 It starts by issuing a JTAG-only reset.
3967 Then it performs checks to verify that the scan chain configuration
3968 matches the TAPs it can observe.
3969 Those checks include checking IDCODE values for each active TAP,
3970 and verifying the length of their instruction registers using
3971 TAP @code{-ircapture} and @code{-irmask} values.
3972 If these tests all pass, TAP @code{setup} events are
3973 issued to all TAPs with handlers for that event.
3976 @deffn {Command} {jtag arp_init-reset}
3977 This uses TRST and SRST to try resetting
3978 everything on the JTAG scan chain
3979 (and anything else connected to SRST).
3980 It then invokes the logic of @command{jtag arp_init}.
3984 @node TAP Declaration
3985 @chapter TAP Declaration
3986 @cindex TAP declaration
3987 @cindex TAP configuration
3989 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3990 TAPs serve many roles, including:
3993 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3994 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3995 Others do it indirectly, making a CPU do it.
3996 @item @b{Program Download} Using the same CPU support GDB uses,
3997 you can initialize a DRAM controller, download code to DRAM, and then
3998 start running that code.
3999 @item @b{Boundary Scan} Most chips support boundary scan, which
4000 helps test for board assembly problems like solder bridges
4001 and missing connections.
4004 OpenOCD must know about the active TAPs on your board(s).
4005 Setting up the TAPs is the core task of your configuration files.
4006 Once those TAPs are set up, you can pass their names to code
4007 which sets up CPUs and exports them as GDB targets,
4008 probes flash memory, performs low-level JTAG operations, and more.
4010 @section Scan Chains
4013 TAPs are part of a hardware @dfn{scan chain},
4014 which is a daisy chain of TAPs.
4015 They also need to be added to
4016 OpenOCD's software mirror of that hardware list,
4017 giving each member a name and associating other data with it.
4018 Simple scan chains, with a single TAP, are common in
4019 systems with a single microcontroller or microprocessor.
4020 More complex chips may have several TAPs internally.
4021 Very complex scan chains might have a dozen or more TAPs:
4022 several in one chip, more in the next, and connecting
4023 to other boards with their own chips and TAPs.
4025 You can display the list with the @command{scan_chain} command.
4026 (Don't confuse this with the list displayed by the @command{targets}
4027 command, presented in the next chapter.
4028 That only displays TAPs for CPUs which are configured as
4030 Here's what the scan chain might look like for a chip more than one TAP:
4033 TapName Enabled IdCode Expected IrLen IrCap IrMask
4034 -- ------------------ ------- ---------- ---------- ----- ----- ------
4035 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
4036 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
4037 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
4040 OpenOCD can detect some of that information, but not all
4041 of it. @xref{autoprobing,,Autoprobing}.
4042 Unfortunately, those TAPs can't always be autoconfigured,
4043 because not all devices provide good support for that.
4044 JTAG doesn't require supporting IDCODE instructions, and
4045 chips with JTAG routers may not link TAPs into the chain
4046 until they are told to do so.
4048 The configuration mechanism currently supported by OpenOCD
4049 requires explicit configuration of all TAP devices using
4050 @command{jtag newtap} commands, as detailed later in this chapter.
4051 A command like this would declare one tap and name it @code{chip1.cpu}:
4054 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
4057 Each target configuration file lists the TAPs provided
4059 Board configuration files combine all the targets on a board,
4061 Note that @emph{the order in which TAPs are declared is very important.}
4062 That declaration order must match the order in the JTAG scan chain,
4063 both inside a single chip and between them.
4064 @xref{faqtaporder,,FAQ TAP Order}.
4066 For example, the STMicroelectronics STR912 chip has
4067 three separate TAPs@footnote{See the ST
4068 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
4069 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
4070 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
4071 To configure those taps, @file{target/str912.cfg}
4072 includes commands something like this:
4075 jtag newtap str912 flash ... params ...
4076 jtag newtap str912 cpu ... params ...
4077 jtag newtap str912 bs ... params ...
4080 Actual config files typically use a variable such as @code{$_CHIPNAME}
4081 instead of literals like @option{str912}, to support more than one chip
4082 of each type. @xref{Config File Guidelines}.
4084 @deffn {Command} {jtag names}
4085 Returns the names of all current TAPs in the scan chain.
4086 Use @command{jtag cget} or @command{jtag tapisenabled}
4087 to examine attributes and state of each TAP.
4089 foreach t [jtag names] @{
4090 puts [format "TAP: %s\n" $t]
4095 @deffn {Command} {scan_chain}
4096 Displays the TAPs in the scan chain configuration,
4098 The set of TAPs listed by this command is fixed by
4099 exiting the OpenOCD configuration stage,
4100 but systems with a JTAG router can
4101 enable or disable TAPs dynamically.
4104 @c FIXME! "jtag cget" should be able to return all TAP
4105 @c attributes, like "$target_name cget" does for targets.
4107 @c Probably want "jtag eventlist", and a "tap-reset" event
4108 @c (on entry to RESET state).
4113 When TAP objects are declared with @command{jtag newtap},
4114 a @dfn{dotted.name} is created for the TAP, combining the
4115 name of a module (usually a chip) and a label for the TAP.
4116 For example: @code{xilinx.tap}, @code{str912.flash},
4117 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4118 Many other commands use that dotted.name to manipulate or
4119 refer to the TAP. For example, CPU configuration uses the
4120 name, as does declaration of NAND or NOR flash banks.
4122 The components of a dotted name should follow ``C'' symbol
4123 name rules: start with an alphabetic character, then numbers
4124 and underscores are OK; while others (including dots!) are not.
4126 @section TAP Declaration Commands
4128 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4129 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4130 and configured according to the various @var{configparams}.
4132 The @var{chipname} is a symbolic name for the chip.
4133 Conventionally target config files use @code{$_CHIPNAME},
4134 defaulting to the model name given by the chip vendor but
4137 @cindex TAP naming convention
4138 The @var{tapname} reflects the role of that TAP,
4139 and should follow this convention:
4142 @item @code{bs} -- For boundary scan if this is a separate TAP;
4143 @item @code{cpu} -- The main CPU of the chip, alternatively
4144 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4145 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4146 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4147 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4148 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4149 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4150 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4152 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4153 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4154 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4155 a JTAG TAP; that TAP should be named @code{sdma}.
4158 Every TAP requires at least the following @var{configparams}:
4161 @item @code{-irlen} @var{NUMBER}
4162 @*The length in bits of the
4163 instruction register, such as 4 or 5 bits.
4166 A TAP may also provide optional @var{configparams}:
4169 @item @code{-disable} (or @code{-enable})
4170 @*Use the @code{-disable} parameter to flag a TAP which is not
4171 linked into the scan chain after a reset using either TRST
4172 or the JTAG state machine's @sc{reset} state.
4173 You may use @code{-enable} to highlight the default state
4174 (the TAP is linked in).
4175 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4176 @item @code{-expected-id} @var{NUMBER}
4177 @*A non-zero @var{number} represents a 32-bit IDCODE
4178 which you expect to find when the scan chain is examined.
4179 These codes are not required by all JTAG devices.
4180 @emph{Repeat the option} as many times as required if more than one
4181 ID code could appear (for example, multiple versions).
4182 Specify @var{number} as zero to suppress warnings about IDCODE
4183 values that were found but not included in the list.
4185 Provide this value if at all possible, since it lets OpenOCD
4186 tell when the scan chain it sees isn't right. These values
4187 are provided in vendors' chip documentation, usually a technical
4188 reference manual. Sometimes you may need to probe the JTAG
4189 hardware to find these values.
4190 @xref{autoprobing,,Autoprobing}.
4191 @item @code{-ignore-version}
4192 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4193 option. When vendors put out multiple versions of a chip, or use the same
4194 JTAG-level ID for several largely-compatible chips, it may be more practical
4195 to ignore the version field than to update config files to handle all of
4196 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4197 @item @code{-ignore-bypass}
4198 @*Specify this to ignore the 'bypass' bit of the idcode. Some vendor put
4199 an invalid idcode regarding this bit. Specify this to ignore this bit and
4200 to not consider this tap in bypass mode.
4201 @item @code{-ircapture} @var{NUMBER}
4202 @*The bit pattern loaded by the TAP into the JTAG shift register
4203 on entry to the @sc{ircapture} state, such as 0x01.
4204 JTAG requires the two LSBs of this value to be 01.
4205 By default, @code{-ircapture} and @code{-irmask} are set
4206 up to verify that two-bit value. You may provide
4207 additional bits if you know them, or indicate that
4208 a TAP doesn't conform to the JTAG specification.
4209 @item @code{-irmask} @var{NUMBER}
4210 @*A mask used with @code{-ircapture}
4211 to verify that instruction scans work correctly.
4212 Such scans are not used by OpenOCD except to verify that
4213 there seems to be no problems with JTAG scan chain operations.
4214 @item @code{-ignore-syspwrupack}
4215 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4216 register during initial examination and when checking the sticky error bit.
4217 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4218 devices do not set the ack bit until sometime later.
4222 @section Other TAP commands
4224 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4225 Get the value of the IDCODE found in hardware.
4228 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4229 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4230 At this writing this TAP attribute
4231 mechanism is limited and used mostly for event handling.
4232 (It is not a direct analogue of the @code{cget}/@code{configure}
4233 mechanism for debugger targets.)
4234 See the next section for information about the available events.
4236 The @code{configure} subcommand assigns an event handler,
4237 a TCL string which is evaluated when the event is triggered.
4238 The @code{cget} subcommand returns that handler.
4245 OpenOCD includes two event mechanisms.
4246 The one presented here applies to all JTAG TAPs.
4247 The other applies to debugger targets,
4248 which are associated with certain TAPs.
4250 The TAP events currently defined are:
4253 @item @b{post-reset}
4254 @* The TAP has just completed a JTAG reset.
4255 The tap may still be in the JTAG @sc{reset} state.
4256 Handlers for these events might perform initialization sequences
4257 such as issuing TCK cycles, TMS sequences to ensure
4258 exit from the ARM SWD mode, and more.
4260 Because the scan chain has not yet been verified, handlers for these events
4261 @emph{should not issue commands which scan the JTAG IR or DR registers}
4262 of any particular target.
4263 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4265 @* The scan chain has been reset and verified.
4266 This handler may enable TAPs as needed.
4267 @item @b{tap-disable}
4268 @* The TAP needs to be disabled. This handler should
4269 implement @command{jtag tapdisable}
4270 by issuing the relevant JTAG commands.
4271 @item @b{tap-enable}
4272 @* The TAP needs to be enabled. This handler should
4273 implement @command{jtag tapenable}
4274 by issuing the relevant JTAG commands.
4277 If you need some action after each JTAG reset which isn't actually
4278 specific to any TAP (since you can't yet trust the scan chain's
4279 contents to be accurate), you might:
4282 jtag configure CHIP.jrc -event post-reset @{
4283 echo "JTAG Reset done"
4284 ... non-scan jtag operations to be done after reset
4289 @anchor{enablinganddisablingtaps}
4290 @section Enabling and Disabling TAPs
4291 @cindex JTAG Route Controller
4294 In some systems, a @dfn{JTAG Route Controller} (JRC)
4295 is used to enable and/or disable specific JTAG TAPs.
4296 Many ARM-based chips from Texas Instruments include
4297 an ``ICEPick'' module, which is a JRC.
4298 Such chips include DaVinci and OMAP3 processors.
4300 A given TAP may not be visible until the JRC has been
4301 told to link it into the scan chain; and if the JRC
4302 has been told to unlink that TAP, it will no longer
4304 Such routers address problems that JTAG ``bypass mode''
4308 @item The scan chain can only go as fast as its slowest TAP.
4309 @item Having many TAPs slows instruction scans, since all
4310 TAPs receive new instructions.
4311 @item TAPs in the scan chain must be powered up, which wastes
4312 power and prevents debugging some power management mechanisms.
4315 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4316 as implied by the existence of JTAG routers.
4317 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4318 does include a kind of JTAG router functionality.
4320 @c (a) currently the event handlers don't seem to be able to
4321 @c fail in a way that could lead to no-change-of-state.
4323 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4324 shown below, and is implemented using TAP event handlers.
4325 So for example, when defining a TAP for a CPU connected to
4326 a JTAG router, your @file{target.cfg} file
4327 should define TAP event handlers using
4328 code that looks something like this:
4331 jtag configure CHIP.cpu -event tap-enable @{
4332 ... jtag operations using CHIP.jrc
4334 jtag configure CHIP.cpu -event tap-disable @{
4335 ... jtag operations using CHIP.jrc
4339 Then you might want that CPU's TAP enabled almost all the time:
4342 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4345 Note how that particular setup event handler declaration
4346 uses quotes to evaluate @code{$CHIP} when the event is configured.
4347 Using brackets @{ @} would cause it to be evaluated later,
4348 at runtime, when it might have a different value.
4350 @deffn {Command} {jtag tapdisable} dotted.name
4351 If necessary, disables the tap
4352 by sending it a @option{tap-disable} event.
4353 Returns the string "1" if the tap
4354 specified by @var{dotted.name} is enabled,
4355 and "0" if it is disabled.
4358 @deffn {Command} {jtag tapenable} dotted.name
4359 If necessary, enables the tap
4360 by sending it a @option{tap-enable} event.
4361 Returns the string "1" if the tap
4362 specified by @var{dotted.name} is enabled,
4363 and "0" if it is disabled.
4366 @deffn {Command} {jtag tapisenabled} dotted.name
4367 Returns the string "1" if the tap
4368 specified by @var{dotted.name} is enabled,
4369 and "0" if it is disabled.
4372 Humans will find the @command{scan_chain} command more helpful
4373 for querying the state of the JTAG taps.
4377 @anchor{autoprobing}
4378 @section Autoprobing
4380 @cindex JTAG autoprobe
4382 TAP configuration is the first thing that needs to be done
4383 after interface and reset configuration. Sometimes it's
4384 hard finding out what TAPs exist, or how they are identified.
4385 Vendor documentation is not always easy to find and use.
4387 To help you get past such problems, OpenOCD has a limited
4388 @emph{autoprobing} ability to look at the scan chain, doing
4389 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4390 To use this mechanism, start the OpenOCD server with only data
4391 that configures your JTAG interface, and arranges to come up
4392 with a slow clock (many devices don't support fast JTAG clocks
4393 right when they come out of reset).
4395 For example, your @file{openocd.cfg} file might have:
4398 source [find interface/olimex-arm-usb-tiny-h.cfg]
4399 reset_config trst_and_srst
4403 When you start the server without any TAPs configured, it will
4404 attempt to autoconfigure the TAPs. There are two parts to this:
4407 @item @emph{TAP discovery} ...
4408 After a JTAG reset (sometimes a system reset may be needed too),
4409 each TAP's data registers will hold the contents of either the
4410 IDCODE or BYPASS register.
4411 If JTAG communication is working, OpenOCD will see each TAP,
4412 and report what @option{-expected-id} to use with it.
4413 @item @emph{IR Length discovery} ...
4414 Unfortunately JTAG does not provide a reliable way to find out
4415 the value of the @option{-irlen} parameter to use with a TAP
4417 If OpenOCD can discover the length of a TAP's instruction
4418 register, it will report it.
4419 Otherwise you may need to consult vendor documentation, such
4420 as chip data sheets or BSDL files.
4423 In many cases your board will have a simple scan chain with just
4424 a single device. Here's what OpenOCD reported with one board
4425 that's a bit more complex:
4429 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4430 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4431 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4432 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4433 AUTO auto0.tap - use "... -irlen 4"
4434 AUTO auto1.tap - use "... -irlen 4"
4435 AUTO auto2.tap - use "... -irlen 6"
4436 no gdb ports allocated as no target has been specified
4439 Given that information, you should be able to either find some existing
4440 config files to use, or create your own. If you create your own, you
4441 would configure from the bottom up: first a @file{target.cfg} file
4442 with these TAPs, any targets associated with them, and any on-chip
4443 resources; then a @file{board.cfg} with off-chip resources, clocking,
4446 @anchor{dapdeclaration}
4447 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4448 @cindex DAP declaration
4450 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4451 no longer implicitly created together with the target. It must be
4452 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4453 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4454 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4456 The @command{dap} command group supports the following sub-commands:
4459 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4460 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4461 @var{dotted.name}. This also creates a new command (@command{dap_name})
4462 which is used for various purposes including additional configuration.
4463 There can only be one DAP for each JTAG tap in the system.
4465 A DAP may also provide optional @var{configparams}:
4468 @item @code{-ignore-syspwrupack}
4469 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4470 register during initial examination and when checking the sticky error bit.
4471 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4472 devices do not set the ack bit until sometime later.
4474 @item @code{-dp-id} @var{number}
4475 @*Debug port identification number for SWD DPv2 multidrop.
4476 The @var{number} is written to bits 0..27 of DP TARGETSEL during DP selection.
4477 To find the id number of a single connected device read DP TARGETID:
4478 @code{device.dap dpreg 0x24}
4479 Use bits 0..27 of TARGETID.
4481 @item @code{-instance-id} @var{number}
4482 @*Instance identification number for SWD DPv2 multidrop.
4483 The @var{number} is written to bits 28..31 of DP TARGETSEL during DP selection.
4484 To find the instance number of a single connected device read DP DLPIDR:
4485 @code{device.dap dpreg 0x34}
4486 The instance number is in bits 28..31 of DLPIDR value.
4490 @deffn {Command} {dap names}
4491 This command returns a list of all registered DAP objects. It it useful mainly
4495 @deffn {Command} {dap info} [num]
4496 Displays the ROM table for MEM-AP @var{num},
4497 defaulting to the currently selected AP of the currently selected target.
4500 @deffn {Command} {dap init}
4501 Initialize all registered DAPs. This command is used internally
4502 during initialization. It can be issued at any time after the
4503 initialization, too.
4506 The following commands exist as subcommands of DAP instances:
4508 @deffn {Command} {$dap_name info} [num]
4509 Displays the ROM table for MEM-AP @var{num},
4510 defaulting to the currently selected AP.
4513 @deffn {Command} {$dap_name apid} [num]
4514 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4517 @anchor{DAP subcommand apreg}
4518 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4519 Displays content of a register @var{reg} from AP @var{ap_num}
4520 or set a new value @var{value}.
4521 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4524 @deffn {Command} {$dap_name apsel} [num]
4525 Select AP @var{num}, defaulting to 0.
4528 @deffn {Command} {$dap_name dpreg} reg [value]
4529 Displays the content of DP register at address @var{reg}, or set it to a new
4532 In case of SWD, @var{reg} is a value in packed format
4533 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4534 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4536 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4537 background activity by OpenOCD while you are operating at such low-level.
4540 @deffn {Command} {$dap_name baseaddr} [num]
4541 Displays debug base address from MEM-AP @var{num},
4542 defaulting to the currently selected AP.
4545 @deffn {Command} {$dap_name memaccess} [value]
4546 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4547 memory bus access [0-255], giving additional time to respond to reads.
4548 If @var{value} is defined, first assigns that.
4551 @deffn {Command} {$dap_name apcsw} [value [mask]]
4552 Displays or changes CSW bit pattern for MEM-AP transfers.
4554 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4555 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4556 and the result is written to the real CSW register. All bits except dynamically
4557 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4558 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4561 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4562 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4565 kx.dap apcsw 0x2000000
4568 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4569 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4570 and leaves the rest of the pattern intact. It configures memory access through
4571 DCache on Cortex-M7.
4573 set CSW_HPROT3_CACHEABLE [expr @{1 << 27@}]
4574 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4577 Another example clears SPROT bit and leaves the rest of pattern intact:
4579 set CSW_SPROT [expr @{1 << 30@}]
4580 samv.dap apcsw 0 $CSW_SPROT
4583 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4584 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4586 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4587 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4588 example with a proper dap name:
4590 xxx.dap apcsw default
4594 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4595 Set/get quirks mode for TI TMS450/TMS570 processors
4600 @node CPU Configuration
4601 @chapter CPU Configuration
4604 This chapter discusses how to set up GDB debug targets for CPUs.
4605 You can also access these targets without GDB
4606 (@pxref{Architecture and Core Commands},
4607 and @ref{targetstatehandling,,Target State handling}) and
4608 through various kinds of NAND and NOR flash commands.
4609 If you have multiple CPUs you can have multiple such targets.
4611 We'll start by looking at how to examine the targets you have,
4612 then look at how to add one more target and how to configure it.
4614 @section Target List
4615 @cindex target, current
4616 @cindex target, list
4618 All targets that have been set up are part of a list,
4619 where each member has a name.
4620 That name should normally be the same as the TAP name.
4621 You can display the list with the @command{targets}
4623 This display often has only one CPU; here's what it might
4624 look like with more than one:
4626 TargetName Type Endian TapName State
4627 -- ------------------ ---------- ------ ------------------ ------------
4628 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4629 1 MyTarget cortex_m little mychip.foo tap-disabled
4632 One member of that list is the @dfn{current target}, which
4633 is implicitly referenced by many commands.
4634 It's the one marked with a @code{*} near the target name.
4635 In particular, memory addresses often refer to the address
4636 space seen by that current target.
4637 Commands like @command{mdw} (memory display words)
4638 and @command{flash erase_address} (erase NOR flash blocks)
4639 are examples; and there are many more.
4641 Several commands let you examine the list of targets:
4643 @deffn {Command} {target current}
4644 Returns the name of the current target.
4647 @deffn {Command} {target names}
4648 Lists the names of all current targets in the list.
4650 foreach t [target names] @{
4651 puts [format "Target: %s\n" $t]
4656 @c yep, "target list" would have been better.
4657 @c plus maybe "target setdefault".
4659 @deffn {Command} {targets} [name]
4660 @emph{Note: the name of this command is plural. Other target
4661 command names are singular.}
4663 With no parameter, this command displays a table of all known
4664 targets in a user friendly form.
4666 With a parameter, this command sets the current target to
4667 the given target with the given @var{name}; this is
4668 only relevant on boards which have more than one target.
4671 @section Target CPU Types
4675 Each target has a @dfn{CPU type}, as shown in the output of
4676 the @command{targets} command. You need to specify that type
4677 when calling @command{target create}.
4678 The CPU type indicates more than just the instruction set.
4679 It also indicates how that instruction set is implemented,
4680 what kind of debug support it integrates,
4681 whether it has an MMU (and if so, what kind),
4682 what core-specific commands may be available
4683 (@pxref{Architecture and Core Commands}),
4686 It's easy to see what target types are supported,
4687 since there's a command to list them.
4689 @anchor{targettypes}
4690 @deffn {Command} {target types}
4691 Lists all supported target types.
4692 At this writing, the supported CPU types are:
4695 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4696 @item @code{arm11} -- this is a generation of ARMv6 cores.
4697 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4698 @item @code{arm7tdmi} -- this is an ARMv4 core.
4699 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4700 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4701 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4702 @item @code{arm966e} -- this is an ARMv5 core.
4703 @item @code{arm9tdmi} -- this is an ARMv4 core.
4704 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4705 (Support for this is preliminary and incomplete.)
4706 @item @code{avr32_ap7k} -- this an AVR32 core.
4707 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4708 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4709 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4710 @item @code{cortex_r4} -- this is an ARMv7-R core.
4711 @item @code{dragonite} -- resembles arm966e.
4712 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4713 (Support for this is still incomplete.)
4714 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4715 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4716 The current implementation supports eSi-32xx cores.
4717 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4718 @item @code{feroceon} -- resembles arm926.
4719 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4720 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4721 allowing access to physical memory addresses independently of CPU cores.
4722 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4723 a CPU, through which bus read and write cycles can be generated; it may be
4724 useful for working with non-CPU hardware behind an AP or during development of
4725 support for new CPUs.
4726 It's possible to connect a GDB client to this target (the GDB port has to be
4727 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4728 be emulated to comply to GDB remote protocol.
4729 @item @code{mips_m4k} -- a MIPS core.
4730 @item @code{mips_mips64} -- a MIPS64 core.
4731 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core.
4732 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core.
4733 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core.
4734 @item @code{or1k} -- this is an OpenRISC 1000 core.
4735 The current implementation supports three JTAG TAP cores:
4737 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4738 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4739 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4741 And two debug interfaces cores:
4743 @item @code{Advanced debug interface}
4744 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4745 @item @code{SoC Debug Interface}
4746 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4748 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4749 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4750 @item @code{riscv} -- a RISC-V core.
4751 @item @code{stm8} -- implements an STM8 core.
4752 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4753 @item @code{xscale} -- this is actually an architecture,
4754 not a CPU type. It is based on the ARMv5 architecture.
4758 To avoid being confused by the variety of ARM based cores, remember
4759 this key point: @emph{ARM is a technology licencing company}.
4760 (See: @url{http://www.arm.com}.)
4761 The CPU name used by OpenOCD will reflect the CPU design that was
4762 licensed, not a vendor brand which incorporates that design.
4763 Name prefixes like arm7, arm9, arm11, and cortex
4764 reflect design generations;
4765 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4766 reflect an architecture version implemented by a CPU design.
4768 @anchor{targetconfiguration}
4769 @section Target Configuration
4771 Before creating a ``target'', you must have added its TAP to the scan chain.
4772 When you've added that TAP, you will have a @code{dotted.name}
4773 which is used to set up the CPU support.
4774 The chip-specific configuration file will normally configure its CPU(s)
4775 right after it adds all of the chip's TAPs to the scan chain.
4777 Although you can set up a target in one step, it's often clearer if you
4778 use shorter commands and do it in two steps: create it, then configure
4780 All operations on the target after it's created will use a new
4781 command, created as part of target creation.
4783 The two main things to configure after target creation are
4784 a work area, which usually has target-specific defaults even
4785 if the board setup code overrides them later;
4786 and event handlers (@pxref{targetevents,,Target Events}), which tend
4787 to be much more board-specific.
4788 The key steps you use might look something like this
4791 dap create mychip.dap -chain-position mychip.cpu
4792 target create MyTarget cortex_m -dap mychip.dap
4793 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4794 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4795 MyTarget configure -event reset-init @{ myboard_reinit @}
4798 You should specify a working area if you can; typically it uses some
4800 Such a working area can speed up many things, including bulk
4801 writes to target memory;
4802 flash operations like checking to see if memory needs to be erased;
4803 GDB memory checksumming;
4807 On more complex chips, the work area can become
4808 inaccessible when application code
4809 (such as an operating system)
4810 enables or disables the MMU.
4811 For example, the particular MMU context used to access the virtual
4812 address will probably matter ... and that context might not have
4813 easy access to other addresses needed.
4814 At this writing, OpenOCD doesn't have much MMU intelligence.
4817 It's often very useful to define a @code{reset-init} event handler.
4818 For systems that are normally used with a boot loader,
4819 common tasks include updating clocks and initializing memory
4821 That may be needed to let you write the boot loader into flash,
4822 in order to ``de-brick'' your board; or to load programs into
4823 external DDR memory without having run the boot loader.
4825 @deffn {Config Command} {target create} target_name type configparams...
4826 This command creates a GDB debug target that refers to a specific JTAG tap.
4827 It enters that target into a list, and creates a new
4828 command (@command{@var{target_name}}) which is used for various
4829 purposes including additional configuration.
4832 @item @var{target_name} ... is the name of the debug target.
4833 By convention this should be the same as the @emph{dotted.name}
4834 of the TAP associated with this target, which must be specified here
4835 using the @code{-chain-position @var{dotted.name}} configparam.
4837 This name is also used to create the target object command,
4838 referred to here as @command{$target_name},
4839 and in other places the target needs to be identified.
4840 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4841 @item @var{configparams} ... all parameters accepted by
4842 @command{$target_name configure} are permitted.
4843 If the target is big-endian, set it here with @code{-endian big}.
4845 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4846 @code{-dap @var{dap_name}} here.
4850 @deffn {Command} {$target_name configure} configparams...
4851 The options accepted by this command may also be
4852 specified as parameters to @command{target create}.
4853 Their values can later be queried one at a time by
4854 using the @command{$target_name cget} command.
4856 @emph{Warning:} changing some of these after setup is dangerous.
4857 For example, moving a target from one TAP to another;
4858 and changing its endianness.
4862 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4863 used to access this target.
4865 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4866 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4867 create and manage DAP instances.
4869 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4870 whether the CPU uses big or little endian conventions
4872 @item @code{-event} @var{event_name} @var{event_body} --
4873 @xref{targetevents,,Target Events}.
4874 Note that this updates a list of named event handlers.
4875 Calling this twice with two different event names assigns
4876 two different handlers, but calling it twice with the
4877 same event name assigns only one handler.
4879 Current target is temporarily overridden to the event issuing target
4880 before handler code starts and switched back after handler is done.
4882 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4883 whether the work area gets backed up; by default,
4884 @emph{it is not backed up.}
4885 When possible, use a working_area that doesn't need to be backed up,
4886 since performing a backup slows down operations.
4887 For example, the beginning of an SRAM block is likely to
4888 be used by most build systems, but the end is often unused.
4890 @item @code{-work-area-size} @var{size} -- specify work are size,
4891 in bytes. The same size applies regardless of whether its physical
4892 or virtual address is being used.
4894 @item @code{-work-area-phys} @var{address} -- set the work area
4895 base @var{address} to be used when no MMU is active.
4897 @item @code{-work-area-virt} @var{address} -- set the work area
4898 base @var{address} to be used when an MMU is active.
4899 @emph{Do not specify a value for this except on targets with an MMU.}
4900 The value should normally correspond to a static mapping for the
4901 @code{-work-area-phys} address, set up by the current operating system.
4904 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4905 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4906 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4907 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
4908 @option{RIOT}, @option{Zephyr}
4909 @xref{gdbrtossupport,,RTOS Support}.
4911 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4912 scan and after a reset. A manual call to arp_examine is required to
4913 access the target for debugging.
4915 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4916 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4917 Use this option with systems where multiple, independent cores are connected
4918 to separate access ports of the same DAP.
4920 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4921 to the target. Currently, only the @code{aarch64} target makes use of this option,
4922 where it is a mandatory configuration for the target run control.
4923 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4924 for instruction on how to declare and control a CTI instance.
4926 @anchor{gdbportoverride}
4927 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4928 possible values of the parameter @var{number}, which are not only numeric values.
4929 Use this option to override, for this target only, the global parameter set with
4930 command @command{gdb_port}.
4931 @xref{gdb_port,,command gdb_port}.
4933 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
4934 number of GDB connections that are allowed for the target. Default is 1.
4935 A negative value for @var{number} means unlimited connections.
4936 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
4940 @section Other $target_name Commands
4941 @cindex object command
4943 The Tcl/Tk language has the concept of object commands,
4944 and OpenOCD adopts that same model for targets.
4946 A good Tk example is a on screen button.
4947 Once a button is created a button
4948 has a name (a path in Tk terms) and that name is useable as a first
4949 class command. For example in Tk, one can create a button and later
4950 configure it like this:
4954 button .foobar -background red -command @{ foo @}
4956 .foobar configure -foreground blue
4958 set x [.foobar cget -background]
4960 puts [format "The button is %s" $x]
4963 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4964 button, and its object commands are invoked the same way.
4967 str912.cpu mww 0x1234 0x42
4968 omap3530.cpu mww 0x5555 123
4971 The commands supported by OpenOCD target objects are:
4973 @deffn {Command} {$target_name arp_examine} @option{allow-defer}
4974 @deffnx {Command} {$target_name arp_halt}
4975 @deffnx {Command} {$target_name arp_poll}
4976 @deffnx {Command} {$target_name arp_reset}
4977 @deffnx {Command} {$target_name arp_waitstate}
4978 Internal OpenOCD scripts (most notably @file{startup.tcl})
4979 use these to deal with specific reset cases.
4980 They are not otherwise documented here.
4983 @deffn {Command} {$target_name array2mem} arrayname width address count
4984 @deffnx {Command} {$target_name mem2array} arrayname width address count
4985 These provide an efficient script-oriented interface to memory.
4986 The @code{array2mem} primitive writes bytes, halfwords, words
4987 or double-words; while @code{mem2array} reads them.
4988 In both cases, the TCL side uses an array, and
4989 the target side uses raw memory.
4991 The efficiency comes from enabling the use of
4992 bulk JTAG data transfer operations.
4993 The script orientation comes from working with data
4994 values that are packaged for use by TCL scripts;
4995 @command{mdw} type primitives only print data they retrieve,
4996 and neither store nor return those values.
4999 @item @var{arrayname} ... is the name of an array variable
5000 @item @var{width} ... is 8/16/32/64 - indicating the memory access size
5001 @item @var{address} ... is the target memory address
5002 @item @var{count} ... is the number of elements to process
5006 @deffn {Command} {$target_name set_reg} dict
5007 Set register values of the target.
5010 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
5013 For example, the following command sets the value 0 to the program counter (pc)
5014 register and 0x1000 to the stack pointer (sp) register:
5017 set_reg @{pc 0 sp 0x1000@}
5021 @deffn {Command} {$target_name get_reg} [-force] list
5022 Get register values from the target and return them as Tcl dictionary with pairs
5023 of register names and values.
5024 If option "-force" is set, the register values are read directly from the
5025 target, bypassing any caching.
5028 @item @var{list} ... List of register names
5031 For example, the following command retrieves the values from the program
5032 counter (pc) and stack pointer (sp) register:
5039 @deffn {Command} {$target_name cget} queryparm
5040 Each configuration parameter accepted by
5041 @command{$target_name configure}
5042 can be individually queried, to return its current value.
5043 The @var{queryparm} is a parameter name
5044 accepted by that command, such as @code{-work-area-phys}.
5045 There are a few special cases:
5048 @item @code{-event} @var{event_name} -- returns the handler for the
5049 event named @var{event_name}.
5050 This is a special case because setting a handler requires
5052 @item @code{-type} -- returns the target type.
5053 This is a special case because this is set using
5054 @command{target create} and can't be changed
5055 using @command{$target_name configure}.
5058 For example, if you wanted to summarize information about
5059 all the targets you might use something like this:
5062 foreach name [target names] @{
5063 set y [$name cget -endian]
5064 set z [$name cget -type]
5065 puts [format "Chip %d is %s, Endian: %s, type: %s" \
5071 @anchor{targetcurstate}
5072 @deffn {Command} {$target_name curstate}
5073 Displays the current target state:
5074 @code{debug-running},
5077 @code{running}, or @code{unknown}.
5078 (Also, @pxref{eventpolling,,Event Polling}.)
5081 @deffn {Command} {$target_name eventlist}
5082 Displays a table listing all event handlers
5083 currently associated with this target.
5084 @xref{targetevents,,Target Events}.
5087 @deffn {Command} {$target_name invoke-event} event_name
5088 Invokes the handler for the event named @var{event_name}.
5089 (This is primarily intended for use by OpenOCD framework
5090 code, for example by the reset code in @file{startup.tcl}.)
5093 @deffn {Command} {$target_name mdd} [phys] addr [count]
5094 @deffnx {Command} {$target_name mdw} [phys] addr [count]
5095 @deffnx {Command} {$target_name mdh} [phys] addr [count]
5096 @deffnx {Command} {$target_name mdb} [phys] addr [count]
5097 Display contents of address @var{addr}, as
5098 64-bit doublewords (@command{mdd}),
5099 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5100 or 8-bit bytes (@command{mdb}).
5101 When the current target has an MMU which is present and active,
5102 @var{addr} is interpreted as a virtual address.
5103 Otherwise, or if the optional @var{phys} flag is specified,
5104 @var{addr} is interpreted as a physical address.
5105 If @var{count} is specified, displays that many units.
5106 (If you want to manipulate the data instead of displaying it,
5107 see the @code{mem2array} primitives.)
5110 @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
5111 @deffnx {Command} {$target_name mww} [phys] addr word [count]
5112 @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
5113 @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
5114 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
5115 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
5116 at the specified address @var{addr}.
5117 When the current target has an MMU which is present and active,
5118 @var{addr} is interpreted as a virtual address.
5119 Otherwise, or if the optional @var{phys} flag is specified,
5120 @var{addr} is interpreted as a physical address.
5121 If @var{count} is specified, fills that many units of consecutive address.
5124 @anchor{targetevents}
5125 @section Target Events
5126 @cindex target events
5128 At various times, certain things can happen, or you want them to happen.
5131 @item What should happen when GDB connects? Should your target reset?
5132 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
5133 @item Is using SRST appropriate (and possible) on your system?
5134 Or instead of that, do you need to issue JTAG commands to trigger reset?
5135 SRST usually resets everything on the scan chain, which can be inappropriate.
5136 @item During reset, do you need to write to certain memory locations
5137 to set up system clocks or
5138 to reconfigure the SDRAM?
5139 How about configuring the watchdog timer, or other peripherals,
5140 to stop running while you hold the core stopped for debugging?
5143 All of the above items can be addressed by target event handlers.
5144 These are set up by @command{$target_name configure -event} or
5145 @command{target create ... -event}.
5147 The programmer's model matches the @code{-command} option used in Tcl/Tk
5148 buttons and events. The two examples below act the same, but one creates
5149 and invokes a small procedure while the other inlines it.
5152 proc my_init_proc @{ @} @{
5153 echo "Disabling watchdog..."
5154 mww 0xfffffd44 0x00008000
5156 mychip.cpu configure -event reset-init my_init_proc
5157 mychip.cpu configure -event reset-init @{
5158 echo "Disabling watchdog..."
5159 mww 0xfffffd44 0x00008000
5163 The following target events are defined:
5166 @item @b{debug-halted}
5167 @* The target has halted for debug reasons (i.e.: breakpoint)
5168 @item @b{debug-resumed}
5169 @* The target has resumed (i.e.: GDB said run)
5170 @item @b{early-halted}
5171 @* Occurs early in the halt process
5172 @item @b{examine-start}
5173 @* Before target examine is called.
5174 @item @b{examine-end}
5175 @* After target examine is called with no errors.
5176 @item @b{examine-fail}
5177 @* After target examine fails.
5178 @item @b{gdb-attach}
5179 @* When GDB connects. Issued before any GDB communication with the target
5180 starts. GDB expects the target is halted during attachment.
5181 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
5182 connect GDB to running target.
5183 The event can be also used to set up the target so it is possible to probe flash.
5184 Probing flash is necessary during GDB connect if you want to use
5185 @pxref{programmingusinggdb,,programming using GDB}.
5186 Another use of the flash memory map is for GDB to automatically choose
5187 hardware or software breakpoints depending on whether the breakpoint
5188 is in RAM or read only memory.
5189 Default is @code{halt}
5190 @item @b{gdb-detach}
5191 @* When GDB disconnects
5193 @* When the target has halted and GDB is not doing anything (see early halt)
5194 @item @b{gdb-flash-erase-start}
5195 @* Before the GDB flash process tries to erase the flash (default is
5197 @item @b{gdb-flash-erase-end}
5198 @* After the GDB flash process has finished erasing the flash
5199 @item @b{gdb-flash-write-start}
5200 @* Before GDB writes to the flash
5201 @item @b{gdb-flash-write-end}
5202 @* After GDB writes to the flash (default is @code{reset halt})
5204 @* Before the target steps, GDB is trying to start/resume the target
5206 @* The target has halted
5207 @item @b{reset-assert-pre}
5208 @* Issued as part of @command{reset} processing
5209 after @command{reset-start} was triggered
5210 but before either SRST alone is asserted on the scan chain,
5211 or @code{reset-assert} is triggered.
5212 @item @b{reset-assert}
5213 @* Issued as part of @command{reset} processing
5214 after @command{reset-assert-pre} was triggered.
5215 When such a handler is present, cores which support this event will use
5216 it instead of asserting SRST.
5217 This support is essential for debugging with JTAG interfaces which
5218 don't include an SRST line (JTAG doesn't require SRST), and for
5219 selective reset on scan chains that have multiple targets.
5220 @item @b{reset-assert-post}
5221 @* Issued as part of @command{reset} processing
5222 after @code{reset-assert} has been triggered.
5223 or the target asserted SRST on the entire scan chain.
5224 @item @b{reset-deassert-pre}
5225 @* Issued as part of @command{reset} processing
5226 after @code{reset-assert-post} has been triggered.
5227 @item @b{reset-deassert-post}
5228 @* Issued as part of @command{reset} processing
5229 after @code{reset-deassert-pre} has been triggered
5230 and (if the target is using it) after SRST has been
5231 released on the scan chain.
5233 @* Issued as the final step in @command{reset} processing.
5234 @item @b{reset-init}
5235 @* Used by @b{reset init} command for board-specific initialization.
5236 This event fires after @emph{reset-deassert-post}.
5238 This is where you would configure PLLs and clocking, set up DRAM so
5239 you can download programs that don't fit in on-chip SRAM, set up pin
5240 multiplexing, and so on.
5241 (You may be able to switch to a fast JTAG clock rate here, after
5242 the target clocks are fully set up.)
5243 @item @b{reset-start}
5244 @* Issued as the first step in @command{reset} processing
5245 before @command{reset-assert-pre} is called.
5247 This is the most robust place to use @command{jtag_rclk}
5248 or @command{adapter speed} to switch to a low JTAG clock rate,
5249 when reset disables PLLs needed to use a fast clock.
5250 @item @b{resume-start}
5251 @* Before any target is resumed
5252 @item @b{resume-end}
5253 @* After all targets have resumed
5255 @* Target has resumed
5256 @item @b{step-start}
5257 @* Before a target is single-stepped
5259 @* After single-step has completed
5260 @item @b{trace-config}
5261 @* After target hardware trace configuration was changed
5262 @item @b{semihosting-user-cmd-0x100}
5263 @* The target made a semihosting call with user-defined operation number 0x100
5264 @item @b{semihosting-user-cmd-0x101}
5265 @* The target made a semihosting call with user-defined operation number 0x101
5266 @item @b{semihosting-user-cmd-0x102}
5267 @* The target made a semihosting call with user-defined operation number 0x102
5268 @item @b{semihosting-user-cmd-0x103}
5269 @* The target made a semihosting call with user-defined operation number 0x103
5270 @item @b{semihosting-user-cmd-0x104}
5271 @* The target made a semihosting call with user-defined operation number 0x104
5272 @item @b{semihosting-user-cmd-0x105}
5273 @* The target made a semihosting call with user-defined operation number 0x105
5274 @item @b{semihosting-user-cmd-0x106}
5275 @* The target made a semihosting call with user-defined operation number 0x106
5276 @item @b{semihosting-user-cmd-0x107}
5277 @* The target made a semihosting call with user-defined operation number 0x107
5281 OpenOCD events are not supposed to be preempt by another event, but this
5282 is not enforced in current code. Only the target event @b{resumed} is
5283 executed with polling disabled; this avoids polling to trigger the event
5284 @b{halted}, reversing the logical order of execution of their handlers.
5285 Future versions of OpenOCD will prevent the event preemption and will
5286 disable the schedule of polling during the event execution. Do not rely
5287 on polling in any event handler; this means, don't expect the status of
5288 a core to change during the execution of the handler. The event handler
5289 will have to enable polling or use @command{$target_name arp_poll} to
5290 check if the core has changed status.
5293 @node Flash Commands
5294 @chapter Flash Commands
5296 OpenOCD has different commands for NOR and NAND flash;
5297 the ``flash'' command works with NOR flash, while
5298 the ``nand'' command works with NAND flash.
5299 This partially reflects different hardware technologies:
5300 NOR flash usually supports direct CPU instruction and data bus access,
5301 while data from a NAND flash must be copied to memory before it can be
5302 used. (SPI flash must also be copied to memory before use.)
5303 However, the documentation also uses ``flash'' as a generic term;
5304 for example, ``Put flash configuration in board-specific files''.
5308 @item Configure via the command @command{flash bank}
5309 @* Do this in a board-specific configuration file,
5310 passing parameters as needed by the driver.
5311 @item Operate on the flash via @command{flash subcommand}
5312 @* Often commands to manipulate the flash are typed by a human, or run
5313 via a script in some automated way. Common tasks include writing a
5314 boot loader, operating system, or other data.
5316 @* Flashing via GDB requires the flash be configured via ``flash
5317 bank'', and the GDB flash features be enabled.
5318 @xref{gdbconfiguration,,GDB Configuration}.
5321 Many CPUs have the ability to ``boot'' from the first flash bank.
5322 This means that misprogramming that bank can ``brick'' a system,
5323 so that it can't boot.
5324 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5325 board by (re)installing working boot firmware.
5327 @anchor{norconfiguration}
5328 @section Flash Configuration Commands
5329 @cindex flash configuration
5331 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5332 Configures a flash bank which provides persistent storage
5333 for addresses from @math{base} to @math{base + size - 1}.
5334 These banks will often be visible to GDB through the target's memory map.
5335 In some cases, configuring a flash bank will activate extra commands;
5336 see the driver-specific documentation.
5339 @item @var{name} ... may be used to reference the flash bank
5340 in other flash commands. A number is also available.
5341 @item @var{driver} ... identifies the controller driver
5342 associated with the flash bank being declared.
5343 This is usually @code{cfi} for external flash, or else
5344 the name of a microcontroller with embedded flash memory.
5345 @xref{flashdriverlist,,Flash Driver List}.
5346 @item @var{base} ... Base address of the flash chip.
5347 @item @var{size} ... Size of the chip, in bytes.
5348 For some drivers, this value is detected from the hardware.
5349 @item @var{chip_width} ... Width of the flash chip, in bytes;
5350 ignored for most microcontroller drivers.
5351 @item @var{bus_width} ... Width of the data bus used to access the
5352 chip, in bytes; ignored for most microcontroller drivers.
5353 @item @var{target} ... Names the target used to issue
5354 commands to the flash controller.
5355 @comment Actually, it's currently a controller-specific parameter...
5356 @item @var{driver_options} ... drivers may support, or require,
5357 additional parameters. See the driver-specific documentation
5358 for more information.
5361 This command is not available after OpenOCD initialization has completed.
5362 Use it in board specific configuration files, not interactively.
5366 @comment less confusing would be: "flash list" (like "nand list")
5367 @deffn {Command} {flash banks}
5368 Prints a one-line summary of each device that was
5369 declared using @command{flash bank}, numbered from zero.
5370 Note that this is the @emph{plural} form;
5371 the @emph{singular} form is a very different command.
5374 @deffn {Command} {flash list}
5375 Retrieves a list of associative arrays for each device that was
5376 declared using @command{flash bank}, numbered from zero.
5377 This returned list can be manipulated easily from within scripts.
5380 @deffn {Command} {flash probe} num
5381 Identify the flash, or validate the parameters of the configured flash. Operation
5382 depends on the flash type.
5383 The @var{num} parameter is a value shown by @command{flash banks}.
5384 Most flash commands will implicitly @emph{autoprobe} the bank;
5385 flash drivers can distinguish between probing and autoprobing,
5386 but most don't bother.
5389 @section Preparing a Target before Flash Programming
5391 The target device should be in well defined state before the flash programming
5394 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5395 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5396 until the programming session is finished.
5398 If you use @ref{programmingusinggdb,,Programming using GDB},
5399 the target is prepared automatically in the event gdb-flash-erase-start
5401 The jimtcl script @command{program} calls @command{reset init} explicitly.
5403 @section Erasing, Reading, Writing to Flash
5404 @cindex flash erasing
5405 @cindex flash reading
5406 @cindex flash writing
5407 @cindex flash programming
5408 @anchor{flashprogrammingcommands}
5410 One feature distinguishing NOR flash from NAND or serial flash technologies
5411 is that for read access, it acts exactly like any other addressable memory.
5412 This means you can use normal memory read commands like @command{mdw} or
5413 @command{dump_image} with it, with no special @command{flash} subcommands.
5414 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5416 Write access works differently. Flash memory normally needs to be erased
5417 before it's written. Erasing a sector turns all of its bits to ones, and
5418 writing can turn ones into zeroes. This is why there are special commands
5419 for interactive erasing and writing, and why GDB needs to know which parts
5420 of the address space hold NOR flash memory.
5423 Most of these erase and write commands leverage the fact that NOR flash
5424 chips consume target address space. They implicitly refer to the current
5425 JTAG target, and map from an address in that target's address space
5426 back to a flash bank.
5427 @comment In May 2009, those mappings may fail if any bank associated
5428 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5429 A few commands use abstract addressing based on bank and sector numbers,
5430 and don't depend on searching the current target and its address space.
5431 Avoid confusing the two command models.
5434 Some flash chips implement software protection against accidental writes,
5435 since such buggy writes could in some cases ``brick'' a system.
5436 For such systems, erasing and writing may require sector protection to be
5438 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5439 and AT91SAM7 on-chip flash.
5440 @xref{flashprotect,,flash protect}.
5442 @deffn {Command} {flash erase_sector} num first last
5443 Erase sectors in bank @var{num}, starting at sector @var{first}
5444 up to and including @var{last}.
5445 Sector numbering starts at 0.
5446 Providing a @var{last} sector of @option{last}
5447 specifies "to the end of the flash bank".
5448 The @var{num} parameter is a value shown by @command{flash banks}.
5451 @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
5452 Erase sectors starting at @var{address} for @var{length} bytes.
5453 Unless @option{pad} is specified, @math{address} must begin a
5454 flash sector, and @math{address + length - 1} must end a sector.
5455 Specifying @option{pad} erases extra data at the beginning and/or
5456 end of the specified region, as needed to erase only full sectors.
5457 The flash bank to use is inferred from the @var{address}, and
5458 the specified length must stay within that bank.
5459 As a special case, when @var{length} is zero and @var{address} is
5460 the start of the bank, the whole flash is erased.
5461 If @option{unlock} is specified, then the flash is unprotected
5462 before erase starts.
5465 @deffn {Command} {flash filld} address double-word length
5466 @deffnx {Command} {flash fillw} address word length
5467 @deffnx {Command} {flash fillh} address halfword length
5468 @deffnx {Command} {flash fillb} address byte length
5469 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5470 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5471 starting at @var{address} and continuing
5472 for @var{length} units (word/halfword/byte).
5473 No erasure is done before writing; when needed, that must be done
5474 before issuing this command.
5475 Writes are done in blocks of up to 1024 bytes, and each write is
5476 verified by reading back the data and comparing it to what was written.
5477 The flash bank to use is inferred from the @var{address} of
5478 each block, and the specified length must stay within that bank.
5480 @comment no current checks for errors if fill blocks touch multiple banks!
5482 @deffn {Command} {flash mdw} addr [count]
5483 @deffnx {Command} {flash mdh} addr [count]
5484 @deffnx {Command} {flash mdb} addr [count]
5485 Display contents of address @var{addr}, as
5486 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5487 or 8-bit bytes (@command{mdb}).
5488 If @var{count} is specified, displays that many units.
5489 Reads from flash using the flash driver, therefore it enables reading
5490 from a bank not mapped in target address space.
5491 The flash bank to use is inferred from the @var{address} of
5492 each block, and the specified length must stay within that bank.
5495 @deffn {Command} {flash write_bank} num filename [offset]
5496 Write the binary @file{filename} to flash bank @var{num},
5497 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5498 is omitted, start at the beginning of the flash bank.
5499 The @var{num} parameter is a value shown by @command{flash banks}.
5502 @deffn {Command} {flash read_bank} num filename [offset [length]]
5503 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5504 and write the contents to the binary @file{filename}. If @var{offset} is
5505 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5506 read the remaining bytes from the flash bank.
5507 The @var{num} parameter is a value shown by @command{flash banks}.
5510 @deffn {Command} {flash verify_bank} num filename [offset]
5511 Compare the contents of the binary file @var{filename} with the contents of the
5512 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5513 start at the beginning of the flash bank. Fail if the contents do not match.
5514 The @var{num} parameter is a value shown by @command{flash banks}.
5517 @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
5518 Write the image @file{filename} to the current target's flash bank(s).
5519 Only loadable sections from the image are written.
5520 A relocation @var{offset} may be specified, in which case it is added
5521 to the base address for each section in the image.
5522 The file [@var{type}] can be specified
5523 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5524 @option{elf} (ELF file), @option{s19} (Motorola s19).
5525 @option{mem}, or @option{builder}.
5526 The relevant flash sectors will be erased prior to programming
5527 if the @option{erase} parameter is given. If @option{unlock} is
5528 provided, then the flash banks are unlocked before erase and
5529 program. The flash bank to use is inferred from the address of
5533 Be careful using the @option{erase} flag when the flash is holding
5534 data you want to preserve.
5535 Portions of the flash outside those described in the image's
5536 sections might be erased with no notice.
5539 When a section of the image being written does not fill out all the
5540 sectors it uses, the unwritten parts of those sectors are necessarily
5541 also erased, because sectors can't be partially erased.
5543 Data stored in sector "holes" between image sections are also affected.
5544 For example, "@command{flash write_image erase ...}" of an image with
5545 one byte at the beginning of a flash bank and one byte at the end
5546 erases the entire bank -- not just the two sectors being written.
5548 Also, when flash protection is important, you must re-apply it after
5549 it has been removed by the @option{unlock} flag.
5554 @deffn {Command} {flash verify_image} filename [offset] [type]
5555 Verify the image @file{filename} to the current target's flash bank(s).
5556 Parameters follow the description of 'flash write_image'.
5557 In contrast to the 'verify_image' command, for banks with specific
5558 verify method, that one is used instead of the usual target's read
5559 memory methods. This is necessary for flash banks not readable by
5560 ordinary memory reads.
5561 This command gives only an overall good/bad result for each bank, not
5562 addresses of individual failed bytes as it's intended only as quick
5563 check for successful programming.
5566 @section Other Flash commands
5567 @cindex flash protection
5569 @deffn {Command} {flash erase_check} num
5570 Check erase state of sectors in flash bank @var{num},
5571 and display that status.
5572 The @var{num} parameter is a value shown by @command{flash banks}.
5575 @deffn {Command} {flash info} num [sectors]
5576 Print info about flash bank @var{num}, a list of protection blocks
5577 and their status. Use @option{sectors} to show a list of sectors instead.
5579 The @var{num} parameter is a value shown by @command{flash banks}.
5580 This command will first query the hardware, it does not print cached
5581 and possibly stale information.
5584 @anchor{flashprotect}
5585 @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
5586 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5587 in flash bank @var{num}, starting at protection block @var{first}
5588 and continuing up to and including @var{last}.
5589 Providing a @var{last} block of @option{last}
5590 specifies "to the end of the flash bank".
5591 The @var{num} parameter is a value shown by @command{flash banks}.
5592 The protection block is usually identical to a flash sector.
5593 Some devices may utilize a protection block distinct from flash sector.
5594 See @command{flash info} for a list of protection blocks.
5597 @deffn {Command} {flash padded_value} num value
5598 Sets the default value used for padding any image sections, This should
5599 normally match the flash bank erased value. If not specified by this
5600 command or the flash driver then it defaults to 0xff.
5604 @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
5605 This is a helper script that simplifies using OpenOCD as a standalone
5606 programmer. The only required parameter is @option{filename}, the others are optional.
5607 @xref{Flash Programming}.
5610 @anchor{flashdriverlist}
5611 @section Flash Driver List
5612 As noted above, the @command{flash bank} command requires a driver name,
5613 and allows driver-specific options and behaviors.
5614 Some drivers also activate driver-specific commands.
5616 @deffn {Flash Driver} {virtual}
5617 This is a special driver that maps a previously defined bank to another
5618 address. All bank settings will be copied from the master physical bank.
5620 The @var{virtual} driver defines one mandatory parameters,
5623 @item @var{master_bank} The bank that this virtual address refers to.
5626 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5627 the flash bank defined at address 0x1fc00000. Any command executed on
5628 the virtual banks is actually performed on the physical banks.
5630 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5631 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5632 $_TARGETNAME $_FLASHNAME
5633 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5634 $_TARGETNAME $_FLASHNAME
5638 @subsection External Flash
5640 @deffn {Flash Driver} {cfi}
5641 @cindex Common Flash Interface
5643 The ``Common Flash Interface'' (CFI) is the main standard for
5644 external NOR flash chips, each of which connects to a
5645 specific external chip select on the CPU.
5646 Frequently the first such chip is used to boot the system.
5647 Your board's @code{reset-init} handler might need to
5648 configure additional chip selects using other commands (like: @command{mww} to
5649 configure a bus and its timings), or
5650 perhaps configure a GPIO pin that controls the ``write protect'' pin
5652 The CFI driver can use a target-specific working area to significantly
5655 The CFI driver can accept the following optional parameters, in any order:
5658 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5659 like AM29LV010 and similar types.
5660 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5661 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5662 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5663 swapped when writing data values (i.e. not CFI commands).
5666 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5667 wide on a sixteen bit bus:
5670 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5671 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5674 To configure one bank of 32 MBytes
5675 built from two sixteen bit (two byte) wide parts wired in parallel
5676 to create a thirty-two bit (four byte) bus with doubled throughput:
5679 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5682 @c "cfi part_id" disabled
5685 @deffn {Flash Driver} {jtagspi}
5686 @cindex Generic JTAG2SPI driver
5690 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5691 SPI flash connected to them. To access this flash from the host, the device
5692 is first programmed with a special proxy bitstream that
5693 exposes the SPI flash on the device's JTAG interface. The flash can then be
5694 accessed through JTAG.
5696 Since signaling between JTAG and SPI is compatible, all that is required for
5697 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5698 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5699 a bitstream for several Xilinx FPGAs can be found in
5700 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5701 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5703 This flash bank driver requires a target on a JTAG tap and will access that
5704 tap directly. Since no support from the target is needed, the target can be a
5705 "testee" dummy. Since the target does not expose the flash memory
5706 mapping, target commands that would otherwise be expected to access the flash
5707 will not work. These include all @command{*_image} and
5708 @command{$target_name m*} commands as well as @command{program}. Equivalent
5709 functionality is available through the @command{flash write_bank},
5710 @command{flash read_bank}, and @command{flash verify_bank} commands.
5712 According to device size, 1- to 4-byte addresses are sent. However, some
5713 flash chips additionally have to be switched to 4-byte addresses by an extra
5717 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5718 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5719 @var{USER1} instruction.
5723 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5724 set _XILINX_USER1 0x02
5725 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5726 $_TARGETNAME $_XILINX_USER1
5729 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5730 Sets flash parameters: @var{name} human readable string, @var{total_size}
5731 size in bytes, @var{page_size} is write page size. @var{read_cmd} and @var{pprg_cmd}
5732 are commands for read and page program, respectively. @var{mass_erase_cmd},
5733 @var{sector_size} and @var{sector_erase_cmd} are optional.
5735 jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
5739 @deffn Command {jtagspi cmd} bank_id resp_num cmd_byte ...
5740 Sends command @var{cmd_byte} and at most 20 following bytes and reads
5741 @var{resp_num} bytes afterwards. E.g. for 'Enter 4-byte address mode'
5743 jtagspi cmd 0 0 0xB7
5747 @deffn Command {jtagspi always_4byte} bank_id [ on | off ]
5748 Some devices use 4-byte addresses for all commands except the legacy 0x03 read
5749 regardless of device size. This command controls the corresponding hack.
5753 @deffn {Flash Driver} {xcf}
5754 @cindex Xilinx Platform flash driver
5756 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5757 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5758 only difference is special registers controlling its FPGA specific behavior.
5759 They must be properly configured for successful FPGA loading using
5760 additional @var{xcf} driver command:
5762 @deffn {Command} {xcf ccb} <bank_id>
5763 command accepts additional parameters:
5765 @item @var{external|internal} ... selects clock source.
5766 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5767 @item @var{slave|master} ... selects slave of master mode for flash device.
5768 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5772 xcf ccb 0 external parallel slave 40
5774 All of them must be specified even if clock frequency is pointless
5775 in slave mode. If only bank id specified than command prints current
5776 CCB register value. Note: there is no need to write this register
5777 every time you erase/program data sectors because it stores in
5781 @deffn {Command} {xcf configure} <bank_id>
5782 Initiates FPGA loading procedure. Useful if your board has no "configure"
5789 Additional driver notes:
5791 @item Only single revision supported.
5792 @item Driver automatically detects need of bit reverse, but
5793 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5794 (Intel hex) file types supported.
5795 @item For additional info check xapp972.pdf and ug380.pdf.
5799 @deffn {Flash Driver} {lpcspifi}
5800 @cindex NXP SPI Flash Interface
5803 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5804 Flash Interface (SPIFI) peripheral that can drive and provide
5805 memory mapped access to external SPI flash devices.
5807 The lpcspifi driver initializes this interface and provides
5808 program and erase functionality for these serial flash devices.
5809 Use of this driver @b{requires} a working area of at least 1kB
5810 to be configured on the target device; more than this will
5811 significantly reduce flash programming times.
5813 The setup command only requires the @var{base} parameter. All
5814 other parameters are ignored, and the flash size and layout
5815 are configured by the driver.
5818 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5823 @deffn {Flash Driver} {stmsmi}
5824 @cindex STMicroelectronics Serial Memory Interface
5827 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5828 SPEAr MPU family) include a proprietary
5829 ``Serial Memory Interface'' (SMI) controller able to drive external
5831 Depending on specific device and board configuration, up to 4 external
5832 flash devices can be connected.
5834 SMI makes the flash content directly accessible in the CPU address
5835 space; each external device is mapped in a memory bank.
5836 CPU can directly read data, execute code and boot from SMI banks.
5837 Normal OpenOCD commands like @command{mdw} can be used to display
5840 The setup command only requires the @var{base} parameter in order
5841 to identify the memory bank.
5842 All other parameters are ignored. Additional information, like
5843 flash size, are detected automatically.
5846 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5851 @deffn {Flash Driver} {stmqspi}
5852 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
5856 Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
5857 (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
5858 controller able to drive one or even two (dual mode) external SPI flash devices.
5859 The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
5860 Currently only the regular command mode is supported, whereas the HyperFlash
5863 QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
5864 space; in case of dual mode both devices must be of the same type and are
5865 mapped in the same memory bank (even and odd addresses interleaved).
5866 CPU can directly read data, execute code (but not boot) from QuadSPI bank.
5868 The 'flash bank' command only requires the @var{base} parameter and the extra
5869 parameter @var{io_base} in order to identify the memory bank. Both are fixed
5870 by hardware, see datasheet or RM. All other parameters are ignored.
5872 The controller must be initialized after each reset and properly configured
5873 for memory-mapped read operation for the particular flash chip(s), for the full
5874 list of available register settings cf. the controller's RM. This setup is quite
5875 board specific (that's why booting from this memory is not possible). The
5876 flash driver infers all parameters from current controller register values when
5877 'flash probe @var{bank_id}' is executed.
5879 Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
5880 but only after proper controller initialization as described above. However,
5881 due to a silicon bug in some devices, attempting to access the very last word
5884 It is possible to use two (even different) flash chips alternatingly, if individual
5885 bank chip selects are available. For some package variants, this is not the case
5886 due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
5887 and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
5888 change, so the address spaces of both devices will overlap. In dual flash mode
5889 both chips must be identical regarding size and most other properties.
5891 Block or sector protection internal to the flash chip is not handled by this
5892 driver at all, but can be dealt with manually by the 'cmd' command, see below.
5893 The sector protection via 'flash protect' command etc. is completely internal to
5894 openocd, intended only to prevent accidental erase or overwrite and it does not
5895 persist across openocd invocations.
5897 OpenOCD contains a hardcoded list of flash devices with their properties,
5898 these are auto-detected. If a device is not included in this list, SFDP discovery
5899 is attempted. If this fails or gives inappropriate results, manual setting is
5900 required (see 'set' command).
5903 flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
5904 $_TARGETNAME 0xA0001000
5905 flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
5906 $_TARGETNAME 0xA0001400
5909 There are three specific commands
5910 @deffn {Command} {stmqspi mass_erase} bank_id
5911 Clears sector protections and performs a mass erase. Works only if there is no
5912 chip specific write protection engaged.
5915 @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5916 Set flash parameters: @var{name} human readable string, @var{total_size} size
5917 in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
5918 are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
5919 @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
5920 and @var{sector_erase_cmd} are optional.
5922 This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
5923 which don't support an id command.
5925 In dual mode parameters of both chips are set identically. The parameters refer to
5926 a single chip, so the whole bank gets twice the specified capacity etc.
5929 @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
5930 If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
5931 bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
5932 sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
5933 i.e. the total number of bytes (including cmd_byte) must be odd.
5935 If @var{resp_num} is not zero, cmd and at most four following data bytes are
5936 sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
5937 are read interleaved from both chips starting with chip 1. In this case
5938 @var{resp_num} must be even.
5940 Note the hardware dictated subtle difference of those two cases in dual-flash mode.
5942 To check basic communication settings, issue
5944 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
5945 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
5947 for single flash mode or
5949 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
5950 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
5952 for dual flash mode. This should return the status register contents.
5954 In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
5955 complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
5956 need a dummy address, e.g.
5958 stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
5960 should return the status register contents.
5966 @deffn {Flash Driver} {mrvlqspi}
5967 This driver supports QSPI flash controller of Marvell's Wireless
5968 Microcontroller platform.
5970 The flash size is autodetected based on the table of known JEDEC IDs
5971 hardcoded in the OpenOCD sources.
5974 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5979 @deffn {Flash Driver} {ath79}
5980 @cindex Atheros ath79 SPI driver
5982 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5984 On reset a SPI flash connected to the first chip select (CS0) is made
5985 directly read-accessible in the CPU address space (up to 16MBytes)
5986 and is usually used to store the bootloader and operating system.
5987 Normal OpenOCD commands like @command{mdw} can be used to display
5988 the flash content while it is in memory-mapped mode (only the first
5989 4MBytes are accessible without additional configuration on reset).
5991 The setup command only requires the @var{base} parameter in order
5992 to identify the memory bank. The actual value for the base address
5993 is not otherwise used by the driver. However the mapping is passed
5994 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5995 address should be the actual memory mapped base address. For unmapped
5996 chipselects (CS1 and CS2) care should be taken to use a base address
5997 that does not overlap with real memory regions.
5998 Additional information, like flash size, are detected automatically.
5999 An optional additional parameter sets the chipselect for the bank,
6000 with the default CS0.
6001 CS1 and CS2 require additional GPIO setup before they can be used
6002 since the alternate function must be enabled on the GPIO pin
6003 CS1/CS2 is routed to on the given SoC.
6006 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
6008 # When using multiple chipselects the base should be different
6009 # for each, otherwise the write_image command is not able to
6010 # distinguish the banks.
6011 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
6012 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
6013 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
6018 @deffn {Flash Driver} {fespi}
6019 @cindex Freedom E SPI
6022 SiFive's Freedom E SPI controller, used in HiFive and other boards.
6025 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
6029 @subsection Internal Flash (Microcontrollers)
6031 @deffn {Flash Driver} {aduc702x}
6032 The ADUC702x analog microcontrollers from Analog Devices
6033 include internal flash and use ARM7TDMI cores.
6034 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
6035 The setup command only requires the @var{target} argument
6036 since all devices in this family have the same memory layout.
6039 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
6043 @deffn {Flash Driver} {ambiqmicro}
6046 All members of the Apollo microcontroller family from
6047 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
6048 The host connects over USB to an FTDI interface that communicates
6049 with the target using SWD.
6051 The @var{ambiqmicro} driver reads the Chip Information Register detect
6052 the device class of the MCU.
6053 The Flash and SRAM sizes directly follow device class, and are used
6054 to set up the flash banks.
6055 If this fails, the driver will use default values set to the minimum
6056 sizes of an Apollo chip.
6058 All Apollo chips have two flash banks of the same size.
6059 In all cases the first flash bank starts at location 0,
6060 and the second bank starts after the first.
6064 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
6065 # Flash bank 1 - same size as bank0, starts after bank 0.
6066 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
6070 Flash is programmed using custom entry points into the bootloader.
6071 This is the only way to program the flash as no flash control registers
6072 are available to the user.
6074 The @var{ambiqmicro} driver adds some additional commands:
6076 @deffn {Command} {ambiqmicro mass_erase} <bank>
6079 @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
6082 @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
6083 Program OTP is a one time operation to create write protected flash.
6084 The user writes sectors to SRAM starting at 0x10000010.
6085 Program OTP will write these sectors from SRAM to flash, and write protect
6091 @deffn {Flash Driver} {at91samd}
6093 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
6094 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
6096 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
6098 The devices have one flash bank:
6101 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
6104 @deffn {Command} {at91samd chip-erase}
6105 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6106 used to erase a chip back to its factory state and does not require the
6107 processor to be halted.
6110 @deffn {Command} {at91samd set-security}
6111 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
6112 to the Flash and can only be undone by using the chip-erase command which
6113 erases the Flash contents and turns off the security bit. Warning: at this
6114 time, openocd will not be able to communicate with a secured chip and it is
6115 therefore not possible to chip-erase it without using another tool.
6118 at91samd set-security enable
6122 @deffn {Command} {at91samd eeprom}
6123 Shows or sets the EEPROM emulation size configuration, stored in the User Row
6124 of the Flash. When setting, the EEPROM size must be specified in bytes and it
6125 must be one of the permitted sizes according to the datasheet. Settings are
6126 written immediately but only take effect on MCU reset. EEPROM emulation
6127 requires additional firmware support and the minimum EEPROM size may not be
6128 the same as the minimum that the hardware supports. Set the EEPROM size to 0
6129 in order to disable this feature.
6133 at91samd eeprom 1024
6137 @deffn {Command} {at91samd bootloader}
6138 Shows or sets the bootloader size configuration, stored in the User Row of the
6139 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6140 must be specified in bytes and it must be one of the permitted sizes according
6141 to the datasheet. Settings are written immediately but only take effect on
6142 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
6146 at91samd bootloader 16384
6150 @deffn {Command} {at91samd dsu_reset_deassert}
6151 This command releases internal reset held by DSU
6152 and prepares reset vector catch in case of reset halt.
6153 Command is used internally in event reset-deassert-post.
6156 @deffn {Command} {at91samd nvmuserrow}
6157 Writes or reads the entire 64 bit wide NVM user row register which is located at
6158 0x804000. This register includes various fuses lock-bits and factory calibration
6159 data. Reading the register is done by invoking this command without any
6160 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
6161 is the register value to be written and the second one is an optional changemask.
6162 Every bit which value in changemask is 0 will stay unchanged. The lock- and
6163 reserved-bits are masked out and cannot be changed.
6167 >at91samd nvmuserrow
6168 NVMUSERROW: 0xFFFFFC5DD8E0C788
6169 # Write 0xFFFFFC5DD8E0C788 to user row
6170 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
6171 # Write 0x12300 to user row but leave other bits and low
6173 >at91samd nvmuserrow 0x12345 0xFFF00
6180 @deffn {Flash Driver} {at91sam3}
6182 All members of the AT91SAM3 microcontroller family from
6183 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
6184 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
6185 that the driver was orginaly developed and tested using the
6186 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
6187 the family was cribbed from the data sheet. @emph{Note to future
6188 readers/updaters: Please remove this worrisome comment after other
6189 chips are confirmed.}
6191 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
6192 have one flash bank. In all cases the flash banks are at
6193 the following fixed locations:
6196 # Flash bank 0 - all chips
6197 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
6198 # Flash bank 1 - only 256K chips
6199 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
6202 Internally, the AT91SAM3 flash memory is organized as follows.
6203 Unlike the AT91SAM7 chips, these are not used as parameters
6204 to the @command{flash bank} command:
6207 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
6208 @item @emph{Bank Size:} 128K/64K Per flash bank
6209 @item @emph{Sectors:} 16 or 8 per bank
6210 @item @emph{SectorSize:} 8K Per Sector
6211 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
6214 The AT91SAM3 driver adds some additional commands:
6216 @deffn {Command} {at91sam3 gpnvm}
6217 @deffnx {Command} {at91sam3 gpnvm clear} number
6218 @deffnx {Command} {at91sam3 gpnvm set} number
6219 @deffnx {Command} {at91sam3 gpnvm show} [@option{all}|number]
6220 With no parameters, @command{show} or @command{show all},
6221 shows the status of all GPNVM bits.
6222 With @command{show} @var{number}, displays that bit.
6224 With @command{set} @var{number} or @command{clear} @var{number},
6225 modifies that GPNVM bit.
6228 @deffn {Command} {at91sam3 info}
6229 This command attempts to display information about the AT91SAM3
6230 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
6231 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
6232 document id: doc6430A] and decodes the values. @emph{Second} it reads the
6233 various clock configuration registers and attempts to display how it
6234 believes the chip is configured. By default, the SLOWCLK is assumed to
6235 be 32768 Hz, see the command @command{at91sam3 slowclk}.
6238 @deffn {Command} {at91sam3 slowclk} [value]
6239 This command shows/sets the slow clock frequency used in the
6240 @command{at91sam3 info} command calculations above.
6244 @deffn {Flash Driver} {at91sam4}
6246 All members of the AT91SAM4 microcontroller family from
6247 Atmel include internal flash and use ARM's Cortex-M4 core.
6248 This driver uses the same command names/syntax as @xref{at91sam3}.
6251 @deffn {Flash Driver} {at91sam4l}
6253 All members of the AT91SAM4L microcontroller family from
6254 Atmel include internal flash and use ARM's Cortex-M4 core.
6255 This driver uses the same command names/syntax as @xref{at91sam3}.
6257 The AT91SAM4L driver adds some additional commands:
6258 @deffn {Command} {at91sam4l smap_reset_deassert}
6259 This command releases internal reset held by SMAP
6260 and prepares reset vector catch in case of reset halt.
6261 Command is used internally in event reset-deassert-post.
6266 @deffn {Flash Driver} {atsame5}
6268 All members of the SAM E54, E53, E51 and D51 microcontroller
6269 families from Microchip (former Atmel) include internal flash
6270 and use ARM's Cortex-M4 core.
6272 The devices have two ECC flash banks with a swapping feature.
6273 This driver handles both banks together as it were one.
6274 Bank swapping is not supported yet.
6277 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
6280 @deffn {Command} {atsame5 bootloader}
6281 Shows or sets the bootloader size configuration, stored in the User Page of the
6282 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6283 must be specified in bytes. The nearest bigger protection size is used.
6284 Settings are written immediately but only take effect on MCU reset.
6285 Setting the bootloader size to 0 disables bootloader protection.
6289 atsame5 bootloader 16384
6293 @deffn {Command} {atsame5 chip-erase}
6294 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6295 used to erase a chip back to its factory state and does not require the
6296 processor to be halted.
6299 @deffn {Command} {atsame5 dsu_reset_deassert}
6300 This command releases internal reset held by DSU
6301 and prepares reset vector catch in case of reset halt.
6302 Command is used internally in event reset-deassert-post.
6305 @deffn {Command} {atsame5 userpage}
6306 Writes or reads the first 64 bits of NVM User Page which is located at
6307 0x804000. This field includes various fuses.
6308 Reading is done by invoking this command without any arguments.
6309 Writing is possible by giving 1 or 2 hex values. The first argument
6310 is the value to be written and the second one is an optional bit mask
6311 (a zero bit in the mask means the bit stays unchanged).
6312 The reserved fields are always masked out and cannot be changed.
6317 USER PAGE: 0xAEECFF80FE9A9239
6319 >atsame5 userpage 0xAEECFF80FE9A9239
6320 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
6321 # bits unchanged (setup SmartEEPROM of virtual size 8192
6323 >atsame5 userpage 0x4200000000 0x7f00000000
6329 @deffn {Flash Driver} {atsamv}
6331 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
6332 Atmel include internal flash and use ARM's Cortex-M7 core.
6333 This driver uses the same command names/syntax as @xref{at91sam3}.
6336 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
6339 @deffn {Command} {atsamv gpnvm} [@option{show} [@option{all}|number]]
6340 @deffnx {Command} {atsamv gpnvm} (@option{clr}|@option{set}) number
6341 With no parameters, @option{show} or @option{show all},
6342 shows the status of all GPNVM bits.
6343 With @option{show} @var{number}, displays that bit.
6345 With @option{set} @var{number} or @option{clear} @var{number},
6346 modifies that GPNVM bit.
6351 @deffn {Flash Driver} {at91sam7}
6352 All members of the AT91SAM7 microcontroller family from Atmel include
6353 internal flash and use ARM7TDMI cores. The driver automatically
6354 recognizes a number of these chips using the chip identification
6355 register, and autoconfigures itself.
6358 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
6361 For chips which are not recognized by the controller driver, you must
6362 provide additional parameters in the following order:
6365 @item @var{chip_model} ... label used with @command{flash info}
6367 @item @var{sectors_per_bank}
6368 @item @var{pages_per_sector}
6369 @item @var{pages_size}
6370 @item @var{num_nvm_bits}
6371 @item @var{freq_khz} ... required if an external clock is provided,
6372 optional (but recommended) when the oscillator frequency is known
6375 It is recommended that you provide zeroes for all of those values
6376 except the clock frequency, so that everything except that frequency
6377 will be autoconfigured.
6378 Knowing the frequency helps ensure correct timings for flash access.
6380 The flash controller handles erases automatically on a page (128/256 byte)
6381 basis, so explicit erase commands are not necessary for flash programming.
6382 However, there is an ``EraseAll`` command that can erase an entire flash
6383 plane (of up to 256KB), and it will be used automatically when you issue
6384 @command{flash erase_sector} or @command{flash erase_address} commands.
6386 @deffn {Command} {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
6387 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
6388 bit for the processor. Each processor has a number of such bits,
6389 used for controlling features such as brownout detection (so they
6390 are not truly general purpose).
6392 This assumes that the first flash bank (number 0) is associated with
6393 the appropriate at91sam7 target.
6398 @deffn {Flash Driver} {avr}
6399 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
6400 @emph{The current implementation is incomplete.}
6401 @comment - defines mass_erase ... pointless given flash_erase_address
6404 @deffn {Flash Driver} {bluenrg-x}
6405 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
6406 The driver automatically recognizes these chips using
6407 the chip identification registers, and autoconfigures itself.
6410 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
6413 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
6414 each single sector one by one.
6417 flash erase_sector 0 0 last # It will perform a mass erase
6420 Triggering a mass erase is also useful when users want to disable readout protection.
6423 @deffn {Flash Driver} {cc26xx}
6424 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
6425 Instruments include internal flash. The cc26xx flash driver supports both the
6426 CC13xx and CC26xx family of devices. The driver automatically recognizes the
6427 specific version's flash parameters and autoconfigures itself. The flash bank
6428 starts at address 0.
6431 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
6435 @deffn {Flash Driver} {cc3220sf}
6436 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
6437 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
6438 supports the internal flash. The serial flash on SimpleLink boards is
6439 programmed via the bootloader over a UART connection. Security features of
6440 the CC3220SF may erase the internal flash during power on reset. Refer to
6441 documentation at @url{www.ti.com/cc3220sf} for details on security features
6442 and programming the serial flash.
6445 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
6449 @deffn {Flash Driver} {efm32}
6450 All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs)
6451 include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically
6452 recognizes a number of these chips using the chip identification register, and
6453 autoconfigures itself.
6455 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
6457 It supports writing to the user data page, as well as the portion of the lockbits page
6458 past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs
6459 bootloader/AppLoader system for encryption keys. Setting protection on these pages is
6460 currently not supported.
6462 flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
6463 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
6466 A special feature of efm32 controllers is that it is possible to completely disable the
6467 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
6468 this via the following command:
6472 The @var{num} parameter is a value shown by @command{flash banks}.
6473 Note that in order for this command to take effect, the target needs to be reset.
6474 @emph{The current implementation is incomplete. Unprotecting flash pages is not
6478 @deffn {Flash Driver} {esirisc}
6479 Members of the eSi-RISC family may optionally include internal flash programmed
6480 via the eSi-TSMC Flash interface. Additional parameters are required to
6481 configure the driver: @option{cfg_address} is the base address of the
6482 configuration register interface, @option{clock_hz} is the expected clock
6483 frequency, and @option{wait_states} is the number of configured read wait states.
6486 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6487 $_TARGETNAME cfg_address clock_hz wait_states
6490 @deffn {Command} {esirisc flash mass_erase} bank_id
6491 Erase all pages in data memory for the bank identified by @option{bank_id}.
6494 @deffn {Command} {esirisc flash ref_erase} bank_id
6495 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6496 is an uncommon operation.}
6500 @deffn {Flash Driver} {fm3}
6501 All members of the FM3 microcontroller family from Fujitsu
6502 include internal flash and use ARM Cortex-M3 cores.
6503 The @var{fm3} driver uses the @var{target} parameter to select the
6504 correct bank config, it can currently be one of the following:
6505 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6506 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6509 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6513 @deffn {Flash Driver} {fm4}
6514 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6515 include internal flash and use ARM Cortex-M4 cores.
6516 The @var{fm4} driver uses a @var{family} parameter to select the
6517 correct bank config, it can currently be one of the following:
6518 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6519 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6520 with @code{x} treated as wildcard and otherwise case (and any trailing
6521 characters) ignored.
6524 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6525 $_TARGETNAME S6E2CCAJ0A
6526 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6527 $_TARGETNAME S6E2CCAJ0A
6529 @emph{The current implementation is incomplete. Protection is not supported,
6530 nor is Chip Erase (only Sector Erase is implemented).}
6533 @deffn {Flash Driver} {kinetis}
6535 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
6536 from NXP (former Freescale) include
6537 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
6538 recognizes flash size and a number of flash banks (1-4) using the chip
6539 identification register, and autoconfigures itself.
6540 Use kinetis_ke driver for KE0x and KEAx devices.
6542 The @var{kinetis} driver defines option:
6544 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
6548 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6551 @deffn {Config Command} {kinetis create_banks}
6552 Configuration command enables automatic creation of additional flash banks
6553 based on real flash layout of device. Banks are created during device probe.
6554 Use 'flash probe 0' to force probe.
6557 @deffn {Command} {kinetis fcf_source} [protection|write]
6558 Select what source is used when writing to a Flash Configuration Field.
6559 @option{protection} mode builds FCF content from protection bits previously
6560 set by 'flash protect' command.
6561 This mode is default. MCU is protected from unwanted locking by immediate
6562 writing FCF after erase of relevant sector.
6563 @option{write} mode enables direct write to FCF.
6564 Protection cannot be set by 'flash protect' command. FCF is written along
6565 with the rest of a flash image.
6566 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6569 @deffn {Command} {kinetis fopt} [num]
6570 Set value to write to FOPT byte of Flash Configuration Field.
6571 Used in kinetis 'fcf_source protection' mode only.
6574 @deffn {Command} {kinetis mdm check_security}
6575 Checks status of device security lock. Used internally in examine-end
6576 and examine-fail event.
6579 @deffn {Command} {kinetis mdm halt}
6580 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6581 loop when connecting to an unsecured target.
6584 @deffn {Command} {kinetis mdm mass_erase}
6585 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6586 back to its factory state, removing security. It does not require the processor
6587 to be halted, however the target will remain in a halted state after this
6591 @deffn {Command} {kinetis nvm_partition}
6592 For FlexNVM devices only (KxxDX and KxxFX).
6593 Command shows or sets data flash or EEPROM backup size in kilobytes,
6594 sets two EEPROM blocks sizes in bytes and enables/disables loading
6595 of EEPROM contents to FlexRAM during reset.
6597 For details see device reference manual, Flash Memory Module,
6598 Program Partition command.
6600 Setting is possible only once after mass_erase.
6601 Reset the device after partition setting.
6603 Show partition size:
6605 kinetis nvm_partition info
6608 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6609 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6611 kinetis nvm_partition dataflash 32 512 1536 on
6614 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6615 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6617 kinetis nvm_partition eebkp 16 1024 1024 off
6621 @deffn {Command} {kinetis mdm reset}
6622 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6623 RESET pin, which can be used to reset other hardware on board.
6626 @deffn {Command} {kinetis disable_wdog}
6627 For Kx devices only (KLx has different COP watchdog, it is not supported).
6628 Command disables watchdog timer.
6632 @deffn {Flash Driver} {kinetis_ke}
6634 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6635 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6636 the KE0x sub-family using the chip identification register, and
6637 autoconfigures itself.
6638 Use kinetis (not kinetis_ke) driver for KE1x devices.
6641 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6644 @deffn {Command} {kinetis_ke mdm check_security}
6645 Checks status of device security lock. Used internally in examine-end event.
6648 @deffn {Command} {kinetis_ke mdm mass_erase}
6649 Issues a complete Flash erase via the MDM-AP.
6650 This can be used to erase a chip back to its factory state.
6651 Command removes security lock from a device (use of SRST highly recommended).
6652 It does not require the processor to be halted.
6655 @deffn {Command} {kinetis_ke disable_wdog}
6656 Command disables watchdog timer.
6660 @deffn {Flash Driver} {lpc2000}
6661 This is the driver to support internal flash of all members of the
6662 LPC11(x)00 and LPC1300 microcontroller families and most members of
6663 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6664 LPC8Nxx and NHS31xx microcontroller families from NXP.
6667 There are LPC2000 devices which are not supported by the @var{lpc2000}
6669 The LPC2888 is supported by the @var{lpc288x} driver.
6670 The LPC29xx family is supported by the @var{lpc2900} driver.
6673 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6674 which must appear in the following order:
6677 @item @var{variant} ... required, may be
6678 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6679 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6680 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6681 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6683 @option{lpc800} (LPC8xx)
6684 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6685 @option{lpc1500} (LPC15xx)
6686 @option{lpc54100} (LPC541xx)
6687 @option{lpc4000} (LPC40xx)
6688 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6689 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6690 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6691 at which the core is running
6692 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6693 telling the driver to calculate a valid checksum for the exception vector table.
6695 If you don't provide @option{calc_checksum} when you're writing the vector
6696 table, the boot ROM will almost certainly ignore your flash image.
6697 However, if you do provide it,
6698 with most tool chains @command{verify_image} will fail.
6700 @item @option{iap_entry} ... optional telling the driver to use a different
6701 ROM IAP entry point.
6704 LPC flashes don't require the chip and bus width to be specified.
6707 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6708 lpc2000_v2 14765 calc_checksum
6711 @deffn {Command} {lpc2000 part_id} bank
6712 Displays the four byte part identifier associated with
6713 the specified flash @var{bank}.
6717 @deffn {Flash Driver} {lpc288x}
6718 The LPC2888 microcontroller from NXP needs slightly different flash
6719 support from its lpc2000 siblings.
6720 The @var{lpc288x} driver defines one mandatory parameter,
6721 the programming clock rate in Hz.
6722 LPC flashes don't require the chip and bus width to be specified.
6725 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6729 @deffn {Flash Driver} {lpc2900}
6730 This driver supports the LPC29xx ARM968E based microcontroller family
6733 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6734 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6735 sector layout are auto-configured by the driver.
6736 The driver has one additional mandatory parameter: The CPU clock rate
6737 (in kHz) at the time the flash operations will take place. Most of the time this
6738 will not be the crystal frequency, but a higher PLL frequency. The
6739 @code{reset-init} event handler in the board script is usually the place where
6742 The driver rejects flashless devices (currently the LPC2930).
6744 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6745 It must be handled much more like NAND flash memory, and will therefore be
6746 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6748 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6749 sector needs to be erased or programmed, it is automatically unprotected.
6750 What is shown as protection status in the @code{flash info} command, is
6751 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6752 sector from ever being erased or programmed again. As this is an irreversible
6753 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6754 and not by the standard @code{flash protect} command.
6756 Example for a 125 MHz clock frequency:
6758 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6761 Some @code{lpc2900}-specific commands are defined. In the following command list,
6762 the @var{bank} parameter is the bank number as obtained by the
6763 @code{flash banks} command.
6765 @deffn {Command} {lpc2900 signature} bank
6766 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6767 content. This is a hardware feature of the flash block, hence the calculation is
6768 very fast. You may use this to verify the content of a programmed device against
6773 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6777 @deffn {Command} {lpc2900 read_custom} bank filename
6778 Reads the 912 bytes of customer information from the flash index sector, and
6779 saves it to a file in binary format.
6782 lpc2900 read_custom 0 /path_to/customer_info.bin
6786 The index sector of the flash is a @emph{write-only} sector. It cannot be
6787 erased! In order to guard against unintentional write access, all following
6788 commands need to be preceded by a successful call to the @code{password}
6791 @deffn {Command} {lpc2900 password} bank password
6792 You need to use this command right before each of the following commands:
6793 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6794 @code{lpc2900 secure_jtag}.
6796 The password string is fixed to "I_know_what_I_am_doing".
6799 lpc2900 password 0 I_know_what_I_am_doing
6800 Potentially dangerous operation allowed in next command!
6804 @deffn {Command} {lpc2900 write_custom} bank filename type
6805 Writes the content of the file into the customer info space of the flash index
6806 sector. The filetype can be specified with the @var{type} field. Possible values
6807 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6808 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6809 contain a single section, and the contained data length must be exactly
6811 @quotation Attention
6812 This cannot be reverted! Be careful!
6816 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6820 @deffn {Command} {lpc2900 secure_sector} bank first last
6821 Secures the sector range from @var{first} to @var{last} (including) against
6822 further program and erase operations. The sector security will be effective
6823 after the next power cycle.
6824 @quotation Attention
6825 This cannot be reverted! Be careful!
6827 Secured sectors appear as @emph{protected} in the @code{flash info} command.
6830 lpc2900 secure_sector 0 1 1
6832 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
6833 # 0: 0x00000000 (0x2000 8kB) not protected
6834 # 1: 0x00002000 (0x2000 8kB) protected
6835 # 2: 0x00004000 (0x2000 8kB) not protected
6839 @deffn {Command} {lpc2900 secure_jtag} bank
6840 Irreversibly disable the JTAG port. The new JTAG security setting will be
6841 effective after the next power cycle.
6842 @quotation Attention
6843 This cannot be reverted! Be careful!
6847 lpc2900 secure_jtag 0
6852 @deffn {Flash Driver} {mdr}
6853 This drivers handles the integrated NOR flash on Milandr Cortex-M
6854 based controllers. A known limitation is that the Info memory can't be
6855 read or verified as it's not memory mapped.
6858 flash bank <name> mdr <base> <size> \
6859 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
6863 @item @var{type} - 0 for main memory, 1 for info memory
6864 @item @var{page_count} - total number of pages
6865 @item @var{sec_count} - number of sector per page count
6870 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
6871 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
6872 0 0 $_TARGETNAME 1 1 4
6874 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
6875 0 0 $_TARGETNAME 0 32 4
6880 @deffn {Flash Driver} {msp432}
6881 All versions of the SimpleLink MSP432 microcontrollers from Texas
6882 Instruments include internal flash. The msp432 flash driver automatically
6883 recognizes the specific version's flash parameters and autoconfigures itself.
6884 Main program flash starts at address 0. The information flash region on
6885 MSP432P4 versions starts at address 0x200000.
6888 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
6891 @deffn {Command} {msp432 mass_erase} bank_id [main|all]
6892 Performs a complete erase of flash. By default, @command{mass_erase} will erase
6893 only the main program flash.
6895 On MSP432P4 versions, using @command{mass_erase all} will erase both the
6896 main program and information flash regions. To also erase the BSL in information
6897 flash, the user must first use the @command{bsl} command.
6900 @deffn {Command} {msp432 bsl} bank_id [unlock|lock]
6901 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
6902 region in information flash so that flash commands can erase or write the BSL.
6903 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
6905 To erase and program the BSL:
6908 flash erase_address 0x202000 0x2000
6909 flash write_image bsl.bin 0x202000
6915 @deffn {Flash Driver} {niietcm4}
6916 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6917 based controllers. Flash size and sector layout are auto-configured by the driver.
6918 Main flash memory is called "Bootflash" and has main region and info region.
6919 Info region is NOT memory mapped by default,
6920 but it can replace first part of main region if needed.
6921 Full erase, single and block writes are supported for both main and info regions.
6922 There is additional not memory mapped flash called "Userflash", which
6923 also have division into regions: main and info.
6924 Purpose of userflash - to store system and user settings.
6925 Driver has special commands to perform operations with this memory.
6928 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6931 Some niietcm4-specific commands are defined:
6933 @deffn {Command} {niietcm4 uflash_read_byte} bank ('main'|'info') address
6934 Read byte from main or info userflash region.
6937 @deffn {Command} {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6938 Write byte to main or info userflash region.
6941 @deffn {Command} {niietcm4 uflash_full_erase} bank
6942 Erase all userflash including info region.
6945 @deffn {Command} {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6946 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6949 @deffn {Command} {niietcm4 uflash_protect_check} bank ('main'|'info')
6950 Check sectors protect.
6953 @deffn {Command} {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6954 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6957 @deffn {Command} {niietcm4 bflash_info_remap} bank ('on'|'off')
6958 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6961 @deffn {Command} {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6962 Configure external memory interface for boot.
6965 @deffn {Command} {niietcm4 service_mode_erase} bank
6966 Perform emergency erase of all flash (bootflash and userflash).
6969 @deffn {Command} {niietcm4 driver_info} bank
6970 Show information about flash driver.
6975 @deffn {Flash Driver} {npcx}
6976 All versions of the NPCX microcontroller families from Nuvoton include internal
6977 flash. The NPCX flash driver supports the NPCX family of devices. The driver
6978 automatically recognizes the specific version's flash parameters and
6979 autoconfigures itself. The flash bank starts at address 0x64000000.
6982 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
6986 @deffn {Flash Driver} {nrf5}
6987 All members of the nRF51 microcontroller families from Nordic Semiconductor
6988 include internal flash and use ARM Cortex-M0 core. nRF52 family powered
6989 by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported
6990 including BPROT flash protection scheme. nRF52833 and nRF52840 devices are
6991 supported with the exception of security extensions (flash access control list
6995 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6998 Some nrf5-specific commands are defined:
7000 @deffn {Command} {nrf5 mass_erase}
7001 Erases the contents of the code memory and user information
7002 configuration registers as well. It must be noted that this command
7003 works only for chips that do not have factory pre-programmed region 0
7007 @deffn {Command} {nrf5 info}
7008 Decodes and shows information from FICR and UICR registers.
7013 @deffn {Flash Driver} {ocl}
7014 This driver is an implementation of the ``on chip flash loader''
7015 protocol proposed by Pavel Chromy.
7017 It is a minimalistic command-response protocol intended to be used
7018 over a DCC when communicating with an internal or external flash
7019 loader running from RAM. An example implementation for AT91SAM7x is
7020 available in @file{contrib/loaders/flash/at91sam7x/}.
7023 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
7027 @deffn {Flash Driver} {pic32mx}
7028 The PIC32MX microcontrollers are based on the MIPS 4K cores,
7029 and integrate flash memory.
7032 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
7033 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
7036 @comment numerous *disabled* commands are defined:
7037 @comment - chip_erase ... pointless given flash_erase_address
7038 @comment - lock, unlock ... pointless given protect on/off (yes?)
7039 @comment - pgm_word ... shouldn't bank be deduced from address??
7040 Some pic32mx-specific commands are defined:
7041 @deffn {Command} {pic32mx pgm_word} address value bank
7042 Programs the specified 32-bit @var{value} at the given @var{address}
7043 in the specified chip @var{bank}.
7045 @deffn {Command} {pic32mx unlock} bank
7046 Unlock and erase specified chip @var{bank}.
7047 This will remove any Code Protection.
7051 @deffn {Flash Driver} {psoc4}
7052 All members of the PSoC 41xx/42xx microcontroller family from Cypress
7053 include internal flash and use ARM Cortex-M0 cores.
7054 The driver automatically recognizes a number of these chips using
7055 the chip identification register, and autoconfigures itself.
7057 Note: Erased internal flash reads as 00.
7058 System ROM of PSoC 4 does not implement erase of a flash sector.
7061 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
7064 psoc4-specific commands
7065 @deffn {Command} {psoc4 flash_autoerase} num (on|off)
7066 Enables or disables autoerase mode for a flash bank.
7068 If flash_autoerase is off, use mass_erase before flash programming.
7069 Flash erase command fails if region to erase is not whole flash memory.
7071 If flash_autoerase is on, a sector is both erased and programmed in one
7072 system ROM call. Flash erase command is ignored.
7073 This mode is suitable for gdb load.
7075 The @var{num} parameter is a value shown by @command{flash banks}.
7078 @deffn {Command} {psoc4 mass_erase} num
7079 Erases the contents of the flash memory, protection and security lock.
7081 The @var{num} parameter is a value shown by @command{flash banks}.
7085 @deffn {Flash Driver} {psoc5lp}
7086 All members of the PSoC 5LP microcontroller family from Cypress
7087 include internal program flash and use ARM Cortex-M3 cores.
7088 The driver probes for a number of these chips and autoconfigures itself,
7089 apart from the base address.
7092 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
7095 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
7096 @quotation Attention
7097 If flash operations are performed in ECC-disabled mode, they will also affect
7098 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
7099 then also erase the corresponding 2k data bytes in the 0x48000000 area.
7100 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
7103 Commands defined in the @var{psoc5lp} driver:
7105 @deffn {Command} {psoc5lp mass_erase}
7106 Erases all flash data and ECC/configuration bytes, all flash protection rows,
7107 and all row latches in all flash arrays on the device.
7111 @deffn {Flash Driver} {psoc5lp_eeprom}
7112 All members of the PSoC 5LP microcontroller family from Cypress
7113 include internal EEPROM and use ARM Cortex-M3 cores.
7114 The driver probes for a number of these chips and autoconfigures itself,
7115 apart from the base address.
7118 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
7123 @deffn {Flash Driver} {psoc5lp_nvl}
7124 All members of the PSoC 5LP microcontroller family from Cypress
7125 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
7126 The driver probes for a number of these chips and autoconfigures itself.
7129 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
7132 PSoC 5LP chips have multiple NV Latches:
7135 @item Device Configuration NV Latch - 4 bytes
7136 @item Write Once (WO) NV Latch - 4 bytes
7139 @b{Note:} This driver only implements the Device Configuration NVL.
7141 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
7142 @quotation Attention
7143 Switching ECC mode via write to Device Configuration NVL will require a reset
7144 after successful write.
7148 @deffn {Flash Driver} {psoc6}
7149 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
7150 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
7151 the same Flash/RAM/MMIO address space.
7153 Flash in PSoC6 is split into three regions:
7155 @item Main Flash - this is the main storage for user application.
7156 Total size varies among devices, sector size: 256 kBytes, row size:
7157 512 bytes. Supports erase operation on individual rows.
7158 @item Work Flash - intended to be used as storage for user data
7159 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
7160 row size: 512 bytes.
7161 @item Supervisory Flash - special region which contains device-specific
7162 service data. This region does not support erase operation. Only few rows can
7163 be programmed by the user, most of the rows are read only. Programming
7164 operation will erase row automatically.
7167 All three flash regions are supported by the driver. Flash geometry is detected
7168 automatically by parsing data in SPCIF_GEOMETRY register.
7170 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
7173 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
7175 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
7177 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
7179 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
7181 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
7183 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
7186 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
7188 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
7190 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
7192 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
7194 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
7196 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
7200 psoc6-specific commands
7201 @deffn {Command} {psoc6 reset_halt}
7202 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
7203 When invoked for CM0+ target, it will set break point at application entry point
7204 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
7205 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
7206 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
7209 @deffn {Command} {psoc6 mass_erase} num
7210 Erases the contents given flash bank. The @var{num} parameter is a value shown
7211 by @command{flash banks}.
7212 Note: only Main and Work flash regions support Erase operation.
7216 @deffn {Flash Driver} {rp2040}
7217 Supports RP2040 "Raspberry Pi Pico" microcontroller.
7218 RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
7219 Flash/RAM/MMIO address space. Non-volatile storage is achieved with an
7220 external QSPI flash; a Boot ROM provides helper functions.
7223 flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
7227 @deffn {Flash Driver} {sim3x}
7228 All members of the SiM3 microcontroller family from Silicon Laboratories
7229 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
7231 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
7232 If this fails, it will use the @var{size} parameter as the size of flash bank.
7235 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
7238 There are 2 commands defined in the @var{sim3x} driver:
7240 @deffn {Command} {sim3x mass_erase}
7241 Erases the complete flash. This is used to unlock the flash.
7242 And this command is only possible when using the SWD interface.
7245 @deffn {Command} {sim3x lock}
7246 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
7250 @deffn {Flash Driver} {stellaris}
7251 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
7252 families from Texas Instruments include internal flash. The driver
7253 automatically recognizes a number of these chips using the chip
7254 identification register, and autoconfigures itself.
7257 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
7260 @deffn {Command} {stellaris recover}
7261 Performs the @emph{Recovering a "Locked" Device} procedure to restore
7262 the flash and its associated nonvolatile registers to their factory
7263 default values (erased). This is the only way to remove flash
7264 protection or re-enable debugging if that capability has been
7267 Note that the final "power cycle the chip" step in this procedure
7268 must be performed by hand, since OpenOCD can't do it.
7270 if more than one Stellaris chip is connected, the procedure is
7271 applied to all of them.
7276 @deffn {Flash Driver} {stm32f1x}
7277 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
7278 from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
7279 families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
7280 The driver automatically recognizes a number of these chips using
7281 the chip identification register, and autoconfigures itself.
7284 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
7287 Note that some devices have been found that have a flash size register that contains
7288 an invalid value, to workaround this issue you can override the probed value used by
7292 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
7295 If you have a target with dual flash banks then define the second bank
7296 as per the following example.
7298 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
7301 Some stm32f1x-specific commands are defined:
7303 @deffn {Command} {stm32f1x lock} num
7304 Locks the entire stm32 device against reading.
7305 The @var{num} parameter is a value shown by @command{flash banks}.
7308 @deffn {Command} {stm32f1x unlock} num
7309 Unlocks the entire stm32 device for reading. This command will cause
7310 a mass erase of the entire stm32 device if previously locked.
7311 The @var{num} parameter is a value shown by @command{flash banks}.
7314 @deffn {Command} {stm32f1x mass_erase} num
7315 Mass erases the entire stm32 device.
7316 The @var{num} parameter is a value shown by @command{flash banks}.
7319 @deffn {Command} {stm32f1x options_read} num
7320 Reads and displays active stm32 option bytes loaded during POR
7321 or upon executing the @command{stm32f1x options_load} command.
7322 The @var{num} parameter is a value shown by @command{flash banks}.
7325 @deffn {Command} {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
7326 Writes the stm32 option byte with the specified values.
7327 The @var{num} parameter is a value shown by @command{flash banks}.
7328 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
7331 @deffn {Command} {stm32f1x options_load} num
7332 Generates a special kind of reset to re-load the stm32 option bytes written
7333 by the @command{stm32f1x options_write} or @command{flash protect} commands
7334 without having to power cycle the target. Not applicable to stm32f1x devices.
7335 The @var{num} parameter is a value shown by @command{flash banks}.
7339 @deffn {Flash Driver} {stm32f2x}
7340 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
7341 include internal flash and use ARM Cortex-M3/M4/M7 cores.
7342 The driver automatically recognizes a number of these chips using
7343 the chip identification register, and autoconfigures itself.
7346 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
7349 If you use OTP (One-Time Programmable) memory define it as a second bank
7350 as per the following example.
7352 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
7355 @deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
7356 Enables or disables OTP write commands for bank @var{num}.
7357 The @var{num} parameter is a value shown by @command{flash banks}.
7360 Note that some devices have been found that have a flash size register that contains
7361 an invalid value, to workaround this issue you can override the probed value used by
7365 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
7368 Some stm32f2x-specific commands are defined:
7370 @deffn {Command} {stm32f2x lock} num
7371 Locks the entire stm32 device.
7372 The @var{num} parameter is a value shown by @command{flash banks}.
7375 @deffn {Command} {stm32f2x unlock} num
7376 Unlocks the entire stm32 device.
7377 The @var{num} parameter is a value shown by @command{flash banks}.
7380 @deffn {Command} {stm32f2x mass_erase} num
7381 Mass erases the entire stm32f2x device.
7382 The @var{num} parameter is a value shown by @command{flash banks}.
7385 @deffn {Command} {stm32f2x options_read} num
7386 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
7387 The @var{num} parameter is a value shown by @command{flash banks}.
7390 @deffn {Command} {stm32f2x options_write} num user_options boot_addr0 boot_addr1
7391 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
7392 Warning: The meaning of the various bits depends on the device, always check datasheet!
7393 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
7394 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
7395 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
7398 @deffn {Command} {stm32f2x optcr2_write} num optcr2
7399 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
7400 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
7404 @deffn {Flash Driver} {stm32h7x}
7405 All members of the STM32H7 microcontroller families from STMicroelectronics
7406 include internal flash and use ARM Cortex-M7 core.
7407 The driver automatically recognizes a number of these chips using
7408 the chip identification register, and autoconfigures itself.
7411 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
7414 Note that some devices have been found that have a flash size register that contains
7415 an invalid value, to workaround this issue you can override the probed value used by
7419 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
7422 Some stm32h7x-specific commands are defined:
7424 @deffn {Command} {stm32h7x lock} num
7425 Locks the entire stm32 device.
7426 The @var{num} parameter is a value shown by @command{flash banks}.
7429 @deffn {Command} {stm32h7x unlock} num
7430 Unlocks the entire stm32 device.
7431 The @var{num} parameter is a value shown by @command{flash banks}.
7434 @deffn {Command} {stm32h7x mass_erase} num
7435 Mass erases the entire stm32h7x device.
7436 The @var{num} parameter is a value shown by @command{flash banks}.
7439 @deffn {Command} {stm32h7x option_read} num reg_offset
7440 Reads an option byte register from the stm32h7x device.
7441 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7442 is the register offset of the option byte to read from the used bank registers' base.
7443 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
7448 stm32h7x option_read 0 0x1c
7450 stm32h7x option_read 0 0x38
7452 stm32h7x option_read 1 0x38
7456 @deffn {Command} {stm32h7x option_write} num reg_offset value [reg_mask]
7457 Writes an option byte register of the stm32h7x device.
7458 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7459 is the register offset of the option byte to write from the used bank register base,
7460 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
7465 # swap bank 1 and bank 2 in dual bank devices
7466 # by setting SWAP_BANK_OPT bit in OPTSR_PRG
7467 stm32h7x option_write 0 0x20 0x8000000 0x8000000
7472 @deffn {Flash Driver} {stm32lx}
7473 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
7474 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
7475 The driver automatically recognizes a number of these chips using
7476 the chip identification register, and autoconfigures itself.
7479 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
7482 Note that some devices have been found that have a flash size register that contains
7483 an invalid value, to workaround this issue you can override the probed value used by
7484 the flash driver. If you use 0 as the bank base address, it tells the
7485 driver to autodetect the bank location assuming you're configuring the
7489 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
7492 Some stm32lx-specific commands are defined:
7494 @deffn {Command} {stm32lx lock} num
7495 Locks the entire stm32 device.
7496 The @var{num} parameter is a value shown by @command{flash banks}.
7499 @deffn {Command} {stm32lx unlock} num
7500 Unlocks the entire stm32 device.
7501 The @var{num} parameter is a value shown by @command{flash banks}.
7504 @deffn {Command} {stm32lx mass_erase} num
7505 Mass erases the entire stm32lx device (all flash banks and EEPROM
7506 data). This is the only way to unlock a protected flash (unless RDP
7507 Level is 2 which can't be unlocked at all).
7508 The @var{num} parameter is a value shown by @command{flash banks}.
7512 @deffn {Flash Driver} {stm32l4x}
7513 All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
7514 microcontroller families from STMicroelectronics include internal flash
7515 and use ARM Cortex-M0+, M4 and M33 cores.
7516 The driver automatically recognizes a number of these chips using
7517 the chip identification register, and autoconfigures itself.
7520 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7523 If you use OTP (One-Time Programmable) memory define it as a second bank
7524 as per the following example.
7526 flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
7529 @deffn {Command} {stm32l4x otp} num (@option{enable}|@option{disable}|@option{show})
7530 Enables or disables OTP write commands for bank @var{num}.
7531 The @var{num} parameter is a value shown by @command{flash banks}.
7534 Note that some devices have been found that have a flash size register that contains
7535 an invalid value, to workaround this issue you can override the probed value used by
7536 the flash driver. However, specifying a wrong value might lead to a completely
7537 wrong flash layout, so this feature must be used carefully.
7540 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7543 Some stm32l4x-specific commands are defined:
7545 @deffn {Command} {stm32l4x lock} num
7546 Locks the entire stm32 device.
7547 The @var{num} parameter is a value shown by @command{flash banks}.
7549 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7552 @deffn {Command} {stm32l4x unlock} num
7553 Unlocks the entire stm32 device.
7554 The @var{num} parameter is a value shown by @command{flash banks}.
7556 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7559 @deffn {Command} {stm32l4x mass_erase} num
7560 Mass erases the entire stm32l4x device.
7561 The @var{num} parameter is a value shown by @command{flash banks}.
7564 @deffn {Command} {stm32l4x option_read} num reg_offset
7565 Reads an option byte register from the stm32l4x device.
7566 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7567 is the register offset of the Option byte to read.
7569 For example to read the FLASH_OPTR register:
7571 stm32l4x option_read 0 0x20
7572 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
7573 # Option Register (for STM32WBx): <0x58004020> = ...
7574 # The correct flash base address will be used automatically
7577 The above example will read out the FLASH_OPTR register which contains the RDP
7578 option byte, Watchdog configuration, BOR level etc.
7581 @deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
7582 Write an option byte register of the stm32l4x device.
7583 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7584 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
7585 to apply when writing the register (only bits with a '1' will be touched).
7587 @emph{Note:} To apply the option bytes change immediately, use @command{stm32l4x option_load}.
7589 For example to write the WRP1AR option bytes:
7591 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
7594 The above example will write the WRP1AR option register configuring the Write protection
7595 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
7596 This will effectively write protect all sectors in flash bank 1.
7599 @deffn {Command} {stm32l4x wrp_info} num [device_bank]
7600 List the protected areas using WRP.
7601 The @var{num} parameter is a value shown by @command{flash banks}.
7602 @var{device_bank} parameter is optional, possible values 'bank1' or 'bank2',
7603 if not specified, the command will display the whole flash protected areas.
7605 @b{Note:} @var{device_bank} is different from banks created using @code{flash bank}.
7606 Devices supported in this flash driver, can have main flash memory organized
7607 in single or dual-banks mode.
7608 Thus the usage of @var{device_bank} is meaningful only in dual-bank mode, to get
7609 write protected areas in a specific @var{device_bank}
7613 @deffn {Command} {stm32l4x option_load} num
7614 Forces a re-load of the option byte registers. Will cause a system reset of the device.
7615 The @var{num} parameter is a value shown by @command{flash banks}.
7618 @deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
7619 Enables or disables Global TrustZone Security, using the TZEN option bit.
7620 If neither @option{enabled} nor @option{disable} are specified, the command will display
7621 the TrustZone status.
7622 @emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
7623 @emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
7627 @deffn {Flash Driver} {str7x}
7628 All members of the STR7 microcontroller family from STMicroelectronics
7629 include internal flash and use ARM7TDMI cores.
7630 The @var{str7x} driver defines one mandatory parameter, @var{variant},
7631 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
7634 flash bank $_FLASHNAME str7x \
7635 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
7638 @deffn {Command} {str7x disable_jtag} bank
7639 Activate the Debug/Readout protection mechanism
7640 for the specified flash bank.
7644 @deffn {Flash Driver} {str9x}
7645 Most members of the STR9 microcontroller family from STMicroelectronics
7646 include internal flash and use ARM966E cores.
7647 The str9 needs the flash controller to be configured using
7648 the @command{str9x flash_config} command prior to Flash programming.
7651 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
7652 str9x flash_config 0 4 2 0 0x80000
7655 @deffn {Command} {str9x flash_config} num bbsr nbbsr bbadr nbbadr
7656 Configures the str9 flash controller.
7657 The @var{num} parameter is a value shown by @command{flash banks}.
7660 @item @var{bbsr} - Boot Bank Size register
7661 @item @var{nbbsr} - Non Boot Bank Size register
7662 @item @var{bbadr} - Boot Bank Start Address register
7663 @item @var{nbbadr} - Boot Bank Start Address register
7669 @deffn {Flash Driver} {str9xpec}
7672 Only use this driver for locking/unlocking the device or configuring the option bytes.
7673 Use the standard str9 driver for programming.
7674 Before using the flash commands the turbo mode must be enabled using the
7675 @command{str9xpec enable_turbo} command.
7677 Here is some background info to help
7678 you better understand how this driver works. OpenOCD has two flash drivers for
7682 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7683 flash programming as it is faster than the @option{str9xpec} driver.
7685 Direct programming @option{str9xpec} using the flash controller. This is an
7686 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7687 core does not need to be running to program using this flash driver. Typical use
7688 for this driver is locking/unlocking the target and programming the option bytes.
7691 Before we run any commands using the @option{str9xpec} driver we must first disable
7692 the str9 core. This example assumes the @option{str9xpec} driver has been
7693 configured for flash bank 0.
7695 # assert srst, we do not want core running
7696 # while accessing str9xpec flash driver
7698 # turn off target polling
7701 str9xpec enable_turbo 0
7703 str9xpec options_read 0
7704 # re-enable str9 core
7705 str9xpec disable_turbo 0
7709 The above example will read the str9 option bytes.
7710 When performing a unlock remember that you will not be able to halt the str9 - it
7711 has been locked. Halting the core is not required for the @option{str9xpec} driver
7712 as mentioned above, just issue the commands above manually or from a telnet prompt.
7714 Several str9xpec-specific commands are defined:
7716 @deffn {Command} {str9xpec disable_turbo} num
7717 Restore the str9 into JTAG chain.
7720 @deffn {Command} {str9xpec enable_turbo} num
7721 Enable turbo mode, will simply remove the str9 from the chain and talk
7722 directly to the embedded flash controller.
7725 @deffn {Command} {str9xpec lock} num
7726 Lock str9 device. The str9 will only respond to an unlock command that will
7730 @deffn {Command} {str9xpec part_id} num
7731 Prints the part identifier for bank @var{num}.
7734 @deffn {Command} {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7735 Configure str9 boot bank.
7738 @deffn {Command} {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
7739 Configure str9 lvd source.
7742 @deffn {Command} {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
7743 Configure str9 lvd threshold.
7746 @deffn {Command} {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
7747 Configure str9 lvd reset warning source.
7750 @deffn {Command} {str9xpec options_read} num
7751 Read str9 option bytes.
7754 @deffn {Command} {str9xpec options_write} num
7755 Write str9 option bytes.
7758 @deffn {Command} {str9xpec unlock} num
7764 @deffn {Flash Driver} {swm050}
7766 All members of the swm050 microcontroller family from Foshan Synwit Tech.
7769 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
7772 One swm050-specific command is defined:
7774 @deffn {Command} {swm050 mass_erase} bank_id
7775 Erases the entire flash bank.
7781 @deffn {Flash Driver} {tms470}
7782 Most members of the TMS470 microcontroller family from Texas Instruments
7783 include internal flash and use ARM7TDMI cores.
7784 This driver doesn't require the chip and bus width to be specified.
7786 Some tms470-specific commands are defined:
7788 @deffn {Command} {tms470 flash_keyset} key0 key1 key2 key3
7789 Saves programming keys in a register, to enable flash erase and write commands.
7792 @deffn {Command} {tms470 osc_megahertz} clock_mhz
7793 Reports the clock speed, which is used to calculate timings.
7796 @deffn {Command} {tms470 plldis} (0|1)
7797 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
7802 @deffn {Flash Driver} {w600}
7803 W60x series Wi-Fi SoC from WinnerMicro
7804 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
7805 The @var{w600} driver uses the @var{target} parameter to select the
7806 correct bank config.
7809 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
7813 @deffn {Flash Driver} {xmc1xxx}
7814 All members of the XMC1xxx microcontroller family from Infineon.
7815 This driver does not require the chip and bus width to be specified.
7818 @deffn {Flash Driver} {xmc4xxx}
7819 All members of the XMC4xxx microcontroller family from Infineon.
7820 This driver does not require the chip and bus width to be specified.
7822 Some xmc4xxx-specific commands are defined:
7824 @deffn {Command} {xmc4xxx flash_password} bank_id passwd1 passwd2
7825 Saves flash protection passwords which are used to lock the user flash
7828 @deffn {Command} {xmc4xxx flash_unprotect} bank_id user_level[0-1]
7829 Removes Flash write protection from the selected user bank
7834 @section NAND Flash Commands
7837 Compared to NOR or SPI flash, NAND devices are inexpensive
7838 and high density. Today's NAND chips, and multi-chip modules,
7839 commonly hold multiple GigaBytes of data.
7841 NAND chips consist of a number of ``erase blocks'' of a given
7842 size (such as 128 KBytes), each of which is divided into a
7843 number of pages (of perhaps 512 or 2048 bytes each). Each
7844 page of a NAND flash has an ``out of band'' (OOB) area to hold
7845 Error Correcting Code (ECC) and other metadata, usually 16 bytes
7846 of OOB for every 512 bytes of page data.
7848 One key characteristic of NAND flash is that its error rate
7849 is higher than that of NOR flash. In normal operation, that
7850 ECC is used to correct and detect errors. However, NAND
7851 blocks can also wear out and become unusable; those blocks
7852 are then marked "bad". NAND chips are even shipped from the
7853 manufacturer with a few bad blocks. The highest density chips
7854 use a technology (MLC) that wears out more quickly, so ECC
7855 support is increasingly important as a way to detect blocks
7856 that have begun to fail, and help to preserve data integrity
7857 with techniques such as wear leveling.
7859 Software is used to manage the ECC. Some controllers don't
7860 support ECC directly; in those cases, software ECC is used.
7861 Other controllers speed up the ECC calculations with hardware.
7862 Single-bit error correction hardware is routine. Controllers
7863 geared for newer MLC chips may correct 4 or more errors for
7864 every 512 bytes of data.
7866 You will need to make sure that any data you write using
7867 OpenOCD includes the appropriate kind of ECC. For example,
7868 that may mean passing the @code{oob_softecc} flag when
7869 writing NAND data, or ensuring that the correct hardware
7872 The basic steps for using NAND devices include:
7874 @item Declare via the command @command{nand device}
7875 @* Do this in a board-specific configuration file,
7876 passing parameters as needed by the controller.
7877 @item Configure each device using @command{nand probe}.
7878 @* Do this only after the associated target is set up,
7879 such as in its reset-init script or in procures defined
7880 to access that device.
7881 @item Operate on the flash via @command{nand subcommand}
7882 @* Often commands to manipulate the flash are typed by a human, or run
7883 via a script in some automated way. Common task include writing a
7884 boot loader, operating system, or other data needed to initialize or
7888 @b{NOTE:} At the time this text was written, the largest NAND
7889 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
7890 This is because the variables used to hold offsets and lengths
7891 are only 32 bits wide.
7892 (Larger chips may work in some cases, unless an offset or length
7893 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
7894 Some larger devices will work, since they are actually multi-chip
7895 modules with two smaller chips and individual chipselect lines.
7897 @anchor{nandconfiguration}
7898 @subsection NAND Configuration Commands
7899 @cindex NAND configuration
7901 NAND chips must be declared in configuration scripts,
7902 plus some additional configuration that's done after
7903 OpenOCD has initialized.
7905 @deffn {Config Command} {nand device} name driver target [configparams...]
7906 Declares a NAND device, which can be read and written to
7907 after it has been configured through @command{nand probe}.
7908 In OpenOCD, devices are single chips; this is unlike some
7909 operating systems, which may manage multiple chips as if
7910 they were a single (larger) device.
7911 In some cases, configuring a device will activate extra
7912 commands; see the controller-specific documentation.
7914 @b{NOTE:} This command is not available after OpenOCD
7915 initialization has completed. Use it in board specific
7916 configuration files, not interactively.
7919 @item @var{name} ... may be used to reference the NAND bank
7920 in most other NAND commands. A number is also available.
7921 @item @var{driver} ... identifies the NAND controller driver
7922 associated with the NAND device being declared.
7923 @xref{nanddriverlist,,NAND Driver List}.
7924 @item @var{target} ... names the target used when issuing
7925 commands to the NAND controller.
7926 @comment Actually, it's currently a controller-specific parameter...
7927 @item @var{configparams} ... controllers may support, or require,
7928 additional parameters. See the controller-specific documentation
7929 for more information.
7933 @deffn {Command} {nand list}
7934 Prints a summary of each device declared
7935 using @command{nand device}, numbered from zero.
7936 Note that un-probed devices show no details.
7939 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7940 blocksize: 131072, blocks: 8192
7941 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7942 blocksize: 131072, blocks: 8192
7947 @deffn {Command} {nand probe} num
7948 Probes the specified device to determine key characteristics
7949 like its page and block sizes, and how many blocks it has.
7950 The @var{num} parameter is the value shown by @command{nand list}.
7951 You must (successfully) probe a device before you can use
7952 it with most other NAND commands.
7955 @subsection Erasing, Reading, Writing to NAND Flash
7957 @deffn {Command} {nand dump} num filename offset length [oob_option]
7958 @cindex NAND reading
7959 Reads binary data from the NAND device and writes it to the file,
7960 starting at the specified offset.
7961 The @var{num} parameter is the value shown by @command{nand list}.
7963 Use a complete path name for @var{filename}, so you don't depend
7964 on the directory used to start the OpenOCD server.
7966 The @var{offset} and @var{length} must be exact multiples of the
7967 device's page size. They describe a data region; the OOB data
7968 associated with each such page may also be accessed.
7970 @b{NOTE:} At the time this text was written, no error correction
7971 was done on the data that's read, unless raw access was disabled
7972 and the underlying NAND controller driver had a @code{read_page}
7973 method which handled that error correction.
7975 By default, only page data is saved to the specified file.
7976 Use an @var{oob_option} parameter to save OOB data:
7978 @item no oob_* parameter
7979 @*Output file holds only page data; OOB is discarded.
7980 @item @code{oob_raw}
7981 @*Output file interleaves page data and OOB data;
7982 the file will be longer than "length" by the size of the
7983 spare areas associated with each data page.
7984 Note that this kind of "raw" access is different from
7985 what's implied by @command{nand raw_access}, which just
7986 controls whether a hardware-aware access method is used.
7987 @item @code{oob_only}
7988 @*Output file has only raw OOB data, and will
7989 be smaller than "length" since it will contain only the
7990 spare areas associated with each data page.
7994 @deffn {Command} {nand erase} num [offset length]
7995 @cindex NAND erasing
7996 @cindex NAND programming
7997 Erases blocks on the specified NAND device, starting at the
7998 specified @var{offset} and continuing for @var{length} bytes.
7999 Both of those values must be exact multiples of the device's
8000 block size, and the region they specify must fit entirely in the chip.
8001 If those parameters are not specified,
8002 the whole NAND chip will be erased.
8003 The @var{num} parameter is the value shown by @command{nand list}.
8005 @b{NOTE:} This command will try to erase bad blocks, when told
8006 to do so, which will probably invalidate the manufacturer's bad
8008 For the remainder of the current server session, @command{nand info}
8009 will still report that the block ``is'' bad.
8012 @deffn {Command} {nand write} num filename offset [option...]
8013 @cindex NAND writing
8014 @cindex NAND programming
8015 Writes binary data from the file into the specified NAND device,
8016 starting at the specified offset. Those pages should already
8017 have been erased; you can't change zero bits to one bits.
8018 The @var{num} parameter is the value shown by @command{nand list}.
8020 Use a complete path name for @var{filename}, so you don't depend
8021 on the directory used to start the OpenOCD server.
8023 The @var{offset} must be an exact multiple of the device's page size.
8024 All data in the file will be written, assuming it doesn't run
8025 past the end of the device.
8026 Only full pages are written, and any extra space in the last
8027 page will be filled with 0xff bytes. (That includes OOB data,
8028 if that's being written.)
8030 @b{NOTE:} At the time this text was written, bad blocks are
8031 ignored. That is, this routine will not skip bad blocks,
8032 but will instead try to write them. This can cause problems.
8034 Provide at most one @var{option} parameter. With some
8035 NAND drivers, the meanings of these parameters may change
8036 if @command{nand raw_access} was used to disable hardware ECC.
8038 @item no oob_* parameter
8039 @*File has only page data, which is written.
8040 If raw access is in use, the OOB area will not be written.
8041 Otherwise, if the underlying NAND controller driver has
8042 a @code{write_page} routine, that routine may write the OOB
8043 with hardware-computed ECC data.
8044 @item @code{oob_only}
8045 @*File has only raw OOB data, which is written to the OOB area.
8046 Each page's data area stays untouched. @i{This can be a dangerous
8047 option}, since it can invalidate the ECC data.
8048 You may need to force raw access to use this mode.
8049 @item @code{oob_raw}
8050 @*File interleaves data and OOB data, both of which are written
8051 If raw access is enabled, the data is written first, then the
8053 Otherwise, if the underlying NAND controller driver has
8054 a @code{write_page} routine, that routine may modify the OOB
8055 before it's written, to include hardware-computed ECC data.
8056 @item @code{oob_softecc}
8057 @*File has only page data, which is written.
8058 The OOB area is filled with 0xff, except for a standard 1-bit
8059 software ECC code stored in conventional locations.
8060 You might need to force raw access to use this mode, to prevent
8061 the underlying driver from applying hardware ECC.
8062 @item @code{oob_softecc_kw}
8063 @*File has only page data, which is written.
8064 The OOB area is filled with 0xff, except for a 4-bit software ECC
8065 specific to the boot ROM in Marvell Kirkwood SoCs.
8066 You might need to force raw access to use this mode, to prevent
8067 the underlying driver from applying hardware ECC.
8071 @deffn {Command} {nand verify} num filename offset [option...]
8072 @cindex NAND verification
8073 @cindex NAND programming
8074 Verify the binary data in the file has been programmed to the
8075 specified NAND device, starting at the specified offset.
8076 The @var{num} parameter is the value shown by @command{nand list}.
8078 Use a complete path name for @var{filename}, so you don't depend
8079 on the directory used to start the OpenOCD server.
8081 The @var{offset} must be an exact multiple of the device's page size.
8082 All data in the file will be read and compared to the contents of the
8083 flash, assuming it doesn't run past the end of the device.
8084 As with @command{nand write}, only full pages are verified, so any extra
8085 space in the last page will be filled with 0xff bytes.
8087 The same @var{options} accepted by @command{nand write},
8088 and the file will be processed similarly to produce the buffers that
8089 can be compared against the contents produced from @command{nand dump}.
8091 @b{NOTE:} This will not work when the underlying NAND controller
8092 driver's @code{write_page} routine must update the OOB with a
8093 hardware-computed ECC before the data is written. This limitation may
8094 be removed in a future release.
8097 @subsection Other NAND commands
8098 @cindex NAND other commands
8100 @deffn {Command} {nand check_bad_blocks} num [offset length]
8101 Checks for manufacturer bad block markers on the specified NAND
8102 device. If no parameters are provided, checks the whole
8103 device; otherwise, starts at the specified @var{offset} and
8104 continues for @var{length} bytes.
8105 Both of those values must be exact multiples of the device's
8106 block size, and the region they specify must fit entirely in the chip.
8107 The @var{num} parameter is the value shown by @command{nand list}.
8109 @b{NOTE:} Before using this command you should force raw access
8110 with @command{nand raw_access enable} to ensure that the underlying
8111 driver will not try to apply hardware ECC.
8114 @deffn {Command} {nand info} num
8115 The @var{num} parameter is the value shown by @command{nand list}.
8116 This prints the one-line summary from "nand list", plus for
8117 devices which have been probed this also prints any known
8118 status for each block.
8121 @deffn {Command} {nand raw_access} num (@option{enable}|@option{disable})
8122 Sets or clears an flag affecting how page I/O is done.
8123 The @var{num} parameter is the value shown by @command{nand list}.
8125 This flag is cleared (disabled) by default, but changing that
8126 value won't affect all NAND devices. The key factor is whether
8127 the underlying driver provides @code{read_page} or @code{write_page}
8128 methods. If it doesn't provide those methods, the setting of
8129 this flag is irrelevant; all access is effectively ``raw''.
8131 When those methods exist, they are normally used when reading
8132 data (@command{nand dump} or reading bad block markers) or
8133 writing it (@command{nand write}). However, enabling
8134 raw access (setting the flag) prevents use of those methods,
8135 bypassing hardware ECC logic.
8136 @i{This can be a dangerous option}, since writing blocks
8137 with the wrong ECC data can cause them to be marked as bad.
8140 @anchor{nanddriverlist}
8141 @subsection NAND Driver List
8142 As noted above, the @command{nand device} command allows
8143 driver-specific options and behaviors.
8144 Some controllers also activate controller-specific commands.
8146 @deffn {NAND Driver} {at91sam9}
8147 This driver handles the NAND controllers found on AT91SAM9 family chips from
8148 Atmel. It takes two extra parameters: address of the NAND chip;
8149 address of the ECC controller.
8151 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
8153 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
8154 @code{read_page} methods are used to utilize the ECC hardware unless they are
8155 disabled by using the @command{nand raw_access} command. There are four
8156 additional commands that are needed to fully configure the AT91SAM9 NAND
8157 controller. Two are optional; most boards use the same wiring for ALE/CLE:
8158 @deffn {Config Command} {at91sam9 cle} num addr_line
8159 Configure the address line used for latching commands. The @var{num}
8160 parameter is the value shown by @command{nand list}.
8162 @deffn {Config Command} {at91sam9 ale} num addr_line
8163 Configure the address line used for latching addresses. The @var{num}
8164 parameter is the value shown by @command{nand list}.
8167 For the next two commands, it is assumed that the pins have already been
8168 properly configured for input or output.
8169 @deffn {Config Command} {at91sam9 rdy_busy} num pio_base_addr pin
8170 Configure the RDY/nBUSY input from the NAND device. The @var{num}
8171 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8172 is the base address of the PIO controller and @var{pin} is the pin number.
8174 @deffn {Config Command} {at91sam9 ce} num pio_base_addr pin
8175 Configure the chip enable input to the NAND device. The @var{num}
8176 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8177 is the base address of the PIO controller and @var{pin} is the pin number.
8181 @deffn {NAND Driver} {davinci}
8182 This driver handles the NAND controllers found on DaVinci family
8183 chips from Texas Instruments.
8184 It takes three extra parameters:
8185 address of the NAND chip;
8186 hardware ECC mode to use (@option{hwecc1},
8187 @option{hwecc4}, @option{hwecc4_infix});
8188 address of the AEMIF controller on this processor.
8190 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
8192 All DaVinci processors support the single-bit ECC hardware,
8193 and newer ones also support the four-bit ECC hardware.
8194 The @code{write_page} and @code{read_page} methods are used
8195 to implement those ECC modes, unless they are disabled using
8196 the @command{nand raw_access} command.
8199 @deffn {NAND Driver} {lpc3180}
8200 These controllers require an extra @command{nand device}
8201 parameter: the clock rate used by the controller.
8202 @deffn {Command} {lpc3180 select} num [mlc|slc]
8203 Configures use of the MLC or SLC controller mode.
8204 MLC implies use of hardware ECC.
8205 The @var{num} parameter is the value shown by @command{nand list}.
8208 At this writing, this driver includes @code{write_page}
8209 and @code{read_page} methods. Using @command{nand raw_access}
8210 to disable those methods will prevent use of hardware ECC
8211 in the MLC controller mode, but won't change SLC behavior.
8213 @comment current lpc3180 code won't issue 5-byte address cycles
8215 @deffn {NAND Driver} {mx3}
8216 This driver handles the NAND controller in i.MX31. The mxc driver
8217 should work for this chip as well.
8220 @deffn {NAND Driver} {mxc}
8221 This driver handles the NAND controller found in Freescale i.MX
8222 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
8223 The driver takes 3 extra arguments, chip (@option{mx27},
8224 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
8225 and optionally if bad block information should be swapped between
8226 main area and spare area (@option{biswap}), defaults to off.
8228 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
8230 @deffn {Command} {mxc biswap} bank_num [enable|disable]
8231 Turns on/off bad block information swapping from main area,
8232 without parameter query status.
8236 @deffn {NAND Driver} {orion}
8237 These controllers require an extra @command{nand device}
8238 parameter: the address of the controller.
8240 nand device orion 0xd8000000
8242 These controllers don't define any specialized commands.
8243 At this writing, their drivers don't include @code{write_page}
8244 or @code{read_page} methods, so @command{nand raw_access} won't
8245 change any behavior.
8248 @deffn {NAND Driver} {s3c2410}
8249 @deffnx {NAND Driver} {s3c2412}
8250 @deffnx {NAND Driver} {s3c2440}
8251 @deffnx {NAND Driver} {s3c2443}
8252 @deffnx {NAND Driver} {s3c6400}
8253 These S3C family controllers don't have any special
8254 @command{nand device} options, and don't define any
8255 specialized commands.
8256 At this writing, their drivers don't include @code{write_page}
8257 or @code{read_page} methods, so @command{nand raw_access} won't
8258 change any behavior.
8261 @node Flash Programming
8262 @chapter Flash Programming
8264 OpenOCD implements numerous ways to program the target flash, whether internal or external.
8265 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
8266 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
8268 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
8269 OpenOCD will program/verify/reset the target and optionally shutdown.
8271 The script is executed as follows and by default the following actions will be performed.
8273 @item 'init' is executed.
8274 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
8275 @item @code{flash write_image} is called to erase and write any flash using the filename given.
8276 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
8277 @item @code{verify_image} is called if @option{verify} parameter is given.
8278 @item @code{reset run} is called if @option{reset} parameter is given.
8279 @item OpenOCD is shutdown if @option{exit} parameter is given.
8282 An example of usage is given below. @xref{program}.
8285 # program and verify using elf/hex/s19. verify and reset
8286 # are optional parameters
8287 openocd -f board/stm32f3discovery.cfg \
8288 -c "program filename.elf verify reset exit"
8290 # binary files need the flash address passing
8291 openocd -f board/stm32f3discovery.cfg \
8292 -c "program filename.bin exit 0x08000000"
8295 @node PLD/FPGA Commands
8296 @chapter PLD/FPGA Commands
8300 Programmable Logic Devices (PLDs) and the more flexible
8301 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
8302 OpenOCD can support programming them.
8303 Although PLDs are generally restrictive (cells are less functional, and
8304 there are no special purpose cells for memory or computational tasks),
8305 they share the same OpenOCD infrastructure.
8306 Accordingly, both are called PLDs here.
8308 @section PLD/FPGA Configuration and Commands
8310 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
8311 OpenOCD maintains a list of PLDs available for use in various commands.
8312 Also, each such PLD requires a driver.
8314 They are referenced by the number shown by the @command{pld devices} command,
8315 and new PLDs are defined by @command{pld device driver_name}.
8317 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
8318 Defines a new PLD device, supported by driver @var{driver_name},
8319 using the TAP named @var{tap_name}.
8320 The driver may make use of any @var{driver_options} to configure its
8324 @deffn {Command} {pld devices}
8325 Lists the PLDs and their numbers.
8328 @deffn {Command} {pld load} num filename
8329 Loads the file @file{filename} into the PLD identified by @var{num}.
8330 The file format must be inferred by the driver.
8333 @section PLD/FPGA Drivers, Options, and Commands
8335 Drivers may support PLD-specific options to the @command{pld device}
8336 definition command, and may also define commands usable only with
8337 that particular type of PLD.
8339 @deffn {FPGA Driver} {virtex2} [no_jstart]
8340 Virtex-II is a family of FPGAs sold by Xilinx.
8341 It supports the IEEE 1532 standard for In-System Configuration (ISC).
8343 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
8344 loading the bitstream. While required for Series2, Series3, and Series6, it
8345 breaks bitstream loading on Series7.
8347 @deffn {Command} {virtex2 read_stat} num
8348 Reads and displays the Virtex-II status register (STAT)
8353 @node General Commands
8354 @chapter General Commands
8357 The commands documented in this chapter here are common commands that
8358 you, as a human, may want to type and see the output of. Configuration type
8359 commands are documented elsewhere.
8363 @item @b{Source Of Commands}
8364 @* OpenOCD commands can occur in a configuration script (discussed
8365 elsewhere) or typed manually by a human or supplied programmatically,
8366 or via one of several TCP/IP Ports.
8368 @item @b{From the human}
8369 @* A human should interact with the telnet interface (default port: 4444)
8370 or via GDB (default port 3333).
8372 To issue commands from within a GDB session, use the @option{monitor}
8373 command, e.g. use @option{monitor poll} to issue the @option{poll}
8374 command. All output is relayed through the GDB session.
8376 @item @b{Machine Interface}
8377 The Tcl interface's intent is to be a machine interface. The default Tcl
8382 @section Server Commands
8384 @deffn {Command} {exit}
8385 Exits the current telnet session.
8388 @deffn {Command} {help} [string]
8389 With no parameters, prints help text for all commands.
8390 Otherwise, prints each helptext containing @var{string}.
8391 Not every command provides helptext.
8393 Configuration commands, and commands valid at any time, are
8394 explicitly noted in parenthesis.
8395 In most cases, no such restriction is listed; this indicates commands
8396 which are only available after the configuration stage has completed.
8399 @deffn {Command} {usage} [string]
8400 With no parameters, prints usage text for all commands. Otherwise,
8401 prints all usage text of which command, help text, and usage text
8402 containing @var{string}.
8403 Not every command provides helptext.
8406 @deffn {Command} {sleep} msec [@option{busy}]
8407 Wait for at least @var{msec} milliseconds before resuming.
8408 If @option{busy} is passed, busy-wait instead of sleeping.
8409 (This option is strongly discouraged.)
8410 Useful in connection with script files
8411 (@command{script} command and @command{target_name} configuration).
8414 @deffn {Command} {shutdown} [@option{error}]
8415 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
8416 other). If option @option{error} is used, OpenOCD will return a
8417 non-zero exit code to the parent process.
8419 Like any TCL commands, also @command{shutdown} can be redefined, e.g.:
8422 rename shutdown original_shutdown
8423 proc shutdown @{@} @{
8424 puts "This is my implementation of shutdown"
8425 # my own stuff before exit OpenOCD
8429 If user types CTRL-C or kills OpenOCD, either the command @command{shutdown}
8430 or its replacement will be automatically executed before OpenOCD exits.
8434 @deffn {Command} {debug_level} [n]
8435 @cindex message level
8436 Display debug level.
8437 If @var{n} (from 0..4) is provided, then set it to that level.
8438 This affects the kind of messages sent to the server log.
8439 Level 0 is error messages only;
8440 level 1 adds warnings;
8441 level 2 adds informational messages;
8442 level 3 adds debugging messages;
8443 and level 4 adds verbose low-level debug messages.
8444 The default is level 2, but that can be overridden on
8445 the command line along with the location of that log
8446 file (which is normally the server's standard output).
8450 @deffn {Command} {echo} [-n] message
8451 Logs a message at "user" priority.
8452 Option "-n" suppresses trailing newline.
8454 echo "Downloading kernel -- please wait"
8458 @deffn {Command} {log_output} [filename | "default"]
8459 Redirect logging to @var{filename} or set it back to default output;
8460 the default log output channel is stderr.
8463 @deffn {Command} {add_script_search_dir} [directory]
8464 Add @var{directory} to the file/script search path.
8467 @deffn {Config Command} {bindto} [@var{name}]
8468 Specify hostname or IPv4 address on which to listen for incoming
8469 TCP/IP connections. By default, OpenOCD will listen on the loopback
8470 interface only. If your network environment is safe, @code{bindto
8471 0.0.0.0} can be used to cover all available interfaces.
8474 @anchor{targetstatehandling}
8475 @section Target State handling
8478 @cindex target initialization
8480 In this section ``target'' refers to a CPU configured as
8481 shown earlier (@pxref{CPU Configuration}).
8482 These commands, like many, implicitly refer to
8483 a current target which is used to perform the
8484 various operations. The current target may be changed
8485 by using @command{targets} command with the name of the
8486 target which should become current.
8488 @deffn {Command} {reg} [(number|name) [(value|'force')]]
8489 Access a single register by @var{number} or by its @var{name}.
8490 The target must generally be halted before access to CPU core
8491 registers is allowed. Depending on the hardware, some other
8492 registers may be accessible while the target is running.
8494 @emph{With no arguments}:
8495 list all available registers for the current target,
8496 showing number, name, size, value, and cache status.
8497 For valid entries, a value is shown; valid entries
8498 which are also dirty (and will be written back later)
8499 are flagged as such.
8501 @emph{With number/name}: display that register's value.
8502 Use @var{force} argument to read directly from the target,
8503 bypassing any internal cache.
8505 @emph{With both number/name and value}: set register's value.
8506 Writes may be held in a writeback cache internal to OpenOCD,
8507 so that setting the value marks the register as dirty instead
8508 of immediately flushing that value. Resuming CPU execution
8509 (including by single stepping) or otherwise activating the
8510 relevant module will flush such values.
8512 Cores may have surprisingly many registers in their
8513 Debug and trace infrastructure:
8518 (0) r0 (/32): 0x0000D3C2 (dirty)
8519 (1) r1 (/32): 0xFD61F31C
8522 (164) ETM_contextid_comparator_mask (/32)
8527 @deffn {Command} {set_reg} dict
8528 Set register values of the target.
8531 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
8534 For example, the following command sets the value 0 to the program counter (pc)
8535 register and 0x1000 to the stack pointer (sp) register:
8538 set_reg @{pc 0 sp 0x1000@}
8542 @deffn {Command} {get_reg} [-force] list
8543 Get register values from the target and return them as Tcl dictionary with pairs
8544 of register names and values.
8545 If option "-force" is set, the register values are read directly from the
8546 target, bypassing any caching.
8549 @item @var{list} ... List of register names
8552 For example, the following command retrieves the values from the program
8553 counter (pc) and stack pointer (sp) register:
8560 @deffn {Command} {halt} [ms]
8561 @deffnx {Command} {wait_halt} [ms]
8562 The @command{halt} command first sends a halt request to the target,
8563 which @command{wait_halt} doesn't.
8564 Otherwise these behave the same: wait up to @var{ms} milliseconds,
8565 or 5 seconds if there is no parameter, for the target to halt
8566 (and enter debug mode).
8567 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
8570 On ARM cores, software using the @emph{wait for interrupt} operation
8571 often blocks the JTAG access needed by a @command{halt} command.
8572 This is because that operation also puts the core into a low
8573 power mode by gating the core clock;
8574 but the core clock is needed to detect JTAG clock transitions.
8576 One partial workaround uses adaptive clocking: when the core is
8577 interrupted the operation completes, then JTAG clocks are accepted
8578 at least until the interrupt handler completes.
8579 However, this workaround is often unusable since the processor, board,
8580 and JTAG adapter must all support adaptive JTAG clocking.
8581 Also, it can't work until an interrupt is issued.
8583 A more complete workaround is to not use that operation while you
8584 work with a JTAG debugger.
8585 Tasking environments generally have idle loops where the body is the
8586 @emph{wait for interrupt} operation.
8587 (On older cores, it is a coprocessor action;
8588 newer cores have a @option{wfi} instruction.)
8589 Such loops can just remove that operation, at the cost of higher
8590 power consumption (because the CPU is needlessly clocked).
8595 @deffn {Command} {resume} [address]
8596 Resume the target at its current code position,
8597 or the optional @var{address} if it is provided.
8598 OpenOCD will wait 5 seconds for the target to resume.
8601 @deffn {Command} {step} [address]
8602 Single-step the target at its current code position,
8603 or the optional @var{address} if it is provided.
8606 @anchor{resetcommand}
8607 @deffn {Command} {reset}
8608 @deffnx {Command} {reset run}
8609 @deffnx {Command} {reset halt}
8610 @deffnx {Command} {reset init}
8611 Perform as hard a reset as possible, using SRST if possible.
8612 @emph{All defined targets will be reset, and target
8613 events will fire during the reset sequence.}
8615 The optional parameter specifies what should
8616 happen after the reset.
8617 If there is no parameter, a @command{reset run} is executed.
8618 The other options will not work on all systems.
8619 @xref{Reset Configuration}.
8622 @item @b{run} Let the target run
8623 @item @b{halt} Immediately halt the target
8624 @item @b{init} Immediately halt the target, and execute the reset-init script
8628 @deffn {Command} {soft_reset_halt}
8629 Requesting target halt and executing a soft reset. This is often used
8630 when a target cannot be reset and halted. The target, after reset is
8631 released begins to execute code. OpenOCD attempts to stop the CPU and
8632 then sets the program counter back to the reset vector. Unfortunately
8633 the code that was executed may have left the hardware in an unknown
8637 @deffn {Command} {adapter assert} [signal [assert|deassert signal]]
8638 @deffnx {Command} {adapter deassert} [signal [assert|deassert signal]]
8639 Set values of reset signals.
8640 Without parameters returns current status of the signals.
8641 The @var{signal} parameter values may be
8642 @option{srst}, indicating that srst signal is to be asserted or deasserted,
8643 @option{trst}, indicating that trst signal is to be asserted or deasserted.
8645 The @command{reset_config} command should already have been used
8646 to configure how the board and the adapter treat these two
8647 signals, and to say if either signal is even present.
8648 @xref{Reset Configuration}.
8649 Trying to assert a signal that is not present triggers an error.
8650 If a signal is present on the adapter and not specified in the command,
8651 the signal will not be modified.
8654 TRST is specially handled.
8655 It actually signifies JTAG's @sc{reset} state.
8656 So if the board doesn't support the optional TRST signal,
8657 or it doesn't support it along with the specified SRST value,
8658 JTAG reset is triggered with TMS and TCK signals
8659 instead of the TRST signal.
8660 And no matter how that JTAG reset is triggered, once
8661 the scan chain enters @sc{reset} with TRST inactive,
8662 TAP @code{post-reset} events are delivered to all TAPs
8663 with handlers for that event.
8667 @anchor{memoryaccess}
8668 @section Memory access commands
8669 @cindex memory access
8671 These commands allow accesses of a specific size to the memory
8672 system. Often these are used to configure the current target in some
8673 special way. For example - one may need to write certain values to the
8674 SDRAM controller to enable SDRAM.
8677 @item Use the @command{targets} (plural) command
8678 to change the current target.
8679 @item In system level scripts these commands are deprecated.
8680 Please use their TARGET object siblings to avoid making assumptions
8681 about what TAP is the current target, or about MMU configuration.
8684 @deffn {Command} {mdd} [phys] addr [count]
8685 @deffnx {Command} {mdw} [phys] addr [count]
8686 @deffnx {Command} {mdh} [phys] addr [count]
8687 @deffnx {Command} {mdb} [phys] addr [count]
8688 Display contents of address @var{addr}, as
8689 64-bit doublewords (@command{mdd}),
8690 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8691 or 8-bit bytes (@command{mdb}).
8692 When the current target has an MMU which is present and active,
8693 @var{addr} is interpreted as a virtual address.
8694 Otherwise, or if the optional @var{phys} flag is specified,
8695 @var{addr} is interpreted as a physical address.
8696 If @var{count} is specified, displays that many units.
8697 (If you want to manipulate the data instead of displaying it,
8698 see the @code{mem2array} primitives.)
8701 @deffn {Command} {mwd} [phys] addr doubleword [count]
8702 @deffnx {Command} {mww} [phys] addr word [count]
8703 @deffnx {Command} {mwh} [phys] addr halfword [count]
8704 @deffnx {Command} {mwb} [phys] addr byte [count]
8705 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
8706 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
8707 at the specified address @var{addr}.
8708 When the current target has an MMU which is present and active,
8709 @var{addr} is interpreted as a virtual address.
8710 Otherwise, or if the optional @var{phys} flag is specified,
8711 @var{addr} is interpreted as a physical address.
8712 If @var{count} is specified, fills that many units of consecutive address.
8715 @anchor{imageaccess}
8716 @section Image loading commands
8717 @cindex image loading
8718 @cindex image dumping
8720 @deffn {Command} {dump_image} filename address size
8721 Dump @var{size} bytes of target memory starting at @var{address} to the
8722 binary file named @var{filename}.
8725 @deffn {Command} {fast_load}
8726 Loads an image stored in memory by @command{fast_load_image} to the
8727 current target. Must be preceded by fast_load_image.
8730 @deffn {Command} {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
8731 Normally you should be using @command{load_image} or GDB load. However, for
8732 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
8733 host), storing the image in memory and uploading the image to the target
8734 can be a way to upload e.g. multiple debug sessions when the binary does not change.
8735 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
8736 memory, i.e. does not affect target. This approach is also useful when profiling
8737 target programming performance as I/O and target programming can easily be profiled
8741 @deffn {Command} {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
8742 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
8743 The file format may optionally be specified
8744 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
8745 In addition the following arguments may be specified:
8746 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
8747 @var{max_length} - maximum number of bytes to load.
8749 proc load_image_bin @{fname foffset address length @} @{
8750 # Load data from fname filename at foffset offset to
8751 # target at address. Load at most length bytes.
8752 load_image $fname [expr @{$address - $foffset@}] bin \
8758 @deffn {Command} {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
8759 Displays image section sizes and addresses
8760 as if @var{filename} were loaded into target memory
8761 starting at @var{address} (defaults to zero).
8762 The file format may optionally be specified
8763 (@option{bin}, @option{ihex}, or @option{elf})
8766 @deffn {Command} {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
8767 Verify @var{filename} against target memory starting at @var{address}.
8768 The file format may optionally be specified
8769 (@option{bin}, @option{ihex}, or @option{elf})
8770 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
8773 @deffn {Command} {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
8774 Verify @var{filename} against target memory starting at @var{address}.
8775 The file format may optionally be specified
8776 (@option{bin}, @option{ihex}, or @option{elf})
8777 This perform a comparison using a CRC checksum only
8781 @section Breakpoint and Watchpoint commands
8785 CPUs often make debug modules accessible through JTAG, with
8786 hardware support for a handful of code breakpoints and data
8788 In addition, CPUs almost always support software breakpoints.
8790 @deffn {Command} {bp} [address len [@option{hw}]]
8791 With no parameters, lists all active breakpoints.
8792 Else sets a breakpoint on code execution starting
8793 at @var{address} for @var{length} bytes.
8794 This is a software breakpoint, unless @option{hw} is specified
8795 in which case it will be a hardware breakpoint.
8797 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
8798 for similar mechanisms that do not consume hardware breakpoints.)
8801 @deffn {Command} {rbp} @option{all} | address
8802 Remove the breakpoint at @var{address} or all breakpoints.
8805 @deffn {Command} {rwp} address
8806 Remove data watchpoint on @var{address}
8809 @deffn {Command} {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
8810 With no parameters, lists all active watchpoints.
8811 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
8812 The watch point is an "access" watchpoint unless
8813 the @option{r} or @option{w} parameter is provided,
8814 defining it as respectively a read or write watchpoint.
8815 If a @var{value} is provided, that value is used when determining if
8816 the watchpoint should trigger. The value may be first be masked
8817 using @var{mask} to mark ``don't care'' fields.
8821 @section Real Time Transfer (RTT)
8823 Real Time Transfer (RTT) is an interface specified by SEGGER based on basic
8824 memory reads and writes to transfer data bidirectionally between target and host.
8825 The specification is independent of the target architecture.
8826 Every target that supports so called "background memory access", which means
8827 that the target memory can be accessed by the debugger while the target is
8828 running, can be used.
8829 This interface is especially of interest for targets without
8830 Serial Wire Output (SWO), such as ARM Cortex-M0, or where semihosting is not
8831 applicable because of real-time constraints.
8834 The current implementation supports only single target devices.
8837 The data transfer between host and target device is organized through
8838 unidirectional up/down-channels for target-to-host and host-to-target
8839 communication, respectively.
8842 The current implementation does not respect channel buffer flags.
8843 They are used to determine what happens when writing to a full buffer, for
8847 Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
8848 assigned to each channel to make them accessible to an unlimited number
8849 of TCP/IP connections.
8851 @deffn {Command} {rtt setup} address size ID
8852 Configure RTT for the currently selected target.
8853 Once RTT is started, OpenOCD searches for a control block with the
8854 identifier @var{ID} starting at the memory address @var{address} within the next
8858 @deffn {Command} {rtt start}
8860 If the control block location is not known, OpenOCD starts searching for it.
8863 @deffn {Command} {rtt stop}
8867 @deffn {Command} {rtt polling_interval} [interval]
8868 Display the polling interval.
8869 If @var{interval} is provided, set the polling interval.
8870 The polling interval determines (in milliseconds) how often the up-channels are
8871 checked for new data.
8874 @deffn {Command} {rtt channels}
8875 Display a list of all channels and their properties.
8878 @deffn {Command} {rtt channellist}
8879 Return a list of all channels and their properties as Tcl list.
8880 The list can be manipulated easily from within scripts.
8883 @deffn {Command} {rtt server start} port channel
8884 Start a TCP server on @var{port} for the channel @var{channel}.
8887 @deffn {Command} {rtt server stop} port
8888 Stop the TCP sever with port @var{port}.
8891 The following example shows how to setup RTT using the SEGGER RTT implementation
8892 on the target device.
8897 rtt setup 0x20000000 2048 "SEGGER RTT"
8900 rtt server start 9090 0
8903 In this example, OpenOCD searches the control block with the ID "SEGGER RTT"
8904 starting at 0x20000000 for 2048 bytes. The RTT channel 0 is exposed through the
8908 @section Misc Commands
8911 @deffn {Command} {profile} seconds filename [start end]
8912 Profiling samples the CPU's program counter as quickly as possible,
8913 which is useful for non-intrusive stochastic profiling.
8914 Saves up to 10000 samples in @file{filename} using ``gmon.out''
8915 format. Optional @option{start} and @option{end} parameters allow to
8916 limit the address range.
8919 @deffn {Command} {version}
8920 Displays a string identifying the version of this OpenOCD server.
8923 @deffn {Command} {virt2phys} virtual_address
8924 Requests the current target to map the specified @var{virtual_address}
8925 to its corresponding physical address, and displays the result.
8928 @deffn {Command} {add_help_text} 'command_name' 'help-string'
8929 Add or replace help text on the given @var{command_name}.
8932 @deffn {Command} {add_usage_text} 'command_name' 'help-string'
8933 Add or replace usage text on the given @var{command_name}.
8936 @node Architecture and Core Commands
8937 @chapter Architecture and Core Commands
8938 @cindex Architecture Specific Commands
8939 @cindex Core Specific Commands
8941 Most CPUs have specialized JTAG operations to support debugging.
8942 OpenOCD packages most such operations in its standard command framework.
8943 Some of those operations don't fit well in that framework, so they are
8944 exposed here as architecture or implementation (core) specific commands.
8946 @anchor{armhardwaretracing}
8947 @section ARM Hardware Tracing
8952 CPUs based on ARM cores may include standard tracing interfaces,
8953 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
8954 address and data bus trace records to a ``Trace Port''.
8958 Development-oriented boards will sometimes provide a high speed
8959 trace connector for collecting that data, when the particular CPU
8960 supports such an interface.
8961 (The standard connector is a 38-pin Mictor, with both JTAG
8962 and trace port support.)
8963 Those trace connectors are supported by higher end JTAG adapters
8964 and some logic analyzer modules; frequently those modules can
8965 buffer several megabytes of trace data.
8966 Configuring an ETM coupled to such an external trace port belongs
8967 in the board-specific configuration file.
8969 If the CPU doesn't provide an external interface, it probably
8970 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
8971 dedicated SRAM. 4KBytes is one common ETB size.
8972 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
8973 (target) configuration file, since it works the same on all boards.
8976 ETM support in OpenOCD doesn't seem to be widely used yet.
8979 ETM support may be buggy, and at least some @command{etm config}
8980 parameters should be detected by asking the ETM for them.
8982 ETM trigger events could also implement a kind of complex
8983 hardware breakpoint, much more powerful than the simple
8984 watchpoint hardware exported by EmbeddedICE modules.
8985 @emph{Such breakpoints can be triggered even when using the
8986 dummy trace port driver}.
8988 It seems like a GDB hookup should be possible,
8989 as well as tracing only during specific states
8990 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
8992 There should be GUI tools to manipulate saved trace data and help
8993 analyse it in conjunction with the source code.
8994 It's unclear how much of a common interface is shared
8995 with the current XScale trace support, or should be
8996 shared with eventual Nexus-style trace module support.
8998 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
8999 for ETM modules is available. The code should be able to
9000 work with some newer cores; but not all of them support
9001 this original style of JTAG access.
9004 @subsection ETM Configuration
9005 ETM setup is coupled with the trace port driver configuration.
9007 @deffn {Config Command} {etm config} target width mode clocking driver
9008 Declares the ETM associated with @var{target}, and associates it
9009 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
9011 Several of the parameters must reflect the trace port capabilities,
9012 which are a function of silicon capabilities (exposed later
9013 using @command{etm info}) and of what hardware is connected to
9014 that port (such as an external pod, or ETB).
9015 The @var{width} must be either 4, 8, or 16,
9016 except with ETMv3.0 and newer modules which may also
9017 support 1, 2, 24, 32, 48, and 64 bit widths.
9018 (With those versions, @command{etm info} also shows whether
9019 the selected port width and mode are supported.)
9021 The @var{mode} must be @option{normal}, @option{multiplexed},
9022 or @option{demultiplexed}.
9023 The @var{clocking} must be @option{half} or @option{full}.
9026 With ETMv3.0 and newer, the bits set with the @var{mode} and
9027 @var{clocking} parameters both control the mode.
9028 This modified mode does not map to the values supported by
9029 previous ETM modules, so this syntax is subject to change.
9033 You can see the ETM registers using the @command{reg} command.
9034 Not all possible registers are present in every ETM.
9035 Most of the registers are write-only, and are used to configure
9036 what CPU activities are traced.
9040 @deffn {Command} {etm info}
9041 Displays information about the current target's ETM.
9042 This includes resource counts from the @code{ETM_CONFIG} register,
9043 as well as silicon capabilities (except on rather old modules).
9044 from the @code{ETM_SYS_CONFIG} register.
9047 @deffn {Command} {etm status}
9048 Displays status of the current target's ETM and trace port driver:
9049 is the ETM idle, or is it collecting data?
9050 Did trace data overflow?
9054 @deffn {Command} {etm tracemode} [type context_id_bits cycle_accurate branch_output]
9055 Displays what data that ETM will collect.
9056 If arguments are provided, first configures that data.
9057 When the configuration changes, tracing is stopped
9058 and any buffered trace data is invalidated.
9061 @item @var{type} ... describing how data accesses are traced,
9062 when they pass any ViewData filtering that was set up.
9064 @option{none} (save nothing),
9065 @option{data} (save data),
9066 @option{address} (save addresses),
9067 @option{all} (save data and addresses)
9068 @item @var{context_id_bits} ... 0, 8, 16, or 32
9069 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
9070 cycle-accurate instruction tracing.
9071 Before ETMv3, enabling this causes much extra data to be recorded.
9072 @item @var{branch_output} ... @option{enable} or @option{disable}.
9073 Disable this unless you need to try reconstructing the instruction
9074 trace stream without an image of the code.
9078 @deffn {Command} {etm trigger_debug} (@option{enable}|@option{disable})
9079 Displays whether ETM triggering debug entry (like a breakpoint) is
9080 enabled or disabled, after optionally modifying that configuration.
9081 The default behaviour is @option{disable}.
9082 Any change takes effect after the next @command{etm start}.
9084 By using script commands to configure ETM registers, you can make the
9085 processor enter debug state automatically when certain conditions,
9086 more complex than supported by the breakpoint hardware, happen.
9089 @subsection ETM Trace Operation
9091 After setting up the ETM, you can use it to collect data.
9092 That data can be exported to files for later analysis.
9093 It can also be parsed with OpenOCD, for basic sanity checking.
9095 To configure what is being traced, you will need to write
9096 various trace registers using @command{reg ETM_*} commands.
9097 For the definitions of these registers, read ARM publication
9098 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
9099 Be aware that most of the relevant registers are write-only,
9100 and that ETM resources are limited. There are only a handful
9101 of address comparators, data comparators, counters, and so on.
9103 Examples of scenarios you might arrange to trace include:
9106 @item Code flow within a function, @emph{excluding} subroutines
9107 it calls. Use address range comparators to enable tracing
9108 for instruction access within that function's body.
9109 @item Code flow within a function, @emph{including} subroutines
9110 it calls. Use the sequencer and address comparators to activate
9111 tracing on an ``entered function'' state, then deactivate it by
9112 exiting that state when the function's exit code is invoked.
9113 @item Code flow starting at the fifth invocation of a function,
9114 combining one of the above models with a counter.
9115 @item CPU data accesses to the registers for a particular device,
9116 using address range comparators and the ViewData logic.
9117 @item Such data accesses only during IRQ handling, combining the above
9118 model with sequencer triggers which on entry and exit to the IRQ handler.
9119 @item @emph{... more}
9122 At this writing, September 2009, there are no Tcl utility
9123 procedures to help set up any common tracing scenarios.
9125 @deffn {Command} {etm analyze}
9126 Reads trace data into memory, if it wasn't already present.
9127 Decodes and prints the data that was collected.
9130 @deffn {Command} {etm dump} filename
9131 Stores the captured trace data in @file{filename}.
9134 @deffn {Command} {etm image} filename [base_address] [type]
9135 Opens an image file.
9138 @deffn {Command} {etm load} filename
9139 Loads captured trace data from @file{filename}.
9142 @deffn {Command} {etm start}
9143 Starts trace data collection.
9146 @deffn {Command} {etm stop}
9147 Stops trace data collection.
9150 @anchor{traceportdrivers}
9151 @subsection Trace Port Drivers
9153 To use an ETM trace port it must be associated with a driver.
9155 @deffn {Trace Port Driver} {dummy}
9156 Use the @option{dummy} driver if you are configuring an ETM that's
9157 not connected to anything (on-chip ETB or off-chip trace connector).
9158 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
9159 any trace data collection.}
9160 @deffn {Config Command} {etm_dummy config} target
9161 Associates the ETM for @var{target} with a dummy driver.
9165 @deffn {Trace Port Driver} {etb}
9166 Use the @option{etb} driver if you are configuring an ETM
9167 to use on-chip ETB memory.
9168 @deffn {Config Command} {etb config} target etb_tap
9169 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
9170 You can see the ETB registers using the @command{reg} command.
9172 @deffn {Command} {etb trigger_percent} [percent]
9173 This displays, or optionally changes, ETB behavior after the
9174 ETM's configured @emph{trigger} event fires.
9175 It controls how much more trace data is saved after the (single)
9176 trace trigger becomes active.
9179 @item The default corresponds to @emph{trace around} usage,
9180 recording 50 percent data before the event and the rest
9182 @item The minimum value of @var{percent} is 2 percent,
9183 recording almost exclusively data before the trigger.
9184 Such extreme @emph{trace before} usage can help figure out
9185 what caused that event to happen.
9186 @item The maximum value of @var{percent} is 100 percent,
9187 recording data almost exclusively after the event.
9188 This extreme @emph{trace after} usage might help sort out
9189 how the event caused trouble.
9191 @c REVISIT allow "break" too -- enter debug mode.
9196 @anchor{armcrosstrigger}
9197 @section ARM Cross-Trigger Interface
9200 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
9201 that connects event sources like tracing components or CPU cores with each
9202 other through a common trigger matrix (CTM). For ARMv8 architecture, a
9203 CTI is mandatory for core run control and each core has an individual
9204 CTI instance attached to it. OpenOCD has limited support for CTI using
9205 the @emph{cti} group of commands.
9207 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
9208 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
9209 @var{apn}. The @var{base_address} must match the base address of the CTI
9210 on the respective MEM-AP. All arguments are mandatory. This creates a
9211 new command @command{$cti_name} which is used for various purposes
9212 including additional configuration.
9215 @deffn {Command} {$cti_name enable} @option{on|off}
9216 Enable (@option{on}) or disable (@option{off}) the CTI.
9219 @deffn {Command} {$cti_name dump}
9220 Displays a register dump of the CTI.
9223 @deffn {Command} {$cti_name write} @var{reg_name} @var{value}
9224 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
9227 @deffn {Command} {$cti_name read} @var{reg_name}
9228 Print the value read from the CTI register with the symbolic name @var{reg_name}.
9231 @deffn {Command} {$cti_name ack} @var{event}
9232 Acknowledge a CTI @var{event}.
9235 @deffn {Command} {$cti_name channel} @var{channel_number} @var{operation}
9236 Perform a specific channel operation, the possible operations are:
9237 gate, ungate, set, clear and pulse
9240 @deffn {Command} {$cti_name testmode} @option{on|off}
9241 Enable (@option{on}) or disable (@option{off}) the integration test mode
9245 @deffn {Command} {cti names}
9246 Prints a list of names of all CTI objects created. This command is mainly
9247 useful in TCL scripting.
9250 @section Generic ARM
9253 These commands should be available on all ARM processors.
9254 They are available in addition to other core-specific
9255 commands that may be available.
9257 @deffn {Command} {arm core_state} [@option{arm}|@option{thumb}]
9258 Displays the core_state, optionally changing it to process
9259 either @option{arm} or @option{thumb} instructions.
9260 The target may later be resumed in the currently set core_state.
9261 (Processors may also support the Jazelle state, but
9262 that is not currently supported in OpenOCD.)
9265 @deffn {Command} {arm disassemble} address [count [@option{thumb}]]
9267 Disassembles @var{count} instructions starting at @var{address}.
9268 If @var{count} is not specified, a single instruction is disassembled.
9269 If @option{thumb} is specified, or the low bit of the address is set,
9270 Thumb2 (mixed 16/32-bit) instructions are used;
9271 else ARM (32-bit) instructions are used.
9272 (Processors may also support the Jazelle state, but
9273 those instructions are not currently understood by OpenOCD.)
9275 Note that all Thumb instructions are Thumb2 instructions,
9276 so older processors (without Thumb2 support) will still
9277 see correct disassembly of Thumb code.
9278 Also, ThumbEE opcodes are the same as Thumb2,
9279 with a handful of exceptions.
9280 ThumbEE disassembly currently has no explicit support.
9283 @deffn {Command} {arm mcr} pX op1 CRn CRm op2 value
9284 Write @var{value} to a coprocessor @var{pX} register
9285 passing parameters @var{CRn},
9286 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9287 and using the MCR instruction.
9288 (Parameter sequence matches the ARM instruction, but omits
9292 @deffn {Command} {arm mrc} pX coproc op1 CRn CRm op2
9293 Read a coprocessor @var{pX} register passing parameters @var{CRn},
9294 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9295 and the MRC instruction.
9296 Returns the result so it can be manipulated by Jim scripts.
9297 (Parameter sequence matches the ARM instruction, but omits
9301 @deffn {Command} {arm reg}
9302 Display a table of all banked core registers, fetching the current value from every
9303 core mode if necessary.
9306 @deffn {Command} {arm semihosting} [@option{enable}|@option{disable}]
9307 @cindex ARM semihosting
9308 Display status of semihosting, after optionally changing that status.
9310 Semihosting allows for code executing on an ARM target to use the
9311 I/O facilities on the host computer i.e. the system where OpenOCD
9312 is running. The target application must be linked against a library
9313 implementing the ARM semihosting convention that forwards operation
9314 requests by using a special SVC instruction that is trapped at the
9315 Supervisor Call vector by OpenOCD.
9318 @deffn {Command} {arm semihosting_cmdline} [@option{enable}|@option{disable}]
9319 @cindex ARM semihosting
9320 Set the command line to be passed to the debugger.
9323 arm semihosting_cmdline argv0 argv1 argv2 ...
9326 This option lets one set the command line arguments to be passed to
9327 the program. The first argument (argv0) is the program name in a
9328 standard C environment (argv[0]). Depending on the program (not much
9329 programs look at argv[0]), argv0 is ignored and can be any string.
9332 @deffn {Command} {arm semihosting_fileio} [@option{enable}|@option{disable}]
9333 @cindex ARM semihosting
9334 Display status of semihosting fileio, after optionally changing that
9337 Enabling this option forwards semihosting I/O to GDB process using the
9338 File-I/O remote protocol extension. This is especially useful for
9339 interacting with remote files or displaying console messages in the
9343 @deffn {Command} {arm semihosting_resexit} [@option{enable}|@option{disable}]
9344 @cindex ARM semihosting
9345 Enable resumable SEMIHOSTING_SYS_EXIT.
9347 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
9348 things are simple, the openocd process calls exit() and passes
9349 the value returned by the target.
9351 When SEMIHOSTING_SYS_EXIT is called during a debug session,
9352 by default execution returns to the debugger, leaving the
9353 debugger in a HALT state, similar to the state entered when
9354 encountering a break.
9356 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
9357 return normally, as any semihosting call, and do not break
9359 The standard allows this to happen, but the condition
9360 to trigger it is a bit obscure ("by performing an RDI_Execute
9361 request or equivalent").
9363 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
9364 this option (default: disabled).
9367 @deffn {Command} {arm semihosting_read_user_param}
9368 @cindex ARM semihosting
9369 Read parameter of the semihosting call from the target. Usable in
9370 semihosting-user-cmd-0x10* event handlers, returning a string.
9372 When the target makes semihosting call with operation number from range 0x100-
9373 0x107, an optional string parameter can be passed to the server. This parameter
9374 is valid during the run of the event handlers and is accessible with this
9378 @section ARMv4 and ARMv5 Architecture
9382 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
9383 and introduced core parts of the instruction set in use today.
9384 That includes the Thumb instruction set, introduced in the ARMv4T
9387 @subsection ARM7 and ARM9 specific commands
9391 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
9392 ARM9TDMI, ARM920T or ARM926EJ-S.
9393 They are available in addition to the ARM commands,
9394 and any other core-specific commands that may be available.
9396 @deffn {Command} {arm7_9 dbgrq} [@option{enable}|@option{disable}]
9397 Displays the value of the flag controlling use of the
9398 EmbeddedIce DBGRQ signal to force entry into debug mode,
9399 instead of breakpoints.
9400 If a boolean parameter is provided, first assigns that flag.
9403 safe for all but ARM7TDMI-S cores (like NXP LPC).
9404 This feature is enabled by default on most ARM9 cores,
9405 including ARM9TDMI, ARM920T, and ARM926EJ-S.
9408 @deffn {Command} {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
9410 Displays the value of the flag controlling use of the debug communications
9411 channel (DCC) to write larger (>128 byte) amounts of memory.
9412 If a boolean parameter is provided, first assigns that flag.
9414 DCC downloads offer a huge speed increase, but might be
9415 unsafe, especially with targets running at very low speeds. This command was introduced
9416 with OpenOCD rev. 60, and requires a few bytes of working area.
9419 @deffn {Command} {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
9420 Displays the value of the flag controlling use of memory writes and reads
9421 that don't check completion of the operation.
9422 If a boolean parameter is provided, first assigns that flag.
9424 This provides a huge speed increase, especially with USB JTAG
9425 cables (FT2232), but might be unsafe if used with targets running at very low
9426 speeds, like the 32kHz startup clock of an AT91RM9200.
9429 @subsection ARM9 specific commands
9432 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
9434 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
9436 @c 9-june-2009: tried this on arm920t, it didn't work.
9437 @c no-params always lists nothing caught, and that's how it acts.
9438 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
9439 @c versions have different rules about when they commit writes.
9441 @anchor{arm9vectorcatch}
9442 @deffn {Command} {arm9 vector_catch} [@option{all}|@option{none}|list]
9443 @cindex vector_catch
9444 Vector Catch hardware provides a sort of dedicated breakpoint
9445 for hardware events such as reset, interrupt, and abort.
9446 You can use this to conserve normal breakpoint resources,
9447 so long as you're not concerned with code that branches directly
9448 to those hardware vectors.
9450 This always finishes by listing the current configuration.
9451 If parameters are provided, it first reconfigures the
9452 vector catch hardware to intercept
9453 @option{all} of the hardware vectors,
9454 @option{none} of them,
9455 or a list with one or more of the following:
9456 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
9457 @option{irq} @option{fiq}.
9460 @subsection ARM920T specific commands
9463 These commands are available to ARM920T based CPUs,
9464 which are implementations of the ARMv4T architecture
9465 built using the ARM9TDMI integer core.
9466 They are available in addition to the ARM, ARM7/ARM9,
9469 @deffn {Command} {arm920t cache_info}
9470 Print information about the caches found. This allows to see whether your target
9471 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
9474 @deffn {Command} {arm920t cp15} regnum [value]
9475 Display cp15 register @var{regnum};
9476 else if a @var{value} is provided, that value is written to that register.
9477 This uses "physical access" and the register number is as
9478 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
9479 (Not all registers can be written.)
9482 @deffn {Command} {arm920t read_cache} filename
9483 Dump the content of ICache and DCache to a file named @file{filename}.
9486 @deffn {Command} {arm920t read_mmu} filename
9487 Dump the content of the ITLB and DTLB to a file named @file{filename}.
9490 @subsection ARM926ej-s specific commands
9493 These commands are available to ARM926ej-s based CPUs,
9494 which are implementations of the ARMv5TEJ architecture
9495 based on the ARM9EJ-S integer core.
9496 They are available in addition to the ARM, ARM7/ARM9,
9499 The Feroceon cores also support these commands, although
9500 they are not built from ARM926ej-s designs.
9502 @deffn {Command} {arm926ejs cache_info}
9503 Print information about the caches found.
9506 @subsection ARM966E specific commands
9509 These commands are available to ARM966 based CPUs,
9510 which are implementations of the ARMv5TE architecture.
9511 They are available in addition to the ARM, ARM7/ARM9,
9514 @deffn {Command} {arm966e cp15} regnum [value]
9515 Display cp15 register @var{regnum};
9516 else if a @var{value} is provided, that value is written to that register.
9517 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
9519 There is no current control over bits 31..30 from that table,
9520 as required for BIST support.
9523 @subsection XScale specific commands
9526 Some notes about the debug implementation on the XScale CPUs:
9528 The XScale CPU provides a special debug-only mini-instruction cache
9529 (mini-IC) in which exception vectors and target-resident debug handler
9530 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
9531 must point vector 0 (the reset vector) to the entry of the debug
9532 handler. However, this means that the complete first cacheline in the
9533 mini-IC is marked valid, which makes the CPU fetch all exception
9534 handlers from the mini-IC, ignoring the code in RAM.
9536 To address this situation, OpenOCD provides the @code{xscale
9537 vector_table} command, which allows the user to explicitly write
9538 individual entries to either the high or low vector table stored in
9541 It is recommended to place a pc-relative indirect branch in the vector
9542 table, and put the branch destination somewhere in memory. Doing so
9543 makes sure the code in the vector table stays constant regardless of
9544 code layout in memory:
9547 ldr pc,[pc,#0x100-8]
9548 ldr pc,[pc,#0x100-8]
9549 ldr pc,[pc,#0x100-8]
9550 ldr pc,[pc,#0x100-8]
9551 ldr pc,[pc,#0x100-8]
9552 ldr pc,[pc,#0x100-8]
9553 ldr pc,[pc,#0x100-8]
9554 ldr pc,[pc,#0x100-8]
9556 .long real_reset_vector
9557 .long real_ui_handler
9558 .long real_swi_handler
9560 .long real_data_abort
9561 .long 0 /* unused */
9562 .long real_irq_handler
9563 .long real_fiq_handler
9566 Alternatively, you may choose to keep some or all of the mini-IC
9567 vector table entries synced with those written to memory by your
9568 system software. The mini-IC can not be modified while the processor
9569 is executing, but for each vector table entry not previously defined
9570 using the @code{xscale vector_table} command, OpenOCD will copy the
9571 value from memory to the mini-IC every time execution resumes from a
9572 halt. This is done for both high and low vector tables (although the
9573 table not in use may not be mapped to valid memory, and in this case
9574 that copy operation will silently fail). This means that you will
9575 need to briefly halt execution at some strategic point during system
9576 start-up; e.g., after the software has initialized the vector table,
9577 but before exceptions are enabled. A breakpoint can be used to
9578 accomplish this once the appropriate location in the start-up code has
9579 been identified. A watchpoint over the vector table region is helpful
9580 in finding the location if you're not sure. Note that the same
9581 situation exists any time the vector table is modified by the system
9584 The debug handler must be placed somewhere in the address space using
9585 the @code{xscale debug_handler} command. The allowed locations for the
9586 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
9587 0xfffff800). The default value is 0xfe000800.
9589 XScale has resources to support two hardware breakpoints and two
9590 watchpoints. However, the following restrictions on watchpoint
9591 functionality apply: (1) the value and mask arguments to the @code{wp}
9592 command are not supported, (2) the watchpoint length must be a
9593 power of two and not less than four, and can not be greater than the
9594 watchpoint address, and (3) a watchpoint with a length greater than
9595 four consumes all the watchpoint hardware resources. This means that
9596 at any one time, you can have enabled either two watchpoints with a
9597 length of four, or one watchpoint with a length greater than four.
9599 These commands are available to XScale based CPUs,
9600 which are implementations of the ARMv5TE architecture.
9602 @deffn {Command} {xscale analyze_trace}
9603 Displays the contents of the trace buffer.
9606 @deffn {Command} {xscale cache_clean_address} address
9607 Changes the address used when cleaning the data cache.
9610 @deffn {Command} {xscale cache_info}
9611 Displays information about the CPU caches.
9614 @deffn {Command} {xscale cp15} regnum [value]
9615 Display cp15 register @var{regnum};
9616 else if a @var{value} is provided, that value is written to that register.
9619 @deffn {Command} {xscale debug_handler} target address
9620 Changes the address used for the specified target's debug handler.
9623 @deffn {Command} {xscale dcache} [@option{enable}|@option{disable}]
9624 Enables or disable the CPU's data cache.
9627 @deffn {Command} {xscale dump_trace} filename
9628 Dumps the raw contents of the trace buffer to @file{filename}.
9631 @deffn {Command} {xscale icache} [@option{enable}|@option{disable}]
9632 Enables or disable the CPU's instruction cache.
9635 @deffn {Command} {xscale mmu} [@option{enable}|@option{disable}]
9636 Enables or disable the CPU's memory management unit.
9639 @deffn {Command} {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
9640 Displays the trace buffer status, after optionally
9641 enabling or disabling the trace buffer
9642 and modifying how it is emptied.
9645 @deffn {Command} {xscale trace_image} filename [offset [type]]
9646 Opens a trace image from @file{filename}, optionally rebasing
9647 its segment addresses by @var{offset}.
9648 The image @var{type} may be one of
9649 @option{bin} (binary), @option{ihex} (Intel hex),
9650 @option{elf} (ELF file), @option{s19} (Motorola s19),
9651 @option{mem}, or @option{builder}.
9654 @anchor{xscalevectorcatch}
9655 @deffn {Command} {xscale vector_catch} [mask]
9656 @cindex vector_catch
9657 Display a bitmask showing the hardware vectors to catch.
9658 If the optional parameter is provided, first set the bitmask to that value.
9660 The mask bits correspond with bit 16..23 in the DCSR:
9663 0x02 Trap Undefined Instructions
9664 0x04 Trap Software Interrupt
9665 0x08 Trap Prefetch Abort
9666 0x10 Trap Data Abort
9673 @deffn {Command} {xscale vector_table} [(@option{low}|@option{high}) index value]
9674 @cindex vector_table
9676 Set an entry in the mini-IC vector table. There are two tables: one for
9677 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
9678 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
9679 points to the debug handler entry and can not be overwritten.
9680 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
9682 Without arguments, the current settings are displayed.
9686 @section ARMv6 Architecture
9689 @subsection ARM11 specific commands
9692 @deffn {Command} {arm11 memwrite burst} [@option{enable}|@option{disable}]
9693 Displays the value of the memwrite burst-enable flag,
9694 which is enabled by default.
9695 If a boolean parameter is provided, first assigns that flag.
9696 Burst writes are only used for memory writes larger than 1 word.
9697 They improve performance by assuming that the CPU has read each data
9698 word over JTAG and completed its write before the next word arrives,
9699 instead of polling for a status flag to verify that completion.
9700 This is usually safe, because JTAG runs much slower than the CPU.
9703 @deffn {Command} {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
9704 Displays the value of the memwrite error_fatal flag,
9705 which is enabled by default.
9706 If a boolean parameter is provided, first assigns that flag.
9707 When set, certain memory write errors cause earlier transfer termination.
9710 @deffn {Command} {arm11 step_irq_enable} [@option{enable}|@option{disable}]
9711 Displays the value of the flag controlling whether
9712 IRQs are enabled during single stepping;
9713 they are disabled by default.
9714 If a boolean parameter is provided, first assigns that.
9717 @deffn {Command} {arm11 vcr} [value]
9718 @cindex vector_catch
9719 Displays the value of the @emph{Vector Catch Register (VCR)},
9720 coprocessor 14 register 7.
9721 If @var{value} is defined, first assigns that.
9723 Vector Catch hardware provides dedicated breakpoints
9724 for certain hardware events.
9725 The specific bit values are core-specific (as in fact is using
9726 coprocessor 14 register 7 itself) but all current ARM11
9727 cores @emph{except the ARM1176} use the same six bits.
9730 @section ARMv7 and ARMv8 Architecture
9734 @subsection ARMv7-A specific commands
9737 @deffn {Command} {cortex_a cache_info}
9738 display information about target caches
9741 @deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
9742 Work around issues with software breakpoints when the program text is
9743 mapped read-only by the operating system. This option sets the CP15 DACR
9744 to "all-manager" to bypass MMU permission checks on memory access.
9748 @deffn {Command} {cortex_a dbginit}
9749 Initialize core debug
9750 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9753 @deffn {Command} {cortex_a smp} [on|off]
9754 Display/set the current SMP mode
9757 @deffn {Command} {cortex_a smp_gdb} [core_id]
9758 Display/set the current core displayed in GDB
9761 @deffn {Command} {cortex_a maskisr} [@option{on}|@option{off}]
9762 Selects whether interrupts will be processed when single stepping
9765 @deffn {Command} {cache_config l2x} [base way]
9769 @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
9770 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
9771 memory location @var{address}. When dumping the table from @var{address}, print at most
9772 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
9773 possible (4096) entries are printed.
9776 @subsection ARMv7-R specific commands
9779 @deffn {Command} {cortex_r4 dbginit}
9780 Initialize core debug
9781 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9784 @deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
9785 Selects whether interrupts will be processed when single stepping
9789 @subsection ARM CoreSight TPIU and SWO specific commands
9795 ARM CoreSight provides several modules to generate debugging
9796 information internally (ITM, DWT and ETM). Their output is directed
9797 through TPIU or SWO modules to be captured externally either on an SWO pin (this
9798 configuration is called SWV) or on a synchronous parallel trace port.
9800 ARM CoreSight provides independent HW blocks named TPIU and SWO each with its
9801 own functionality. Embedded in Cortex-M3 and M4, ARM provides an optional HW
9802 block that includes both TPIU and SWO functionalities and is again named TPIU,
9803 which causes quite some confusion.
9804 The registers map of all the TPIU and SWO implementations allows using a single
9805 driver that detects at runtime the features available.
9807 The @command{tpiu} is used for either TPIU or SWO.
9808 A convenient alias @command{swo} is available to help distinguish, in scripts,
9809 the commands for SWO from the commands for TPIU.
9811 @deffn {Command} {swo} ...
9812 Alias of @command{tpiu ...}. Can be used in scripts to distinguish the commands
9813 for SWO from the commands for TPIU.
9816 @deffn {Command} {tpiu create} tpiu_name configparams...
9817 Creates a TPIU or a SWO object. The two commands are equivalent.
9818 Add the object in a list and add new commands (@command{@var{tpiu_name}})
9819 which are used for various purposes including additional configuration.
9822 @item @var{tpiu_name} -- the name of the TPIU or SWO object.
9823 This name is also used to create the object's command, referred to here
9824 as @command{$tpiu_name}, and in other places where the TPIU or SWO needs to be identified.
9825 @item @var{configparams} -- all parameters accepted by @command{$tpiu_name configure} are permitted.
9827 You @emph{must} set here the AP and MEM_AP base_address through @code{-dap @var{dap_name}},
9828 @code{-ap-num @var{ap_number}} and @code{-baseaddr @var{base_address}}.
9832 @deffn {Command} {tpiu names}
9833 Lists all the TPIU or SWO objects created so far. The two commands are equivalent.
9836 @deffn {Command} {tpiu init}
9837 Initialize all registered TPIU and SWO. The two commands are equivalent.
9838 These commands are used internally during initialization. They can be issued
9839 at any time after the initialization, too.
9842 @deffn {Command} {$tpiu_name cget} queryparm
9843 Each configuration parameter accepted by @command{$tpiu_name configure} can be
9844 individually queried, to return its current value.
9845 The @var{queryparm} is a parameter name accepted by that command, such as @code{-dap}.
9848 @deffn {Command} {$tpiu_name configure} configparams...
9849 The options accepted by this command may also be specified as parameters
9850 to @command{tpiu create}. Their values can later be queried one at a time by
9851 using the @command{$tpiu_name cget} command.
9854 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
9855 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
9857 @item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU,
9858 @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
9860 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
9861 to access the TPIU in the DAP AP memory space.
9863 @item @code{-protocol} (@option{sync}|@option{uart}|@option{manchester}) -- sets the
9864 protocol used for trace data:
9866 @item @option{sync} -- synchronous parallel trace output mode, using @var{port_width}
9867 data bits (default);
9868 @item @option{uart} -- use asynchronous SWO mode with NRZ (same as regular UART 8N1) coding;
9869 @item @option{manchester} -- use asynchronous SWO mode with Manchester coding.
9872 @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler,
9873 a TCL string which is evaluated when the event is triggered. The events
9874 @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable}
9875 are defined for TPIU/SWO.
9876 A typical use case for the event @code{pre-enable} is to enable the trace clock
9879 @item @code{-output} (@option{external}|@option{:}@var{port}|@var{filename}|@option{-}) -- specifies
9880 the destination of the trace data:
9882 @item @option{external} -- configure TPIU/SWO to let user capture trace
9883 output externally, either with an additional UART or with a logic analyzer (default);
9884 @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data
9885 and forward it to @command{tcl_trace} command;
9886 @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather
9887 trace data, open a TCP server at port @var{port} and send the trace data to
9888 each connected client;
9889 @item @var{filename} -- configure TPIU/SWO and debug adapter to
9890 gather trace data and append it to @var{filename}, which can be
9891 either a regular file or a named pipe.
9894 @item @code{-traceclk} @var{TRACECLKIN_freq} -- mandatory parameter.
9895 Specifies the frequency in Hz of the trace clock. For the TPIU embedded in
9896 Cortex-M3 or M4, this is usually the same frequency as HCLK. For protocol
9897 @option{sync} this is twice the frequency of the pin data rate.
9899 @item @code{-pin-freq} @var{trace_freq} -- specifies the expected data rate
9900 in Hz of the SWO pin. Parameter used only on protocols @option{uart} and
9901 @option{manchester}. Can be omitted to let the adapter driver select the
9902 maximum supported rate automatically.
9904 @item @code{-port-width} @var{port_width} -- sets to @var{port_width} the width
9905 of the synchronous parallel port used for trace output. Parameter used only on
9906 protocol @option{sync}. If not specified, default value is @var{1}.
9908 @item @code{-formatter} (@option{0}|@option{1}) -- specifies if the formatter
9909 should be enabled. Parameter used only on protocol @option{sync}. If not specified,
9910 default value is @var{0}.
9914 @deffn {Command} {$tpiu_name enable}
9915 Uses the parameters specified by the previous @command{$tpiu_name configure}
9916 to configure and enable the TPIU or the SWO.
9917 If required, the adapter is also configured and enabled to receive the trace
9919 This command can be used before @command{init}, but it will take effect only
9920 after the @command{init}.
9923 @deffn {Command} {$tpiu_name disable}
9924 Disable the TPIU or the SWO, terminating the receiving of the trace data.
9931 @item STM32L152 board is programmed with an application that configures
9932 PLL to provide core clock with 24MHz frequency; to use ITM output it's
9935 #include <libopencm3/cm3/itm.h>
9940 (the most obvious way is to use the first stimulus port for printf,
9941 for that this ITM_STIM8 assignment can be used inside _write(); to make it
9942 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
9943 ITM_STIM_FIFOREADY));});
9944 @item An FT2232H UART is connected to the SWO pin of the board;
9945 @item Commands to configure UART for 12MHz baud rate:
9947 $ setserial /dev/ttyUSB1 spd_cust divisor 5
9948 $ stty -F /dev/ttyUSB1 38400
9950 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
9951 baud with our custom divisor to get 12MHz)
9952 @item @code{itmdump -f /dev/ttyUSB1 -d1}
9953 @item OpenOCD invocation line:
9955 openocd -f interface/stlink.cfg \
9956 -c "transport select hla_swd" \
9957 -f target/stm32l1.cfg \
9958 -c "stm32l1.tpiu configure -protocol uart" \
9959 -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
9960 -c "stm32l1.tpiu enable"
9964 @subsection ARMv7-M specific commands
9971 @deffn {Command} {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
9972 Enable or disable trace output for ITM stimulus @var{port} (counting
9973 from 0). Port 0 is enabled on target creation automatically.
9976 @deffn {Command} {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
9977 Enable or disable trace output for all ITM stimulus ports.
9980 @subsection Cortex-M specific commands
9983 @deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
9984 Control masking (disabling) interrupts during target step/resume.
9986 The @option{auto} option handles interrupts during stepping in a way that they
9987 get served but don't disturb the program flow. The step command first allows
9988 pending interrupt handlers to execute, then disables interrupts and steps over
9989 the next instruction where the core was halted. After the step interrupts
9990 are enabled again. If the interrupt handlers don't complete within 500ms,
9991 the step command leaves with the core running.
9993 The @option{steponly} option disables interrupts during single-stepping but
9994 enables them during normal execution. This can be used as a partial workaround
9995 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
9996 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
9998 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
9999 option. If no breakpoint is available at the time of the step, then the step
10000 is taken with interrupts enabled, i.e. the same way the @option{off} option
10003 Default is @option{auto}.
10006 @deffn {Command} {cortex_m vector_catch} [@option{all}|@option{none}|list]
10007 @cindex vector_catch
10008 Vector Catch hardware provides dedicated breakpoints
10009 for certain hardware events.
10011 Parameters request interception of
10012 @option{all} of these hardware event vectors,
10013 @option{none} of them,
10014 or one or more of the following:
10015 @option{hard_err} for a HardFault exception;
10016 @option{mm_err} for a MemManage exception;
10017 @option{bus_err} for a BusFault exception;
10019 @option{state_err},
10020 @option{chk_err}, or
10021 @option{nocp_err} for various UsageFault exceptions; or
10023 If NVIC setup code does not enable them,
10024 MemManage, BusFault, and UsageFault exceptions
10025 are mapped to HardFault.
10026 UsageFault checks for
10027 divide-by-zero and unaligned access
10028 must also be explicitly enabled.
10030 This finishes by listing the current vector catch configuration.
10033 @deffn {Command} {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
10034 Control reset handling if hardware srst is not fitted
10035 @xref{reset_config,,reset_config}.
10038 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
10039 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
10042 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
10043 This however has the disadvantage of only resetting the core, all peripherals
10044 are unaffected. A solution would be to use a @code{reset-init} event handler
10045 to manually reset the peripherals.
10046 @xref{targetevents,,Target Events}.
10048 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
10052 @subsection ARMv8-A specific commands
10056 @deffn {Command} {aarch64 cache_info}
10057 Display information about target caches
10060 @deffn {Command} {aarch64 dbginit}
10061 This command enables debugging by clearing the OS Lock and sticky power-down and reset
10062 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
10063 target code relies on. In a configuration file, the command would typically be called from a
10064 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
10065 However, normally it is not necessary to use the command at all.
10068 @deffn {Command} {aarch64 disassemble} address [count]
10069 @cindex disassemble
10070 Disassembles @var{count} instructions starting at @var{address}.
10071 If @var{count} is not specified, a single instruction is disassembled.
10074 @deffn {Command} {aarch64 smp} [on|off]
10075 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
10076 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
10077 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
10078 group. With SMP handling disabled, all targets need to be treated individually.
10081 @deffn {Command} {aarch64 maskisr} [@option{on}|@option{off}]
10082 Selects whether interrupts will be processed when single stepping. The default configuration is
10086 @deffn {Command} {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
10087 Cause @command{$target_name} to halt when an exception is taken. Any combination of
10088 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
10089 @command{$target_name} will halt before taking the exception. In order to resume
10090 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
10091 Issuing the command without options prints the current configuration.
10094 @section EnSilica eSi-RISC Architecture
10096 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
10097 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
10099 @subsection eSi-RISC Configuration
10101 @deffn {Command} {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
10102 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
10103 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
10106 @deffn {Command} {esirisc hwdc} (@option{all}|@option{none}|mask ...)
10107 Configure hardware debug control. The HWDC register controls which exceptions return
10108 control back to the debugger. Possible masks are @option{all}, @option{none},
10109 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
10110 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
10113 @subsection eSi-RISC Operation
10115 @deffn {Command} {esirisc flush_caches}
10116 Flush instruction and data caches. This command requires that the target is halted
10117 when the command is issued and configured with an instruction or data cache.
10120 @subsection eSi-Trace Configuration
10122 eSi-RISC targets may be configured with support for instruction tracing. Trace
10123 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
10124 is typically employed to move trace data off-device using a high-speed
10125 peripheral (eg. SPI). Collected trace data is encoded in one of three different
10126 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
10127 fifo} must be issued along with @command{esirisc trace format} before trace data
10130 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
10131 needed, collected trace data can be dumped to a file and processed by external
10135 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
10136 for this issue is to configure DMA to copy trace data to an in-memory buffer,
10137 which can then be passed to the @command{esirisc trace analyze} and
10138 @command{esirisc trace dump} commands.
10140 It is possible to corrupt trace data when using a FIFO if the peripheral
10141 responsible for draining data from the FIFO is not fast enough. This can be
10142 managed by enabling flow control, however this can impact timing-sensitive
10143 software operation on the CPU.
10146 @deffn {Command} {esirisc trace buffer} address size [@option{wrap}]
10147 Configure trace buffer using the provided address and size. If the @option{wrap}
10148 option is specified, trace collection will continue once the end of the buffer
10149 is reached. By default, wrap is disabled.
10152 @deffn {Command} {esirisc trace fifo} address
10153 Configure trace FIFO using the provided address.
10156 @deffn {Command} {esirisc trace flow_control} (@option{enable}|@option{disable})
10157 Enable or disable stalling the CPU to collect trace data. By default, flow
10158 control is disabled.
10161 @deffn {Command} {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
10162 Configure trace format and number of PC bits to be captured. @option{pc_bits}
10163 must be within 1 and 31 as the LSB is not collected. If external tooling is used
10164 to analyze collected trace data, these values must match.
10166 Supported trace formats:
10168 @item @option{full} capture full trace data, allowing execution history and
10169 timing to be determined.
10170 @item @option{branch} capture taken branch instructions and branch target
10172 @item @option{icache} capture instruction cache misses.
10176 @deffn {Command} {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
10177 Configure trigger start condition using the provided start data and mask. A
10178 brief description of each condition is provided below; for more detail on how
10179 these values are used, see the eSi-RISC Architecture Manual.
10181 Supported conditions:
10183 @item @option{none} manual tracing (see @command{esirisc trace start}).
10184 @item @option{pc} start tracing if the PC matches start data and mask.
10185 @item @option{load} start tracing if the effective address of a load
10186 instruction matches start data and mask.
10187 @item @option{store} start tracing if the effective address of a store
10188 instruction matches start data and mask.
10189 @item @option{exception} start tracing if the EID of an exception matches start
10191 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
10192 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
10193 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
10194 @item @option{high} start tracing when an external signal is a logical high.
10195 @item @option{low} start tracing when an external signal is a logical low.
10199 @deffn {Command} {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
10200 Configure trigger stop condition using the provided stop data and mask. A brief
10201 description of each condition is provided below; for more detail on how these
10202 values are used, see the eSi-RISC Architecture Manual.
10204 Supported conditions:
10206 @item @option{none} manual tracing (see @command{esirisc trace stop}).
10207 @item @option{pc} stop tracing if the PC matches stop data and mask.
10208 @item @option{load} stop tracing if the effective address of a load
10209 instruction matches stop data and mask.
10210 @item @option{store} stop tracing if the effective address of a store
10211 instruction matches stop data and mask.
10212 @item @option{exception} stop tracing if the EID of an exception matches stop
10214 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
10215 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
10216 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
10220 @deffn {Command} {esirisc trace trigger delay} (@option{trigger}) [cycles]
10221 Configure trigger start/stop delay in clock cycles.
10223 Supported triggers:
10225 @item @option{none} no delay to start or stop collection.
10226 @item @option{start} delay @option{cycles} after trigger to start collection.
10227 @item @option{stop} delay @option{cycles} after trigger to stop collection.
10228 @item @option{both} delay @option{cycles} after both triggers to start or stop
10233 @subsection eSi-Trace Operation
10235 @deffn {Command} {esirisc trace init}
10236 Initialize trace collection. This command must be called any time the
10237 configuration changes. If a trace buffer has been configured, the contents will
10238 be overwritten when trace collection starts.
10241 @deffn {Command} {esirisc trace info}
10242 Display trace configuration.
10245 @deffn {Command} {esirisc trace status}
10246 Display trace collection status.
10249 @deffn {Command} {esirisc trace start}
10250 Start manual trace collection.
10253 @deffn {Command} {esirisc trace stop}
10254 Stop manual trace collection.
10257 @deffn {Command} {esirisc trace analyze} [address size]
10258 Analyze collected trace data. This command may only be used if a trace buffer
10259 has been configured. If a trace FIFO has been configured, trace data must be
10260 copied to an in-memory buffer identified by the @option{address} and
10261 @option{size} options using DMA.
10264 @deffn {Command} {esirisc trace dump} [address size] @file{filename}
10265 Dump collected trace data to file. This command may only be used if a trace
10266 buffer has been configured. If a trace FIFO has been configured, trace data must
10267 be copied to an in-memory buffer identified by the @option{address} and
10268 @option{size} options using DMA.
10271 @section Intel Architecture
10273 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
10274 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
10275 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
10276 software debug and the CLTAP is used for SoC level operations.
10277 Useful docs are here: https://communities.intel.com/community/makers/documentation
10279 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
10280 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
10281 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
10284 @subsection x86 32-bit specific commands
10285 The three main address spaces for x86 are memory, I/O and configuration space.
10286 These commands allow a user to read and write to the 64Kbyte I/O address space.
10288 @deffn {Command} {x86_32 idw} address
10289 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
10292 @deffn {Command} {x86_32 idh} address
10293 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
10296 @deffn {Command} {x86_32 idb} address
10297 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
10300 @deffn {Command} {x86_32 iww} address
10301 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
10304 @deffn {Command} {x86_32 iwh} address
10305 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
10308 @deffn {Command} {x86_32 iwb} address
10309 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
10312 @section OpenRISC Architecture
10314 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
10315 configured with any of the TAP / Debug Unit available.
10317 @subsection TAP and Debug Unit selection commands
10318 @deffn {Command} {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
10319 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
10321 @deffn {Command} {du_select} (@option{adv}|@option{mohor}) [option]
10322 Select between the Advanced Debug Interface and the classic one.
10324 An option can be passed as a second argument to the debug unit.
10326 When using the Advanced Debug Interface, option = 1 means the RTL core is
10327 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
10328 between bytes while doing read or write bursts.
10331 @subsection Registers commands
10332 @deffn {Command} {addreg} [name] [address] [feature] [reg_group]
10333 Add a new register in the cpu register list. This register will be
10334 included in the generated target descriptor file.
10336 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
10338 @strong{[reg_group]} can be anything. The default register list defines "system",
10339 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
10340 and "timer" groups.
10344 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
10349 @section RISC-V Architecture
10351 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
10352 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
10353 harts. (It's possible to increase this limit to 1024 by changing
10354 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
10355 Debug Specification, but there is also support for legacy targets that
10356 implement version 0.11.
10358 @subsection RISC-V Terminology
10360 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
10361 another hart, or may be a separate core. RISC-V treats those the same, and
10362 OpenOCD exposes each hart as a separate core.
10364 @subsection Vector Registers
10366 For harts that implement the vector extension, OpenOCD provides access to the
10367 relevant CSRs, as well as the vector registers (v0-v31). The size of each
10368 vector register is dependent on the value of vlenb. RISC-V allows each vector
10369 register to be divided into selected-width elements, and this division can be
10370 changed at run-time. Because OpenOCD cannot update register definitions at
10371 run-time, it exposes each vector register to gdb as a union of fields of
10372 vectors so that users can easily access individual bytes, shorts, words,
10373 longs, and quads inside each vector register. It is left to gdb or
10374 higher-level debuggers to present this data in a more intuitive format.
10376 In the XML register description, the vector registers (when vlenb=16) look as
10380 <feature name="org.gnu.gdb.riscv.vector">
10381 <vector id="bytes" type="uint8" count="16"/>
10382 <vector id="shorts" type="uint16" count="8"/>
10383 <vector id="words" type="uint32" count="4"/>
10384 <vector id="longs" type="uint64" count="2"/>
10385 <vector id="quads" type="uint128" count="1"/>
10386 <union id="riscv_vector">
10387 <field name="b" type="bytes"/>
10388 <field name="s" type="shorts"/>
10389 <field name="w" type="words"/>
10390 <field name="l" type="longs"/>
10391 <field name="q" type="quads"/>
10393 <reg name="v0" bitsize="128" regnum="4162" save-restore="no"
10394 type="riscv_vector" group="vector"/>
10396 <reg name="v31" bitsize="128" regnum="4193" save-restore="no"
10397 type="riscv_vector" group="vector"/>
10401 @subsection RISC-V Debug Configuration Commands
10403 @deffn {Config Command} {riscv expose_csrs} n[-m|=name] [...]
10404 Configure which CSRs to expose in addition to the standard ones. The CSRs to expose
10405 can be specified as individual register numbers or register ranges (inclusive). For the
10406 individually listed CSRs, a human-readable name can optionally be set using the @code{n=name}
10407 syntax, which will get @code{csr_} prepended to it. If no name is provided, the register will be
10408 named @code{csr<n>}.
10410 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
10411 and then only if the corresponding extension appears to be implemented. This
10412 command can be used if OpenOCD gets this wrong, or if the target implements custom
10416 # Expose a single RISC-V CSR number 128 under the name "csr128":
10417 $_TARGETNAME expose_csrs 128
10419 # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
10420 $_TARGETNAME expose_csrs 128-132
10422 # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
10423 $_TARGETNAME expose_csrs 1996=myregister
10427 @deffn {Config Command} {riscv expose_custom} n[-m|=name] [...]
10428 The RISC-V Debug Specification allows targets to expose custom registers
10429 through abstract commands. (See Section 3.5.1.1 in that document.) This command
10430 configures individual registers or register ranges (inclusive) that shall be exposed.
10431 Number 0 indicates the first custom register, whose abstract command number is 0xc000.
10432 For individually listed registers, a human-readable name can be optionally provided
10433 using the @code{n=name} syntax, which will get @code{custom_} prepended to it. If no
10434 name is provided, the register will be named @code{custom<n>}.
10437 # Expose one RISC-V custom register with number 0xc010 (0xc000 + 16)
10438 # under the name "custom16":
10439 $_TARGETNAME expose_custom 16
10441 # Expose a range of RISC-V custom registers with numbers 0xc010 .. 0xc018
10442 # (0xc000+16 .. 0xc000+24) under the names "custom16" through "custom24":
10443 $_TARGETNAME expose_custom 16-24
10445 # Expose one RISC-V custom register with number 0xc020 (0xc000 + 32) under
10446 # user-defined name "custom_myregister":
10447 $_TARGETNAME expose_custom 32=myregister
10451 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
10452 Set the wall-clock timeout (in seconds) for individual commands. The default
10453 should work fine for all but the slowest targets (eg. simulators).
10456 @deffn {Command} {riscv set_reset_timeout_sec} [seconds]
10457 Set the maximum time to wait for a hart to come out of reset after reset is
10461 @deffn {Command} {riscv set_scratch_ram} none|[address]
10462 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
10463 This is used to access 64-bit floating point registers on 32-bit targets.
10466 @deffn Command {riscv set_mem_access} method1 [method2] [method3]
10467 Specify which RISC-V memory access method(s) shall be used, and in which order
10468 of priority. At least one method must be specified.
10470 Available methods are:
10472 @item @code{progbuf} - Use RISC-V Debug Program Buffer to access memory.
10473 @item @code{sysbus} - Access memory via RISC-V Debug System Bus interface.
10474 @item @code{abstract} - Access memory via RISC-V Debug abstract commands.
10477 By default, all memory access methods are enabled in the following order:
10478 @code{progbuf sysbus abstract}.
10480 This command can be used to change the memory access methods if the default
10481 behavior is not suitable for a particular target.
10484 @deffn {Command} {riscv set_enable_virtual} on|off
10485 When on, memory accesses are performed on physical or virtual memory depending
10486 on the current system configuration. When off (default), all memory accessses are performed
10487 on physical memory.
10490 @deffn {Command} {riscv set_enable_virt2phys} on|off
10491 When on (default), memory accesses are performed on physical or virtual memory
10492 depending on the current satp configuration. When off, all memory accessses are
10493 performed on physical memory.
10496 @deffn {Command} {riscv resume_order} normal|reversed
10497 Some software assumes all harts are executing nearly continuously. Such
10498 software may be sensitive to the order that harts are resumed in. On harts
10499 that don't support hasel, this option allows the user to choose the order the
10500 harts are resumed in. If you are using this option, it's probably masking a
10501 race condition problem in your code.
10503 Normal order is from lowest hart index to highest. This is the default
10504 behavior. Reversed order is from highest hart index to lowest.
10507 @deffn {Command} {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
10508 Set the IR value for the specified JTAG register. This is useful, for
10509 example, when using the existing JTAG interface on a Xilinx FPGA by
10510 way of BSCANE2 primitives that only permit a limited selection of IR
10513 When utilizing version 0.11 of the RISC-V Debug Specification,
10514 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
10515 and DBUS registers, respectively.
10518 @deffn {Command} {riscv use_bscan_tunnel} value
10519 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
10520 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
10523 @deffn {Command} {riscv set_ebreakm} on|off
10524 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
10525 OpenOCD. When off, they generate a breakpoint exception handled internally.
10528 @deffn {Command} {riscv set_ebreaks} on|off
10529 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
10530 OpenOCD. When off, they generate a breakpoint exception handled internally.
10533 @deffn {Command} {riscv set_ebreaku} on|off
10534 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
10535 OpenOCD. When off, they generate a breakpoint exception handled internally.
10538 @subsection RISC-V Authentication Commands
10540 The following commands can be used to authenticate to a RISC-V system. Eg. a
10541 trivial challenge-response protocol could be implemented as follows in a
10542 configuration file, immediately following @command{init}:
10544 set challenge [riscv authdata_read]
10545 riscv authdata_write [expr @{$challenge + 1@}]
10548 @deffn {Command} {riscv authdata_read}
10549 Return the 32-bit value read from authdata.
10552 @deffn {Command} {riscv authdata_write} value
10553 Write the 32-bit value to authdata.
10556 @subsection RISC-V DMI Commands
10558 The following commands allow direct access to the Debug Module Interface, which
10559 can be used to interact with custom debug features.
10561 @deffn {Command} {riscv dmi_read} address
10562 Perform a 32-bit DMI read at address, returning the value.
10565 @deffn {Command} {riscv dmi_write} address value
10566 Perform a 32-bit DMI write of value at address.
10569 @section ARC Architecture
10572 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
10573 designers can optimize for a wide range of uses, from deeply embedded to
10574 high-performance host applications in a variety of market segments. See more
10575 at: @url{http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx}.
10576 OpenOCD currently supports ARC EM processors.
10577 There is a set ARC-specific OpenOCD commands that allow low-level
10578 access to the core and provide necessary support for ARC extensibility and
10579 configurability capabilities. ARC processors has much more configuration
10580 capabilities than most of the other processors and in addition there is an
10581 extension interface that allows SoC designers to add custom registers and
10582 instructions. For the OpenOCD that mostly means that set of core and AUX
10583 registers in target will vary and is not fixed for a particular processor
10584 model. To enable extensibility several TCL commands are provided that allow to
10585 describe those optional registers in OpenOCD configuration files. Moreover
10586 those commands allow for a dynamic target features discovery.
10589 @subsection General ARC commands
10591 @deffn {Config Command} {arc add-reg} configparams
10593 Add a new register to processor target. By default newly created register is
10594 marked as not existing. @var{configparams} must have following required
10599 @item @code{-name} name
10600 @*Name of a register.
10602 @item @code{-num} number
10603 @*Architectural register number: core register number or AUX register number.
10605 @item @code{-feature} XML_feature
10606 @*Name of GDB XML target description feature.
10610 @var{configparams} may have following optional arguments:
10614 @item @code{-gdbnum} number
10615 @*GDB register number. It is recommended to not assign GDB register number
10616 manually, because there would be a risk that two register will have same
10617 number. When register GDB number is not set with this option, then register
10618 will get a previous register number + 1. This option is required only for those
10619 registers that must be at particular address expected by GDB.
10622 @*This option specifies that register is a core registers. If not - this is an
10623 AUX register. AUX registers and core registers reside in different address
10627 @*This options specifies that register is a BCR register. BCR means Build
10628 Configuration Registers - this is a special type of AUX registers that are read
10629 only and non-volatile, that is - they never change their value. Therefore OpenOCD
10630 never invalidates values of those registers in internal caches. Because BCR is a
10631 type of AUX registers, this option cannot be used with @code{-core}.
10633 @item @code{-type} type_name
10634 @*Name of type of this register. This can be either one of the basic GDB types,
10635 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
10638 @* If specified then this is a "general" register. General registers are always
10639 read by OpenOCD on context save (when core has just been halted) and is always
10640 transferred to GDB client in a response to g-packet. Contrary to this,
10641 non-general registers are read and sent to GDB client on-demand. In general it
10642 is not recommended to apply this option to custom registers.
10648 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
10649 Adds new register type of ``flags'' class. ``Flags'' types can contain only
10650 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
10653 @anchor{add-reg-type-struct}
10654 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
10655 Adds new register type of ``struct'' class. ``Struct'' types can contain either
10656 bit-fields or fields of other types, however at the moment only bit fields are
10657 supported. Structure bit field definition looks like @code{-bitfield name
10661 @deffn {Command} {arc get-reg-field} reg-name field-name
10662 Returns value of bit-field in a register. Register must be ``struct'' register
10663 type, @xref{add-reg-type-struct}. command definition.
10666 @deffn {Command} {arc set-reg-exists} reg-names...
10667 Specify that some register exists. Any amount of names can be passed
10668 as an argument for a single command invocation.
10671 @subsection ARC JTAG commands
10673 @deffn {Command} {arc jtag set-aux-reg} regnum value
10674 This command writes value to AUX register via its number. This command access
10675 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10676 therefore it is unsafe to use if that register can be operated by other means.
10680 @deffn {Command} {arc jtag set-core-reg} regnum value
10681 This command is similar to @command{arc jtag set-aux-reg} but is for core
10685 @deffn {Command} {arc jtag get-aux-reg} regnum
10686 This command returns the value storded in AUX register via its number. This commands access
10687 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10688 therefore it is unsafe to use if that register can be operated by other means.
10692 @deffn {Command} {arc jtag get-core-reg} regnum
10693 This command is similar to @command{arc jtag get-aux-reg} but is for core
10697 @section STM8 Architecture
10698 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
10699 STMicroelectronics, based on a proprietary 8-bit core architecture.
10701 OpenOCD supports debugging STM8 through the STMicroelectronics debug
10702 protocol SWIM, @pxref{swimtransport,,SWIM}.
10704 @anchor{softwaredebugmessagesandtracing}
10705 @section Software Debug Messages and Tracing
10706 @cindex Linux-ARM DCC support
10710 OpenOCD can process certain requests from target software, when
10711 the target uses appropriate libraries.
10712 The most powerful mechanism is semihosting, but there is also
10713 a lighter weight mechanism using only the DCC channel.
10715 Currently @command{target_request debugmsgs}
10716 is supported only for @option{arm7_9} and @option{cortex_m} cores.
10717 These messages are received as part of target polling, so
10718 you need to have @command{poll on} active to receive them.
10719 They are intrusive in that they will affect program execution
10720 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
10722 See @file{libdcc} in the contrib dir for more details.
10723 In addition to sending strings, characters, and
10724 arrays of various size integers from the target,
10725 @file{libdcc} also exports a software trace point mechanism.
10726 The target being debugged may
10727 issue trace messages which include a 24-bit @dfn{trace point} number.
10728 Trace point support includes two distinct mechanisms,
10729 each supported by a command:
10732 @item @emph{History} ... A circular buffer of trace points
10733 can be set up, and then displayed at any time.
10734 This tracks where code has been, which can be invaluable in
10735 finding out how some fault was triggered.
10737 The buffer may overflow, since it collects records continuously.
10738 It may be useful to use some of the 24 bits to represent a
10739 particular event, and other bits to hold data.
10741 @item @emph{Counting} ... An array of counters can be set up,
10742 and then displayed at any time.
10743 This can help establish code coverage and identify hot spots.
10745 The array of counters is directly indexed by the trace point
10746 number, so trace points with higher numbers are not counted.
10749 Linux-ARM kernels have a ``Kernel low-level debugging
10750 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
10751 depends on CONFIG_DEBUG_LL) which uses this mechanism to
10752 deliver messages before a serial console can be activated.
10753 This is not the same format used by @file{libdcc}.
10754 Other software, such as the U-Boot boot loader, sometimes
10755 does the same thing.
10757 @deffn {Command} {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
10758 Displays current handling of target DCC message requests.
10759 These messages may be sent to the debugger while the target is running.
10760 The optional @option{enable} and @option{charmsg} parameters
10761 both enable the messages, while @option{disable} disables them.
10763 With @option{charmsg} the DCC words each contain one character,
10764 as used by Linux with CONFIG_DEBUG_ICEDCC;
10765 otherwise the libdcc format is used.
10768 @deffn {Command} {trace history} [@option{clear}|count]
10769 With no parameter, displays all the trace points that have triggered
10770 in the order they triggered.
10771 With the parameter @option{clear}, erases all current trace history records.
10772 With a @var{count} parameter, allocates space for that many
10776 @deffn {Command} {trace point} [@option{clear}|identifier]
10777 With no parameter, displays all trace point identifiers and how many times
10778 they have been triggered.
10779 With the parameter @option{clear}, erases all current trace point counters.
10780 With a numeric @var{identifier} parameter, creates a new a trace point counter
10781 and associates it with that identifier.
10783 @emph{Important:} The identifier and the trace point number
10784 are not related except by this command.
10785 These trace point numbers always start at zero (from server startup,
10786 or after @command{trace point clear}) and count up from there.
10790 @node JTAG Commands
10791 @chapter JTAG Commands
10792 @cindex JTAG Commands
10793 Most general purpose JTAG commands have been presented earlier.
10794 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
10795 Lower level JTAG commands, as presented here,
10796 may be needed to work with targets which require special
10797 attention during operations such as reset or initialization.
10799 To use these commands you will need to understand some
10800 of the basics of JTAG, including:
10803 @item A JTAG scan chain consists of a sequence of individual TAP
10804 devices such as a CPUs.
10805 @item Control operations involve moving each TAP through the same
10806 standard state machine (in parallel)
10807 using their shared TMS and clock signals.
10808 @item Data transfer involves shifting data through the chain of
10809 instruction or data registers of each TAP, writing new register values
10810 while the reading previous ones.
10811 @item Data register sizes are a function of the instruction active in
10812 a given TAP, while instruction register sizes are fixed for each TAP.
10813 All TAPs support a BYPASS instruction with a single bit data register.
10814 @item The way OpenOCD differentiates between TAP devices is by
10815 shifting different instructions into (and out of) their instruction
10819 @section Low Level JTAG Commands
10821 These commands are used by developers who need to access
10822 JTAG instruction or data registers, possibly controlling
10823 the order of TAP state transitions.
10824 If you're not debugging OpenOCD internals, or bringing up a
10825 new JTAG adapter or a new type of TAP device (like a CPU or
10826 JTAG router), you probably won't need to use these commands.
10827 In a debug session that doesn't use JTAG for its transport protocol,
10828 these commands are not available.
10830 @deffn {Command} {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
10831 Loads the data register of @var{tap} with a series of bit fields
10832 that specify the entire register.
10833 Each field is @var{numbits} bits long with
10834 a numeric @var{value} (hexadecimal encouraged).
10835 The return value holds the original value of each
10838 For example, a 38 bit number might be specified as one
10839 field of 32 bits then one of 6 bits.
10840 @emph{For portability, never pass fields which are more
10841 than 32 bits long. Many OpenOCD implementations do not
10842 support 64-bit (or larger) integer values.}
10844 All TAPs other than @var{tap} must be in BYPASS mode.
10845 The single bit in their data registers does not matter.
10847 When @var{tap_state} is specified, the JTAG state machine is left
10849 For example @sc{drpause} might be specified, so that more
10850 instructions can be issued before re-entering the @sc{run/idle} state.
10851 If the end state is not specified, the @sc{run/idle} state is entered.
10854 OpenOCD does not record information about data register lengths,
10855 so @emph{it is important that you get the bit field lengths right}.
10856 Remember that different JTAG instructions refer to different
10857 data registers, which may have different lengths.
10858 Moreover, those lengths may not be fixed;
10859 the SCAN_N instruction can change the length of
10860 the register accessed by the INTEST instruction
10861 (by connecting a different scan chain).
10865 @deffn {Command} {flush_count}
10866 Returns the number of times the JTAG queue has been flushed.
10867 This may be used for performance tuning.
10869 For example, flushing a queue over USB involves a
10870 minimum latency, often several milliseconds, which does
10871 not change with the amount of data which is written.
10872 You may be able to identify performance problems by finding
10873 tasks which waste bandwidth by flushing small transfers too often,
10874 instead of batching them into larger operations.
10877 @deffn {Command} {irscan} [tap instruction]+ [@option{-endstate} tap_state]
10878 For each @var{tap} listed, loads the instruction register
10879 with its associated numeric @var{instruction}.
10880 (The number of bits in that instruction may be displayed
10881 using the @command{scan_chain} command.)
10882 For other TAPs, a BYPASS instruction is loaded.
10884 When @var{tap_state} is specified, the JTAG state machine is left
10886 For example @sc{irpause} might be specified, so the data register
10887 can be loaded before re-entering the @sc{run/idle} state.
10888 If the end state is not specified, the @sc{run/idle} state is entered.
10891 OpenOCD currently supports only a single field for instruction
10892 register values, unlike data register values.
10893 For TAPs where the instruction register length is more than 32 bits,
10894 portable scripts currently must issue only BYPASS instructions.
10898 @deffn {Command} {pathmove} start_state [next_state ...]
10899 Start by moving to @var{start_state}, which
10900 must be one of the @emph{stable} states.
10901 Unless it is the only state given, this will often be the
10902 current state, so that no TCK transitions are needed.
10903 Then, in a series of single state transitions
10904 (conforming to the JTAG state machine) shift to
10905 each @var{next_state} in sequence, one per TCK cycle.
10906 The final state must also be stable.
10909 @deffn {Command} {runtest} @var{num_cycles}
10910 Move to the @sc{run/idle} state, and execute at least
10911 @var{num_cycles} of the JTAG clock (TCK).
10912 Instructions often need some time
10913 to execute before they take effect.
10916 @c tms_sequence (short|long)
10917 @c ... temporary, debug-only, other than USBprog bug workaround...
10919 @deffn {Command} {verify_ircapture} (@option{enable}|@option{disable})
10920 Verify values captured during @sc{ircapture} and returned
10921 during IR scans. Default is enabled, but this can be
10922 overridden by @command{verify_jtag}.
10923 This flag is ignored when validating JTAG chain configuration.
10926 @deffn {Command} {verify_jtag} (@option{enable}|@option{disable})
10927 Enables verification of DR and IR scans, to help detect
10928 programming errors. For IR scans, @command{verify_ircapture}
10929 must also be enabled.
10930 Default is enabled.
10933 @section TAP state names
10934 @cindex TAP state names
10936 The @var{tap_state} names used by OpenOCD in the @command{drscan},
10937 @command{irscan}, and @command{pathmove} commands are the same
10938 as those used in SVF boundary scan documents, except that
10939 SVF uses @sc{idle} instead of @sc{run/idle}.
10942 @item @b{RESET} ... @emph{stable} (with TMS high);
10943 acts as if TRST were pulsed
10944 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
10946 @item @b{DRCAPTURE}
10947 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
10948 through the data register
10950 @item @b{DRPAUSE} ... @emph{stable}; data register ready
10951 for update or more shifting
10955 @item @b{IRCAPTURE}
10956 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
10957 through the instruction register
10959 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
10960 for update or more shifting
10965 Note that only six of those states are fully ``stable'' in the
10966 face of TMS fixed (low except for @sc{reset})
10967 and a free-running JTAG clock. For all the
10968 others, the next TCK transition changes to a new state.
10971 @item From @sc{drshift} and @sc{irshift}, clock transitions will
10972 produce side effects by changing register contents. The values
10973 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
10974 may not be as expected.
10975 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
10976 choices after @command{drscan} or @command{irscan} commands,
10977 since they are free of JTAG side effects.
10978 @item @sc{run/idle} may have side effects that appear at non-JTAG
10979 levels, such as advancing the ARM9E-S instruction pipeline.
10980 Consult the documentation for the TAP(s) you are working with.
10983 @node Boundary Scan Commands
10984 @chapter Boundary Scan Commands
10986 One of the original purposes of JTAG was to support
10987 boundary scan based hardware testing.
10988 Although its primary focus is to support On-Chip Debugging,
10989 OpenOCD also includes some boundary scan commands.
10991 @section SVF: Serial Vector Format
10992 @cindex Serial Vector Format
10995 The Serial Vector Format, better known as @dfn{SVF}, is a
10996 way to represent JTAG test patterns in text files.
10997 In a debug session using JTAG for its transport protocol,
10998 OpenOCD supports running such test files.
11000 @deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
11001 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
11002 This issues a JTAG reset (Test-Logic-Reset) and then
11003 runs the SVF script from @file{filename}.
11005 Arguments can be specified in any order; the optional dash doesn't
11006 affect their semantics.
11010 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
11011 specified by the SVF file with HIR, TIR, HDR and TDR commands;
11012 instead, calculate them automatically according to the current JTAG
11013 chain configuration, targeting @var{tapname};
11014 @item @option{[-]quiet} do not log every command before execution;
11015 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
11016 on the real interface;
11017 @item @option{[-]progress} enable progress indication;
11018 @item @option{[-]ignore_error} continue execution despite TDO check
11023 @section XSVF: Xilinx Serial Vector Format
11024 @cindex Xilinx Serial Vector Format
11027 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
11028 binary representation of SVF which is optimized for use with
11030 In a debug session using JTAG for its transport protocol,
11031 OpenOCD supports running such test files.
11033 @quotation Important
11034 Not all XSVF commands are supported.
11037 @deffn {Command} {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
11038 This issues a JTAG reset (Test-Logic-Reset) and then
11039 runs the XSVF script from @file{filename}.
11040 When a @var{tapname} is specified, the commands are directed at
11042 When @option{virt2} is specified, the @sc{xruntest} command counts
11043 are interpreted as TCK cycles instead of microseconds.
11044 Unless the @option{quiet} option is specified,
11045 messages are logged for comments and some retries.
11048 The OpenOCD sources also include two utility scripts
11049 for working with XSVF; they are not currently installed
11050 after building the software.
11051 You may find them useful:
11054 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
11055 syntax understood by the @command{xsvf} command; see notes below.
11056 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
11057 understands the OpenOCD extensions.
11060 The input format accepts a handful of non-standard extensions.
11061 These include three opcodes corresponding to SVF extensions
11062 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
11063 two opcodes supporting a more accurate translation of SVF
11064 (XTRST, XWAITSTATE).
11065 If @emph{xsvfdump} shows a file is using those opcodes, it
11066 probably will not be usable with other XSVF tools.
11069 @section IPDBG: JTAG-Host server
11070 @cindex IPDBG JTAG-Host server
11073 IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary
11074 waveform generator. These are synthesize-able hardware descriptions of
11075 logic circuits in addition to software for control, visualization and further analysis.
11076 In a session using JTAG for its transport protocol, OpenOCD supports the function
11077 of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the
11078 control-software. For more details see @url{http://ipdbg.org}.
11080 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}]
11081 Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order.
11085 @item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start).
11086 @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}.
11087 @item @option{-hub @var{ir_value}} states that the JTAG hub is
11088 reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}.
11089 @item @option{-port @var{number}} tcp port number where the JTAG-Host is listening.
11090 @item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub.
11091 @item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a
11092 specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an
11093 access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second
11094 parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to
11095 shift data through vir can be configured.
11101 ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4
11103 Starts a server listening on tcp-port 4242 which connects to tool 4.
11104 The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board).
11107 ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1
11109 Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1).
11110 The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5).
11112 @node Utility Commands
11113 @chapter Utility Commands
11114 @cindex Utility Commands
11116 @section RAM testing
11117 @cindex RAM testing
11119 There is often a need to stress-test random access memory (RAM) for
11120 errors. OpenOCD comes with a Tcl implementation of well-known memory
11121 testing procedures allowing the detection of all sorts of issues with
11122 electrical wiring, defective chips, PCB layout and other common
11125 To use them, you usually need to initialise your RAM controller first;
11126 consult your SoC's documentation to get the recommended list of
11127 register operations and translate them to the corresponding
11128 @command{mww}/@command{mwb} commands.
11130 Load the memory testing functions with
11133 source [find tools/memtest.tcl]
11136 to get access to the following facilities:
11138 @deffn {Command} {memTestDataBus} address
11139 Test the data bus wiring in a memory region by performing a walking
11140 1's test at a fixed address within that region.
11143 @deffn {Command} {memTestAddressBus} baseaddress size
11144 Perform a walking 1's test on the relevant bits of the address and
11145 check for aliasing. This test will find single-bit address failures
11146 such as stuck-high, stuck-low, and shorted pins.
11149 @deffn {Command} {memTestDevice} baseaddress size
11150 Test the integrity of a physical memory device by performing an
11151 increment/decrement test over the entire region. In the process every
11152 storage bit in the device is tested as zero and as one.
11155 @deffn {Command} {runAllMemTests} baseaddress size
11156 Run all of the above tests over a specified memory region.
11159 @section Firmware recovery helpers
11160 @cindex Firmware recovery
11162 OpenOCD includes an easy-to-use script to facilitate mass-market
11163 devices recovery with JTAG.
11165 For quickstart instructions run:
11167 openocd -f tools/firmware-recovery.tcl -c firmware_help
11170 @node GDB and OpenOCD
11171 @chapter GDB and OpenOCD
11173 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
11174 to debug remote targets.
11175 Setting up GDB to work with OpenOCD can involve several components:
11178 @item The OpenOCD server support for GDB may need to be configured.
11179 @xref{gdbconfiguration,,GDB Configuration}.
11180 @item GDB's support for OpenOCD may need configuration,
11181 as shown in this chapter.
11182 @item If you have a GUI environment like Eclipse,
11183 that also will probably need to be configured.
11186 Of course, the version of GDB you use will need to be one which has
11187 been built to know about the target CPU you're using. It's probably
11188 part of the tool chain you're using. For example, if you are doing
11189 cross-development for ARM on an x86 PC, instead of using the native
11190 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
11191 if that's the tool chain used to compile your code.
11193 @section Connecting to GDB
11194 @cindex Connecting to GDB
11195 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
11196 instance GDB 6.3 has a known bug that produces bogus memory access
11197 errors, which has since been fixed; see
11198 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
11200 OpenOCD can communicate with GDB in two ways:
11204 A socket (TCP/IP) connection is typically started as follows:
11206 target extended-remote localhost:3333
11208 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
11210 The extended remote protocol is a super-set of the remote protocol and should
11211 be the preferred choice. More details are available in GDB documentation
11212 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
11214 To speed-up typing, any GDB command can be abbreviated, including the extended
11215 remote command above that becomes:
11220 @b{Note:} If any backward compatibility issue requires using the old remote
11221 protocol in place of the extended remote one, the former protocol is still
11222 available through the command:
11224 target remote localhost:3333
11228 A pipe connection is typically started as follows:
11230 target extended-remote | \
11231 openocd -c "gdb_port pipe; log_output openocd.log"
11233 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
11234 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
11235 session. log_output sends the log output to a file to ensure that the pipe is
11236 not saturated when using higher debug level outputs.
11239 To list the available OpenOCD commands type @command{monitor help} on the
11242 @section Sample GDB session startup
11244 With the remote protocol, GDB sessions start a little differently
11245 than they do when you're debugging locally.
11246 Here's an example showing how to start a debug session with a
11248 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
11249 Most programs would be written into flash (address 0) and run from there.
11252 $ arm-none-eabi-gdb example.elf
11253 (gdb) target extended-remote localhost:3333
11254 Remote debugging using localhost:3333
11256 (gdb) monitor reset halt
11259 Loading section .vectors, size 0x100 lma 0x20000000
11260 Loading section .text, size 0x5a0 lma 0x20000100
11261 Loading section .data, size 0x18 lma 0x200006a0
11262 Start address 0x2000061c, load size 1720
11263 Transfer rate: 22 KB/sec, 573 bytes/write.
11269 You could then interrupt the GDB session to make the program break,
11270 type @command{where} to show the stack, @command{list} to show the
11271 code around the program counter, @command{step} through code,
11272 set breakpoints or watchpoints, and so on.
11274 @section Configuring GDB for OpenOCD
11276 OpenOCD supports the gdb @option{qSupported} packet, this enables information
11277 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
11278 packet size and the device's memory map.
11279 You do not need to configure the packet size by hand,
11280 and the relevant parts of the memory map should be automatically
11281 set up when you declare (NOR) flash banks.
11283 However, there are other things which GDB can't currently query.
11284 You may need to set those up by hand.
11285 As OpenOCD starts up, you will often see a line reporting
11289 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
11292 You can pass that information to GDB with these commands:
11295 set remote hardware-breakpoint-limit 6
11296 set remote hardware-watchpoint-limit 4
11299 With that particular hardware (Cortex-M3) the hardware breakpoints
11300 only work for code running from flash memory. Most other ARM systems
11301 do not have such restrictions.
11303 Rather than typing such commands interactively, you may prefer to
11304 save them in a file and have GDB execute them as it starts, perhaps
11305 using a @file{.gdbinit} in your project directory or starting GDB
11306 using @command{gdb -x filename}.
11308 @section Programming using GDB
11309 @cindex Programming using GDB
11310 @anchor{programmingusinggdb}
11312 By default the target memory map is sent to GDB. This can be disabled by
11313 the following OpenOCD configuration option:
11315 gdb_memory_map disable
11317 For this to function correctly a valid flash configuration must also be set
11318 in OpenOCD. For faster performance you should also configure a valid
11321 Informing GDB of the memory map of the target will enable GDB to protect any
11322 flash areas of the target and use hardware breakpoints by default. This means
11323 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
11324 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
11326 To view the configured memory map in GDB, use the GDB command @option{info mem}.
11327 All other unassigned addresses within GDB are treated as RAM.
11329 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
11330 This can be changed to the old behaviour by using the following GDB command
11332 set mem inaccessible-by-default off
11335 If @command{gdb_flash_program enable} is also used, GDB will be able to
11336 program any flash memory using the vFlash interface.
11338 GDB will look at the target memory map when a load command is given, if any
11339 areas to be programmed lie within the target flash area the vFlash packets
11342 If the target needs configuring before GDB programming, set target
11343 event gdb-flash-erase-start:
11345 $_TARGETNAME configure -event gdb-flash-erase-start BODY
11347 @xref{targetevents,,Target Events}, for other GDB programming related events.
11349 To verify any flash programming the GDB command @option{compare-sections}
11352 @section Using GDB as a non-intrusive memory inspector
11353 @cindex Using GDB as a non-intrusive memory inspector
11354 @anchor{gdbmeminspect}
11356 If your project controls more than a blinking LED, let's say a heavy industrial
11357 robot or an experimental nuclear reactor, stopping the controlling process
11358 just because you want to attach GDB is not a good option.
11360 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
11361 Though there is a possible setup where the target does not get stopped
11362 and GDB treats it as it were running.
11363 If the target supports background access to memory while it is running,
11364 you can use GDB in this mode to inspect memory (mainly global variables)
11365 without any intrusion of the target process.
11367 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
11368 Place following command after target configuration:
11370 $_TARGETNAME configure -event gdb-attach @{@}
11373 If any of installed flash banks does not support probe on running target,
11374 switch off gdb_memory_map:
11376 gdb_memory_map disable
11379 Ensure GDB is configured without interrupt-on-connect.
11380 Some GDB versions set it by default, some does not.
11382 set remote interrupt-on-connect off
11385 If you switched gdb_memory_map off, you may want to setup GDB memory map
11386 manually or issue @command{set mem inaccessible-by-default off}
11388 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
11389 of a running target. Do not use GDB commands @command{continue},
11390 @command{step} or @command{next} as they synchronize GDB with your target
11391 and GDB would require stopping the target to get the prompt back.
11393 Do not use this mode under an IDE like Eclipse as it caches values of
11394 previously shown variables.
11396 It's also possible to connect more than one GDB to the same target by the
11397 target's configuration option @code{-gdb-max-connections}. This allows, for
11398 example, one GDB to run a script that continuously polls a set of variables
11399 while other GDB can be used interactively. Be extremely careful in this case,
11400 because the two GDB can easily get out-of-sync.
11402 @section RTOS Support
11403 @cindex RTOS Support
11404 @anchor{gdbrtossupport}
11406 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
11407 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
11409 @xref{Threads, Debugging Programs with Multiple Threads,
11410 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
11413 @* An example setup is below:
11416 $_TARGETNAME configure -rtos auto
11419 This will attempt to auto detect the RTOS within your application.
11421 Currently supported rtos's include:
11423 @item @option{eCos}
11424 @item @option{ThreadX}
11425 @item @option{FreeRTOS}
11426 @item @option{linux}
11427 @item @option{ChibiOS}
11428 @item @option{embKernel}
11430 @item @option{uCOS-III}
11431 @item @option{nuttx}
11432 @item @option{RIOT}
11433 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
11434 @item @option{Zephyr}
11437 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
11438 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
11442 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
11443 @item ThreadX symbols
11444 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
11445 @item FreeRTOS symbols
11447 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
11448 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
11449 uxCurrentNumberOfTasks, uxTopUsedPriority.
11451 @item linux symbols
11453 @item ChibiOS symbols
11454 rlist, ch_debug, chSysInit.
11455 @item embKernel symbols
11456 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
11457 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
11459 _mqx_kernel_data, MQX_init_struct.
11460 @item uC/OS-III symbols
11461 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
11462 @item nuttx symbols
11463 g_readytorun, g_tasklisttable.
11466 sched_threads, sched_num_threads, sched_active_pid, max_threads,
11469 @item Zephyr symbols
11470 _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
11473 For most RTOS supported the above symbols will be exported by default. However for
11474 some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken.
11476 Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols
11477 with information needed in order to build the list of threads.
11479 FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked
11480 along with the project:
11484 contrib/rtos-helpers/FreeRTOS-openocd.c
11486 contrib/rtos-helpers/uCOS-III-openocd.c
11489 @anchor{usingopenocdsmpwithgdb}
11490 @section Using OpenOCD SMP with GDB
11494 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
11495 ("hardware threads") in an SMP system as threads to GDB. With this extension,
11496 GDB can be used to inspect the state of an SMP system in a natural way.
11497 After halting the system, using the GDB command @command{info threads} will
11498 list the context of each active CPU core in the system. GDB's @command{thread}
11499 command can be used to switch the view to a different CPU core.
11500 The @command{step} and @command{stepi} commands can be used to step a specific core
11501 while other cores are free-running or remain halted, depending on the
11502 scheduler-locking mode configured in GDB.
11504 @section Legacy SMP core switching support
11506 This method is deprecated in favor of the @emph{hwthread} pseudo RTOS.
11509 For SMP support following GDB serial protocol packet have been defined :
11511 @item j - smp status request
11512 @item J - smp set request
11515 OpenOCD implements :
11517 @item @option{jc} packet for reading core id displayed by
11518 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
11519 @option{E01} for target not smp.
11520 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
11521 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
11522 for target not smp or @option{OK} on success.
11525 Handling of this packet within GDB can be done :
11527 @item by the creation of an internal variable (i.e @option{_core}) by mean
11528 of function allocate_computed_value allowing following GDB command.
11531 #Jc01 packet is sent
11533 #jc packet is sent and result is affected in $
11536 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
11537 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
11540 # toggle0 : force display of coreid 0
11546 # toggle1 : force display of coreid 1
11555 @node Tcl Scripting API
11556 @chapter Tcl Scripting API
11557 @cindex Tcl Scripting API
11558 @cindex Tcl scripts
11561 Tcl commands are stateless; e.g. the @command{telnet} command has
11562 a concept of currently active target, the Tcl API proc's take this sort
11563 of state information as an argument to each proc.
11565 There are three main types of return values: single value, name value
11566 pair list and lists.
11568 Name value pair. The proc 'foo' below returns a name/value pair
11572 > set foo(me) Duane
11573 > set foo(you) Oyvind
11574 > set foo(mouse) Micky
11575 > set foo(duck) Donald
11587 me Duane you Oyvind mouse Micky duck Donald
11590 Thus, to get the names of the associative array is easy:
11593 foreach { name value } [set foo] {
11594 puts "Name: $name, Value: $value"
11598 Lists returned should be relatively small. Otherwise, a range
11599 should be passed in to the proc in question.
11601 @section Internal low-level Commands
11603 By "low-level", we mean commands that a human would typically not
11607 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
11609 Read memory and return as a Tcl array for script processing
11610 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
11612 Convert a Tcl array to memory locations and write the values
11613 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
11615 Return information about the flash banks
11617 @item @b{capture} <@var{command}>
11619 Run <@var{command}> and return full log output that was produced during
11620 its execution. Example:
11623 > capture "reset init"
11628 OpenOCD commands can consist of two words, e.g. "flash banks". The
11629 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
11630 called "flash_banks".
11632 @section Tcl RPC server
11635 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
11636 commands and receive the results.
11638 To access it, your application needs to connect to a configured TCP port
11639 (see @command{tcl_port}). Then it can pass any string to the
11640 interpreter terminating it with @code{0x1a} and wait for the return
11641 value (it will be terminated with @code{0x1a} as well). This can be
11642 repeated as many times as desired without reopening the connection.
11644 It is not needed anymore to prefix the OpenOCD commands with
11645 @code{ocd_} to get the results back. But sometimes you might need the
11646 @command{capture} command.
11648 See @file{contrib/rpc_examples/} for specific client implementations.
11650 @section Tcl RPC server notifications
11651 @cindex RPC Notifications
11653 Notifications are sent asynchronously to other commands being executed over
11654 the RPC server, so the port must be polled continuously.
11656 Target event, state and reset notifications are emitted as Tcl associative arrays
11657 in the following format.
11660 type target_event event [event-name]
11661 type target_state state [state-name]
11662 type target_reset mode [reset-mode]
11665 @deffn {Command} {tcl_notifications} [on/off]
11666 Toggle output of target notifications to the current Tcl RPC server.
11667 Only available from the Tcl RPC server.
11672 @section Tcl RPC server trace output
11673 @cindex RPC trace output
11675 Trace data is sent asynchronously to other commands being executed over
11676 the RPC server, so the port must be polled continuously.
11678 Target trace data is emitted as a Tcl associative array in the following format.
11681 type target_trace data [trace-data-hex-encoded]
11684 @deffn {Command} {tcl_trace} [on/off]
11685 Toggle output of target trace data to the current Tcl RPC server.
11686 Only available from the Tcl RPC server.
11689 See an example application here:
11690 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
11699 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
11701 @cindex adaptive clocking
11704 In digital circuit design it is often referred to as ``clock
11705 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
11706 operating at some speed, your CPU target is operating at another.
11707 The two clocks are not synchronised, they are ``asynchronous''
11709 In order for the two to work together they must be synchronised
11710 well enough to work; JTAG can't go ten times faster than the CPU,
11711 for example. There are 2 basic options:
11714 Use a special "adaptive clocking" circuit to change the JTAG
11715 clock rate to match what the CPU currently supports.
11717 The JTAG clock must be fixed at some speed that's enough slower than
11718 the CPU clock that all TMS and TDI transitions can be detected.
11721 @b{Does this really matter?} For some chips and some situations, this
11722 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
11723 the CPU has no difficulty keeping up with JTAG.
11724 Startup sequences are often problematic though, as are other
11725 situations where the CPU clock rate changes (perhaps to save
11728 For example, Atmel AT91SAM chips start operation from reset with
11729 a 32kHz system clock. Boot firmware may activate the main oscillator
11730 and PLL before switching to a faster clock (perhaps that 500 MHz
11732 If you're using JTAG to debug that startup sequence, you must slow
11733 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
11734 JTAG can use a faster clock.
11736 Consider also debugging a 500MHz ARM926 hand held battery powered
11737 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
11738 clock, between keystrokes unless it has work to do. When would
11739 that 5 MHz JTAG clock be usable?
11741 @b{Solution #1 - A special circuit}
11743 In order to make use of this,
11744 your CPU, board, and JTAG adapter must all support the RTCK
11745 feature. Not all of them support this; keep reading!
11747 The RTCK ("Return TCK") signal in some ARM chips is used to help with
11748 this problem. ARM has a good description of the problem described at
11749 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
11750 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
11751 work? / how does adaptive clocking work?''.
11753 The nice thing about adaptive clocking is that ``battery powered hand
11754 held device example'' - the adaptiveness works perfectly all the
11755 time. One can set a break point or halt the system in the deep power
11756 down code, slow step out until the system speeds up.
11758 Note that adaptive clocking may also need to work at the board level,
11759 when a board-level scan chain has multiple chips.
11760 Parallel clock voting schemes are good way to implement this,
11761 both within and between chips, and can easily be implemented
11763 It's not difficult to have logic fan a module's input TCK signal out
11764 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
11765 back with the right polarity before changing the output RTCK signal.
11766 Texas Instruments makes some clock voting logic available
11767 for free (with no support) in VHDL form; see
11768 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
11770 @b{Solution #2 - Always works - but may be slower}
11772 Often this is a perfectly acceptable solution.
11774 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
11775 the target clock speed. But what that ``magic division'' is varies
11776 depending on the chips on your board.
11777 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
11778 ARM11 cores use an 8:1 division.
11779 @b{Xilinx rule of thumb} is 1/12 the clock speed.
11781 Note: most full speed FT2232 based JTAG adapters are limited to a
11782 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
11783 often support faster clock rates (and adaptive clocking).
11785 You can still debug the 'low power' situations - you just need to
11786 either use a fixed and very slow JTAG clock rate ... or else
11787 manually adjust the clock speed at every step. (Adjusting is painful
11788 and tedious, and is not always practical.)
11790 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
11791 have a special debug mode in your application that does a ``high power
11792 sleep''. If you are careful - 98% of your problems can be debugged
11795 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
11796 operation in your idle loops even if you don't otherwise change the CPU
11798 That operation gates the CPU clock, and thus the JTAG clock; which
11799 prevents JTAG access. One consequence is not being able to @command{halt}
11800 cores which are executing that @emph{wait for interrupt} operation.
11802 To set the JTAG frequency use the command:
11805 # Example: 1.234MHz
11810 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
11812 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
11813 around Windows filenames.
11826 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
11828 Make sure you have Cygwin installed, or at least a version of OpenOCD that
11829 claims to come with all the necessary DLLs. When using Cygwin, try launching
11830 OpenOCD from the Cygwin shell.
11832 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
11833 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
11834 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
11836 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
11837 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
11838 software breakpoints consume one of the two available hardware breakpoints.
11840 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
11842 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
11843 clock at the time you're programming the flash. If you've specified the crystal's
11844 frequency, make sure the PLL is disabled. If you've specified the full core speed
11845 (e.g. 60MHz), make sure the PLL is enabled.
11847 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
11848 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
11849 out while waiting for end of scan, rtck was disabled".
11851 Make sure your PC's parallel port operates in EPP mode. You might have to try several
11852 settings in your PC BIOS (ECP, EPP, and different versions of those).
11854 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
11855 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
11856 memory read caused data abort".
11858 The errors are non-fatal, and are the result of GDB trying to trace stack frames
11859 beyond the last valid frame. It might be possible to prevent this by setting up
11860 a proper "initial" stack frame, if you happen to know what exactly has to
11861 be done, feel free to add this here.
11863 @b{Simple:} In your startup code - push 8 registers of zeros onto the
11864 stack before calling main(). What GDB is doing is ``climbing'' the run
11865 time stack by reading various values on the stack using the standard
11866 call frame for the target. GDB keeps going - until one of 2 things
11867 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
11868 stackframes have been processed. By pushing zeros on the stack, GDB
11871 @b{Debugging Interrupt Service Routines} - In your ISR before you call
11872 your C code, do the same - artificially push some zeros onto the stack,
11873 remember to pop them off when the ISR is done.
11875 @b{Also note:} If you have a multi-threaded operating system, they
11876 often do not @b{in the interest of saving memory} waste these few
11880 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
11881 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
11883 This warning doesn't indicate any serious problem, as long as you don't want to
11884 debug your core right out of reset. Your .cfg file specified @option{reset_config
11885 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
11886 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
11887 independently. With this setup, it's not possible to halt the core right out of
11888 reset, everything else should work fine.
11890 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
11891 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
11892 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
11893 quit with an error message. Is there a stability issue with OpenOCD?
11895 No, this is not a stability issue concerning OpenOCD. Most users have solved
11896 this issue by simply using a self-powered USB hub, which they connect their
11897 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
11898 supply stable enough for the Amontec JTAGkey to be operated.
11900 @b{Laptops running on battery have this problem too...}
11902 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
11903 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
11904 What does that mean and what might be the reason for this?
11906 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
11907 has closed the connection to OpenOCD. This might be a GDB issue.
11909 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
11910 are described, there is a parameter for specifying the clock frequency
11911 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
11912 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
11913 specified in kilohertz. However, I do have a quartz crystal of a
11914 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
11915 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
11918 No. The clock frequency specified here must be given as an integral number.
11919 However, this clock frequency is used by the In-Application-Programming (IAP)
11920 routines of the LPC2000 family only, which seems to be very tolerant concerning
11921 the given clock frequency, so a slight difference between the specified clock
11922 frequency and the actual clock frequency will not cause any trouble.
11924 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
11926 Well, yes and no. Commands can be given in arbitrary order, yet the
11927 devices listed for the JTAG scan chain must be given in the right
11928 order (jtag newdevice), with the device closest to the TDO-Pin being
11929 listed first. In general, whenever objects of the same type exist
11930 which require an index number, then these objects must be given in the
11931 right order (jtag newtap, targets and flash banks - a target
11932 references a jtag newtap and a flash bank references a target).
11934 You can use the ``scan_chain'' command to verify and display the tap order.
11936 Also, some commands can't execute until after @command{init} has been
11937 processed. Such commands include @command{nand probe} and everything
11938 else that needs to write to controller registers, perhaps for setting
11939 up DRAM and loading it with code.
11941 @anchor{faqtaporder}
11942 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
11945 Yes; whenever you have more than one, you must declare them in
11946 the same order used by the hardware.
11948 Many newer devices have multiple JTAG TAPs. For example:
11949 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
11950 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
11951 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
11952 connected to the boundary scan TAP, which then connects to the
11953 Cortex-M3 TAP, which then connects to the TDO pin.
11955 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
11956 (2) The boundary scan TAP. If your board includes an additional JTAG
11957 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
11958 place it before or after the STM32 chip in the chain. For example:
11961 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
11962 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
11963 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
11964 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
11965 @item Xilinx TDO Pin -> OpenOCD TDO (input)
11968 The ``jtag device'' commands would thus be in the order shown below. Note:
11971 @item jtag newtap Xilinx tap -irlen ...
11972 @item jtag newtap stm32 cpu -irlen ...
11973 @item jtag newtap stm32 bs -irlen ...
11974 @item # Create the debug target and say where it is
11975 @item target create stm32.cpu -chain-position stm32.cpu ...
11979 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
11980 log file, I can see these error messages: Error: arm7_9_common.c:561
11981 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
11987 @node Tcl Crash Course
11988 @chapter Tcl Crash Course
11991 Not everyone knows Tcl - this is not intended to be a replacement for
11992 learning Tcl, the intent of this chapter is to give you some idea of
11993 how the Tcl scripts work.
11995 This chapter is written with two audiences in mind. (1) OpenOCD users
11996 who need to understand a bit more of how Jim-Tcl works so they can do
11997 something useful, and (2) those that want to add a new command to
12000 @section Tcl Rule #1
12001 There is a famous joke, it goes like this:
12003 @item Rule #1: The wife is always correct
12004 @item Rule #2: If you think otherwise, See Rule #1
12007 The Tcl equal is this:
12010 @item Rule #1: Everything is a string
12011 @item Rule #2: If you think otherwise, See Rule #1
12014 As in the famous joke, the consequences of Rule #1 are profound. Once
12015 you understand Rule #1, you will understand Tcl.
12017 @section Tcl Rule #1b
12018 There is a second pair of rules.
12020 @item Rule #1: Control flow does not exist. Only commands
12021 @* For example: the classic FOR loop or IF statement is not a control
12022 flow item, they are commands, there is no such thing as control flow
12024 @item Rule #2: If you think otherwise, See Rule #1
12025 @* Actually what happens is this: There are commands that by
12026 convention, act like control flow key words in other languages. One of
12027 those commands is the word ``for'', another command is ``if''.
12030 @section Per Rule #1 - All Results are strings
12031 Every Tcl command results in a string. The word ``result'' is used
12032 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
12033 Everything is a string}
12035 @section Tcl Quoting Operators
12036 In life of a Tcl script, there are two important periods of time, the
12037 difference is subtle.
12040 @item Evaluation Time
12043 The two key items here are how ``quoted things'' work in Tcl. Tcl has
12044 three primary quoting constructs, the [square-brackets] the
12045 @{curly-braces@} and ``double-quotes''
12047 By now you should know $VARIABLES always start with a $DOLLAR
12048 sign. BTW: To set a variable, you actually use the command ``set'', as
12049 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
12050 = 1'' statement, but without the equal sign.
12053 @item @b{[square-brackets]}
12054 @* @b{[square-brackets]} are command substitutions. It operates much
12055 like Unix Shell `back-ticks`. The result of a [square-bracket]
12056 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
12057 string}. These two statements are roughly identical:
12061 echo "The Date is: $X"
12064 puts "The Date is: $X"
12066 @item @b{``double-quoted-things''}
12067 @* @b{``double-quoted-things''} are just simply quoted
12068 text. $VARIABLES and [square-brackets] are expanded in place - the
12069 result however is exactly 1 string. @i{Remember Rule #1 - Everything
12073 puts "It is now \"[date]\", $x is in 1 hour"
12075 @item @b{@{Curly-Braces@}}
12076 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
12077 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
12078 'single-quote' operators in BASH shell scripts, with the added
12079 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
12080 nested 3 times@}@}@} NOTE: [date] is a bad example;
12081 at this writing, Jim/OpenOCD does not have a date command.
12084 @section Consequences of Rule 1/2/3/4
12086 The consequences of Rule 1 are profound.
12088 @subsection Tokenisation & Execution.
12090 Of course, whitespace, blank lines and #comment lines are handled in
12093 As a script is parsed, each (multi) line in the script file is
12094 tokenised and according to the quoting rules. After tokenisation, that
12095 line is immediately executed.
12097 Multi line statements end with one or more ``still-open''
12098 @{curly-braces@} which - eventually - closes a few lines later.
12100 @subsection Command Execution
12102 Remember earlier: There are no ``control flow''
12103 statements in Tcl. Instead there are COMMANDS that simply act like
12104 control flow operators.
12106 Commands are executed like this:
12109 @item Parse the next line into (argc) and (argv[]).
12110 @item Look up (argv[0]) in a table and call its function.
12111 @item Repeat until End Of File.
12114 It sort of works like this:
12117 ReadAndParse( &argc, &argv );
12119 cmdPtr = LookupCommand( argv[0] );
12121 (*cmdPtr->Execute)( argc, argv );
12125 When the command ``proc'' is parsed (which creates a procedure
12126 function) it gets 3 parameters on the command line. @b{1} the name of
12127 the proc (function), @b{2} the list of parameters, and @b{3} the body
12128 of the function. Not the choice of words: LIST and BODY. The PROC
12129 command stores these items in a table somewhere so it can be found by
12130 ``LookupCommand()''
12132 @subsection The FOR command
12134 The most interesting command to look at is the FOR command. In Tcl,
12135 the FOR command is normally implemented in C. Remember, FOR is a
12136 command just like any other command.
12138 When the ascii text containing the FOR command is parsed, the parser
12139 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
12143 @item The ascii text 'for'
12144 @item The start text
12145 @item The test expression
12146 @item The next text
12147 @item The body text
12150 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
12151 Remember @i{Rule #1 - Everything is a string.} The key point is this:
12152 Often many of those parameters are in @{curly-braces@} - thus the
12153 variables inside are not expanded or replaced until later.
12155 Remember that every Tcl command looks like the classic ``main( argc,
12156 argv )'' function in C. In JimTCL - they actually look like this:
12160 MyCommand( Jim_Interp *interp,
12162 Jim_Obj * const *argvs );
12165 Real Tcl is nearly identical. Although the newer versions have
12166 introduced a byte-code parser and interpreter, but at the core, it
12167 still operates in the same basic way.
12169 @subsection FOR command implementation
12171 To understand Tcl it is perhaps most helpful to see the FOR
12172 command. Remember, it is a COMMAND not a control flow structure.
12174 In Tcl there are two underlying C helper functions.
12176 Remember Rule #1 - You are a string.
12178 The @b{first} helper parses and executes commands found in an ascii
12179 string. Commands can be separated by semicolons, or newlines. While
12180 parsing, variables are expanded via the quoting rules.
12182 The @b{second} helper evaluates an ascii string as a numerical
12183 expression and returns a value.
12185 Here is an example of how the @b{FOR} command could be
12186 implemented. The pseudo code below does not show error handling.
12188 void Execute_AsciiString( void *interp, const char *string );
12190 int Evaluate_AsciiExpression( void *interp, const char *string );
12193 MyForCommand( void *interp,
12198 SetResult( interp, "WRONG number of parameters");
12202 // argv[0] = the ascii string just like C
12204 // Execute the start statement.
12205 Execute_AsciiString( interp, argv[1] );
12207 // Top of loop test
12209 i = Evaluate_AsciiExpression(interp, argv[2]);
12213 // Execute the body
12214 Execute_AsciiString( interp, argv[3] );
12216 // Execute the LOOP part
12217 Execute_AsciiString( interp, argv[4] );
12221 SetResult( interp, "" );
12226 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
12227 in the same basic way.
12229 @section OpenOCD Tcl Usage
12231 @subsection source and find commands
12232 @b{Where:} In many configuration files
12233 @* Example: @b{ source [find FILENAME] }
12234 @*Remember the parsing rules
12236 @item The @command{find} command is in square brackets,
12237 and is executed with the parameter FILENAME. It should find and return
12238 the full path to a file with that name; it uses an internal search path.
12239 The RESULT is a string, which is substituted into the command line in
12240 place of the bracketed @command{find} command.
12241 (Don't try to use a FILENAME which includes the "#" character.
12242 That character begins Tcl comments.)
12243 @item The @command{source} command is executed with the resulting filename;
12244 it reads a file and executes as a script.
12246 @subsection format command
12247 @b{Where:} Generally occurs in numerous places.
12248 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
12254 puts [format "The answer: %d" [expr @{$x * $y@}]]
12257 @item The SET command creates 2 variables, X and Y.
12258 @item The double [nested] EXPR command performs math
12259 @* The EXPR command produces numerical result as a string.
12260 @* Refer to Rule #1
12261 @item The format command is executed, producing a single string
12262 @* Refer to Rule #1.
12263 @item The PUTS command outputs the text.
12265 @subsection Body or Inlined Text
12266 @b{Where:} Various TARGET scripts.
12269 proc someproc @{@} @{
12270 ... multiple lines of stuff ...
12272 $_TARGETNAME configure -event FOO someproc
12273 #2 Good - no variables
12274 $_TARGETNAME configure -event foo "this ; that;"
12275 #3 Good Curly Braces
12276 $_TARGETNAME configure -event FOO @{
12277 puts "Time: [date]"
12279 #4 DANGER DANGER DANGER
12280 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
12283 @item The $_TARGETNAME is an OpenOCD variable convention.
12284 @*@b{$_TARGETNAME} represents the last target created, the value changes
12285 each time a new target is created. Remember the parsing rules. When
12286 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
12287 the name of the target which happens to be a TARGET (object)
12289 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
12290 @*There are 4 examples:
12292 @item The TCLBODY is a simple string that happens to be a proc name
12293 @item The TCLBODY is several simple commands separated by semicolons
12294 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
12295 @item The TCLBODY is a string with variables that get expanded.
12298 In the end, when the target event FOO occurs the TCLBODY is
12299 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
12300 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
12302 Remember the parsing rules. In case #3, @{curly-braces@} mean the
12303 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
12304 and the text is evaluated. In case #4, they are replaced before the
12305 ``Target Object Command'' is executed. This occurs at the same time
12306 $_TARGETNAME is replaced. In case #4 the date will never
12307 change. @{BTW: [date] is a bad example; at this writing,
12308 Jim/OpenOCD does not have a date command@}
12310 @subsection Global Variables
12311 @b{Where:} You might discover this when writing your own procs @* In
12312 simple terms: Inside a PROC, if you need to access a global variable
12313 you must say so. See also ``upvar''. Example:
12315 proc myproc @{ @} @{
12316 set y 0 #Local variable Y
12317 global x #Global variable X
12318 puts [format "X=%d, Y=%d" $x $y]
12321 @section Other Tcl Hacks
12322 @b{Dynamic variable creation}
12324 # Dynamically create a bunch of variables.
12325 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr @{$x + 1@}]@} @{
12327 set vn [format "BIT%d" $x]
12331 set $vn [expr @{1 << $x@}]
12334 @b{Dynamic proc/command creation}
12336 # One "X" function - 5 uart functions.
12337 foreach who @{A B C D E@}
12338 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
12343 @appendix The GNU Free Documentation License.
12346 @node OpenOCD Concept Index
12347 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
12348 @comment case issue with ``Index.html'' and ``index.html''
12349 @comment Occurs when creating ``--html --no-split'' output
12350 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
12351 @unnumbered OpenOCD Concept Index
12355 @node Command and Driver Index
12356 @unnumbered Command and Driver Index