1 /* Register definitions for pic16f785.
2 * This file was automatically generated by:
4 * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
8 __sfr __at (INDF_ADDR) INDF;
9 __sfr __at (TMR0_ADDR) TMR0;
10 __sfr __at (PCL_ADDR) PCL;
11 __sfr __at (STATUS_ADDR) STATUS;
12 __sfr __at (FSR_ADDR) FSR;
13 __sfr __at (PORTA_ADDR) PORTA;
14 __sfr __at (PORTB_ADDR) PORTB;
15 __sfr __at (PORTC_ADDR) PORTC;
16 __sfr __at (PCLATH_ADDR) PCLATH;
17 __sfr __at (INTCON_ADDR) INTCON;
18 __sfr __at (PIR1_ADDR) PIR1;
19 __sfr __at (TMR1L_ADDR) TMR1L;
20 __sfr __at (TMR1H_ADDR) TMR1H;
21 __sfr __at (T1CON_ADDR) T1CON;
22 __sfr __at (TMR2_ADDR) TMR2;
23 __sfr __at (T2CON_ADDR) T2CON;
24 __sfr __at (CCPR1L_ADDR) CCPR1L;
25 __sfr __at (CCPR1H_ADDR) CCPR1H;
26 __sfr __at (CCP1CON_ADDR) CCP1CON;
27 __sfr __at (WDTCON_ADDR) WDTCON;
28 __sfr __at (ADRESH_ADDR) ADRESH;
29 __sfr __at (ADCON0_ADDR) ADCON0;
30 __sfr __at (OPTION_REG_ADDR) OPTION_REG;
31 __sfr __at (TRISA_ADDR) TRISA;
32 __sfr __at (TRISB_ADDR) TRISB;
33 __sfr __at (TRISC_ADDR) TRISC;
34 __sfr __at (PIE1_ADDR) PIE1;
35 __sfr __at (PCON_ADDR) PCON;
36 __sfr __at (OSCCON_ADDR) OSCCON;
37 __sfr __at (OSCTUNE_ADDR) OSCTUNE;
38 __sfr __at (ANSEL_ADDR) ANSEL;
39 __sfr __at (ANSEL0_ADDR) ANSEL0;
40 __sfr __at (PR2_ADDR) PR2;
41 __sfr __at (ANSEL1_ADDR) ANSEL1;
42 __sfr __at (WPU_ADDR) WPU;
43 __sfr __at (WPUA_ADDR) WPUA;
44 __sfr __at (IOC_ADDR) IOC;
45 __sfr __at (IOCA_ADDR) IOCA;
46 __sfr __at (REFCON_ADDR) REFCON;
47 __sfr __at (VRCON_ADDR) VRCON;
48 __sfr __at (EEDAT_ADDR) EEDAT;
49 __sfr __at (EEDATA_ADDR) EEDATA;
50 __sfr __at (EEADR_ADDR) EEADR;
51 __sfr __at (EECON1_ADDR) EECON1;
52 __sfr __at (EECON2_ADDR) EECON2;
53 __sfr __at (ADRESL_ADDR) ADRESL;
54 __sfr __at (ADCON1_ADDR) ADCON1;
55 __sfr __at (PWMCON1_ADDR) PWMCON1;
56 __sfr __at (PWMCON0_ADDR) PWMCON0;
57 __sfr __at (PWMCLK_ADDR) PWMCLK;
58 __sfr __at (PWMPH1_ADDR) PWMPH1;
59 __sfr __at (PWMPH2_ADDR) PWMPH2;
60 __sfr __at (CM1CON0_ADDR) CM1CON0;
61 __sfr __at (CM2CON0_ADDR) CM2CON0;
62 __sfr __at (CM2CON1_ADDR) CM2CON1;
63 __sfr __at (OPA1CON_ADDR) OPA1CON;
64 __sfr __at (OPA2CON_ADDR) OPA2CON;
67 // bitfield definitions
69 volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
70 volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
71 volatile __ANSEL1_bits_t __at(ANSEL1_ADDR) ANSEL1_bits;
72 volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
73 volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
74 volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
75 volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
76 volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
77 volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
78 volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
79 volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
80 volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
81 volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
82 volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
83 volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
84 volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
85 volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
86 volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
87 volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
88 volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
89 volatile __PWMCLK_bits_t __at(PWMCLK_ADDR) PWMCLK_bits;
90 volatile __PWMCON0_bits_t __at(PWMCON0_ADDR) PWMCON0_bits;
91 volatile __PWMCON1_bits_t __at(PWMCON1_ADDR) PWMCON1_bits;
92 volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
93 volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
94 volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
95 volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
96 volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
97 volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
98 volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
99 volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
100 volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
101 volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;