1 /* Register definitions for pic16c745.
2 * This file was automatically generated by:
4 * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
8 data __at (INDF_ADDR) volatile char INDF;
9 sfr __at (TMR0_ADDR) TMR0;
10 data __at (PCL_ADDR) volatile char PCL;
11 sfr __at (STATUS_ADDR) STATUS;
12 sfr __at (FSR_ADDR) FSR;
13 sfr __at (PORTA_ADDR) PORTA;
14 sfr __at (PORTB_ADDR) PORTB;
15 sfr __at (PORTC_ADDR) PORTC;
16 sfr __at (PCLATH_ADDR) PCLATH;
17 sfr __at (INTCON_ADDR) INTCON;
18 sfr __at (PIR1_ADDR) PIR1;
19 sfr __at (PIR2_ADDR) PIR2;
20 sfr __at (TMR1L_ADDR) TMR1L;
21 sfr __at (TMR1H_ADDR) TMR1H;
22 sfr __at (T1CON_ADDR) T1CON;
23 sfr __at (TMR2_ADDR) TMR2;
24 sfr __at (T2CON_ADDR) T2CON;
25 sfr __at (CCPR1L_ADDR) CCPR1L;
26 sfr __at (CCPR1H_ADDR) CCPR1H;
27 sfr __at (CCP1CON_ADDR) CCP1CON;
28 sfr __at (RCSTA_ADDR) RCSTA;
29 sfr __at (TXREG_ADDR) TXREG;
30 sfr __at (RCREG_ADDR) RCREG;
31 sfr __at (CCPR2L_ADDR) CCPR2L;
32 sfr __at (CCPR2H_ADDR) CCPR2H;
33 sfr __at (CCP2CON_ADDR) CCP2CON;
34 sfr __at (ADRES_ADDR) ADRES;
35 sfr __at (ADCON0_ADDR) ADCON0;
36 sfr __at (OPTION_REG_ADDR) OPTION_REG;
37 sfr __at (TRISA_ADDR) TRISA;
38 sfr __at (TRISB_ADDR) TRISB;
39 sfr __at (TRISC_ADDR) TRISC;
40 sfr __at (PIE1_ADDR) PIE1;
41 sfr __at (PIE2_ADDR) PIE2;
42 sfr __at (PCON_ADDR) PCON;
43 sfr __at (PR2_ADDR) PR2;
44 sfr __at (TXSTA_ADDR) TXSTA;
45 sfr __at (SPBRG_ADDR) SPBRG;
46 sfr __at (ADCON1_ADDR) ADCON1;
47 sfr __at (UIR_ADDR) UIR;
48 sfr __at (UIE_ADDR) UIE;
49 sfr __at (UEIR_ADDR) UEIR;
50 sfr __at (UEIE_ADDR) UEIE;
51 sfr __at (USTAT_ADDR) USTAT;
52 sfr __at (UCTRL_ADDR) UCTRL;
53 sfr __at (UADDR_ADDR) UADDR;
54 sfr __at (USWSTAT_ADDR) USWSTAT;
55 sfr __at (UEP0_ADDR) UEP0;
56 sfr __at (UEP1_ADDR) UEP1;
57 sfr __at (UEP2_ADDR) UEP2;
58 sfr __at (BD0OST_ADDR) BD0OST;
59 sfr __at (BD0OBC_ADDR) BD0OBC;
60 sfr __at (BD0OAL_ADDR) BD0OAL;
61 sfr __at (BD0IST_ADDR) BD0IST;
62 sfr __at (BD0IBC_ADDR) BD0IBC;
63 sfr __at (BD0IAL_ADDR) BD0IAL;
64 sfr __at (BD1OST_ADDR) BD1OST;
65 sfr __at (BD1OBC_ADDR) BD1OBC;
66 sfr __at (BD1OAL_ADDR) BD1OAL;
67 sfr __at (BD1IST_ADDR) BD1IST;
68 sfr __at (BD1IBC_ADDR) BD1IBC;
69 sfr __at (BD1IAL_ADDR) BD1IAL;
70 sfr __at (BD2OST_ADDR) BD2OST;
71 sfr __at (BD2OBC_ADDR) BD2OBC;
72 sfr __at (BD2OAL_ADDR) BD2OAL;
73 sfr __at (BD2IST_ADDR) BD2IST;
74 sfr __at (BD2IBC_ADDR) BD2IBC;
75 sfr __at (BD2IAL_ADDR) BD2IAL;
78 // bitfield definitions
80 volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
81 volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
82 volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
83 volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
84 volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
85 volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
86 volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
87 volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
88 volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
89 volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
90 volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
91 volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
92 volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
93 volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
94 volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
95 volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
96 volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits;
97 volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits;
98 volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits;
99 volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits;
100 volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits;