1 /* Register definitions for pic12f683.
2 * This file was automatically generated by:
4 * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
8 __sfr __at (INDF_ADDR) INDF;
9 __sfr __at (TMR0_ADDR) TMR0;
10 __sfr __at (PCL_ADDR) PCL;
11 __sfr __at (STATUS_ADDR) STATUS;
12 __sfr __at (FSR_ADDR) FSR;
13 __sfr __at (GPIO_ADDR) GPIO;
14 __sfr __at (PCLATH_ADDR) PCLATH;
15 __sfr __at (INTCON_ADDR) INTCON;
16 __sfr __at (PIR1_ADDR) PIR1;
17 __sfr __at (TMR1L_ADDR) TMR1L;
18 __sfr __at (TMR1H_ADDR) TMR1H;
19 __sfr __at (T1CON_ADDR) T1CON;
20 __sfr __at (TMR2_ADDR) TMR2;
21 __sfr __at (T2CON_ADDR) T2CON;
22 __sfr __at (CCPR1L_ADDR) CCPR1L;
23 __sfr __at (CCPR1H_ADDR) CCPR1H;
24 __sfr __at (CCP1CON_ADDR) CCP1CON;
25 __sfr __at (WDTCON_ADDR) WDTCON;
26 __sfr __at (CMCON0_ADDR) CMCON0;
27 __sfr __at (CMCON1_ADDR) CMCON1;
28 __sfr __at (ADRESH_ADDR) ADRESH;
29 __sfr __at (ADCON0_ADDR) ADCON0;
30 __sfr __at (OPTION_REG_ADDR) OPTION_REG;
31 __sfr __at (TRISIO_ADDR) TRISIO;
32 __sfr __at (PIE1_ADDR) PIE1;
33 __sfr __at (PCON_ADDR) PCON;
34 __sfr __at (OSCCON_ADDR) OSCCON;
35 __sfr __at (OSCTUNE_ADDR) OSCTUNE;
36 __sfr __at (PR2_ADDR) PR2;
37 __sfr __at (WPU_ADDR) WPU;
38 __sfr __at (WPUA_ADDR) WPUA;
39 __sfr __at (IOC_ADDR) IOC;
40 __sfr __at (IOCA_ADDR) IOCA;
41 __sfr __at (VRCON_ADDR) VRCON;
42 __sfr __at (EEDATA_ADDR) EEDATA;
43 __sfr __at (EEDAT_ADDR) EEDAT;
44 __sfr __at (EEADR_ADDR) EEADR;
45 __sfr __at (EECON1_ADDR) EECON1;
46 __sfr __at (EECON2_ADDR) EECON2;
47 __sfr __at (ADRESL_ADDR) ADRESL;
48 __sfr __at (ANSEL_ADDR) ANSEL;
51 // bitfield definitions
53 volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
54 volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
55 volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
56 volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
57 volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
58 volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
59 volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
60 volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
61 volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
62 volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
63 volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
64 volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
65 volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
66 volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
67 volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
68 volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
69 volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
70 volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
71 volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
72 volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;