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   1                               1 ;--------------------------------------------------------
   2                               2 ; File Created by SDCC : FreeWare ANSI-C Compiler
   3                               3 ; Version 2.1.9Ga Sun Jan 16 17:31:23 2000
   4                               4
   5                               5 ;--------------------------------------------------------
   6                               6         .module _divuint
   7                               7 ;--------------------------------------------------------
   8                               8 ; publics variables in this module
   9                               9 ;--------------------------------------------------------
  10                              10         .globl __divuint_PARM_2
  11                              11         .globl __divuint
  12                              12 ;--------------------------------------------------------
  13                              13 ; special function registers
  14                              14 ;--------------------------------------------------------
  15                              15 ;--------------------------------------------------------
  16                              16 ; special function bits
  17                              17 ;--------------------------------------------------------
  18                              18 ;--------------------------------------------------------
  19                              19 ; internal ram data
  20                              20 ;--------------------------------------------------------
  21                              21         .area   DSEG    (DATA)
  22                              22 ;--------------------------------------------------------
  23                              23 ; overlayable items in internal ram
  24                              24 ;--------------------------------------------------------
  25                              25         .area   OSEG    (OVR,DATA)
  26                              26 ;--------------------------------------------------------
  27                              27 ; indirectly addressable internal ram data
  28                              28 ;--------------------------------------------------------
  29                              29         .area   ISEG    (DATA)
  30                              30 ;--------------------------------------------------------
  31                              31 ; bit data
  32                              32 ;--------------------------------------------------------
  33                              33         .area   BSEG    (BIT)
  34    0000                      34 __divuint_c_1_1:
  35    0000                      35         .ds     0x0001
  36                              36 ;--------------------------------------------------------
  37                              37 ; external ram data
  38                              38 ;--------------------------------------------------------
  39                              39         .area   XSEG    (XDATA)
  40    0000                      40 __divuint_PARM_2:
  41    0000                      41         .ds     0x0002
  42    0002                      42 __divuint_a_1_1:
  43    0002                      43         .ds     0x0002
  44    0004                      44 __divuint_reste_1_1:
  45    0004                      45         .ds     0x0002
  46    0006                      46 __divuint_count_1_1:
  47    0006                      47         .ds     0x0001
  48                              48 ;--------------------------------------------------------
  49                              49 ; global & static initialisations
  50                              50 ;--------------------------------------------------------
  51                              51         .area GSINIT (CODE)
  52                              52 ;--------------------------------------------------------
  53                              53 ; code
  54                              54 ;--------------------------------------------------------
  55                              55         .area CSEG (CODE)
  56                     0000     56         G$_divuint$0$0 ==.
  57                              57 ;       _divuint.c 28
  58                              58 ;       -----------------------------------------
  59                              59 ;        function _divuint
  60                              60 ;       -----------------------------------------
  61    0000                      61 __divuint:
  62                     0002     62         ar2 = 0x02
  63                     0003     63         ar3 = 0x03
  64                     0004     64         ar4 = 0x04
  65                     0005     65         ar5 = 0x05
  66                     0006     66         ar6 = 0x06
  67                     0007     67         ar7 = 0x07
  68                     0000     68         ar0 = 0x00
  69                     0001     69         ar1 = 0x01
  70                              70 ;       _divuint.c 49
  71    0000 C0 83                71         push    dph
  72    0002 C0 82                72         push    dpl
  73    0004 90s00r02             73         mov     dptr,#__divuint_a_1_1
  74    0007 D0 E0                74         pop     acc
  75    0009 F0                   75         movx    @dptr,a
  76    000A D0 E0                76         pop     acc
  77    000C A3                   77         inc     dptr
  78    000D F0                   78         movx    @dptr,a
  79                              79 ;       _divuint.c 30
  80    000E 90s00r04             80         mov     dptr,#__divuint_reste_1_1
  81    0011 E4                   81         clr     a
  82    0012 A3                   82         inc     dptr
  83    0013 F0                   83         movx    @dptr,a
  84    0014 12s00r00             84         lcall   __decdptr
  85    0017 F0                   85         movx    @dptr,a
  86                              86 ;       _divuint.c 31
  87    0018 90s00r06             87         mov     dptr,#__divuint_count_1_1
  88    001B 74 10                88         mov     a,#0x10
  89    001D F0                   89         movx    @dptr,a
  90                              90 ;       _divuint.c 34
  91    001E 90s00r00             91         mov     dptr,#__divuint_PARM_2
  92    0021 E0                   92         movx    a,@dptr
  93    0022 FA                   93         mov     r2,a
  94    0023 A3                   94         inc     dptr
  95    0024 E0                   95         movx    a,@dptr
  96    0025 FB                   96         mov     r3,a
  97    0026                      97 00105$:
  98                              98 ;       _divuint.c 36
  99    0026 90s00r02             99         mov     dptr,#__divuint_a_1_1
 100    0029 E0                  100         movx    a,@dptr
 101    002A FC                  101         mov     r4,a
 102    002B A3                  102         inc     dptr
 103    002C E0                  103         movx    a,@dptr
 104                             104 ; Peephole 105   removed redundant mov
 105    002D FD                  105         mov  r5,a
 106    002E 23                  106         rl      a
 107    002F 54 01               107         anl     a,#0x01
 108    0031 FE                  108         mov     r6,a
 109                             109 ;       _divuint.c 37
 110    0032 ED                  110         mov     a,r5
 111    0033 CC                  111         xch     a,r4
 112    0034 25 E0               112         add     a,acc
 113    0036 CC                  113         xch     a,r4
 114    0037 33                  114         rlc     a
 115    0038 FD                  115         mov     r5,a
 116    0039 90s00r02            116         mov     dptr,#__divuint_a_1_1
 117    003C EC                  117         mov     a,r4
 118    003D F0                  118         movx    @dptr,a
 119    003E A3                  119         inc     dptr
 120    003F ED                  120         mov     a,r5
 121    0040 F0                  121         movx    @dptr,a
 122                             122 ;       _divuint.c 38
 123    0041 90s00r04            123         mov     dptr,#__divuint_reste_1_1
 124    0044 E0                  124         movx    a,@dptr
 125    0045 FF                  125         mov     r7,a
 126    0046 A3                  126         inc     dptr
 127    0047 E0                  127         movx    a,@dptr
 128                             128 ; Peephole 105   removed redundant mov
 129    0048 F8                  129         mov  r0,a
 130    0049 CF                  130         xch     a,r7
 131    004A 25 E0               131         add     a,acc
 132    004C CF                  132         xch     a,r7
 133    004D 33                  133         rlc     a
 134    004E F8                  134         mov     r0,a
 135    004F 90s00r04            135         mov     dptr,#__divuint_reste_1_1
 136    0052 EF                  136         mov     a,r7
 137    0053 F0                  137         movx    @dptr,a
 138    0054 A3                  138         inc     dptr
 139    0055 E8                  139         mov     a,r0
 140    0056 F0                  140         movx    @dptr,a
 141                             141 ;       _divuint.c 39
 142    0057 EE                  142         mov     a,r6
 143                             143 ; Peephole 110   removed ljmp by inverse jump logic
 144    0058 60 0A               144         jz  00102$
 145    005A                     145 00114$:
 146                             146 ;       _divuint.c 40
 147    005A 90s00r04            147         mov     dptr,#__divuint_reste_1_1
 148    005D 74 01               148         mov     a,#0x01
 149    005F 4F                  149         orl     a,r7
 150    0060 F0                  150         movx    @dptr,a
 151    0061 A3                  151         inc     dptr
 152    0062 E8                  152         mov     a,r0
 153    0063 F0                  153         movx    @dptr,a
 154    0064                     154 00102$:
 155                             155 ;       _divuint.c 42
 156    0064 90s00r04            156         mov     dptr,#__divuint_reste_1_1
 157    0067 E0                  157         movx    a,@dptr
 158    0068 FE                  158         mov     r6,a
 159    0069 A3                  159         inc     dptr
 160    006A E0                  160         movx    a,@dptr
 161    006B FF                  161         mov     r7,a
 162    006C C3                  162         clr     c
 163    006D EE                  163         mov     a,r6
 164    006E 9A                  164         subb    a,r2
 165    006F EF                  165         mov     a,r7
 166    0070 9B                  166         subb    a,r3
 167                             167 ; Peephole 132   changed ljmp to sjmp
 168                             168 ; Peephole 160   removed sjmp by inverse jump logic
 169    0071 40 15               169         jc   00106$
 170    0073                     170 00115$:
 171                             171 ;       _divuint.c 43
 172    0073 90s00r04            172         mov     dptr,#__divuint_reste_1_1
 173    0076 C3                  173         clr     c
 174    0077 EE                  174         mov     a,r6
 175    0078 9A                  175         subb    a,r2
 176    0079 F0                  176         movx    @dptr,a
 177    007A EF                  177         mov     a,r7
 178    007B 9B                  178         subb    a,r3
 179    007C A3                  179         inc     dptr
 180    007D F0                  180         movx    @dptr,a
 181                             181 ;       _divuint.c 45
 182    007E 90s00r02            182         mov     dptr,#__divuint_a_1_1
 183    0081 74 01               183         mov     a,#0x01
 184    0083 4C                  184         orl     a,r4
 185    0084 F0                  185         movx    @dptr,a
 186    0085 A3                  186         inc     dptr
 187    0086 ED                  187         mov     a,r5
 188    0087 F0                  188         movx    @dptr,a
 189    0088                     189 00106$:
 190                             190 ;       _divuint.c 47
 191    0088 90s00r06            191         mov     dptr,#__divuint_count_1_1
 192    008B E0                  192         movx    a,@dptr
 193    008C 24 FF               193         add     a,#0xff
 194                             194 ; Peephole 100   removed redundant mov
 195    008E FC                  195         mov  r4,a
 196    008F 90s00r06            196         mov  dptr,#__divuint_count_1_1
 197    0092 F0                  197         movx @dptr,a
 198    0093 EC                  198         mov     a,r4
 199    0094 60 03               199         jz      00116$
 200    0096 02s00r26            200         ljmp    00105$
 201    0099                     201 00116$:
 202                             202 ;       _divuint.c 49
 203    0099 90s00r02            203         mov     dptr,#__divuint_a_1_1
 204    009C E0                  204         movx    a,@dptr
 205    009D FA                  205         mov     r2,a
 206    009E A3                  206         inc     dptr
 207    009F E0                  207         movx    a,@dptr
 208    00A0 FB                  208         mov     r3,a
 209    00A1 8A 82               209         mov     dpl,r2
 210    00A3 8B 83               210         mov     dph,r3
 211    00A5                     211 00108$:
 212                     00A5    212         C$_divuint.c$50$1$1 ==.
 213                     00A5    213         XG$_divuint$0$0 ==.
 214    00A5 22                  214         ret
 215                             215         .area   CSEG    (CODE)