1 #if !defined( __Z180_H__ )
4 *---------------------------------------------------------------------------
8 * PURPOSE: definitions on the built in I/O ports for the Z180/HD64180
11 * Makes use of the newly included Z80 I/O support in SDCC
13 * AUTHOR : Peter Townson 2003
15 *---------------------------------------------------------------------------
17 #if !defined( Z180_IO_BASE )
18 #define Z180_IO_BASE 0 /* zero is the Reset default */
21 /* will want this to be the case by default (I think) */
24 static void _ENABLE_Z180_ASSEMBLER_(void) __naked { __asm .hd64 __endasm; }
27 *---------------------------------------------------------------------------
28 * Z180/HD64180 internal port addresses
30 __sfr __at (Z180_IO_BASE+0x00) CNTLA0; /* ASCI control register A channel 0 */
31 __sfr __at (Z180_IO_BASE+0x01) CNTLA1; /* ASCI control register A channel 1 */
32 __sfr __at (Z180_IO_BASE+0x02) CNTLB0; /* ASCI control register B channel 0 */
33 __sfr __at (Z180_IO_BASE+0x03) CNTLB1; /* ASCI control register B channel 0 */
34 __sfr __at (Z180_IO_BASE+0x04) STAT0 ; /* ASCI status register channel 0 */
35 __sfr __at (Z180_IO_BASE+0x05) STAT1 ; /* ASCI status register channel 1 */
36 __sfr __at (Z180_IO_BASE+0x06) TDR0 ; /* ASCI transmit data reg, channel 0 */
37 __sfr __at (Z180_IO_BASE+0x07) TDR1 ; /* ASCI transmit data reg, channel 1 */
38 __sfr __at (Z180_IO_BASE+0x08) RDR0 ; /* ASCI receive data reg, channel 0 */
39 __sfr __at (Z180_IO_BASE+0x09) RDR1 ; /* ASCI receive data reg, channel 0 */
40 __sfr __at (Z180_IO_BASE+0x0A) CNTR ; /* CSI/0 control register */
41 __sfr __at (Z180_IO_BASE+0x0B) TRDR ; /* CSI/0 transmit/receive data reg */
43 __sfr __at (Z180_IO_BASE+0x0C) TMDR0L; /* Timer data register, channel 0L */
44 __sfr __at (Z180_IO_BASE+0x0D) TMDR0H; /* Timer data register, channel 0H */
45 __sfr __at (Z180_IO_BASE+0x0E) RLDR0L; /* Timer reload register, channel 0L */
46 __sfr __at (Z180_IO_BASE+0x0F) RLDR0H; /* Timer reload register, channel 0H */
47 __sfr __at (Z180_IO_BASE+0x10) TCR ; /* Timer control register */
48 __sfr __at (Z180_IO_BASE+0x14) TMDR1L; /* Timer data register, channel 1L */
49 __sfr __at (Z180_IO_BASE+0x15) TMDR1H; /* Timer data register, channel 1H */
50 __sfr __at (Z180_IO_BASE+0x16) RLDR1L; /* Timer reload register, channel 1L */
51 __sfr __at (Z180_IO_BASE+0x17) RLDR1H; /* Timer reload register, channel 1H */
52 __sfr __at (Z180_IO_BASE+0x18) FRC ; /* Timer Free running counter */
54 __sfr __at (Z180_IO_BASE+0x20) SAR0L ; /* DMA source address reg, channel 0L */
55 __sfr __at (Z180_IO_BASE+0x21) SAR0H ; /* DMA source address reg, channel 0H */
56 __sfr __at (Z180_IO_BASE+0x22) SAR0B ; /* DMA source address reg, channel 0B */
57 __sfr __at (Z180_IO_BASE+0x23) DAR0L ; /* DMA dest address reg, channel 0L */
58 __sfr __at (Z180_IO_BASE+0x24) DAR0H ; /* DMA dest address reg, channel 0H */
59 __sfr __at (Z180_IO_BASE+0x25) DAR0B ; /* DMA dest address reg, channel 0B */
60 __sfr __at (Z180_IO_BASE+0x26) BCR0L ; /* DMA byte count reg, channel 0L */
61 __sfr __at (Z180_IO_BASE+0x27) BCR0H ; /* DMA byte count reg, channel 0H */
62 __sfr __at (Z180_IO_BASE+0x28) MAR1L ; /* DMA memory address reg, channel 1L */
63 __sfr __at (Z180_IO_BASE+0x29) MAR1H ; /* DMA memory address reg, channel 1H */
64 __sfr __at (Z180_IO_BASE+0x2A) MAR1B ; /* DMA memory address reg, channel 1B */
65 __sfr __at (Z180_IO_BASE+0x2B) IAR1L ; /* DMA I/O address reg, channel 1L */
66 __sfr __at (Z180_IO_BASE+0x2C) IAR1H ; /* DMA I/O address reg, channel 1H */
67 __sfr __at (Z180_IO_BASE+0x2E) BCR1L ; /* DMA byte count reg, channel 1L */
68 __sfr __at (Z180_IO_BASE+0x2F) BCR1H ; /* DMA byte count reg, channel 1H */
69 __sfr __at (Z180_IO_BASE+0x30) DSTAT ; /* DMA status register */
70 __sfr __at (Z180_IO_BASE+0x31) DMODE ; /* DMA mode register */
71 __sfr __at (Z180_IO_BASE+0x32) DCNTL ; /* DMA/WAIT control register */
73 __sfr __at (Z180_IO_BASE+0x33) IL ; /* Interrupt vector low register */
74 __sfr __at (Z180_IO_BASE+0x34) ITC ; /* INT/TRAP control register */
76 __sfr __at (Z180_IO_BASE+0x36) RCR ; /* Refresh control register */
78 __sfr __at (Z180_IO_BASE+0x38) CBR ; /* MMU common base register */
79 __sfr __at (Z180_IO_BASE+0x39) BBR ; /* MMU bank base register */
80 __sfr __at (Z180_IO_BASE+0x3A) CBAR ; /* MMU common/bank area register */
82 __sfr __at (Z180_IO_BASE+0x3E) OMCR ; /* Operation mode control register */
84 __sfr __at 0x3F ICR ; /* I/O base control register - does not move */
87 *---------------------------------------------------------------------------
88 * Interrupt vectors (offsets) for Z180/HD64180 internal interrupts
90 #define INT1_VECTOR 0x00 /* external /INT1 */
91 #define INT2_VECTOR 0x02 /* external /INT2 */
92 #define PRT0_VECTOR 0x04 /* PRT channel 0 */
93 #define PRT1_VECTOR 0x06 /* PRT channel 1 */
94 #define DMA0_VECTOR 0x08 /* DMA channel 0 */ /* ???? */
95 #define DMA1_VECTOR 0x0A /* DMA Channel 1 */
96 #define CSIO_VECTOR 0x0C /* Clocked serial I/O */
97 #define ASCI0_VECTOR 0x0E /* Async channel 0 */
98 #define ASCI1_VECTOR 0x10 /* Async channel 1 */
99 #define INCAP_VECTOR 0x12 /* input capture */
100 #define OUTCMP_VECTOR 0x14 /* output compare */
101 #define TIMOV_VECTOR 0x16 /* timer overflow */
103 *---------------------------------------------------------------------------
105 #endif /* __Z180_H__ */