1 /*-------------------------------------------------------------------------
2 Register Declarations for SIEMENS SAB 80515 Processor
4 Written By - Bela Torok
6 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
7 KEIL C compatible definitions are included
9 This program is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published by the
11 Free Software Foundation; either version 2, or (at your option) any
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 In other words, you are welcome to use, share and improve this program.
24 You are forbidden to forbid anyone else to use, share and improve
25 what you give them. Help stamp out software-hoarding!
26 -------------------------------------------------------------------------*/
31 /* BYTE addressable registers */
48 sfr at 0xA8 IEN0 ; /* as called by Siemens */
49 sfr at 0xA9 IP0 ; /* interrupt priority register - SAB80515 specific */
51 sfr at 0xB8 IEN1 ; /* interrupt enable register - SAB80515 specific */
52 sfr at 0xB9 IP1 ; /* interrupt priority register as called by Siemens */
53 sfr at 0xC0 IRCON ; /* interrupt control register - SAB80515 specific */
54 sfr at 0xC1 CCEN ; /* compare/capture enable register */
55 sfr at 0xC2 CCL1 ; /* compare/capture register 1, low byte */
56 sfr at 0xC3 CCH1 ; /* compare/capture register 1, high byte */
57 sfr at 0xC4 CCL2 ; /* compare/capture register 2, low byte */
58 sfr at 0xC5 CCH2 ; /* compare/capture register 2, high byte */
59 sfr at 0xC6 CCL3 ; /* compare/capture register 3, low byte */
60 sfr at 0xC7 CCH3 ; /* compare/capture register 3, high byte */
62 sfr at 0xCA CRCL ; /* compare/reload/capture register, low byte */
63 sfr at 0xCB CRCH ; /* compare/reload/capture register, high byte */
67 sfr at 0xD8 ADCON ; /* A/D-converter control register */
68 sfr at 0xD9 ADDAT ; /* A/D-converter data register */
69 sfr at 0xD8 DAPR ; /* D/A-converter program register */
72 sfr at 0xE8 P4 ; /* Port 4 - SAB80515 specific */
74 sfr at 0xF8 P5 ; /* Port 5 - SAB80515 specific */
77 /* BIT addressable registers */
108 sbit at 0x90 INT3_CC0 ; /* P1 alternate functions - SAB80515 specific */
109 sbit at 0x91 INT4_CC1 ;
110 sbit at 0x92 INT5_CC2 ;
111 sbit at 0x93 INT6_CC3 ;
114 sbit at 0x96 CLKOUT ;
144 sbit at 0xAE WDT ; /* watchdog timer reset - SAB80515 specific */
147 sbit at 0xAF EAL ; /* EA as called by Siemens */
169 sbit at 0xB8 EADC ; /* A/D converter interrupt enable */
175 sbit at 0xBE SWDT ; /* watchdog timer start/reset */
176 sbit at 0xBF EXEN2 ; /* timer2 external reload interrupt enable */
179 sbit at 0xC0 IADC ; /* A/D converter irq flag */
180 sbit at 0xC1 IEX2 ; /* external interrupt edge detect flag */
185 sbit at 0xC6 TF2 ; /* timer 2 owerflow flag */
186 sbit at 0xC7 EXF2 ; /* timer2 reload flag */
189 sbit at 0xC8 T2CON_0 ;
190 sbit at 0xC9 T2CON_1 ;
191 sbit at 0xCA T2CON_2 ;
192 sbit at 0xCB T2CON_3 ;
193 sbit at 0xCC T2CON_4 ;
194 sbit at 0xCD T2CON_5 ;
195 sbit at 0xCE T2CON_6 ;
196 sbit at 0xCF T2CON_7 ;
231 sbit at 0xA0 AREG_F0 ;
232 sbit at 0xA1 AREG_F1 ;
233 sbit at 0xA2 AREG_F2 ;
234 sbit at 0xA3 AREG_F3 ;
235 sbit at 0xA4 AREG_F4 ;
236 sbit at 0xA5 AREG_F5 ;
237 sbit at 0xA6 AREG_F6 ;
238 sbit at 0xA7 AREG_F7 ;
251 sbit at 0xF0 BREG_F0 ;
252 sbit at 0xF1 BREG_F1 ;
253 sbit at 0xF2 BREG_F2 ;
254 sbit at 0xF3 BREG_F3 ;
255 sbit at 0xF4 BREG_F4 ;
256 sbit at 0xF5 BREG_F5 ;
257 sbit at 0xF6 BREG_F6 ;
258 sbit at 0xF7 BREG_F7 ;
270 /* BIT definitions for bits that are not directly accessible */
315 #define T0_GATE_ 0x08
319 #define T1_GATE_ 0x80
324 #define T0_MASK_ 0x0F
325 #define T1_MASK_ 0xF0
335 #define WMCON_WDTEN 0x01
336 #define WMCON_WDTRST 0x02
337 #define WMCON_DPS 0x04
338 #define WMCON_EEMEN 0x08
339 #define WMCON_EEMWE 0x10
340 #define WMCON_PS0 0x20
341 #define WMCON_PS1 0x40
342 #define WMCON_PS2 0x80
345 #define SPCR_SPR0 0x01
346 #define SPCR_SPR1 0x02
347 #define SPCR_CPHA 0x04
348 #define SPCR_CPOL 0x08
349 #define SPCR_MSTR 0x10
350 #define SPCR_DORD 0x20
351 #define SPCR_SPE 0x40
352 #define SPCR_SPIE 0x80
355 #define SPSR_WCOL 0x40
356 #define SPSR_SPIF 0x80
359 #define SPDR_SPD0 0x10
360 #define SPDR_SPD1 0x20
361 #define SPDR_SPD2 0x40
362 #define SPDR_SPD3 0x80
363 #define SPDR_SPD4 0x10
364 #define SPDR_SPD5 0x20
365 #define SPDR_SPD6 0x40
366 #define SPDR_SPD7 0x80
368 /* Interrupt numbers: address = (number * 8) + 3 */
369 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
370 #define TF0_VECTOR 1 /* 0x0b timer 0 */
371 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
372 #define TF1_VECTOR 3 /* 0x1b timer 1 */
373 #define SI0_VECTOR 4 /* 0x23 serial port 0 */
374 #define TF2_VECTOR 5 /* 0x2B timer 2 */
375 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
377 #define IADC_VECTOR 8 /* 0x43 A/D converter interrupt */
378 #define IEX2_VECTOR 9 /* 0x4B external interrupt 2 */
379 #define IEX3_VECTOR 10 /* 0x53 external interrupt 3 */
380 #define IEX4_VECTOR 11 /* 0x5B external interrupt 4 */
381 #define IEX5_VECTOR 12 /* 0x63 external interrupt 5 */
382 #define IEX6_VECTOR 13 /* 0x6B external interrupt 6 */