1 /*-------------------------------------------------------------------------
2 Register Declarations for 87C764
3 Written By - Robert Lacoste, robert_lacoste@yahoo.fr
4 based upon reg51.h written by Sandeep Dutta
5 Registers are taken from the Phillips Semiconductor
7 This program is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 In other words, you are welcome to use, share and improve this program.
22 You are forbidden to forbid anyone else to use, share and improve
23 what you give them. Help stamp out software-hoarding!
24 -------------------------------------------------------------------------*/
29 /* Special Function Registers */
31 sfr at 0x80 P0 ; // Port 0
32 sfr at 0x81 SP ; // Stack Pointer
33 sfr at 0x82 DPL ; // Data Pointer Low
34 sfr at 0x83 DPH ; // Data Pointer High
35 sfr at 0x84 P0M1 ; // Port 0 output mode 1
36 sfr at 0x85 P0M2 ; // Port 0 output mode 2
37 sfr at 0x86 KBI ; // Keyboard interrupt
38 sfr at 0x87 PCON ; // Power Control
39 sfr at 0x88 TCON ; // Timer Control
40 sfr at 0x89 TMOD ; // Timer Mode
41 sfr at 0x8A TL0 ; // Timer Low 0
42 sfr at 0x8B TL1 ; // Timer Low 1
43 sfr at 0x8C TH0 ; // Timer High 0
44 sfr at 0x8D TH1 ; // Timer High 1
46 sfr at 0x90 P1 ; // Port 1
47 sfr at 0x91 P1M1 ; // Port 1 output mode 1
48 sfr at 0x92 P1M2 ; // Port 1 output mode 2
49 sfr at 0x95 DIVM ; // CPU clock divide by N control
50 sfr at 0x98 SCON ; // Serial Control
51 sfr at 0x99 SBUF ; // Serial Data Buffer
53 sfr at 0xA0 P2 ; // Port 2
54 sfr at 0xA2 AUXR1 ; // Auxilliary 1 (not available on 80C51FA/87C51Fx)
55 sfr at 0xA4 P2M1 ; // Port 2 output mode 1
56 sfr at 0xA5 P2M2 ; // Port 2 output mode 2
57 sfr at 0xA6 WDRST ; // Watchdog reset register
58 sfr at 0xA7 WDCON ; // Watchdog control register
59 sfr at 0xA8 IEN0 ; // Interrupt Enable 0
60 sfr at 0xA9 SADDR ; // Serial slave Address
61 sfr at 0xAC CMP1 ; // Comparator 1 control register
62 sfr at 0xAD CMP2 ; // Comparator 2 control register
64 sfr at 0xB7 IP0H ; // Interrupt Priority 0 High
65 sfr at 0xB8 IP0 ; // Interrupt Priority 0
66 sfr at 0xB9 SADEN ; // Serial slave Address Mask
68 sfr at 0xC8 I2CFG ; // I2C configuration register
70 sfr at 0xD0 PSW ; // Program Status Word
71 sfr at 0xD8 I2CON ; // I2C control register
72 sfr at 0xD9 I2DAT ; // I2C data register
74 sfr at 0xE0 ACC ; // Accumulator
75 sfr at 0xE8 IEN1 ; // Interrupt enable 1
77 sfr at 0xF0 B ; // B Register
78 sfr at 0xF6 PT0AD ; // Port 0 digital input disable
79 sfr at 0xF7 IP1H ; // Interrupt Priority 1 High
80 sfr at 0xF8 IP1 ; // Interrupt Priority 1
83 /* Bit Addressable Registers */
86 sbit at 0x80 P0_0 ; // Also CMP2
87 sbit at 0x81 P0_1 ; // Also CIN2B
88 sbit at 0x82 P0_2 ; // Also CIN2A
89 sbit at 0x83 P0_3 ; // Also CIN1B
90 sbit at 0x84 P0_4 ; // Also CIN1A
91 sbit at 0x85 P0_5 ; // Also CMPREF
92 sbit at 0x86 P0_6 ; // Also CMP1
93 sbit at 0x87 P0_7 ; // Also T1
96 sbit at 0x88 IT0 ; // External Interrupt 0 Type
97 sbit at 0x89 IE0 ; // External Interrupt 0 Edge Flag
98 sbit at 0x8A IT1 ; // External Interrupt 1 Type
99 sbit at 0x8B IE1 ; // External Interrupt 1 Edge Flag
100 sbit at 0x8C TR0 ; // Timer 0 Run Control
101 sbit at 0x8D TF0 ; // Timer 0 Overflow Flag
102 sbit at 0x8E TR1 ; // Timer 1 Run Control
103 sbit at 0x8F TF1 ; // Timer 1 Overflow Flag
106 sbit at 0x90 P1_0 ; // Also TxD
107 sbit at 0x91 P1_1 ; // Also RxD
108 sbit at 0x92 P1_2 ; // Also T0
109 sbit at 0x93 P1_3 ; // Also INT0
110 sbit at 0x94 P1_4 ; // Also INT1
111 sbit at 0x95 P1_5 ; // Also RST
116 sbit at 0x98 RI ; // Receive Interrupt Flag
117 sbit at 0x99 TI ; // Transmit Interrupt Flag
118 sbit at 0x9A RB8 ; // Receive Bit 8
119 sbit at 0x9B TB8 ; // Transmit Bit 8
120 sbit at 0x9C REN ; // Receiver Enable
121 sbit at 0x9D SM2 ; // Serial Mode Control Bit 2
122 sbit at 0x9E SM1 ; // Serial Mode Control Bit 1
123 sbit at 0x9F SM0 ; // Serial Mode Control Bit 0
126 sbit at 0xA0 P2_0 ; // Also X2
127 sbit at 0xA1 P2_1 ; // Also X1
130 sbit at 0xA8 EX0 ; // External Interrupt 0 Enable
131 sbit at 0xA9 ET0 ; // Timer 0 Interrupt Enable
132 sbit at 0xAA EX1 ; // External Interrupt 1 Enable
133 sbit at 0xAB ET1 ; // Timer 1 Interrupt Enable
134 sbit at 0xAC ES ; // Serial Port Interrupt Enable
135 sbit at 0xAD EBO ; // Brownout Interrupt Enable
136 sbit at 0xAE EWD ; // Watchdog Interrupt Enable
137 sbit at 0xAF EA ; // Global Interrupt Enable
140 sbit at 0xB8 PX0 ; // External Interrupt 0 Priority
141 sbit at 0xB9 PT0 ; // Timer 0 Interrupt Priority
142 sbit at 0xBA PX1 ; // External Interrupt 1 Priority
143 sbit at 0xBB PT1 ; // Timer 1 Interrupt Priority
144 sbit at 0xBC PS ; // Serial Port Interrupt Priority
145 sbit at 0xBD PB0 ; // Brownout Interrupt Priority
146 sbit at 0xBE PWD ; // Watchdog Interrupt Priority
149 sbit at 0xC8 CT0 ; // Clock Time Select 0
150 sbit at 0xC9 CT1 ; // Clock Time Select 1
151 sbit at 0xCC TIRUN ; // Timer I Run Enable
152 sbit at 0xCD CLRTI ; // Clear Timer I
153 sbit at 0xCE MASTRQ; // Master Request
154 sbit at 0xCF SLAVEN; // Slave Enable
157 sbit at 0xD0 P ; // Accumulator Parity Flag
158 sbit at 0xD1 F1 ; // Flag 1
159 sbit at 0xD2 OV ; // Overflow Flag
160 sbit at 0xD3 RS0 ; // Register Bank Select 0
161 sbit at 0xD4 RS1 ; // Register Bank Select 1
162 sbit at 0xD5 F0 ; // Flag 0
163 sbit at 0xD6 AC ; // Auxiliary Carry Flag
164 sbit at 0xD7 CY ; // Carry Flag
168 sbit at 0xD9 MASTER;// Master Status
169 sbit at 0xDA STP ; // Stop Detect Flag
170 sbit at 0xDB STR ; // Start Detect Flag
171 sbit at 0xDC ARL ; // Arbitration Loss Flag
172 sbit at 0xDD DRDY ; // Data Ready Flag
173 sbit at 0xDE ATN ; // Attention: I2C Interrupt Flag
174 sbit at 0xDF RDAT ; // I2C Read Data
187 sbit at 0xE8 EI2 ; // I2C Interrupt Enable
188 sbit at 0xE9 EKB ; // Keyboard Interrupt Enable
189 sbit at 0xEA EC2 ; // Comparator 2 Interrupt Enable
190 sbit at 0xED EC1 ; // Comparator 1 Interrupt Enable
191 sbit at 0xEF ETI ; // Timer I Interrupt Enable
204 sbit at 0xF8 PI2; // I2C Interrupt Priority
205 sbit at 0xF9 PKB; // Keyboard Interrupt Priority
206 sbit at 0xFA PC2; // Comparator 2 Interrupt Priority
207 sbit at 0xFD PC1; // Comparator 1 Interrupt Priority
208 sbit at 0xFF PTI; // Timer I Interrupt Priority
210 /* Bitmasks for SFRs */
284 /* Masks for I2CFG bits */
285 #define BTIR 0x10 // Mask for TIRUN bit.
286 #define BMRQ 0x40 // Mask for MASTRQ bit.
287 #define BSLV 0x80 // Mask for SLAVEN bit.
290 /* Masks for I2CON bits */
291 #define BCXA 0x80 // Mask for CXA bit.
292 #define BIDLE 0x40 // Mask for IDLE bit.
293 #define BCDR 0x20 // Mask for CDR bit.
294 #define BCARL 0x10 // Mask for CARL bit.
295 #define BCSTR 0x08 // Mask for CSTR bit.
296 #define BCSTP 0x04 // Mask for CSTP bit.
297 #define BXSTR 0x02 // Mask for XSTR bit.
298 #define BXSTP 0x01 // Mask for XSTP bit.