3 * pic18f8680.h - PIC18F8680 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F8680_H__
16 #define __PIC18F8680_H__
18 extern sfr at 0xf00 RXF0SIDH;
19 extern sfr at 0xf01 RXF0SIDL;
33 extern volatile __RXF0SIDLbits_t at 0xf01 RXF0SIDLbits;
35 extern sfr at 0xf02 RXF0EIDH;
36 extern sfr at 0xf03 RXF0EIDL;
37 extern sfr at 0xf04 RXF1SIDH;
38 extern sfr at 0xf05 RXF1SIDL;
52 extern volatile __RXF1SIDLbits_t at 0xf05 RXF1SIDLbits;
54 extern sfr at 0xf06 RXF1EIDH;
55 extern sfr at 0xf07 RXF1EIDL;
56 extern sfr at 0xf08 RXF2SIDH;
57 extern sfr at 0xf09 RXF2SIDL;
58 extern sfr at 0xf0a RXF2EIDH;
59 extern sfr at 0xf0b RXF2EIDL;
73 extern volatile __RXF2EIDLbits_t at 0xf0b RXF2EIDLbits;
75 extern sfr at 0xf0c RXF3SIDH;
76 extern sfr at 0xf0d RXF3SIDL;
90 extern volatile __RXF3SIDLbits_t at 0xf0d RXF3SIDLbits;
92 extern sfr at 0xf0e RXF3EIDH;
93 extern sfr at 0xf0f RXF3EIDL;
94 extern sfr at 0xf10 RXF4SIDH;
95 extern sfr at 0xf11 RXF4SIDL;
109 extern volatile __RXF4SIDLbits_t at 0xf11 RXF4SIDLbits;
111 extern sfr at 0xf12 RXF4EIDH;
112 extern sfr at 0xf13 RXF4EIDL;
113 extern sfr at 0xf14 RXF5SIDH;
114 extern sfr at 0xf15 RXF5SIDL;
128 extern volatile __RXF5SIDLbits_t at 0xf15 RXF5SIDLbits;
130 extern sfr at 0xf16 RXF5EIDH;
131 extern sfr at 0xf17 RXF5EIDL;
132 extern sfr at 0xf18 RXM0SIDH;
133 extern sfr at 0xf19 RXM0SIDL;
147 extern volatile __RXM0SIDLbits_t at 0xf19 RXM0SIDLbits;
149 extern sfr at 0xf1a RXM0EIDH;
150 extern sfr at 0xf1b RXM0EIDL;
151 extern sfr at 0xf1c RXM1SIDH;
152 extern sfr at 0xf1d RXM1SIDL;
166 extern volatile __RXM1SIDLbits_t at 0xf1d RXM1SIDLbits;
168 extern sfr at 0xf1e RXM1EIDH;
169 extern sfr at 0xf1f RXM1EIDL;
170 extern sfr at 0xf20 TXB2CON;
184 extern volatile __TXB2CONbits_t at 0xf20 TXB2CONbits;
186 extern sfr at 0xf21 TXB2SIDH;
187 extern sfr at 0xf22 TXB2SIDL;
201 extern volatile __TXB2SIDLbits_t at 0xf22 TXB2SIDLbits;
203 extern sfr at 0xf23 TXB2EIDH;
204 extern sfr at 0xf24 TXB2EIDL;
205 extern sfr at 0xf25 TXB2DLC;
219 extern volatile __TXB2DLCbits_t at 0xf25 TXB2DLCbits;
221 extern sfr at 0xf26 TXB2D0;
222 extern sfr at 0xf27 TXB2D1;
223 extern sfr at 0xf28 TXB2D2;
224 extern sfr at 0xf29 TXB2D3;
225 extern sfr at 0xf2a TXB2D4;
226 extern sfr at 0xf2b TXB2D5;
227 extern sfr at 0xf2c TXB2D6;
228 extern sfr at 0xf2d TXB2D7;
229 extern sfr at 0xf2e CANSTATRO3;
230 extern sfr at 0xf30 TXB1CON;
244 extern volatile __TXB1CONbits_t at 0xf30 TXB1CONbits;
246 extern sfr at 0xf31 TXB1SIDH;
247 extern sfr at 0xf32 TXB1SIDL;
261 extern volatile __TXB1SIDLbits_t at 0xf32 TXB1SIDLbits;
263 extern sfr at 0xf33 TXB1EIDH;
264 extern sfr at 0xf34 TXB1EIDL;
265 extern sfr at 0xf35 TXB1DLC;
279 extern volatile __TXB1DLCbits_t at 0xf35 TXB1DLCbits;
281 extern sfr at 0xf36 TXB1D0;
282 extern sfr at 0xf37 TXB1D1;
283 extern sfr at 0xf38 TXB1D2;
284 extern sfr at 0xf39 TXB1D3;
285 extern sfr at 0xf3a TXB1D4;
286 extern sfr at 0xf3b TXB1D5;
287 extern sfr at 0xf3c TXB1D6;
288 extern sfr at 0xf3d TXB1D7;
289 extern sfr at 0xf3e CANSTATRO2;
290 extern sfr at 0xf40 TXB0CON;
304 extern volatile __TXB0CONbits_t at 0xf40 TXB0CONbits;
306 extern sfr at 0xf41 TXB0SIDH;
307 extern sfr at 0xf42 TXB0SIDL;
308 extern sfr at 0xf43 TXB0EIDH;
309 extern sfr at 0xf44 TXB0EIDL;
310 extern sfr at 0xf45 TXB0DLC;
324 extern volatile __TXB0DLCbits_t at 0xf45 TXB0DLCbits;
326 extern sfr at 0xf46 TXB0D0;
327 extern sfr at 0xf47 TXB0D1;
328 extern sfr at 0xf48 TXB0D2;
329 extern sfr at 0xf49 TXB0D3;
330 extern sfr at 0xf4a TXB0D4;
331 extern sfr at 0xf4b TXB0D5;
332 extern sfr at 0xf4c TXB0D6;
333 extern sfr at 0xf4d TXB0D7;
334 extern sfr at 0xf4e CANSTATRO1;
335 extern sfr at 0xf50 RXB1CON;
349 extern volatile __RXB1CONbits_t at 0xf50 RXB1CONbits;
351 extern sfr at 0xf51 RXB1SIDH;
352 extern sfr at 0xf52 RXB1SIDL;
366 extern volatile __RXB1SIDLbits_t at 0xf52 RXB1SIDLbits;
368 extern sfr at 0xf53 RXB1EIDH;
369 extern sfr at 0xf54 RXB1EIDL;
370 extern sfr at 0xf55 RXB1DLC;
384 extern volatile __RXB1DLCbits_t at 0xf55 RXB1DLCbits;
386 extern sfr at 0xf56 RXB1D0;
387 extern sfr at 0xf57 RXB1D1;
388 extern sfr at 0xf58 RXB1D2;
389 extern sfr at 0xf59 RXB1D3;
390 extern sfr at 0xf5a RXB1D4;
391 extern sfr at 0xf5b RXB1D5;
392 extern sfr at 0xf5c RXB1D6;
393 extern sfr at 0xf5d RXB1D7;
394 extern sfr at 0xf5e CANSTATRO0;
395 extern sfr at 0xf60 RXB0CON;
409 extern volatile __RXB0CONbits_t at 0xf60 RXB0CONbits;
411 extern sfr at 0xf61 RXB0SIDH;
412 extern sfr at 0xf62 RXB0SIDL;
426 extern volatile __RXB0SIDLbits_t at 0xf62 RXB0SIDLbits;
428 extern sfr at 0xf63 RXB0EIDH;
429 extern sfr at 0xf64 RXB0EIDL;
430 extern sfr at 0xf65 RXB0DLC;
431 extern sfr at 0xf66 RXB0D0;
432 extern sfr at 0xf67 RXB0D1;
433 extern sfr at 0xf68 RXB0D2;
434 extern sfr at 0xf69 RXB0D3;
435 extern sfr at 0xf6a RXB0D4;
436 extern sfr at 0xf6b RXB0D5;
437 extern sfr at 0xf6c RXB0D6;
438 extern sfr at 0xf6d RXB0D7;
439 extern sfr at 0xf6e CANSTAT;
453 extern volatile __CANSTATbits_t at 0xf6e CANSTATbits;
455 extern sfr at 0xf6f CANCON;
469 extern volatile __CANCONbits_t at 0xf6f CANCONbits;
471 extern sfr at 0xf70 BRGCON1;
485 extern volatile __BRGCON1bits_t at 0xf70 BRGCON1bits;
487 extern sfr at 0xf71 BRGCON2;
501 extern volatile __BRGCON2bits_t at 0xf71 BRGCON2bits;
503 extern sfr at 0xf72 BRGCON3;
517 extern volatile __BRGCON3bits_t at 0xf72 BRGCON3bits;
519 extern sfr at 0xf73 CIOCON;
533 extern volatile __CIOCONbits_t at 0xf73 CIOCONbits;
535 extern sfr at 0xf74 COMSTAT;
549 extern volatile __COMSTATbits_t at 0xf74 COMSTATbits;
551 extern sfr at 0xf75 RXERRCNT;
565 extern volatile __RXERRCNTbits_t at 0xf75 RXERRCNTbits;
567 extern sfr at 0xf76 TXERRCNT;
581 extern volatile __TXERRCNTbits_t at 0xf76 TXERRCNTbits;
583 extern sfr at 0xf80 PORTA;
630 extern volatile __PORTAbits_t at 0xf80 PORTAbits;
632 extern sfr at 0xf81 PORTB;
657 extern volatile __PORTBbits_t at 0xf81 PORTBbits;
659 extern sfr at 0xf82 PORTC;
695 extern volatile __PORTCbits_t at 0xf82 PORTCbits;
697 extern sfr at 0xf83 PORTD;
722 extern volatile __PORTDbits_t at 0xf83 PORTDbits;
724 extern sfr at 0xf84 PORTE;
760 extern volatile __PORTEbits_t at 0xf84 PORTEbits;
762 extern sfr at 0xf85 PORTF;
776 extern volatile __PORTFbits_t at 0xf85 PORTFbits;
778 extern sfr at 0xf86 PORTG;
792 extern volatile __PORTGbits_t at 0xf86 PORTGbits;
794 extern sfr at 0xf87 PORTH;
808 extern volatile __PORTHbits_t at 0xf87 PORTHbits;
810 extern sfr at 0xf88 PORTJ;
824 extern volatile __PORTJbits_t at 0xf88 PORTJbits;
826 extern sfr at 0xf89 LATA;
840 extern volatile __LATAbits_t at 0xf89 LATAbits;
842 extern sfr at 0xf8a LATB;
856 extern volatile __LATBbits_t at 0xf8a LATBbits;
858 extern sfr at 0xf8b LATC;
872 extern volatile __LATCbits_t at 0xf8b LATCbits;
874 extern sfr at 0xf8c LATD;
888 extern volatile __LATDbits_t at 0xf8c LATDbits;
890 extern sfr at 0xf8d LATE;
904 extern volatile __LATEbits_t at 0xf8d LATEbits;
906 extern sfr at 0xf8e LATF;
920 extern volatile __LATFbits_t at 0xf8e LATFbits;
922 extern sfr at 0xf8f LATG;
936 extern volatile __LATGbits_t at 0xf8f LATGbits;
938 extern sfr at 0xf90 LATH;
952 extern volatile __LATHbits_t at 0xf90 LATHbits;
954 extern sfr at 0xf91 LATJ;
968 extern volatile __LATJbits_t at 0xf91 LATJbits;
970 extern sfr at 0xf92 TRISA;
984 extern volatile __TRISAbits_t at 0xf92 TRISAbits;
986 extern sfr at 0xf93 TRISB;
1000 extern volatile __TRISBbits_t at 0xf93 TRISBbits;
1002 extern sfr at 0xf94 TRISC;
1016 extern volatile __TRISCbits_t at 0xf94 TRISCbits;
1018 extern sfr at 0xf95 TRISD;
1032 extern volatile __TRISDbits_t at 0xf95 TRISDbits;
1034 extern sfr at 0xf96 TRISE;
1048 extern volatile __TRISEbits_t at 0xf96 TRISEbits;
1050 extern sfr at 0xf97 TRISF;
1064 extern volatile __TRISFbits_t at 0xf97 TRISFbits;
1066 extern sfr at 0xf98 TRISG;
1080 extern volatile __TRISGbits_t at 0xf98 TRISGbits;
1082 extern sfr at 0xf99 TRISH;
1096 extern volatile __TRISHbits_t at 0xf99 TRISHbits;
1098 extern sfr at 0xf9a TRISJ;
1112 extern volatile __TRISJbits_t at 0xf9a TRISJbits;
1114 extern sfr at 0xf9c MEMCON;
1128 extern volatile __MEMCONbits_t at 0xf9c MEMCONbits;
1130 extern sfr at 0xf9d PIE1;
1144 extern volatile __PIE1bits_t at 0xf9d PIE1bits;
1146 extern sfr at 0xf9e PIR1;
1160 extern volatile __PIR1bits_t at 0xf9e PIR1bits;
1162 extern sfr at 0xf9f IPR1;
1176 extern volatile __IPR1bits_t at 0xf9f IPR1bits;
1178 extern sfr at 0xfa0 PIE2;
1192 extern volatile __PIE2bits_t at 0xfa0 PIE2bits;
1194 extern sfr at 0xfa1 PIR2;
1208 extern volatile __PIR2bits_t at 0xfa1 PIR2bits;
1210 extern sfr at 0xfa2 IPR2;
1224 extern volatile __IPR2bits_t at 0xfa2 IPR2bits;
1226 extern sfr at 0xfa3 PIE3;
1240 extern volatile __PIE3bits_t at 0xfa3 PIE3bits;
1242 extern sfr at 0xfa4 PIR3;
1256 extern volatile __PIR3bits_t at 0xfa4 PIR3bits;
1258 extern sfr at 0xfa5 IPR3;
1272 extern volatile __IPR3bits_t at 0xfa5 IPR3bits;
1274 extern sfr at 0xfa6 EECON1;
1288 extern volatile __EECON1bits_t at 0xfa6 EECON1bits;
1290 extern sfr at 0xfa7 EECON2;
1291 extern sfr at 0xfa8 EEDATA;
1292 extern sfr at 0xfa9 EEADR;
1293 extern sfr at 0xfaa EEADRH;
1294 extern sfr at 0xfab RCSTA;
1308 extern volatile __RCSTAbits_t at 0xfab RCSTAbits;
1310 extern sfr at 0xfac TXSTA;
1324 extern volatile __TXSTAbits_t at 0xfac TXSTAbits;
1326 extern sfr at 0xfad TXREG;
1327 extern sfr at 0xfae RCREG;
1328 extern sfr at 0xfaf SPBRG;
1329 extern sfr at 0xfb0 PSPCON;
1343 extern volatile __PSPCONbits_t at 0xfb0 PSPCONbits;
1345 extern sfr at 0xfb1 T3CON;
1359 extern volatile __T3CONbits_t at 0xfb1 T3CONbits;
1361 extern sfr at 0xfb2 TMR3L;
1362 extern sfr at 0xfb3 TMR3H;
1363 extern sfr at 0xfb4 CMCON;
1377 extern volatile __CMCONbits_t at 0xfb4 CMCONbits;
1379 extern sfr at 0xfb5 CVRCON;
1393 extern volatile __CVRCONbits_t at 0xfb5 CVRCONbits;
1395 extern sfr at 0xfb6 ECCPAS;
1409 extern volatile __ECCPASbits_t at 0xfb6 ECCPASbits;
1411 extern sfr at 0xfb7 ECCP1DEL;
1425 extern volatile __ECCP1DELbits_t at 0xfb7 ECCP1DELbits;
1427 extern sfr at 0xfba ECCP1CON;
1441 extern volatile __ECCP1CONbits_t at 0xfba ECCP1CONbits;
1443 extern sfr at 0xfba CCP2CON;
1457 extern volatile __CCP2CONbits_t at 0xfba CCP2CONbits;
1459 extern sfr at 0xfbb ECCPR1L;
1460 extern sfr at 0xfbb CCPR2L;
1461 extern sfr at 0xfbc ECCPR1H;
1462 extern sfr at 0xfbc CCPR2H;
1463 extern sfr at 0xfc0 ADCON2;
1477 extern volatile __ADCON2bits_t at 0xfc0 ADCON2bits;
1479 extern sfr at 0xfc1 ADCON1;
1493 extern volatile __ADCON1bits_t at 0xfc1 ADCON1bits;
1495 extern sfr at 0xfc2 ADCON0;
1509 extern volatile __ADCON0bits_t at 0xfc2 ADCON0bits;
1511 extern sfr at 0xfc3 ADRESL;
1512 extern sfr at 0xfc4 ADRESH;
1513 extern sfr at 0xfc5 SSPCON2;
1527 extern volatile __SSPCON2bits_t at 0xfc5 SSPCON2bits;
1529 extern sfr at 0xfc6 SSPCON1;
1543 extern volatile __SSPCON1bits_t at 0xfc6 SSPCON1bits;
1545 extern sfr at 0xfc7 SSPSTAT;
1559 extern volatile __SSPSTATbits_t at 0xfc7 SSPSTATbits;
1561 extern sfr at 0xfc8 SSPADD;
1562 extern sfr at 0xfc9 SSPBUF;
1563 extern sfr at 0xfca T2CON;
1577 extern volatile __T2CONbits_t at 0xfca T2CONbits;
1579 extern sfr at 0xfcb PR2;
1580 extern sfr at 0xfcc TMR2;
1581 extern sfr at 0xfcd T1CON;
1586 unsigned NOT_T1SYNC:1;
1595 extern volatile __T1CONbits_t at 0xfcd T1CONbits;
1597 extern sfr at 0xfce TMR1L;
1598 extern sfr at 0xfcf TMR1H;
1599 extern sfr at 0xfd0 RCON;
1613 extern volatile __RCONbits_t at 0xfd0 RCONbits;
1615 extern sfr at 0xfd1 WDTCON;
1640 extern volatile __WDTCONbits_t at 0xfd1 WDTCONbits;
1642 extern sfr at 0xfd2 LVDCON;
1667 extern volatile __LVDCONbits_t at 0xfd2 LVDCONbits;
1669 extern sfr at 0xfd3 OSCCON;
1683 extern volatile __OSCCONbits_t at 0xfd3 OSCCONbits;
1685 extern sfr at 0xfd5 T0CON;
1686 extern sfr at 0xfd6 TMR0L;
1687 extern sfr at 0xfd7 TMR0H;
1688 extern sfr at 0xfd8 STATUS;
1702 extern volatile __STATUSbits_t at 0xfd8 STATUSbits;
1704 extern sfr at 0xfd9 FSR2L;
1705 extern sfr at 0xfda FSR2H;
1706 extern sfr at 0xfdb PLUSW2;
1707 extern sfr at 0xfdc PREINC2;
1708 extern sfr at 0xfdd POSTDEC2;
1709 extern sfr at 0xfde POSTINC2;
1710 extern sfr at 0xfdf INDF2;
1711 extern sfr at 0xfe0 BSR;
1712 extern sfr at 0xfe1 FSR1L;
1713 extern sfr at 0xfe2 FSR1H;
1714 extern sfr at 0xfe3 PLUSW1;
1715 extern sfr at 0xfe4 PREINC1;
1716 extern sfr at 0xfe5 POSTDEC1;
1717 extern sfr at 0xfe6 POSTINC1;
1718 extern sfr at 0xfe7 INDF1;
1719 extern sfr at 0xfe8 WREG;
1720 extern sfr at 0xfe9 FSR0L;
1721 extern sfr at 0xfea FSR0H;
1722 extern sfr at 0xfeb PLUSW0;
1723 extern sfr at 0xfec PREINC0;
1724 extern sfr at 0xfed POSTDEC0;
1725 extern sfr at 0xfee POSTINC0;
1726 extern sfr at 0xfef INDF0;
1727 extern sfr at 0xff0 INTCON3;
1752 extern volatile __INTCON3bits_t at 0xff0 INTCON3bits;
1754 extern sfr at 0xff1 INTCON2;
1768 extern volatile __INTCON2bits_t at 0xff1 INTCON2bits;
1770 extern sfr at 0xff2 INTCON;
1784 extern volatile __INTCONbits_t at 0xff2 INTCONbits;
1786 extern sfr at 0xff3 PRODL;
1787 extern sfr at 0xff4 PRODH;
1788 extern sfr at 0xff5 TABLAT;
1789 extern sfr at 0xff6 TBLPTRL;
1790 extern sfr at 0xff7 TBLPTRH;
1791 extern sfr at 0xff8 TBLPTRU;
1792 extern sfr at 0xff9 PCL;
1793 extern sfr at 0xffa PCLATH;
1794 extern sfr at 0xffb PCLATU;
1795 extern sfr at 0xffc STKPTR;
1809 extern volatile __STKPTRbits_t at 0xffc STKPTRbits;
1811 extern sfr at 0xffd TOSL;
1812 extern sfr at 0xffe TOSH;
1813 extern sfr at 0xfff TOSU;
1816 /* Configuration registers locations */
1817 #define __CONFIG1H 0x300001
1818 #define __CONFIG2L 0x300002
1819 #define __CONFIG2H 0x300003
1820 #define __CONFIG3L 0x300004
1821 #define __CONFIG3H 0x300005
1822 #define __CONFIG4L 0x300006
1823 #define __CONFIG5L 0x300008
1824 #define __CONFIG5H 0x300009
1825 #define __CONFIG6L 0x30000A
1826 #define __CONFIG6H 0x30000B
1827 #define __CONFIG7L 0x30000C
1828 #define __CONFIG7H 0x30000D
1832 /* Oscillator 1H options */
1833 #define _OSC_RC_CLKOUT_1H 0xFF /* RC-CLKOUT on RA6 */
1834 #define _OSC_HS_SOFTWARE_1H 0xFE /* HS-Software enabled PLL */
1835 #define _OSC_EC_CLKOUT_Software_nabld_PLL_1H 0xFD /* EC-CLKOUT on RA6,Software_enabled_PLL */
1836 #define _OSC_EC_CLKOUT_PLL_enabld_frq_4xFosc1_1H 0xFC /* EC-CLKOUT on RA6,PLL_enabled_freq_4xFosc1 */
1837 #define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */
1838 #define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
1839 #define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */
1840 #define _OSC_EC_CLKOUT__1H 0xF4 /* EC-CLKOUT on RA6 */
1841 #define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
1842 #define _OSC_HS_1H 0xF2 /* HS */
1843 #define _OSC_XT_1H 0xF1 /* XT */
1844 #define _OSC_LP_1H 0xF0 /* LP */
1846 /* Low Power System Clock Timer1 Enable 1H options */
1847 #define _OSCSEN_ON_1H 0xDF /* Enabled */
1848 #define _OSCSEN_OFF_1H 0xFF /* Disabled */
1850 /* Power Up Timer 2L options */
1851 #define _PUT_OFF_2L 0xFF /* Disabled */
1852 #define _PUT_ON_2L 0xFE /* Enabled */
1854 /* Brown Out Detect 2L options */
1855 #define _BODEN_ON_2L 0xFF /* Enabled */
1856 #define _BODEN_OFF_2L 0xFD /* Disabled */
1858 /* Brown Out Voltage 2L options */
1859 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
1860 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
1861 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
1862 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
1864 /* Watchdog Timer 2H options */
1865 #define _WDT_ON_2H 0xFF /* Enabled */
1866 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1868 /* Watchdog Postscaler 2H options */
1869 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1870 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1871 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1872 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1873 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1874 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1875 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1876 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1877 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1878 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1879 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1880 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1881 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1882 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1883 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1884 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1886 /* Processor Mode 3L options */
1887 #define _PMODE_MICROCONTROLLER_3L 0xFF /* Microcontroller */
1888 #define _PMODE_MICROPROCESSOR__3L 0xFE /* Microprocessor */
1889 #define _PMODE_MICROPROCESSOR_w_Boot_3L 0xFD /* Microprocessor w_Boot */
1890 #define _PMODE_EXT_3L 0xFC /* Ext Microcontroller */
1892 /* External Bus Wait 3L options */
1893 #define _WAIT_OFF_3L 0xFF /* Disabled */
1894 #define _WAIT_ON_3L 0x7F /* Enabled */
1896 /* CCP2 Mux 3H options */
1897 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1898 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1900 /* ECCP Mux 3H options */
1901 #define _ECCPMX_ECCP1_E6E3_3H 0xFF /* ECCP1 and ECCP6 are muxed onto RE6 through RE3 */
1902 #define _ECCPMX_ECCP1_H7H4_3H 0xFD /* ECCP1 and ECCP6 are muxed onto RH7 through RH4 */
1904 /* MCLR enable 3H options */
1905 #define _MCLRE_MCLR_Enabled_RE3_Disabled_3H 0xFF /* MCLR Enabled_RE3_Disabled */
1906 #define _MCLRE_MCLR_Disabled_RE3_Enabled_3H 0x7F /* MCLR Disabled__RE3_Enabled */
1908 /* Stack Overflow Reset 4L options */
1909 #define _STVR_ON_4L 0xFF /* Enabled */
1910 #define _STVR_OFF_4L 0xFE /* Disabled */
1912 /* Low Voltage Program 4L options */
1913 #define _LVP_ON_4L 0xFF /* Enabled */
1914 #define _LVP_OFF_4L 0xFB /* Disabled */
1916 /* Background Debug 4L options */
1917 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1918 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1920 /* Code Protect 000800-0003FFF 5L options */
1921 #define _CP_0_OFF_5L 0xFF /* Disabled */
1922 #define _CP_0_ON_5L 0xFE /* Enabled */
1924 /* Code Protect 0004000-007FFF 5L options */
1925 #define _CP_1_OFF_5L 0xFF /* Disabled */
1926 #define _CP_1_ON_5L 0xFD /* Enabled */
1928 /* Code Protect 008000-00BFFF 5L options */
1929 #define _CP_2_OFF_5L 0xFF /* Disabled */
1930 #define _CP_2_ON_5L 0xFB /* Enabled */
1932 /* Code Protect 00C000F-00FFFF 5L options */
1933 #define _CP_3_OFF_5L 0xFF /* Disabled */
1934 #define _CP_3_ON_5L 0xF7 /* Enabled */
1936 /* Data EE Read Protect 5H options */
1937 #define _CPD_OFF_5H 0xFF /* Disabled */
1938 #define _CPD_ON_5H 0x7F /* Enabled */
1940 /* Code Protect Boot 5H options */
1941 #define _CPB_OFF_5H 0xFF /* Disabled */
1942 #define _CPB_ON_5H 0xBF /* Enabled */
1944 /* Table Write Protect 00800-003FFF 6L options */
1945 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1946 #define _WRT_0_ON_6L 0xFE /* Enabled */
1948 /* Table Write Protect 004000-007FFF 6L options */
1949 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1950 #define _WRT_1_ON_6L 0xFD /* Enabled */
1952 /* Table Write Protect 08000-0BFFF 6L options */
1953 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1954 #define _WRT_2_ON_6L 0xFB /* Enabled */
1956 /* Table Write Protect 0C000-0FFFF 6L options */
1957 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1958 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1960 /* Data EE Write Protect 6H options */
1961 #define _WRTD_OFF_6H 0xFF /* Disabled */
1962 #define _WRTD_ON_6H 0x7F /* Enabled */
1964 /* Table Write Protect Boot 6H options */
1965 #define _WRTB_OFF_6H 0xFF /* Disabled */
1966 #define _WRTB_ON_6H 0xBF /* Enabled */
1968 /* Config. Write Protect 6H options */
1969 #define _WRTC_OFF_6H 0xFF /* Disabled */
1970 #define _WRTC_ON_6H 0xDF /* Enabled */
1972 /* Table Read Protect 00800-003FFF 7L options */
1973 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1974 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1976 /* Table Read Protect 004000-07FFF 7L options */
1977 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1978 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1980 /* Table Read Protect 08000-0BFFF 7L options */
1981 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1982 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1984 /* Table Read Protect 0C000-0FFFF 7L options */
1985 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1986 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1988 /* Table Read Protect Boot 7H options */
1989 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1990 #define _EBTRB_ON_7H 0xBF /* Enabled */
1993 /* Device ID locations */
1994 #define __IDLOC0 0x200000
1995 #define __IDLOC1 0x200001
1996 #define __IDLOC2 0x200002
1997 #define __IDLOC3 0x200003
1998 #define __IDLOC4 0x200004
1999 #define __IDLOC5 0x200005
2000 #define __IDLOC6 0x200006
2001 #define __IDLOC7 0x200007