3 * pic18f8520.h - PIC18F8520 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F8520_H__
16 #define __PIC18F8520_H__
18 extern __sfr __at (0xf6b) RCSTA2;
32 extern volatile __RCSTA2bits_t __at (0xf6b) RCSTA2bits;
34 extern __sfr __at (0xf6c) TXSTA2;
48 extern volatile __TXSTA2bits_t __at (0xf6c) TXSTA2bits;
50 extern __sfr __at (0xf6d) TXREG2;
51 extern __sfr __at (0xf6e) RCREG2;
52 extern __sfr __at (0xf6f) SPBRG2;
53 extern __sfr __at (0xf70) CCP5CON;
67 extern volatile __CCP5CONbits_t __at (0xf70) CCP5CONbits;
69 extern __sfr __at (0xf71) CCPR5L;
70 extern __sfr __at (0xf72) CCPR5H;
71 extern __sfr __at (0xf73) CCP4CON;
85 extern volatile __CCP4CONbits_t __at (0xf73) CCP4CONbits;
87 extern __sfr __at (0xf74) CCPR4L;
88 extern __sfr __at (0xf75) CCPR4H;
89 extern __sfr __at (0xf76) T4CON;
103 extern volatile __T4CONbits_t __at (0xf76) T4CONbits;
105 extern __sfr __at (0xf77) PR4;
106 extern __sfr __at (0xf78) TMR4;
107 extern __sfr __at (0xf80) PORTA;
154 extern volatile __PORTAbits_t __at (0xf80) PORTAbits;
156 extern __sfr __at (0xf81) PORTB;
181 extern volatile __PORTBbits_t __at (0xf81) PORTBbits;
183 extern __sfr __at (0xf82) PORTC;
219 extern volatile __PORTCbits_t __at (0xf82) PORTCbits;
221 extern __sfr __at (0xf83) PORTD;
246 extern volatile __PORTDbits_t __at (0xf83) PORTDbits;
248 extern __sfr __at (0xf84) PORTE;
284 extern volatile __PORTEbits_t __at (0xf84) PORTEbits;
286 extern __sfr __at (0xf85) PORTF;
300 extern volatile __PORTFbits_t __at (0xf85) PORTFbits;
302 extern __sfr __at (0xf86) PORTG;
316 extern volatile __PORTGbits_t __at (0xf86) PORTGbits;
318 extern __sfr __at (0xf87) PORTH;
332 extern volatile __PORTHbits_t __at (0xf87) PORTHbits;
334 extern __sfr __at (0xf88) PORTJ;
348 extern volatile __PORTJbits_t __at (0xf88) PORTJbits;
350 extern __sfr __at (0xf89) LATA;
364 extern volatile __LATAbits_t __at (0xf89) LATAbits;
366 extern __sfr __at (0xf8a) LATB;
380 extern volatile __LATBbits_t __at (0xf8a) LATBbits;
382 extern __sfr __at (0xf8b) LATC;
396 extern volatile __LATCbits_t __at (0xf8b) LATCbits;
398 extern __sfr __at (0xf8c) LATD;
412 extern volatile __LATDbits_t __at (0xf8c) LATDbits;
414 extern __sfr __at (0xf8d) LATE;
428 extern volatile __LATEbits_t __at (0xf8d) LATEbits;
430 extern __sfr __at (0xf8e) LATF;
444 extern volatile __LATFbits_t __at (0xf8e) LATFbits;
446 extern __sfr __at (0xf8f) LATG;
460 extern volatile __LATGbits_t __at (0xf8f) LATGbits;
462 extern __sfr __at (0xf90) LATH;
476 extern volatile __LATHbits_t __at (0xf90) LATHbits;
478 extern __sfr __at (0xf91) LATJ;
492 extern volatile __LATJbits_t __at (0xf91) LATJbits;
494 extern __sfr __at (0xf92) TRISA;
508 extern volatile __TRISAbits_t __at (0xf92) TRISAbits;
510 extern __sfr __at (0xf93) TRISB;
524 extern volatile __TRISBbits_t __at (0xf93) TRISBbits;
526 extern __sfr __at (0xf94) TRISC;
540 extern volatile __TRISCbits_t __at (0xf94) TRISCbits;
542 extern __sfr __at (0xf95) TRISD;
556 extern volatile __TRISDbits_t __at (0xf95) TRISDbits;
558 extern __sfr __at (0xf96) TRISE;
572 extern volatile __TRISEbits_t __at (0xf96) TRISEbits;
574 extern __sfr __at (0xf97) TRISF;
588 extern volatile __TRISFbits_t __at (0xf97) TRISFbits;
590 extern __sfr __at (0xf98) TRISG;
604 extern volatile __TRISGbits_t __at (0xf98) TRISGbits;
606 extern __sfr __at (0xf99) TRISH;
620 extern volatile __TRISHbits_t __at (0xf99) TRISHbits;
622 extern __sfr __at (0xf9a) TRISJ;
636 extern volatile __TRISJbits_t __at (0xf9a) TRISJbits;
638 extern __sfr __at (0xf9c) MEMCON;
652 extern volatile __MEMCONbits_t __at (0xf9c) MEMCONbits;
654 extern __sfr __at (0xf9d) PIE1;
668 extern volatile __PIE1bits_t __at (0xf9d) PIE1bits;
670 extern __sfr __at (0xf9e) PIR1;
684 extern volatile __PIR1bits_t __at (0xf9e) PIR1bits;
686 extern __sfr __at (0xf9f) IPR1;
700 extern volatile __IPR1bits_t __at (0xf9f) IPR1bits;
702 extern __sfr __at (0xfa0) PIE2;
716 extern volatile __PIE2bits_t __at (0xfa0) PIE2bits;
718 extern __sfr __at (0xfa1) PIR2;
732 extern volatile __PIR2bits_t __at (0xfa1) PIR2bits;
734 extern __sfr __at (0xfa2) IPR2;
748 extern volatile __IPR2bits_t __at (0xfa2) IPR2bits;
750 extern __sfr __at (0xfa3) PIE3;
764 extern volatile __PIE3bits_t __at (0xfa3) PIE3bits;
766 extern __sfr __at (0xfa4) PIR3;
780 extern volatile __PIR3bits_t __at (0xfa4) PIR3bits;
782 extern __sfr __at (0xfa5) IPR3;
796 extern volatile __IPR3bits_t __at (0xfa5) IPR3bits;
798 extern __sfr __at (0xfa6) EECON1;
812 extern volatile __EECON1bits_t __at (0xfa6) EECON1bits;
814 extern __sfr __at (0xfa7) EECON2;
815 extern __sfr __at (0xfa8) EEDATA;
816 extern __sfr __at (0xfa9) EEADR;
817 extern __sfr __at (0xfaa) EEADRH;
818 extern __sfr __at (0xfab) RCSTA1;
832 extern volatile __RCSTA1bits_t __at (0xfab) RCSTA1bits;
834 extern __sfr __at (0xfac) TXSTA1;
848 extern volatile __TXSTA1bits_t __at (0xfac) TXSTA1bits;
850 extern __sfr __at (0xfad) TXREG1;
851 extern __sfr __at (0xfae) RCREG1;
852 extern __sfr __at (0xfaf) SPBRG1;
853 extern __sfr __at (0xfb0) PSPCON;
867 extern volatile __PSPCONbits_t __at (0xfb0) PSPCONbits;
869 extern __sfr __at (0xfb1) T3CON;
883 extern volatile __T3CONbits_t __at (0xfb1) T3CONbits;
885 extern __sfr __at (0xfb2) TMR3L;
886 extern __sfr __at (0xfb3) TMR3H;
887 extern __sfr __at (0xfb4) CMCON;
901 extern volatile __CMCONbits_t __at (0xfb4) CMCONbits;
903 extern __sfr __at (0xfb5) CVRCON;
917 extern volatile __CVRCONbits_t __at (0xfb5) CVRCONbits;
919 extern __sfr __at (0xfb7) CCP3CON;
933 extern volatile __CCP3CONbits_t __at (0xfb7) CCP3CONbits;
935 extern __sfr __at (0xfb8) CCPR3L;
936 extern __sfr __at (0xfb9) CCPR3H;
937 extern __sfr __at (0xfba) CCP2CON;
951 extern volatile __CCP2CONbits_t __at (0xfba) CCP2CONbits;
953 extern __sfr __at (0xfbb) CCPR2L;
954 extern __sfr __at (0xfbc) CCPR2H;
955 extern __sfr __at (0xfbd) CCP1CON;
969 extern volatile __CCP1CONbits_t __at (0xfbd) CCP1CONbits;
971 extern __sfr __at (0xfbe) CCPR1L;
972 extern __sfr __at (0xfbf) CCPR1H;
973 extern __sfr __at (0xfc0) ADCON2;
987 extern volatile __ADCON2bits_t __at (0xfc0) ADCON2bits;
989 extern __sfr __at (0xfc1) ADCON1;
1003 extern volatile __ADCON1bits_t __at (0xfc1) ADCON1bits;
1005 extern __sfr __at (0xfc2) ADCON0;
1019 extern volatile __ADCON0bits_t __at (0xfc2) ADCON0bits;
1021 extern __sfr __at (0xfc3) ADRESL;
1022 extern __sfr __at (0xfc4) ADRESH;
1023 extern __sfr __at (0xfc5) SSPCON2;
1037 extern volatile __SSPCON2bits_t __at (0xfc5) SSPCON2bits;
1039 extern __sfr __at (0xfc6) SSPCON1;
1053 extern volatile __SSPCON1bits_t __at (0xfc6) SSPCON1bits;
1055 extern __sfr __at (0xfc7) SSPSTAT;
1069 extern volatile __SSPSTATbits_t __at (0xfc7) SSPSTATbits;
1071 extern __sfr __at (0xfc8) SSPADD;
1072 extern __sfr __at (0xfc9) SSPBUF;
1073 extern __sfr __at (0xfca) T2CON;
1087 extern volatile __T2CONbits_t __at (0xfca) T2CONbits;
1089 extern __sfr __at (0xfcb) PR2;
1090 extern __sfr __at (0xfcc) TMR2;
1091 extern __sfr __at (0xfcd) T1CON;
1096 unsigned NOT_T1SYNC:1;
1105 extern volatile __T1CONbits_t __at (0xfcd) T1CONbits;
1107 extern __sfr __at (0xfce) TMR1L;
1108 extern __sfr __at (0xfcf) TMR1H;
1109 extern __sfr __at (0xfd0) RCON;
1123 extern volatile __RCONbits_t __at (0xfd0) RCONbits;
1125 extern __sfr __at (0xfd1) WDTCON;
1150 extern volatile __WDTCONbits_t __at (0xfd1) WDTCONbits;
1152 extern __sfr __at (0xfd2) LVDCON;
1177 extern volatile __LVDCONbits_t __at (0xfd2) LVDCONbits;
1179 extern __sfr __at (0xfd3) OSCCON;
1193 extern volatile __OSCCONbits_t __at (0xfd3) OSCCONbits;
1195 extern __sfr __at (0xfd5) T0CON;
1196 extern __sfr __at (0xfd6) TMR0L;
1197 extern __sfr __at (0xfd7) TMR0H;
1198 extern __sfr __at (0xfd8) STATUS;
1212 extern volatile __STATUSbits_t __at (0xfd8) STATUSbits;
1214 extern __sfr __at (0xfd9) FSR2L;
1215 extern __sfr __at (0xfda) FSR2H;
1216 extern __sfr __at (0xfdb) PLUSW2;
1217 extern __sfr __at (0xfdc) PREINC2;
1218 extern __sfr __at (0xfdd) POSTDEC2;
1219 extern __sfr __at (0xfde) POSTINC2;
1220 extern __sfr __at (0xfdf) INDF2;
1221 extern __sfr __at (0xfe0) BSR;
1222 extern __sfr __at (0xfe1) FSR1L;
1223 extern __sfr __at (0xfe2) FSR1H;
1224 extern __sfr __at (0xfe3) PLUSW1;
1225 extern __sfr __at (0xfe4) PREINC1;
1226 extern __sfr __at (0xfe5) POSTDEC1;
1227 extern __sfr __at (0xfe6) POSTINC1;
1228 extern __sfr __at (0xfe7) INDF1;
1229 extern __sfr __at (0xfe8) WREG;
1230 extern __sfr __at (0xfe9) FSR0L;
1231 extern __sfr __at (0xfea) FSR0H;
1232 extern __sfr __at (0xfeb) PLUSW0;
1233 extern __sfr __at (0xfec) PREINC0;
1234 extern __sfr __at (0xfed) POSTDEC0;
1235 extern __sfr __at (0xfee) POSTINC0;
1236 extern __sfr __at (0xfef) INDF0;
1237 extern __sfr __at (0xff0) INTCON3;
1262 extern volatile __INTCON3bits_t __at (0xff0) INTCON3bits;
1264 extern __sfr __at (0xff1) INTCON2;
1278 extern volatile __INTCON2bits_t __at (0xff1) INTCON2bits;
1280 extern __sfr __at (0xff2) INTCON;
1294 extern volatile __INTCONbits_t __at (0xff2) INTCONbits;
1296 extern __sfr __at (0xff3) PRODL;
1297 extern __sfr __at (0xff4) PRODH;
1298 extern __sfr __at (0xff5) TABLAT;
1299 extern __sfr __at (0xff6) TBLPTRL;
1300 extern __sfr __at (0xff7) TBLPTRH;
1301 extern __sfr __at (0xff8) TBLPTRU;
1302 extern __sfr __at (0xff9) PCL;
1303 extern __sfr __at (0xffa) PCLATH;
1304 extern __sfr __at (0xffb) PCLATU;
1305 extern __sfr __at (0xffc) STKPTR;
1319 extern volatile __STKPTRbits_t __at (0xffc) STKPTRbits;
1321 extern __sfr __at (0xffd) TOSL;
1322 extern __sfr __at (0xffe) TOSH;
1323 extern __sfr __at (0xfff) TOSU;
1326 /* Configuration registers locations */
1327 #define __CONFIG1H 0x300001
1328 #define __CONFIG2L 0x300002
1329 #define __CONFIG2H 0x300003
1330 #define __CONFIG3L 0x300004
1331 #define __CONFIG3H 0x300005
1332 #define __CONFIG5L 0x300008
1333 #define __CONFIG5H 0x300009
1334 #define __CONFIG6L 0x30000A
1335 #define __CONFIG6H 0x30000B
1336 #define __CONFIG7L 0x30000C
1337 #define __CONFIG7H 0x30000D
1341 /* Oscillator 1H options */
1342 #define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */
1343 #define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */
1344 #define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */
1345 #define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */
1346 #define _OSC_RC_1H 0xFB /* RC */
1347 #define _OSC_HS_1H 0xFA /* HS */
1348 #define _OSC_XT_1H 0xF9 /* XT */
1349 #define _OSC_LP_1H 0xF8 /* LP */
1351 /* Osc. Switch Enable 1H options */
1352 #define _OSCS_OFF_1H 0xFF /* Disabled */
1353 #define _OSCS_ON_1H 0xDF /* Enabled */
1355 /* Power Up Timer 2L options */
1356 #define _PUT_OFF_2L 0xFF /* Disabled */
1357 #define _PUT_ON_2L 0xFE /* Enabled */
1359 /* Brown Out Detect 2L options */
1360 #define _BODEN_ON_2L 0xFF /* Enabled */
1361 #define _BODEN_OFF_2L 0xFD /* Disabled */
1363 /* Brown Out Voltage 2L options */
1364 #define _BODENV_2_5V_2L 0xFF /* 2.5V */
1365 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
1366 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
1367 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
1369 /* Watchdog Timer 2H options */
1370 #define _WDT_ON_2H 0xFF /* Enabled */
1371 #define _WDT_OFF_2H 0xFE /* Disabled */
1373 /* Watchdog Postscaler 2H options */
1374 #define _WDTPS_1_128_2H 0xFF /* 1:128 */
1375 #define _WDTPS_1_64_2H 0xFD /* 1:64 */
1376 #define _WDTPS_1_32_2H 0xFB /* 1:32 */
1377 #define _WDTPS_1_16_2H 0xF9 /* 1:16 */
1378 #define _WDTPS_1_8_2H 0xF7 /* 1:8 */
1379 #define _WDTPS_1_4_2H 0xF5 /* 1:4 */
1380 #define _WDTPS_1_2_2H 0xF3 /* 1:2 */
1381 #define _WDTPS_1_1_2H 0xF1 /* 1:1 */
1383 /* Processor Mode 3L options */
1384 #define _PMODE_MICROCONTROLLER_3L 0xFF /* Microcontroller */
1385 #define _PMODE_MICROPROCESSOR__3L 0xFE /* Microprocessor */
1386 #define _PMODE_MICROPROCESSOR_w_Boot_3L 0xFD /* Microprocessor w_Boot */
1387 #define _PMODE_EXT_3L 0xFC /* Ext Microcontroller */
1389 /* External Bus Wait 3L options */
1390 #define _WAIT_OFF_3L 0xFF /* Disabled */
1391 #define _WAIT_ON_3L 0x7F /* Enabled */
1393 /* CCP2 Mux 3H options */
1394 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1395 #define _CCP2MUX_RE7_MICROCONTROLLER__RB3_3H 0xFE /* RE7(Microcontroller)/RB3 */
1397 /* Timer1 OSC 3H options */
1398 #define _T1OSCMX_LOW_3H 0xFD /* Low Power */
1400 /* Low Voltage Program 3H options */
1401 #define _LVP_ON_3H 0xFF /* Enabled */
1402 #define _LVP_OFF_3H 0xFB /* Disabled */
1404 /* Background Debug 3H options */
1405 #define _BACKBUG_OFF_3H 0xFF /* Disabled */
1406 #define _BACKBUG_ON_3H 0x7F /* Enabled */
1408 /* Stack Overflow Reset 3H options */
1409 #define _STVR_ON_3H 0xFF /* Enabled */
1410 #define _STVR_OFF_3H 0xFE /* Disabled */
1412 /* Code Protect 00800-01FFF 5L options */
1413 #define _CP_0_OFF_5L 0xFF /* Disabled */
1414 #define _CP_0_ON_5L 0xFE /* Enabled */
1416 /* Code Protect 02000-03FFF 5L options */
1417 #define _CP_1_OFF_5L 0xFF /* Disabled */
1418 #define _CP_1_ON_5L 0xFD /* Enabled */
1420 /* Code Protect 04000-05FFF 5L options */
1421 #define _CP_2_OFF_5L 0xFF /* Disabled */
1422 #define _CP_2_ON_5L 0xFB /* Enabled */
1424 /* Code Protect 06000-07FFF 5L options */
1425 #define _CP_3_OFF_5L 0xFF /* Disabled */
1426 #define _CP_3_ON_5L 0xF7 /* Enabled */
1428 /* Data EE Read Protect 5H options */
1429 #define _CPD_OFF_5H 0xFF /* Disabled */
1430 #define _CPD_ON_5H 0x7F /* Enabled */
1432 /* Code Protect Boot 5H options */
1433 #define _CPB_OFF_5H 0xFF /* Disabled */
1434 #define _CPB_ON_5H 0xBF /* Enabled */
1436 /* Table Write Protect 00800-01FFF 6L options */
1437 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1438 #define _WRT_0_ON_6L 0xFE /* Enabled */
1440 /* Table Write Protect 02000-03FFF 6L options */
1441 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1442 #define _WRT_1_ON_6L 0xFD /* Enabled */
1444 /* Table Write Protect 04000-05FFF 6L options */
1445 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1446 #define _WRT_2_ON_6L 0xFB /* Enabled */
1448 /* Table Write Protect 06000-07FFF 6L options */
1449 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1450 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1452 /* Data EE Write Protect 6H options */
1453 #define _WRTD_OFF_6H 0xFF /* Disabled */
1454 #define _WRTD_ON_6H 0x7F /* Enabled */
1456 /* Table Write Protect Boot 6H options */
1457 #define _WRTB_OFF_6H 0xFF /* Disabled */
1458 #define _WRTB_ON_6H 0xBF /* Enabled */
1460 /* Config. Write Protect 6H options */
1461 #define _WRTC_OFF_6H 0xFF /* Disabled */
1462 #define _WRTC_ON_6H 0xDF /* Enabled */
1464 /* Table Read Protect 00800-01FFF 7L options */
1465 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1466 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1468 /* Table Read Protect 02000-03FFF 7L options */
1469 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1470 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1472 /* Table Read Protect 04000-05FFF 7L options */
1473 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1474 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1476 /* Table Read Protect 06000-07FFF 7L options */
1477 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1478 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1480 /* Table Read Protect Boot 7H options */
1481 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1482 #define _EBTRB_ON_7H 0xBF /* Enabled */
1485 /* Device ID locations */
1486 #define __IDLOC0 0x200000
1487 #define __IDLOC1 0x200001
1488 #define __IDLOC2 0x200002
1489 #define __IDLOC3 0x200003
1490 #define __IDLOC4 0x200004
1491 #define __IDLOC5 0x200005
1492 #define __IDLOC6 0x200006
1493 #define __IDLOC7 0x200007
1496 /* added for USART compatibility with smaller devices */
1497 #define __MULTIPLE_USARTS 1