3 * pic18f6720.h - PIC18F6720 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F6720_H__
16 #define __PIC18F6720_H__
18 extern __sfr __at (0xf6b) RCSTA2;
32 extern volatile __RCSTA2bits_t __at (0xf6b) RCSTA2bits;
34 extern __sfr __at (0xf6c) TXSTA2;
48 extern volatile __TXSTA2bits_t __at (0xf6c) TXSTA2bits;
50 extern __sfr __at (0xf6d) TXREG2;
51 extern __sfr __at (0xf6e) RCREG2;
52 extern __sfr __at (0xf6f) SPBRG2;
53 extern __sfr __at (0xf70) CCP5CON;
67 extern volatile __CCP5CONbits_t __at (0xf70) CCP5CONbits;
69 extern __sfr __at (0xf71) CCPR5L;
70 extern __sfr __at (0xf72) CCPR5H;
71 extern __sfr __at (0xf73) CCP4CON;
85 extern volatile __CCP4CONbits_t __at (0xf73) CCP4CONbits;
87 extern __sfr __at (0xf74) CCPR4L;
88 extern __sfr __at (0xf75) CCPR4H;
89 extern __sfr __at (0xf76) T4CON;
103 extern volatile __T4CONbits_t __at (0xf76) T4CONbits;
105 extern __sfr __at (0xf77) PR4;
106 extern __sfr __at (0xf78) TMR4;
107 extern __sfr __at (0xf80) PORTA;
154 extern volatile __PORTAbits_t __at (0xf80) PORTAbits;
156 extern __sfr __at (0xf81) PORTB;
181 extern volatile __PORTBbits_t __at (0xf81) PORTBbits;
183 extern __sfr __at (0xf82) PORTC;
219 extern volatile __PORTCbits_t __at (0xf82) PORTCbits;
221 extern __sfr __at (0xf83) PORTD;
246 extern volatile __PORTDbits_t __at (0xf83) PORTDbits;
248 extern __sfr __at (0xf84) PORTE;
284 extern volatile __PORTEbits_t __at (0xf84) PORTEbits;
286 extern __sfr __at (0xf85) PORTF;
300 extern volatile __PORTFbits_t __at (0xf85) PORTFbits;
302 extern __sfr __at (0xf86) PORTG;
316 extern volatile __PORTGbits_t __at (0xf86) PORTGbits;
318 extern __sfr __at (0xf89) LATA;
332 extern volatile __LATAbits_t __at (0xf89) LATAbits;
334 extern __sfr __at (0xf8a) LATB;
348 extern volatile __LATBbits_t __at (0xf8a) LATBbits;
350 extern __sfr __at (0xf8b) LATC;
364 extern volatile __LATCbits_t __at (0xf8b) LATCbits;
366 extern __sfr __at (0xf8c) LATD;
380 extern volatile __LATDbits_t __at (0xf8c) LATDbits;
382 extern __sfr __at (0xf8d) LATE;
396 extern volatile __LATEbits_t __at (0xf8d) LATEbits;
398 extern __sfr __at (0xf8e) LATF;
412 extern volatile __LATFbits_t __at (0xf8e) LATFbits;
414 extern __sfr __at (0xf8f) LATG;
428 extern volatile __LATGbits_t __at (0xf8f) LATGbits;
430 extern __sfr __at (0xf92) TRISA;
444 extern volatile __TRISAbits_t __at (0xf92) TRISAbits;
446 extern __sfr __at (0xf93) TRISB;
460 extern volatile __TRISBbits_t __at (0xf93) TRISBbits;
462 extern __sfr __at (0xf94) TRISC;
476 extern volatile __TRISCbits_t __at (0xf94) TRISCbits;
478 extern __sfr __at (0xf95) TRISD;
492 extern volatile __TRISDbits_t __at (0xf95) TRISDbits;
494 extern __sfr __at (0xf96) TRISE;
508 extern volatile __TRISEbits_t __at (0xf96) TRISEbits;
510 extern __sfr __at (0xf97) TRISF;
524 extern volatile __TRISFbits_t __at (0xf97) TRISFbits;
526 extern __sfr __at (0xf98) TRISG;
540 extern volatile __TRISGbits_t __at (0xf98) TRISGbits;
542 extern __sfr __at (0xf9d) PIE1;
556 extern volatile __PIE1bits_t __at (0xf9d) PIE1bits;
558 extern __sfr __at (0xf9e) PIR1;
572 extern volatile __PIR1bits_t __at (0xf9e) PIR1bits;
574 extern __sfr __at (0xf9f) IPR1;
588 extern volatile __IPR1bits_t __at (0xf9f) IPR1bits;
590 extern __sfr __at (0xfa0) PIE2;
604 extern volatile __PIE2bits_t __at (0xfa0) PIE2bits;
606 extern __sfr __at (0xfa1) PIR2;
620 extern volatile __PIR2bits_t __at (0xfa1) PIR2bits;
622 extern __sfr __at (0xfa2) IPR2;
636 extern volatile __IPR2bits_t __at (0xfa2) IPR2bits;
638 extern __sfr __at (0xfa3) PIE3;
652 extern volatile __PIE3bits_t __at (0xfa3) PIE3bits;
654 extern __sfr __at (0xfa4) PIR3;
668 extern volatile __PIR3bits_t __at (0xfa4) PIR3bits;
670 extern __sfr __at (0xfa5) IPR3;
684 extern volatile __IPR3bits_t __at (0xfa5) IPR3bits;
686 extern __sfr __at (0xfa6) EECON1;
700 extern volatile __EECON1bits_t __at (0xfa6) EECON1bits;
702 extern __sfr __at (0xfa7) EECON2;
703 extern __sfr __at (0xfa8) EEDATA;
704 extern __sfr __at (0xfa9) EEADR;
705 extern __sfr __at (0xfaa) EEADRH;
706 extern __sfr __at (0xfab) RCSTA1;
720 extern volatile __RCSTA1bits_t __at (0xfab) RCSTA1bits;
722 extern __sfr __at (0xfac) TXSTA1;
736 extern volatile __TXSTA1bits_t __at (0xfac) TXSTA1bits;
738 extern __sfr __at (0xfad) TXREG1;
739 extern __sfr __at (0xfae) RCREG1;
740 extern __sfr __at (0xfaf) SPBRG1;
742 /* for compatibility reasons */
743 extern __sfr __at (0xfab) RCSTA;
744 extern volatile __RCSTA1bits_t __at (0xfab) RCSTAbits;
745 extern __sfr __at (0xfac) TXSTA;
746 extern volatile __TXSTA1bits_t __at (0xfac) TXSTAbits;
747 extern __sfr __at (0xfad) TXREG;
748 extern __sfr __at (0xfae) RCREG;
749 extern __sfr __at (0xfaf) SPBRG;
751 extern __sfr __at (0xfb0) PSPCON;
765 extern volatile __PSPCONbits_t __at (0xfb0) PSPCONbits;
767 extern __sfr __at (0xfb1) T3CON;
781 extern volatile __T3CONbits_t __at (0xfb1) T3CONbits;
783 extern __sfr __at (0xfb2) TMR3L;
784 extern __sfr __at (0xfb3) TMR3H;
785 extern __sfr __at (0xfb4) CMCON;
799 extern volatile __CMCONbits_t __at (0xfb4) CMCONbits;
801 extern __sfr __at (0xfb5) CVRCON;
815 extern volatile __CVRCONbits_t __at (0xfb5) CVRCONbits;
817 extern __sfr __at (0xfb7) CCP3CON;
831 extern volatile __CCP3CONbits_t __at (0xfb7) CCP3CONbits;
833 extern __sfr __at (0xfb8) CCPR3L;
834 extern __sfr __at (0xfb9) CCPR3H;
835 extern __sfr __at (0xfba) CCP2CON;
849 extern volatile __CCP2CONbits_t __at (0xfba) CCP2CONbits;
851 extern __sfr __at (0xfbb) CCPR2L;
852 extern __sfr __at (0xfbc) CCPR2H;
853 extern __sfr __at (0xfbd) CCP1CON;
867 extern volatile __CCP1CONbits_t __at (0xfbd) CCP1CONbits;
869 extern __sfr __at (0xfbe) CCPR1L;
870 extern __sfr __at (0xfbf) CCPR1H;
871 extern __sfr __at (0xfc0) ADCON2;
885 extern volatile __ADCON2bits_t __at (0xfc0) ADCON2bits;
887 extern __sfr __at (0xfc1) ADCON1;
901 extern volatile __ADCON1bits_t __at (0xfc1) ADCON1bits;
903 extern __sfr __at (0xfc2) ADCON0;
917 extern volatile __ADCON0bits_t __at (0xfc2) ADCON0bits;
919 extern __sfr __at (0xfc3) ADRESL;
920 extern __sfr __at (0xfc4) ADRESH;
921 extern __sfr __at (0xfc5) SSPCON2;
935 extern volatile __SSPCON2bits_t __at (0xfc5) SSPCON2bits;
937 extern __sfr __at (0xfc6) SSPCON1;
951 extern volatile __SSPCON1bits_t __at (0xfc6) SSPCON1bits;
953 extern __sfr __at (0xfc7) SSPSTAT;
967 extern volatile __SSPSTATbits_t __at (0xfc7) SSPSTATbits;
969 extern __sfr __at (0xfc8) SSPADD;
970 extern __sfr __at (0xfc9) SSPBUF;
971 extern __sfr __at (0xfca) T2CON;
985 extern volatile __T2CONbits_t __at (0xfca) T2CONbits;
987 extern __sfr __at (0xfcb) PR2;
988 extern __sfr __at (0xfcc) TMR2;
989 extern __sfr __at (0xfcd) T1CON;
994 unsigned NOT_T1SYNC:1;
1003 extern volatile __T1CONbits_t __at (0xfcd) T1CONbits;
1005 extern __sfr __at (0xfce) TMR1L;
1006 extern __sfr __at (0xfcf) TMR1H;
1007 extern __sfr __at (0xfd0) RCON;
1021 extern volatile __RCONbits_t __at (0xfd0) RCONbits;
1023 extern __sfr __at (0xfd1) WDTCON;
1048 extern volatile __WDTCONbits_t __at (0xfd1) WDTCONbits;
1050 extern __sfr __at (0xfd2) LVDCON;
1075 extern volatile __LVDCONbits_t __at (0xfd2) LVDCONbits;
1077 extern __sfr __at (0xfd3) OSCCON;
1091 extern volatile __OSCCONbits_t __at (0xfd3) OSCCONbits;
1093 extern __sfr __at (0xfd5) T0CON;
1094 extern __sfr __at (0xfd6) TMR0L;
1095 extern __sfr __at (0xfd7) TMR0H;
1096 extern __sfr __at (0xfd8) STATUS;
1110 extern volatile __STATUSbits_t __at (0xfd8) STATUSbits;
1112 extern __sfr __at (0xfd9) FSR2L;
1113 extern __sfr __at (0xfda) FSR2H;
1114 extern __sfr __at (0xfdb) PLUSW2;
1115 extern __sfr __at (0xfdc) PREINC2;
1116 extern __sfr __at (0xfdd) POSTDEC2;
1117 extern __sfr __at (0xfde) POSTINC2;
1118 extern __sfr __at (0xfdf) INDF2;
1119 extern __sfr __at (0xfe0) BSR;
1120 extern __sfr __at (0xfe1) FSR1L;
1121 extern __sfr __at (0xfe2) FSR1H;
1122 extern __sfr __at (0xfe3) PLUSW1;
1123 extern __sfr __at (0xfe4) PREINC1;
1124 extern __sfr __at (0xfe5) POSTDEC1;
1125 extern __sfr __at (0xfe6) POSTINC1;
1126 extern __sfr __at (0xfe7) INDF1;
1127 extern __sfr __at (0xfe8) WREG;
1128 extern __sfr __at (0xfe9) FSR0L;
1129 extern __sfr __at (0xfea) FSR0H;
1130 extern __sfr __at (0xfeb) PLUSW0;
1131 extern __sfr __at (0xfec) PREINC0;
1132 extern __sfr __at (0xfed) POSTDEC0;
1133 extern __sfr __at (0xfee) POSTINC0;
1134 extern __sfr __at (0xfef) INDF0;
1135 extern __sfr __at (0xff0) INTCON3;
1160 extern volatile __INTCON3bits_t __at (0xff0) INTCON3bits;
1162 extern __sfr __at (0xff1) INTCON2;
1176 extern volatile __INTCON2bits_t __at (0xff1) INTCON2bits;
1178 extern __sfr __at (0xff2) INTCON;
1192 extern volatile __INTCONbits_t __at (0xff2) INTCONbits;
1194 extern __sfr __at (0xff3) PRODL;
1195 extern __sfr __at (0xff4) PRODH;
1196 extern __sfr __at (0xff5) TABLAT;
1197 extern __sfr __at (0xff6) TBLPTRL;
1198 extern __sfr __at (0xff7) TBLPTRH;
1199 extern __sfr __at (0xff8) TBLPTRU;
1200 extern __sfr __at (0xff9) PCL;
1201 extern __sfr __at (0xffa) PCLATH;
1202 extern __sfr __at (0xffb) PCLATU;
1203 extern __sfr __at (0xffc) STKPTR;
1217 extern volatile __STKPTRbits_t __at (0xffc) STKPTRbits;
1219 extern __sfr __at (0xffd) TOSL;
1220 extern __sfr __at (0xffe) TOSH;
1221 extern __sfr __at (0xfff) TOSU;
1224 /* Configuration registers locations */
1225 #define __CONFIG1H 0x300001
1226 #define __CONFIG2L 0x300002
1227 #define __CONFIG2H 0x300003
1228 #define __CONFIG3H 0x300005
1229 #define __CONFIG4L 0x300006
1230 #define __CONFIG5L 0x300008
1231 #define __CONFIG5H 0x300009
1232 #define __CONFIG6L 0x30000A
1233 #define __CONFIG6H 0x30000B
1234 #define __CONFIG7L 0x30000C
1235 #define __CONFIG7H 0x30000D
1239 /* Oscillator 1H options */
1240 #define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */
1241 #define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */
1242 #define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */
1243 #define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */
1244 #define _OSC_RC_1H 0xFB /* RC */
1245 #define _OSC_HS_1H 0xFA /* HS */
1246 #define _OSC_XT_1H 0xF9 /* XT */
1247 #define _OSC_LP_1H 0xF8 /* LP */
1249 /* Osc. Switch Enable 1H options */
1250 #define _OSCS_OFF_1H 0xFF /* Disabled */
1251 #define _OSCS_ON_1H 0xDF /* Enabled */
1253 /* Power Up Timer 2L options */
1254 #define _PUT_OFF_2L 0xFF /* Disabled */
1255 #define _PUT_ON_2L 0xFE /* Enabled */
1257 /* Brown Out Detect 2L options */
1258 #define _BODEN_ON_2L 0xFF /* Enabled */
1259 #define _BODEN_OFF_2L 0xFD /* Disabled */
1261 /* Brown Out Voltage 2L options */
1262 #define _BODENV_2_5V_2L 0xFF /* 2.5V */
1263 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
1264 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
1265 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
1267 /* Watchdog Timer 2H options */
1268 #define _WDT_ON_2H 0xFF /* Enabled */
1269 #define _WDT_OFF_2H 0xFE /* Disabled */
1271 /* Watchdog Postscaler 2H options */
1272 #define _WDTPS_1_128_2H 0xFF /* 1:128 */
1273 #define _WDTPS_1_64_2H 0xFD /* 1:64 */
1274 #define _WDTPS_1_32_2H 0xFB /* 1:32 */
1275 #define _WDTPS_1_16_2H 0xF9 /* 1:16 */
1276 #define _WDTPS_1_8_2H 0xF7 /* 1:8 */
1277 #define _WDTPS_1_4_2H 0xF5 /* 1:4 */
1278 #define _WDTPS_1_2_2H 0xF3 /* 1:2 */
1279 #define _WDTPS_1_1_2H 0xF1 /* 1:1 */
1281 /* CCP2 Mux 3H options */
1282 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1283 #define _CCP2MUX_RE7_3H 0xFE /* RE7 */
1285 /* Low Voltage Program 4L options */
1286 #define _LVP_ON_4L 0xFF /* Enabled */
1287 #define _LVP_OFF_4L 0xFB /* Disabled */
1289 /* Background Debug 4L options */
1290 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1291 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1293 /* Stack Overflow Reset 4L options */
1294 #define _STVR_ON_4L 0xFF /* Enabled */
1295 #define _STVR_OFF_4L 0xFE /* Disabled */
1297 /* Code Protect 00200-03FFF 5L options */
1298 #define _CP_0_OFF_5L 0xFF /* Disabled */
1299 #define _CP_0_ON_5L 0xFE /* Enabled */
1301 /* Code Protect 04000-07FFF 5L options */
1302 #define _CP_1_OFF_5L 0xFF /* Disabled */
1303 #define _CP_1_ON_5L 0xFD /* Enabled */
1305 /* Code Protect 08000-0BFFF 5L options */
1306 #define _CP_2_OFF_5L 0xFF /* Disabled */
1307 #define _CP_2_ON_5L 0xFB /* Enabled */
1309 /* Code Protect 0C000-0FFFF 5L options */
1310 #define _CP_3_OFF_5L 0xFF /* Disabled */
1311 #define _CP_3_ON_5L 0xF7 /* Enabled */
1313 /* Code Protect 10000-13FFF 5L options */
1314 #define _CP_4_OFF_5L 0xFF /* Disabled */
1315 #define _CP_4_ON_5L 0xEF /* Enabled */
1317 /* Code Protect 14000-17FFF 5L options */
1318 #define _CP_5_OFF_5L 0xFF /* Disabled */
1319 #define _CP_5_ON_5L 0xDF /* Enabled */
1321 /* Code Protect 18000-1BFFF 5L options */
1322 #define _CP_6_OFF_5L 0xFF /* Disabled */
1323 #define _CP_6_ON_5L 0xBF /* Enabled */
1325 /* Code Protect 1C000-1FFFF 5L options */
1326 #define _CP_7_OFF_5L 0xFF /* Disabled */
1327 #define _CP_7_ON_5L 0x7F /* Enabled */
1329 /* Data EE Read Protect 5H options */
1330 #define _CPD_OFF_5H 0xFF /* Disabled */
1331 #define _CPD_ON_5H 0x7F /* Enabled */
1333 /* Code Protect Boot 5H options */
1334 #define _CPB_OFF_5H 0xFF /* Disabled */
1335 #define _CPB_ON_5H 0xBF /* Enabled */
1337 /* Table Write Protect 00200-03FFF 6L options */
1338 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1339 #define _WRT_0_ON_6L 0xFE /* Enabled */
1341 /* Table Write Protect 04000-07FFF 6L options */
1342 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1343 #define _WRT_1_ON_6L 0xFD /* Enabled */
1345 /* Table Write Protect 08000-0BFFF 6L options */
1346 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1347 #define _WRT_2_ON_6L 0xFB /* Enabled */
1349 /* Table Write Protect 0C000-0FFFF 6L options */
1350 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1351 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1353 /* Table Write Protect 10000-13FFF 6L options */
1354 #define _WRT_4_OFF_6L 0xFF /* Disabled */
1355 #define _WRT_4_ON_6L 0xEF /* Enabled */
1357 /* Table Write Protect 14000-17FFF 6L options */
1358 #define _WRT_5_OFF_6L 0xFF /* Disabled */
1359 #define _WRT_5_ON_6L 0xDF /* Enabled */
1361 /* Table Write Protect 18000-1BFFF 6L options */
1362 #define _WRT_6_OFF_6L 0xFF /* Disabled */
1363 #define _WRT_6_ON_6L 0xBF /* Enabled */
1365 /* Table Write Protect 1C000-1FFFF 6L options */
1366 #define _WRT_7_OFF_6L 0xFF /* Disabled */
1367 #define _WRT_7_ON_6L 0x7F /* Enabled */
1369 /* Data EE Write Protect 6H options */
1370 #define _WRTD_OFF_6H 0xFF /* Disabled */
1371 #define _WRTD_ON_6H 0x7F /* Enabled */
1373 /* Table Write Protect Boot 6H options */
1374 #define _WRTB_OFF_6H 0xFF /* Disabled */
1375 #define _WRTB_ON_6H 0xBF /* Enabled */
1377 /* Config. Write Protect 6H options */
1378 #define _WRTC_OFF_6H 0xFF /* Disabled */
1379 #define _WRTC_ON_6H 0xDF /* Enabled */
1381 /* Table Read Protect 00200-03FFF 7L options */
1382 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1383 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1385 /* Table Read Protect 04000-07FFF 7L options */
1386 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1387 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1389 /* Table Read Protect 08000-0BFFF 7L options */
1390 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1391 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1393 /* Table Read Protect 0C000-0FFFF 7L options */
1394 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1395 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1397 /* Table Read Protect 10000-13FFF 7L options */
1398 #define _EBTR_4_OFF_7L 0xFF /* Disabled */
1399 #define _EBTR_4_ON_7L 0xEF /* Enabled */
1401 /* Table Read Protect 14000-17FFF 7L options */
1402 #define _EBTR_5_OFF_7L 0xFF /* Disabled */
1403 #define _EBTR_5_ON_7L 0xDF /* Enabled */
1405 /* Table Read Protect 18000-1BFFF 7L options */
1406 #define _EBTR_6_OFF_7L 0xFF /* Disabled */
1407 #define _EBTR_6_ON_7L 0xBF /* Enabled */
1409 /* Table Read Protect 1C000-1FFFF 7L options */
1410 #define _EBTR_7_OFF_7L 0xFF /* Disabled */
1411 #define _EBTR_7_ON_7L 0x7F /* Enabled */
1413 /* Table Read Protect Boot 7H options */
1414 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1415 #define _EBTRB_ON_7H 0xBF /* Enabled */
1418 /* Device ID locations */
1419 #define __IDLOC0 0x200000
1420 #define __IDLOC1 0x200001
1421 #define __IDLOC2 0x200002
1422 #define __IDLOC3 0x200003
1423 #define __IDLOC4 0x200004
1424 #define __IDLOC5 0x200005
1425 #define __IDLOC6 0x200006
1426 #define __IDLOC7 0x200007