3 * pic18f6620.h - PIC18F6620 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F6620_H__
16 #define __PIC18F6620_H__
18 extern sfr at 0xf6b RCSTA2;
32 extern volatile __RCSTA2bits_t at 0xf6b RCSTA2bits;
34 extern sfr at 0xf6c TXSTA2;
48 extern volatile __TXSTA2bits_t at 0xf6c TXSTA2bits;
50 extern sfr at 0xf6d TXREG2;
51 extern sfr at 0xf6e RCREG2;
52 extern sfr at 0xf6f SPBRG2;
53 extern sfr at 0xf70 CCP5CON;
67 extern volatile __CCP5CONbits_t at 0xf70 CCP5CONbits;
69 extern sfr at 0xf71 CCPR5L;
70 extern sfr at 0xf72 CCPR5H;
71 extern sfr at 0xf73 CCP4CON;
85 extern volatile __CCP4CONbits_t at 0xf73 CCP4CONbits;
87 extern sfr at 0xf74 CCPR4L;
88 extern sfr at 0xf75 CCPR4H;
89 extern sfr at 0xf76 T4CON;
103 extern volatile __T4CONbits_t at 0xf76 T4CONbits;
105 extern sfr at 0xf77 PR4;
106 extern sfr at 0xf78 TMR4;
107 extern sfr at 0xf80 PORTA;
154 extern volatile __PORTAbits_t at 0xf80 PORTAbits;
156 extern sfr at 0xf81 PORTB;
181 extern volatile __PORTBbits_t at 0xf81 PORTBbits;
183 extern sfr at 0xf82 PORTC;
219 extern volatile __PORTCbits_t at 0xf82 PORTCbits;
221 extern sfr at 0xf83 PORTD;
246 extern volatile __PORTDbits_t at 0xf83 PORTDbits;
248 extern sfr at 0xf84 PORTE;
284 extern volatile __PORTEbits_t at 0xf84 PORTEbits;
286 extern sfr at 0xf85 PORTF;
300 extern volatile __PORTFbits_t at 0xf85 PORTFbits;
302 extern sfr at 0xf86 PORTG;
316 extern volatile __PORTGbits_t at 0xf86 PORTGbits;
318 extern sfr at 0xf89 LATA;
332 extern volatile __LATAbits_t at 0xf89 LATAbits;
334 extern sfr at 0xf8a LATB;
348 extern volatile __LATBbits_t at 0xf8a LATBbits;
350 extern sfr at 0xf8b LATC;
364 extern volatile __LATCbits_t at 0xf8b LATCbits;
366 extern sfr at 0xf8c LATD;
380 extern volatile __LATDbits_t at 0xf8c LATDbits;
382 extern sfr at 0xf8d LATE;
396 extern volatile __LATEbits_t at 0xf8d LATEbits;
398 extern sfr at 0xf8e LATF;
412 extern volatile __LATFbits_t at 0xf8e LATFbits;
414 extern sfr at 0xf8f LATG;
428 extern volatile __LATGbits_t at 0xf8f LATGbits;
430 extern sfr at 0xf92 TRISA;
444 extern volatile __TRISAbits_t at 0xf92 TRISAbits;
446 extern sfr at 0xf93 TRISB;
460 extern volatile __TRISBbits_t at 0xf93 TRISBbits;
462 extern sfr at 0xf94 TRISC;
476 extern volatile __TRISCbits_t at 0xf94 TRISCbits;
478 extern sfr at 0xf95 TRISD;
492 extern volatile __TRISDbits_t at 0xf95 TRISDbits;
494 extern sfr at 0xf96 TRISE;
508 extern volatile __TRISEbits_t at 0xf96 TRISEbits;
510 extern sfr at 0xf97 TRISF;
524 extern volatile __TRISFbits_t at 0xf97 TRISFbits;
526 extern sfr at 0xf98 TRISG;
540 extern volatile __TRISGbits_t at 0xf98 TRISGbits;
542 extern sfr at 0xf9d PIE1;
556 extern volatile __PIE1bits_t at 0xf9d PIE1bits;
558 extern sfr at 0xf9e PIR1;
572 extern volatile __PIR1bits_t at 0xf9e PIR1bits;
574 extern sfr at 0xf9f IPR1;
588 extern volatile __IPR1bits_t at 0xf9f IPR1bits;
590 extern sfr at 0xfa0 PIE2;
604 extern volatile __PIE2bits_t at 0xfa0 PIE2bits;
606 extern sfr at 0xfa1 PIR2;
620 extern volatile __PIR2bits_t at 0xfa1 PIR2bits;
622 extern sfr at 0xfa2 IPR2;
636 extern volatile __IPR2bits_t at 0xfa2 IPR2bits;
638 extern sfr at 0xfa3 PIE3;
652 extern volatile __PIE3bits_t at 0xfa3 PIE3bits;
654 extern sfr at 0xfa4 PIR3;
668 extern volatile __PIR3bits_t at 0xfa4 PIR3bits;
670 extern sfr at 0xfa5 IPR3;
684 extern volatile __IPR3bits_t at 0xfa5 IPR3bits;
686 extern sfr at 0xfa6 EECON1;
700 extern volatile __EECON1bits_t at 0xfa6 EECON1bits;
702 extern sfr at 0xfa7 EECON2;
703 extern sfr at 0xfa8 EEDATA;
704 extern sfr at 0xfa9 EEADR;
705 extern sfr at 0xfaa EEADRH;
706 extern sfr at 0xfab RCSTA1;
720 extern volatile __RCSTA1bits_t at 0xfab RCSTA1bits;
722 extern sfr at 0xfac TXSTA1;
736 extern volatile __TXSTA1bits_t at 0xfac TXSTA1bits;
738 extern sfr at 0xfad TXREG1;
739 extern sfr at 0xfae RCREG1;
740 extern sfr at 0xfaf SPBRG1;
741 extern sfr at 0xfb0 PSPCON;
755 extern volatile __PSPCONbits_t at 0xfb0 PSPCONbits;
757 extern sfr at 0xfb1 T3CON;
771 extern volatile __T3CONbits_t at 0xfb1 T3CONbits;
773 extern sfr at 0xfb2 TMR3L;
774 extern sfr at 0xfb3 TMR3H;
775 extern sfr at 0xfb4 CMCON;
789 extern volatile __CMCONbits_t at 0xfb4 CMCONbits;
791 extern sfr at 0xfb5 CVRCON;
805 extern volatile __CVRCONbits_t at 0xfb5 CVRCONbits;
807 extern sfr at 0xfb7 CCP3CON;
821 extern volatile __CCP3CONbits_t at 0xfb7 CCP3CONbits;
823 extern sfr at 0xfb8 CCPR3L;
824 extern sfr at 0xfb9 CCPR3H;
825 extern sfr at 0xfba CCP2CON;
839 extern volatile __CCP2CONbits_t at 0xfba CCP2CONbits;
841 extern sfr at 0xfbb CCPR2L;
842 extern sfr at 0xfbc CCPR2H;
843 extern sfr at 0xfbd CCP1CON;
857 extern volatile __CCP1CONbits_t at 0xfbd CCP1CONbits;
859 extern sfr at 0xfbe CCPR1L;
860 extern sfr at 0xfbf CCPR1H;
861 extern sfr at 0xfc0 ADCON2;
875 extern volatile __ADCON2bits_t at 0xfc0 ADCON2bits;
877 extern sfr at 0xfc1 ADCON1;
891 extern volatile __ADCON1bits_t at 0xfc1 ADCON1bits;
893 extern sfr at 0xfc2 ADCON0;
907 extern volatile __ADCON0bits_t at 0xfc2 ADCON0bits;
909 extern sfr at 0xfc3 ADRESL;
910 extern sfr at 0xfc4 ADRESH;
911 extern sfr at 0xfc5 SSPCON2;
925 extern volatile __SSPCON2bits_t at 0xfc5 SSPCON2bits;
927 extern sfr at 0xfc6 SSPCON1;
941 extern volatile __SSPCON1bits_t at 0xfc6 SSPCON1bits;
943 extern sfr at 0xfc7 SSPSTAT;
957 extern volatile __SSPSTATbits_t at 0xfc7 SSPSTATbits;
959 extern sfr at 0xfc8 SSPADD;
960 extern sfr at 0xfc9 SSPBUF;
961 extern sfr at 0xfca T2CON;
975 extern volatile __T2CONbits_t at 0xfca T2CONbits;
977 extern sfr at 0xfcb PR2;
978 extern sfr at 0xfcc TMR2;
979 extern sfr at 0xfcd T1CON;
984 unsigned NOT_T1SYNC:1;
993 extern volatile __T1CONbits_t at 0xfcd T1CONbits;
995 extern sfr at 0xfce TMR1L;
996 extern sfr at 0xfcf TMR1H;
997 extern sfr at 0xfd0 RCON;
1011 extern volatile __RCONbits_t at 0xfd0 RCONbits;
1013 extern sfr at 0xfd1 WDTCON;
1038 extern volatile __WDTCONbits_t at 0xfd1 WDTCONbits;
1040 extern sfr at 0xfd2 LVDCON;
1065 extern volatile __LVDCONbits_t at 0xfd2 LVDCONbits;
1067 extern sfr at 0xfd3 OSCCON;
1081 extern volatile __OSCCONbits_t at 0xfd3 OSCCONbits;
1083 extern sfr at 0xfd5 T0CON;
1084 extern sfr at 0xfd6 TMR0L;
1085 extern sfr at 0xfd7 TMR0H;
1086 extern sfr at 0xfd8 STATUS;
1100 extern volatile __STATUSbits_t at 0xfd8 STATUSbits;
1102 extern sfr at 0xfd9 FSR2L;
1103 extern sfr at 0xfda FSR2H;
1104 extern sfr at 0xfdb PLUSW2;
1105 extern sfr at 0xfdc PREINC2;
1106 extern sfr at 0xfdd POSTDEC2;
1107 extern sfr at 0xfde POSTINC2;
1108 extern sfr at 0xfdf INDF2;
1109 extern sfr at 0xfe0 BSR;
1110 extern sfr at 0xfe1 FSR1L;
1111 extern sfr at 0xfe2 FSR1H;
1112 extern sfr at 0xfe3 PLUSW1;
1113 extern sfr at 0xfe4 PREINC1;
1114 extern sfr at 0xfe5 POSTDEC1;
1115 extern sfr at 0xfe6 POSTINC1;
1116 extern sfr at 0xfe7 INDF1;
1117 extern sfr at 0xfe8 WREG;
1118 extern sfr at 0xfe9 FSR0L;
1119 extern sfr at 0xfea FSR0H;
1120 extern sfr at 0xfeb PLUSW0;
1121 extern sfr at 0xfec PREINC0;
1122 extern sfr at 0xfed POSTDEC0;
1123 extern sfr at 0xfee POSTINC0;
1124 extern sfr at 0xfef INDF0;
1125 extern sfr at 0xff0 INTCON3;
1150 extern volatile __INTCON3bits_t at 0xff0 INTCON3bits;
1152 extern sfr at 0xff1 INTCON2;
1166 extern volatile __INTCON2bits_t at 0xff1 INTCON2bits;
1168 extern sfr at 0xff2 INTCON;
1182 extern volatile __INTCONbits_t at 0xff2 INTCONbits;
1184 extern sfr at 0xff3 PRODL;
1185 extern sfr at 0xff4 PRODH;
1186 extern sfr at 0xff5 TABLAT;
1187 extern sfr at 0xff6 TBLPTRL;
1188 extern sfr at 0xff7 TBLPTRH;
1189 extern sfr at 0xff8 TBLPTRU;
1190 extern sfr at 0xff9 PCL;
1191 extern sfr at 0xffa PCLATH;
1192 extern sfr at 0xffb PCLATU;
1193 extern sfr at 0xffc STKPTR;
1207 extern volatile __STKPTRbits_t at 0xffc STKPTRbits;
1209 extern sfr at 0xffd TOSL;
1210 extern sfr at 0xffe TOSH;
1211 extern sfr at 0xfff TOSU;
1214 /* Configuration registers locations */
1215 #define __CONFIG0H 0x300001
1216 #define __CONFIG1L 0x300002
1217 #define __CONFIG1H 0x300003
1218 #define __CONFIG2H 0x300005
1219 #define __CONFIG3L 0x300006
1220 #define __CONFIG4L 0x300008
1221 #define __CONFIG4H 0x300009
1222 #define __CONFIG5L 0x30000A
1223 #define __CONFIG5H 0x30000B
1224 #define __CONFIG6L 0x30000C
1225 #define __CONFIG6H 0x30000D
1229 /* Oscillator 0H options */
1230 #define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */
1231 #define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */
1232 #define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */
1233 #define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */
1234 #define _OSC_RC_0H 0xFB /* RC */
1235 #define _OSC_HS_0H 0xFA /* HS */
1236 #define _OSC_XT_0H 0xF9 /* XT */
1237 #define _OSC_LP_0H 0xF8 /* LP */
1239 /* Osc. Switch Enable 0H options */
1240 #define _OSCS_OFF_0H 0xFF /* Disabled */
1241 #define _OSCS_ON_0H 0xDF /* Enabled */
1243 /* Power Up Timer 1L options */
1244 #define _PUT_OFF_1L 0xFF /* Disabled */
1245 #define _PUT_ON_1L 0xFE /* Enabled */
1247 /* Brown Out Detect 1L options */
1248 #define _BODEN_ON_1L 0xFF /* Enabled */
1249 #define _BODEN_OFF_1L 0xFD /* Disabled */
1251 /* Brown Out Voltage 1L options */
1252 #define _BODENV_2_5V_1L 0xFF /* 2.5V */
1253 #define _BODENV_2_7V_1L 0xFB /* 2.7V */
1254 #define _BODENV_4_2V_1L 0xF7 /* 4.2V */
1255 #define _BODENV_4_5V_1L 0xF3 /* 4.5V */
1257 /* Watchdog Timer 1H options */
1258 #define _WDT_ON_1H 0xFF /* Enabled */
1259 #define _WDT_OFF_1H 0xFE /* Disabled */
1261 /* Watchdog Postscaler 1H options */
1262 #define _WDTPS_1_128_1H 0xFF /* 1:128 */
1263 #define _WDTPS_1_64_1H 0xFD /* 1:64 */
1264 #define _WDTPS_1_32_1H 0xFB /* 1:32 */
1265 #define _WDTPS_1_16_1H 0xF9 /* 1:16 */
1266 #define _WDTPS_1_8_1H 0xF7 /* 1:8 */
1267 #define _WDTPS_1_4_1H 0xF5 /* 1:4 */
1268 #define _WDTPS_1_2_1H 0xF3 /* 1:2 */
1269 #define _WDTPS_1_1_1H 0xF1 /* 1:1 */
1271 /* CCP2 Mux 2H options */
1272 #define _CCP2MUX_RC1_2H 0xFF /* RC1 */
1273 #define _CCP2MUX_RE7_2H 0xFE /* RE7 */
1275 /* Low Voltage Program 3L options */
1276 #define _LVP_ON_3L 0xFF /* Enabled */
1277 #define _LVP_OFF_3L 0xFB /* Disabled */
1279 /* Background Debug 3L options */
1280 #define _BACKBUG_OFF_3L 0xFF /* Disabled */
1281 #define _BACKBUG_ON_3L 0x7F /* Enabled */
1283 /* Stack Overflow Reset 3L options */
1284 #define _STVR_ON_3L 0xFF /* Enabled */
1285 #define _STVR_OFF_3L 0xFE /* Disabled */
1287 /* Code Protect 00200-03FFF 4L options */
1288 #define _CP_0_OFF_4L 0xFF /* Disabled */
1289 #define _CP_0_ON_4L 0xFE /* Enabled */
1291 /* Code Protect 04000-07FFF 4L options */
1292 #define _CP_1_OFF_4L 0xFF /* Disabled */
1293 #define _CP_1_ON_4L 0xFD /* Enabled */
1295 /* Code Protect 08000-0BFFF 4L options */
1296 #define _CP_2_OFF_4L 0xFF /* Disabled */
1297 #define _CP_2_ON_4L 0xFB /* Enabled */
1299 /* Code Protect 0C000-0FFFF 4L options */
1300 #define _CP_3_OFF_4L 0xFF /* Disabled */
1301 #define _CP_3_ON_4L 0xF7 /* Enabled */
1303 /* Data EE Read Protect 4H options */
1304 #define _CPD_OFF_4H 0xFF /* Disabled */
1305 #define _CPD_ON_4H 0x7F /* Enabled */
1307 /* Code Protect Boot 4H options */
1308 #define _CPB_OFF_4H 0xFF /* Disabled */
1309 #define _CPB_ON_4H 0xBF /* Enabled */
1311 /* Table Write Protect 00200-03FFF 5L options */
1312 #define _WRT_0_OFF_5L 0xFF /* Disabled */
1313 #define _WRT_0_ON_5L 0xFE /* Enabled */
1315 /* Table Write Protect 04000-07FFF 5L options */
1316 #define _WRT_1_OFF_5L 0xFF /* Disabled */
1317 #define _WRT_1_ON_5L 0xFD /* Enabled */
1319 /* Table Write Protect 08000-0BFFF 5L options */
1320 #define _WRT_2_OFF_5L 0xFF /* Disabled */
1321 #define _WRT_2_ON_5L 0xFB /* Enabled */
1323 /* Table Write Protect 0C000-0FFFF 5L options */
1324 #define _WRT_3_OFF_5L 0xFF /* Disabled */
1325 #define _WRT_3_ON_5L 0xF7 /* Enabled */
1327 /* Data EE Write Protect 5H options */
1328 #define _WRTD_OFF_5H 0xFF /* Disabled */
1329 #define _WRTD_ON_5H 0x7F /* Enabled */
1331 /* Table Write Protect Boot 5H options */
1332 #define _WRTB_OFF_5H 0xFF /* Disabled */
1333 #define _WRTB_ON_5H 0xBF /* Enabled */
1335 /* Config. Write Protect 5H options */
1336 #define _WRTC_OFF_5H 0xFF /* Disabled */
1337 #define _WRTC_ON_5H 0xDF /* Enabled */
1339 /* Table Read Protect 00200-03FFF 6L options */
1340 #define _EBTR_0_OFF_6L 0xFF /* Disabled */
1341 #define _EBTR_0_ON_6L 0xFE /* Enabled */
1343 /* Table Read Protect 04000-07FFF 6L options */
1344 #define _EBTR_1_OFF_6L 0xFF /* Disabled */
1345 #define _EBTR_1_ON_6L 0xFD /* Enabled */
1347 /* Table Read Protect 08000-0BFFF 6L options */
1348 #define _EBTR_2_OFF_6L 0xFF /* Disabled */
1349 #define _EBTR_2_ON_6L 0xFB /* Enabled */
1351 /* Table Read Protect 0C000-0FFFF 6L options */
1352 #define _EBTR_3_OFF_6L 0xFF /* Disabled */
1353 #define _EBTR_3_ON_6L 0xF7 /* Enabled */
1355 /* Table Read Protect Boot 6H options */
1356 #define _EBTRB_OFF_6H 0xFF /* Disabled */
1357 #define _EBTRB_ON_6H 0xBF /* Enabled */
1360 /* Device ID locations */
1361 #define __IDLOC0 0x200000
1362 #define __IDLOC1 0x200001
1363 #define __IDLOC2 0x200002
1364 #define __IDLOC3 0x200003
1365 #define __IDLOC4 0x200004
1366 #define __IDLOC5 0x200005
1367 #define __IDLOC6 0x200006
1368 #define __IDLOC7 0x200007