3 * pic18f6520.h - PIC18F6520 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F6520_H__
16 #define __PIC18F6520_H__
18 extern sfr at 0xf6b RCSTA2;
32 extern volatile __RCSTA2bits_t at 0xf6b RCSTA2bits;
34 extern sfr at 0xf6c TXSTA2;
48 extern volatile __TXSTA2bits_t at 0xf6c TXSTA2bits;
50 extern sfr at 0xf6d TXREG2;
51 extern sfr at 0xf6e RCREG2;
52 extern sfr at 0xf6f SPBRG2;
53 extern sfr at 0xf70 CCP5CON;
67 extern volatile __CCP5CONbits_t at 0xf70 CCP5CONbits;
69 extern sfr at 0xf71 CCPR5L;
70 extern sfr at 0xf72 CCPR5H;
71 extern sfr at 0xf73 CCP4CON;
85 extern volatile __CCP4CONbits_t at 0xf73 CCP4CONbits;
87 extern sfr at 0xf74 CCPR4L;
88 extern sfr at 0xf75 CCPR4H;
89 extern sfr at 0xf76 T4CON;
103 extern volatile __T4CONbits_t at 0xf76 T4CONbits;
105 extern sfr at 0xf77 PR4;
106 extern sfr at 0xf78 TMR4;
107 extern sfr at 0xf80 PORTA;
154 extern volatile __PORTAbits_t at 0xf80 PORTAbits;
156 extern sfr at 0xf81 PORTB;
181 extern volatile __PORTBbits_t at 0xf81 PORTBbits;
183 extern sfr at 0xf82 PORTC;
219 extern volatile __PORTCbits_t at 0xf82 PORTCbits;
221 extern sfr at 0xf83 PORTD;
246 extern volatile __PORTDbits_t at 0xf83 PORTDbits;
248 extern sfr at 0xf84 PORTE;
284 extern volatile __PORTEbits_t at 0xf84 PORTEbits;
286 extern sfr at 0xf85 PORTF;
300 extern volatile __PORTFbits_t at 0xf85 PORTFbits;
302 extern sfr at 0xf86 PORTG;
316 extern volatile __PORTGbits_t at 0xf86 PORTGbits;
318 extern sfr at 0xf89 LATA;
332 extern volatile __LATAbits_t at 0xf89 LATAbits;
334 extern sfr at 0xf8a LATB;
348 extern volatile __LATBbits_t at 0xf8a LATBbits;
350 extern sfr at 0xf8b LATC;
364 extern volatile __LATCbits_t at 0xf8b LATCbits;
366 extern sfr at 0xf8c LATD;
380 extern volatile __LATDbits_t at 0xf8c LATDbits;
382 extern sfr at 0xf8d LATE;
396 extern volatile __LATEbits_t at 0xf8d LATEbits;
398 extern sfr at 0xf8e LATF;
412 extern volatile __LATFbits_t at 0xf8e LATFbits;
414 extern sfr at 0xf8f LATG;
428 extern volatile __LATGbits_t at 0xf8f LATGbits;
430 extern sfr at 0xf92 TRISA;
444 extern volatile __TRISAbits_t at 0xf92 TRISAbits;
446 extern sfr at 0xf93 TRISB;
460 extern volatile __TRISBbits_t at 0xf93 TRISBbits;
462 extern sfr at 0xf94 TRISC;
476 extern volatile __TRISCbits_t at 0xf94 TRISCbits;
478 extern sfr at 0xf95 TRISD;
492 extern volatile __TRISDbits_t at 0xf95 TRISDbits;
494 extern sfr at 0xf96 TRISE;
508 extern volatile __TRISEbits_t at 0xf96 TRISEbits;
510 extern sfr at 0xf97 TRISF;
524 extern volatile __TRISFbits_t at 0xf97 TRISFbits;
526 extern sfr at 0xf98 TRISG;
540 extern volatile __TRISGbits_t at 0xf98 TRISGbits;
542 extern sfr at 0xf9c MEMCON;
556 extern volatile __MEMCONbits_t at 0xf9c MEMCONbits;
558 extern sfr at 0xf9d PIE1;
572 extern volatile __PIE1bits_t at 0xf9d PIE1bits;
574 extern sfr at 0xf9e PIR1;
588 extern volatile __PIR1bits_t at 0xf9e PIR1bits;
590 extern sfr at 0xf9f IPR1;
604 extern volatile __IPR1bits_t at 0xf9f IPR1bits;
606 extern sfr at 0xfa0 PIE2;
620 extern volatile __PIE2bits_t at 0xfa0 PIE2bits;
622 extern sfr at 0xfa1 PIR2;
636 extern volatile __PIR2bits_t at 0xfa1 PIR2bits;
638 extern sfr at 0xfa2 IPR2;
652 extern volatile __IPR2bits_t at 0xfa2 IPR2bits;
654 extern sfr at 0xfa3 PIE3;
668 extern volatile __PIE3bits_t at 0xfa3 PIE3bits;
670 extern sfr at 0xfa4 PIR3;
684 extern volatile __PIR3bits_t at 0xfa4 PIR3bits;
686 extern sfr at 0xfa5 IPR3;
700 extern volatile __IPR3bits_t at 0xfa5 IPR3bits;
702 extern sfr at 0xfa6 EECON1;
716 extern volatile __EECON1bits_t at 0xfa6 EECON1bits;
718 extern sfr at 0xfa7 EECON2;
719 extern sfr at 0xfa8 EEDATA;
720 extern sfr at 0xfa9 EEADR;
721 extern sfr at 0xfaa EEADRH;
722 extern sfr at 0xfab RCSTA1;
736 extern volatile __RCSTA1bits_t at 0xfab RCSTA1bits;
738 extern sfr at 0xfac TXSTA1;
752 extern volatile __TXSTA1bits_t at 0xfac TXSTA1bits;
754 extern sfr at 0xfad TXREG1;
755 extern sfr at 0xfae RCREG1;
756 extern sfr at 0xfaf SPBRG1;
757 extern sfr at 0xfb0 PSPCON;
771 extern volatile __PSPCONbits_t at 0xfb0 PSPCONbits;
773 extern sfr at 0xfb1 T3CON;
787 extern volatile __T3CONbits_t at 0xfb1 T3CONbits;
789 extern sfr at 0xfb2 TMR3L;
790 extern sfr at 0xfb3 TMR3H;
791 extern sfr at 0xfb4 CMCON;
805 extern volatile __CMCONbits_t at 0xfb4 CMCONbits;
807 extern sfr at 0xfb5 CVRCON;
821 extern volatile __CVRCONbits_t at 0xfb5 CVRCONbits;
823 extern sfr at 0xfb7 CCP3CON;
837 extern volatile __CCP3CONbits_t at 0xfb7 CCP3CONbits;
839 extern sfr at 0xfb8 CCPR3L;
840 extern sfr at 0xfb9 CCPR3H;
841 extern sfr at 0xfba CCP2CON;
855 extern volatile __CCP2CONbits_t at 0xfba CCP2CONbits;
857 extern sfr at 0xfbb CCPR2L;
858 extern sfr at 0xfbc CCPR2H;
859 extern sfr at 0xfbd CCP1CON;
873 extern volatile __CCP1CONbits_t at 0xfbd CCP1CONbits;
875 extern sfr at 0xfbe CCPR1L;
876 extern sfr at 0xfbf CCPR1H;
877 extern sfr at 0xfc0 ADCON2;
891 extern volatile __ADCON2bits_t at 0xfc0 ADCON2bits;
893 extern sfr at 0xfc1 ADCON1;
907 extern volatile __ADCON1bits_t at 0xfc1 ADCON1bits;
909 extern sfr at 0xfc2 ADCON0;
923 extern volatile __ADCON0bits_t at 0xfc2 ADCON0bits;
925 extern sfr at 0xfc3 ADRESL;
926 extern sfr at 0xfc4 ADRESH;
927 extern sfr at 0xfc5 SSPCON2;
941 extern volatile __SSPCON2bits_t at 0xfc5 SSPCON2bits;
943 extern sfr at 0xfc6 SSPCON1;
957 extern volatile __SSPCON1bits_t at 0xfc6 SSPCON1bits;
959 extern sfr at 0xfc7 SSPSTAT;
973 extern volatile __SSPSTATbits_t at 0xfc7 SSPSTATbits;
975 extern sfr at 0xfc8 SSPADD;
976 extern sfr at 0xfc9 SSPBUF;
977 extern sfr at 0xfca T2CON;
991 extern volatile __T2CONbits_t at 0xfca T2CONbits;
993 extern sfr at 0xfcb PR2;
994 extern sfr at 0xfcc TMR2;
995 extern sfr at 0xfcd T1CON;
1000 unsigned NOT_T1SYNC:1;
1009 extern volatile __T1CONbits_t at 0xfcd T1CONbits;
1011 extern sfr at 0xfce TMR1L;
1012 extern sfr at 0xfcf TMR1H;
1013 extern sfr at 0xfd0 RCON;
1027 extern volatile __RCONbits_t at 0xfd0 RCONbits;
1029 extern sfr at 0xfd1 WDTCON;
1054 extern volatile __WDTCONbits_t at 0xfd1 WDTCONbits;
1056 extern sfr at 0xfd2 LVDCON;
1081 extern volatile __LVDCONbits_t at 0xfd2 LVDCONbits;
1083 extern sfr at 0xfd3 OSCCON;
1097 extern volatile __OSCCONbits_t at 0xfd3 OSCCONbits;
1099 extern sfr at 0xfd5 T0CON;
1100 extern sfr at 0xfd6 TMR0L;
1101 extern sfr at 0xfd7 TMR0H;
1102 extern sfr at 0xfd8 STATUS;
1116 extern volatile __STATUSbits_t at 0xfd8 STATUSbits;
1118 extern sfr at 0xfd9 FSR2L;
1119 extern sfr at 0xfda FSR2H;
1120 extern sfr at 0xfdb PLUSW2;
1121 extern sfr at 0xfdc PREINC2;
1122 extern sfr at 0xfdd POSTDEC2;
1123 extern sfr at 0xfde POSTINC2;
1124 extern sfr at 0xfdf INDF2;
1125 extern sfr at 0xfe0 BSR;
1126 extern sfr at 0xfe1 FSR1L;
1127 extern sfr at 0xfe2 FSR1H;
1128 extern sfr at 0xfe3 PLUSW1;
1129 extern sfr at 0xfe4 PREINC1;
1130 extern sfr at 0xfe5 POSTDEC1;
1131 extern sfr at 0xfe6 POSTINC1;
1132 extern sfr at 0xfe7 INDF1;
1133 extern sfr at 0xfe8 WREG;
1134 extern sfr at 0xfe9 FSR0L;
1135 extern sfr at 0xfea FSR0H;
1136 extern sfr at 0xfeb PLUSW0;
1137 extern sfr at 0xfec PREINC0;
1138 extern sfr at 0xfed POSTDEC0;
1139 extern sfr at 0xfee POSTINC0;
1140 extern sfr at 0xfef INDF0;
1141 extern sfr at 0xff0 INTCON3;
1166 extern volatile __INTCON3bits_t at 0xff0 INTCON3bits;
1168 extern sfr at 0xff1 INTCON2;
1182 extern volatile __INTCON2bits_t at 0xff1 INTCON2bits;
1184 extern sfr at 0xff2 INTCON;
1198 extern volatile __INTCONbits_t at 0xff2 INTCONbits;
1200 extern sfr at 0xff3 PRODL;
1201 extern sfr at 0xff4 PRODH;
1202 extern sfr at 0xff5 TABLAT;
1203 extern sfr at 0xff6 TBLPTRL;
1204 extern sfr at 0xff7 TBLPTRH;
1205 extern sfr at 0xff8 TBLPTRU;
1206 extern sfr at 0xff9 PCL;
1207 extern sfr at 0xffa PCLATH;
1208 extern sfr at 0xffb PCLATU;
1209 extern sfr at 0xffc STKPTR;
1223 extern volatile __STKPTRbits_t at 0xffc STKPTRbits;
1225 extern sfr at 0xffd TOSL;
1226 extern sfr at 0xffe TOSH;
1227 extern sfr at 0xfff TOSU;
1230 /* Configuration registers locations */
1231 #define __CONFIG1H 0x300001
1232 #define __CONFIG2L 0x300002
1233 #define __CONFIG2H 0x300003
1234 #define __CONFIG3L 0x300004
1235 #define __CONFIG3H 0x300005
1236 #define __CONFIG5L 0x300008
1237 #define __CONFIG5H 0x300009
1238 #define __CONFIG6L 0x30000A
1239 #define __CONFIG6H 0x30000B
1240 #define __CONFIG7L 0x30000C
1241 #define __CONFIG7H 0x30000D
1245 /* Oscillator 1H options */
1246 #define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */
1247 #define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */
1248 #define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */
1249 #define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */
1250 #define _OSC_RC_1H 0xFB /* RC */
1251 #define _OSC_HS_1H 0xFA /* HS */
1252 #define _OSC_XT_1H 0xF9 /* XT */
1253 #define _OSC_LP_1H 0xF8 /* LP */
1255 /* Osc. Switch Enable 1H options */
1256 #define _OSCS_OFF_1H 0xFF /* Disabled */
1257 #define _OSCS_ON_1H 0xDF /* Enabled */
1259 /* Power Up Timer 2L options */
1260 #define _PUT_OFF_2L 0xFF /* Disabled */
1261 #define _PUT_ON_2L 0xFE /* Enabled */
1263 /* Brown Out Detect 2L options */
1264 #define _BODEN_ON_2L 0xFF /* Enabled */
1265 #define _BODEN_OFF_2L 0xFD /* Disabled */
1267 /* Brown Out Voltage 2L options */
1268 #define _BODENV_2_5V_2L 0xFF /* 2.5V */
1269 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
1270 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
1271 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
1273 /* Watchdog Timer 2H options */
1274 #define _WDT_ON_2H 0xFF /* Enabled */
1275 #define _WDT_OFF_2H 0xFE /* Disabled */
1277 /* Watchdog Postscaler 2H options */
1278 #define _WDTPS_1_128_2H 0xFF /* 1:128 */
1279 #define _WDTPS_1_64_2H 0xFD /* 1:64 */
1280 #define _WDTPS_1_32_2H 0xFB /* 1:32 */
1281 #define _WDTPS_1_16_2H 0xF9 /* 1:16 */
1282 #define _WDTPS_1_8_2H 0xF7 /* 1:8 */
1283 #define _WDTPS_1_4_2H 0xF5 /* 1:4 */
1284 #define _WDTPS_1_2_2H 0xF3 /* 1:2 */
1285 #define _WDTPS_1_1_2H 0xF1 /* 1:1 */
1287 /* External Bus Wait 3L options */
1288 #define _WAIT_OFF_3L 0xFF /* Disabled */
1289 #define _WAIT_ON_3L 0x7F /* Enabled */
1291 /* CCP2 Mux 3H options */
1292 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1293 #define _CCP2MUX_RE7_MICROCONTROLLER__RB3_3H 0xFE /* RE7(Microcontroller)/RB3 */
1295 /* Timer1 OSC 3H options */
1296 #define _T1OSCMX_LOW_3H 0xFD /* Low Power */
1298 /* Low Voltage Program 3H options */
1299 #define _LVP_ON_3H 0xFF /* Enabled */
1300 #define _LVP_OFF_3H 0xFB /* Disabled */
1302 /* Background Debug 3H options */
1303 #define _BACKBUG_OFF_3H 0xFF /* Disabled */
1304 #define _BACKBUG_ON_3H 0x7F /* Enabled */
1306 /* Stack Overflow Reset 3H options */
1307 #define _STVR_ON_3H 0xFF /* Enabled */
1308 #define _STVR_OFF_3H 0xFE /* Disabled */
1310 /* Code Protect 00800-01FFF 5L options */
1311 #define _CP_0_OFF_5L 0xFF /* Disabled */
1312 #define _CP_0_ON_5L 0xFE /* Enabled */
1314 /* Code Protect 02000-03FFF 5L options */
1315 #define _CP_1_OFF_5L 0xFF /* Disabled */
1316 #define _CP_1_ON_5L 0xFD /* Enabled */
1318 /* Code Protect 04000-05FFF 5L options */
1319 #define _CP_2_OFF_5L 0xFF /* Disabled */
1320 #define _CP_2_ON_5L 0xFB /* Enabled */
1322 /* Code Protect 06000-07FFF 5L options */
1323 #define _CP_3_OFF_5L 0xFF /* Disabled */
1324 #define _CP_3_ON_5L 0xF7 /* Enabled */
1326 /* Data EE Read Protect 5H options */
1327 #define _CPD_OFF_5H 0xFF /* Disabled */
1328 #define _CPD_ON_5H 0x7F /* Enabled */
1330 /* Code Protect Boot 5H options */
1331 #define _CPB_OFF_5H 0xFF /* Disabled */
1332 #define _CPB_ON_5H 0xBF /* Enabled */
1334 /* Table Write Protect 00800-01FFF 6L options */
1335 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1336 #define _WRT_0_ON_6L 0xFE /* Enabled */
1338 /* Table Write Protect 02000-03FFF 6L options */
1339 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1340 #define _WRT_1_ON_6L 0xFD /* Enabled */
1342 /* Table Write Protect 04000-05FFF 6L options */
1343 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1344 #define _WRT_2_ON_6L 0xFB /* Enabled */
1346 /* Table Write Protect 06000-07FFF 6L options */
1347 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1348 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1350 /* Data EE Write Protect 6H options */
1351 #define _WRTD_OFF_6H 0xFF /* Disabled */
1352 #define _WRTD_ON_6H 0x7F /* Enabled */
1354 /* Table Write Protect Boot 6H options */
1355 #define _WRTB_OFF_6H 0xFF /* Disabled */
1356 #define _WRTB_ON_6H 0xBF /* Enabled */
1358 /* Config. Write Protect 6H options */
1359 #define _WRTC_OFF_6H 0xFF /* Disabled */
1360 #define _WRTC_ON_6H 0xDF /* Enabled */
1362 /* Table Read Protect 00800-01FFF 7L options */
1363 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1364 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1366 /* Table Read Protect 02000-03FFF 7L options */
1367 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1368 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1370 /* Table Read Protect 04000-05FFF 7L options */
1371 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1372 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1374 /* Table Read Protect 06000-07FFF 7L options */
1375 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1376 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1378 /* Table Read Protect Boot 7H options */
1379 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1380 #define _EBTRB_ON_7H 0xBF /* Enabled */
1383 /* Device ID locations */
1384 #define __IDLOC0 0x200000
1385 #define __IDLOC1 0x200001
1386 #define __IDLOC2 0x200002
1387 #define __IDLOC3 0x200003
1388 #define __IDLOC4 0x200004
1389 #define __IDLOC5 0x200005
1390 #define __IDLOC6 0x200006
1391 #define __IDLOC7 0x200007