2 * pic18f46k20.h - device specific declarations
4 * This file is part of the GNU PIC library for SDCC,
5 * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
7 * It has been automatically generated by inc2h-pic16.pl,
8 * (c) 2007 by Raphael Neider <rneider AT web.de>
11 #ifndef __PIC18F46K20_H__
12 #define __PIC18F46K20_H__ 1
17 #define __CONFIG1H 0x300001
18 #define __CONFIG2L 0x300002
19 #define __CONFIG2H 0x300003
20 #define __CONFIG3H 0x300005
21 #define __CONFIG4L 0x300006
22 #define __CONFIG5L 0x300008
23 #define __CONFIG5H 0x300009
24 #define __CONFIG6L 0x30000A
25 #define __CONFIG6H 0x30000B
26 #define __CONFIG7L 0x30000C
27 #define __CONFIG7H 0x30000D
30 #define _OSC_LP_1H 0xF0 // LP
31 #define _OSC_XT_1H 0xF1 // XT
32 #define _OSC_HS_1H 0xF2 // HS
33 #define _OSC_RC_1H 0xF3 // RC
34 #define _OSC_EC_1H 0xF4 // EC-OSC2 as Clock Out
35 #define _OSC_ECIO6_1H 0xF5 // EC-OSC2 as RA6
36 #define _OSC_HSPLL_1H 0xF6 // HS-PLL Enabled
37 #define _OSC_RCIO6_1H 0xF7 // RC-OSC2 as RA6
38 #define _OSC_INTIO67_1H 0xF8 // INTRC-OSC2 as RA6, OSC1 as RA7
39 #define _OSC_INTIO7_1H 0xF9 // INTRC-OSC2 as Clock Out, OSC1 as RA7
40 #define _FCMEN_OFF_1H 0xBF // Disabled
41 #define _FCMEN_ON_1H 0xFF // Enabled
42 #define _IESO_OFF_1H 0x7F // Disabled
43 #define _IESO_ON_1H 0xFF // Enabled
46 #define _PWRT_ON_2L 0xFE // Enabled
47 #define _PWRT_OFF_2L 0xFF // Disabled
48 #define _BOREN_OFF_2L 0xF9 // Disabled
49 #define _BOREN_ON_2L 0xFB // SBOREN Enabled
50 #define _BOREN_NOSLP_2L 0xFD // Enabled except SLEEP, SBOREN Disabled
51 #define _BOREN_SBORDIS_2L 0xFF // Enabled, SBOREN Disabled
52 #define _BORV_46_2L 0xE7 // 3.0V
53 #define _BORV_43_2L 0xEF // 2.7V
54 #define _BORV_28_2L 0xF7 // 2.2V
55 #define _BORV_21_2L 0xFF // 1.8
58 #define _WDT_OFF_2H 0xFE // Disabled
59 #define _WDT_ON_2H 0xFF // Enabled
60 #define _WDTPS_1_2H 0xE1 // 1:1
61 #define _WDTPS_2_2H 0xE3 // 1:2
62 #define _WDTPS_4_2H 0xE5 // 1:4
63 #define _WDTPS_8_2H 0xE7 // 1:8
64 #define _WDTPS_16_2H 0xE9 // 1:16
65 #define _WDTPS_32_2H 0xEB // 1:32
66 #define _WDTPS_64_2H 0xED // 1:64
67 #define _WDTPS_128_2H 0xEF // 1:128
68 #define _WDTPS_256_2H 0xF1 // 1:256
69 #define _WDTPS_512_2H 0xF3 // 1:512
70 #define _WDTPS_1024_2H 0xF5 // 1:1024
71 #define _WDTPS_2048_2H 0xF7 // 1:2048
72 #define _WDTPS_4096_2H 0xF9 // 1:4096
73 #define _WDTPS_8192_2H 0xFB // 1:8192
74 #define _WDTPS_16384_2H 0xFD // 1:16384
75 #define _WDTPS_32768_2H 0xFF // 1:32768
78 #define _MCLRE_OFF_3H 0x7F // Disabled
79 #define _MCLRE_ON_3H 0xFF // Enabled
80 #define _LPT1OSC_OFF_3H 0xFB // Disabled
81 #define _LPT1OSC_ON_3H 0xFF // Enabled
82 #define _PBADEN_OFF_3H 0xFD // Port B<4:0> digital on RESET
83 #define _PBADEN_ON_3H 0xFF // Port B<4:0> analog on RESET
84 #define _CCP2MX_PORTBE_3H 0xFE // Muxed with RB3
85 #define _CCP2MX_PORTC_3H 0xFF // Muxed with RC1
88 #define _STVREN_OFF_4L 0xFE // Disabled
89 #define _STVREN_ON_4L 0xFF // Enabled
90 #define _LVP_OFF_4L 0xFB // Disabled
91 #define _LVP_ON_4L 0xFF // Enabled
92 #define _XINST_OFF_4L 0xBF // Disabled
93 #define _XINST_ON_4L 0xFF // Enabled
94 #define _DEBUG_ON_4L 0x7F // Enabled
95 #define _DEBUG_OFF_4L 0xFF // Disabled
98 #define _CP0_ON_5L 0xFE // Enabled
99 #define _CP0_OFF_5L 0xFF // Disabled
100 #define _CP1_ON_5L 0xFD // Enabled
101 #define _CP1_OFF_5L 0xFF // Disabled
102 #define _CP2_ON_5L 0xFB // Enabled
103 #define _CP2_OFF_5L 0xFF // Disabled
104 #define _CP3_ON_5L 0xF7 // Enabled
105 #define _CP3_OFF_5L 0xFF // Disabled
108 #define _CPB_ON_5H 0xBF // Enabled
109 #define _CPB_OFF_5H 0xFF // Disabled
110 #define _CPD_ON_5H 0x7F // Enabled
111 #define _CPD_OFF_5H 0xFF // Disabled
114 #define _WRT0_ON_6L 0xFE // Enabled
115 #define _WRT0_OFF_6L 0xFF // Disabled
116 #define _WRT1_ON_6L 0xFD // Enabled
117 #define _WRT1_OFF_6L 0xFF // Disabled
118 #define _WRT2_ON_6L 0xFB // Enabled
119 #define _WRT2_OFF_6L 0xFF // Disabled
120 #define _WRT3_ON_6L 0xF7 // Enabled
121 #define _WRT3_OFF_6L 0xFF // Disabled
124 #define _WRTB_ON_6H 0xBF // Enabled
125 #define _WRTB_OFF_6H 0xFF // Disabled
126 #define _WRTC_ON_6H 0xDF // Enabled
127 #define _WRTC_OFF_6H 0xFF // Disabled
128 #define _WRTD_ON_6H 0x7F // Enabled
129 #define _WRTD_OFF_6H 0xFF // Disabled
132 #define _EBTR0_ON_7L 0xFE // Enabled
133 #define _EBTR0_OFF_7L 0xFF // Disabled
134 #define _EBTR1_ON_7L 0xFD // Enabled
135 #define _EBTR1_OFF_7L 0xFF // Disabled
136 #define _EBTR2_ON_7L 0xFB // Enabled
137 #define _EBTR2_OFF_7L 0xFF // Disabled
138 #define _EBTR3_ON_7L 0xF7 // Enabled
139 #define _EBTR3_OFF_7L 0xFF // Disabled
142 #define _EBTRB_ON_7H 0xBF // Enabled
143 #define _EBTRB_OFF_7H 0xFF // Disabled
144 #define _DEVID1 0x3FFFFE
145 #define _DEVID2 0x3FFFFF
146 #define _IDLOC0 0x200000
147 #define _IDLOC1 0x200001
148 #define _IDLOC2 0x200002
149 #define _IDLOC3 0x200003
150 #define _IDLOC4 0x200004
151 #define _IDLOC5 0x200005
152 #define _IDLOC6 0x200006
153 #define _IDLOC7 0x200007
155 extern __sfr __at (0xF77) SSPMSK;
157 extern __sfr __at (0xF78) SLRCON;
170 extern volatile __SLRCONbits_t __at (0xF78) SLRCONbits;
172 extern __sfr __at (0xF79) CM12CON;
185 extern volatile __CM12CONbits_t __at (0xF79) CM12CONbits;
187 extern __sfr __at (0xF7A) CM2CON;
200 extern volatile __CM2CONbits_t __at (0xF7A) CM2CONbits;
202 extern __sfr __at (0xF7B) CM1CON;
215 extern volatile __CM1CONbits_t __at (0xF7B) CM1CONbits;
217 extern __sfr __at (0xF7C) WPUB;
230 extern volatile __WPUBbits_t __at (0xF7C) WPUBbits;
232 extern __sfr __at (0xF7D) IOCB;
245 extern volatile __IOCBbits_t __at (0xF7D) IOCBbits;
247 extern __sfr __at (0xF7E) ANSEL;
260 extern volatile __ANSELbits_t __at (0xF7E) ANSELbits;
262 extern __sfr __at (0xF7F) ANSELH;
275 extern volatile __ANSELHbits_t __at (0xF7F) ANSELHbits;
277 extern __sfr __at (0xF80) PORTA;
300 unsigned C12IN0M : 1;
301 unsigned C12IN1M : 1;
310 unsigned C12IN0N : 1;
311 unsigned C12IN1N : 1;
350 extern volatile __PORTAbits_t __at (0xF80) PORTAbits;
352 extern __sfr __at (0xF81) PORTB;
368 unsigned CCP2_PORTB : 1;
386 unsigned C12IN2M : 1;
388 unsigned C12IN3M : 1;
396 unsigned C12IN2N : 1;
398 unsigned C12IN3N : 1;
405 extern volatile __PORTBbits_t __at (0xF81) PORTBbits;
407 extern __sfr __at (0xF82) PORTC;
431 unsigned CCP2_PORTC : 1;
450 extern volatile __PORTCbits_t __at (0xF82) PORTCbits;
452 extern __sfr __at (0xF83) PORTD;
485 extern volatile __PORTDbits_t __at (0xF83) PORTDbits;
487 extern __sfr __at (0xF84) PORTE;
513 unsigned NOT_MCLR : 1;
530 extern volatile __PORTEbits_t __at (0xF84) PORTEbits;
532 extern __sfr __at (0xF89) LATA;
545 extern volatile __LATAbits_t __at (0xF89) LATAbits;
547 extern __sfr __at (0xF8A) LATB;
560 extern volatile __LATBbits_t __at (0xF8A) LATBbits;
562 extern __sfr __at (0xF8B) LATC;
575 extern volatile __LATCbits_t __at (0xF8B) LATCbits;
577 extern __sfr __at (0xF8C) LATD;
590 extern volatile __LATDbits_t __at (0xF8C) LATDbits;
592 extern __sfr __at (0xF8D) LATE;
605 extern volatile __LATEbits_t __at (0xF8D) LATEbits;
607 extern __sfr __at (0xF92) DDRA;
620 extern volatile __DDRAbits_t __at (0xF92) DDRAbits;
622 extern __sfr __at (0xF92) TRISA;
635 extern volatile __TRISAbits_t __at (0xF92) TRISAbits;
637 extern __sfr __at (0xF93) DDRB;
650 extern volatile __DDRBbits_t __at (0xF93) DDRBbits;
652 extern __sfr __at (0xF93) TRISB;
665 extern volatile __TRISBbits_t __at (0xF93) TRISBbits;
667 extern __sfr __at (0xF94) DDRC;
680 extern volatile __DDRCbits_t __at (0xF94) DDRCbits;
682 extern __sfr __at (0xF94) TRISC;
695 extern volatile __TRISCbits_t __at (0xF94) TRISCbits;
697 extern __sfr __at (0xF95) DDRD;
710 extern volatile __DDRDbits_t __at (0xF95) DDRDbits;
712 extern __sfr __at (0xF95) TRISD;
725 extern volatile __TRISDbits_t __at (0xF95) TRISDbits;
727 extern __sfr __at (0xF96) DDRE;
740 extern volatile __DDREbits_t __at (0xF96) DDREbits;
742 extern __sfr __at (0xF96) TRISE;
749 unsigned PSPMODE : 1;
755 extern volatile __TRISEbits_t __at (0xF96) TRISEbits;
757 extern __sfr __at (0xF9B) OSCTUNE;
770 extern volatile __OSCTUNEbits_t __at (0xF9B) OSCTUNEbits;
772 extern __sfr __at (0xF9D) PIE1;
785 extern volatile __PIE1bits_t __at (0xF9D) PIE1bits;
787 extern __sfr __at (0xF9E) PIR1;
800 extern volatile __PIR1bits_t __at (0xF9E) PIR1bits;
802 extern __sfr __at (0xF9F) IPR1;
815 extern volatile __IPR1bits_t __at (0xF9F) IPR1bits;
817 extern __sfr __at (0xFA0) PIE2;
840 extern volatile __PIE2bits_t __at (0xFA0) PIE2bits;
842 extern __sfr __at (0xFA1) PIR2;
865 extern volatile __PIR2bits_t __at (0xFA1) PIR2bits;
867 extern __sfr __at (0xFA2) IPR2;
890 extern volatile __IPR2bits_t __at (0xFA2) IPR2bits;
892 extern __sfr __at (0xFA6) EECON1;
905 extern volatile __EECON1bits_t __at (0xFA6) EECON1bits;
907 extern __sfr __at (0xFA7) EECON2;
909 extern __sfr __at (0xFA8) EEDATA;
911 extern __sfr __at (0xFA9) EEADR;
913 extern __sfr __at (0xFAB) RCSTA;
936 extern volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;
938 extern __sfr __at (0xFAC) TXSTA;
951 extern volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;
953 extern __sfr __at (0xFAD) TXREG;
955 extern __sfr __at (0xFAE) RCREG;
957 extern __sfr __at (0xFAF) SPBRG;
959 extern __sfr __at (0xFB0) SPBRGH;
961 extern __sfr __at (0xFB1) T3CON;
968 unsigned T3CKPS0 : 1;
969 unsigned T3CKPS1 : 1;
976 unsigned NOT_T3SYNC : 1;
984 extern volatile __T3CONbits_t __at (0xFB1) T3CONbits;
986 extern __sfr __at (0xFB2) TMR3L;
988 extern __sfr __at (0xFB3) TMR3H;
990 extern __sfr __at (0xFB4) CVRCON2;
1003 extern volatile __CVRCON2bits_t __at (0xFB4) CVRCON2bits;
1005 extern __sfr __at (0xFB5) CVRCON;
1018 extern volatile __CVRCONbits_t __at (0xFB5) CVRCONbits;
1020 extern __sfr __at (0xFB6) ECCP1AS;
1023 unsigned PSSBD0 : 1;
1024 unsigned PSSBD1 : 1;
1025 unsigned PSSAC0 : 1;
1026 unsigned PSSAC1 : 1;
1027 unsigned ECCPAS0 : 1;
1028 unsigned ECCPAS1 : 1;
1029 unsigned ECCPAS2 : 1;
1030 unsigned ECCPASE : 1;
1033 extern volatile __ECCP1ASbits_t __at (0xFB6) ECCP1ASbits;
1035 extern __sfr __at (0xFB7) PWM1CON;
1048 extern volatile __PWM1CONbits_t __at (0xFB7) PWM1CONbits;
1050 extern __sfr __at (0xFB8) BAUDCON;
1060 unsigned ABDOVF : 1;
1073 extern volatile __BAUDCONbits_t __at (0xFB8) BAUDCONbits;
1075 extern __sfr __at (0xFB8) BAUDCTL;
1085 unsigned ABDOVF : 1;
1098 extern volatile __BAUDCTLbits_t __at (0xFB8) BAUDCTLbits;
1100 extern __sfr __at (0xFB9) PSTRCON;
1107 unsigned STRSYNC : 1;
1113 extern volatile __PSTRCONbits_t __at (0xFB9) PSTRCONbits;
1115 extern __sfr __at (0xFBA) CCP2CON;
1118 unsigned CCP2M0 : 1;
1119 unsigned CCP2M1 : 1;
1120 unsigned CCP2M2 : 1;
1121 unsigned CCP2M3 : 1;
1128 extern volatile __CCP2CONbits_t __at (0xFBA) CCP2CONbits;
1130 extern __sfr __at (0xFBB) CCPR2;
1132 extern __sfr __at (0xFBB) CCPR2L;
1134 extern __sfr __at (0xFBC) CCPR2H;
1136 extern __sfr __at (0xFBD) CCP1CON;
1139 unsigned CCP1M0 : 1;
1140 unsigned CCP1M1 : 1;
1141 unsigned CCP1M2 : 1;
1142 unsigned CCP1M3 : 1;
1149 extern volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;
1151 extern __sfr __at (0xFBE) CCPR1;
1153 extern __sfr __at (0xFBE) CCPR1L;
1155 extern __sfr __at (0xFBF) CCPR1H;
1157 extern __sfr __at (0xFC0) ADCON2;
1170 extern volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;
1172 extern __sfr __at (0xFC1) ADCON1;
1185 extern volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;
1187 extern __sfr __at (0xFC2) ADCON0;
1211 unsigned NOT_DONE : 1;
1221 unsigned GO_DONE : 1;
1230 extern volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;
1232 extern __sfr __at (0xFC3) ADRES;
1234 extern __sfr __at (0xFC3) ADRESL;
1236 extern __sfr __at (0xFC4) ADRESH;
1238 extern __sfr __at (0xFC5) SSPCON2;
1247 unsigned ACKSTAT : 1;
1251 extern volatile __SSPCON2bits_t __at (0xFC5) SSPCON2bits;
1253 extern __sfr __at (0xFC6) SSPCON1;
1266 extern volatile __SSPCON1bits_t __at (0xFC6) SSPCON1bits;
1268 extern __sfr __at (0xFC7) SSPSTAT;
1303 unsigned NOT_WRITE : 1;
1306 unsigned NOT_ADDRESS : 1;
1311 extern volatile __SSPSTATbits_t __at (0xFC7) SSPSTATbits;
1313 extern __sfr __at (0xFC8) SSPADD;
1315 extern __sfr __at (0xFC9) SSPBUF;
1317 extern __sfr __at (0xFCA) T2CON;
1320 unsigned T2CKPS0 : 1;
1321 unsigned T2CKPS1 : 1;
1322 unsigned TMR2ON : 1;
1323 unsigned T2OUTPS0 : 1;
1324 unsigned T2OUTPS1 : 1;
1325 unsigned T2OUTPS2 : 1;
1326 unsigned T2OUTPS3 : 1;
1330 extern volatile __T2CONbits_t __at (0xFCA) T2CONbits;
1332 extern __sfr __at (0xFCB) PR2;
1334 extern __sfr __at (0xFCC) TMR2;
1336 extern __sfr __at (0xFCD) T1CON;
1339 unsigned TMR1ON : 1;
1340 unsigned TMR1CS : 1;
1341 unsigned T1SYNC : 1;
1342 unsigned T1OSCEN : 1;
1343 unsigned T1CKPS0 : 1;
1344 unsigned T1CKPS1 : 1;
1351 unsigned NOT_T1SYNC : 1;
1359 extern volatile __T1CONbits_t __at (0xFCD) T1CONbits;
1361 extern __sfr __at (0xFCE) TMR1L;
1363 extern __sfr __at (0xFCF) TMR1H;
1365 extern __sfr __at (0xFD0) RCON;
1374 unsigned SBOREN : 1;
1378 unsigned NOT_BOR : 1;
1379 unsigned NOT_POR : 1;
1380 unsigned NOT_PD : 1;
1381 unsigned NOT_TO : 1;
1382 unsigned NOT_RI : 1;
1388 extern volatile __RCONbits_t __at (0xFD0) RCONbits;
1390 extern __sfr __at (0xFD1) WDTCON;
1393 unsigned SWDTEN : 1;
1413 extern volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;
1415 extern __sfr __at (0xFD2) HLVDCON;
1425 unsigned VDIRMAG : 1;
1432 unsigned HLVDEN : 1;
1438 unsigned HLVDL0 : 1;
1439 unsigned HLVDL1 : 1;
1440 unsigned HLVDL2 : 1;
1441 unsigned HLVDL3 : 1;
1448 extern volatile __HLVDCONbits_t __at (0xFD2) HLVDCONbits;
1450 extern __sfr __at (0xFD2) LVDCON;
1460 unsigned VDIRMAG : 1;
1467 unsigned HLVDEN : 1;
1473 unsigned HLVDL0 : 1;
1474 unsigned HLVDL1 : 1;
1475 unsigned HLVDL2 : 1;
1476 unsigned HLVDL3 : 1;
1483 extern volatile __LVDCONbits_t __at (0xFD2) LVDCONbits;
1485 extern __sfr __at (0xFD3) OSCCON;
1498 extern volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;
1500 extern __sfr __at (0xFD4) DEBUG;
1502 extern __sfr __at (0xFD5) T0CON;
1511 unsigned T08BIT : 1;
1512 unsigned TMR0ON : 1;
1515 extern volatile __T0CONbits_t __at (0xFD5) T0CONbits;
1517 extern __sfr __at (0xFD6) TMR0L;
1519 extern __sfr __at (0xFD7) TMR0H;
1521 extern __sfr __at (0xFD8) STATUS;
1534 extern volatile __STATUSbits_t __at (0xFD8) STATUSbits;
1536 extern __sfr __at (0xFD9) FSR2L;
1538 extern __sfr __at (0xFDA) FSR2H;
1540 extern __sfr __at (0xFDB) PLUSW2;
1542 extern __sfr __at (0xFDC) PREINC2;
1544 extern __sfr __at (0xFDD) POSTDEC2;
1546 extern __sfr __at (0xFDE) POSTINC2;
1548 extern __sfr __at (0xFDF) INDF2;
1550 extern __sfr __at (0xFE0) BSR;
1552 extern __sfr __at (0xFE1) FSR1L;
1554 extern __sfr __at (0xFE2) FSR1H;
1556 extern __sfr __at (0xFE3) PLUSW1;
1558 extern __sfr __at (0xFE4) PREINC1;
1560 extern __sfr __at (0xFE5) POSTDEC1;
1562 extern __sfr __at (0xFE6) POSTINC1;
1564 extern __sfr __at (0xFE7) INDF1;
1566 extern __sfr __at (0xFE8) WREG;
1568 extern __sfr __at (0xFE9) FSR0L;
1570 extern __sfr __at (0xFEA) FSR0H;
1572 extern __sfr __at (0xFEB) PLUSW0;
1574 extern __sfr __at (0xFEC) PREINC0;
1576 extern __sfr __at (0xFED) POSTDEC0;
1578 extern __sfr __at (0xFEE) POSTINC0;
1580 extern __sfr __at (0xFEF) INDF0;
1582 extern __sfr __at (0xFF0) INTCON3;
1595 unsigned INT1IF : 1;
1596 unsigned INT2IF : 1;
1598 unsigned INT1IE : 1;
1599 unsigned INT2IE : 1;
1601 unsigned INT1IP : 1;
1602 unsigned INT2IP : 1;
1605 extern volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;
1607 extern __sfr __at (0xFF1) INTCON2;
1612 unsigned TMR0IP : 1;
1614 unsigned INTEDG2 : 1;
1615 unsigned INTEDG1 : 1;
1616 unsigned INTEDG0 : 1;
1627 unsigned NOT_RBPU : 1;
1630 extern volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;
1632 extern __sfr __at (0xFF2) INTCON;
1637 unsigned TMR0IF : 1;
1640 unsigned TMR0IE : 1;
1646 unsigned INT0IF : 1;
1649 unsigned INT0IE : 1;
1655 extern volatile __INTCONbits_t __at (0xFF2) INTCONbits;
1657 extern __sfr __at (0xFF3) PROD;
1659 extern __sfr __at (0xFF3) PRODL;
1661 extern __sfr __at (0xFF4) PRODH;
1663 extern __sfr __at (0xFF5) TABLAT;
1665 extern __sfr __at (0xFF6) TBLPTR;
1667 extern __sfr __at (0xFF6) TBLPTRL;
1669 extern __sfr __at (0xFF7) TBLPTRH;
1671 extern __sfr __at (0xFF8) TBLPTRU;
1673 extern __sfr __at (0xFF9) PC;
1675 extern __sfr __at (0xFF9) PCL;
1677 extern __sfr __at (0xFFA) PCLATH;
1679 extern __sfr __at (0xFFB) PCLATU;
1681 extern __sfr __at (0xFFC) STKPTR;
1690 unsigned STKUNF : 1;
1691 unsigned STKOVF : 1;
1694 extern volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;
1696 extern __sfr __at (0xFFD) TOS;
1698 extern __sfr __at (0xFFD) TOSL;
1700 extern __sfr __at (0xFFE) TOSH;
1702 extern __sfr __at (0xFFF) TOSU;