2 * pic18f4620.h - PIC18F4620 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * The GNU PIC Library is maintained by
8 * Raphael Neider <rneider AT web.de>
10 * originally designed by
11 * Vangelis Rokas <vrokas@otenet.gr>
14 * Added based on existing PICs
15 * Gary Plumbridge <gary@phodex.net>
21 #ifndef __PIC18F4620_H__
22 #define __PIC18F4620_H__ 1
24 extern __sfr __at (0xF80) PORTA;
81 extern volatile __PORTA_t __at (0xF80) PORTAbits;
83 extern __sfr __at (0xF81) PORTB;
120 extern volatile __PORTB_t __at (0xF81) PORTBbits;
122 extern __sfr __at (0xF82) PORTC;
154 unsigned DTC :1; /* DT might be a reserved word in ASM */
169 extern volatile __PORTC_t __at (0xF82) PORTCbits;
171 extern __sfr __at (0xF83) PORTD;
208 extern volatile __PORTD_t __at (0xF83) PORTDbits;
210 extern __sfr __at (0xF84) PORTE;
247 extern volatile __PORTE_t __at (0xF84) PORTEbits;
249 extern __sfr __at (0xF89) LATA;
262 extern volatile __LATA_t __at (0xF89) LATAbits;
264 extern __sfr __at (0xF8A) LATB;
277 extern volatile __LATB_t __at (0xF8A) LATBbits;
279 extern __sfr __at (0xF8B) LATC;
292 extern volatile __LATC_t __at (0xF8B) LATCbits;
294 extern __sfr __at (0xF8C) LATD;
307 extern volatile __LATD_t __at (0xF8C) LATDbits;
309 extern __sfr __at (0xF8D) LATE;
322 extern volatile __LATE_t __at (0xF8D) LATEbits;
324 extern __sfr __at (0xF92) TRISA;
337 extern volatile __TRISA_t __at (0xF92) TRISAbits;
339 extern __sfr __at (0xF93) TRISB;
352 extern volatile __TRISB_t __at (0xF93) TRISBbits;
354 extern __sfr __at (0xF94) TRISC;
367 extern volatile __TRISC_t __at (0xF94) TRISCbits;
369 extern __sfr __at (0xF95) TRISD;
382 extern volatile __TRISD_t __at (0xF95) TRISDbits;
384 extern __sfr __at (0xF96) TRISE;
397 extern volatile __TRISE_t __at (0xF96) TRISEbits;
399 extern __sfr __at (0xF9B) OSCTUNE;
408 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
410 extern __sfr __at (0xF9D) PIE1;
423 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
425 extern __sfr __at (0xF9E) PIR1;
438 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
440 extern __sfr __at (0xF9F) IPR1;
453 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
455 extern __sfr __at (0xFA0) PIE2;
468 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
470 extern __sfr __at (0xFA1) PIR2;
483 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
485 extern __sfr __at (0xFA2) IPR2;
498 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
500 extern __sfr __at (0xFA6) EECON1;
513 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
515 extern __sfr __at (0xFA7) EECON2;
517 extern __sfr __at (0xFA8) EEDATA;
519 extern __sfr __at (0xFA9) EEADR;
521 extern __sfr __at (0xFAB) RCSTA;
534 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
536 extern __sfr __at (0xFAC) TXSTA;
549 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
551 extern __sfr __at (0xFAD) TXREG;
553 extern __sfr __at (0xFAE) RCREG;
555 extern __sfr __at (0xFAF) SPBRG;
557 extern __sfr __at (0xFB0) SPBRGH;
559 extern __sfr __at (0xFB1) T3CON;
564 unsigned NOT_T3SYNC : 1;
566 unsigned T3CKPS0 : 1;
567 unsigned T3CKPS1 : 1;
572 extern volatile __T3CON_t __at (0xFB1) T3CONbits;
574 extern __sfr __at (0xFB2) TMR3L;
576 extern __sfr __at (0xFB3) TMR3H;
578 extern __sfr __at (0xFB4) CMCON;
591 extern volatile __CMCON_t __at (0xFB4) CMCONbits;
593 extern __sfr __at (0xFB5) CVRCON;
606 extern volatile __CVRCON_t __at (0xFB5) CVRCONbits;
608 extern __sfr __at (0xFB6) ECCP1AS;
615 unsigned ECCPAS0 : 1;
616 unsigned ECCPAS1 : 1;
617 unsigned ECCPAS2 : 1;
618 unsigned ECCPASE : 1;
621 extern volatile __ECCP1AS_t __at (0xFB6) ECCP1ASbits;
623 extern __sfr __at (0xFB7) PWM1CON;
636 extern volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
638 extern __sfr __at (0xFB8) BAUDCON;
651 extern volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
653 extern __sfr __at (0xFBA) CCP2CON;
666 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
668 extern __sfr __at (0xFBB) CCPR2L;
670 extern __sfr __at (0xFBC) CCPR2H;
672 extern __sfr __at (0xFBD) CCP1CON;
685 extern volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
687 extern __sfr __at (0xFBE) CCPR1L;
689 extern __sfr __at (0xFBF) CCPR1H;
691 extern __sfr __at (0xFC0) ADCON2;
704 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
706 extern __sfr __at (0xFC1) ADCON1;
719 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
721 extern __sfr __at (0xFC2) ADCON0;
734 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
736 extern __sfr __at (0xFC3) ADRESL;
738 extern __sfr __at (0xFC4) ADRESH;
740 extern __sfr __at (0xFC5) SSPCON2;
749 unsigned ACKSTAT : 1;
753 extern volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
755 extern __sfr __at (0xFC6) SSPCON1;
768 extern volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
770 extern __sfr __at (0xFC7) SSPSTAT;
783 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
785 extern __sfr __at (0xFC8) SSPADD;
787 extern __sfr __at (0xFC9) SSPBUF;
789 extern __sfr __at (0xFCA) T2CON;
792 unsigned T2CKPS0 : 1;
793 unsigned T2CKPS1 : 1;
795 unsigned TOUTPS0 : 1;
796 unsigned TOUTPS1 : 1;
797 unsigned TOUTPS2 : 1;
798 unsigned TOUTPS3 : 1;
802 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
804 extern __sfr __at (0xFCB) PR2;
806 extern __sfr __at (0xFCC) TMR2;
808 extern __sfr __at (0xFCD) T1CON;
813 unsigned NOT_T1SYNC : 1;
814 unsigned T1OSCEN : 1;
815 unsigned T1CKPS0 : 1;
816 unsigned T1CKPS1 : 1;
821 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
823 extern __sfr __at (0xFCE) TMR1L;
825 extern __sfr __at (0xFCF) TMR1H;
827 extern __sfr __at (0xFD0) RCON;
840 extern volatile __RCON_t __at (0xFD0) RCONbits;
842 extern __sfr __at (0xFD1) WDTCON;
855 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
857 extern __sfr __at (0xFD2) HLVDCON;
867 unsigned VDIRMAG : 1;
870 extern volatile __HLVDCON_t __at (0xFD2) HLVDCONbits;
872 extern __sfr __at (0xFD3) OSCCON;
882 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
884 extern __sfr __at (0xFD5) T0CON;
897 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
899 extern __sfr __at (0xFD6) TMR0L;
901 extern __sfr __at (0xFD7) TMR0H;
903 extern __sfr __at (0xFD8) STATUS;
916 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
918 extern __sfr __at (0xFD9) FSR2L;
920 extern __sfr __at (0xFDA) FSR2H;
930 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
932 extern __sfr __at (0xFDB) PLUSW2;
934 extern __sfr __at (0xFDC) PREINC2;
936 extern __sfr __at (0xFDD) POSTDEC2;
938 extern __sfr __at (0xFDE) POSTINC2;
940 extern __sfr __at (0xFDF) INDF2;
942 extern __sfr __at (0xFE0) BSR;
952 extern volatile __BSR_t __at (0xFE0) BSRbits;
954 extern __sfr __at (0xFE1) FSR1L;
956 extern __sfr __at (0xFE2) FSR1H;
966 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
968 extern __sfr __at (0xFE3) PLUSW1;
970 extern __sfr __at (0xFE4) PREINC1;
972 extern __sfr __at (0xFE5) POSTDEC1;
974 extern __sfr __at (0xFE6) POSTINC1;
976 extern __sfr __at (0xFE7) INDF1;
978 extern __sfr __at (0xFE8) WREG;
980 extern __sfr __at (0xFE9) FSR0L;
982 extern __sfr __at (0xFEA) FSR0H;
992 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
994 extern __sfr __at (0xFEB) PLUSW0;
996 extern __sfr __at (0xFEC) PREINC0;
998 extern __sfr __at (0xFED) POSTDEC0;
1000 extern __sfr __at (0xFEE) POSTINC0;
1002 extern __sfr __at (0xFEF) INDF0;
1004 extern __sfr __at (0xFF0) INTCON3;
1007 unsigned INT1IF : 1;
1008 unsigned INT2IF : 1;
1010 unsigned INT1IE : 1;
1011 unsigned INT2IE : 1;
1013 unsigned INT1IP : 1;
1014 unsigned INT2IP : 1;
1017 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
1019 extern __sfr __at (0xFF1) INTCON2;
1024 unsigned TMR0IP : 1;
1026 unsigned INTEDG2 : 1;
1027 unsigned INTEDG1 : 1;
1028 unsigned INTEDG0 : 1;
1032 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
1034 extern __sfr __at (0xFF2) INTCON;
1038 unsigned INT0IF : 1;
1039 unsigned TMR0IF : 1;
1041 unsigned INT0IE : 1;
1042 unsigned TMR0IE : 1;
1057 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
1059 extern __sfr __at (0xFF3) PRODL;
1061 extern __sfr __at (0xFF4) PRODH;
1063 extern __sfr __at (0xFF5) TABLAT;
1065 extern __sfr __at (0xFF6) TBLPTRL;
1067 extern __sfr __at (0xFF7) TBLPTRH;
1069 extern __sfr __at (0xFF8) TBLPTRU;
1072 unsigned TBLPTRU : 5;
1078 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
1080 extern __sfr __at (0xFF9) PCL;
1082 extern __sfr __at (0xFFA) PCLATH;
1088 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
1090 extern __sfr __at (0xFFB) PCLATU;
1099 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1101 extern __sfr __at (0xFFC) STKPTR;
1104 unsigned STKPTR : 5;
1106 unsigned STKUNF : 1;
1107 unsigned STKFUL : 1;
1110 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1112 extern __sfr __at (0xFFD) TOSL;
1114 extern __sfr __at (0xFFE) TOSH;
1116 extern __sfr __at (0xFFF) TOSU;
1125 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1127 /* Configuration register locations */
1128 #define __CONFIG1H 0x300001
1129 #define __CONFIG2L 0x300002
1130 #define __CONFIG2H 0x300003
1131 #define __CONFIG3H 0x300005
1132 #define __CONFIG4L 0x300006
1133 #define __CONFIG5L 0x300008
1134 #define __CONFIG5H 0x300009
1135 #define __CONFIG6L 0x30000A
1136 #define __CONFIG6H 0x30000B
1137 #define __CONFIG7L 0x30000C
1138 #define __CONFIG7H 0x30000D
1141 /* Oscillator 1H options */
1142 #define _OSC_INTIO7_1H 0xF9 /* INTRC-OSC2 as Clock Out, OSC1 as RA7 */
1143 #define _OSC_INTIO67_1H 0xF8 /* INTRC-OSC2 as RA6, OSC1 as RA7 */
1144 #define _OSC_RCIO6_1H 0xF7 /* RC-OSC2 as RA6 */
1145 #define _OSC_HSPLL_1H 0xF6 /* HS-PLL Enabled */
1146 #define _OSC_ECIO6_1H 0xF5 /* EC-OSC2 as RA6 */
1147 #define _OSC_EC_1H 0xF4 /* EC-OSC2 as Clock Out */
1148 #define _OSC_RC_1H 0xF3 /* RC */
1149 #define _OSC_HS_1H 0xF2 /* HS */
1150 #define _OSC_XT_1H 0xF1 /* XT */
1151 #define _OSC_LP_1H 0xF0 /* LP */
1153 /* Fail-Safe Clock Monitor Enable 1H options */
1154 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1155 #define _FCMEN_ON_1H 0xFF /* Enabled */
1157 /* Internal External Switch Over Mode 1H options */
1158 #define _IESO_OFF_1H 0x7F /* Disabled */
1159 #define _IESO_ON_1H 0xFF /* Enabled */
1161 /* Power Up Timer 2L options */
1162 #define _PUT_OFF_2L 0xFF /* Disabled */
1163 #define _PUT_ON_2L 0xFE /* Enabled */
1165 /* Brown Out Detect 2L options */
1166 #define _BODEN_ON_2L 0xFF /* Enabled in hardware, SBOREN disabled */
1167 #define _BODEN_ON_WHILE_ACTIVE_2L 0xFD /* Enabled while active,disabled in SLEEP,SBOREN disabled */
1168 #define _BODEN_CONTROLLED_WITH_SBOREN_BIT_2L 0xFB /* Controlled with SBOREN bit */
1169 #define _BODEN_OFF_2L 0xF9 /* Disabled in hardware, SBOREN disabled */
1171 /* Brown Out Voltage 2L options */
1172 #define _BODENV_2_0V_2L 0xFF /* 2.1V */
1173 #define _BODENV_2_7V_2L 0xF7 /* 2.8V */
1174 #define _BODENV_4_2V_2L 0xEF /* 4.3V */
1175 #define _BODENV_4_5V_2L 0xE7 /* 4.6V */
1178 /* Watchdog Timer 2H options */
1179 #define _WDT_ON_2H 0xFF /* Enabled */
1180 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1182 /* Watchdog Postscaler 2H options */
1183 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1184 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1185 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1186 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1187 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1188 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1189 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1190 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1191 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1192 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1193 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1194 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1195 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1196 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1197 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1198 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1201 /* CCP2 Mux 3H options */
1202 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1203 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1205 /* PortB A/D Enable 3H options */
1206 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
1207 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
1209 /* Low Power Timer1 Osc enable 3H options */
1210 #define _LPT1OSC_ON_3H 0xFF /* Enabled */
1211 #define _LPT1OSC_OFF_3H 0xFB /* Disabled */
1213 /* Master Clear Enable 3H options */
1214 #define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
1215 #define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
1218 /* Stack Overflow Reset 4L options */
1219 #define _STVR_ON_4L 0xFF /* Enabled */
1220 #define _STVR_OFF_4L 0xFE /* Disabled */
1222 /* Low Voltage Program 4L options */
1223 #define _LVP_ON_4L 0xFF /* Enabled */
1224 #define _LVP_OFF_4L 0xFB /* Disabled */
1226 /* Extended CPU Enable 4L options */
1227 #define _ENHCPU_ON_4L 0xFF /* Enabled */
1228 #define _ENHCPU_OFF_4L 0xBF /* Disabled */
1230 /* Background Debug 4L options */
1231 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1232 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1235 /* Code Protect 00800-01FFF 5L options */
1236 #define _CP_0_OFF_5L 0xFF /* Disabled */
1237 #define _CP_0_ON_5L 0xFE /* Enabled */
1239 /* Code Protect 02000-03FFF 5L options */
1240 #define _CP_1_OFF_5L 0xFF /* Disabled */
1241 #define _CP_1_ON_5L 0xFD /* Enabled */
1243 /* Code Protect 04000-05FFF 5L options */
1244 #define _CP_2_OFF_5L 0xFF /* Disabled */
1245 #define _CP_2_ON_5L 0xFB /* Enabled */
1247 /* Code Protect 06000-07FFF 5L options */
1248 #define _CP_3_OFF_5L 0xFF /* Disabled */
1249 #define _CP_3_ON_5L 0xF7 /* Enabled */
1252 /* Data EE Read Protect 5H options */
1253 #define _CPD_OFF_5H 0xFF /* Disabled */
1254 #define _CPD_ON_5H 0x7F /* Enabled */
1256 /* Code Protect Boot 5H options */
1257 #define _CPB_OFF_5H 0xFF /* Disabled */
1258 #define _CPB_ON_5H 0xBF /* Enabled */
1261 /* Table Write Protect 00800-01FFF 6L options */
1262 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1263 #define _WRT_0_ON_6L 0xFE /* Enabled */
1265 /* Table Write Protect 02000-03FFF 6L options */
1266 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1267 #define _WRT_1_ON_6L 0xFD /* Enabled */
1269 /* Table Write Protect 04000-05FFF 6L options */
1270 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1271 #define _WRT_2_ON_6L 0xFB /* Enabled */
1273 /* Table Write Protect 06000-07FFF 6L options */
1274 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1275 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1278 /* Data EE Write Protect 6H options */
1279 #define _WRTD_OFF_6H 0xFF /* Disabled */
1280 #define _WRTD_ON_6H 0x7F /* Enabled */
1282 /* Table Write Protect Boot 6H options */
1283 #define _WRTB_OFF_6H 0xFF /* Disabled */
1284 #define _WRTB_ON_6H 0xBF /* Enabled */
1286 /* Config. Write Protect 6H options */
1287 #define _WRTC_OFF_6H 0xFF /* Disabled */
1288 #define _WRTC_ON_6H 0xDF /* Enabled */
1291 /* Table Read Protect 00800-01FFF 7L options */
1292 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1293 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1295 /* Table Read Protect 02000-03FFF 7L options */
1296 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1297 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1299 /* Table Read Protect 04000-05FFF 7L options */
1300 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1301 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1303 /* Table Read Protect 06000-07FFF 7L options */
1304 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1305 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1308 /* Table Read Protect Boot 7H options */
1309 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1310 #define _EBTRB_ON_7H 0xBF /* Enabled */
1313 /* Device ID bytes */
1314 #define _DEVID1 0x3FFFFE
1315 #define _DEVID2 0x3FFFFF
1318 /* Location of User ID words */
1319 #define __IDLOC0 0x200000
1320 #define __IDLOC1 0x200001
1321 #define __IDLOC2 0x200002
1322 #define __IDLOC3 0x200003
1323 #define __IDLOC4 0x200004
1324 #define __IDLOC5 0x200005
1325 #define __IDLOC6 0x200006
1326 #define __IDLOC7 0x200007
1328 #endif // __PIC18F4620__