2 * pic18f4620.h - PIC18F4620 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * Added modifications by
8 * Gary Plumbridge <gary AT phodex.net>
11 * Copied from 18f2550 and modified for 18f2620 by
12 * Anton Strobl <a.strobl AT aws-it.at>
15 * The GNU PIC Library is maintained by
16 * Raphael Neider <rneider AT web.de>
18 * originally designed by
19 * Vangelis Rokas <vrokas AT otenet.gr>
25 #ifndef __PIC18F4620_H__
26 #define __PIC18F4620_H__ 1
28 extern __sfr __at (0xF80) PORTA;
95 extern volatile __PORTA_t __at (0xF80) PORTAbits;
97 extern __sfr __at (0xF81) PORTB;
138 extern volatile __PORTB_t __at (0xF81) PORTBbits;
140 extern __sfr __at (0xF82) PORTC;
174 unsigned DTC :1; /* DT might be a reserved word in ASM */
197 extern volatile __PORTC_t __at (0xF82) PORTCbits;
199 extern __sfr __at (0xF83) PORTD;
236 extern volatile __PORTD_t __at (0xF83) PORTDbits;
238 extern __sfr __at (0xF84) PORTE;
275 extern volatile __PORTE_t __at (0xF84) PORTEbits;
277 extern __sfr __at (0xF89) LATA;
290 extern volatile __LATA_t __at (0xF89) LATAbits;
292 extern __sfr __at (0xF8A) LATB;
305 extern volatile __LATB_t __at (0xF8A) LATBbits;
307 extern __sfr __at (0xF8B) LATC;
320 extern volatile __LATC_t __at (0xF8B) LATCbits;
322 extern __sfr __at (0xF8C) LATD;
335 extern volatile __LATD_t __at (0xF8C) LATDbits;
337 extern __sfr __at (0xF8D) LATE;
350 extern volatile __LATE_t __at (0xF8D) LATEbits;
352 extern __sfr __at (0xF92) TRISA;
365 extern volatile __TRISA_t __at (0xF92) TRISAbits;
367 extern __sfr __at (0xF93) TRISB;
380 extern volatile __TRISB_t __at (0xF93) TRISBbits;
382 extern __sfr __at (0xF94) TRISC;
395 extern volatile __TRISC_t __at (0xF94) TRISCbits;
397 extern __sfr __at (0xF95) TRISD;
410 extern volatile __TRISD_t __at (0xF95) TRISDbits;
412 extern __sfr __at (0xF96) TRISE;
419 unsigned PSPMODE : 1;
425 extern volatile __TRISE_t __at (0xF96) TRISEbits;
427 extern __sfr __at (0xF9B) OSCTUNE;
436 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
438 extern __sfr __at (0xF9D) PIE1;
451 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
453 extern __sfr __at (0xF9E) PIR1;
466 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
468 extern __sfr __at (0xF9F) IPR1;
481 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
483 extern __sfr __at (0xFA0) PIE2;
496 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
498 extern __sfr __at (0xFA1) PIR2;
511 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
513 extern __sfr __at (0xFA2) IPR2;
526 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
528 extern __sfr __at (0xFA6) EECON1;
541 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
543 extern __sfr __at (0xFA7) EECON2;
545 extern __sfr __at (0xFA8) EEDATA;
547 extern __sfr __at (0xFA9) EEADR;
549 extern __sfr __at (0xFAA) EEADRH;
551 extern __sfr __at (0xFAB) RCSTA;
564 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
566 extern __sfr __at (0xFAC) TXSTA;
579 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
581 extern __sfr __at (0xFAD) TXREG;
583 extern __sfr __at (0xFAE) RCREG;
585 extern __sfr __at (0xFAF) SPBRG;
587 extern __sfr __at (0xFB0) SPBRGH;
589 extern __sfr __at (0xFB1) T3CON;
594 unsigned NOT_T3SYNC : 1;
596 unsigned T3CKPS0 : 1;
597 unsigned T3CKPS1 : 1;
602 extern volatile __T3CON_t __at (0xFB1) T3CONbits;
604 extern __sfr __at (0xFB2) TMR3L;
606 extern __sfr __at (0xFB3) TMR3H;
608 extern __sfr __at (0xFB4) CMCON;
621 extern volatile __CMCON_t __at (0xFB4) CMCONbits;
623 extern __sfr __at (0xFB5) CVRCON;
636 extern volatile __CVRCON_t __at (0xFB5) CVRCONbits;
638 extern __sfr __at (0xFB6) ECCP1AS;
645 unsigned ECCPAS0 : 1;
646 unsigned ECCPAS1 : 1;
647 unsigned ECCPAS2 : 1;
648 unsigned ECCPASE : 1;
651 extern volatile __ECCP1AS_t __at (0xFB6) ECCP1ASbits;
653 extern __sfr __at (0xFB7) PWM1CON;
660 extern volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
662 extern __sfr __at (0xFB8) BAUDCON;
675 extern volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
677 extern __sfr __at (0xFBA) CCP2CON;
690 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
692 extern __sfr __at (0xFBB) CCPR2L;
694 extern __sfr __at (0xFBC) CCPR2H;
696 extern __sfr __at (0xFBD) CCP1CON;
709 extern volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
711 extern __sfr __at (0xFBE) CCPR1L;
713 extern __sfr __at (0xFBF) CCPR1H;
715 extern __sfr __at (0xFC0) ADCON2;
728 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
730 extern __sfr __at (0xFC1) ADCON1;
743 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
745 extern __sfr __at (0xFC2) ADCON0;
758 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
760 extern __sfr __at (0xFC3) ADRESL;
762 extern __sfr __at (0xFC4) ADRESH;
764 extern __sfr __at (0xFC5) SSPCON2;
773 unsigned ACKSTAT : 1;
777 extern volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
779 extern __sfr __at (0xFC6) SSPCON1;
792 extern volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
794 extern __sfr __at (0xFC7) SSPSTAT;
807 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
809 extern __sfr __at (0xFC8) SSPADD;
811 extern __sfr __at (0xFC9) SSPBUF;
813 extern __sfr __at (0xFCA) T2CON;
816 unsigned T2CKPS0 : 1;
817 unsigned T2CKPS1 : 1;
819 unsigned TOUTPS0 : 1;
820 unsigned TOUTPS1 : 1;
821 unsigned TOUTPS2 : 1;
822 unsigned TOUTPS3 : 1;
826 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
828 extern __sfr __at (0xFCB) PR2;
830 extern __sfr __at (0xFCC) TMR2;
832 extern __sfr __at (0xFCD) T1CON;
837 unsigned NOT_T1SYNC : 1;
838 unsigned T1OSCEN : 1;
839 unsigned T1CKPS0 : 1;
840 unsigned T1CKPS1 : 1;
845 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
847 extern __sfr __at (0xFCE) TMR1L;
849 extern __sfr __at (0xFCF) TMR1H;
851 extern __sfr __at (0xFD0) RCON;
864 extern volatile __RCON_t __at (0xFD0) RCONbits;
866 extern __sfr __at (0xFD1) WDTCON;
879 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
881 extern __sfr __at (0xFD2) HLVDCON;
891 unsigned VDIRMAG : 1;
894 extern volatile __HLVDCON_t __at (0xFD2) HLVDCONbits;
896 extern __sfr __at (0xFD3) OSCCON;
906 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
908 extern __sfr __at (0xFD5) T0CON;
921 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
923 extern __sfr __at (0xFD6) TMR0L;
925 extern __sfr __at (0xFD7) TMR0H;
927 extern __sfr __at (0xFD8) STATUS;
940 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
942 extern __sfr __at (0xFD9) FSR2L;
944 extern __sfr __at (0xFDA) FSR2H;
954 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
956 extern __sfr __at (0xFDB) PLUSW2;
958 extern __sfr __at (0xFDC) PREINC2;
960 extern __sfr __at (0xFDD) POSTDEC2;
962 extern __sfr __at (0xFDE) POSTINC2;
964 extern __sfr __at (0xFDF) INDF2;
966 extern __sfr __at (0xFE0) BSR;
976 extern volatile __BSR_t __at (0xFE0) BSRbits;
978 extern __sfr __at (0xFE1) FSR1L;
980 extern __sfr __at (0xFE2) FSR1H;
990 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
992 extern __sfr __at (0xFE3) PLUSW1;
994 extern __sfr __at (0xFE4) PREINC1;
996 extern __sfr __at (0xFE5) POSTDEC1;
998 extern __sfr __at (0xFE6) POSTINC1;
1000 extern __sfr __at (0xFE7) INDF1;
1002 extern __sfr __at (0xFE8) WREG;
1004 extern __sfr __at (0xFE9) FSR0L;
1006 extern __sfr __at (0xFEA) FSR0H;
1016 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
1018 extern __sfr __at (0xFEB) PLUSW0;
1020 extern __sfr __at (0xFEC) PREINC0;
1022 extern __sfr __at (0xFED) POSTDEC0;
1024 extern __sfr __at (0xFEE) POSTINC0;
1026 extern __sfr __at (0xFEF) INDF0;
1028 extern __sfr __at (0xFF0) INTCON3;
1031 unsigned INT1IF : 1;
1032 unsigned INT2IF : 1;
1034 unsigned INT1IE : 1;
1035 unsigned INT2IE : 1;
1037 unsigned INT1IP : 1;
1038 unsigned INT2IP : 1;
1041 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
1043 extern __sfr __at (0xFF1) INTCON2;
1048 unsigned TMR0IP : 1;
1050 unsigned INTEDG2 : 1;
1051 unsigned INTEDG1 : 1;
1052 unsigned INTEDG0 : 1;
1056 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
1058 extern __sfr __at (0xFF2) INTCON;
1062 unsigned INT0IF : 1;
1063 unsigned TMR0IF : 1;
1065 unsigned INT0IE : 1;
1066 unsigned TMR0IE : 1;
1081 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
1083 extern __sfr __at (0xFF3) PRODL;
1085 extern __sfr __at (0xFF4) PRODH;
1087 extern __sfr __at (0xFF5) TABLAT;
1089 extern __sfr __at (0xFF6) TBLPTRL;
1091 extern __sfr __at (0xFF7) TBLPTRH;
1093 extern __sfr __at (0xFF8) TBLPTRU;
1096 unsigned TBLPTRU : 5;
1102 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
1104 extern __sfr __at (0xFF9) PCL;
1106 extern __sfr __at (0xFFA) PCLATH;
1112 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
1114 extern __sfr __at (0xFFB) PCLATU;
1123 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1125 extern __sfr __at (0xFFC) STKPTR;
1128 unsigned STKPTR : 5;
1130 unsigned STKUNF : 1;
1131 unsigned STKFUL : 1;
1134 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1136 extern __sfr __at (0xFFD) TOSL;
1138 extern __sfr __at (0xFFE) TOSH;
1140 extern __sfr __at (0xFFF) TOSU;
1149 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1151 /* Configuration register locations */
1152 #define __CONFIG1H 0x300001
1153 #define __CONFIG2L 0x300002
1154 #define __CONFIG2H 0x300003
1155 #define __CONFIG3H 0x300005
1156 #define __CONFIG4L 0x300006
1157 #define __CONFIG5L 0x300008
1158 #define __CONFIG5H 0x300009
1159 #define __CONFIG6L 0x30000A
1160 #define __CONFIG6H 0x30000B
1161 #define __CONFIG7L 0x30000C
1162 #define __CONFIG7H 0x30000D
1165 /* Oscillator 1H options */
1166 #define _OSC_INTIO7_1H 0xF9 /* INTRC-OSC2 as Clock Out, OSC1 as RA7 */
1167 #define _OSC_INTIO67_1H 0xF8 /* INTRC-OSC2 as RA6, OSC1 as RA7 */
1168 #define _OSC_RCIO6_1H 0xF7 /* RC-OSC2 as RA6 */
1169 #define _OSC_HSPLL_1H 0xF6 /* HS-PLL Enabled */
1170 #define _OSC_ECIO6_1H 0xF5 /* EC-OSC2 as RA6 */
1171 #define _OSC_EC_1H 0xF4 /* EC-OSC2 as Clock Out */
1172 #define _OSC_RC_1H 0xF3 /* RC */
1173 #define _OSC_HS_1H 0xF2 /* HS */
1174 #define _OSC_XT_1H 0xF1 /* XT */
1175 #define _OSC_LP_1H 0xF0 /* LP */
1177 /* Fail-Safe Clock Monitor Enable 1H options */
1178 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1179 #define _FCMEN_ON_1H 0xFF /* Enabled */
1181 /* Internal External Switch Over Mode 1H options */
1182 #define _IESO_OFF_1H 0x7F /* Disabled */
1183 #define _IESO_ON_1H 0xFF /* Enabled */
1185 /* Power Up Timer 2L options */
1186 #define _PWRT_OFF_2L 0xFF /* Disabled */
1187 #define _PWRT_ON_2L 0xFE /* Enabled */
1189 /* Brown Out Detect 2L options */
1190 #define _BOREN_OFF_2L 0xF9 /* Disabled */
1191 #define _BOREN_ON_2L 0xFB /* SBOREN Enabled */
1192 #define _BOREN_NOSLP_2L 0xFD /* Enabled except SLEEP, SBOREN Disabled */
1193 #define _BOREN_SBORDIS_2L 0xFF /* Enabled, SBOREN Disabled */
1195 /* Brown Out Voltage 2L options */
1196 #define _BORV_46_2L 0xE7 /* 4.6V */
1197 #define _BORV_43_2L 0xEF /* 4.3V */
1198 #define _BORV_28_2L 0xF7 /* 2.8V */
1199 #define _BORV_21_2L 0xFF /* 2.1V */
1201 /* Watchdog Timer 2H options */
1202 #define _WDT_ON_2H 0xFF /* Enabled */
1203 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1205 /* Watchdog Postscaler 2H options */
1206 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1207 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1208 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1209 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1210 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1211 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1212 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1213 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1214 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1215 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1216 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1217 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1218 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1219 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1220 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1221 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1224 /* CCP2 Mux 3H options */
1225 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1226 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1228 /* PortB A/D Enable 3H options */
1229 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
1230 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
1232 /* Low Power Timer1 Osc enable 3H options */
1233 #define _LPT1OSC_ON_3H 0xFF /* Enabled */
1234 #define _LPT1OSC_OFF_3H 0xFB /* Disabled */
1236 /* Master Clear Enable 3H options */
1237 #define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
1238 #define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
1241 /* Stack Overflow Reset 4L options */
1242 #define _STVR_ON_4L 0xFF /* Enabled */
1243 #define _STVR_OFF_4L 0xFE /* Disabled */
1245 /* Low Voltage Program 4L options */
1246 #define _LVP_ON_4L 0xFF /* Enabled */
1247 #define _LVP_OFF_4L 0xFB /* Disabled */
1249 /* Extended CPU Enable 4L options */
1250 #define _XINST_OFF_4L 0xBF /* Disabled */
1251 #define _XINST_ON_4L 0xFF /* Enabled */
1253 /* Background Debug 4L options */
1254 #define _DEBUG_ON_4L 0x7F /* Enabled */
1255 #define _DEBUG_OFF_4L 0xFF /* Disabled */
1257 /* Code Protect 00800-01FFF 5L options */
1258 #define _CP_0_OFF_5L 0xFF /* Disabled */
1259 #define _CP_0_ON_5L 0xFE /* Enabled */
1261 /* Code Protect 02000-03FFF 5L options */
1262 #define _CP_1_OFF_5L 0xFF /* Disabled */
1263 #define _CP_1_ON_5L 0xFD /* Enabled */
1265 /* Code Protect 04000-05FFF 5L options */
1266 #define _CP_2_OFF_5L 0xFF /* Disabled */
1267 #define _CP_2_ON_5L 0xFB /* Enabled */
1269 /* Code Protect 06000-07FFF 5L options */
1270 #define _CP_3_OFF_5L 0xFF /* Disabled */
1271 #define _CP_3_ON_5L 0xF7 /* Enabled */
1274 /* Data EE Read Protect 5H options */
1275 #define _CPD_OFF_5H 0xFF /* Disabled */
1276 #define _CPD_ON_5H 0x7F /* Enabled */
1278 /* Code Protect Boot 5H options */
1279 #define _CPB_OFF_5H 0xFF /* Disabled */
1280 #define _CPB_ON_5H 0xBF /* Enabled */
1283 /* Table Write Protect 00800-01FFF 6L options */
1284 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1285 #define _WRT_0_ON_6L 0xFE /* Enabled */
1287 /* Table Write Protect 02000-03FFF 6L options */
1288 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1289 #define _WRT_1_ON_6L 0xFD /* Enabled */
1291 /* Table Write Protect 04000-05FFF 6L options */
1292 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1293 #define _WRT_2_ON_6L 0xFB /* Enabled */
1295 /* Table Write Protect 06000-07FFF 6L options */
1296 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1297 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1300 /* Data EE Write Protect 6H options */
1301 #define _WRTD_OFF_6H 0xFF /* Disabled */
1302 #define _WRTD_ON_6H 0x7F /* Enabled */
1304 /* Table Write Protect Boot 6H options */
1305 #define _WRTB_OFF_6H 0xFF /* Disabled */
1306 #define _WRTB_ON_6H 0xBF /* Enabled */
1308 /* Config. Write Protect 6H options */
1309 #define _WRTC_OFF_6H 0xFF /* Disabled */
1310 #define _WRTC_ON_6H 0xDF /* Enabled */
1313 /* Table Read Protect 00800-01FFF 7L options */
1314 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1315 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1317 /* Table Read Protect 02000-03FFF 7L options */
1318 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1319 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1321 /* Table Read Protect 04000-05FFF 7L options */
1322 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1323 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1325 /* Table Read Protect 06000-07FFF 7L options */
1326 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1327 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1330 /* Table Read Protect Boot 7H options */
1331 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1332 #define _EBTRB_ON_7H 0xBF /* Enabled */
1335 /* Device ID bytes */
1336 #define _DEVID1 0x3FFFFE
1337 #define _DEVID2 0x3FFFFF
1340 /* Location of User ID words */
1341 #define __IDLOC0 0x200000
1342 #define __IDLOC1 0x200001
1343 #define __IDLOC2 0x200002
1344 #define __IDLOC3 0x200003
1345 #define __IDLOC4 0x200004
1346 #define __IDLOC5 0x200005
1347 #define __IDLOC6 0x200006
1348 #define __IDLOC7 0x200007
1350 #endif // __PIC18F4620__