2 * pic18f4550.h - PIC18F4550 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * The GNU PIC Library is maintained by
8 * Raphael Neider <rneider AT web.de>
10 * originally designed by
11 * Vangelis Rokas <vrokas@otenet.gr>
17 #ifndef __PIC18F4550_H__
18 #define __PIC18F4550_H__ 1
20 extern __sfr __at (0xF62) SPPDATA;
26 extern volatile __SPPDATA_t __at (0xF62) SPPDATAbits;
28 extern __sfr __at (0xF63) SPPCFG;
37 extern volatile __SPPCFG_t __at (0xF63) SPPCFGbits;
39 extern __sfr __at (0xF64) SPPEPS;
49 extern volatile __SPPEPS_t __at (0xF64) SPPEPSbits;
51 extern __sfr __at (0xF65) SPPCON;
64 extern volatile __SPPCON_t __at (0xF65) SPPCONbits;
66 extern __sfr __at (0xF66) UFRML;
72 extern volatile __UFRML_t __at (0xF66) UFRMLbits;
74 extern __sfr __at (0xF67) UFRMH;
85 extern volatile __UFRMH_t __at (0xF67) UFRMHbits;
87 extern __sfr __at (0xF68) UIR;
100 extern volatile __UIR_t __at (0xF68) UIRbits;
102 extern __sfr __at (0xF69) UIE;
107 unsigned ACTIVIE : 1;
110 unsigned STALLIE : 1;
115 extern volatile __UIE_t __at (0xF69) UIEbits;
117 extern __sfr __at (0xF6A) UEIR;
122 unsigned CRC16EF : 1;
130 extern volatile __UEIR_t __at (0xF6A) UEIRbits;
132 extern __sfr __at (0xF6B) UEIE;
137 unsigned CRC16EE : 1;
145 extern volatile __UEIE_t __at (0xF6B) UEIEbits;
147 extern __sfr __at (0xF6C) USTAT;
157 extern volatile __USTAT_t __at (0xF6C) USTATbits;
159 extern __sfr __at (0xF6D) UCON;
172 extern volatile __UCON_t __at (0xF6D) UCONbits;
174 extern __sfr __at (0xF6E) UADDR;
181 extern volatile __UADDR_t __at (0xF6E) UADDRbits;
183 extern __sfr __at (0xF6F) UCFG;
195 extern volatile __UCFG_t __at (0xF6F) UCFGbits;
197 extern __sfr __at (0xF70) UEP0;
200 unsigned EPSTALL : 1;
202 unsigned EPOUTEN : 1;
203 unsigned EPCONDIS : 1;
210 extern volatile __UEP0_t __at (0xF70) UEP0bits;
212 extern __sfr __at (0xF71) UEP1;
215 unsigned EPSTALL : 1;
217 unsigned EPOUTEN : 1;
218 unsigned EPCONDIS : 1;
225 extern volatile __UEP1_t __at (0xF71) UEP1bits;
227 extern __sfr __at (0xF72) UEP2;
230 unsigned EPSTALL : 1;
232 unsigned EPOUTEN : 1;
233 unsigned EPCONDIS : 1;
240 extern volatile __UEP2_t __at (0xF72) UEP2bits;
242 extern __sfr __at (0xF73) UEP3;
245 unsigned EPSTALL : 1;
247 unsigned EPOUTEN : 1;
248 unsigned EPCONDIS : 1;
255 extern volatile __UEP3_t __at (0xF73) UEP3bits;
257 extern __sfr __at (0xF74) UEP4;
260 unsigned EPSTALL : 1;
262 unsigned EPOUTEN : 1;
263 unsigned EPCONDIS : 1;
270 extern volatile __UEP4_t __at (0xF74) UEP4bits;
272 extern __sfr __at (0xF75) UEP5;
275 unsigned EPSTALL : 1;
277 unsigned EPOUTEN : 1;
278 unsigned EPCONDIS : 1;
285 extern volatile __UEP5_t __at (0xF75) UEP5bits;
287 extern __sfr __at (0xF76) UEP6;
290 unsigned EPSTALL : 1;
292 unsigned EPOUTEN : 1;
293 unsigned EPCONDIS : 1;
300 extern volatile __UEP6_t __at (0xF76) UEP6bits;
302 extern __sfr __at (0xF77) UEP7;
305 unsigned EPSTALL : 1;
307 unsigned EPOUTEN : 1;
308 unsigned EPCONDIS : 1;
315 extern volatile __UEP7_t __at (0xF77) UEP7bits;
317 extern __sfr __at (0xF78) UEP8;
320 unsigned EPSTALL : 1;
322 unsigned EPOUTEN : 1;
323 unsigned EPCONDIS : 1;
330 extern volatile __UEP8_t __at (0xF78) UEP8bits;
332 extern __sfr __at (0xF79) UEP9;
335 unsigned EPSTALL : 1;
337 unsigned EPOUTEN : 1;
338 unsigned EPCONDIS : 1;
345 extern volatile __UEP9_t __at (0xF79) UEP9bits;
347 extern __sfr __at (0xF7A) UEP10;
350 unsigned EPSTALL : 1;
352 unsigned EPOUTEN : 1;
353 unsigned EPCONDIS : 1;
360 extern volatile __UEP10_t __at (0xF7A) UEP10bits;
362 extern __sfr __at (0xF7B) UEP11;
365 unsigned EPSTALL : 1;
367 unsigned EPOUTEN : 1;
368 unsigned EPCONDIS : 1;
375 extern volatile __UEP11_t __at (0xF7B) UEP11bits;
377 extern __sfr __at (0xF7C) UEP12;
380 unsigned EPSTALL : 1;
382 unsigned EPOUTEN : 1;
383 unsigned EPCONDIS : 1;
390 extern volatile __UEP12_t __at (0xF7C) UEP12bits;
392 extern __sfr __at (0xF7D) UEP13;
395 unsigned EPSTALL : 1;
397 unsigned EPOUTEN : 1;
398 unsigned EPCONDIS : 1;
405 extern volatile __UEP13_t __at (0xF7D) UEP13bits;
407 extern __sfr __at (0xF7E) UEP14;
410 unsigned EPSTALL : 1;
412 unsigned EPOUTEN : 1;
413 unsigned EPCONDIS : 1;
420 extern volatile __UEP14_t __at (0xF7E) UEP14bits;
422 extern __sfr __at (0xF7F) UEP15;
425 unsigned EPSTALL : 1;
427 unsigned EPOUTEN : 1;
428 unsigned EPCONDIS : 1;
435 extern volatile __UEP15_t __at (0xF7F) UEP15bits;
437 extern __sfr __at (0xF80) PORTA;
474 extern volatile __PORTA_t __at (0xF80) PORTAbits;
476 extern __sfr __at (0xF81) PORTB;
503 extern volatile __PORTB_t __at (0xF81) PORTBbits;
505 extern __sfr __at (0xF82) PORTC;
552 extern volatile __PORTC_t __at (0xF82) PORTCbits;
554 extern __sfr __at (0xF83) PORTD;
581 extern volatile __PORTD_t __at (0xF83) PORTDbits;
583 extern __sfr __at (0xF84) PORTE;
610 extern volatile __PORTE_t __at (0xF84) PORTEbits;
612 extern __sfr __at (0xF89) LATA;
625 extern volatile __LATA_t __at (0xF89) LATAbits;
627 extern __sfr __at (0xF8A) LATB;
640 extern volatile __LATB_t __at (0xF8A) LATBbits;
642 extern __sfr __at (0xF8B) LATC;
655 extern volatile __LATC_t __at (0xF8B) LATCbits;
657 extern __sfr __at (0xF92) TRISA;
670 extern volatile __TRISA_t __at (0xF92) TRISAbits;
672 extern __sfr __at (0xF93) TRISB;
685 extern volatile __TRISB_t __at (0xF93) TRISBbits;
687 extern __sfr __at (0xF94) TRISC;
700 extern volatile __TRISC_t __at (0xF94) TRISCbits;
702 extern __sfr __at (0xF95) TRISD;
715 extern volatile __TRISD_t __at (0xF95) TRISDbits;
717 extern __sfr __at (0xF9B) OSCTUNE;
723 unsigned HF256DIV : 1;
726 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
728 extern __sfr __at (0xF9D) PIE1;
741 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
743 extern __sfr __at (0xF9E) PIR1;
756 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
758 extern __sfr __at (0xF9F) IPR1;
771 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
773 extern __sfr __at (0xFA0) PIE2;
786 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
788 extern __sfr __at (0xFA1) PIR2;
801 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
803 extern __sfr __at (0xFA2) IPR2;
816 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
818 extern __sfr __at (0xFA6) EECON1;
831 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
833 extern __sfr __at (0xFA7) EECON2;
835 extern __sfr __at (0xFA8) EEDATA;
837 extern __sfr __at (0xFA9) EEADR;
839 extern __sfr __at (0xFAB) RCSTA;
852 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
854 extern __sfr __at (0xFAC) TXSTA;
867 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
869 extern __sfr __at (0xFAD) TXREG;
871 extern __sfr __at (0xFAE) RCREG;
873 extern __sfr __at (0xFAF) SPBRG;
875 extern __sfr __at (0xFB0) SPBRGH;
877 extern __sfr __at (0xFB1) T3CON;
882 unsigned NOT_T3SYNC : 1;
884 unsigned T3CKPS0 : 1;
885 unsigned T3CKPS1 : 1;
890 extern volatile __T3CON_t __at (0xFB1) T3CONbits;
892 extern __sfr __at (0xFB2) TMR3L;
894 extern __sfr __at (0xFB3) TMR3H;
896 extern __sfr __at (0xFB4) CMCON;
909 extern volatile __CMCON_t __at (0xFB4) CMCONbits;
911 extern __sfr __at (0xFB5) CVRCON;
924 extern volatile __CVRCON_t __at (0xFB5) CVRCONbits;
926 extern __sfr __at (0xFB6) ECCP1AS;
933 unsigned ECCPAS0 : 1;
934 unsigned ECCPAS1 : 1;
935 unsigned ECCPAS2 : 1;
936 unsigned ECCPASE : 1;
939 extern volatile __ECCP1AS_t __at (0xFB6) ECCP1ASbits;
941 extern __sfr __at (0xFB7) ECCP1DEL;
954 extern volatile __ECCP1DEL_t __at (0xFB7) ECCP1DELbits;
956 extern __sfr __at (0xFB8) BAUDCON;
969 extern volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
971 extern __sfr __at (0xFBA) CCP2CON;
984 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
986 extern __sfr __at (0xFBB) CCPR2L;
988 extern __sfr __at (0xFBC) CCPR2H;
990 extern __sfr __at (0xFBD) CCP1CON;
1003 extern volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
1005 extern __sfr __at (0xFBE) CCPR1L;
1007 extern __sfr __at (0xFBF) CCPR1H;
1009 extern __sfr __at (0xFC0) ADCON2;
1022 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
1024 extern __sfr __at (0xFC1) ADCON1;
1037 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
1039 extern __sfr __at (0xFC2) ADCON0;
1052 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
1054 extern __sfr __at (0xFC3) ADRESL;
1056 extern __sfr __at (0xFC4) ADRESH;
1058 extern __sfr __at (0xFC5) SSPCON2;
1067 unsigned ACKSTAT : 1;
1071 extern volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
1073 extern __sfr __at (0xFC6) SSPCON1;
1086 extern volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
1088 extern __sfr __at (0xFC7) SSPSTAT;
1101 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
1103 extern __sfr __at (0xFC8) SSPADD;
1105 extern __sfr __at (0xFC9) SSPBUF;
1107 extern __sfr __at (0xFCA) T2CON;
1110 unsigned T2CKPS0 : 1;
1111 unsigned T2CKPS1 : 1;
1112 unsigned TMR2ON : 1;
1113 unsigned TOUTPS0 : 1;
1114 unsigned TOUTPS1 : 1;
1115 unsigned TOUTPS2 : 1;
1116 unsigned TOUTPS3 : 1;
1120 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
1122 extern __sfr __at (0xFCB) PR2;
1124 extern __sfr __at (0xFCC) TMR2;
1126 extern __sfr __at (0xFCD) T1CON;
1129 unsigned TMR1ON : 1;
1130 unsigned TMR1CS : 1;
1131 unsigned NOT_T1SYNC : 1;
1132 unsigned T1OSCEN : 1;
1133 unsigned T1CKPS0 : 1;
1134 unsigned T1CKPS1 : 1;
1139 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
1141 extern __sfr __at (0xFCE) TMR1L;
1143 extern __sfr __at (0xFCF) TMR1H;
1145 extern __sfr __at (0xFD0) RCON;
1154 unsigned SBOREN : 1;
1158 extern volatile __RCON_t __at (0xFD0) RCONbits;
1160 extern __sfr __at (0xFD1) WDTCON;
1163 unsigned SWDTEN : 1;
1173 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
1175 extern __sfr __at (0xFD2) HLVDCON;
1178 unsigned HLVDL0 : 1;
1179 unsigned HLVDL1 : 1;
1180 unsigned HLVDL2 : 1;
1181 unsigned HLVDL3 : 1;
1182 unsigned HLVDEN : 1;
1185 unsigned VDIRMAG : 1;
1188 extern volatile __HLVDCON_t __at (0xFD2) HLVDCONbits;
1190 extern __sfr __at (0xFD3) OSCCON;
1200 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
1202 extern __sfr __at (0xFD5) T0CON;
1211 unsigned T08BIT : 1;
1212 unsigned TMR0ON : 1;
1215 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
1217 extern __sfr __at (0xFD6) TMR0L;
1219 extern __sfr __at (0xFD7) TMR0H;
1221 extern __sfr __at (0xFD8) STATUS;
1234 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
1236 extern __sfr __at (0xFD9) FSR2L;
1238 extern __sfr __at (0xFDA) FSR2H;
1248 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
1250 extern __sfr __at (0xFDB) PLUSW2;
1252 extern __sfr __at (0xFDC) PREINC2;
1254 extern __sfr __at (0xFDD) POSTDEC2;
1256 extern __sfr __at (0xFDE) POSTINC2;
1258 extern __sfr __at (0xFDF) INDF2;
1260 extern __sfr __at (0xFE0) BSR;
1270 extern volatile __BSR_t __at (0xFE0) BSRbits;
1272 extern __sfr __at (0xFE1) FSR1L;
1274 extern __sfr __at (0xFE2) FSR1H;
1284 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
1286 extern __sfr __at (0xFE3) PLUSW1;
1288 extern __sfr __at (0xFE4) PREINC1;
1290 extern __sfr __at (0xFE5) POSTDEC1;
1292 extern __sfr __at (0xFE6) POSTINC1;
1294 extern __sfr __at (0xFE7) INDF1;
1296 extern __sfr __at (0xFE8) WREG;
1298 extern __sfr __at (0xFE9) FSR0L;
1300 extern __sfr __at (0xFEA) FSR0H;
1310 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
1312 extern __sfr __at (0xFEB) PLUSW0;
1314 extern __sfr __at (0xFEC) PREINC0;
1316 extern __sfr __at (0xFED) POSTDEC0;
1318 extern __sfr __at (0xFEE) POSTINC0;
1320 extern __sfr __at (0xFEF) INDF0;
1322 extern __sfr __at (0xFF0) INTCON3;
1325 unsigned INT1IF : 1;
1326 unsigned INT2IF : 1;
1328 unsigned INT1IE : 1;
1329 unsigned INT2IE : 1;
1331 unsigned INT1IP : 1;
1332 unsigned INT2IP : 1;
1335 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
1337 extern __sfr __at (0xFF1) INTCON2;
1342 unsigned TMR0IP : 1;
1344 unsigned INTEDG2 : 1;
1345 unsigned INTEDG1 : 1;
1346 unsigned INTEDG0 : 1;
1350 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
1352 extern __sfr __at (0xFF2) INTCON;
1356 unsigned INT0IF : 1;
1357 unsigned TMR0IF : 1;
1359 unsigned INT0IE : 1;
1360 unsigned TMR0IE : 1;
1375 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
1377 extern __sfr __at (0xFF3) PRODL;
1379 extern __sfr __at (0xFF4) PRODH;
1381 extern __sfr __at (0xFF5) TABLAT;
1383 extern __sfr __at (0xFF6) TBLPTRL;
1385 extern __sfr __at (0xFF7) TBLPTRH;
1387 extern __sfr __at (0xFF8) TBLPTRU;
1390 unsigned TBLPTRU : 5;
1396 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
1398 extern __sfr __at (0xFF9) PCL;
1400 extern __sfr __at (0xFFA) PCLATH;
1406 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
1408 extern __sfr __at (0xFFB) PCLATU;
1417 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1419 extern __sfr __at (0xFFC) STKPTR;
1422 unsigned STKPTR : 5;
1424 unsigned STKUNF : 1;
1425 unsigned STKFUL : 1;
1428 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1430 extern __sfr __at (0xFFD) TOSL;
1432 extern __sfr __at (0xFFE) TOSH;
1434 extern __sfr __at (0xFFF) TOSU;
1443 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1445 /* Configuration register locations */
1446 #define __CONFIG1L 0x300000
1447 #define __CONFIG1H 0x300001
1448 #define __CONFIG2L 0x300002
1449 #define __CONFIG2H 0x300003
1450 #define __CONFIG3H 0x300005
1451 #define __CONFIG4L 0x300006
1452 #define __CONFIG5L 0x300008
1453 #define __CONFIG5H 0x300009
1454 #define __CONFIG6L 0x30000A
1455 #define __CONFIG6H 0x30000B
1456 #define __CONFIG7L 0x30000C
1457 #define __CONFIG7H 0x30000D
1460 /* Full-Speed USB Clock Source Selection 1L options */
1461 #define _USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2_1L 0xFF /* Clock src from 96MHz PLL/2 */
1462 #define _USBPLL_CLOCK_SRC_FROM_OSC1_OSC2_1L 0xDF /* Clock src from OSC1/OSC2 */
1464 /* CPU System Clock Postscaler 1L options */
1465 #define _CPUDIV__OSC1_OSC2_SRC___4__96MHZ_PLL_SRC___6__1L 0xFF /* [OSC1/OSC2 Src: /4][96MHz PLL Src: /6] */
1466 #define _CPUDIV__OSC1_OSC2_SRC___3__96MHZ_PLL_SRC___4__1L 0xF7 /* [OSC1/OSC2 Src: /3][96MHz PLL Src: /4] */
1467 #define _CPUDIV__OSC1_OSC2_SRC___2__96MHZ_PLL_SRC___3__1L 0xEF /* [OSC1/OSC2 Src: /2][96MHz PLL Src: /3] */
1468 #define _CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2__1L 0xE7 /* [OSC1/OSC2 Src: /1][96MHz PLL Src: /2] */
1470 /* 96MHz PLL Prescaler 1L options */
1471 #define _PLLDIV_DIVIDE_BY_12__48MHZ_INPUT__1L 0xFF /* Divide by 12 (48MHz input) */
1472 #define _PLLDIV_DIVIDE_BY_10__40MHZ_INPUT__1L 0xFE /* Divide by 10 (40MHz input) */
1473 #define _PLLDIV_DIVIDE_BY_6__24MHZ_INPUT__1L 0xFD /* Divide by 6 (24MHz input) */
1474 #define _PLLDIV_DIVIDE_BY_5__20MHZ_INPUT__1L 0xFC /* Divide by 5 (20MHz input) */
1475 #define _PLLDIV_DIVIDE_BY_4__16MHZ_INPUT__1L 0xFB /* Divide by 4 (16MHz input) */
1476 #define _PLLDIV_DIVIDE_BY_3__12MHZ_INPUT__1L 0xFA /* Divide by 3 (12MHz input) */
1477 #define _PLLDIV_DIVIDE_BY_2__8MHZ_INPUT__1L 0xF9 /* Divide by 2 (8MHz input) */
1478 #define _PLLDIV_NO_DIVIDE__4MHZ_INPUT__1L 0xF8 /* No Divide (4MHz input) */
1481 /* Oscillator 1H options */
1482 #define _OSC_HS__HS_PLL__USB_HS_1H 0xFE /* HS: HS+PLL, USB-HS */
1483 #define _OSC_HS__USB_HS_1H 0xFC /* HS: USB-HS */
1484 #define _OSC_INTOSC__USB_HS_1H 0xFB /* INTOSC: USB-HS */
1485 #define _OSC_INTOSC__USB_XT_1H 0xFA /* INTOSC: USB-XT */
1486 #define _OSC_INTOSC__INTOSC_CLK0_RA6___USB_EC_1H 0xF9 /* INTOSC: INTOSC+CLK0{RA6}, USB-EC */
1487 #define _OSC_INTOSC__INTOSC_RA6__USB_EC_1H 0xF8 /* INTOSC: INTOSC+RA6, USB-EC */
1488 #define _OSC_EC__EC_PLL__EC_PLL_CLKO_RA6___USB_EC_1H 0xF7 /* EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC */
1489 #define _OSC_EC__EC_PLL__EC_PLL_RA6__USB_EC_1H 0xF6 /* EC: EC+PLL, EC+PLL+RA6, USB-EC */
1490 #define _OSC_EC__EC_CLKO_RA6___USB_EC_1H 0xF5 /* EC: EC+CLKO{RA6}, USB-EC */
1491 #define _OSC_EC__EC_RA6__USB_EC_1H 0xF4 /* EC: EC+RA6, USB-EC */
1492 #define _OSC_XT__XT_PLL__USB_XT_1H 0xF2 /* XT: XT+PLL, USB-XT */
1493 #define _OSC_XT__USB_XT_1H 0xF0 /* XT: USB-XT */
1495 /* Fail-Safe Clock Monitor Enable 1H options */
1496 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1497 #define _FCMEN_ON_1H 0xFF /* Enabled */
1499 /* Internal External Switch Over Mode 1H options */
1500 #define _IESO_OFF_1H 0x7F /* Disabled */
1501 #define _IESO_ON_1H 0xFF /* Enabled */
1504 /* USB Voltage Regulator 2L options */
1505 #define _VREGEN_ON_2L 0xFF /* Enabled */
1506 #define _VREGEN_OFF_2L 0xDF /* Disabled */
1508 /* Power Up Timer 2L options */
1509 #define _PUT_OFF_2L 0xFF /* Disabled */
1510 #define _PUT_ON_2L 0xFE /* Enabled */
1512 /* Brown Out Detect 2L options */
1513 #define _BODEN_ON_2L 0xFF /* Enabled in hardware, SBOREN disabled */
1514 #define _BODEN_ON_WHILE_ACTIVE_2L 0xFD /* Enabled while active,disabled in SLEEP,SBOREN disabled */
1515 #define _BODEN_CONTROLLED_WITH_SBOREN_BIT_2L 0xFB /* Controlled with SBOREN bit */
1516 #define _BODEN_OFF_2L 0xF9 /* Disabled in hardware, SBOREN disabled */
1518 /* Brown Out Voltage 2L options */
1519 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
1520 #define _BODENV_2_7V_2L 0xF7 /* 2.7V */
1521 #define _BODENV_4_2V_2L 0xEF /* 4.2V */
1522 #define _BODENV_4_5V_2L 0xE7 /* 4.5V */
1525 /* Watchdog Timer 2H options */
1526 #define _WDT_ON_2H 0xFF /* Enabled */
1527 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1529 /* Watchdog Postscaler 2H options */
1530 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1531 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1532 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1533 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1534 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1535 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1536 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1537 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1538 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1539 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1540 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1541 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1542 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1543 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1544 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1545 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1548 /* CCP2 Mux 3H options */
1549 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1550 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1552 /* PortB A/D Enable 3H options */
1553 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
1554 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
1556 /* Low Power Timer1 Osc enable 3H options */
1557 #define _LPT1OSC_ON_3H 0xFF /* Enabled */
1558 #define _LPT1OSC_OFF_3H 0xFB /* Disabled */
1560 /* Master Clear Enable 3H options */
1561 #define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
1562 #define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
1565 /* Stack Overflow Reset 4L options */
1566 #define _STVR_ON_4L 0xFF /* Enabled */
1567 #define _STVR_OFF_4L 0xFE /* Disabled */
1569 /* Low Voltage Program 4L options */
1570 #define _LVP_ON_4L 0xFF /* Enabled */
1571 #define _LVP_OFF_4L 0xFB /* Disabled */
1573 /* Dedicated In-Circuit Port {ICD/ICSP} 4L options */
1574 #define _ENICPORT_OFF_4L 0xDF /* Disabled */
1576 /* Extended CPU Enable 4L options */
1577 #define _ENHCPU_ON_4L 0xFF /* Enabled */
1578 #define _ENHCPU_OFF_4L 0xBF /* Disabled */
1580 /* Background Debug 4L options */
1581 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1582 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1585 /* Code Protect 00800-01FFF 5L options */
1586 #define _CP_0_OFF_5L 0xFF /* Disabled */
1587 #define _CP_0_ON_5L 0xFE /* Enabled */
1589 /* Code Protect 02000-03FFF 5L options */
1590 #define _CP_1_OFF_5L 0xFF /* Disabled */
1591 #define _CP_1_ON_5L 0xFD /* Enabled */
1593 /* Code Protect 04000-05FFF 5L options */
1594 #define _CP_2_OFF_5L 0xFF /* Disabled */
1595 #define _CP_2_ON_5L 0xFB /* Enabled */
1597 /* Code Protect 06000-07FFF 5L options */
1598 #define _CP_3_OFF_5L 0xFF /* Disabled */
1599 #define _CP_3_ON_5L 0xF7 /* Enabled */
1602 /* Data EE Read Protect 5H options */
1603 #define _CPD_OFF_5H 0xFF /* Disabled */
1604 #define _CPD_ON_5H 0x7F /* Enabled */
1606 /* Code Protect Boot 5H options */
1607 #define _CPB_OFF_5H 0xFF /* Disabled */
1608 #define _CPB_ON_5H 0xBF /* Enabled */
1611 /* Table Write Protect 00800-01FFF 6L options */
1612 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1613 #define _WRT_0_ON_6L 0xFE /* Enabled */
1615 /* Table Write Protect 02000-03FFF 6L options */
1616 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1617 #define _WRT_1_ON_6L 0xFD /* Enabled */
1619 /* Table Write Protect 04000-05FFF 6L options */
1620 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1621 #define _WRT_2_ON_6L 0xFB /* Enabled */
1623 /* Table Write Protect 06000-07FFF 6L options */
1624 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1625 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1628 /* Data EE Write Protect 6H options */
1629 #define _WRTD_OFF_6H 0xFF /* Disabled */
1630 #define _WRTD_ON_6H 0x7F /* Enabled */
1632 /* Table Write Protect Boot 6H options */
1633 #define _WRTB_OFF_6H 0xFF /* Disabled */
1634 #define _WRTB_ON_6H 0xBF /* Enabled */
1636 /* Config. Write Protect 6H options */
1637 #define _WRTC_OFF_6H 0xFF /* Disabled */
1638 #define _WRTC_ON_6H 0xDF /* Enabled */
1641 /* Table Read Protect 00800-01FFF 7L options */
1642 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1643 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1645 /* Table Read Protect 02000-03FFF 7L options */
1646 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1647 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1649 /* Table Read Protect 04000-05FFF 7L options */
1650 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1651 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1653 /* Table Read Protect 06000-07FFF 7L options */
1654 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1655 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1658 /* Table Read Protect Boot 7H options */
1659 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1660 #define _EBTRB_ON_7H 0xBF /* Enabled */
1664 /* Location of User ID words */
1665 #define __IDLOC0 0x200000
1666 #define __IDLOC1 0x200001
1667 #define __IDLOC2 0x200002
1668 #define __IDLOC3 0x200003
1669 #define __IDLOC4 0x200004
1670 #define __IDLOC5 0x200005
1671 #define __IDLOC6 0x200006
1672 #define __IDLOC7 0x200007
1674 #endif // __PIC18F4550__