2 * pic18f4520.h - PIC18F4520 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * The GNU PIC Library is maintained by
8 * Raphael Neider <rneider AT web.de>
10 * originally designed by
11 * Vangelis Rokas <vrokas@otenet.gr>
17 #ifndef __PIC18F4520_H__
18 #define __PIC18F4520_H__ 1
20 extern __sfr __at (0xF80) PORTA;
57 extern volatile __PORTA_t __at (0xF80) PORTAbits;
59 extern __sfr __at (0xF81) PORTB;
86 extern volatile __PORTB_t __at (0xF81) PORTBbits;
88 extern __sfr __at (0xF82) PORTC;
135 extern volatile __PORTC_t __at (0xF82) PORTCbits;
137 extern __sfr __at (0xF83) PORTD;
164 extern volatile __PORTD_t __at (0xF83) PORTDbits;
166 extern __sfr __at (0xF84) PORTE;
193 extern volatile __PORTE_t __at (0xF84) PORTEbits;
195 extern __sfr __at (0xF89) LATA;
208 extern volatile __LATA_t __at (0xF89) LATAbits;
210 extern __sfr __at (0xF8A) LATB;
223 extern volatile __LATB_t __at (0xF8A) LATBbits;
225 extern __sfr __at (0xF8B) LATC;
238 extern volatile __LATC_t __at (0xF8B) LATCbits;
240 extern __sfr __at (0xF8C) LATD;
253 extern volatile __LATD_t __at (0xF8C) LATDbits;
255 extern __sfr __at (0xF8D) LATE;
268 extern volatile __LATE_t __at (0xF8D) LATEbits;
270 extern __sfr __at (0xF92) TRISA;
283 extern volatile __TRISA_t __at (0xF92) TRISAbits;
285 extern __sfr __at (0xF93) TRISB;
298 extern volatile __TRISB_t __at (0xF93) TRISBbits;
300 extern __sfr __at (0xF94) TRISC;
313 extern volatile __TRISC_t __at (0xF94) TRISCbits;
315 extern __sfr __at (0xF95) TRISD;
328 extern volatile __TRISD_t __at (0xF95) TRISDbits;
330 extern __sfr __at (0xF96) TRISE;
337 unsigned PSPMODE : 1;
343 extern volatile __TRISE_t __at (0xF96) TRISEbits;
345 extern __sfr __at (0xF9B) OSCTUNE;
351 unsigned HF256DIV : 1;
354 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
356 extern __sfr __at (0xF9D) PIE1;
369 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
371 extern __sfr __at (0xF9E) PIR1;
384 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
386 extern __sfr __at (0xF9F) IPR1;
399 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
401 extern __sfr __at (0xFA0) PIE2;
414 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
416 extern __sfr __at (0xFA1) PIR2;
429 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
431 extern __sfr __at (0xFA2) IPR2;
444 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
446 extern __sfr __at (0xFA6) EECON1;
459 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
461 extern __sfr __at (0xFA7) EECON2;
463 extern __sfr __at (0xFA8) EEDATA;
465 extern __sfr __at (0xFA9) EEADR;
467 extern __sfr __at (0xFAB) RCSTA;
480 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
482 extern __sfr __at (0xFAC) TXSTA;
495 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
497 extern __sfr __at (0xFAD) TXREG;
499 extern __sfr __at (0xFAE) RCREG;
501 extern __sfr __at (0xFAF) SPBRG;
503 extern __sfr __at (0xFB0) SPBRGH;
505 extern __sfr __at (0xFB1) T3CON;
510 unsigned NOT_T3SYNC : 1;
512 unsigned T3CKPS0 : 1;
513 unsigned T3CKPS1 : 1;
518 extern volatile __T3CON_t __at (0xFB1) T3CONbits;
520 extern __sfr __at (0xFB2) TMR3L;
522 extern __sfr __at (0xFB3) TMR3H;
524 extern __sfr __at (0xFB4) CMCON;
537 extern volatile __CMCON_t __at (0xFB4) CMCONbits;
539 extern __sfr __at (0xFB5) CVRCON;
552 extern volatile __CVRCON_t __at (0xFB5) CVRCONbits;
554 extern __sfr __at (0xFB6) ECCPAS1;
561 unsigned ECCPAS0 : 1;
562 unsigned ECCPAS1 : 1;
563 unsigned ECCPAS2 : 1;
564 unsigned ECCPASE : 1;
567 extern volatile __ECCPAS1_t __at (0xFB6) ECCPAS1bits;
569 extern __sfr __at (0xFB7) PWM1CON;
576 extern volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
578 extern __sfr __at (0xFB8) BAUDCON;
591 extern volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
593 extern __sfr __at (0xFBA) CCP2CON;
606 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
608 extern __sfr __at (0xFBB) CCPR2L;
610 extern __sfr __at (0xFBC) CCPR2H;
612 extern __sfr __at (0xFBD) ECCP1CON;
625 extern volatile __ECCP1CON_t __at (0xFBD) ECCP1CONbits;
627 extern __sfr __at (0xFBE) CCPR1L;
629 extern __sfr __at (0xFBF) CCPR1H;
631 extern __sfr __at (0xFC0) ADCON2;
644 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
646 extern __sfr __at (0xFC1) ADCON1;
659 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
661 extern __sfr __at (0xFC2) ADCON0;
674 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
676 extern __sfr __at (0xFC3) ADRESL;
678 extern __sfr __at (0xFC4) ADRESH;
680 extern __sfr __at (0xFC5) SSPCON2;
689 unsigned ACKSTAT : 1;
693 extern volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
695 extern __sfr __at (0xFC6) SSPCON1;
708 extern volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
710 extern __sfr __at (0xFC7) SSPSTAT;
723 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
725 extern __sfr __at (0xFC8) SSPADD;
727 extern __sfr __at (0xFC9) SSPBUF;
729 extern __sfr __at (0xFCA) T2CON;
732 unsigned T2CKPS0 : 1;
733 unsigned T2CKPS1 : 1;
735 unsigned TOUTPS0 : 1;
736 unsigned TOUTPS1 : 1;
737 unsigned TOUTPS2 : 1;
738 unsigned TOUTPS3 : 1;
742 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
744 extern __sfr __at (0xFCB) PR2;
746 extern __sfr __at (0xFCC) TMR2;
748 extern __sfr __at (0xFCD) T1CON;
753 unsigned NOT_T1SYNC : 1;
754 unsigned T1OSCEN : 1;
755 unsigned T1CKPS0 : 1;
756 unsigned T1CKPS1 : 1;
761 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
763 extern __sfr __at (0xFCE) TMR1L;
765 extern __sfr __at (0xFCF) TMR1H;
767 extern __sfr __at (0xFD0) RCON;
780 extern volatile __RCON_t __at (0xFD0) RCONbits;
782 extern __sfr __at (0xFD1) WDTCON;
795 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
797 extern __sfr __at (0xFD2) LVDCON;
810 extern volatile __LVDCON_t __at (0xFD2) LVDCONbits;
812 extern __sfr __at (0xFD3) OSCCON;
822 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
824 extern __sfr __at (0xFD5) T0CON;
837 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
839 extern __sfr __at (0xFD6) TMR0L;
841 extern __sfr __at (0xFD7) TMR0H;
843 extern __sfr __at (0xFD8) STATUS;
856 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
858 extern __sfr __at (0xFD9) FSR2L;
860 extern __sfr __at (0xFDA) FSR2H;
870 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
872 extern __sfr __at (0xFDB) PLUSW2;
874 extern __sfr __at (0xFDC) PREINC2;
876 extern __sfr __at (0xFDD) POSTDEC2;
878 extern __sfr __at (0xFDE) POSTINC2;
880 extern __sfr __at (0xFDF) INDF2;
882 extern __sfr __at (0xFE0) BSR;
892 extern volatile __BSR_t __at (0xFE0) BSRbits;
894 extern __sfr __at (0xFE1) FSR1L;
896 extern __sfr __at (0xFE2) FSR1H;
906 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
908 extern __sfr __at (0xFE3) PLUSW1;
910 extern __sfr __at (0xFE4) PREINC1;
912 extern __sfr __at (0xFE5) POSTDEC1;
914 extern __sfr __at (0xFE6) POSTINC1;
916 extern __sfr __at (0xFE7) INDF1;
918 extern __sfr __at (0xFE8) WREG;
920 extern __sfr __at (0xFE9) FSR0L;
922 extern __sfr __at (0xFEA) FSR0H;
932 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
934 extern __sfr __at (0xFEB) PLUSW0;
936 extern __sfr __at (0xFEC) PREINC0;
938 extern __sfr __at (0xFED) POSTDEC0;
940 extern __sfr __at (0xFEE) POSTINC0;
942 extern __sfr __at (0xFEF) INDF0;
944 extern __sfr __at (0xFF0) INTCON3;
957 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
959 extern __sfr __at (0xFF1) INTCON2;
966 unsigned INTEDG2 : 1;
967 unsigned INTEDG1 : 1;
968 unsigned INTEDG0 : 1;
972 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
974 extern __sfr __at (0xFF2) INTCON;
997 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
999 extern __sfr __at (0xFF3) PRODL;
1001 extern __sfr __at (0xFF4) PRODH;
1003 extern __sfr __at (0xFF5) TABLAT;
1005 extern __sfr __at (0xFF6) TBLPTRL;
1007 extern __sfr __at (0xFF7) TBLPTRH;
1009 extern __sfr __at (0xFF8) TBLPTRU;
1012 unsigned TBLPTRU : 5;
1018 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
1020 extern __sfr __at (0xFF9) PCL;
1022 extern __sfr __at (0xFFA) PCLATH;
1028 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
1030 extern __sfr __at (0xFFB) PCLATU;
1039 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1041 extern __sfr __at (0xFFC) STKPTR;
1044 unsigned STKPTR : 5;
1046 unsigned STKUNF : 1;
1047 unsigned STKFUL : 1;
1050 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1052 extern __sfr __at (0xFFD) TOSL;
1054 extern __sfr __at (0xFFE) TOSH;
1056 extern __sfr __at (0xFFF) TOSU;
1065 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1067 /* Configuration register locations */
1068 #define __CONFIG1H 0x300001
1069 #define __CONFIG2L 0x300002
1070 #define __CONFIG2H 0x300003
1071 #define __CONFIG3H 0x300005
1072 #define __CONFIG4L 0x300006
1073 #define __CONFIG5L 0x300008
1074 #define __CONFIG5H 0x300009
1075 #define __CONFIG6L 0x30000A
1076 #define __CONFIG6H 0x30000B
1077 #define __CONFIG7L 0x30000C
1078 #define __CONFIG7H 0x30000D
1081 /* Oscillator 1H options */
1082 #define _OSC_11XX_EXT_RC_CLKOUT_ON_RA6_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
1083 #define _OSC_101X_EXT_RC_CLKOUT_ON_RA6_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
1084 #define _OSC_INT_RC_CLKOUT_ON_RA6_PORT_ON_RA7_1H 0xF9 /* INT RC-CLKOUT on RA6,Port on RA7 */
1085 #define _OSC_INT_RC_PORT_ON_RA6_PORT_ON_RA7_1H 0xF8 /* INT RC-Port on RA6,Port on RA7 */
1086 #define _OSC_EXT_RC_PORT_ON_RA6_1H 0xF7 /* EXT RC-Port on RA6 */
1087 #define _OSC_HS_PLL_ON_FREQ_4XFOSC1_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
1088 #define _OSC_EC_PORT_ON_RA6_1H 0xF5 /* EC-Port on RA6 */
1089 #define _OSC_EC_CLKOUT_ON_RA6_1H 0xF4 /* EC-CLKOUT on RA6 */
1090 #define _OSC_0011_EXT_RC_CLKOUT_ON_RA6_1H 0xF3 /* 0011 EXT RC-CLKOUT on RA6 */
1091 #define _OSC_HS_1H 0xF2 /* HS */
1092 #define _OSC_XT_1H 0xF1 /* XT */
1093 #define _OSC_LP_1H 0xF0 /* LP */
1095 /* Fail-Safe Clock Monitor Enable 1H options */
1096 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1097 #define _FCMEN_ON_1H 0xFF /* Enabled */
1099 /* Internal External Switch Over Mode 1H options */
1100 #define _IESO_OFF_1H 0x7F /* Disabled */
1101 #define _IESO_ON_1H 0xFF /* Enabled */
1104 /* Power Up Timer 2L options */
1105 #define _PUT_OFF_2L 0xFF /* Disabled */
1106 #define _PUT_ON_2L 0xFE /* Enabled */
1108 /* Brown Out Detect 2L options */
1109 #define _BODEN_ON_2L 0xFF /* Enabled in hardware, SBOREN disabled */
1110 #define _BODEN_ON_WHILE_ACTIVE_2L 0xFD /* Enabled while active,disabled in SLEEP,SBOREN disabled */
1111 #define _BODEN_CONTROLLED_WITH_SBOREN_BIT_2L 0xFB /* Controlled with SBOREN bit */
1112 #define _BODEN_OFF_2L 0xF9 /* Disabled in hardware, SBOREN disabled */
1114 /* Brown Out Voltage 2L options */
1115 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
1116 #define _BODENV_2_7V_2L 0xF7 /* 2.7V */
1117 #define _BODENV_4_2V_2L 0xEF /* 4.2V */
1118 #define _BODENV_4_5V_2L 0xE7 /* 4.5V */
1121 /* Watchdog Timer 2H options */
1122 #define _WDT_ON_2H 0xFF /* Enabled */
1123 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1125 /* Watchdog Postscaler 2H options */
1126 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1127 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1128 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1129 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1130 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1131 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1132 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1133 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1134 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1135 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1136 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1137 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1138 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1139 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1140 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1141 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1144 /* CCP2 Mux 3H options */
1145 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1146 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1148 /* PortB A/D Enable 3H options */
1149 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
1150 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
1152 /* Low Power Timer1 Osc enable 3H options */
1153 #define _LPT1OSC_ON_3H 0xFF /* Enabled */
1154 #define _LPT1OSC_OFF_3H 0xFB /* Disabled */
1156 /* Master Clear Enable 3H options */
1157 #define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
1158 #define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
1161 /* Stack Overflow Reset 4L options */
1162 #define _STVR_ON_4L 0xFF /* Enabled */
1163 #define _STVR_OFF_4L 0xFE /* Disabled */
1165 /* Low Voltage Program 4L options */
1166 #define _LVP_ON_4L 0xFF /* Enabled */
1167 #define _LVP_OFF_4L 0xFB /* Disabled */
1169 /* Extended CPU Enable 4L options */
1170 #define _ENHCPU_ON_4L 0xFF /* Enabled */
1171 #define _ENHCPU_OFF_4L 0xBF /* Disabled */
1173 /* Background Debug 4L options */
1174 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1175 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1178 /* Code Protect 00800-01FFF 5L options */
1179 #define _CP_0_OFF_5L 0xFF /* Disabled */
1180 #define _CP_0_ON_5L 0xFE /* Enabled */
1182 /* Code Protect 02000-03FFF 5L options */
1183 #define _CP_1_OFF_5L 0xFF /* Disabled */
1184 #define _CP_1_ON_5L 0xFD /* Enabled */
1186 /* Code Protect 04000-05FFF 5L options */
1187 #define _CP_2_OFF_5L 0xFF /* Disabled */
1188 #define _CP_2_ON_5L 0xFB /* Enabled */
1190 /* Code Protect 06000-07FFF 5L options */
1191 #define _CP_3_OFF_5L 0xFF /* Disabled */
1192 #define _CP_3_ON_5L 0xF7 /* Enabled */
1195 /* Data EEPROM Code Protect 5H options */
1196 #define _CPD_OFF_5H 0xFF /* Disabled */
1197 #define _CPD_ON_5H 0x7F /* Enabled */
1199 /* Code Protect Boot 5H options */
1200 #define _CPB_OFF_5H 0xFF /* Disabled */
1201 #define _CPB_ON_5H 0xBF /* Enabled */
1204 /* Table Write Protect 00800-01FFF 6L options */
1205 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1206 #define _WRT_0_ON_6L 0xFE /* Enabled */
1208 /* Table Write Protect 02000-03FFF 6L options */
1209 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1210 #define _WRT_1_ON_6L 0xFD /* Enabled */
1212 /* Table Write Protect 04000-05FFF 6L options */
1213 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1214 #define _WRT_2_ON_6L 0xFB /* Enabled */
1216 /* Table Write Protect 06000-07FFF 6L options */
1217 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1218 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1221 /* Data EEPROM Write Protect 6H options */
1222 #define _WRTD_OFF_6H 0xFF /* Disabled */
1223 #define _WRTD_ON_6H 0x7F /* Enabled */
1225 /* Table Write Protect Boot 6H options */
1226 #define _WRTB_OFF_6H 0xFF /* Disabled */
1227 #define _WRTB_ON_6H 0xBF /* Enabled */
1229 /* Config. Write Protect 6H options */
1230 #define _WRTC_OFF_6H 0xFF /* Disabled */
1231 #define _WRTC_ON_6H 0xDF /* Enabled */
1234 /* Table Read Protect 00800-01FFF 7L options */
1235 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1236 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1238 /* Table Read Protect 02000-03FFF 7L options */
1239 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1240 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1242 /* Table Read Protect 04000-05FFF 7L options */
1243 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1244 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1246 /* Table Read Protect 06000-07FFF 7L options */
1247 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1248 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1251 /* Table Read Protect Boot 7H options */
1252 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1253 #define _EBTRB_ON_7H 0xBF /* Enabled */
1257 /* Location of User ID words */
1258 #define __IDLOC0 0x200000
1259 #define __IDLOC1 0x200001
1260 #define __IDLOC2 0x200002
1261 #define __IDLOC3 0x200003
1262 #define __IDLOC4 0x200004
1263 #define __IDLOC5 0x200005
1264 #define __IDLOC6 0x200006
1265 #define __IDLOC7 0x200007
1267 #endif // __PIC18F4520__