2 * pic18f4520.h - device specific declarations
4 * This file is part of the GNU PIC library for SDCC,
5 * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
7 * It has been automatically generated by inc2h-pic16.pl,
8 * (c) 2007 by Raphael Neider <rneider AT web.de>
11 #ifndef __PIC18F4520_H__
12 #define __PIC18F4520_H__ 1
17 #define __CONFIG1H 0x300001
18 #define __CONFIG2L 0x300002
19 #define __CONFIG2H 0x300003
20 #define __CONFIG3H 0x300005
21 #define __CONFIG4L 0x300006
22 #define __CONFIG5L 0x300008
23 #define __CONFIG5H 0x300009
24 #define __CONFIG6L 0x30000A
25 #define __CONFIG6H 0x30000B
26 #define __CONFIG7L 0x30000C
27 #define __CONFIG7H 0x30000D
30 #define _OSC_LP_1H 0xF0 // LP oscillator
31 #define _OSC_XT_1H 0xF1 // XT oscillator
32 #define _OSC_HS_1H 0xF2 // HS oscillator
33 #define _OSC_RC_1H 0xF3 // External RC oscillator, CLKO function on RA6
34 #define _OSC_EC_1H 0xF4 // EC oscillator, CLKO function on RA6
35 #define _OSC_ECIO6_1H 0xF5 // EC oscillator, port function on RA6
36 #define _OSC_HSPLL_1H 0xF6 // HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
37 #define _OSC_RCIO6_1H 0xF7 // External RC oscillator, port function on RA6
38 #define _OSC_INTIO67_1H 0xF8 // Internal oscillator block, port function on RA6 and RA7
39 #define _OSC_INTIO7_1H 0xF9 // Internal oscillator block, CLKO function on RA6, port function on RA7
40 #define _FCMEN_OFF_1H 0xBF // Fail-Safe Clock Monitor disabled
41 #define _FCMEN_ON_1H 0xFF // Fail-Safe Clock Monitor enabled
42 #define _IESO_OFF_1H 0x7F // Oscillator Switchover mode disabled
43 #define _IESO_ON_1H 0xFF // Oscillator Switchover mode enabled
46 #define _PWRT_ON_2L 0xFE // PWRT enabled
47 #define _PWRT_OFF_2L 0xFF // PWRT disabled
48 #define _BOREN_OFF_2L 0xF9 // Brown-out Reset disabled in hardware and software
49 #define _BOREN_ON_2L 0xFB // Brown-out Reset enabled and controlled by software (SBOREN is enabled)
50 #define _BOREN_NOSLP_2L 0xFD // Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
51 #define _BOREN_SBORDIS_2L 0xFF // Brown-out Reset enabled in hardware only (SBOREN is disabled)
52 #define _BORV_0_2L 0xE7 // Maximum setting
53 #define _BORV_1_2L 0xEF //
54 #define _BORV_2_2L 0xF7 //
55 #define _BORV_3_2L 0xFF // Minimum setting
58 #define _WDT_OFF_2H 0xFE // WDT disabled (control is placed on the SWDTEN bit)
59 #define _WDT_ON_2H 0xFF // WDT enabled
60 #define _WDTPS_1_2H 0xE1 // 1:1
61 #define _WDTPS_2_2H 0xE3 // 1:2
62 #define _WDTPS_4_2H 0xE5 // 1:4
63 #define _WDTPS_8_2H 0xE7 // 1:8
64 #define _WDTPS_16_2H 0xE9 // 1:16
65 #define _WDTPS_32_2H 0xEB // 1:32
66 #define _WDTPS_64_2H 0xED // 1:64
67 #define _WDTPS_128_2H 0xEF // 1:128
68 #define _WDTPS_256_2H 0xF1 // 1:256
69 #define _WDTPS_512_2H 0xF3 // 1:512
70 #define _WDTPS_1024_2H 0xF5 // 1:1024
71 #define _WDTPS_2048_2H 0xF7 // 1:2048
72 #define _WDTPS_4096_2H 0xF9 // 1:4096
73 #define _WDTPS_8192_2H 0xFB // 1:8192
74 #define _WDTPS_16384_2H 0xFD // 1:16384
75 #define _WDTPS_32768_2H 0xFF // 1:32768
78 #define _MCLRE_OFF_3H 0x7F // RE3 input pin enabled; MCLR disabled
79 #define _MCLRE_ON_3H 0xFF // MCLR pin enabled; RE3 input pin disabled
80 #define _LPT1OSC_OFF_3H 0xFB // Timer1 configured for higher power operation
81 #define _LPT1OSC_ON_3H 0xFF // Timer1 configured for low-power operation
82 #define _PBADEN_OFF_3H 0xFD // PORTB<4:0> pins are configured as digital I/O on Reset
83 #define _PBADEN_ON_3H 0xFF // PORTB<4:0> pins are configured as analog input channels on Reset
84 #define _CCP2MX_PORTBE_3H 0xFE // CCP2 input/output is multiplexed with RB3
85 #define _CCP2MX_PORTC_3H 0xFF // CCP2 input/output is multiplexed with RC1
88 #define _STVREN_OFF_4L 0xFE // Stack full/underflow will not cause Reset
89 #define _STVREN_ON_4L 0xFF // Stack full/underflow will cause Reset
90 #define _LVP_OFF_4L 0xFB // Single-Supply ICSP disabled
91 #define _LVP_ON_4L 0xFF // Single-Supply ICSP enabled
92 #define _XINST_OFF_4L 0xBF // Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
93 #define _XINST_ON_4L 0xFF // Instruction set extension and Indexed Addressing mode enabled
94 #define _DEBUG_ON_4L 0x7F // Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
95 #define _DEBUG_OFF_4L 0xFF // Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
98 #define _CP0_ON_5L 0xFE // Block 0 (000800-001FFFh) code-protected
99 #define _CP0_OFF_5L 0xFF // Block 0 (000800-001FFFh) not code-protected
100 #define _CP1_ON_5L 0xFD // Block 1 (002000-003FFFh) code-protected
101 #define _CP1_OFF_5L 0xFF // Block 1 (002000-003FFFh) not code-protected
102 #define _CP2_ON_5L 0xFB // Block 2 (004000-005FFFh) code-protected
103 #define _CP2_OFF_5L 0xFF // Block 2 (004000-005FFFh) not code-protected
104 #define _CP3_ON_5L 0xF7 // Block 3 (006000-007FFFh) code-protected
105 #define _CP3_OFF_5L 0xFF // Block 3 (006000-007FFFh) not code-protected
108 #define _CPB_ON_5H 0xBF // Boot block (000000-0007FFh) code-protected
109 #define _CPB_OFF_5H 0xFF // Boot block (000000-0007FFh) not code-protected
110 #define _CPD_ON_5H 0x7F // Data EEPROM code-protected
111 #define _CPD_OFF_5H 0xFF // Data EEPROM not code-protected
114 #define _WRT0_ON_6L 0xFE // Block 0 (000800-001FFFh) write-protected
115 #define _WRT0_OFF_6L 0xFF // Block 0 (000800-001FFFh) not write-protected
116 #define _WRT1_ON_6L 0xFD // Block 1 (002000-003FFFh) write-protected
117 #define _WRT1_OFF_6L 0xFF // Block 1 (002000-003FFFh) not write-protected
118 #define _WRT2_ON_6L 0xFB // Block 2 (004000-005FFFh) write-protected
119 #define _WRT2_OFF_6L 0xFF // Block 2 (004000-005FFFh) not write-protected
120 #define _WRT3_ON_6L 0xF7 // Block 3 (006000-007FFFh) write-protected
121 #define _WRT3_OFF_6L 0xFF // Block 3 (006000-007FFFh) not write-protected
124 #define _WRTB_ON_6H 0xBF // Boot block (000000-0007FFh) write-protected
125 #define _WRTB_OFF_6H 0xFF // Boot block (000000-0007FFh) not write-protected
126 #define _WRTC_ON_6H 0xDF // Configuration registers (300000-3000FFh) write-protected
127 #define _WRTC_OFF_6H 0xFF // Configuration registers (300000-3000FFh) not write-protected
128 #define _WRTD_ON_6H 0x7F // Data EEPROM write-protected
129 #define _WRTD_OFF_6H 0xFF // Data EEPROM not write-protected
132 #define _EBTR0_ON_7L 0xFE // Block 0 (000800-001FFFh) protected from table reads executed in other blocks
133 #define _EBTR0_OFF_7L 0xFF // Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
134 #define _EBTR1_ON_7L 0xFD // Block 1 (002000-003FFFh) protected from table reads executed in other blocks
135 #define _EBTR1_OFF_7L 0xFF // Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
136 #define _EBTR2_ON_7L 0xFB // Block 2 (004000-005FFFh) protected from table reads executed in other blocks
137 #define _EBTR2_OFF_7L 0xFF // Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
138 #define _EBTR3_ON_7L 0xF7 // Block 3 (006000-007FFFh) protected from table reads executed in other blocks
139 #define _EBTR3_OFF_7L 0xFF // Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
142 #define _EBTRB_ON_7H 0xBF // Boot block (000000-0007FFh) protected from table reads executed in other blocks
143 #define _EBTRB_OFF_7H 0xFF // Boot block (000000-0007FFh) not protected from table reads executed in other blocks
144 #define _DEVID1 0x3FFFFE
145 #define _DEVID2 0x3FFFFF
146 #define _IDLOC0 0x200000
147 #define _IDLOC1 0x200001
148 #define _IDLOC2 0x200002
149 #define _IDLOC3 0x200003
150 #define _IDLOC4 0x200004
151 #define _IDLOC5 0x200005
152 #define _IDLOC6 0x200006
153 #define _IDLOC7 0x200007
155 extern __sfr __at (0xF80) PORTA;
218 extern volatile __PORTAbits_t __at (0xF80) PORTAbits;
220 extern __sfr __at (0xF81) PORTB;
236 unsigned CCP2_PORTB : 1;
253 extern volatile __PORTBbits_t __at (0xF81) PORTBbits;
255 extern __sfr __at (0xF82) PORTC;
279 unsigned CCP2_PORTC : 1;
298 extern volatile __PORTCbits_t __at (0xF82) PORTCbits;
300 extern __sfr __at (0xF83) PORTD;
333 extern volatile __PORTDbits_t __at (0xF83) PORTDbits;
335 extern __sfr __at (0xF84) PORTE;
361 unsigned NOT_MCLR : 1;
378 extern volatile __PORTEbits_t __at (0xF84) PORTEbits;
380 extern __sfr __at (0xF89) LATA;
393 extern volatile __LATAbits_t __at (0xF89) LATAbits;
395 extern __sfr __at (0xF8A) LATB;
408 extern volatile __LATBbits_t __at (0xF8A) LATBbits;
410 extern __sfr __at (0xF8B) LATC;
423 extern volatile __LATCbits_t __at (0xF8B) LATCbits;
425 extern __sfr __at (0xF8C) LATD;
438 extern volatile __LATDbits_t __at (0xF8C) LATDbits;
440 extern __sfr __at (0xF8D) LATE;
453 extern volatile __LATEbits_t __at (0xF8D) LATEbits;
455 extern __sfr __at (0xF92) DDRA;
468 extern volatile __DDRAbits_t __at (0xF92) DDRAbits;
470 extern __sfr __at (0xF92) TRISA;
483 extern volatile __TRISAbits_t __at (0xF92) TRISAbits;
485 extern __sfr __at (0xF93) DDRB;
498 extern volatile __DDRBbits_t __at (0xF93) DDRBbits;
500 extern __sfr __at (0xF93) TRISB;
513 extern volatile __TRISBbits_t __at (0xF93) TRISBbits;
515 extern __sfr __at (0xF94) DDRC;
528 extern volatile __DDRCbits_t __at (0xF94) DDRCbits;
530 extern __sfr __at (0xF94) TRISC;
543 extern volatile __TRISCbits_t __at (0xF94) TRISCbits;
545 extern __sfr __at (0xF95) DDRD;
558 extern volatile __DDRDbits_t __at (0xF95) DDRDbits;
560 extern __sfr __at (0xF95) TRISD;
573 extern volatile __TRISDbits_t __at (0xF95) TRISDbits;
575 extern __sfr __at (0xF96) DDRE;
588 extern volatile __DDREbits_t __at (0xF96) DDREbits;
590 extern __sfr __at (0xF96) TRISE;
597 unsigned PSPMODE : 1;
603 extern volatile __TRISEbits_t __at (0xF96) TRISEbits;
605 extern __sfr __at (0xF9B) OSCTUNE;
618 extern volatile __OSCTUNEbits_t __at (0xF9B) OSCTUNEbits;
620 extern __sfr __at (0xF9D) PIE1;
633 extern volatile __PIE1bits_t __at (0xF9D) PIE1bits;
635 extern __sfr __at (0xF9E) PIR1;
648 extern volatile __PIR1bits_t __at (0xF9E) PIR1bits;
650 extern __sfr __at (0xF9F) IPR1;
663 extern volatile __IPR1bits_t __at (0xF9F) IPR1bits;
665 extern __sfr __at (0xFA0) PIE2;
688 extern volatile __PIE2bits_t __at (0xFA0) PIE2bits;
690 extern __sfr __at (0xFA1) PIR2;
713 extern volatile __PIR2bits_t __at (0xFA1) PIR2bits;
715 extern __sfr __at (0xFA2) IPR2;
738 extern volatile __IPR2bits_t __at (0xFA2) IPR2bits;
740 extern __sfr __at (0xFA6) EECON1;
753 extern volatile __EECON1bits_t __at (0xFA6) EECON1bits;
755 extern __sfr __at (0xFA7) EECON2;
757 extern __sfr __at (0xFA8) EEDATA;
759 extern __sfr __at (0xFA9) EEADR;
761 extern __sfr __at (0xFAB) RCSTA;
784 extern volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;
786 extern __sfr __at (0xFAC) TXSTA;
799 extern volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;
801 extern __sfr __at (0xFAD) TXREG;
803 extern __sfr __at (0xFAE) RCREG;
805 extern __sfr __at (0xFAF) SPBRG;
807 extern __sfr __at (0xFB0) SPBRGH;
809 extern __sfr __at (0xFB1) T3CON;
816 unsigned T3CKPS0 : 1;
817 unsigned T3CKPS1 : 1;
824 unsigned NOT_T3SYNC : 1;
832 extern volatile __T3CONbits_t __at (0xFB1) T3CONbits;
834 extern __sfr __at (0xFB2) TMR3L;
836 extern __sfr __at (0xFB3) TMR3H;
838 extern __sfr __at (0xFB4) CMCON;
851 extern volatile __CMCONbits_t __at (0xFB4) CMCONbits;
853 extern __sfr __at (0xFB5) CVRCON;
866 extern volatile __CVRCONbits_t __at (0xFB5) CVRCONbits;
868 extern __sfr __at (0xFB6) ECCP1AS;
875 unsigned ECCPAS0 : 1;
876 unsigned ECCPAS1 : 1;
877 unsigned ECCPAS2 : 1;
878 unsigned ECCPASE : 1;
881 extern volatile __ECCP1ASbits_t __at (0xFB6) ECCP1ASbits;
883 extern __sfr __at (0xFB7) PWM1CON;
896 extern volatile __PWM1CONbits_t __at (0xFB7) PWM1CONbits;
898 extern __sfr __at (0xFB8) BAUDCON;
921 extern volatile __BAUDCONbits_t __at (0xFB8) BAUDCONbits;
923 extern __sfr __at (0xFB8) BAUDCTL;
946 extern volatile __BAUDCTLbits_t __at (0xFB8) BAUDCTLbits;
948 extern __sfr __at (0xFBA) CCP2CON;
971 extern volatile __CCP2CONbits_t __at (0xFBA) CCP2CONbits;
973 extern __sfr __at (0xFBB) CCPR2;
975 extern __sfr __at (0xFBB) CCPR2L;
977 extern __sfr __at (0xFBC) CCPR2H;
979 extern __sfr __at (0xFBD) CCP1CON;
1002 extern volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;
1004 extern __sfr __at (0xFBE) CCPR1;
1006 extern __sfr __at (0xFBE) CCPR1L;
1008 extern __sfr __at (0xFBF) CCPR1H;
1010 extern __sfr __at (0xFC0) ADCON2;
1023 extern volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;
1025 extern __sfr __at (0xFC1) ADCON1;
1038 extern volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;
1040 extern __sfr __at (0xFC2) ADCON0;
1064 unsigned NOT_DONE : 1;
1074 unsigned GO_DONE : 1;
1083 extern volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;
1085 extern __sfr __at (0xFC3) ADRES;
1087 extern __sfr __at (0xFC3) ADRESL;
1089 extern __sfr __at (0xFC4) ADRESH;
1091 extern __sfr __at (0xFC5) SSPCON2;
1100 unsigned ACKSTAT : 1;
1104 extern volatile __SSPCON2bits_t __at (0xFC5) SSPCON2bits;
1106 extern __sfr __at (0xFC6) SSPCON1;
1119 extern volatile __SSPCON1bits_t __at (0xFC6) SSPCON1bits;
1121 extern __sfr __at (0xFC7) SSPSTAT;
1156 unsigned NOT_WRITE : 1;
1159 unsigned NOT_ADDRESS : 1;
1164 extern volatile __SSPSTATbits_t __at (0xFC7) SSPSTATbits;
1166 extern __sfr __at (0xFC8) SSPADD;
1168 extern __sfr __at (0xFC9) SSPBUF;
1170 extern __sfr __at (0xFCA) T2CON;
1173 unsigned T2CKPS0 : 1;
1174 unsigned T2CKPS1 : 1;
1175 unsigned TMR2ON : 1;
1176 unsigned T2OUTPS0 : 1;
1177 unsigned T2OUTPS1 : 1;
1178 unsigned T2OUTPS2 : 1;
1179 unsigned T2OUTPS3 : 1;
1183 extern volatile __T2CONbits_t __at (0xFCA) T2CONbits;
1185 extern __sfr __at (0xFCB) PR2;
1187 extern __sfr __at (0xFCC) TMR2;
1189 extern __sfr __at (0xFCD) T1CON;
1192 unsigned TMR1ON : 1;
1193 unsigned TMR1CS : 1;
1194 unsigned T1SYNC : 1;
1195 unsigned T1OSCEN : 1;
1196 unsigned T1CKPS0 : 1;
1197 unsigned T1CKPS1 : 1;
1204 unsigned NOT_T1SYNC : 1;
1212 extern volatile __T1CONbits_t __at (0xFCD) T1CONbits;
1214 extern __sfr __at (0xFCE) TMR1L;
1216 extern __sfr __at (0xFCF) TMR1H;
1218 extern __sfr __at (0xFD0) RCON;
1227 unsigned SBOREN : 1;
1231 unsigned NOT_BOR : 1;
1232 unsigned NOT_POR : 1;
1233 unsigned NOT_PD : 1;
1234 unsigned NOT_TO : 1;
1235 unsigned NOT_RI : 1;
1241 extern volatile __RCONbits_t __at (0xFD0) RCONbits;
1243 extern __sfr __at (0xFD1) WDTCON;
1246 unsigned SWDTEN : 1;
1266 extern volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;
1268 extern __sfr __at (0xFD2) HLVDCON;
1278 unsigned VDIRMAG : 1;
1285 unsigned HLVDEN : 1;
1291 unsigned HLVDL0 : 1;
1292 unsigned HLVDL1 : 1;
1293 unsigned HLVDL2 : 1;
1294 unsigned HLVDL3 : 1;
1301 extern volatile __HLVDCONbits_t __at (0xFD2) HLVDCONbits;
1303 extern __sfr __at (0xFD2) LVDCON;
1313 unsigned VDIRMAG : 1;
1320 unsigned HLVDEN : 1;
1326 unsigned HLVDL0 : 1;
1327 unsigned HLVDL1 : 1;
1328 unsigned HLVDL2 : 1;
1329 unsigned HLVDL3 : 1;
1336 extern volatile __LVDCONbits_t __at (0xFD2) LVDCONbits;
1338 extern __sfr __at (0xFD3) OSCCON;
1361 extern volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;
1363 extern __sfr __at (0xFD5) T0CON;
1372 unsigned T08BIT : 1;
1373 unsigned TMR0ON : 1;
1376 extern volatile __T0CONbits_t __at (0xFD5) T0CONbits;
1378 extern __sfr __at (0xFD6) TMR0L;
1380 extern __sfr __at (0xFD7) TMR0H;
1382 extern __sfr __at (0xFD8) STATUS;
1395 extern volatile __STATUSbits_t __at (0xFD8) STATUSbits;
1397 extern __sfr __at (0xFD9) FSR2L;
1399 extern __sfr __at (0xFDA) FSR2H;
1401 extern __sfr __at (0xFDB) PLUSW2;
1403 extern __sfr __at (0xFDC) PREINC2;
1405 extern __sfr __at (0xFDD) POSTDEC2;
1407 extern __sfr __at (0xFDE) POSTINC2;
1409 extern __sfr __at (0xFDF) INDF2;
1411 extern __sfr __at (0xFE0) BSR;
1413 extern __sfr __at (0xFE1) FSR1L;
1415 extern __sfr __at (0xFE2) FSR1H;
1417 extern __sfr __at (0xFE3) PLUSW1;
1419 extern __sfr __at (0xFE4) PREINC1;
1421 extern __sfr __at (0xFE5) POSTDEC1;
1423 extern __sfr __at (0xFE6) POSTINC1;
1425 extern __sfr __at (0xFE7) INDF1;
1427 extern __sfr __at (0xFE8) WREG;
1429 extern __sfr __at (0xFE9) FSR0L;
1431 extern __sfr __at (0xFEA) FSR0H;
1433 extern __sfr __at (0xFEB) PLUSW0;
1435 extern __sfr __at (0xFEC) PREINC0;
1437 extern __sfr __at (0xFED) POSTDEC0;
1439 extern __sfr __at (0xFEE) POSTINC0;
1441 extern __sfr __at (0xFEF) INDF0;
1443 extern __sfr __at (0xFF0) INTCON3;
1456 unsigned INT1IF : 1;
1457 unsigned INT2IF : 1;
1459 unsigned INT1IE : 1;
1460 unsigned INT2IE : 1;
1462 unsigned INT1IP : 1;
1463 unsigned INT2IP : 1;
1466 extern volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;
1468 extern __sfr __at (0xFF1) INTCON2;
1473 unsigned TMR0IP : 1;
1475 unsigned INTEDG2 : 1;
1476 unsigned INTEDG1 : 1;
1477 unsigned INTEDG0 : 1;
1488 unsigned NOT_RBPU : 1;
1491 extern volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;
1493 extern __sfr __at (0xFF2) INTCON;
1498 unsigned TMR0IF : 1;
1501 unsigned TMR0IE : 1;
1507 unsigned INT0IF : 1;
1510 unsigned INT0IE : 1;
1516 extern volatile __INTCONbits_t __at (0xFF2) INTCONbits;
1518 extern __sfr __at (0xFF3) PROD;
1520 extern __sfr __at (0xFF3) PRODL;
1522 extern __sfr __at (0xFF4) PRODH;
1524 extern __sfr __at (0xFF5) TABLAT;
1526 extern __sfr __at (0xFF6) TBLPTR;
1528 extern __sfr __at (0xFF6) TBLPTRL;
1530 extern __sfr __at (0xFF7) TBLPTRH;
1532 extern __sfr __at (0xFF8) TBLPTRU;
1534 extern __sfr __at (0xFF9) PC;
1536 extern __sfr __at (0xFF9) PCL;
1538 extern __sfr __at (0xFFA) PCLATH;
1540 extern __sfr __at (0xFFB) PCLATU;
1542 extern __sfr __at (0xFFC) STKPTR;
1551 unsigned STKUNF : 1;
1552 unsigned STKFUL : 1;
1562 unsigned STKOVF : 1;
1565 extern volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;
1567 extern __sfr __at (0xFFD) TOS;
1569 extern __sfr __at (0xFFD) TOSL;
1571 extern __sfr __at (0xFFE) TOSH;
1573 extern __sfr __at (0xFFF) TOSU;