3 * pic18f452.h - PIC18F452 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F452_H__
16 #define __PIC18F452_H__
18 extern sfr at 0xf80 PORTA;
65 extern volatile __PORTAbits_t at 0xf80 PORTAbits;
67 extern sfr at 0xf81 PORTB;
92 extern volatile __PORTBbits_t at 0xf81 PORTBbits;
94 extern sfr at 0xf82 PORTC;
130 extern volatile __PORTCbits_t at 0xf82 PORTCbits;
132 extern sfr at 0xf83 PORTD;
157 extern volatile __PORTDbits_t at 0xf83 PORTDbits;
159 extern sfr at 0xf84 PORTE;
195 extern volatile __PORTEbits_t at 0xf84 PORTEbits;
197 extern sfr at 0xf89 LATA;
211 extern volatile __LATAbits_t at 0xf89 LATAbits;
213 extern sfr at 0xf8a LATB;
227 extern volatile __LATBbits_t at 0xf8a LATBbits;
229 extern sfr at 0xf8b LATC;
243 extern volatile __LATCbits_t at 0xf8b LATCbits;
245 extern sfr at 0xf8c LATD;
259 extern volatile __LATDbits_t at 0xf8c LATDbits;
261 extern sfr at 0xf8d LATE;
275 extern volatile __LATEbits_t at 0xf8d LATEbits;
277 extern sfr at 0xf92 TRISA;
291 extern volatile __TRISAbits_t at 0xf92 TRISAbits;
293 extern sfr at 0xf93 TRISB;
307 extern volatile __TRISBbits_t at 0xf93 TRISBbits;
309 extern sfr at 0xf94 TRISC;
323 extern volatile __TRISCbits_t at 0xf94 TRISCbits;
325 extern sfr at 0xf95 TRISD;
339 extern volatile __TRISDbits_t at 0xf95 TRISDbits;
341 extern sfr at 0xf96 TRISE;
355 extern volatile __TRISEbits_t at 0xf96 TRISEbits;
357 extern sfr at 0xf9d PIE1;
371 extern volatile __PIE1bits_t at 0xf9d PIE1bits;
373 extern sfr at 0xf9e PIR1;
387 extern volatile __PIR1bits_t at 0xf9e PIR1bits;
389 extern sfr at 0xf9f IPR1;
403 extern volatile __IPR1bits_t at 0xf9f IPR1bits;
405 extern sfr at 0xfa0 PIE2;
419 extern volatile __PIE2bits_t at 0xfa0 PIE2bits;
421 extern sfr at 0xfa1 PIR2;
435 extern volatile __PIR2bits_t at 0xfa1 PIR2bits;
437 extern sfr at 0xfa2 IPR2;
451 extern volatile __IPR2bits_t at 0xfa2 IPR2bits;
453 extern sfr at 0xfa6 EECON1;
467 extern volatile __EECON1bits_t at 0xfa6 EECON1bits;
469 extern sfr at 0xfa7 EECON2;
470 extern sfr at 0xfa8 EEDATA;
471 extern sfr at 0xfa9 EEADR;
472 extern sfr at 0xfab RCSTA;
486 extern volatile __RCSTAbits_t at 0xfab RCSTAbits;
488 extern sfr at 0xfac TXSTA;
502 extern volatile __TXSTAbits_t at 0xfac TXSTAbits;
504 extern sfr at 0xfad TXREG;
505 extern sfr at 0xfae RCREG;
506 extern sfr at 0xfaf SPBRG;
507 extern sfr at 0xfb1 T3CON;
521 extern volatile __T3CONbits_t at 0xfb1 T3CONbits;
523 extern sfr at 0xfb2 TMR3L;
524 extern sfr at 0xfb3 TMR3H;
525 extern sfr at 0xfba CCP2CON;
539 extern volatile __CCP2CONbits_t at 0xfba CCP2CONbits;
541 extern sfr at 0xfbb CCPR2L;
542 extern sfr at 0xfbc CCPR2H;
543 extern sfr at 0xfbd CCP1CON;
557 extern volatile __CCP1CONbits_t at 0xfbd CCP1CONbits;
559 extern sfr at 0xfbe CCPR1L;
560 extern sfr at 0xfbf CCPR1H;
561 extern sfr at 0xfc1 ADCON1;
575 extern volatile __ADCON1bits_t at 0xfc1 ADCON1bits;
577 extern sfr at 0xfc2 ADCON0;
591 extern volatile __ADCON0bits_t at 0xfc2 ADCON0bits;
593 extern sfr at 0xfc3 ADRESL;
594 extern sfr at 0xfc4 ADRESH;
595 extern sfr at 0xfc5 SSPCON2;
609 extern volatile __SSPCON2bits_t at 0xfc5 SSPCON2bits;
611 extern sfr at 0xfc6 SSPCON1;
625 extern volatile __SSPCON1bits_t at 0xfc6 SSPCON1bits;
627 extern sfr at 0xfc7 SSPSTAT;
641 extern volatile __SSPSTATbits_t at 0xfc7 SSPSTATbits;
643 extern sfr at 0xfc8 SSPADD;
644 extern sfr at 0xfc9 SSPBUF;
645 extern sfr at 0xfca T2CON;
659 extern volatile __T2CONbits_t at 0xfca T2CONbits;
661 extern sfr at 0xfcb PR2;
662 extern sfr at 0xfcc TMR2;
663 extern sfr at 0xfcd T1CON;
668 unsigned NOT_T1SYNC:1;
677 extern volatile __T1CONbits_t at 0xfcd T1CONbits;
679 extern sfr at 0xfce TMR1L;
680 extern sfr at 0xfcf TMR1H;
681 extern sfr at 0xfd0 RCON;
695 extern volatile __RCONbits_t at 0xfd0 RCONbits;
697 extern sfr at 0xfd1 WDTCON;
722 extern volatile __WDTCONbits_t at 0xfd1 WDTCONbits;
724 extern sfr at 0xfd2 LVDCON;
749 extern volatile __LVDCONbits_t at 0xfd2 LVDCONbits;
751 extern sfr at 0xfd3 OSCCON;
765 extern volatile __OSCCONbits_t at 0xfd3 OSCCONbits;
767 extern sfr at 0xfd5 T0CON;
768 extern sfr at 0xfd6 TMR0L;
769 extern sfr at 0xfd7 TMR0H;
770 extern sfr at 0xfd8 STATUS;
784 extern volatile __STATUSbits_t at 0xfd8 STATUSbits;
786 extern sfr at 0xfd9 FSR2L;
787 extern sfr at 0xfda FSR2H;
788 extern sfr at 0xfdb PLUSW2;
789 extern sfr at 0xfdc PREINC2;
790 extern sfr at 0xfdd POSTDEC2;
791 extern sfr at 0xfde POSTINC2;
792 extern sfr at 0xfdf INDF2;
793 extern sfr at 0xfe0 BSR;
794 extern sfr at 0xfe1 FSR1L;
795 extern sfr at 0xfe2 FSR1H;
796 extern sfr at 0xfe3 PLUSW1;
797 extern sfr at 0xfe4 PREINC1;
798 extern sfr at 0xfe5 POSTDEC1;
799 extern sfr at 0xfe6 POSTINC1;
800 extern sfr at 0xfe7 INDF1;
801 extern sfr at 0xfe8 WREG;
802 extern sfr at 0xfe9 FSR0L;
803 extern sfr at 0xfea FSR0H;
804 extern sfr at 0xfeb PLUSW0;
805 extern sfr at 0xfec PREINC0;
806 extern sfr at 0xfed POSTDEC0;
807 extern sfr at 0xfee POSTINC0;
808 extern sfr at 0xfef INDF0;
809 extern sfr at 0xff0 INTCON3;
834 extern volatile __INTCON3bits_t at 0xff0 INTCON3bits;
836 extern sfr at 0xff1 INTCON2;
850 extern volatile __INTCON2bits_t at 0xff1 INTCON2bits;
852 extern sfr at 0xff2 INTCON;
866 extern volatile __INTCONbits_t at 0xff2 INTCONbits;
868 extern sfr at 0xff3 PRODL;
869 extern sfr at 0xff4 PRODH;
870 extern sfr at 0xff5 TABLAT;
871 extern sfr at 0xff6 TBLPTRL;
872 extern sfr at 0xff7 TBLPTRH;
873 extern sfr at 0xff8 TBLPTRU;
874 extern sfr at 0xff9 PCL;
875 extern sfr at 0xffa PCLATH;
876 extern sfr at 0xffb PCLATU;
877 extern sfr at 0xffc STKPTR;
891 extern volatile __STKPTRbits_t at 0xffc STKPTRbits;
893 extern sfr at 0xffd TOSL;
894 extern sfr at 0xffe TOSH;
895 extern sfr at 0xfff TOSU;
898 /* Configuration registers locations */
899 #define __CONFIG0H 0x300001
900 #define __CONFIG1L 0x300002
901 #define __CONFIG1H 0x300003
902 #define __CONFIG2H 0x300005
903 #define __CONFIG3L 0x300006
904 #define __CONFIG4L 0x300008
905 #define __CONFIG4H 0x300009
906 #define __CONFIG5L 0x30000A
907 #define __CONFIG5H 0x30000B
908 #define __CONFIG6L 0x30000C
909 #define __CONFIG6H 0x30000D
913 /* Oscillator 0H options */
914 #define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */
915 #define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */
916 #define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */
917 #define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */
918 #define _OSC_RC_0H 0xFB /* RC */
919 #define _OSC_HS_0H 0xFA /* HS */
920 #define _OSC_XT_0H 0xF9 /* XT */
921 #define _OSC_LP_0H 0xF8 /* LP */
923 /* Osc. Switch Enable 0H options */
924 #define _OSCS_OFF_0H 0xFF /* Disabled */
925 #define _OSCS_ON_0H 0xDF /* Enabled */
927 /* Power Up Timer 1L options */
928 #define _PUT_OFF_1L 0xFF /* Disabled */
929 #define _PUT_ON_1L 0xFE /* Enabled */
931 /* Brown Out Detect 1L options */
932 #define _BODEN_ON_1L 0xFF /* Enabled */
933 #define _BODEN_OFF_1L 0xFD /* Disabled */
935 /* Brown Out Voltage 1L options */
936 #define _BODENV_2_0V_1L 0xFF /* 2.0V */
937 #define _BODENV_2_7V_1L 0xFB /* 2.7V */
938 #define _BODENV_4_2V_1L 0xF7 /* 4.2V */
939 #define _BODENV_4_5V_1L 0xF3 /* 4.5V */
941 /* Watchdog Timer 1H options */
942 #define _WDT_ON_1H 0xFF /* Enabled */
943 #define _WDT_OFF_1H 0xFE /* Disabled */
945 /* Watchdog Postscaler 1H options */
946 #define _WDTPS_1_128_1H 0xFF /* 1:128 */
947 #define _WDTPS_1_64_1H 0xFD /* 1:64 */
948 #define _WDTPS_1_32_1H 0xFB /* 1:32 */
949 #define _WDTPS_1_16_1H 0xF9 /* 1:16 */
950 #define _WDTPS_1_8_1H 0xF7 /* 1:8 */
951 #define _WDTPS_1_4_1H 0xF5 /* 1:4 */
952 #define _WDTPS_1_2_1H 0xF3 /* 1:2 */
953 #define _WDTPS_1_1_1H 0xF1 /* 1:1 */
955 /* CCP2 Mux 2H options */
956 #define _CCP2MUX_RC1_2H 0xFF /* RC1 */
957 #define _CCP2MUX_RB3_2H 0xFE /* RB3 */
959 /* Low Voltage Program 3L options */
960 #define _LVP_ON_3L 0xFF /* Enabled */
961 #define _LVP_OFF_3L 0xFB /* Disabled */
963 /* Background Debug 3L options */
964 #define _BACKBUG_OFF_3L 0xFF /* Disabled */
965 #define _BACKBUG_ON_3L 0x7F /* Enabled */
967 /* Stack Overflow Reset 3L options */
968 #define _STVR_ON_3L 0xFF /* Enabled */
969 #define _STVR_OFF_3L 0xFE /* Disabled */
971 /* Code Protect 00200-01FFF 4L options */
972 #define _CP_0_OFF_4L 0xFF /* Disabled */
973 #define _CP_0_ON_4L 0xFE /* Enabled */
975 /* Code Protect 02000-03FFF 4L options */
976 #define _CP_1_OFF_4L 0xFF /* Disabled */
977 #define _CP_1_ON_4L 0xFD /* Enabled */
979 /* Code Protect 04000-05FFF 4L options */
980 #define _CP_2_OFF_4L 0xFF /* Disabled */
981 #define _CP_2_ON_4L 0xFB /* Enabled */
983 /* Code Protect 06000-07FFF 4L options */
984 #define _CP_3_OFF_4L 0xFF /* Disabled */
985 #define _CP_3_ON_4L 0xF7 /* Enabled */
987 /* Data EE Read Protect 4H options */
988 #define _CPD_OFF_4H 0xFF /* Disabled */
989 #define _CPD_ON_4H 0x7F /* Enabled */
991 /* Code Protect Boot 4H options */
992 #define _CPB_OFF_4H 0xFF /* Disabled */
993 #define _CPB_ON_4H 0xBF /* Enabled */
995 /* Table Write Protect 00200-01FFF 5L options */
996 #define _WRT_0_OFF_5L 0xFF /* Disabled */
997 #define _WRT_0_ON_5L 0xFE /* Enabled */
999 /* Table Write Protect 02000-03FFF 5L options */
1000 #define _WRT_1_OFF_5L 0xFF /* Disabled */
1001 #define _WRT_1_ON_5L 0xFD /* Enabled */
1003 /* Table Write Protect 04000-05FFF 5L options */
1004 #define _WRT_2_OFF_5L 0xFF /* Disabled */
1005 #define _WRT_2_ON_5L 0xFB /* Enabled */
1007 /* Table Write Protect 06000-07FFF 5L options */
1008 #define _WRT_3_OFF_5L 0xFF /* Disabled */
1009 #define _WRT_3_ON_5L 0xF7 /* Enabled */
1011 /* Data EE Write Protect 5H options */
1012 #define _WRTD_OFF_5H 0xFF /* Disabled */
1013 #define _WRTD_ON_5H 0x7F /* Enabled */
1015 /* Table Write Protect Boot 5H options */
1016 #define _WRTB_OFF_5H 0xFF /* Disabled */
1017 #define _WRTB_ON_5H 0xBF /* Enabled */
1019 /* Config. Write Protect 5H options */
1020 #define _WRTC_OFF_5H 0xFF /* Disabled */
1021 #define _WRTC_ON_5H 0xDF /* Enabled */
1023 /* Table Read Protect 00200-01FFF 6L options */
1024 #define _EBTR_0_OFF_6L 0xFF /* Disabled */
1025 #define _EBTR_0_ON_6L 0xFE /* Enabled */
1027 /* Table Read Protect 02000-03FFF 6L options */
1028 #define _EBTR_1_OFF_6L 0xFF /* Disabled */
1029 #define _EBTR_1_ON_6L 0xFD /* Enabled */
1031 /* Table Read Protect 04000-05FFF 6L options */
1032 #define _EBTR_2_OFF_6L 0xFF /* Disabled */
1033 #define _EBTR_2_ON_6L 0xFB /* Enabled */
1035 /* Table Read Protect 06000-07FFF 6L options */
1036 #define _EBTR_3_OFF_6L 0xFF /* Disabled */
1037 #define _EBTR_3_ON_6L 0xF7 /* Enabled */
1039 /* Table Read Protect Boot 6H options */
1040 #define _EBTRB_OFF_6H 0xFF /* Disabled */
1041 #define _EBTRB_ON_6H 0xBF /* Enabled */
1044 /* Device ID locations */
1045 #define __IDLOC0 0x200000
1046 #define __IDLOC1 0x200001
1047 #define __IDLOC2 0x200002
1048 #define __IDLOC3 0x200003
1049 #define __IDLOC4 0x200004
1050 #define __IDLOC5 0x200005
1051 #define __IDLOC6 0x200006
1052 #define __IDLOC7 0x200007