2 * pic18f4450.h - device specific declarations
4 * This file is part of the GNU PIC library for SDCC,
5 * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
7 * It has been automatically generated by inc2h-pic16.pl,
8 * (c) 2007 by Raphael Neider <rneider AT web.de>
11 #ifndef __PIC18F4450_H__
12 #define __PIC18F4450_H__ 1
17 #define __CONFIG1L 0x300000
18 #define __CONFIG1H 0x300001
19 #define __CONFIG2L 0x300002
20 #define __CONFIG2H 0x300003
21 #define __CONFIG3H 0x300005
22 #define __CONFIG4L 0x300006
23 #define __CONFIG5L 0x300008
24 #define __CONFIG5H 0x300009
25 #define __CONFIG6L 0x30000A
26 #define __CONFIG6H 0x30000B
27 #define __CONFIG7L 0x30000C
28 #define __CONFIG7H 0x30000D
31 #define _PLLDIV_1_1L 0xF8 // No divide (4 MHz input)
32 #define _PLLDIV_2_1L 0xF9 // Divide by 2 (8 MHz input)
33 #define _PLLDIV_3_1L 0xFA // Divide by 3 (12 MHz input)
34 #define _PLLDIV_4_1L 0xFB // Divide by 4 (16 MHz input)
35 #define _PLLDIV_5_1L 0xFC // Divide by 5 (20 MHz input)
36 #define _PLLDIV_6_1L 0xFD // Divide by 6 (24 MHz input)
37 #define _PLLDIV_10_1L 0xFE // Divide by 10 (40 MHz input)
38 #define _PLLDIV_12_1L 0xFF // Divide by 12 (48 MHz input)
39 #define _CPUDIV_OSC1_PLL2_1L 0xE7 // [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
40 #define _CPUDIV_OSC2_PLL3_1L 0xEF // [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
41 #define _CPUDIV_OSC3_PLL4_1L 0xF7 // [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
42 #define _CPUDIV_OSC4_PLL6_1L 0xFF // [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
43 #define _USBDIV_1_1L 0xDF // Clock source from OSC1/OSC2
44 #define _USBDIV_2_1L 0xFF // Clock source from 96 MHz PLL/2
47 #define _FOSC_XT_XT_1H 0xF0 // XT oscillator, XT used by USB
48 #define _FOSC_XTPLL_XT_1H 0xF2 // XT oscillator, PLL enabled, XT used by USB
49 #define _FOSC_ECIO_EC_1H 0xF4 // External clock, port function on RA6, EC used by USB
50 #define _FOSC_EC_EC_1H 0xF5 // External clock, CLKOUT on RA6, EC used by USB
51 #define _FOSC_ECPLLIO_EC_1H 0xF6 // External clock, PLL enabled, port function on RA6, EC used by USB
52 #define _FOSC_ECPLL_EC_1H 0xF7 // External clock, PLL enabled, CLKOUT on RA6, EC used by USB
53 #define _FOSC_INTOSCIO_EC_1H 0xF8 // Internal oscillator, port function on RA6, EC used by USB
54 #define _FOSC_INTOSC_EC_1H 0xF9 // Internal oscillator, CLKOUT on RA6, EC used by USB
55 #define _FOSC_INTOSC_XT_1H 0xFA // Internal oscillator, XT used by USB
56 #define _FOSC_INTOSC_HS_1H 0xFB // Internal oscillator, HS used by USB
57 #define _FOSC_HS_1H 0xFC // HS oscillator, HS used by USB
58 #define _FOSC_HSPLL_HS_1H 0xFE // HS oscillator, PLL enabled, HS used by USB
59 #define _FCMEM_OFF_1H 0xBF // Disabled
60 #define _FCMEM_ON_1H 0xFF // Enabled
61 #define _IESO_OFF_1H 0x7F // Disabled
62 #define _IESO_ON_1H 0xFF // Enabled
65 #define _PWRT_ON_2L 0xFE // Enabled
66 #define _PWRT_OFF_2L 0xFF // Disabled
67 #define _BOR_OFF_2L 0xF9 // Disabled
68 #define _BOR_SOFT_2L 0xFB // Controlled by SBOREN
69 #define _BOR_ON_ACTIVE_2L 0xFD // Enabled when the device is not in Sleep, SBOREN bit is disabled
70 #define _BOR_ON_2L 0xFF // Enabled, SBOREN bit is disabled
71 #define _BORV_46_2L 0xE7 // 4.6V
72 #define _BORV_43_2L 0xEF // 4.3V
73 #define _BORV_28_2L 0xF7 // 2.8V
74 #define _BORV_21_2L 0xFF // 2.1V
75 #define _VREGEN_OFF_2L 0xDF // Disabled
76 #define _VREGEN_ON_2L 0xFF // Enabled
79 #define _WDT_OFF_2H 0xFE // HW Disabled - SW Controlled
80 #define _WDT_ON_2H 0xFF // HW Enabled - SW Disabled
81 #define _WDTPS_1_2H 0xE1 // 1:1
82 #define _WDTPS_2_2H 0xE3 // 1:2
83 #define _WDTPS_4_2H 0xE5 // 1:4
84 #define _WDTPS_8_2H 0xE7 // 1:8
85 #define _WDTPS_16_2H 0xE9 // 1:16
86 #define _WDTPS_32_2H 0xEB // 1:32
87 #define _WDTPS_64_2H 0xED // 1:64
88 #define _WDTPS_128_2H 0xEF // 1:128
89 #define _WDTPS_256_2H 0xF1 // 1:256
90 #define _WDTPS_512_2H 0xF3 // 1:512
91 #define _WDTPS_1024_2H 0xF5 // 1:1024
92 #define _WDTPS_2048_2H 0xF7 // 1:2048
93 #define _WDTPS_4096_2H 0xF9 // 1:4096
94 #define _WDTPS_8192_2H 0xFB // 1:8192
95 #define _WDTPS_16384_2H 0xFD // 1:16384
96 #define _WDTPS_32768_2H 0xFF // 1:32768
99 #define _MCLRE_OFF_3H 0x7F // Disabled
100 #define _MCLRE_ON_3H 0xFF // Enabled
101 #define _LPT1OSC_OFF_3H 0xFB // Timer1 oscillator configured for high power
102 #define _LPT1OSC_ON_3H 0xFF // Timer1 oscillator configured for low power
103 #define _PBADEN_OFF_3H 0xFD // PORTB<4:0> pins are configured as digital I/O on Reset
104 #define _PBADEN_ON_3H 0xFF // PORTB<4:0> pins are configured as analog input on Reset
107 #define _STVREN_OFF_4L 0xFE // Disabled
108 #define _STVREN_ON_4L 0xFF // Enabled
109 #define _LVP_OFF_4L 0xFB // Disabled
110 #define _LVP_ON_4L 0xFF // Enabled
111 #define _BBSIZ_BB2K_4L 0xF7 // 2KW Boot Block Size
112 #define _BBSIZ_BB1K_4L 0xFF // 1KW Boot Block Size
113 #define _ICPRT_OFF_4L 0xDF // Disabled
114 #define _ICPRT_ON_4L 0xFF // Enabled
115 #define _XINST_OFF_4L 0xBF // Disabled
116 #define _XINST_ON_4L 0xFF // Enabled
117 #define _DEBUG_ON_4L 0x7F // Enabled
118 #define _DEBUG_OFF_4L 0xFF // Disabled
121 #define _CP0_ON_5L 0xFE // Enabled
122 #define _CP0_OFF_5L 0xFF // Disabled
123 #define _CP1_ON_5L 0xFD // Enabled
124 #define _CP1_OFF_5L 0xFF // Disabled
127 #define _CPB_ON_5H 0xBF // Enabled
128 #define _CPB_OFF_5H 0xFF // Disabled
131 #define _WRT0_ON_6L 0xFE // Enabled
132 #define _WRT0_OFF_6L 0xFF // Disabled
133 #define _WRT1_ON_6L 0xFD // Enabled
134 #define _WRT1_OFF_6L 0xFF // Disabled
137 #define _WRTB_ON_6H 0xBF // Enabled
138 #define _WRTB_OFF_6H 0xFF // Disabled
139 #define _WRTC_ON_6H 0xDF // Enabled
140 #define _WRTC_OFF_6H 0xFF // Disabled
143 #define _EBTR0_ON_7L 0xFE // Enabled
144 #define _EBTR0_OFF_7L 0xFF // Disabled
145 #define _EBTR1_ON_7L 0xFD // Enabled
146 #define _EBTR1_OFF_7L 0xFF // Disabled
149 #define _EBTRB_ON_7H 0xBF // Enabled
150 #define _EBTRB_OFF_7H 0xFF // Disabled
151 #define _DEVID1 0x3FFFFE
152 #define _DEVID2 0x3FFFFF
153 #define _IDLOC0 0x200000
154 #define _IDLOC1 0x200001
155 #define _IDLOC2 0x200002
156 #define _IDLOC3 0x200003
157 #define _IDLOC4 0x200004
158 #define _IDLOC5 0x200005
159 #define _IDLOC6 0x200006
160 #define _IDLOC7 0x200007
162 extern __sfr __at (0xF66) UFRM;
164 extern __sfr __at (0xF66) UFRML;
166 extern __sfr __at (0xF67) UFRMH;
168 extern __sfr __at (0xF68) UIR;
176 unsigned STALLIF : 1;
181 extern volatile __UIRbits_t __at (0xF68) UIRbits;
183 extern __sfr __at (0xF69) UIE;
191 unsigned STALLIE : 1;
196 extern volatile __UIEbits_t __at (0xF69) UIEbits;
198 extern __sfr __at (0xF6A) UEIR;
203 unsigned CRC16EF : 1;
211 extern volatile __UEIRbits_t __at (0xF6A) UEIRbits;
213 extern __sfr __at (0xF6B) UEIE;
218 unsigned CRC16EE : 1;
226 extern volatile __UEIEbits_t __at (0xF6B) UEIEbits;
228 extern __sfr __at (0xF6C) USTAT;
241 extern volatile __USTATbits_t __at (0xF6C) USTATbits;
243 extern __sfr __at (0xF6D) UCON;
256 extern volatile __UCONbits_t __at (0xF6D) UCONbits;
258 extern __sfr __at (0xF6E) UADDR;
271 extern volatile __UADDRbits_t __at (0xF6E) UADDRbits;
273 extern __sfr __at (0xF6F) UCFG;
286 extern volatile __UCFGbits_t __at (0xF6F) UCFGbits;
288 extern __sfr __at (0xF70) UEP0;
291 unsigned EPSTALL : 1;
293 unsigned EPOUTEN : 1;
294 unsigned EPCONDIS : 1;
301 extern volatile __UEP0bits_t __at (0xF70) UEP0bits;
303 extern __sfr __at (0xF71) UEP1;
306 unsigned EPSTALL : 1;
308 unsigned EPOUTEN : 1;
309 unsigned EPCONDIS : 1;
316 extern volatile __UEP1bits_t __at (0xF71) UEP1bits;
318 extern __sfr __at (0xF72) UEP2;
321 unsigned EPSTALL : 1;
323 unsigned EPOUTEN : 1;
324 unsigned EPCONDIS : 1;
331 extern volatile __UEP2bits_t __at (0xF72) UEP2bits;
333 extern __sfr __at (0xF73) UEP3;
336 unsigned EPSTALL : 1;
338 unsigned EPOUTEN : 1;
339 unsigned EPCONDIS : 1;
346 extern volatile __UEP3bits_t __at (0xF73) UEP3bits;
348 extern __sfr __at (0xF74) UEP4;
351 unsigned EPSTALL : 1;
353 unsigned EPOUTEN : 1;
354 unsigned EPCONDIS : 1;
361 extern volatile __UEP4bits_t __at (0xF74) UEP4bits;
363 extern __sfr __at (0xF75) UEP5;
366 unsigned EPSTALL : 1;
368 unsigned EPOUTEN : 1;
369 unsigned EPCONDIS : 1;
376 extern volatile __UEP5bits_t __at (0xF75) UEP5bits;
378 extern __sfr __at (0xF76) UEP6;
381 unsigned EPSTALL : 1;
383 unsigned EPOUTEN : 1;
384 unsigned EPCONDIS : 1;
391 extern volatile __UEP6bits_t __at (0xF76) UEP6bits;
393 extern __sfr __at (0xF77) UEP7;
396 unsigned EPSTALL : 1;
398 unsigned EPOUTEN : 1;
399 unsigned EPCONDIS : 1;
406 extern volatile __UEP7bits_t __at (0xF77) UEP7bits;
408 extern __sfr __at (0xF78) UEP8;
411 unsigned EPSTALL : 1;
413 unsigned EPOUTEN : 1;
414 unsigned EPCONDIS : 1;
421 extern volatile __UEP8bits_t __at (0xF78) UEP8bits;
423 extern __sfr __at (0xF79) UEP9;
426 unsigned EPSTALL : 1;
428 unsigned EPOUTEN : 1;
429 unsigned EPCONDIS : 1;
436 extern volatile __UEP9bits_t __at (0xF79) UEP9bits;
438 extern __sfr __at (0xF7A) UEP10;
441 unsigned EPSTALL : 1;
443 unsigned EPOUTEN : 1;
444 unsigned EPCONDIS : 1;
451 extern volatile __UEP10bits_t __at (0xF7A) UEP10bits;
453 extern __sfr __at (0xF7B) UEP11;
456 unsigned EPSTALL : 1;
458 unsigned EPOUTEN : 1;
459 unsigned EPCONDIS : 1;
466 extern volatile __UEP11bits_t __at (0xF7B) UEP11bits;
468 extern __sfr __at (0xF7C) UEP12;
471 unsigned EPSTALL : 1;
473 unsigned EPOUTEN : 1;
474 unsigned EPCONDIS : 1;
481 extern volatile __UEP12bits_t __at (0xF7C) UEP12bits;
483 extern __sfr __at (0xF7D) UEP13;
486 unsigned EPSTALL : 1;
488 unsigned EPOUTEN : 1;
489 unsigned EPCONDIS : 1;
496 extern volatile __UEP13bits_t __at (0xF7D) UEP13bits;
498 extern __sfr __at (0xF7E) UEP14;
501 unsigned EPSTALL : 1;
503 unsigned EPOUTEN : 1;
504 unsigned EPCONDIS : 1;
511 extern volatile __UEP14bits_t __at (0xF7E) UEP14bits;
513 extern __sfr __at (0xF7F) UEP15;
516 unsigned EPSTALL : 1;
518 unsigned EPOUTEN : 1;
519 unsigned EPCONDIS : 1;
526 extern volatile __UEP15bits_t __at (0xF7F) UEP15bits;
528 extern __sfr __at (0xF80) PORTA;
571 extern volatile __PORTAbits_t __at (0xF80) PORTAbits;
573 extern __sfr __at (0xF81) PORTB;
616 extern volatile __PORTBbits_t __at (0xF81) PORTBbits;
618 extern __sfr __at (0xF82) PORTC;
642 unsigned NOT_UOE : 1;
661 extern volatile __PORTCbits_t __at (0xF82) PORTCbits;
663 extern __sfr __at (0xF83) PORTD;
676 extern volatile __PORTDbits_t __at (0xF83) PORTDbits;
678 extern __sfr __at (0xF84) PORTE;
701 extern volatile __PORTEbits_t __at (0xF84) PORTEbits;
703 extern __sfr __at (0xF89) LATA;
716 extern volatile __LATAbits_t __at (0xF89) LATAbits;
718 extern __sfr __at (0xF8A) LATB;
731 extern volatile __LATBbits_t __at (0xF8A) LATBbits;
733 extern __sfr __at (0xF8B) LATC;
746 extern volatile __LATCbits_t __at (0xF8B) LATCbits;
748 extern __sfr __at (0xF8C) LATD;
761 extern volatile __LATDbits_t __at (0xF8C) LATDbits;
763 extern __sfr __at (0xF8D) LATE;
776 extern volatile __LATEbits_t __at (0xF8D) LATEbits;
778 extern __sfr __at (0xF92) DDRA;
791 extern volatile __DDRAbits_t __at (0xF92) DDRAbits;
793 extern __sfr __at (0xF92) TRISA;
806 extern volatile __TRISAbits_t __at (0xF92) TRISAbits;
808 extern __sfr __at (0xF93) DDRB;
821 extern volatile __DDRBbits_t __at (0xF93) DDRBbits;
823 extern __sfr __at (0xF93) TRISB;
836 extern volatile __TRISBbits_t __at (0xF93) TRISBbits;
838 extern __sfr __at (0xF94) DDRC;
851 extern volatile __DDRCbits_t __at (0xF94) DDRCbits;
853 extern __sfr __at (0xF94) TRISC;
866 extern volatile __TRISCbits_t __at (0xF94) TRISCbits;
868 extern __sfr __at (0xF95) DDRD;
881 extern volatile __DDRDbits_t __at (0xF95) DDRDbits;
883 extern __sfr __at (0xF95) TRISD;
896 extern volatile __TRISDbits_t __at (0xF95) TRISDbits;
898 extern __sfr __at (0xF96) DDRE;
911 extern volatile __DDREbits_t __at (0xF96) DDREbits;
913 extern __sfr __at (0xF96) TRISE;
926 extern volatile __TRISEbits_t __at (0xF96) TRISEbits;
928 extern __sfr __at (0xF9D) PIE1;
941 extern volatile __PIE1bits_t __at (0xF9D) PIE1bits;
943 extern __sfr __at (0xF9E) PIR1;
956 extern volatile __PIR1bits_t __at (0xF9E) PIR1bits;
958 extern __sfr __at (0xF9F) IPR1;
971 extern volatile __IPR1bits_t __at (0xF9F) IPR1bits;
973 extern __sfr __at (0xFA0) PIE2;
996 extern volatile __PIE2bits_t __at (0xFA0) PIE2bits;
998 extern __sfr __at (0xFA1) PIR2;
1008 unsigned OSCFIF : 1;
1013 unsigned HLVDIF : 1;
1021 extern volatile __PIR2bits_t __at (0xFA1) PIR2bits;
1023 extern __sfr __at (0xFA2) IPR2;
1033 unsigned OSCFIP : 1;
1038 unsigned HLVDIP : 1;
1046 extern volatile __IPR2bits_t __at (0xFA2) IPR2bits;
1048 extern __sfr __at (0xFA6) EECON1;
1061 extern volatile __EECON1bits_t __at (0xFA6) EECON1bits;
1063 extern __sfr __at (0xFA7) EECON2;
1065 extern __sfr __at (0xFAB) RCSTA;
1088 extern volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;
1090 extern __sfr __at (0xFAC) TXSTA;
1103 extern volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;
1105 extern __sfr __at (0xFAD) TXREG;
1107 extern __sfr __at (0xFAE) RCREG;
1109 extern __sfr __at (0xFAF) SPBRG;
1111 extern __sfr __at (0xFB0) SPBRGH;
1113 extern __sfr __at (0xFB8) BAUDCON;
1123 unsigned ABDOVF : 1;
1136 extern volatile __BAUDCONbits_t __at (0xFB8) BAUDCONbits;
1138 extern __sfr __at (0xFBD) CCP1CON;
1141 unsigned CCP1M0 : 1;
1142 unsigned CCP1M1 : 1;
1143 unsigned CCP1M2 : 1;
1144 unsigned CCP1M3 : 1;
1151 extern volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;
1153 extern __sfr __at (0xFBE) CCPR1;
1155 extern __sfr __at (0xFBE) CCPR1L;
1157 extern __sfr __at (0xFBF) CCPR1H;
1159 extern __sfr __at (0xFC0) ADCON2;
1172 extern volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;
1174 extern __sfr __at (0xFC1) ADCON1;
1187 extern volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;
1189 extern __sfr __at (0xFC2) ADCON0;
1193 unsigned GO_DONE : 1;
1223 unsigned NOT_DONE : 1;
1232 extern volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;
1234 extern __sfr __at (0xFC3) ADRES;
1236 extern __sfr __at (0xFC3) ADRESL;
1238 extern __sfr __at (0xFC4) ADRESH;
1240 extern __sfr __at (0xFCA) T2CON;
1243 unsigned T2CKPS0 : 1;
1244 unsigned T2CKPS1 : 1;
1245 unsigned TMR2ON : 1;
1246 unsigned T2OUTPS0 : 1;
1247 unsigned T2OUTPS1 : 1;
1248 unsigned T2OUTPS2 : 1;
1249 unsigned T2OUTPS3 : 1;
1253 extern volatile __T2CONbits_t __at (0xFCA) T2CONbits;
1255 extern __sfr __at (0xFCB) PR2;
1257 extern __sfr __at (0xFCC) TMR2;
1259 extern __sfr __at (0xFCD) T1CON;
1262 unsigned TMR1ON : 1;
1263 unsigned TMR1CS : 1;
1264 unsigned T1SYNC : 1;
1265 unsigned T1OSCEN : 1;
1266 unsigned T1CKPS0 : 1;
1267 unsigned T1CKPS1 : 1;
1274 unsigned NOT_T1SYNC : 1;
1282 extern volatile __T1CONbits_t __at (0xFCD) T1CONbits;
1284 extern __sfr __at (0xFCE) TMR1L;
1286 extern __sfr __at (0xFCF) TMR1H;
1288 extern __sfr __at (0xFD0) RCON;
1291 unsigned NOT_BOR : 1;
1292 unsigned NOT_POR : 1;
1293 unsigned NOT_PD : 1;
1294 unsigned NOT_TO : 1;
1295 unsigned NOT_RI : 1;
1297 unsigned SBOREN : 1;
1298 unsigned NOT_IPEN : 1;
1311 extern volatile __RCONbits_t __at (0xFD0) RCONbits;
1313 extern __sfr __at (0xFD1) WDTCON;
1316 unsigned SWDTEN : 1;
1336 extern volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;
1338 extern __sfr __at (0xFD2) HLVDCON;
1348 unsigned VDIRMAG : 1;
1355 unsigned HLVDEN : 1;
1361 unsigned HLVDL0 : 1;
1362 unsigned HLVDL1 : 1;
1363 unsigned HLVDL2 : 1;
1364 unsigned HLVDL3 : 1;
1371 extern volatile __HLVDCONbits_t __at (0xFD2) HLVDCONbits;
1373 extern __sfr __at (0xFD2) LVDCON;
1383 unsigned VDIRMAG : 1;
1390 unsigned HLVDEN : 1;
1396 unsigned HLVDL0 : 1;
1397 unsigned HLVDL1 : 1;
1398 unsigned HLVDL2 : 1;
1399 unsigned HLVDL3 : 1;
1406 extern volatile __LVDCONbits_t __at (0xFD2) LVDCONbits;
1408 extern __sfr __at (0xFD3) OSCCON;
1421 extern volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;
1423 extern __sfr __at (0xFD5) T0CON;
1432 unsigned T08BIT : 1;
1433 unsigned TMR0ON : 1;
1436 extern volatile __T0CONbits_t __at (0xFD5) T0CONbits;
1438 extern __sfr __at (0xFD6) TMR0L;
1440 extern __sfr __at (0xFD7) TMR0H;
1442 extern __sfr __at (0xFD8) STATUS;
1455 extern volatile __STATUSbits_t __at (0xFD8) STATUSbits;
1457 extern __sfr __at (0xFD9) FSR2L;
1459 extern __sfr __at (0xFDA) FSR2H;
1461 extern __sfr __at (0xFDB) PLUSW2;
1463 extern __sfr __at (0xFDC) PREINC2;
1465 extern __sfr __at (0xFDD) POSTDEC2;
1467 extern __sfr __at (0xFDE) POSTINC2;
1469 extern __sfr __at (0xFDF) INDF2;
1471 extern __sfr __at (0xFE0) BSR;
1473 extern __sfr __at (0xFE1) FSR1L;
1475 extern __sfr __at (0xFE2) FSR1H;
1477 extern __sfr __at (0xFE3) PLUSW1;
1479 extern __sfr __at (0xFE4) PREINC1;
1481 extern __sfr __at (0xFE5) POSTDEC1;
1483 extern __sfr __at (0xFE6) POSTINC1;
1485 extern __sfr __at (0xFE7) INDF1;
1487 extern __sfr __at (0xFE8) WREG;
1489 extern __sfr __at (0xFE9) FSR0L;
1491 extern __sfr __at (0xFEA) FSR0H;
1493 extern __sfr __at (0xFEB) PLUSW0;
1495 extern __sfr __at (0xFEC) PREINC0;
1497 extern __sfr __at (0xFED) POSTDEC0;
1499 extern __sfr __at (0xFEE) POSTINC0;
1501 extern __sfr __at (0xFEF) INDF0;
1503 extern __sfr __at (0xFF0) INTCON3;
1506 unsigned INT1IF : 1;
1507 unsigned INT2IF : 1;
1509 unsigned INT1IE : 1;
1510 unsigned INT2IE : 1;
1512 unsigned INT1IP : 1;
1513 unsigned INT2IP : 1;
1526 extern volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;
1528 extern __sfr __at (0xFF1) INTCON2;
1533 unsigned TMR0IP : 1;
1535 unsigned INTEDG2 : 1;
1536 unsigned INTEDG1 : 1;
1537 unsigned INTEDG0 : 1;
1538 unsigned NOT_RBPU : 1;
1551 extern volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;
1553 extern __sfr __at (0xFF2) INTCON;
1557 unsigned INT0IF : 1;
1558 unsigned TMR0IF : 1;
1560 unsigned INT0IE : 1;
1561 unsigned TMR0IE : 1;
1576 extern volatile __INTCONbits_t __at (0xFF2) INTCONbits;
1578 extern __sfr __at (0xFF3) PROD;
1580 extern __sfr __at (0xFF3) PRODL;
1582 extern __sfr __at (0xFF4) PRODH;
1584 extern __sfr __at (0xFF5) TABLAT;
1586 extern __sfr __at (0xFF6) TBLPTR;
1588 extern __sfr __at (0xFF6) TBLPTRL;
1590 extern __sfr __at (0xFF7) TBLPTRH;
1592 extern __sfr __at (0xFF8) TBLPTRU;
1594 extern __sfr __at (0xFF9) PC;
1596 extern __sfr __at (0xFF9) PCL;
1598 extern __sfr __at (0xFFA) PCLATH;
1600 extern __sfr __at (0xFFB) PCLATU;
1602 extern __sfr __at (0xFFC) STKPTR;
1605 unsigned STKPTR0 : 1;
1606 unsigned STKPTR1 : 1;
1607 unsigned STKPTR2 : 1;
1608 unsigned STKPTR3 : 1;
1609 unsigned STKPTR4 : 1;
1611 unsigned STKUNF : 1;
1612 unsigned STKFUL : 1;
1622 unsigned STKOVF : 1;
1625 extern volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;
1627 extern __sfr __at (0xFFD) TOS;
1629 extern __sfr __at (0xFFD) TOSL;
1631 extern __sfr __at (0xFFE) TOSH;
1633 extern __sfr __at (0xFFF) TOSU;