2 * pic18f4331.h - PIC18F4331 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * The GNU PIC Library is maintained by
8 * Raphael Neider <rneider@web.de>
10 * originally designed by
11 * Vangelis Rokas <vrokas@otenet.gr>
17 #ifndef __PIC18F4331_H__
18 #define __PIC18F4331_H__ 1
20 extern __sfr __at (0xF60) DFLTCON;
31 extern volatile __DFLTCON_t __at (0xF60) DFLTCONbits;
33 extern __sfr __at (0xF61) CAP3CON;
43 extern volatile __CAP3CON_t __at (0xF61) CAP3CONbits;
45 extern __sfr __at (0xF62) CAP2CON;
55 extern volatile __CAP2CON_t __at (0xF62) CAP2CONbits;
57 extern __sfr __at (0xF63) CAP1CON;
67 extern volatile __CAP1CON_t __at (0xF63) CAP1CONbits;
69 extern __sfr __at (0xF64) CAP3BUFL;
71 extern __sfr __at (0xF65) CAP3BUFH;
73 extern __sfr __at (0xF66) CAP2BUFL;
75 extern __sfr __at (0xF67) CAP2BUFH;
77 extern __sfr __at (0xF68) CAP1BUFL;
79 extern __sfr __at (0xF69) CAP1BUFH;
81 extern __sfr __at (0xF6A) OVDCONS;
87 extern volatile __OVDCONS_t __at (0xF6A) OVDCONSbits;
89 extern __sfr __at (0xF6B) OVDCOND;
95 extern volatile __OVDCOND_t __at (0xF6B) OVDCONDbits;
97 extern __sfr __at (0xF6C) FLTCONFIG;
101 unsigned FLTAMOD : 1;
105 unsigned FLTBMOD : 1;
110 extern volatile __FLTCONFIG_t __at (0xF6C) FLTCONFIGbits;
112 extern __sfr __at (0xF6D) DTCON;
119 extern volatile __DTCON_t __at (0xF6D) DTCONbits;
121 extern __sfr __at (0xF6E) PWMCON1;
127 unsigned SEVTDIR : 1;
131 extern volatile __PWMCON1_t __at (0xF6E) PWMCON1bits;
133 extern __sfr __at (0xF6F) PWMCON0;
141 extern volatile __PWMCON0_t __at (0xF6F) PWMCON0bits;
143 extern __sfr __at (0xF70) SEVTCMPH;
146 unsigned SEVTCMPH : 4;
153 extern volatile __SEVTCMPH_t __at (0xF70) SEVTCMPHbits;
155 extern __sfr __at (0xF71) SEVTCMPL;
157 extern __sfr __at (0xF72) PDC3H;
165 extern volatile __PDC3H_t __at (0xF72) PDC3Hbits;
167 extern __sfr __at (0xF73) PDC3L;
169 extern __sfr __at (0xF74) PDC2H;
177 extern volatile __PDC2H_t __at (0xF74) PDC2Hbits;
179 extern __sfr __at (0xF75) PDC2L;
181 extern __sfr __at (0xF76) PDC1H;
189 extern volatile __PDC1H_t __at (0xF76) PDC1Hbits;
191 extern __sfr __at (0xF77) PDC1L;
193 extern __sfr __at (0xF78) PDC0H;
201 extern volatile __PDC0H_t __at (0xF78) PDC0Hbits;
203 extern __sfr __at (0xF79) PDC0L;
205 extern __sfr __at (0xF7A) PTPERH;
215 extern volatile __PTPERH_t __at (0xF7A) PTPERHbits;
217 extern __sfr __at (0xF7B) PTPERL;
219 extern __sfr __at (0xF7C) PTMRH;
229 extern volatile __PTMRH_t __at (0xF7C) PTMRHbits;
231 extern __sfr __at (0xF7D) PTMRL;
233 extern __sfr __at (0xF7E) PTCON1;
246 extern volatile __PTCON1_t __at (0xF7E) PTCON1bits;
248 extern __sfr __at (0xF7F) PTCON0;
256 extern volatile __PTCON0_t __at (0xF7F) PTCON0bits;
258 extern __sfr __at (0xF80) PORTA;
295 extern volatile __PORTA_t __at (0xF80) PORTAbits;
297 extern __sfr __at (0xF81) PORTB;
324 extern volatile __PORTB_t __at (0xF81) PORTBbits;
326 extern __sfr __at (0xF82) PORTC;
363 extern volatile __PORTC_t __at (0xF82) PORTCbits;
365 extern __sfr __at (0xF83) PORTD;
392 extern volatile __PORTD_t __at (0xF83) PORTDbits;
394 extern __sfr __at (0xF84) PORTE;
421 extern volatile __PORTE_t __at (0xF84) PORTEbits;
423 extern __sfr __at (0xF87) TMR5L;
425 extern __sfr __at (0xF88) TMR5H;
427 extern __sfr __at (0xF89) LATA;
440 extern volatile __LATA_t __at (0xF89) LATAbits;
442 extern __sfr __at (0xF8A) LATB;
455 extern volatile __LATB_t __at (0xF8A) LATBbits;
457 extern __sfr __at (0xF8B) LATC;
470 extern volatile __LATC_t __at (0xF8B) LATCbits;
472 extern __sfr __at (0xF8C) LATD;
485 extern volatile __LATD_t __at (0xF8C) LATDbits;
487 extern __sfr __at (0xF8D) LATE;
500 extern volatile __LATE_t __at (0xF8D) LATEbits;
502 extern __sfr __at (0xF90) PR5L;
504 extern __sfr __at (0xF91) PR5H;
506 extern __sfr __at (0xF92) TRISA;
519 extern volatile __TRISA_t __at (0xF92) TRISAbits;
521 extern __sfr __at (0xF93) TRISB;
534 extern volatile __TRISB_t __at (0xF93) TRISBbits;
536 extern __sfr __at (0xF94) TRISC;
549 extern volatile __TRISC_t __at (0xF94) TRISCbits;
551 extern __sfr __at (0xF95) TRISD;
564 extern volatile __TRISD_t __at (0xF95) TRISDbits;
566 extern __sfr __at (0xF96) TRISE;
579 extern volatile __TRISE_t __at (0xF96) TRISEbits;
581 extern __sfr __at (0xF99) ADCHS;
590 extern volatile __ADCHS_t __at (0xF99) ADCHSbits;
592 extern __sfr __at (0xF9A) ADCON3;
600 extern volatile __ADCON3_t __at (0xF9A) ADCON3bits;
602 extern __sfr __at (0xF9B) OSCTUNE;
610 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
612 extern __sfr __at (0xF9D) PIE1;
625 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
627 extern __sfr __at (0xF9E) PIR1;
640 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
642 extern __sfr __at (0xF9F) IPR1;
655 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
657 extern __sfr __at (0xFA0) PIE2;
670 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
672 extern __sfr __at (0xFA1) PIR2;
685 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
687 extern __sfr __at (0xFA2) IPR2;
700 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
702 extern __sfr __at (0xFA3) PIE3;
707 unsigned IC2QEIE : 1;
708 unsigned IC3DRIE : 1;
715 extern volatile __PIE3_t __at (0xFA3) PIE3bits;
717 extern __sfr __at (0xFA4) PIR3;
722 unsigned IC2QEIF : 1;
723 unsigned IC3DRIF : 1;
730 extern volatile __PIR3_t __at (0xFA4) PIR3bits;
732 extern __sfr __at (0xFA5) IPR3;
737 unsigned IC2QEIP : 1;
738 unsigned IC3DRIP : 1;
745 extern volatile __IPR3_t __at (0xFA5) IPR3bits;
747 extern __sfr __at (0xFA6) EECON1;
760 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
762 extern __sfr __at (0xFA7) EECON2;
764 extern __sfr __at (0xFA8) EEDATA;
766 extern __sfr __at (0xFA9) EEADR;
768 extern __sfr __at (0xFAA) BAUDCTL;
781 extern volatile __BAUDCTL_t __at (0xFAA) BAUDCTLbits;
783 extern __sfr __at (0xFAB) RCSTA;
796 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
798 extern __sfr __at (0xFAC) TXSTA;
811 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
813 extern __sfr __at (0xFAD) TXREG;
815 extern __sfr __at (0xFAE) RCREG;
817 extern __sfr __at (0xFAF) SPBRG;
819 extern __sfr __at (0xFB0) SPBRGH;
821 extern __sfr __at (0xFB6) QEICON;
826 unsigned UP_nDOWN : 1;
831 extern volatile __QEICON_t __at (0xFB6) QEICONbits;
833 extern __sfr __at (0xFB7) T5CON;
838 unsigned nT5SYNC : 1;
845 extern volatile __T5CON_t __at (0xFB7) T5CONbits;
847 extern __sfr __at (0xFB8) ANSEL0;
860 extern volatile __ANSEL0_t __at (0xFB8) ANSEL0bits;
862 extern __sfr __at (0xFB9) ANSEL1;
875 extern volatile __ANSEL1_t __at (0xFB9) ANSEL1bits;
877 extern __sfr __at (0xFBA) CCP2CON;
886 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
888 extern __sfr __at (0xFBB) CCPR2L;
890 extern __sfr __at (0xFBC) CCPR2H;
892 extern __sfr __at (0xFBD) CCP1CON;
901 extern volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
903 extern __sfr __at (0xFBE) CCPR1L;
905 extern __sfr __at (0xFBF) CCPR1H;
907 extern __sfr __at (0xFC0) ADCON2;
915 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
917 extern __sfr __at (0xFC1) ADCON1;
928 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
930 extern __sfr __at (0xFC2) ADCON0;
934 unsigned GO_nDONE : 1;
942 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
944 extern __sfr __at (0xFC3) ADRESL;
946 extern __sfr __at (0xFC4) ADRESH;
948 extern __sfr __at (0xFC6) SSPCON;
958 extern volatile __SSPCON_t __at (0xFC6) SSPCONbits;
960 extern __sfr __at (0xFC7) SSPSTAT;
973 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
975 extern __sfr __at (0xFC8) SSPADD;
977 extern __sfr __at (0xFC9) SSPBUF;
979 extern __sfr __at (0xFCA) T2CON;
988 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
990 extern __sfr __at (0xFCB) PR2;
992 extern __sfr __at (0xFCC) TMR2;
994 extern __sfr __at (0xFCD) T1CON;
999 unsigned nT1SYNC : 1;
1000 unsigned T1OSCEN : 1;
1001 unsigned T1CKPS : 2;
1006 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
1008 extern __sfr __at (0xFCE) TMR1L;
1010 extern __sfr __at (0xFCF) TMR1H;
1012 extern __sfr __at (0xFD0) RCON;
1025 extern volatile __RCON_t __at (0xFD0) RCONbits;
1027 extern __sfr __at (0xFD1) WDTCON;
1030 unsigned SWDTEN : 1;
1034 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
1036 extern __sfr __at (0xFD2) LVDCON;
1046 extern volatile __LVDCON_t __at (0xFD2) LVDCONbits;
1048 extern __sfr __at (0xFD3) OSCCON;
1058 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
1060 extern __sfr __at (0xFD5) T0CON;
1066 unsigned _16BIT : 1;
1067 unsigned TMR0ON : 1;
1070 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
1072 extern __sfr __at (0xFD6) TMR0L;
1074 extern __sfr __at (0xFD7) TMR0H;
1076 extern __sfr __at (0xFD8) STATUS;
1089 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
1091 extern __sfr __at (0xFD9) FSR2L;
1093 extern __sfr __at (0xFDA) FSR2H;
1103 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
1105 extern __sfr __at (0xFDB) PLUSW2;
1107 extern __sfr __at (0xFDC) PREINC2;
1109 extern __sfr __at (0xFDD) POSTDEC2;
1111 extern __sfr __at (0xFDE) POSTINC2;
1113 extern __sfr __at (0xFDF) INDF2;
1115 extern __sfr __at (0xFE0) BSR;
1125 extern volatile __BSR_t __at (0xFE0) BSRbits;
1127 extern __sfr __at (0xFE1) FSR1L;
1129 extern __sfr __at (0xFE2) FSR1H;
1139 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
1141 extern __sfr __at (0xFE3) PLUSW1;
1143 extern __sfr __at (0xFE4) PREINC1;
1145 extern __sfr __at (0xFE5) POSTDEC1;
1147 extern __sfr __at (0xFE6) POSTINC1;
1149 extern __sfr __at (0xFE7) INDF1;
1151 extern __sfr __at (0xFE8) WREG;
1153 extern __sfr __at (0xFE9) FSR0L;
1155 extern __sfr __at (0xFEA) FSR0H;
1165 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
1167 extern __sfr __at (0xFEB) PLUSW0;
1169 extern __sfr __at (0xFEC) PREINC0;
1171 extern __sfr __at (0xFED) POSTDEC0;
1173 extern __sfr __at (0xFEE) POSTINC0;
1175 extern __sfr __at (0xFEF) INDF0;
1177 extern __sfr __at (0xFF0) INTCON3;
1180 unsigned INT1IF : 1;
1181 unsigned INT2IF : 1;
1183 unsigned INT1IE : 1;
1184 unsigned INT2IE : 1;
1186 unsigned INT1IP : 1;
1187 unsigned INT2IP : 1;
1190 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
1192 extern __sfr __at (0xFF1) INTCON2;
1197 unsigned TMR0IP : 1;
1199 unsigned INTEDG2 : 1;
1200 unsigned INTEDG1 : 1;
1201 unsigned INTEDG0 : 1;
1205 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
1207 extern __sfr __at (0xFF2) INTCON;
1211 unsigned INT0IF : 1;
1212 unsigned TMR0IF : 1;
1214 unsigned INT0IE : 1;
1215 unsigned TMR0IE : 1;
1216 unsigned PEIE_GIEL : 1;
1217 unsigned GIE_GIEH : 1;
1240 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
1242 extern __sfr __at (0xFF3) PRODL;
1244 extern __sfr __at (0xFF4) PRODH;
1246 extern __sfr __at (0xFF5) TABLAT;
1248 extern __sfr __at (0xFF6) TBLPTRL;
1250 extern __sfr __at (0xFF7) TBLPTRH;
1252 extern __sfr __at (0xFF8) TBLPTRU;
1255 unsigned TBLPTRU : 5;
1261 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
1263 extern __sfr __at (0xFF9) PCL;
1265 extern __sfr __at (0xFFA) PCLATH;
1271 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
1273 extern __sfr __at (0xFFB) PCLATU;
1282 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1284 extern __sfr __at (0xFFC) STKPTR;
1287 unsigned STKPTR : 5;
1289 unsigned STKUNF : 1;
1290 unsigned STKFUL : 1;
1293 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1295 extern __sfr __at (0xFFD) TOSL;
1297 extern __sfr __at (0xFFE) TOSH;
1299 extern __sfr __at (0xFFF) TOSU;
1308 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1310 /* Configuration register locations */
1311 #define CONFIG1H 0x300001
1312 #define CONFIG2L 0x300002
1313 #define CONFIG2H 0x300003
1314 #define CONFIG3L 0x300004
1315 #define CONFIG3H 0x300005
1316 #define CONFIG4L 0x300006
1317 #define CONFIG5L 0x300008
1318 #define CONFIG5H 0x300009
1319 #define CONFIG6L 0x30000A
1320 #define CONFIG6H 0x30000B
1321 #define CONFIG7L 0x30000C
1322 #define CONFIG7H 0x30000D
1325 /* Oscillator 1H options */
1326 #define _OSC_11XX_EXT_RC_CLKOUT_ON_RA6_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
1327 #define _OSC_101X_EXT_RC_CLKOUT_ON_RA6_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
1328 #define _OSC_INT_RC_CLKOUT_ON_RA6_PORT_ON_RA7_1H 0xF9 /* INT RC-CLKOUT on RA6,Port on RA7 */
1329 #define _OSC_INT_RC_PORT_ON_RA6_PORT_ON_RA7_1H 0xF8 /* INT RC-Port on RA6,Port on RA7 */
1330 #define _OSC_EXT_RC_PORT_ON_RA6_1H 0xF7 /* EXT RC-Port on RA6 */
1331 #define _OSC_HS_PLL_ON_FREQ_4XFOSC1_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
1332 #define _OSC_EC_PORT_ON_RA6_1H 0xF5 /* EC-Port on RA6 */
1333 #define _OSC_EC_CLKOUT_ON_RA6_1H 0xF4 /* EC-CLKOUT on RA6 */
1334 #define _OSC_0011_EXT_RC_CLKOUT_ON_RA6_1H 0xF3 /* 0011 EXT RC-CLKOUT on RA6 */
1335 #define _OSC_HS_1H 0xF2 /* HS */
1336 #define _OSC_XT_1H 0xF1 /* XT */
1337 #define _OSC_LP_1H 0xF0 /* LP */
1339 /* Fail-Safe Clock Monitor Enable 1H options */
1340 #define _FCMEN_ON_1H 0xFF /* Enabled */
1341 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1343 /* Internal External Switch Over Mode 1H options */
1344 #define _IESO_OFF_1H 0x7F /* Disabled */
1345 #define _IESO_ON_1H 0xFF /* Enabled */
1348 /* Power Up Timer 2L options */
1349 #define _PUT_OFF_2L 0xFF /* Disabled */
1350 #define _PUT_ON_2L 0xFE /* Enabled */
1352 /* Brown Out Detect 2L options */
1353 #define _BODEN_ON_2L 0xFF /* Enabled */
1354 #define _BODEN_OFF_2L 0xFD /* Disabled */
1356 /* Brown Out Voltage 2L options */
1357 #define _BODENV_UNDEFINED_2L 0xFF /* Undefined */
1358 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
1359 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
1360 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
1363 /* Watchdog Timer 2H options */
1364 #define _WDT_ON_2H 0xFF /* Enabled */
1365 #define _WDT_OFF_2H 0xFE /* Disabled */
1367 /* Watchdog Postscaler 2H options */
1368 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1369 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1370 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1371 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1372 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1373 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1374 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1375 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1376 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1377 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1378 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1379 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1380 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1381 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1382 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1383 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1385 /* Watchdog Timer Window 2H options */
1386 #define _WINEN_OFF_2H 0xFF /* Disabled */
1387 #define _WINEN_ON_2H 0xDF /* Enabled */
1390 /* PWM Output Pin Reset 3L options */
1391 #define _PWMPIN_PWM_OUTPUTS_OFF_UPON_RESET_3L 0xFF /* PWM outputs disabled upon RESET */
1392 #define _PWMPIN_PWM_OUTPUTS_DRIVE_ACTIVE_STATES_UPON_RESET_3L 0xFB /* PWM outputs drive active states upon RESET */
1394 /* Low-Side Transistors Polarity 3L options */
1395 #define _LPOL_PWM_0__2__4_AND_6_ARE_ACTIVE_HIGH_3L 0xFF /* PWM 0, 2, 4 and 6 are active high */
1396 #define _LPOL_PWM_0__2__4_AND_6_ARE_ACTIVE_LOW_3L 0xF7 /* PWM 0, 2, 4 and 6 are active low */
1398 /* High-Side Transistors Polarity 3L options */
1399 #define _HPOL_PWM_1__3__5__AND_7_ARE_ACTIVE_HIGH_3L 0xFF /* PWM 1, 3, 5, and 7 are active high */
1400 #define _HPOL_PWM_1__3__5__AND_7_ARE_ACTIVE_LOW_3L 0xEF /* PWM 1, 3, 5, and 7 are active low */
1402 /* Timer1 OSC 3L options */
1403 #define _T1OSCMX_LOW_POWER_3L 0xFF /* Low Power */
1404 #define _T1OSCMX_LEGACY_3L 0xDF /* Legacy */
1407 /* FLTA Mux 3H options */
1408 #define _FLTAMX_FLTA_INPUT_MUXED_WITH_RC1_3H 0xFF /* FLTA input muxed with RC1 */
1409 #define _FLTAMX_FLTA_INPUT_MUXED_WITH_RD4_3H 0xFE /* FLTA input muxed with RD4 */
1411 /* SSP I/O Mux 3H options */
1412 #define _SSPMX_SCK_SCL__SDA_SDI_AND_SDO_ARE_MUX_W__RD3__RD2_AND_RD1_RESPECTIVELY__3H 0xFB /* SCK/SCL, SDA/SDI and SDO are mux w/ RD3, RD2 and RD1 respectively. */
1413 #define _SSPMX_SCK_SCL__SDA_SDI_AND_SDO_ARE_MUX_W__RC5__RC4_AND_RC7_RESPECTIVELY__3H 0xFF /* SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively. */
1415 /* PWM4 Mux 3H options */
1416 #define _PWM4MX_PWM4_OUTPUT_MUXED_W__RB5_3H 0xFF /* PWM4 output muxed w/ RB5 */
1417 #define _PWM4MX_PWM4_OUTPUT_MUXED_W__RD5_3H 0xF7 /* PWM4 output muxed w/ RD5 */
1419 /* TMR0/T5CKI EXT CLK Mux 3H options */
1420 #define _EXCLKMX_TMR0_T5CKI_EXTERNAL_CLOCK_INPUT_IS_MULTIPLEXED_WITH_RD0_3H 0xEF /* TMR0/T5CKI external clock input is multiplexed with RD0 */
1421 #define _EXCLKMX_TMR0_T5CKI_EXTERNAL_CLOCK_INPUT_IS_MULTIPLEXED_WITH_RC3_3H 0xFF /* TMR0/T5CKI external clock input is multiplexed with RC3 */
1423 /* Master Clear Enable 3H options */
1424 #define _MCLRE_MCLR_ON__RE3_INPUT_OFF_3H 0xFF /* MCLR enabled, RE3 input disabled */
1425 #define _MCLRE_RE3_INPUT_ON__MCLR_OFF_3H 0x7F /* RE3 input enabled, MCLR disabled */
1428 /* Background Debug 4L options */
1429 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1430 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1432 /* Low Voltage Program 4L options */
1433 #define _LVP_ON_4L 0xFF /* Enabled */
1434 #define _LVP_OFF_4L 0xFB /* Disabled */
1436 /* Stack Overflow Reset 4L options */
1437 #define _STVR_ON_4L 0xFF /* Enabled */
1438 #define _STVR_OFF_4L 0xFE /* Disabled */
1441 /* Code Protect 00200-00FFF 5L options */
1442 #define _CP_0_OFF_5L 0xFF /* Disabled */
1443 #define _CP_0_ON_5L 0xFE /* Enabled */
1445 /* Code Protect 01000-01FFF 5L options */
1446 #define _CP_1_OFF_5L 0xFF /* Disabled */
1447 #define _CP_1_ON_5L 0xFD /* Enabled */
1449 /* Code Protect 02000-02FFF 5L options */
1450 #define _CP_2_OFF_5L 0xFF /* Disabled */
1451 #define _CP_2_ON_5L 0xFB /* Enabled */
1453 /* Code Protect 03000-03FFF 5L options */
1454 #define _CP_3_OFF_5L 0xFF /* Disabled */
1455 #define _CP_3_ON_5L 0xF7 /* Enabled */
1458 /* Data EE Read Protect 5H options */
1459 #define _CPD_OFF_5H 0xFF /* Disabled */
1460 #define _CPD_ON_5H 0x7F /* Enabled */
1462 /* Code Protect Boot 5H options */
1463 #define _CPB_OFF_5H 0xFF /* Disabled */
1464 #define _CPB_ON_5H 0xBF /* Enabled */
1467 /* Table Write Protect 00200-00FFF 6L options */
1468 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1469 #define _WRT_0_ON_6L 0xFE /* Enabled */
1471 /* Table Write Protect 01000-01FFF 6L options */
1472 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1473 #define _WRT_1_ON_6L 0xFD /* Enabled */
1475 /* Table Write Protect 02000-02FFF 6L options */
1476 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1477 #define _WRT_2_ON_6L 0xFB /* Enabled */
1479 /* Table Write Protect 03000-03FFF 6L options */
1480 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1481 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1484 /* Data EE Write Protect 6H options */
1485 #define _WRTD_OFF_6H 0xFF /* Disabled */
1486 #define _WRTD_ON_6H 0x7F /* Enabled */
1488 /* Table Write Protect Boot 6H options */
1489 #define _WRTB_OFF_6H 0xFF /* Disabled */
1490 #define _WRTB_ON_6H 0xBF /* Enabled */
1492 /* Config. Write Protect 6H options */
1493 #define _WRTC_OFF_6H 0xFF /* Disabled */
1494 #define _WRTC_ON_6H 0xDF /* Enabled */
1497 /* Table Read Protect 00200-00FFF 7L options */
1498 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1499 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1501 /* Table Read Protect 01000-01FFF 7L options */
1502 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1503 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1505 /* Table Read Protect 02000-02FFF 7L options */
1506 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1507 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1509 /* Table Read Protect 03000-03FFF 7L options */
1510 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1511 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1514 /* Table Read Protect Boot 7H options */
1515 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1516 #define _EBTRB_ON_7H 0xBF /* Enabled */
1520 /* Location of User ID words */
1521 #define __IDLOC0 0x200000
1522 #define __IDLOC1 0x200001
1523 #define __IDLOC2 0x200002
1524 #define __IDLOC3 0x200003
1525 #define __IDLOC4 0x200004
1526 #define __IDLOC5 0x200005
1527 #define __IDLOC6 0x200006
1528 #define __IDLOC7 0x200007
1530 #endif // __PIC18F4331__