2 * pic18f4331.h - PIC18F4331 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * The GNU PIC Library is maintained by
8 * Raphael Neider <rneider@web.de>
10 * originally designed by
11 * Vangelis Rokas <vrokas@otenet.gr>
17 #ifndef __PIC18F4331_H__
18 #define __PIC18F4331_H__ 1
20 extern __sfr __at (0xF60) DFLTCON;
33 extern volatile __DFLTCON_t __at (0xF60) DFLTCONbits;
35 extern __sfr __at (0xF61) CAP3CON;
48 extern volatile __CAP3CON_t __at (0xF61) CAP3CONbits;
50 extern __sfr __at (0xF62) CAP2CON;
63 extern volatile __CAP2CON_t __at (0xF62) CAP2CONbits;
65 extern __sfr __at (0xF63) CAP1CON;
78 extern volatile __CAP1CON_t __at (0xF63) CAP1CONbits;
80 extern __sfr __at (0xF64) CAP3BUFL;
82 extern __sfr __at (0xF65) CAP3BUFH;
84 extern __sfr __at (0xF66) CAP2BUFL;
86 extern __sfr __at (0xF67) CAP2BUFH;
88 extern __sfr __at (0xF68) CAP1BUFL;
90 extern __sfr __at (0xF69) CAP1BUFH;
92 extern __sfr __at (0xF6A) OVDCONS;
98 extern volatile __OVDCONS_t __at (0xF6A) OVDCONSbits;
100 extern __sfr __at (0xF6B) OVDCOND;
106 extern volatile __OVDCOND_t __at (0xF6B) OVDCONDbits;
108 extern __sfr __at (0xF6C) FLTCONFIG;
112 unsigned FLTAMOD : 1;
116 unsigned FLTBMOD : 1;
121 extern volatile __FLTCONFIG_t __at (0xF6C) FLTCONFIGbits;
123 extern __sfr __at (0xF6D) DTCON;
131 extern volatile __DTCON_t __at (0xF6D) DTCONbits;
133 extern __sfr __at (0xF6E) PWMCON1;
139 unsigned SEVTDIR : 1;
140 unsigned SEVOPS0 : 1;
141 unsigned SEVOPS1 : 1;
142 unsigned SEVOPS2 : 1;
143 unsigned SEVOPS3 : 1;
146 extern volatile __PWMCON1_t __at (0xF6E) PWMCON1bits;
148 extern __sfr __at (0xF6F) PWMCON0;
161 extern volatile __PWMCON0_t __at (0xF6F) PWMCON0bits;
163 extern __sfr __at (0xF70) SEVTCMPH;
166 unsigned SEVTCMPH : 4;
173 extern volatile __SEVTCMPH_t __at (0xF70) SEVTCMPHbits;
175 extern __sfr __at (0xF71) SEVTCMPL;
177 extern __sfr __at (0xF72) PDC3H;
185 extern volatile __PDC3H_t __at (0xF72) PDC3Hbits;
187 extern __sfr __at (0xF73) PDC3L;
189 extern __sfr __at (0xF74) PDC2H;
197 extern volatile __PDC2H_t __at (0xF74) PDC2Hbits;
199 extern __sfr __at (0xF75) PDC2L;
201 extern __sfr __at (0xF76) PDC1H;
209 extern volatile __PDC1H_t __at (0xF76) PDC1Hbits;
211 extern __sfr __at (0xF77) PDC1L;
213 extern __sfr __at (0xF78) PDC0H;
221 extern volatile __PDC0H_t __at (0xF78) PDC0Hbits;
223 extern __sfr __at (0xF79) PDC0L;
225 extern __sfr __at (0xF7A) PTPERH;
235 extern volatile __PTPERH_t __at (0xF7A) PTPERHbits;
237 extern __sfr __at (0xF7B) PTPERL;
239 extern __sfr __at (0xF7C) PTMRH;
249 extern volatile __PTMRH_t __at (0xF7C) PTMRHbits;
251 extern __sfr __at (0xF7D) PTMRL;
253 extern __sfr __at (0xF7E) PTCON1;
266 extern volatile __PTCON1_t __at (0xF7E) PTCON1bits;
268 extern __sfr __at (0xF7F) PTCON0;
273 unsigned PTCKPS0 : 1;
274 unsigned PTCKPS1 : 1;
281 extern volatile __PTCON0_t __at (0xF7F) PTCON0bits;
283 extern __sfr __at (0xF80) PORTA;
320 extern volatile __PORTA_t __at (0xF80) PORTAbits;
322 extern __sfr __at (0xF81) PORTB;
349 extern volatile __PORTB_t __at (0xF81) PORTBbits;
351 extern __sfr __at (0xF82) PORTC;
388 extern volatile __PORTC_t __at (0xF82) PORTCbits;
390 extern __sfr __at (0xF83) PORTD;
417 extern volatile __PORTD_t __at (0xF83) PORTDbits;
419 extern __sfr __at (0xF84) PORTE;
446 extern volatile __PORTE_t __at (0xF84) PORTEbits;
448 extern __sfr __at (0xF87) TMR5L;
450 extern __sfr __at (0xF88) TMR5H;
452 extern __sfr __at (0xF89) LATA;
465 extern volatile __LATA_t __at (0xF89) LATAbits;
467 extern __sfr __at (0xF8A) LATB;
480 extern volatile __LATB_t __at (0xF8A) LATBbits;
482 extern __sfr __at (0xF8B) LATC;
495 extern volatile __LATC_t __at (0xF8B) LATCbits;
497 extern __sfr __at (0xF8C) LATD;
510 extern volatile __LATD_t __at (0xF8C) LATDbits;
512 extern __sfr __at (0xF8D) LATE;
525 extern volatile __LATE_t __at (0xF8D) LATEbits;
527 extern __sfr __at (0xF90) PR5L;
529 extern __sfr __at (0xF91) PR5H;
531 extern __sfr __at (0xF92) TRISA;
544 extern volatile __TRISA_t __at (0xF92) TRISAbits;
546 extern __sfr __at (0xF93) TRISB;
559 extern volatile __TRISB_t __at (0xF93) TRISBbits;
561 extern __sfr __at (0xF94) TRISC;
574 extern volatile __TRISC_t __at (0xF94) TRISCbits;
576 extern __sfr __at (0xF95) TRISD;
589 extern volatile __TRISD_t __at (0xF95) TRISDbits;
591 extern __sfr __at (0xF96) TRISE;
604 extern volatile __TRISE_t __at (0xF96) TRISEbits;
606 extern __sfr __at (0xF99) ADCHS;
619 extern volatile __ADCHS_t __at (0xF99) ADCHSbits;
621 extern __sfr __at (0xF9A) ADCON3;
629 extern volatile __ADCON3_t __at (0xF9A) ADCON3bits;
631 extern __sfr __at (0xF9B) OSCTUNE;
639 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
641 extern __sfr __at (0xF9D) PIE1;
654 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
656 extern __sfr __at (0xF9E) PIR1;
669 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
671 extern __sfr __at (0xF9F) IPR1;
684 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
686 extern __sfr __at (0xFA0) PIE2;
699 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
701 extern __sfr __at (0xFA1) PIR2;
714 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
716 extern __sfr __at (0xFA2) IPR2;
729 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
731 extern __sfr __at (0xFA3) PIE3;
736 unsigned IC2QEIE : 1;
737 unsigned IC3DRIE : 1;
744 extern volatile __PIE3_t __at (0xFA3) PIE3bits;
746 extern __sfr __at (0xFA4) PIR3;
751 unsigned IC2QEIF : 1;
752 unsigned IC3DRIF : 1;
759 extern volatile __PIR3_t __at (0xFA4) PIR3bits;
761 extern __sfr __at (0xFA5) IPR3;
766 unsigned IC2QEIP : 1;
767 unsigned IC3DRIP : 1;
774 extern volatile __IPR3_t __at (0xFA5) IPR3bits;
776 extern __sfr __at (0xFA6) EECON1;
789 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
791 extern __sfr __at (0xFA7) EECON2;
793 extern __sfr __at (0xFA8) EEDATA;
795 extern __sfr __at (0xFA9) EEADR;
797 extern __sfr __at (0xFAA) BAUDCTL;
810 extern volatile __BAUDCTL_t __at (0xFAA) BAUDCTLbits;
812 extern __sfr __at (0xFAB) RCSTA;
825 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
827 extern __sfr __at (0xFAC) TXSTA;
840 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
842 extern __sfr __at (0xFAD) TXREG;
844 extern __sfr __at (0xFAE) RCREG;
846 extern __sfr __at (0xFAF) SPBRG;
848 extern __sfr __at (0xFB0) SPBRGH;
850 extern __sfr __at (0xFB6) QEICON;
855 unsigned UP_DOWN : 1;
860 extern volatile __QEICON_t __at (0xFB6) QEICONbits;
862 extern __sfr __at (0xFB7) T5CON;
867 unsigned NOT_T5SYNC : 1;
875 extern volatile __T5CON_t __at (0xFB7) T5CONbits;
877 extern __sfr __at (0xFB8) ANSEL0;
890 extern volatile __ANSEL0_t __at (0xFB8) ANSEL0bits;
892 extern __sfr __at (0xFB9) ANSEL1;
905 extern volatile __ANSEL1_t __at (0xFB9) ANSEL1bits;
907 extern __sfr __at (0xFBA) CCP2CON;
920 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
922 extern __sfr __at (0xFBB) CCPR2L;
924 extern __sfr __at (0xFBC) CCPR2H;
926 extern __sfr __at (0xFBD) CCP1CON;
939 extern volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
941 extern __sfr __at (0xFBE) CCPR1L;
943 extern __sfr __at (0xFBF) CCPR1H;
945 extern __sfr __at (0xFC0) ADCON2;
958 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
960 extern __sfr __at (0xFC1) ADCON1;
973 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
975 extern __sfr __at (0xFC2) ADCON0;
988 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
990 extern __sfr __at (0xFC3) ADRESL;
992 extern __sfr __at (0xFC4) ADRESH;
994 extern __sfr __at (0xFC6) SSPCON;
1007 extern volatile __SSPCON_t __at (0xFC6) SSPCONbits;
1009 extern __sfr __at (0xFC7) SSPSTAT;
1022 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
1024 extern __sfr __at (0xFC8) SSPADD;
1026 extern __sfr __at (0xFC9) SSPBUF;
1028 extern __sfr __at (0xFCA) T2CON;
1031 unsigned T2CKPS0 : 1;
1032 unsigned T2CKPS1 : 1;
1033 unsigned TMR2ON : 1;
1034 unsigned TOUTPS0 : 1;
1035 unsigned TOUTPS1 : 1;
1036 unsigned TOUTPS2 : 1;
1037 unsigned TOUTPS3 : 1;
1041 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
1043 extern __sfr __at (0xFCB) PR2;
1045 extern __sfr __at (0xFCC) TMR2;
1047 extern __sfr __at (0xFCD) T1CON;
1050 unsigned TMR1ON : 1;
1051 unsigned TMR1CS : 1;
1052 unsigned NOT_T1SYNC : 1;
1053 unsigned T1OSCEN : 1;
1054 unsigned T1CKPS0 : 1;
1055 unsigned T1CKPS1 : 1;
1060 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
1062 extern __sfr __at (0xFCE) TMR1L;
1064 extern __sfr __at (0xFCF) TMR1H;
1066 extern __sfr __at (0xFD0) RCON;
1079 extern volatile __RCON_t __at (0xFD0) RCONbits;
1081 extern __sfr __at (0xFD1) WDTCON;
1084 unsigned SWDTEN : 1;
1088 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
1090 extern __sfr __at (0xFD2) LVDCON;
1103 extern volatile __LVDCON_t __at (0xFD2) LVDCONbits;
1105 extern __sfr __at (0xFD3) OSCCON;
1115 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
1117 extern __sfr __at (0xFD5) T0CON;
1126 unsigned _16BIT : 1;
1127 unsigned TMR0ON : 1;
1130 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
1132 extern __sfr __at (0xFD6) TMR0L;
1134 extern __sfr __at (0xFD7) TMR0H;
1136 extern __sfr __at (0xFD8) STATUS;
1149 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
1151 extern __sfr __at (0xFD9) FSR2L;
1153 extern __sfr __at (0xFDA) FSR2H;
1163 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
1165 extern __sfr __at (0xFDB) PLUSW2;
1167 extern __sfr __at (0xFDC) PREINC2;
1169 extern __sfr __at (0xFDD) POSTDEC2;
1171 extern __sfr __at (0xFDE) POSTINC2;
1173 extern __sfr __at (0xFDF) INDF2;
1175 extern __sfr __at (0xFE0) BSR;
1185 extern volatile __BSR_t __at (0xFE0) BSRbits;
1187 extern __sfr __at (0xFE1) FSR1L;
1189 extern __sfr __at (0xFE2) FSR1H;
1199 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
1201 extern __sfr __at (0xFE3) PLUSW1;
1203 extern __sfr __at (0xFE4) PREINC1;
1205 extern __sfr __at (0xFE5) POSTDEC1;
1207 extern __sfr __at (0xFE6) POSTINC1;
1209 extern __sfr __at (0xFE7) INDF1;
1211 extern __sfr __at (0xFE8) WREG;
1213 extern __sfr __at (0xFE9) FSR0L;
1215 extern __sfr __at (0xFEA) FSR0H;
1225 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
1227 extern __sfr __at (0xFEB) PLUSW0;
1229 extern __sfr __at (0xFEC) PREINC0;
1231 extern __sfr __at (0xFED) POSTDEC0;
1233 extern __sfr __at (0xFEE) POSTINC0;
1235 extern __sfr __at (0xFEF) INDF0;
1237 extern __sfr __at (0xFF0) INTCON3;
1240 unsigned INT1IF : 1;
1241 unsigned INT2IF : 1;
1243 unsigned INT1IE : 1;
1244 unsigned INT2IE : 1;
1246 unsigned INT1IP : 1;
1247 unsigned INT2IP : 1;
1250 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
1252 extern __sfr __at (0xFF1) INTCON2;
1257 unsigned TMR0IP : 1;
1259 unsigned INTEDG2 : 1;
1260 unsigned INTEDG1 : 1;
1261 unsigned INTEDG0 : 1;
1265 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
1267 extern __sfr __at (0xFF2) INTCON;
1271 unsigned INT0IF : 1;
1272 unsigned TMR0IF : 1;
1274 unsigned INT0IE : 1;
1275 unsigned TMR0IE : 1;
1276 unsigned PEIE_GIEL : 1;
1277 unsigned GIE_GIEH : 1;
1300 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
1302 extern __sfr __at (0xFF3) PRODL;
1304 extern __sfr __at (0xFF4) PRODH;
1306 extern __sfr __at (0xFF5) TABLAT;
1308 extern __sfr __at (0xFF6) TBLPTRL;
1310 extern __sfr __at (0xFF7) TBLPTRH;
1312 extern __sfr __at (0xFF8) TBLPTRU;
1315 unsigned TBLPTRU : 5;
1321 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
1323 extern __sfr __at (0xFF9) PCL;
1325 extern __sfr __at (0xFFA) PCLATH;
1331 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
1333 extern __sfr __at (0xFFB) PCLATU;
1342 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1344 extern __sfr __at (0xFFC) STKPTR;
1347 unsigned STKPTR : 5;
1349 unsigned STKUNF : 1;
1350 unsigned STKFUL : 1;
1353 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1355 extern __sfr __at (0xFFD) TOSL;
1357 extern __sfr __at (0xFFE) TOSH;
1359 extern __sfr __at (0xFFF) TOSU;
1368 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1370 /* Configuration register locations */
1371 #define __CONFIG1H 0x300001
1372 #define __CONFIG2L 0x300002
1373 #define __CONFIG2H 0x300003
1374 #define __CONFIG3L 0x300004
1375 #define __CONFIG3H 0x300005
1376 #define __CONFIG4L 0x300006
1377 #define __CONFIG5L 0x300008
1378 #define __CONFIG5H 0x300009
1379 #define __CONFIG6L 0x30000A
1380 #define __CONFIG6H 0x30000B
1381 #define __CONFIG7L 0x30000C
1382 #define __CONFIG7H 0x30000D
1385 /* Oscillator 1H options */
1386 #define _OSC_11XX_EXT_RC_CLKOUT_ON_RA6_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
1387 #define _OSC_101X_EXT_RC_CLKOUT_ON_RA6_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
1388 #define _OSC_INT_RC_CLKOUT_ON_RA6_PORT_ON_RA7_1H 0xF9 /* INT RC-CLKOUT on RA6,Port on RA7 */
1389 #define _OSC_INT_RC_PORT_ON_RA6_PORT_ON_RA7_1H 0xF8 /* INT RC-Port on RA6,Port on RA7 */
1390 #define _OSC_EXT_RC_PORT_ON_RA6_1H 0xF7 /* EXT RC-Port on RA6 */
1391 #define _OSC_HS_PLL_ON_FREQ_4XFOSC1_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
1392 #define _OSC_EC_PORT_ON_RA6_1H 0xF5 /* EC-Port on RA6 */
1393 #define _OSC_EC_CLKOUT_ON_RA6_1H 0xF4 /* EC-CLKOUT on RA6 */
1394 #define _OSC_0011_EXT_RC_CLKOUT_ON_RA6_1H 0xF3 /* 0011 EXT RC-CLKOUT on RA6 */
1395 #define _OSC_HS_1H 0xF2 /* HS */
1396 #define _OSC_XT_1H 0xF1 /* XT */
1397 #define _OSC_LP_1H 0xF0 /* LP */
1399 /* Fail-Safe Clock Monitor Enable 1H options */
1400 #define _FCMEN_ON_1H 0xFF /* Enabled */
1401 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1403 /* Internal External Switch Over Mode 1H options */
1404 #define _IESO_OFF_1H 0x7F /* Disabled */
1405 #define _IESO_ON_1H 0xFF /* Enabled */
1408 /* Power Up Timer 2L options */
1409 #define _PUT_OFF_2L 0xFF /* Disabled */
1410 #define _PUT_ON_2L 0xFE /* Enabled */
1412 /* Brown Out Detect 2L options */
1413 #define _BODEN_ON_2L 0xFF /* Enabled */
1414 #define _BODEN_OFF_2L 0xFD /* Disabled */
1416 /* Brown Out Voltage 2L options */
1417 #define _BODENV_UNDEFINED_2L 0xFF /* Undefined */
1418 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
1419 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
1420 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
1423 /* Watchdog Timer 2H options */
1424 #define _WDT_ON_2H 0xFF /* Enabled */
1425 #define _WDT_OFF_2H 0xFE /* Disabled */
1427 /* Watchdog Postscaler 2H options */
1428 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1429 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1430 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1431 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1432 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1433 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1434 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1435 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1436 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1437 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1438 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1439 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1440 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1441 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1442 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1443 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1445 /* Watchdog Timer Window 2H options */
1446 #define _WINEN_OFF_2H 0xFF /* Disabled */
1447 #define _WINEN_ON_2H 0xDF /* Enabled */
1450 /* PWM Output Pin Reset 3L options */
1451 #define _PWMPIN_PWM_OUTPUTS_OFF_UPON_RESET_3L 0xFF /* PWM outputs disabled upon RESET */
1452 #define _PWMPIN_PWM_OUTPUTS_DRIVE_ACTIVE_STATES_UPON_RESET_3L 0xFB /* PWM outputs drive active states upon RESET */
1454 /* Low-Side Transistors Polarity 3L options */
1455 #define _LPOL_PWM_0__2__4_AND_6_ARE_ACTIVE_HIGH_3L 0xFF /* PWM 0, 2, 4 and 6 are active high */
1456 #define _LPOL_PWM_0__2__4_AND_6_ARE_ACTIVE_LOW_3L 0xF7 /* PWM 0, 2, 4 and 6 are active low */
1458 /* High-Side Transistors Polarity 3L options */
1459 #define _HPOL_PWM_1__3__5__AND_7_ARE_ACTIVE_HIGH_3L 0xFF /* PWM 1, 3, 5, and 7 are active high */
1460 #define _HPOL_PWM_1__3__5__AND_7_ARE_ACTIVE_LOW_3L 0xEF /* PWM 1, 3, 5, and 7 are active low */
1462 /* Timer1 OSC 3L options */
1463 #define _T1OSCMX_LOW_POWER_3L 0xFF /* Low Power */
1464 #define _T1OSCMX_LEGACY_3L 0xDF /* Legacy */
1467 /* FLTA Mux 3H options */
1468 #define _FLTAMX_FLTA_INPUT_MUXED_WITH_RC1_3H 0xFF /* FLTA input muxed with RC1 */
1469 #define _FLTAMX_FLTA_INPUT_MUXED_WITH_RD4_3H 0xFE /* FLTA input muxed with RD4 */
1471 /* SSP I/O Mux 3H options */
1472 #define _SSPMX_SCK_SCL__SDA_SDI_AND_SDO_ARE_MUX_W__RD3__RD2_AND_RD1_RESPECTIVELY__3H 0xFB /* SCK/SCL, SDA/SDI and SDO are mux w/ RD3, RD2 and RD1 respectively. */
1473 #define _SSPMX_SCK_SCL__SDA_SDI_AND_SDO_ARE_MUX_W__RC5__RC4_AND_RC7_RESPECTIVELY__3H 0xFF /* SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively. */
1475 /* PWM4 Mux 3H options */
1476 #define _PWM4MX_PWM4_OUTPUT_MUXED_W__RB5_3H 0xFF /* PWM4 output muxed w/ RB5 */
1477 #define _PWM4MX_PWM4_OUTPUT_MUXED_W__RD5_3H 0xF7 /* PWM4 output muxed w/ RD5 */
1479 /* TMR0/T5CKI EXT CLK Mux 3H options */
1480 #define _EXCLKMX_TMR0_T5CKI_EXTERNAL_CLOCK_INPUT_IS_MULTIPLEXED_WITH_RD0_3H 0xEF /* TMR0/T5CKI external clock input is multiplexed with RD0 */
1481 #define _EXCLKMX_TMR0_T5CKI_EXTERNAL_CLOCK_INPUT_IS_MULTIPLEXED_WITH_RC3_3H 0xFF /* TMR0/T5CKI external clock input is multiplexed with RC3 */
1483 /* Master Clear Enable 3H options */
1484 #define _MCLRE_MCLR_ON__RE3_INPUT_OFF_3H 0xFF /* MCLR enabled, RE3 input disabled */
1485 #define _MCLRE_RE3_INPUT_ON__MCLR_OFF_3H 0x7F /* RE3 input enabled, MCLR disabled */
1488 /* Background Debug 4L options */
1489 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1490 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1492 /* Low Voltage Program 4L options */
1493 #define _LVP_ON_4L 0xFF /* Enabled */
1494 #define _LVP_OFF_4L 0xFB /* Disabled */
1496 /* Stack Overflow Reset 4L options */
1497 #define _STVR_ON_4L 0xFF /* Enabled */
1498 #define _STVR_OFF_4L 0xFE /* Disabled */
1501 /* Code Protect 00200-00FFF 5L options */
1502 #define _CP_0_OFF_5L 0xFF /* Disabled */
1503 #define _CP_0_ON_5L 0xFE /* Enabled */
1505 /* Code Protect 01000-01FFF 5L options */
1506 #define _CP_1_OFF_5L 0xFF /* Disabled */
1507 #define _CP_1_ON_5L 0xFD /* Enabled */
1509 /* Code Protect 02000-02FFF 5L options */
1510 #define _CP_2_OFF_5L 0xFF /* Disabled */
1511 #define _CP_2_ON_5L 0xFB /* Enabled */
1513 /* Code Protect 03000-03FFF 5L options */
1514 #define _CP_3_OFF_5L 0xFF /* Disabled */
1515 #define _CP_3_ON_5L 0xF7 /* Enabled */
1518 /* Data EE Read Protect 5H options */
1519 #define _CPD_OFF_5H 0xFF /* Disabled */
1520 #define _CPD_ON_5H 0x7F /* Enabled */
1522 /* Code Protect Boot 5H options */
1523 #define _CPB_OFF_5H 0xFF /* Disabled */
1524 #define _CPB_ON_5H 0xBF /* Enabled */
1527 /* Table Write Protect 00200-00FFF 6L options */
1528 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1529 #define _WRT_0_ON_6L 0xFE /* Enabled */
1531 /* Table Write Protect 01000-01FFF 6L options */
1532 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1533 #define _WRT_1_ON_6L 0xFD /* Enabled */
1535 /* Table Write Protect 02000-02FFF 6L options */
1536 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1537 #define _WRT_2_ON_6L 0xFB /* Enabled */
1539 /* Table Write Protect 03000-03FFF 6L options */
1540 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1541 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1544 /* Data EE Write Protect 6H options */
1545 #define _WRTD_OFF_6H 0xFF /* Disabled */
1546 #define _WRTD_ON_6H 0x7F /* Enabled */
1548 /* Table Write Protect Boot 6H options */
1549 #define _WRTB_OFF_6H 0xFF /* Disabled */
1550 #define _WRTB_ON_6H 0xBF /* Enabled */
1552 /* Config. Write Protect 6H options */
1553 #define _WRTC_OFF_6H 0xFF /* Disabled */
1554 #define _WRTC_ON_6H 0xDF /* Enabled */
1557 /* Table Read Protect 00200-00FFF 7L options */
1558 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1559 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1561 /* Table Read Protect 01000-01FFF 7L options */
1562 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1563 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1565 /* Table Read Protect 02000-02FFF 7L options */
1566 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1567 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1569 /* Table Read Protect 03000-03FFF 7L options */
1570 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1571 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1574 /* Table Read Protect Boot 7H options */
1575 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1576 #define _EBTRB_ON_7H 0xBF /* Enabled */
1580 /* Location of User ID words */
1581 #define __IDLOC0 0x200000
1582 #define __IDLOC1 0x200001
1583 #define __IDLOC2 0x200002
1584 #define __IDLOC3 0x200003
1585 #define __IDLOC4 0x200004
1586 #define __IDLOC5 0x200005
1587 #define __IDLOC6 0x200006
1588 #define __IDLOC7 0x200007
1590 #endif // __PIC18F4331__