2 * pic18f4331.h - device specific declarations
4 * This file is part of the GNU PIC library for SDCC,
5 * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
7 * It has been automatically generated by inc2h-pic16.pl,
8 * (c) 2007 by Raphael Neider <rneider AT web.de>
11 #ifndef __PIC18F4331_H__
12 #define __PIC18F4331_H__ 1
17 #define __CONFIG1H 0x300001
18 #define __CONFIG2L 0x300002
19 #define __CONFIG2H 0x300003
20 #define __CONFIG3L 0x300004
21 #define __CONFIG3H 0x300005
22 #define __CONFIG4L 0x300006
23 #define __CONFIG5L 0x300008
24 #define __CONFIG5H 0x300009
25 #define __CONFIG6L 0x30000A
26 #define __CONFIG6H 0x30000B
27 #define __CONFIG7L 0x30000C
28 #define __CONFIG7H 0x30000D
31 #define _OSC_LP_1H 0xF0 // LP
32 #define _OSC_XT_1H 0xF1 // XT
33 #define _OSC_HS_1H 0xF2 // HS
34 #define _OSC_RC2_1H 0xF3 // External RC, RA6 is CLKOUT
35 #define _OSC_EC_1H 0xF4 // EC, RA6 is CLKOUT
36 #define _OSC_ECIO_1H 0xF5 // EC, RA6 is I/O
37 #define _OSC_HSPLL_1H 0xF6 // HS-PLL Enabled
38 #define _OSC_RCIO_1H 0xF7 // External RC, RA6 is I/O
39 #define _OSC_IRCIO_1H 0xF8 // Internal RC, RA6 & RA7 are I/O
40 #define _OSC_IRC_1H 0xF9 // Internal RC, RA6 is CLKOUT, RA7 is I/O
41 #define _OSC_RC1_1H 0xFB // External RC, RA6 is CLKOUT
42 #define _OSC_RC_1H 0xFF // External RC, RA6 is CLKOUT
43 #define _FCMEN_OFF_1H 0xBF // Disabled
44 #define _FCMEN_ON_1H 0xFF // Enabled
45 #define _IESO_OFF_1H 0x7F // Disabled
46 #define _IESO_ON_1H 0xFF // Enabled
49 #define _PWRTEN_ON_2L 0xFE // Enabled
50 #define _PWRTEN_OFF_2L 0xFF // Disabled
51 #define _BOREN_OFF_2L 0xFD // Disabled
52 #define _BOREN_ON_2L 0xFF // Enabled
53 #define _BORV_45_2L 0xF3 // 4.5V
54 #define _BORV_42_2L 0xF7 // 4.2V
55 #define _BORV_27_2L 0xFB // 2.7V
56 #define _BORV_20_2L 0xFF // 2.0V
59 #define _WDTEN_OFF_2H 0xFE // Disabled
60 #define _WDTEN_ON_2H 0xFF // Enabled
61 #define _WINEN_ON_2H 0xDF // Enabled
62 #define _WINEN_OFF_2H 0xFF // Disabled
63 #define _WDPS_1_2H 0xE1 // 1:1
64 #define _WDPS_2_2H 0xE3 // 1:2
65 #define _WDPS_4_2H 0xE5 // 1:4
66 #define _WDPS_8_2H 0xE7 // 1:8
67 #define _WDPS_16_2H 0xE9 // 1:16
68 #define _WDPS_32_2H 0xEB // 1:32
69 #define _WDPS_64_2H 0xED // 1:64
70 #define _WDPS_128_2H 0xEF // 1:128
71 #define _WDPS_256_2H 0xF1 // 1:256
72 #define _WDPS_512_2H 0xF3 // 1:512
73 #define _WDPS_1024_2H 0xF5 // 1:1024
74 #define _WDPS_2048_2H 0xF7 // 1:2048
75 #define _WDPS_4096_2H 0xF9 // 1:4096
76 #define _WDPS_8192_2H 0xFB // 1:8192
77 #define _WDPS_16384_2H 0xFD // 1:16384
78 #define _WDPS_32768_2H 0xFF // 1:32768
81 #define _T1OSCMX_OFF_3L 0xDF // Active
82 #define _T1OSCMX_ON_3L 0xFF // Inactive
83 #define _HPOL_LOW_3L 0xEF // Active low
84 #define _HPOL_HIGH_3L 0xFF // Active high
85 #define _LPOL_LOW_3L 0xF7 // Active low
86 #define _LPOL_HIGH_3L 0xFF // Active high
87 #define _PWMPIN_ON_3L 0xFB // Enabled
88 #define _PWMPIN_OFF_3L 0xFF // Disabled
91 #define _MCLRE_OFF_3H 0x7F // Disabled
92 #define _MCLRE_ON_3H 0xFF // Enabled
93 #define _EXCLKMX_RD0_3H 0xEF // Multiplexed with RD0
94 #define _EXCLKMX_RC3_3H 0xFF // Multiplexed with RC3
95 #define _PWM4MX_RD5_3H 0xF7 // Multiplexed with RD5
96 #define _PWM4MX_RB5_3H 0xFF // Multiplexed with RB5
97 #define _SSPMX_RD1_3H 0xFB // SDO output is multiplexed with RD1
98 #define _SSPMX_RC7_3H 0xFF // SD0 output is multiplexed with RC7
99 #define _FLTAMX_RD4_3H 0xFE // Multiplexed with RD4
100 #define _FLTAMX_RC1_3H 0xFF // Multiplexed with RC1
103 #define _STVREN_OFF_4L 0xFE // Disabled
104 #define _STVREN_ON_4L 0xFF // Enabled
105 #define _LVP_OFF_4L 0xFB // Disabled
106 #define _LVP_ON_4L 0xFF // Enabled
107 #define _DEBUG_ON_4L 0x7F // Enabled
108 #define _DEBUG_OFF_4L 0xFF // Disabled
111 #define _CP0_ON_5L 0xFE // Enabled
112 #define _CP0_OFF_5L 0xFF // Disabled
113 #define _CP1_ON_5L 0xFD // Enabled
114 #define _CP1_OFF_5L 0xFF // Disabled
115 #define _CP2_ON_5L 0xFB // Enabled
116 #define _CP2_OFF_5L 0xFF // Disabled
117 #define _CP3_ON_5L 0xF7 // Enabled
118 #define _CP3_OFF_5L 0xFF // Disabled
121 #define _CPB_ON_5H 0xBF // Enabled
122 #define _CPB_OFF_5H 0xFF // Disabled
123 #define _CPD_ON_5H 0x7F // Enabled
124 #define _CPD_OFF_5H 0xFF // Disabled
127 #define _WRT0_ON_6L 0xFE // Enabled
128 #define _WRT0_OFF_6L 0xFF // Disabled
129 #define _WRT1_ON_6L 0xFD // Enabled
130 #define _WRT1_OFF_6L 0xFF // Disabled
131 #define _WRT2_ON_6L 0xFB // Enabled
132 #define _WRT2_OFF_6L 0xFF // Disabled
133 #define _WRT3_ON_6L 0xF7 // Enabled
134 #define _WRT3_OFF_6L 0xFF // Disabled
137 #define _WRTB_ON_6H 0xBF // Enabled
138 #define _WRTB_OFF_6H 0xFF // Disabled
139 #define _WRTC_ON_6H 0xDF // Enabled
140 #define _WRTC_OFF_6H 0xFF // Disabled
141 #define _WRTD_ON_6H 0x7F // Enabled
142 #define _WRTD_OFF_6H 0xFF // Disabled
145 #define _EBTR0_ON_7L 0xFE // Enabled
146 #define _EBTR0_OFF_7L 0xFF // Disabled
147 #define _EBTR1_ON_7L 0xFD // Enabled
148 #define _EBTR1_OFF_7L 0xFF // Disabled
149 #define _EBTR2_ON_7L 0xFB // Enabled
150 #define _EBTR2_OFF_7L 0xFF // Disabled
151 #define _EBTR3_ON_7L 0xF7 // Enabled
152 #define _EBTR3_OFF_7L 0xFF // Disabled
155 #define _EBTRB_ON_7H 0xBF // Enabled
156 #define _EBTRB_OFF_7H 0xFF // Disabled
157 #define _DEVID1 0x3FFFFE
158 #define _DEVID2 0x3FFFFF
159 #define _IDLOC0 0x200000
160 #define _IDLOC1 0x200001
161 #define _IDLOC2 0x200002
162 #define _IDLOC3 0x200003
163 #define _IDLOC4 0x200004
164 #define _IDLOC5 0x200005
165 #define _IDLOC6 0x200006
166 #define _IDLOC7 0x200007
168 extern __sfr __at (0xF60) DFLTCON;
181 extern volatile __DFLTCONbits_t __at (0xF60) DFLTCONbits;
183 extern __sfr __at (0xF61) CAP3CON;
191 unsigned CAP3TMR : 1;
192 unsigned CAP3REN : 1;
196 extern volatile __CAP3CONbits_t __at (0xF61) CAP3CONbits;
198 extern __sfr __at (0xF62) CAP2CON;
206 unsigned CAP2TMR : 1;
207 unsigned CAP2REN : 1;
211 extern volatile __CAP2CONbits_t __at (0xF62) CAP2CONbits;
213 extern __sfr __at (0xF63) CAP1CON;
221 unsigned CAP1TMR : 1;
222 unsigned CAP1REN : 1;
226 extern volatile __CAP1CONbits_t __at (0xF63) CAP1CONbits;
228 extern __sfr __at (0xF64) CAP3BUFL;
230 extern __sfr __at (0xF64) MAXCNTL;
232 extern __sfr __at (0xF65) CAP3BUFH;
234 extern __sfr __at (0xF65) MAXCNTH;
236 extern __sfr __at (0xF66) CAP2BUFL;
238 extern __sfr __at (0xF66) POSCNTL;
240 extern __sfr __at (0xF67) CAP2BUFH;
242 extern __sfr __at (0xF67) POSCNTH;
244 extern __sfr __at (0xF68) CAP1BUFL;
246 extern __sfr __at (0xF68) VELRL;
248 extern __sfr __at (0xF69) CAP1BUFH;
250 extern __sfr __at (0xF69) VELRH;
252 extern __sfr __at (0xF6A) OVDCONS;
265 extern volatile __OVDCONSbits_t __at (0xF6A) OVDCONSbits;
267 extern __sfr __at (0xF6B) OVDCOND;
280 extern volatile __OVDCONDbits_t __at (0xF6B) OVDCONDbits;
282 extern __sfr __at (0xF6C) FLTCONFIG;
286 unsigned FLTAMOD : 1;
290 unsigned FLTBMOD : 1;
295 extern volatile __FLTCONFIGbits_t __at (0xF6C) FLTCONFIGbits;
297 extern __sfr __at (0xF6D) DTCON;
320 extern volatile __DTCONbits_t __at (0xF6D) DTCONbits;
322 extern __sfr __at (0xF6E) PWMCON1;
328 unsigned SEVTDIR : 1;
329 unsigned SEVOPS0 : 1;
330 unsigned SEVOPS1 : 1;
331 unsigned SEVOPS2 : 1;
332 unsigned SEVOPS3 : 1;
335 extern volatile __PWMCON1bits_t __at (0xF6E) PWMCON1bits;
337 extern __sfr __at (0xF6F) PWMCON0;
350 extern volatile __PWMCON0bits_t __at (0xF6F) PWMCON0bits;
352 extern __sfr __at (0xF70) SEVTCMPH;
354 extern __sfr __at (0xF71) SEVTCMPL;
356 extern __sfr __at (0xF72) PDC3H;
358 extern __sfr __at (0xF73) PDC3L;
360 extern __sfr __at (0xF74) PDC2H;
362 extern __sfr __at (0xF75) PDC2L;
364 extern __sfr __at (0xF76) PDC1H;
366 extern __sfr __at (0xF77) PDC1L;
368 extern __sfr __at (0xF78) PDC0H;
370 extern __sfr __at (0xF79) PDC0L;
372 extern __sfr __at (0xF7A) PTPERH;
374 extern __sfr __at (0xF7B) PTPERL;
376 extern __sfr __at (0xF7C) PTMRH;
378 extern __sfr __at (0xF7D) PTMRL;
380 extern __sfr __at (0xF7E) PTCON1;
393 extern volatile __PTCON1bits_t __at (0xF7E) PTCON1bits;
395 extern __sfr __at (0xF7F) PTCON0;
400 unsigned PTCKPS0 : 1;
401 unsigned PTCKPS1 : 1;
408 extern volatile __PTCON0bits_t __at (0xF7F) PTCON0bits;
410 extern __sfr __at (0xF80) PORTA;
443 extern volatile __PORTAbits_t __at (0xF80) PORTAbits;
445 extern __sfr __at (0xF81) PORTB;
458 extern volatile __PORTBbits_t __at (0xF81) PORTBbits;
460 extern __sfr __at (0xF82) PORTC;
485 unsigned NOT_FLTB : 1;
494 unsigned NOT_FLTA : 1;
513 extern volatile __PORTCbits_t __at (0xF82) PORTCbits;
515 extern __sfr __at (0xF83) PORTD;
528 extern volatile __PORTDbits_t __at (0xF83) PORTDbits;
530 extern __sfr __at (0xF84) PORTE;
546 unsigned NOT_MCLR : 1;
563 extern volatile __PORTEbits_t __at (0xF84) PORTEbits;
565 extern __sfr __at (0xF87) TMR5L;
567 extern __sfr __at (0xF88) TMR5H;
569 extern __sfr __at (0xF89) LATA;
582 extern volatile __LATAbits_t __at (0xF89) LATAbits;
584 extern __sfr __at (0xF8A) LATB;
597 extern volatile __LATBbits_t __at (0xF8A) LATBbits;
599 extern __sfr __at (0xF8B) LATC;
612 extern volatile __LATCbits_t __at (0xF8B) LATCbits;
614 extern __sfr __at (0xF8C) LATD;
627 extern volatile __LATDbits_t __at (0xF8C) LATDbits;
629 extern __sfr __at (0xF8D) LATE;
642 extern volatile __LATEbits_t __at (0xF8D) LATEbits;
644 extern __sfr __at (0xF90) PR5L;
646 extern __sfr __at (0xF91) PR5H;
648 extern __sfr __at (0xF92) DDRA;
661 extern volatile __DDRAbits_t __at (0xF92) DDRAbits;
663 extern __sfr __at (0xF92) TRISA;
676 extern volatile __TRISAbits_t __at (0xF92) TRISAbits;
678 extern __sfr __at (0xF93) DDRB;
691 extern volatile __DDRBbits_t __at (0xF93) DDRBbits;
693 extern __sfr __at (0xF93) TRISB;
706 extern volatile __TRISBbits_t __at (0xF93) TRISBbits;
708 extern __sfr __at (0xF94) DDRC;
721 extern volatile __DDRCbits_t __at (0xF94) DDRCbits;
723 extern __sfr __at (0xF94) TRISC;
736 extern volatile __TRISCbits_t __at (0xF94) TRISCbits;
738 extern __sfr __at (0xF95) DDRD;
751 extern volatile __DDRDbits_t __at (0xF95) DDRDbits;
753 extern __sfr __at (0xF95) TRISD;
766 extern volatile __TRISDbits_t __at (0xF95) TRISDbits;
768 extern __sfr __at (0xF96) DDRE;
781 extern volatile __DDREbits_t __at (0xF96) DDREbits;
783 extern __sfr __at (0xF96) TRISE;
796 extern volatile __TRISEbits_t __at (0xF96) TRISEbits;
798 extern __sfr __at (0xF99) ADCHS;
821 extern volatile __ADCHSbits_t __at (0xF99) ADCHSbits;
823 extern __sfr __at (0xF9A) ADCON3;
836 extern volatile __ADCON3bits_t __at (0xF9A) ADCON3bits;
838 extern __sfr __at (0xF9B) OSCTUNE;
851 extern volatile __OSCTUNEbits_t __at (0xF9B) OSCTUNEbits;
853 extern __sfr __at (0xF9D) PIE1;
876 extern volatile __PIE1bits_t __at (0xF9D) PIE1bits;
878 extern __sfr __at (0xF9E) PIR1;
901 extern volatile __PIR1bits_t __at (0xF9E) PIR1bits;
903 extern __sfr __at (0xF9F) IPR1;
926 extern volatile __IPR1bits_t __at (0xF9F) IPR1bits;
928 extern __sfr __at (0xFA0) PIE2;
941 extern volatile __PIE2bits_t __at (0xFA0) PIE2bits;
943 extern __sfr __at (0xFA1) PIR2;
956 extern volatile __PIR2bits_t __at (0xFA1) PIR2bits;
958 extern __sfr __at (0xFA2) IPR2;
971 extern volatile __IPR2bits_t __at (0xFA2) IPR2bits;
973 extern __sfr __at (0xFA3) PIE3;
978 unsigned IC2QEIE : 1;
979 unsigned IC3DRIE : 1;
986 extern volatile __PIE3bits_t __at (0xFA3) PIE3bits;
988 extern __sfr __at (0xFA4) PIR3;
993 unsigned IC2QEIF : 1;
994 unsigned IC3DRIF : 1;
1001 extern volatile __PIR3bits_t __at (0xFA4) PIR3bits;
1003 extern __sfr __at (0xFA5) IPR3;
1006 unsigned TMR5IP : 1;
1008 unsigned IC2QEIP : 1;
1009 unsigned IC3DRIP : 1;
1016 extern volatile __IPR3bits_t __at (0xFA5) IPR3bits;
1018 extern __sfr __at (0xFA6) EECON1;
1031 extern volatile __EECON1bits_t __at (0xFA6) EECON1bits;
1033 extern __sfr __at (0xFA7) EECON2;
1035 extern __sfr __at (0xFA8) EEDATA;
1037 extern __sfr __at (0xFA9) EEADR;
1039 extern __sfr __at (0xFAA) BAUDCON;
1052 extern volatile __BAUDCONbits_t __at (0xFAA) BAUDCONbits;
1054 extern __sfr __at (0xFAA) BAUDCTL;
1067 extern volatile __BAUDCTLbits_t __at (0xFAA) BAUDCTLbits;
1069 extern __sfr __at (0xFAB) RCSTA;
1082 extern volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;
1084 extern __sfr __at (0xFAC) TXSTA;
1097 extern volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;
1099 extern __sfr __at (0xFAD) TXREG;
1101 extern __sfr __at (0xFAE) RCREG;
1103 extern __sfr __at (0xFAF) SPBRG;
1105 extern __sfr __at (0xFB0) SPBRGH;
1107 extern __sfr __at (0xFB6) QEICON;
1115 unsigned UP_DOWN : 1;
1127 unsigned NOT_VELM : 1;
1145 unsigned NOT_DOWN : 1;
1150 extern volatile __QEICONbits_t __at (0xFB6) QEICONbits;
1152 extern __sfr __at (0xFB7) T5CON;
1155 unsigned TMR5ON : 1;
1156 unsigned TMR5CS : 1;
1157 unsigned T5SYNC : 1;
1167 unsigned NOT_T5SYNC : 1;
1171 unsigned NOT_RESEN : 1;
1175 extern volatile __T5CONbits_t __at (0xFB7) T5CONbits;
1177 extern __sfr __at (0xFB8) ANSEL0;
1190 extern volatile __ANSEL0bits_t __at (0xFB8) ANSEL0bits;
1192 extern __sfr __at (0xFB9) ANSEL1;
1205 extern volatile __ANSEL1bits_t __at (0xFB9) ANSEL1bits;
1207 extern __sfr __at (0xFBA) CCP2CON;
1210 unsigned CCP2M0 : 1;
1211 unsigned CCP2M1 : 1;
1212 unsigned CCP2M2 : 1;
1213 unsigned CCP2M3 : 1;
1230 extern volatile __CCP2CONbits_t __at (0xFBA) CCP2CONbits;
1232 extern __sfr __at (0xFBB) CCPR2;
1234 extern __sfr __at (0xFBB) CCPR2L;
1236 extern __sfr __at (0xFBC) CCPR2H;
1238 extern __sfr __at (0xFBD) CCP1CON;
1241 unsigned CCP1M0 : 1;
1242 unsigned CCP1M1 : 1;
1243 unsigned CCP1M2 : 1;
1244 unsigned CCP1M3 : 1;
1261 extern volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;
1263 extern __sfr __at (0xFBE) CCPR1;
1265 extern __sfr __at (0xFBE) CCPR1L;
1267 extern __sfr __at (0xFBF) CCPR1H;
1269 extern __sfr __at (0xFC0) ADCON2;
1282 extern volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;
1284 extern __sfr __at (0xFC1) ADCON1;
1287 unsigned ADPNT0 : 1;
1288 unsigned ADPNT1 : 1;
1289 unsigned BFOVFL : 1;
1291 unsigned FIFOEN : 1;
1299 unsigned FFOVFL : 1;
1307 extern volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;
1309 extern __sfr __at (0xFC2) ADCON0;
1313 unsigned GO_DONE : 1;
1314 unsigned ACMOD0 : 1;
1315 unsigned ACMOD1 : 1;
1343 unsigned NOT_DONE : 1;
1352 extern volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;
1354 extern __sfr __at (0xFC3) ADRES;
1356 extern __sfr __at (0xFC3) ADRESL;
1358 extern __sfr __at (0xFC4) ADRESH;
1360 extern __sfr __at (0xFC6) SSPCON;
1373 extern volatile __SSPCONbits_t __at (0xFC6) SSPCONbits;
1375 extern __sfr __at (0xFC7) SSPSTAT;
1400 unsigned NOT_WRITE : 1;
1403 unsigned NOT_ADDRESS : 1;
1410 unsigned READ_WRITE : 1;
1413 unsigned DATA_ADDRESS : 1;
1428 extern volatile __SSPSTATbits_t __at (0xFC7) SSPSTATbits;
1430 extern __sfr __at (0xFC8) SSPADD;
1432 extern __sfr __at (0xFC9) SSPBUF;
1434 extern __sfr __at (0xFCA) T2CON;
1437 unsigned T2CKPS0 : 1;
1438 unsigned T2CKPS1 : 1;
1439 unsigned TMR2ON : 1;
1440 unsigned T2OUTPS0 : 1;
1441 unsigned T2OUTPS1 : 1;
1442 unsigned T2OUTPS2 : 1;
1443 unsigned T2OUTPS3 : 1;
1447 extern volatile __T2CONbits_t __at (0xFCA) T2CONbits;
1449 extern __sfr __at (0xFCB) PR2;
1451 extern __sfr __at (0xFCC) TMR2;
1453 extern __sfr __at (0xFCD) T1CON;
1456 unsigned TMR1ON : 1;
1457 unsigned TMR1CS : 1;
1458 unsigned T1SYNC : 1;
1459 unsigned T1OSCEN : 1;
1460 unsigned T1CKPS0 : 1;
1461 unsigned T1CKPS1 : 1;
1468 unsigned T1INSYNC : 1;
1478 unsigned NOT_T1SYNC : 1;
1486 extern volatile __T1CONbits_t __at (0xFCD) T1CONbits;
1488 extern __sfr __at (0xFCE) TMR1L;
1490 extern __sfr __at (0xFCF) TMR1H;
1492 extern __sfr __at (0xFD0) RCON;
1495 unsigned NOT_BOR : 1;
1496 unsigned NOT_POR : 1;
1497 unsigned NOT_PD : 1;
1498 unsigned NOT_TO : 1;
1499 unsigned NOT_RI : 1;
1502 unsigned NOT_IPEN : 1;
1515 extern volatile __RCONbits_t __at (0xFD0) RCONbits;
1517 extern __sfr __at (0xFD1) WDTCON;
1520 unsigned SWDTEN : 1;
1540 extern volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;
1542 extern __sfr __at (0xFD2) LVDCON;
1565 extern volatile __LVDCONbits_t __at (0xFD2) LVDCONbits;
1567 extern __sfr __at (0xFD3) OSCCON;
1590 extern volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;
1592 extern __sfr __at (0xFD5) T0CON;
1601 unsigned T016BIT : 1;
1602 unsigned TMR0ON : 1;
1615 extern volatile __T0CONbits_t __at (0xFD5) T0CONbits;
1617 extern __sfr __at (0xFD6) TMR0L;
1619 extern __sfr __at (0xFD7) TMR0H;
1621 extern __sfr __at (0xFD8) STATUS;
1634 extern volatile __STATUSbits_t __at (0xFD8) STATUSbits;
1636 extern __sfr __at (0xFD9) FSR2L;
1638 extern __sfr __at (0xFDA) FSR2H;
1640 extern __sfr __at (0xFDB) PLUSW2;
1642 extern __sfr __at (0xFDC) PREINC2;
1644 extern __sfr __at (0xFDD) POSTDEC2;
1646 extern __sfr __at (0xFDE) POSTINC2;
1648 extern __sfr __at (0xFDF) INDF2;
1650 extern __sfr __at (0xFE0) BSR;
1652 extern __sfr __at (0xFE1) FSR1L;
1654 extern __sfr __at (0xFE2) FSR1H;
1656 extern __sfr __at (0xFE3) PLUSW1;
1658 extern __sfr __at (0xFE4) PREINC1;
1660 extern __sfr __at (0xFE5) POSTDEC1;
1662 extern __sfr __at (0xFE6) POSTINC1;
1664 extern __sfr __at (0xFE7) INDF1;
1666 extern __sfr __at (0xFE8) WREG;
1668 extern __sfr __at (0xFE9) FSR0L;
1670 extern __sfr __at (0xFEA) FSR0H;
1672 extern __sfr __at (0xFEB) PLUSW0;
1674 extern __sfr __at (0xFEC) PREINC0;
1676 extern __sfr __at (0xFED) POSTDEC0;
1678 extern __sfr __at (0xFEE) POSTINC0;
1680 extern __sfr __at (0xFEF) INDF0;
1682 extern __sfr __at (0xFF0) INTCON3;
1685 unsigned INT1IF : 1;
1686 unsigned INT2IF : 1;
1688 unsigned INT1IE : 1;
1689 unsigned INT2IE : 1;
1691 unsigned INT1IP : 1;
1692 unsigned INT2IP : 1;
1705 extern volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;
1707 extern __sfr __at (0xFF1) INTCON2;
1712 unsigned TMR0IP : 1;
1714 unsigned INTEDG2 : 1;
1715 unsigned INTEDG1 : 1;
1716 unsigned INTEDG0 : 1;
1717 unsigned NOT_RBPU : 1;
1730 extern volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;
1732 extern __sfr __at (0xFF2) INTCON;
1736 unsigned INT0IF : 1;
1737 unsigned TMR0IF : 1;
1739 unsigned INT0IE : 1;
1740 unsigned TMR0IE : 1;
1755 extern volatile __INTCONbits_t __at (0xFF2) INTCONbits;
1757 extern __sfr __at (0xFF3) PROD;
1759 extern __sfr __at (0xFF3) PRODL;
1761 extern __sfr __at (0xFF4) PRODH;
1763 extern __sfr __at (0xFF5) TABLAT;
1765 extern __sfr __at (0xFF6) TBLPTR;
1767 extern __sfr __at (0xFF6) TBLPTRL;
1769 extern __sfr __at (0xFF7) TBLPTRH;
1771 extern __sfr __at (0xFF8) TBLPTRU;
1773 extern __sfr __at (0xFF9) PC;
1775 extern __sfr __at (0xFF9) PCL;
1777 extern __sfr __at (0xFFA) PCLATH;
1779 extern __sfr __at (0xFFB) PCLATU;
1781 extern __sfr __at (0xFFC) STKPTR;
1784 unsigned STKPTR0 : 1;
1785 unsigned STKPTR1 : 1;
1786 unsigned STKPTR2 : 1;
1787 unsigned STKPTR3 : 1;
1788 unsigned STKPTR4 : 1;
1790 unsigned STKUNF : 1;
1791 unsigned STKOVF : 1;
1801 unsigned STKFUL : 1;
1804 extern volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;
1806 extern __sfr __at (0xFFD) TOS;
1808 extern __sfr __at (0xFFD) TOSL;
1810 extern __sfr __at (0xFFE) TOSH;
1812 extern __sfr __at (0xFFF) TOSU;