2 * pic18f4321.h - device specific declarations
4 * This file is part of the GNU PIC library for SDCC,
5 * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
7 * It has been automatically generated by inc2h-pic16.pl,
8 * (c) 2007 by Raphael Neider <rneider AT web.de>
11 #ifndef __PIC18F4321_H__
12 #define __PIC18F4321_H__ 1
17 #define __CONFIG1H 0x300001
18 #define __CONFIG2L 0x300002
19 #define __CONFIG2H 0x300003
20 #define __CONFIG3H 0x300005
21 #define __CONFIG4L 0x300006
22 #define __CONFIG5L 0x300008
23 #define __CONFIG5H 0x300009
24 #define __CONFIG6L 0x30000A
25 #define __CONFIG6H 0x30000B
26 #define __CONFIG7L 0x30000C
27 #define __CONFIG7H 0x30000D
30 #define _OSC_LP_1H 0xF0 // LP Oscillator
31 #define _OSC_XT_1H 0xF1 // XT Oscillator
32 #define _OSC_HS_1H 0xF2 // HS Oscillator
33 #define _OSC_RC_1H 0xF3 // External RC oscillator, CLKO function on RA6
34 #define _OSC_EC_1H 0xF4 // EC oscillator, CLKO function on RA6
35 #define _OSC_ECIO_1H 0xF5 // EC oscillator, port function on RA6
36 #define _OSC_HSPLL_1H 0xF6 // HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
37 #define _OSC_RCIO_1H 0xF7 // External RC oscillator, port function on RA6
38 #define _OSC_INTIO2_1H 0xF8 // Internal oscillator block, port function on RA6 and RA7
39 #define _OSC_INTIO1_1H 0xF9 // Internal oscillator block, CLKO function on RA6, port function on RA7
40 #define _FCMEN_OFF_1H 0xBF // Fail-Safe Clock Monitor disabled
41 #define _FCMEN_ON_1H 0xFF // Fail-Safe Clock Monitor enabled
42 #define _IESO_OFF_1H 0x7F // Oscillator Switchover mode disabled
43 #define _IESO_ON_1H 0xFF // Oscillator Switchover mode enabled
46 #define _PWRT_ON_2L 0xFE // PWRT enabled
47 #define _PWRT_OFF_2L 0xFF // PWRT disabled
48 #define _BOR_OFF_2L 0xF9 // Brown-out Reset disabled in hardware and software
49 #define _BOR_SOFT_2L 0xFB // Brown-out Reset enabled and controlled by software (SBOREN is enabled)
50 #define _BOR_NOSLP_2L 0xFD // Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
51 #define _BOR_ON_2L 0xFF // Brown-out Reset enabled in hardware only (SBOREN is disabled)
52 #define _BORV_0_2L 0xE7 // Maximum Setting
53 #define _BORV_1_2L 0xEF //
54 #define _BORV_2_2L 0xF7 //
55 #define _BORV_3_2L 0xFF // Minimum Setting
58 #define _WDT_OFF_2H 0xFE // WDT disabled (control is placed on the SWDTEN bit)
59 #define _WDT_ON_2H 0xFF // WDT enabled
60 #define _WDTPS_1_2H 0xE1 // 1:1
61 #define _WDTPS_2_2H 0xE3 // 1:2
62 #define _WDTPS_4_2H 0xE5 // 1:4
63 #define _WDTPS_8_2H 0xE7 // 1:8
64 #define _WDTPS_16_2H 0xE9 // 1:16
65 #define _WDTPS_32_2H 0xEB // 1:32
66 #define _WDTPS_64_2H 0xED // 1:64
67 #define _WDTPS_128_2H 0xEF // 1:128
68 #define _WDTPS_256_2H 0xF1 // 1:256
69 #define _WDTPS_512_2H 0xF3 // 1:512
70 #define _WDTPS_1024_2H 0xF5 // 1:1024
71 #define _WDTPS_2048_2H 0xF7 // 1:2048
72 #define _WDTPS_4096_2H 0xF9 // 1:4096
73 #define _WDTPS_8192_2H 0xFB // 1:8192
74 #define _WDTPS_16384_2H 0xFD // 1:16384
75 #define _WDTPS_32768_2H 0xFF // 1:32768
78 #define _MCLRE_OFF_3H 0x7F // RE3 input pin enabled; MCLR disabled
79 #define _MCLRE_ON_3H 0xFF // MCLR pin enabled; RE3 input pin disabled
80 #define _LPT1OSC_OFF_3H 0xFB // Timer1 configured for higher power operation
81 #define _LPT1OSC_ON_3H 0xFF // Timer1 configured for low-power operation
82 #define _PBADEN_DIG_3H 0xFD // PORTB<4:0> pins are configured as digital I/O on Reset
83 #define _PBADEN_ANA_3H 0xFF // PORTB<4:0> pins are configured as analog input channels on Reset
84 #define _CCP2MX_RB3_3H 0xFE // CCP2 input/output is multiplexed with RB3
85 #define _CCP2MX_RC1_3H 0xFF // CCP2 input/output is multiplexed with RC1
88 #define _STVREN_OFF_4L 0xFE // Stack full/underflow will not cause Reset
89 #define _STVREN_ON_4L 0xFF // Stack full/underflow will cause Reset
90 #define _LVP_OFF_4L 0xFB // Single-Supply ICSP disabled
91 #define _LVP_ON_4L 0xFF // Single-Supply ICSP enabled
92 #define _ICPORT_OFF_4L 0xF7 // ICPORT disabled
93 #define _ICPORT_ON_4L 0xFF // ICPORT enabled
94 #define _BBSIZ_BB256_4L 0xCF // 256 Word
95 #define _BBSIZ_BB512_4L 0xDF // 512 Word
96 #define _BBSIZ_BB1K_4L 0xFF // 1024 Word
97 #define _XINST_OFF_4L 0xBF // Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
98 #define _XINST_ON_4L 0xFF // Instruction set extension and Indexed Addressing mode enabled
99 #define _DEBUG_ON_4L 0x7F // Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
100 #define _DEBUG_OFF_4L 0xFF // Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
103 #define _CP0_ON_5L 0xFE // Block 0 code-protected
104 #define _CP0_OFF_5L 0xFF // Block 0 not code-protected
105 #define _CP1_ON_5L 0xFD // Block 1 code-protected
106 #define _CP1_OFF_5L 0xFF // Block 1 not code-protected
109 #define _CPB_ON_5H 0xBF // Boot block code-protected
110 #define _CPB_OFF_5H 0xFF // Boot block not code-protected
111 #define _CPD_ON_5H 0x7F // Data EEPROM code-protected
112 #define _CPD_OFF_5H 0xFF // Data EEPROM not code-protected
115 #define _WRT0_ON_6L 0xFE // Block 0 write-protected
116 #define _WRT0_OFF_6L 0xFF // Block 0 not write-protected
117 #define _WRT1_ON_6L 0xFD // Block 1 write-protected
118 #define _WRT1_OFF_6L 0xFF // Block 1 not write-protected
121 #define _WRTC_ON_6H 0xDF // Configuration registers (300000-3000FFh) write-protected
122 #define _WRTC_OFF_6H 0xFF // Configuration registers (300000-3000FFh) not write-protected
123 #define _WRTB_ON_6H 0xBF // Boot block write-protected
124 #define _WRTB_OFF_6H 0xFF // Boot block not write-protected
125 #define _WRTD_ON_6H 0x7F // Data EEPROM write-protected
126 #define _WRTD_OFF_6H 0xFF // Data EEPROM not write-protected
129 #define _EBTR0_ON_7L 0xFE // Block 0 protected from table reads executed in other blocks
130 #define _EBTR0_OFF_7L 0xFF // Block 0 not protected from table reads executed in other blocks
131 #define _EBTR1_ON_7L 0xFD // Block 1 protected from table reads executed in other blocks
132 #define _EBTR1_OFF_7L 0xFF // Block 1 not protected from table reads executed in other blocks
135 #define _EBTRB_ON_7H 0xBF // Boot block protected from table reads executed in other blocks
136 #define _EBTRB_OFF_7H 0xFF // Boot block not protected from table reads executed in other blocks
137 #define _DEVID1 0x3FFFFE
138 #define _DEVID2 0x3FFFFF
139 #define _IDLOC0 0x200000
140 #define _IDLOC1 0x200001
141 #define _IDLOC2 0x200002
142 #define _IDLOC3 0x200003
143 #define _IDLOC4 0x200004
144 #define _IDLOC5 0x200005
145 #define _IDLOC6 0x200006
146 #define _IDLOC7 0x200007
148 extern __sfr __at (0xF80) PORTA;
165 unsigned C1OUT_PORTA : 1;
176 unsigned C2OUT_PORTA : 1;
201 extern volatile __PORTAbits_t __at (0xF80) PORTAbits;
203 extern __sfr __at (0xF81) PORTB;
219 unsigned CCP2_PORTB : 1;
246 extern volatile __PORTBbits_t __at (0xF81) PORTBbits;
248 extern __sfr __at (0xF82) PORTC;
272 unsigned CCP2_PORTC : 1;
291 extern volatile __PORTCbits_t __at (0xF82) PORTCbits;
293 extern __sfr __at (0xF83) PORTD;
326 extern volatile __PORTDbits_t __at (0xF83) PORTDbits;
328 extern __sfr __at (0xF84) PORTE;
354 unsigned NOT_MCLR : 1;
371 extern volatile __PORTEbits_t __at (0xF84) PORTEbits;
373 extern __sfr __at (0xF89) LATA;
386 extern volatile __LATAbits_t __at (0xF89) LATAbits;
388 extern __sfr __at (0xF8A) LATB;
401 extern volatile __LATBbits_t __at (0xF8A) LATBbits;
403 extern __sfr __at (0xF8B) LATC;
416 extern volatile __LATCbits_t __at (0xF8B) LATCbits;
418 extern __sfr __at (0xF8C) LATD;
431 extern volatile __LATDbits_t __at (0xF8C) LATDbits;
433 extern __sfr __at (0xF8D) LATE;
446 extern volatile __LATEbits_t __at (0xF8D) LATEbits;
448 extern __sfr __at (0xF92) TRISA;
461 extern volatile __TRISAbits_t __at (0xF92) TRISAbits;
463 extern __sfr __at (0xF93) TRISB;
476 extern volatile __TRISBbits_t __at (0xF93) TRISBbits;
478 extern __sfr __at (0xF94) TRISC;
491 extern volatile __TRISCbits_t __at (0xF94) TRISCbits;
493 extern __sfr __at (0xF95) TRISD;
506 extern volatile __TRISDbits_t __at (0xF95) TRISDbits;
508 extern __sfr __at (0xF96) TRISE;
515 unsigned PSPMODE : 1;
521 extern volatile __TRISEbits_t __at (0xF96) TRISEbits;
523 extern __sfr __at (0xF9B) OSCTUNE;
536 extern volatile __OSCTUNEbits_t __at (0xF9B) OSCTUNEbits;
538 extern __sfr __at (0xF9D) PIE1;
551 extern volatile __PIE1bits_t __at (0xF9D) PIE1bits;
553 extern __sfr __at (0xF9E) PIR1;
566 extern volatile __PIR1bits_t __at (0xF9E) PIR1bits;
568 extern __sfr __at (0xF9F) IPR1;
581 extern volatile __IPR1bits_t __at (0xF9F) IPR1bits;
583 extern __sfr __at (0xFA0) PIE2;
606 extern volatile __PIE2bits_t __at (0xFA0) PIE2bits;
608 extern __sfr __at (0xFA1) PIR2;
631 extern volatile __PIR2bits_t __at (0xFA1) PIR2bits;
633 extern __sfr __at (0xFA2) IPR2;
656 extern volatile __IPR2bits_t __at (0xFA2) IPR2bits;
658 extern __sfr __at (0xFA6) EECON1;
671 extern volatile __EECON1bits_t __at (0xFA6) EECON1bits;
673 extern __sfr __at (0xFA7) EECON2;
675 extern __sfr __at (0xFA8) EEDATA;
677 extern __sfr __at (0xFA9) EEADR;
679 extern __sfr __at (0xFAB) RCSTA;
702 extern volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;
704 extern __sfr __at (0xFAC) TXSTA;
717 extern volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;
719 extern __sfr __at (0xFAD) TXREG;
721 extern __sfr __at (0xFAE) RCREG;
723 extern __sfr __at (0xFAF) SPBRG;
725 extern __sfr __at (0xFB0) SPBRGH;
727 extern __sfr __at (0xFB1) T3CON;
734 unsigned T3CKPS0 : 1;
735 unsigned T3CKPS1 : 1;
742 unsigned NOT_T3SYNC : 1;
750 extern volatile __T3CONbits_t __at (0xFB1) T3CONbits;
752 extern __sfr __at (0xFB2) TMR3L;
754 extern __sfr __at (0xFB3) TMR3H;
756 extern __sfr __at (0xFB4) CMCON;
765 unsigned C1OUT_CMCON : 1;
766 unsigned C2OUT_CMCON : 1;
769 extern volatile __CMCONbits_t __at (0xFB4) CMCONbits;
771 extern __sfr __at (0xFB5) CVRCON;
784 extern volatile __CVRCONbits_t __at (0xFB5) CVRCONbits;
786 extern __sfr __at (0xFB6) ECCP1AS;
793 unsigned ECCPAS0 : 1;
794 unsigned ECCPAS1 : 1;
795 unsigned ECCPAS2 : 1;
796 unsigned ECCPASE : 1;
799 extern volatile __ECCP1ASbits_t __at (0xFB6) ECCP1ASbits;
801 extern __sfr __at (0xFB7) ECCP1DEL;
814 extern volatile __ECCP1DELbits_t __at (0xFB7) ECCP1DELbits;
816 extern __sfr __at (0xFB7) PWM1CON;
829 extern volatile __PWM1CONbits_t __at (0xFB7) PWM1CONbits;
831 extern __sfr __at (0xFB8) BAUDCON;
854 extern volatile __BAUDCONbits_t __at (0xFB8) BAUDCONbits;
856 extern __sfr __at (0xFB8) BAUDCTL;
879 extern volatile __BAUDCTLbits_t __at (0xFB8) BAUDCTLbits;
881 extern __sfr __at (0xFBA) CCP2CON;
904 extern volatile __CCP2CONbits_t __at (0xFBA) CCP2CONbits;
906 extern __sfr __at (0xFBB) CCPR2;
908 extern __sfr __at (0xFBB) CCPR2L;
910 extern __sfr __at (0xFBC) CCPR2H;
912 extern __sfr __at (0xFBD) CCP1CON;
935 extern volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;
937 extern __sfr __at (0xFBD) ECCP1CON;
960 extern volatile __ECCP1CONbits_t __at (0xFBD) ECCP1CONbits;
962 extern __sfr __at (0xFBE) CCPR1;
964 extern __sfr __at (0xFBE) CCPR1L;
966 extern __sfr __at (0xFBF) CCPR1H;
968 extern __sfr __at (0xFC0) ADCON2;
981 extern volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;
983 extern __sfr __at (0xFC1) ADCON1;
996 extern volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;
998 extern __sfr __at (0xFC2) ADCON0;
1022 unsigned NOT_DONE : 1;
1032 unsigned GO_DONE : 1;
1041 extern volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;
1043 extern __sfr __at (0xFC3) ADRES;
1045 extern __sfr __at (0xFC3) ADRESL;
1047 extern __sfr __at (0xFC4) ADRESH;
1049 extern __sfr __at (0xFC5) SSPCON2;
1058 unsigned ACKSTAT : 1;
1063 unsigned ADMSK1 : 1;
1064 unsigned ADMSK2 : 1;
1065 unsigned ADMSK3 : 1;
1066 unsigned ADMSK4 : 1;
1067 unsigned ADMSK5 : 1;
1072 extern volatile __SSPCON2bits_t __at (0xFC5) SSPCON2bits;
1074 extern __sfr __at (0xFC6) SSPCON1;
1087 extern volatile __SSPCON1bits_t __at (0xFC6) SSPCON1bits;
1089 extern __sfr __at (0xFC7) SSPSTAT;
1124 unsigned NOT_WRITE : 1;
1127 unsigned NOT_ADDRESS : 1;
1132 extern volatile __SSPSTATbits_t __at (0xFC7) SSPSTATbits;
1134 extern __sfr __at (0xFC8) SSPADD;
1136 extern __sfr __at (0xFC9) SSPBUF;
1138 extern __sfr __at (0xFCA) T2CON;
1141 unsigned T2CKPS0 : 1;
1142 unsigned T2CKPS1 : 1;
1143 unsigned TMR2ON : 1;
1144 unsigned TOUTPS0 : 1;
1145 unsigned TOUTPS1 : 1;
1146 unsigned TOUTPS2 : 1;
1147 unsigned TOUTPS3 : 1;
1154 unsigned T2OUTPS0 : 1;
1155 unsigned T2OUTPS1 : 1;
1156 unsigned T2OUTPS2 : 1;
1157 unsigned T2OUTPS3 : 1;
1161 extern volatile __T2CONbits_t __at (0xFCA) T2CONbits;
1163 extern __sfr __at (0xFCB) PR2;
1165 extern __sfr __at (0xFCC) TMR2;
1167 extern __sfr __at (0xFCD) T1CON;
1170 unsigned TMR1ON : 1;
1171 unsigned TMR1CS : 1;
1172 unsigned T1SYNC : 1;
1173 unsigned T1OSCEN : 1;
1174 unsigned T1CKPS0 : 1;
1175 unsigned T1CKPS1 : 1;
1182 unsigned NOT_T1SYNC : 1;
1190 extern volatile __T1CONbits_t __at (0xFCD) T1CONbits;
1192 extern __sfr __at (0xFCE) TMR1L;
1194 extern __sfr __at (0xFCF) TMR1H;
1196 extern __sfr __at (0xFD0) RCON;
1205 unsigned SBOREN : 1;
1209 unsigned NOT_BOR : 1;
1210 unsigned NOT_POR : 1;
1211 unsigned NOT_PD : 1;
1212 unsigned NOT_TO : 1;
1213 unsigned NOT_RI : 1;
1219 extern volatile __RCONbits_t __at (0xFD0) RCONbits;
1221 extern __sfr __at (0xFD1) WDTCON;
1224 unsigned SWDTEN : 1;
1244 extern volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;
1246 extern __sfr __at (0xFD2) HLVDCON;
1256 unsigned VDIRMAG : 1;
1269 extern volatile __HLVDCONbits_t __at (0xFD2) HLVDCONbits;
1271 extern __sfr __at (0xFD2) LVDCON;
1281 unsigned VDIRMAG : 1;
1294 extern volatile __LVDCONbits_t __at (0xFD2) LVDCONbits;
1296 extern __sfr __at (0xFD3) OSCCON;
1319 extern volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;
1321 extern __sfr __at (0xFD5) T0CON;
1330 unsigned T08BIT : 1;
1331 unsigned TMR0ON : 1;
1340 unsigned T016BIT : 1;
1344 extern volatile __T0CONbits_t __at (0xFD5) T0CONbits;
1346 extern __sfr __at (0xFD6) TMR0L;
1348 extern __sfr __at (0xFD7) TMR0H;
1350 extern __sfr __at (0xFD8) STATUS;
1363 extern volatile __STATUSbits_t __at (0xFD8) STATUSbits;
1365 extern __sfr __at (0xFD9) FSR2L;
1367 extern __sfr __at (0xFDA) FSR2H;
1369 extern __sfr __at (0xFDB) PLUSW2;
1371 extern __sfr __at (0xFDC) PREINC2;
1373 extern __sfr __at (0xFDD) POSTDEC2;
1375 extern __sfr __at (0xFDE) POSTINC2;
1377 extern __sfr __at (0xFDF) INDF2;
1379 extern __sfr __at (0xFE0) BSR;
1381 extern __sfr __at (0xFE1) FSR1L;
1383 extern __sfr __at (0xFE2) FSR1H;
1385 extern __sfr __at (0xFE3) PLUSW1;
1387 extern __sfr __at (0xFE4) PREINC1;
1389 extern __sfr __at (0xFE5) POSTDEC1;
1391 extern __sfr __at (0xFE6) POSTINC1;
1393 extern __sfr __at (0xFE7) INDF1;
1395 extern __sfr __at (0xFE8) WREG;
1397 extern __sfr __at (0xFE9) FSR0L;
1399 extern __sfr __at (0xFEA) FSR0H;
1401 extern __sfr __at (0xFEB) PLUSW0;
1403 extern __sfr __at (0xFEC) PREINC0;
1405 extern __sfr __at (0xFED) POSTDEC0;
1407 extern __sfr __at (0xFEE) POSTINC0;
1409 extern __sfr __at (0xFEF) INDF0;
1411 extern __sfr __at (0xFF0) INTCON3;
1414 unsigned INT1IF : 1;
1415 unsigned INT2IF : 1;
1417 unsigned INT1IE : 1;
1418 unsigned INT2IE : 1;
1420 unsigned INT1IP : 1;
1421 unsigned INT2IP : 1;
1434 extern volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;
1436 extern __sfr __at (0xFF1) INTCON2;
1441 unsigned TMR0IP : 1;
1443 unsigned INTEDG2 : 1;
1444 unsigned INTEDG1 : 1;
1445 unsigned INTEDG0 : 1;
1456 unsigned NOT_RBPU : 1;
1459 extern volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;
1461 extern __sfr __at (0xFF2) INTCON;
1465 unsigned INT0IF : 1;
1466 unsigned TMR0IF : 1;
1468 unsigned INT0IE : 1;
1469 unsigned TMR0IE : 1;
1484 extern volatile __INTCONbits_t __at (0xFF2) INTCONbits;
1486 extern __sfr __at (0xFF3) PROD;
1488 extern __sfr __at (0xFF3) PRODL;
1490 extern __sfr __at (0xFF4) PRODH;
1492 extern __sfr __at (0xFF5) TABLAT;
1494 extern __sfr __at (0xFF6) TBLPTR;
1496 extern __sfr __at (0xFF6) TBLPTRL;
1498 extern __sfr __at (0xFF7) TBLPTRH;
1500 extern __sfr __at (0xFF8) TBLPTRU;
1502 extern __sfr __at (0xFF9) PC;
1504 extern __sfr __at (0xFF9) PCL;
1506 extern __sfr __at (0xFFA) PCLATH;
1508 extern __sfr __at (0xFFB) PCLATU;
1510 extern __sfr __at (0xFFC) STKPTR;
1519 unsigned STKUNF : 1;
1520 unsigned STKFUL : 1;
1530 unsigned STKOVF : 1;
1533 extern volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;
1535 extern __sfr __at (0xFFD) TOS;
1537 extern __sfr __at (0xFFD) TOSL;
1539 extern __sfr __at (0xFFE) TOSH;
1541 extern __sfr __at (0xFFF) TOSU;