2 * pic18f4221.h - device specific declarations
4 * This file is part of the GNU PIC library for SDCC,
5 * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
7 * It has been automatically generated by inc2h-pic16.pl,
8 * (c) 2007 by Raphael Neider <rneider AT web.de>
11 #ifndef __PIC18F4221_H__
12 #define __PIC18F4221_H__ 1
17 #define __CONFIG1H 0x300001
18 #define __CONFIG2L 0x300002
19 #define __CONFIG2H 0x300003
20 #define __CONFIG3H 0x300005
21 #define __CONFIG4L 0x300006
22 #define __CONFIG5L 0x300008
23 #define __CONFIG5H 0x300009
24 #define __CONFIG6L 0x30000A
25 #define __CONFIG6H 0x30000B
26 #define __CONFIG7L 0x30000C
27 #define __CONFIG7H 0x30000D
30 #define _OSC_LP_1H 0xF0 // LP Oscillator
31 #define _OSC_XT_1H 0xF1 // XT Oscillator
32 #define _OSC_HS_1H 0xF2 // HS Oscillator
33 #define _OSC_RC_1H 0xF3 // External RC oscillator, CLKO function on RA6
34 #define _OSC_EC_1H 0xF4 // EC oscillator, CLKO function on RA6
35 #define _OSC_ECIO_1H 0xF5 // EC oscillator, port function on RA6
36 #define _OSC_HSPLL_1H 0xF6 // HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
37 #define _OSC_RCIO_1H 0xF7 // External RC oscillator, port function on RA6
38 #define _OSC_INTIO2_1H 0xF8 // Internal oscillator block, port function on RA6 and RA7
39 #define _OSC_INTIO1_1H 0xF9 // Internal oscillator block, CLKO function on RA6, port function on RA7
40 #define _FCMEN_OFF_1H 0xBF // Fail-Safe Clock Monitor disabled
41 #define _FCMEN_ON_1H 0xFF // Fail-Safe Clock Monitor enabled
42 #define _IESO_OFF_1H 0x7F // Oscillator Switchover mode disabled
43 #define _IESO_ON_1H 0xFF // Oscillator Switchover mode enabled
46 #define _PWRT_ON_2L 0xFE // PWRT enabled
47 #define _PWRT_OFF_2L 0xFF // PWRT disabled
48 #define _BOR_OFF_2L 0xF9 // Brown-out Reset disabled in hardware and software
49 #define _BOR_SOFT_2L 0xFB // Brown-out Reset enabled and controlled by software (SBOREN is enabled)
50 #define _BOR_NOSLP_2L 0xFD // Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
51 #define _BOR_ON_2L 0xFF // Brown-out Reset enabled in hardware only (SBOREN is disabled)
52 #define _BORV_0_2L 0xE7 // Maximum Setting
53 #define _BORV_1_2L 0xEF //
54 #define _BORV_2_2L 0xF7 //
55 #define _BORV_3_2L 0xFF // Minimum Setting
58 #define _WDT_OFF_2H 0xFE // WDT disabled (control is placed on the SWDTEN bit)
59 #define _WDT_ON_2H 0xFF // WDT enabled
60 #define _WDTPS_1_2H 0xE1 // 1:1
61 #define _WDTPS_2_2H 0xE3 // 1:2
62 #define _WDTPS_4_2H 0xE5 // 1:4
63 #define _WDTPS_8_2H 0xE7 // 1:8
64 #define _WDTPS_16_2H 0xE9 // 1:16
65 #define _WDTPS_32_2H 0xEB // 1:32
66 #define _WDTPS_64_2H 0xED // 1:64
67 #define _WDTPS_128_2H 0xEF // 1:128
68 #define _WDTPS_256_2H 0xF1 // 1:256
69 #define _WDTPS_512_2H 0xF3 // 1:512
70 #define _WDTPS_1024_2H 0xF5 // 1:1024
71 #define _WDTPS_2048_2H 0xF7 // 1:2048
72 #define _WDTPS_4096_2H 0xF9 // 1:4096
73 #define _WDTPS_8192_2H 0xFB // 1:8192
74 #define _WDTPS_16384_2H 0xFD // 1:16384
75 #define _WDTPS_32768_2H 0xFF // 1:32768
78 #define _MCLRE_OFF_3H 0x7F // RE3 input pin enabled; MCLR disabled
79 #define _MCLRE_ON_3H 0xFF // MCLR pin enabled; RE3 input pin disabled
80 #define _LPT1OSC_OFF_3H 0xFB // Timer1 configured for higher power operation
81 #define _LPT1OSC_ON_3H 0xFF // Timer1 configured for low-power operation
82 #define _PBADEN_DIG_3H 0xFD // PORTB<4:0> pins are configured as digital I/O on Reset
83 #define _PBADEN_ANA_3H 0xFF // PORTB<4:0> pins are configured as analog input channels on Reset
84 #define _CCP2MX_RB3_3H 0xFE // CCP2 input/output is multiplexed with RB3
85 #define _CCP2MX_RC1_3H 0xFF // CCP2 input/output is multiplexed with RC1
88 #define _STVREN_OFF_4L 0xFE // Stack full/underflow will not cause Reset
89 #define _STVREN_ON_4L 0xFF // Stack full/underflow will cause Reset
90 #define _LVP_OFF_4L 0xFB // Single-Supply ICSP disabled
91 #define _LVP_ON_4L 0xFF // Single-Supply ICSP enabled
92 #define _ICPORT_OFF_4L 0xF7 // ICPORT disabled
93 #define _ICPORT_ON_4L 0xFF // ICPORT enabled
94 #define _BBSIZ_BB256_4L 0xCF // 256 Word
95 #define _BBSIZ_BB512_4L 0xFF // 512 Word
96 #define _XINST_OFF_4L 0xBF // Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
97 #define _XINST_ON_4L 0xFF // Instruction set extension and Indexed Addressing mode enabled
98 #define _DEBUG_ON_4L 0x7F // Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
99 #define _DEBUG_OFF_4L 0xFF // Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
102 #define _CP0_ON_5L 0xFE // Block 0 code-protected
103 #define _CP0_OFF_5L 0xFF // Block 0 not code-protected
104 #define _CP1_ON_5L 0xFD // Block 1 code-protected
105 #define _CP1_OFF_5L 0xFF // Block 1 not code-protected
108 #define _CPB_ON_5H 0xBF // Boot block code-protected
109 #define _CPB_OFF_5H 0xFF // Boot block not code-protected
110 #define _CPD_ON_5H 0x7F // Data EEPROM code-protected
111 #define _CPD_OFF_5H 0xFF // Data EEPROM not code-protected
114 #define _WRT0_ON_6L 0xFE // Block 0 write-protected
115 #define _WRT0_OFF_6L 0xFF // Block 0 not write-protected
116 #define _WRT1_ON_6L 0xFD // Block 1 write-protected
117 #define _WRT1_OFF_6L 0xFF // Block 1 not write-protected
120 #define _WRTC_ON_6H 0xDF // Configuration registers (300000-3000FFh) write-protected
121 #define _WRTC_OFF_6H 0xFF // Configuration registers (300000-3000FFh) not write-protected
122 #define _WRTB_ON_6H 0xBF // Boot block write-protected
123 #define _WRTB_OFF_6H 0xFF // Boot block not write-protected
124 #define _WRTD_ON_6H 0x7F // Data EEPROM write-protected
125 #define _WRTD_OFF_6H 0xFF // Data EEPROM not write-protected
128 #define _EBTR0_ON_7L 0xFE // Block 0 protected from table reads executed in other blocks
129 #define _EBTR0_OFF_7L 0xFF // Block 0 not protected from table reads executed in other blocks
130 #define _EBTR1_ON_7L 0xFD // Block 1 protected from table reads executed in other blocks
131 #define _EBTR1_OFF_7L 0xFF // Block 1 not protected from table reads executed in other blocks
134 #define _EBTRB_ON_7H 0xBF // Boot block protected from table reads executed in other blocks
135 #define _EBTRB_OFF_7H 0xFF // Boot block not protected from table reads executed in other blocks
136 #define _DEVID1 0x3FFFFE
137 #define _DEVID2 0x3FFFFF
138 #define _IDLOC0 0x200000
139 #define _IDLOC1 0x200001
140 #define _IDLOC2 0x200002
141 #define _IDLOC3 0x200003
142 #define _IDLOC4 0x200004
143 #define _IDLOC5 0x200005
144 #define _IDLOC6 0x200006
145 #define _IDLOC7 0x200007
147 extern __sfr __at (0xF80) PORTA;
164 unsigned C1OUT_PORTA : 1;
175 unsigned C2OUT_PORTA : 1;
200 extern volatile __PORTAbits_t __at (0xF80) PORTAbits;
202 extern __sfr __at (0xF81) PORTB;
218 unsigned CCP2_PORTB : 1;
245 extern volatile __PORTBbits_t __at (0xF81) PORTBbits;
247 extern __sfr __at (0xF82) PORTC;
271 unsigned CCP2_PORTC : 1;
290 extern volatile __PORTCbits_t __at (0xF82) PORTCbits;
292 extern __sfr __at (0xF83) PORTD;
325 extern volatile __PORTDbits_t __at (0xF83) PORTDbits;
327 extern __sfr __at (0xF84) PORTE;
353 unsigned NOT_MCLR : 1;
370 extern volatile __PORTEbits_t __at (0xF84) PORTEbits;
372 extern __sfr __at (0xF89) LATA;
385 extern volatile __LATAbits_t __at (0xF89) LATAbits;
387 extern __sfr __at (0xF8A) LATB;
400 extern volatile __LATBbits_t __at (0xF8A) LATBbits;
402 extern __sfr __at (0xF8B) LATC;
415 extern volatile __LATCbits_t __at (0xF8B) LATCbits;
417 extern __sfr __at (0xF8C) LATD;
430 extern volatile __LATDbits_t __at (0xF8C) LATDbits;
432 extern __sfr __at (0xF8D) LATE;
445 extern volatile __LATEbits_t __at (0xF8D) LATEbits;
447 extern __sfr __at (0xF92) TRISA;
460 extern volatile __TRISAbits_t __at (0xF92) TRISAbits;
462 extern __sfr __at (0xF93) TRISB;
475 extern volatile __TRISBbits_t __at (0xF93) TRISBbits;
477 extern __sfr __at (0xF94) TRISC;
490 extern volatile __TRISCbits_t __at (0xF94) TRISCbits;
492 extern __sfr __at (0xF95) TRISD;
505 extern volatile __TRISDbits_t __at (0xF95) TRISDbits;
507 extern __sfr __at (0xF96) TRISE;
514 unsigned PSPMODE : 1;
520 extern volatile __TRISEbits_t __at (0xF96) TRISEbits;
522 extern __sfr __at (0xF9B) OSCTUNE;
535 extern volatile __OSCTUNEbits_t __at (0xF9B) OSCTUNEbits;
537 extern __sfr __at (0xF9D) PIE1;
550 extern volatile __PIE1bits_t __at (0xF9D) PIE1bits;
552 extern __sfr __at (0xF9E) PIR1;
565 extern volatile __PIR1bits_t __at (0xF9E) PIR1bits;
567 extern __sfr __at (0xF9F) IPR1;
580 extern volatile __IPR1bits_t __at (0xF9F) IPR1bits;
582 extern __sfr __at (0xFA0) PIE2;
605 extern volatile __PIE2bits_t __at (0xFA0) PIE2bits;
607 extern __sfr __at (0xFA1) PIR2;
630 extern volatile __PIR2bits_t __at (0xFA1) PIR2bits;
632 extern __sfr __at (0xFA2) IPR2;
655 extern volatile __IPR2bits_t __at (0xFA2) IPR2bits;
657 extern __sfr __at (0xFA6) EECON1;
670 extern volatile __EECON1bits_t __at (0xFA6) EECON1bits;
672 extern __sfr __at (0xFA7) EECON2;
674 extern __sfr __at (0xFA8) EEDATA;
676 extern __sfr __at (0xFA9) EEADR;
678 extern __sfr __at (0xFAB) RCSTA;
701 extern volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;
703 extern __sfr __at (0xFAC) TXSTA;
716 extern volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;
718 extern __sfr __at (0xFAD) TXREG;
720 extern __sfr __at (0xFAE) RCREG;
722 extern __sfr __at (0xFAF) SPBRG;
724 extern __sfr __at (0xFB0) SPBRGH;
726 extern __sfr __at (0xFB1) T3CON;
733 unsigned T3CKPS0 : 1;
734 unsigned T3CKPS1 : 1;
741 unsigned NOT_T3SYNC : 1;
749 extern volatile __T3CONbits_t __at (0xFB1) T3CONbits;
751 extern __sfr __at (0xFB2) TMR3L;
753 extern __sfr __at (0xFB3) TMR3H;
755 extern __sfr __at (0xFB4) CMCON;
764 unsigned C1OUT_CMCON : 1;
765 unsigned C2OUT_CMCON : 1;
768 extern volatile __CMCONbits_t __at (0xFB4) CMCONbits;
770 extern __sfr __at (0xFB5) CVRCON;
783 extern volatile __CVRCONbits_t __at (0xFB5) CVRCONbits;
785 extern __sfr __at (0xFB6) ECCP1AS;
792 unsigned ECCPAS0 : 1;
793 unsigned ECCPAS1 : 1;
794 unsigned ECCPAS2 : 1;
795 unsigned ECCPASE : 1;
798 extern volatile __ECCP1ASbits_t __at (0xFB6) ECCP1ASbits;
800 extern __sfr __at (0xFB7) ECCP1DEL;
813 extern volatile __ECCP1DELbits_t __at (0xFB7) ECCP1DELbits;
815 extern __sfr __at (0xFB7) PWM1CON;
828 extern volatile __PWM1CONbits_t __at (0xFB7) PWM1CONbits;
830 extern __sfr __at (0xFB8) BAUDCON;
853 extern volatile __BAUDCONbits_t __at (0xFB8) BAUDCONbits;
855 extern __sfr __at (0xFB8) BAUDCTL;
878 extern volatile __BAUDCTLbits_t __at (0xFB8) BAUDCTLbits;
880 extern __sfr __at (0xFBA) CCP2CON;
903 extern volatile __CCP2CONbits_t __at (0xFBA) CCP2CONbits;
905 extern __sfr __at (0xFBB) CCPR2;
907 extern __sfr __at (0xFBB) CCPR2L;
909 extern __sfr __at (0xFBC) CCPR2H;
911 extern __sfr __at (0xFBD) CCP1CON;
934 extern volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;
936 extern __sfr __at (0xFBD) ECCP1CON;
959 extern volatile __ECCP1CONbits_t __at (0xFBD) ECCP1CONbits;
961 extern __sfr __at (0xFBE) CCPR1;
963 extern __sfr __at (0xFBE) CCPR1L;
965 extern __sfr __at (0xFBF) CCPR1H;
967 extern __sfr __at (0xFC0) ADCON2;
980 extern volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;
982 extern __sfr __at (0xFC1) ADCON1;
995 extern volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;
997 extern __sfr __at (0xFC2) ADCON0;
1021 unsigned NOT_DONE : 1;
1031 unsigned GO_DONE : 1;
1040 extern volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;
1042 extern __sfr __at (0xFC3) ADRES;
1044 extern __sfr __at (0xFC3) ADRESL;
1046 extern __sfr __at (0xFC4) ADRESH;
1048 extern __sfr __at (0xFC5) SSPCON2;
1057 unsigned ACKSTAT : 1;
1062 unsigned ADMSK1 : 1;
1063 unsigned ADMSK2 : 1;
1064 unsigned ADMSK3 : 1;
1065 unsigned ADMSK4 : 1;
1066 unsigned ADMSK5 : 1;
1071 extern volatile __SSPCON2bits_t __at (0xFC5) SSPCON2bits;
1073 extern __sfr __at (0xFC6) SSPCON1;
1086 extern volatile __SSPCON1bits_t __at (0xFC6) SSPCON1bits;
1088 extern __sfr __at (0xFC7) SSPSTAT;
1123 unsigned NOT_WRITE : 1;
1126 unsigned NOT_ADDRESS : 1;
1131 extern volatile __SSPSTATbits_t __at (0xFC7) SSPSTATbits;
1133 extern __sfr __at (0xFC8) SSPADD;
1135 extern __sfr __at (0xFC9) SSPBUF;
1137 extern __sfr __at (0xFCA) T2CON;
1140 unsigned T2CKPS0 : 1;
1141 unsigned T2CKPS1 : 1;
1142 unsigned TMR2ON : 1;
1143 unsigned TOUTPS0 : 1;
1144 unsigned TOUTPS1 : 1;
1145 unsigned TOUTPS2 : 1;
1146 unsigned TOUTPS3 : 1;
1153 unsigned T2OUTPS0 : 1;
1154 unsigned T2OUTPS1 : 1;
1155 unsigned T2OUTPS2 : 1;
1156 unsigned T2OUTPS3 : 1;
1160 extern volatile __T2CONbits_t __at (0xFCA) T2CONbits;
1162 extern __sfr __at (0xFCB) PR2;
1164 extern __sfr __at (0xFCC) TMR2;
1166 extern __sfr __at (0xFCD) T1CON;
1169 unsigned TMR1ON : 1;
1170 unsigned TMR1CS : 1;
1171 unsigned T1SYNC : 1;
1172 unsigned T1OSCEN : 1;
1173 unsigned T1CKPS0 : 1;
1174 unsigned T1CKPS1 : 1;
1181 unsigned NOT_T1SYNC : 1;
1189 extern volatile __T1CONbits_t __at (0xFCD) T1CONbits;
1191 extern __sfr __at (0xFCE) TMR1L;
1193 extern __sfr __at (0xFCF) TMR1H;
1195 extern __sfr __at (0xFD0) RCON;
1204 unsigned SBOREN : 1;
1208 unsigned NOT_BOR : 1;
1209 unsigned NOT_POR : 1;
1210 unsigned NOT_PD : 1;
1211 unsigned NOT_TO : 1;
1212 unsigned NOT_RI : 1;
1218 extern volatile __RCONbits_t __at (0xFD0) RCONbits;
1220 extern __sfr __at (0xFD1) WDTCON;
1223 unsigned SWDTEN : 1;
1243 extern volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;
1245 extern __sfr __at (0xFD2) HLVDCON;
1255 unsigned VDIRMAG : 1;
1268 extern volatile __HLVDCONbits_t __at (0xFD2) HLVDCONbits;
1270 extern __sfr __at (0xFD2) LVDCON;
1280 unsigned VDIRMAG : 1;
1293 extern volatile __LVDCONbits_t __at (0xFD2) LVDCONbits;
1295 extern __sfr __at (0xFD3) OSCCON;
1318 extern volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;
1320 extern __sfr __at (0xFD5) T0CON;
1329 unsigned T08BIT : 1;
1330 unsigned TMR0ON : 1;
1339 unsigned T016BIT : 1;
1343 extern volatile __T0CONbits_t __at (0xFD5) T0CONbits;
1345 extern __sfr __at (0xFD6) TMR0L;
1347 extern __sfr __at (0xFD7) TMR0H;
1349 extern __sfr __at (0xFD8) STATUS;
1362 extern volatile __STATUSbits_t __at (0xFD8) STATUSbits;
1364 extern __sfr __at (0xFD9) FSR2L;
1366 extern __sfr __at (0xFDA) FSR2H;
1368 extern __sfr __at (0xFDB) PLUSW2;
1370 extern __sfr __at (0xFDC) PREINC2;
1372 extern __sfr __at (0xFDD) POSTDEC2;
1374 extern __sfr __at (0xFDE) POSTINC2;
1376 extern __sfr __at (0xFDF) INDF2;
1378 extern __sfr __at (0xFE0) BSR;
1380 extern __sfr __at (0xFE1) FSR1L;
1382 extern __sfr __at (0xFE2) FSR1H;
1384 extern __sfr __at (0xFE3) PLUSW1;
1386 extern __sfr __at (0xFE4) PREINC1;
1388 extern __sfr __at (0xFE5) POSTDEC1;
1390 extern __sfr __at (0xFE6) POSTINC1;
1392 extern __sfr __at (0xFE7) INDF1;
1394 extern __sfr __at (0xFE8) WREG;
1396 extern __sfr __at (0xFE9) FSR0L;
1398 extern __sfr __at (0xFEA) FSR0H;
1400 extern __sfr __at (0xFEB) PLUSW0;
1402 extern __sfr __at (0xFEC) PREINC0;
1404 extern __sfr __at (0xFED) POSTDEC0;
1406 extern __sfr __at (0xFEE) POSTINC0;
1408 extern __sfr __at (0xFEF) INDF0;
1410 extern __sfr __at (0xFF0) INTCON3;
1413 unsigned INT1IF : 1;
1414 unsigned INT2IF : 1;
1416 unsigned INT1IE : 1;
1417 unsigned INT2IE : 1;
1419 unsigned INT1IP : 1;
1420 unsigned INT2IP : 1;
1433 extern volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;
1435 extern __sfr __at (0xFF1) INTCON2;
1440 unsigned TMR0IP : 1;
1442 unsigned INTEDG2 : 1;
1443 unsigned INTEDG1 : 1;
1444 unsigned INTEDG0 : 1;
1455 unsigned NOT_RBPU : 1;
1458 extern volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;
1460 extern __sfr __at (0xFF2) INTCON;
1464 unsigned INT0IF : 1;
1465 unsigned TMR0IF : 1;
1467 unsigned INT0IE : 1;
1468 unsigned TMR0IE : 1;
1483 extern volatile __INTCONbits_t __at (0xFF2) INTCONbits;
1485 extern __sfr __at (0xFF3) PROD;
1487 extern __sfr __at (0xFF3) PRODL;
1489 extern __sfr __at (0xFF4) PRODH;
1491 extern __sfr __at (0xFF5) TABLAT;
1493 extern __sfr __at (0xFF6) TBLPTR;
1495 extern __sfr __at (0xFF6) TBLPTRL;
1497 extern __sfr __at (0xFF7) TBLPTRH;
1499 extern __sfr __at (0xFF8) TBLPTRU;
1501 extern __sfr __at (0xFF9) PC;
1503 extern __sfr __at (0xFF9) PCL;
1505 extern __sfr __at (0xFFA) PCLATH;
1507 extern __sfr __at (0xFFB) PCLATU;
1509 extern __sfr __at (0xFFC) STKPTR;
1518 unsigned STKUNF : 1;
1519 unsigned STKFUL : 1;
1529 unsigned STKOVF : 1;
1532 extern volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;
1534 extern __sfr __at (0xFFD) TOS;
1536 extern __sfr __at (0xFFD) TOSL;
1538 extern __sfr __at (0xFFE) TOSH;
1540 extern __sfr __at (0xFFF) TOSU;