3 * pic18f4220.h - PIC18F4220 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F4220_H__
16 #define __PIC18F4220_H__
18 extern __sfr __at (0xf80) PORTA;
65 extern volatile __PORTAbits_t __at (0xf80) PORTAbits;
67 extern __sfr __at (0xf81) PORTB;
103 extern volatile __PORTBbits_t __at (0xf81) PORTBbits;
105 extern __sfr __at (0xf82) PORTC;
141 extern volatile __PORTCbits_t __at (0xf82) PORTCbits;
143 extern __sfr __at (0xf83) PORTD;
180 extern volatile __PORTDbits_t __at (0xf83) PORTDbits;
182 extern __sfr __at (0xf84) PORTE;
219 extern volatile __PORTEbits_t __at (0xf84) PORTEbits;
221 extern __sfr __at (0xf89) LATA;
235 extern volatile __LATAbits_t __at (0xf89) LATAbits;
237 extern __sfr __at (0xf8a) LATB;
251 extern volatile __LATBbits_t __at (0xf8a) LATBbits;
253 extern __sfr __at (0xf8b) LATC;
267 extern volatile __LATCbits_t __at (0xf8b) LATCbits;
269 extern __sfr __at (0xf8c) LATD;
283 extern volatile __LATDbits_t __at (0xf8c) LATDbits;
285 extern __sfr __at (0xf8d) LATE;
299 extern volatile __LATEbits_t __at (0xf8d) LATEbits;
301 extern __sfr __at (0xf92) TRISA;
315 extern volatile __TRISAbits_t __at (0xf92) TRISAbits;
317 extern __sfr __at (0xf93) TRISB;
331 extern volatile __TRISBbits_t __at (0xf93) TRISBbits;
333 extern __sfr __at (0xf94) TRISC;
347 extern volatile __TRISCbits_t __at (0xf94) TRISCbits;
349 extern __sfr __at (0xf95) TRISD;
363 extern volatile __TRISDbits_t __at (0xf95) TRISDbits;
365 extern __sfr __at (0xf96) TRISE;
379 extern volatile __TRISEbits_t __at (0xf96) TRISEbits;
381 extern __sfr __at (0xf9b) OSCTUNE;
395 extern volatile __OSCTUNEbits_t __at (0xf9b) OSCTUNEbits;
397 extern __sfr __at (0xf9d) PIE1;
411 extern volatile __PIE1bits_t __at (0xf9d) PIE1bits;
413 extern __sfr __at (0xf9e) PIR1;
427 extern volatile __PIR1bits_t __at (0xf9e) PIR1bits;
429 extern __sfr __at (0xf9f) IPR1;
443 extern volatile __IPR1bits_t __at (0xf9f) IPR1bits;
445 extern __sfr __at (0xfa0) PIE2;
459 extern volatile __PIE2bits_t __at (0xfa0) PIE2bits;
461 extern __sfr __at (0xfa1) PIR2;
475 extern volatile __PIR2bits_t __at (0xfa1) PIR2bits;
477 extern __sfr __at (0xfa2) IPR2;
491 extern volatile __IPR2bits_t __at (0xfa2) IPR2bits;
493 extern __sfr __at (0xfa6) EECON1;
507 extern volatile __EECON1bits_t __at (0xfa6) EECON1bits;
509 extern __sfr __at (0xfa7) EECON2;
510 extern __sfr __at (0xfa8) EEDATA;
511 extern __sfr __at (0xfa9) EEADR;
512 extern __sfr __at (0xfab) RCSTA;
526 extern volatile __RCSTAbits_t __at (0xfab) RCSTAbits;
528 extern __sfr __at (0xfac) TXSTA;
542 extern volatile __TXSTAbits_t __at (0xfac) TXSTAbits;
544 extern __sfr __at (0xfad) TXREG;
545 extern __sfr __at (0xfae) RCREG;
546 extern __sfr __at (0xfaf) SPBRG;
547 extern __sfr __at (0xfb1) T3CON;
561 extern volatile __T3CONbits_t __at (0xfb1) T3CONbits;
563 extern __sfr __at (0xfb2) TMR3L;
564 extern __sfr __at (0xfb3) TMR3H;
565 extern __sfr __at (0xfb4) CMCON;
579 extern volatile __CMCONbits_t __at (0xfb4) CMCONbits;
581 extern __sfr __at (0xfb5) CVRCON;
595 extern volatile __CVRCONbits_t __at (0xfb5) CVRCONbits;
597 extern __sfr __at (0xfba) CCP2CON;
611 extern volatile __CCP2CONbits_t __at (0xfba) CCP2CONbits;
613 extern __sfr __at (0xfbb) CCPR2L;
614 extern __sfr __at (0xfbc) CCPR2H;
615 extern __sfr __at (0xfbd) CCP1CON;
629 extern volatile __CCP1CONbits_t __at (0xfbd) CCP1CONbits;
631 extern __sfr __at (0xfb7) PWM1CON;
645 extern volatile __PWM1CONbits_t __at (0xfb7) PWM1CONbits;
647 extern __sfr __at (0xfb6) ECCPAS;
661 extern volatile __ECCPASbits_t __at (0xfb6) ECCPASbits;
663 extern __sfr __at (0xfbe) CCPR1L;
664 extern __sfr __at (0xfbf) CCPR1H;
665 extern __sfr __at (0xfc0) ADCON2;
679 extern volatile __ADCON2bits_t __at (0xfc0) ADCON2bits;
681 extern __sfr __at (0xfc1) ADCON1;
695 extern volatile __ADCON1bits_t __at (0xfc1) ADCON1bits;
697 extern __sfr __at (0xfc2) ADCON0;
711 extern volatile __ADCON0bits_t __at (0xfc2) ADCON0bits;
713 extern __sfr __at (0xfc3) ADRESL;
714 extern __sfr __at (0xfc4) ADRESH;
715 extern __sfr __at (0xfc5) SSPCON2;
729 extern volatile __SSPCON2bits_t __at (0xfc5) SSPCON2bits;
731 extern __sfr __at (0xfc6) SSPCON1;
745 extern volatile __SSPCON1bits_t __at (0xfc6) SSPCON1bits;
747 extern __sfr __at (0xfc7) SSPSTAT;
761 extern volatile __SSPSTATbits_t __at (0xfc7) SSPSTATbits;
763 extern __sfr __at (0xfc8) SSPADD;
764 extern __sfr __at (0xfc9) SSPBUF;
765 extern __sfr __at (0xfca) T2CON;
779 extern volatile __T2CONbits_t __at (0xfca) T2CONbits;
781 extern __sfr __at (0xfcb) PR2;
782 extern __sfr __at (0xfcc) TMR2;
783 extern __sfr __at (0xfcd) T1CON;
788 unsigned NOT_T1SYNC:1;
797 extern volatile __T1CONbits_t __at (0xfcd) T1CONbits;
799 extern __sfr __at (0xfce) TMR1L;
800 extern __sfr __at (0xfcf) TMR1H;
801 extern __sfr __at (0xfd0) RCON;
815 extern volatile __RCONbits_t __at (0xfd0) RCONbits;
817 extern __sfr __at (0xfd1) WDTCON;
842 extern volatile __WDTCONbits_t __at (0xfd1) WDTCONbits;
844 extern __sfr __at (0xfd2) LVDCON;
869 extern volatile __LVDCONbits_t __at (0xfd2) LVDCONbits;
871 extern __sfr __at (0xfd3) OSCCON;
885 extern volatile __OSCCONbits_t __at (0xfd3) OSCCONbits;
887 extern __sfr __at (0xfd5) T0CON;
901 extern volatile __T0CONbits_t __at (0xfd5) T0CONbits;
903 extern __sfr __at (0xfd6) TMR0L;
904 extern __sfr __at (0xfd7) TMR0H;
905 extern __sfr __at (0xfd8) STATUS;
919 extern volatile __STATUSbits_t __at (0xfd8) STATUSbits;
921 extern __sfr __at (0xfd9) FSR2L;
922 extern __sfr __at (0xfda) FSR2H;
923 extern __sfr __at (0xfdb) PLUSW2;
924 extern __sfr __at (0xfdc) PREINC2;
925 extern __sfr __at (0xfdd) POSTDEC2;
926 extern __sfr __at (0xfde) POSTINC2;
927 extern __sfr __at (0xfdf) INDF2;
928 extern __sfr __at (0xfe0) BSR;
929 extern __sfr __at (0xfe1) FSR1L;
930 extern __sfr __at (0xfe2) FSR1H;
931 extern __sfr __at (0xfe3) PLUSW1;
932 extern __sfr __at (0xfe4) PREINC1;
933 extern __sfr __at (0xfe5) POSTDEC1;
934 extern __sfr __at (0xfe6) POSTINC1;
935 extern __sfr __at (0xfe7) INDF1;
936 extern __sfr __at (0xfe8) WREG;
937 extern __sfr __at (0xfe9) FSR0L;
938 extern __sfr __at (0xfea) FSR0H;
939 extern __sfr __at (0xfeb) PLUSW0;
940 extern __sfr __at (0xfec) PREINC0;
941 extern __sfr __at (0xfed) POSTDEC0;
942 extern __sfr __at (0xfee) POSTINC0;
943 extern __sfr __at (0xfef) INDF0;
944 extern __sfr __at (0xff0) INTCON3;
969 extern volatile __INTCON3bits_t __at (0xff0) INTCON3bits;
971 extern __sfr __at (0xff1) INTCON2;
985 extern volatile __INTCON2bits_t __at (0xff1) INTCON2bits;
987 extern __sfr __at (0xff2) INTCON;
1001 extern volatile __INTCONbits_t __at (0xff2) INTCONbits;
1003 extern __sfr __at (0xff3) PRODL;
1004 extern __sfr __at (0xff4) PRODH;
1005 extern __sfr __at (0xff5) TABLAT;
1006 extern __sfr __at (0xff6) TBLPTRL;
1007 extern __sfr __at (0xff7) TBLPTRH;
1008 extern __sfr __at (0xff8) TBLPTRU;
1009 extern __sfr __at (0xff9) PCL;
1010 extern __sfr __at (0xffa) PCLATH;
1011 extern __sfr __at (0xffb) PCLATU;
1012 extern __sfr __at (0xffc) STKPTR;
1026 extern volatile __STKPTRbits_t __at (0xffc) STKPTRbits;
1028 extern __sfr __at (0xffd) TOSL;
1029 extern __sfr __at (0xffe) TOSH;
1030 extern __sfr __at (0xfff) TOSU;
1033 /* Configuration registers locations */
1034 #define __CONFIG1H 0x300001
1035 #define __CONFIG2L 0x300002
1036 #define __CONFIG2H 0x300003
1037 #define __CONFIG3H 0x300005
1038 #define __CONFIG4L 0x300006
1039 #define __CONFIG5L 0x300008
1040 #define __CONFIG5H 0x300009
1041 #define __CONFIG6L 0x30000A
1042 #define __CONFIG6H 0x30000B
1043 #define __CONFIG7L 0x30000C
1044 #define __CONFIG7H 0x30000D
1048 /* Oscillator 1H options */
1049 #define _OSC_11XX_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
1050 #define _OSC_101X_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
1051 #define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_1H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */
1052 #define _OSC_INT_Port_on_RA6_Port_on_RA7_1H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */
1053 #define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */
1054 #define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
1055 #define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */
1056 #define _OSC_EC_CLKOUT_1H 0xF4 /* EC-CLKOUT on RA6 */
1057 #define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
1058 #define _OSC_HS_1H 0xF2 /* HS */
1059 #define _OSC_XT_1H 0xF1 /* XT */
1060 #define _OSC_LP_1H 0xF0 /* LP */
1062 /* Fail Safe Clock Monitor Enable 1H options */
1063 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1064 #define _FCMEN_ON_1H 0xFF /* Enabled */
1066 /* Internal External Switch Over 1H options */
1067 #define _IESO_OFF_1H 0x7F /* Disabled */
1068 #define _IESO_ON_1H 0xFF /* Enabled */
1070 /* Power Up Timer 2L options */
1071 #define _PUT_OFF_2L 0xFF /* Disabled */
1072 #define _PUT_ON_2L 0xFE /* Enabled */
1074 /* Brown Out Detect 2L options */
1075 #define _BODEN_ON_2L 0xFF /* Enabled */
1076 #define _BODEN_OFF_2L 0xFD /* Disabled */
1078 /* Brown Out Voltage 2L options */
1079 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
1080 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
1081 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
1082 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
1084 /* Watchdog Timer 2H options */
1085 #define _WDT_ON_2H 0xFF /* Enabled */
1086 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1088 /* Watchdog Postscaler 2H options */
1089 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1090 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1091 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1092 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1093 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1094 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1095 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1096 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1097 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1098 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1099 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1100 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1101 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1102 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1103 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1104 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1106 /* CCP2 Mux 3H options */
1107 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1108 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1110 /* PortB A/D Enable 3H options */
1111 #define _PBADEN_PORTB_4_0__analog_inputs_on_RSET_3H 0xFF /* PORTB<4:0> configured as analog_inputs_on_RESET */
1112 #define _PBADEN_PORTB_4_0__digital_I_O_on_REST_3H 0xFD /* PORTB<4:0> configured as digital_I_O_on_RESET */
1114 /* MCLR enable 3H options */
1115 #define _MCLRE_MCLR_Enabled_RE3_Disabled_3H 0xFF /* MCLR Enabled_RE3_Disabled */
1116 #define _MCLRE_MCLR_Disabled_RE3_Enabled_3H 0x7F /* MCLR Disabled__RE3_Enabled */
1118 /* Stack Overflow Reset 4L options */
1119 #define _STVR_ON_4L 0xFF /* Enabled */
1120 #define _STVR_OFF_4L 0xFE /* Disabled */
1122 /* Low Voltage Program 4L options */
1123 #define _LVP_ON_4L 0xFF /* Enabled */
1124 #define _LVP_OFF_4L 0xFB /* Disabled */
1126 /* Background Debug 4L options */
1127 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1128 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1130 /* Code Protect 000200-0007FF 5L options */
1131 #define _CP_0_OFF_5L 0xFF /* Disabled */
1132 #define _CP_0_ON_5L 0xFE /* Enabled */
1134 /* Code Protect 000800-000FFF 5L options */
1135 #define _CP_1_OFF_5L 0xFF /* Disabled */
1136 #define _CP_1_ON_5L 0xFD /* Enabled */
1138 /* Data EE Read Protect 5H options */
1139 #define _CPD_OFF_5H 0xFF /* Disabled */
1140 #define _CPD_ON_5H 0x7F /* Enabled */
1142 /* Code Protect Boot 5H options */
1143 #define _CPB_OFF_5H 0xFF /* Disabled */
1144 #define _CPB_ON_5H 0xBF /* Enabled */
1146 /* Table Write Protect 00200-007FF 6L options */
1147 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1148 #define _WRT_0_ON_6L 0xFE /* Enabled */
1150 /* Table Write Protect 00800-00FFF 6L options */
1151 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1152 #define _WRT_1_ON_6L 0xFD /* Enabled */
1154 /* Data EE Write Protect 6H options */
1155 #define _WRTD_OFF_6H 0xFF /* Disabled */
1156 #define _WRTD_ON_6H 0x7F /* Enabled */
1158 /* Table Write Protect Boot 6H options */
1159 #define _WRTB_OFF_6H 0xFF /* Disabled */
1160 #define _WRTB_ON_6H 0xBF /* Enabled */
1162 /* Config. Write Protect 6H options */
1163 #define _WRTC_OFF_6H 0xFF /* Disabled */
1164 #define _WRTC_ON_6H 0xDF /* Enabled */
1166 /* Table Read Protect 00200-007FF 7L options */
1167 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1168 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1170 /* Table Read Protect 00800-00FFF 7L options */
1171 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1172 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1174 /* Table Read Protect Boot 7H options */
1175 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1176 #define _EBTRB_ON_7H 0xBF /* Enabled */
1179 /* Device ID locations */
1180 #define __IDLOC0 0x200000
1181 #define __IDLOC1 0x200001
1182 #define __IDLOC2 0x200002
1183 #define __IDLOC3 0x200003
1184 #define __IDLOC4 0x200004
1185 #define __IDLOC5 0x200005
1186 #define __IDLOC6 0x200006
1187 #define __IDLOC7 0x200007