2 * pic18f2620.h - PIC18F2620 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * Added modifications by
8 * Gary Plumbridge <gary AT phodex.net>
11 * Copied from 18f2550 and modified for 18f2620 by
12 * Anton Strobl <a.strobl AT aws-it.at>
15 * The GNU PIC Library is maintained by
16 * Raphael Neider <rneider AT web.de>
18 * originally designed by
19 * Vangelis Rokas <vrokas AT otenet.gr>
26 #ifndef __PIC18F2620_H__
27 #define __PIC18F2620_H__ 1
29 extern __sfr __at (0xF80) PORTA;
96 extern volatile __PORTA_t __at (0xF80) PORTAbits;
98 extern __sfr __at (0xF81) PORTB;
139 extern volatile __PORTB_t __at (0xF81) PORTBbits;
141 extern __sfr __at (0xF82) PORTC;
175 unsigned DTC :1; /* DT might be a reserved word in ASM */
200 extern volatile __PORTC_t __at (0xF82) PORTCbits;
202 extern __sfr __at (0xF83) PORTD;
239 extern volatile __PORTD_t __at (0xF83) PORTDbits;
241 extern __sfr __at (0xF84) PORTE;
278 extern volatile __PORTE_t __at (0xF84) PORTEbits;
280 extern __sfr __at (0xF89) LATA;
293 extern volatile __LATA_t __at (0xF89) LATAbits;
295 extern __sfr __at (0xF8A) LATB;
308 extern volatile __LATB_t __at (0xF8A) LATBbits;
310 extern __sfr __at (0xF8B) LATC;
323 extern volatile __LATC_t __at (0xF8B) LATCbits;
325 extern __sfr __at (0xF8C) LATD;
338 extern volatile __LATD_t __at (0xF8C) LATDbits;
340 extern __sfr __at (0xF8D) LATE;
353 extern volatile __LATE_t __at (0xF8D) LATEbits;
355 extern __sfr __at (0xF92) TRISA;
368 extern volatile __TRISA_t __at (0xF92) TRISAbits;
370 extern __sfr __at (0xF93) TRISB;
383 extern volatile __TRISB_t __at (0xF93) TRISBbits;
385 extern __sfr __at (0xF94) TRISC;
398 extern volatile __TRISC_t __at (0xF94) TRISCbits;
400 extern __sfr __at (0xF95) TRISD;
413 extern volatile __TRISD_t __at (0xF95) TRISDbits;
415 extern __sfr __at (0xF96) TRISE;
422 unsigned PSPMODE : 1;
428 extern volatile __TRISE_t __at (0xF96) TRISEbits;
430 extern __sfr __at (0xF9B) OSCTUNE;
439 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
441 extern __sfr __at (0xF9D) PIE1;
454 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
456 extern __sfr __at (0xF9E) PIR1;
469 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
471 extern __sfr __at (0xF9F) IPR1;
484 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
486 extern __sfr __at (0xFA0) PIE2;
499 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
501 extern __sfr __at (0xFA1) PIR2;
514 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
516 extern __sfr __at (0xFA2) IPR2;
529 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
531 extern __sfr __at (0xFA6) EECON1;
544 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
546 extern __sfr __at (0xFA7) EECON2;
548 extern __sfr __at (0xFA8) EEDATA;
550 extern __sfr __at (0xFA9) EEADR;
552 extern __sfr __at (0xFAA) EEADRH;
554 extern __sfr __at (0xFAB) RCSTA;
567 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
569 extern __sfr __at (0xFAC) TXSTA;
582 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
584 extern __sfr __at (0xFAD) TXREG;
586 extern __sfr __at (0xFAE) RCREG;
588 extern __sfr __at (0xFAF) SPBRG;
590 extern __sfr __at (0xFB0) SPBRGH;
592 extern __sfr __at (0xFB1) T3CON;
597 unsigned NOT_T3SYNC : 1;
599 unsigned T3CKPS0 : 1;
600 unsigned T3CKPS1 : 1;
605 extern volatile __T3CON_t __at (0xFB1) T3CONbits;
607 extern __sfr __at (0xFB2) TMR3L;
609 extern __sfr __at (0xFB3) TMR3H;
611 extern __sfr __at (0xFB4) CMCON;
624 extern volatile __CMCON_t __at (0xFB4) CMCONbits;
626 extern __sfr __at (0xFB5) CVRCON;
639 extern volatile __CVRCON_t __at (0xFB5) CVRCONbits;
641 extern __sfr __at (0xFB6) ECCP1AS;
648 unsigned ECCPAS0 : 1;
649 unsigned ECCPAS1 : 1;
650 unsigned ECCPAS2 : 1;
651 unsigned ECCPASE : 1;
654 extern volatile __ECCP1AS_t __at (0xFB6) ECCP1ASbits;
656 extern __sfr __at (0xFB7) PWM1CON;
663 extern volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
665 extern __sfr __at (0xFB8) BAUDCON;
678 extern volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
680 extern __sfr __at (0xFBA) CCP2CON;
693 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
695 extern __sfr __at (0xFBB) CCPR2L;
697 extern __sfr __at (0xFBC) CCPR2H;
699 extern __sfr __at (0xFBD) CCP1CON;
712 extern volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
714 extern __sfr __at (0xFBE) CCPR1L;
716 extern __sfr __at (0xFBF) CCPR1H;
718 extern __sfr __at (0xFC0) ADCON2;
731 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
733 extern __sfr __at (0xFC1) ADCON1;
746 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
748 extern __sfr __at (0xFC2) ADCON0;
761 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
763 extern __sfr __at (0xFC3) ADRESL;
765 extern __sfr __at (0xFC4) ADRESH;
767 extern __sfr __at (0xFC5) SSPCON2;
776 unsigned ACKSTAT : 1;
780 extern volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
782 extern __sfr __at (0xFC6) SSPCON1;
795 extern volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
797 extern __sfr __at (0xFC7) SSPSTAT;
810 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
812 extern __sfr __at (0xFC8) SSPADD;
814 extern __sfr __at (0xFC9) SSPBUF;
816 extern __sfr __at (0xFCA) T2CON;
819 unsigned T2CKPS0 : 1;
820 unsigned T2CKPS1 : 1;
822 unsigned TOUTPS0 : 1;
823 unsigned TOUTPS1 : 1;
824 unsigned TOUTPS2 : 1;
825 unsigned TOUTPS3 : 1;
829 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
831 extern __sfr __at (0xFCB) PR2;
833 extern __sfr __at (0xFCC) TMR2;
835 extern __sfr __at (0xFCD) T1CON;
840 unsigned NOT_T1SYNC : 1;
841 unsigned T1OSCEN : 1;
842 unsigned T1CKPS0 : 1;
843 unsigned T1CKPS1 : 1;
848 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
850 extern __sfr __at (0xFCE) TMR1L;
852 extern __sfr __at (0xFCF) TMR1H;
854 extern __sfr __at (0xFD0) RCON;
867 extern volatile __RCON_t __at (0xFD0) RCONbits;
869 extern __sfr __at (0xFD1) WDTCON;
882 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
884 extern __sfr __at (0xFD2) HLVDCON;
894 unsigned VDIRMAG : 1;
897 extern volatile __HLVDCON_t __at (0xFD2) HLVDCONbits;
899 extern __sfr __at (0xFD3) OSCCON;
909 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
911 extern __sfr __at (0xFD5) T0CON;
924 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
926 extern __sfr __at (0xFD6) TMR0L;
928 extern __sfr __at (0xFD7) TMR0H;
930 extern __sfr __at (0xFD8) STATUS;
943 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
945 extern __sfr __at (0xFD9) FSR2L;
947 extern __sfr __at (0xFDA) FSR2H;
957 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
959 extern __sfr __at (0xFDB) PLUSW2;
961 extern __sfr __at (0xFDC) PREINC2;
963 extern __sfr __at (0xFDD) POSTDEC2;
965 extern __sfr __at (0xFDE) POSTINC2;
967 extern __sfr __at (0xFDF) INDF2;
969 extern __sfr __at (0xFE0) BSR;
979 extern volatile __BSR_t __at (0xFE0) BSRbits;
981 extern __sfr __at (0xFE1) FSR1L;
983 extern __sfr __at (0xFE2) FSR1H;
993 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
995 extern __sfr __at (0xFE3) PLUSW1;
997 extern __sfr __at (0xFE4) PREINC1;
999 extern __sfr __at (0xFE5) POSTDEC1;
1001 extern __sfr __at (0xFE6) POSTINC1;
1003 extern __sfr __at (0xFE7) INDF1;
1005 extern __sfr __at (0xFE8) WREG;
1007 extern __sfr __at (0xFE9) FSR0L;
1009 extern __sfr __at (0xFEA) FSR0H;
1019 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
1021 extern __sfr __at (0xFEB) PLUSW0;
1023 extern __sfr __at (0xFEC) PREINC0;
1025 extern __sfr __at (0xFED) POSTDEC0;
1027 extern __sfr __at (0xFEE) POSTINC0;
1029 extern __sfr __at (0xFEF) INDF0;
1031 extern __sfr __at (0xFF0) INTCON3;
1034 unsigned INT1IF : 1;
1035 unsigned INT2IF : 1;
1037 unsigned INT1IE : 1;
1038 unsigned INT2IE : 1;
1040 unsigned INT1IP : 1;
1041 unsigned INT2IP : 1;
1044 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
1046 extern __sfr __at (0xFF1) INTCON2;
1051 unsigned TMR0IP : 1;
1053 unsigned INTEDG2 : 1;
1054 unsigned INTEDG1 : 1;
1055 unsigned INTEDG0 : 1;
1059 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
1061 extern __sfr __at (0xFF2) INTCON;
1065 unsigned INT0IF : 1;
1066 unsigned TMR0IF : 1;
1068 unsigned INT0IE : 1;
1069 unsigned TMR0IE : 1;
1084 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
1086 extern __sfr __at (0xFF3) PRODL;
1088 extern __sfr __at (0xFF4) PRODH;
1090 extern __sfr __at (0xFF5) TABLAT;
1092 extern __sfr __at (0xFF6) TBLPTRL;
1094 extern __sfr __at (0xFF7) TBLPTRH;
1096 extern __sfr __at (0xFF8) TBLPTRU;
1099 unsigned TBLPTRU : 5;
1105 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
1107 extern __sfr __at (0xFF9) PCL;
1109 extern __sfr __at (0xFFA) PCLATH;
1115 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
1117 extern __sfr __at (0xFFB) PCLATU;
1126 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1128 extern __sfr __at (0xFFC) STKPTR;
1131 unsigned STKPTR : 5;
1133 unsigned STKUNF : 1;
1134 unsigned STKFUL : 1;
1137 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1139 extern __sfr __at (0xFFD) TOSL;
1141 extern __sfr __at (0xFFE) TOSH;
1143 extern __sfr __at (0xFFF) TOSU;
1152 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1154 /* Configuration register locations */
1155 #define __CONFIG1H 0x300001
1156 #define __CONFIG2L 0x300002
1157 #define __CONFIG2H 0x300003
1158 #define __CONFIG3H 0x300005
1159 #define __CONFIG4L 0x300006
1160 #define __CONFIG5L 0x300008
1161 #define __CONFIG5H 0x300009
1162 #define __CONFIG6L 0x30000A
1163 #define __CONFIG6H 0x30000B
1164 #define __CONFIG7L 0x30000C
1165 #define __CONFIG7H 0x30000D
1168 /* Oscillator 1H options */
1169 #define _OSC_INTIO7_1H 0xF9 /* INTRC-OSC2 as Clock Out, OSC1 as RA7 */
1170 #define _OSC_INTIO67_1H 0xF8 /* INTRC-OSC2 as RA6, OSC1 as RA7 */
1171 #define _OSC_RCIO6_1H 0xF7 /* RC-OSC2 as RA6 */
1172 #define _OSC_HSPLL_1H 0xF6 /* HS-PLL Enabled */
1173 #define _OSC_ECIO6_1H 0xF5 /* EC-OSC2 as RA6 */
1174 #define _OSC_EC_1H 0xF4 /* EC-OSC2 as Clock Out */
1175 #define _OSC_RC_1H 0xF3 /* RC */
1176 #define _OSC_HS_1H 0xF2 /* HS */
1177 #define _OSC_XT_1H 0xF1 /* XT */
1178 #define _OSC_LP_1H 0xF0 /* LP */
1180 /* Fail-Safe Clock Monitor Enable 1H options */
1181 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1182 #define _FCMEN_ON_1H 0xFF /* Enabled */
1184 /* Internal External Switch Over Mode 1H options */
1185 #define _IESO_OFF_1H 0x7F /* Disabled */
1186 #define _IESO_ON_1H 0xFF /* Enabled */
1188 /* Power Up Timer 2L options */
1189 #define _PWRT_OFF_2L 0xFF /* Disabled */
1190 #define _PWRT_ON_2L 0xFE /* Enabled */
1192 /* Brown Out Detect 2L options */
1193 #define _BOREN_OFF_2L 0xF9 // Disabled
1194 #define _BOREN_ON_2L 0xFB // SBOREN Enabled
1195 #define _BOREN_NOSLP_2L 0xFD // Enabled except SLEEP, SBOREN Disabled
1196 #define _BOREN_SBORDIS_2L 0xFF // Enabled, SBOREN Disabled
1198 /* Brown Out Voltage 2L options */
1199 #define _BORV_46_2L 0xE7 // 4.6V
1200 #define _BORV_43_2L 0xEF // 4.3V
1201 #define _BORV_28_2L 0xF7 // 2.8V
1202 #define _BORV_21_2L 0xFF // 2.1V
1204 /* Watchdog Timer 2H options */
1205 #define _WDT_ON_2H 0xFF /* Enabled */
1206 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1208 /* Watchdog Postscaler 2H options */
1209 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1210 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1211 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1212 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1213 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1214 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1215 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1216 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1217 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1218 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1219 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1220 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1221 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1222 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1223 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1224 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1227 /* CCP2 Mux 3H options */
1228 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1229 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1231 /* PortB A/D Enable 3H options */
1232 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
1233 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
1235 /* Low Power Timer1 Osc enable 3H options */
1236 #define _LPT1OSC_ON_3H 0xFF /* Enabled */
1237 #define _LPT1OSC_OFF_3H 0xFB /* Disabled */
1239 /* Master Clear Enable 3H options */
1240 #define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
1241 #define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
1244 /* Stack Overflow Reset 4L options */
1245 #define _STVR_ON_4L 0xFF /* Enabled */
1246 #define _STVR_OFF_4L 0xFE /* Disabled */
1248 /* Low Voltage Program 4L options */
1249 #define _LVP_ON_4L 0xFF /* Enabled */
1250 #define _LVP_OFF_4L 0xFB /* Disabled */
1252 /* Extended CPU Enable 4L options */
1253 #define _XINST_OFF_4L 0xBF // Disabled
1254 #define _XINST_ON_4L 0xFF // Enabled
1256 /* Background Debug 4L options */
1257 #define _DEBUG_ON_4L 0x7F // Enabled
1258 #define _DEBUG_OFF_4L 0xFF // Disabled
1260 /* Code Protect 00800-01FFF 5L options */
1261 #define _CP_0_OFF_5L 0xFF /* Disabled */
1262 #define _CP_0_ON_5L 0xFE /* Enabled */
1264 /* Code Protect 02000-03FFF 5L options */
1265 #define _CP_1_OFF_5L 0xFF /* Disabled */
1266 #define _CP_1_ON_5L 0xFD /* Enabled */
1268 /* Code Protect 04000-05FFF 5L options */
1269 #define _CP_2_OFF_5L 0xFF /* Disabled */
1270 #define _CP_2_ON_5L 0xFB /* Enabled */
1272 /* Code Protect 06000-07FFF 5L options */
1273 #define _CP_3_OFF_5L 0xFF /* Disabled */
1274 #define _CP_3_ON_5L 0xF7 /* Enabled */
1277 /* Data EE Read Protect 5H options */
1278 #define _CPD_OFF_5H 0xFF /* Disabled */
1279 #define _CPD_ON_5H 0x7F /* Enabled */
1281 /* Code Protect Boot 5H options */
1282 #define _CPB_OFF_5H 0xFF /* Disabled */
1283 #define _CPB_ON_5H 0xBF /* Enabled */
1286 /* Table Write Protect 00800-01FFF 6L options */
1287 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1288 #define _WRT_0_ON_6L 0xFE /* Enabled */
1290 /* Table Write Protect 02000-03FFF 6L options */
1291 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1292 #define _WRT_1_ON_6L 0xFD /* Enabled */
1294 /* Table Write Protect 04000-05FFF 6L options */
1295 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1296 #define _WRT_2_ON_6L 0xFB /* Enabled */
1298 /* Table Write Protect 06000-07FFF 6L options */
1299 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1300 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1303 /* Data EE Write Protect 6H options */
1304 #define _WRTD_OFF_6H 0xFF /* Disabled */
1305 #define _WRTD_ON_6H 0x7F /* Enabled */
1307 /* Table Write Protect Boot 6H options */
1308 #define _WRTB_OFF_6H 0xFF /* Disabled */
1309 #define _WRTB_ON_6H 0xBF /* Enabled */
1311 /* Config. Write Protect 6H options */
1312 #define _WRTC_OFF_6H 0xFF /* Disabled */
1313 #define _WRTC_ON_6H 0xDF /* Enabled */
1316 /* Table Read Protect 00800-01FFF 7L options */
1317 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1318 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1320 /* Table Read Protect 02000-03FFF 7L options */
1321 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1322 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1324 /* Table Read Protect 04000-05FFF 7L options */
1325 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1326 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1328 /* Table Read Protect 06000-07FFF 7L options */
1329 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1330 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1333 /* Table Read Protect Boot 7H options */
1334 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1335 #define _EBTRB_ON_7H 0xBF /* Enabled */
1338 /* Device ID bytes */
1339 #define _DEVID1 0x3FFFFE
1340 #define _DEVID2 0x3FFFFF
1343 /* Location of User ID words */
1344 #define __IDLOC0 0x200000
1345 #define __IDLOC1 0x200001
1346 #define __IDLOC2 0x200002
1347 #define __IDLOC3 0x200003
1348 #define __IDLOC4 0x200004
1349 #define __IDLOC5 0x200005
1350 #define __IDLOC6 0x200006
1351 #define __IDLOC7 0x200007
1353 #endif // __PIC18F2620__