2 * pic18f2455.h - Device Library Header for 18F{2455,2550,4455,4550}
4 * This file is part of the GNU PIC Library.
7 * The GNU PIC Library is maintained by
8 * Raphael Neider <rneider AT web.de>
10 * originally designed by
11 * Vangelis Rokas <vrokas@otenet.gr>
17 #ifndef __PIC18F2455_H__
18 #define __PIC18F2455_H__ 1
20 extern __sfr __at (0xF62) SPPDATA;
26 extern volatile __SPPDATA_t __at (0xF62) SPPDATAbits;
28 extern __sfr __at (0xF63) SPPCFG;
37 extern volatile __SPPCFG_t __at (0xF63) SPPCFGbits;
39 extern __sfr __at (0xF64) SPPEPS;
49 extern volatile __SPPEPS_t __at (0xF64) SPPEPSbits;
51 extern __sfr __at (0xF65) SPPCON;
64 extern volatile __SPPCON_t __at (0xF65) SPPCONbits;
66 extern __sfr __at (0xF66) UFRML;
72 extern volatile __UFRML_t __at (0xF66) UFRMLbits;
74 extern __sfr __at (0xF67) UFRMH;
85 extern volatile __UFRMH_t __at (0xF67) UFRMHbits;
87 extern __sfr __at (0xF68) UIR;
100 extern volatile __UIR_t __at (0xF68) UIRbits;
102 extern __sfr __at (0xF69) UIE;
110 unsigned STALLIE : 1;
115 extern volatile __UIE_t __at (0xF69) UIEbits;
117 extern __sfr __at (0xF6A) UEIR;
122 unsigned CRC16EF : 1;
130 extern volatile __UEIR_t __at (0xF6A) UEIRbits;
132 extern __sfr __at (0xF6B) UEIE;
137 unsigned CRC16EE : 1;
145 extern volatile __UEIE_t __at (0xF6B) UEIEbits;
147 extern __sfr __at (0xF6C) USTAT;
157 extern volatile __USTAT_t __at (0xF6C) USTATbits;
159 extern __sfr __at (0xF6D) UCON;
172 extern volatile __UCON_t __at (0xF6D) UCONbits;
174 extern __sfr __at (0xF6E) UADDR;
181 extern volatile __UADDR_t __at (0xF6E) UADDRbits;
183 extern __sfr __at (0xF6F) UCFG;
195 extern volatile __UCFG_t __at (0xF6F) UCFGbits;
197 extern __sfr __at (0xF70) UEP0;
200 unsigned EPSTALL : 1;
202 unsigned EPOUTEN : 1;
203 unsigned EPCONDIS : 1;
210 extern volatile __UEP0_t __at (0xF70) UEP0bits;
212 extern __sfr __at (0xF71) UEP1;
215 unsigned EPSTALL : 1;
217 unsigned EPOUTEN : 1;
218 unsigned EPCONDIS : 1;
225 extern volatile __UEP1_t __at (0xF71) UEP1bits;
227 extern __sfr __at (0xF72) UEP2;
230 unsigned EPSTALL : 1;
232 unsigned EPOUTEN : 1;
233 unsigned EPCONDIS : 1;
240 extern volatile __UEP2_t __at (0xF72) UEP2bits;
242 extern __sfr __at (0xF73) UEP3;
245 unsigned EPSTALL : 1;
247 unsigned EPOUTEN : 1;
248 unsigned EPCONDIS : 1;
255 extern volatile __UEP3_t __at (0xF73) UEP3bits;
257 extern __sfr __at (0xF74) UEP4;
260 unsigned EPSTALL : 1;
262 unsigned EPOUTEN : 1;
263 unsigned EPCONDIS : 1;
270 extern volatile __UEP4_t __at (0xF74) UEP4bits;
272 extern __sfr __at (0xF75) UEP5;
275 unsigned EPSTALL : 1;
277 unsigned EPOUTEN : 1;
278 unsigned EPCONDIS : 1;
285 extern volatile __UEP5_t __at (0xF75) UEP5bits;
287 extern __sfr __at (0xF76) UEP6;
290 unsigned EPSTALL : 1;
292 unsigned EPOUTEN : 1;
293 unsigned EPCONDIS : 1;
300 extern volatile __UEP6_t __at (0xF76) UEP6bits;
302 extern __sfr __at (0xF77) UEP7;
305 unsigned EPSTALL : 1;
307 unsigned EPOUTEN : 1;
308 unsigned EPCONDIS : 1;
315 extern volatile __UEP7_t __at (0xF77) UEP7bits;
317 extern __sfr __at (0xF78) UEP8;
320 unsigned EPSTALL : 1;
322 unsigned EPOUTEN : 1;
323 unsigned EPCONDIS : 1;
330 extern volatile __UEP8_t __at (0xF78) UEP8bits;
332 extern __sfr __at (0xF79) UEP9;
335 unsigned EPSTALL : 1;
337 unsigned EPOUTEN : 1;
338 unsigned EPCONDIS : 1;
345 extern volatile __UEP9_t __at (0xF79) UEP9bits;
347 extern __sfr __at (0xF7A) UEP10;
350 unsigned EPSTALL : 1;
352 unsigned EPOUTEN : 1;
353 unsigned EPCONDIS : 1;
360 extern volatile __UEP10_t __at (0xF7A) UEP10bits;
362 extern __sfr __at (0xF7B) UEP11;
365 unsigned EPSTALL : 1;
367 unsigned EPOUTEN : 1;
368 unsigned EPCONDIS : 1;
375 extern volatile __UEP11_t __at (0xF7B) UEP11bits;
377 extern __sfr __at (0xF7C) UEP12;
380 unsigned EPSTALL : 1;
382 unsigned EPOUTEN : 1;
383 unsigned EPCONDIS : 1;
390 extern volatile __UEP12_t __at (0xF7C) UEP12bits;
392 extern __sfr __at (0xF7D) UEP13;
395 unsigned EPSTALL : 1;
397 unsigned EPOUTEN : 1;
398 unsigned EPCONDIS : 1;
405 extern volatile __UEP13_t __at (0xF7D) UEP13bits;
407 extern __sfr __at (0xF7E) UEP14;
410 unsigned EPSTALL : 1;
412 unsigned EPOUTEN : 1;
413 unsigned EPCONDIS : 1;
420 extern volatile __UEP14_t __at (0xF7E) UEP14bits;
422 extern __sfr __at (0xF7F) UEP15;
425 unsigned EPSTALL : 1;
427 unsigned EPOUTEN : 1;
428 unsigned EPCONDIS : 1;
435 extern volatile __UEP15_t __at (0xF7F) UEP15bits;
437 extern __sfr __at (0xF80) PORTA;
475 extern volatile __PORTA_t __at (0xF80) PORTAbits;
477 extern __sfr __at (0xF81) PORTB;
504 extern volatile __PORTB_t __at (0xF81) PORTBbits;
506 extern __sfr __at (0xF82) PORTC;
553 extern volatile __PORTC_t __at (0xF82) PORTCbits;
555 extern __sfr __at (0xF83) PORTD;
568 extern volatile __PORTD_t __at (0xF83) PORTDbits;
570 extern __sfr __at (0xF84) PORTE;
597 extern volatile __PORTE_t __at (0xF84) PORTEbits;
599 extern __sfr __at (0xF89) LATA;
612 extern volatile __LATA_t __at (0xF89) LATAbits;
614 extern __sfr __at (0xF8A) LATB;
627 extern volatile __LATB_t __at (0xF8A) LATBbits;
629 extern __sfr __at (0xF8B) LATC;
642 extern volatile __LATC_t __at (0xF8B) LATCbits;
644 extern __sfr __at (0xF8C) LATD;
657 extern volatile __LATD_t __at (0xF8C) LATDbits;
659 extern __sfr __at (0xF8D) LATE;
672 extern volatile __LATE_t __at (0xF8D) LATEbits;
674 extern __sfr __at (0xF92) TRISA;
687 extern volatile __TRISA_t __at (0xF92) TRISAbits;
689 extern __sfr __at (0xF93) TRISB;
702 extern volatile __TRISB_t __at (0xF93) TRISBbits;
704 extern __sfr __at (0xF94) TRISC;
717 extern volatile __TRISC_t __at (0xF94) TRISCbits;
719 extern __sfr __at (0xF95) TRISD;
732 extern volatile __TRISD_t __at (0xF95) TRISDbits;
734 extern __sfr __at (0xF96) TRISE;
747 extern volatile __TRISE_t __at (0xF96) TRISEbits;
749 extern __sfr __at (0xF9B) OSCTUNE;
758 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
760 extern __sfr __at (0xF9D) PIE1;
773 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
775 extern __sfr __at (0xF9E) PIR1;
788 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
790 extern __sfr __at (0xF9F) IPR1;
803 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
805 extern __sfr __at (0xFA0) PIE2;
818 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
820 extern __sfr __at (0xFA1) PIR2;
833 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
835 extern __sfr __at (0xFA2) IPR2;
848 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
850 extern __sfr __at (0xFA6) EECON1;
863 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
865 extern __sfr __at (0xFA7) EECON2;
867 extern __sfr __at (0xFA8) EEDATA;
869 extern __sfr __at (0xFA9) EEADR;
871 extern __sfr __at (0xFAB) RCSTA;
884 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
886 extern __sfr __at (0xFAC) TXSTA;
899 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
901 extern __sfr __at (0xFAD) TXREG;
903 extern __sfr __at (0xFAE) RCREG;
905 extern __sfr __at (0xFAF) SPBRG;
907 extern __sfr __at (0xFB0) SPBRGH;
909 extern __sfr __at (0xFB1) T3CON;
914 unsigned NOT_T3SYNC : 1;
916 unsigned T3CKPS0 : 1;
917 unsigned T3CKPS1 : 1;
922 extern volatile __T3CON_t __at (0xFB1) T3CONbits;
924 extern __sfr __at (0xFB2) TMR3L;
926 extern __sfr __at (0xFB3) TMR3H;
928 extern __sfr __at (0xFB4) CMCON;
941 extern volatile __CMCON_t __at (0xFB4) CMCONbits;
943 extern __sfr __at (0xFB5) CVRCON;
956 extern volatile __CVRCON_t __at (0xFB5) CVRCONbits;
958 extern __sfr __at (0xFB6) ECCP1AS;
965 unsigned ECCPAS0 : 1;
966 unsigned ECCPAS1 : 1;
967 unsigned ECCPAS2 : 1;
968 unsigned ECCPASE : 1;
971 extern volatile __ECCP1AS_t __at (0xFB6) ECCP1ASbits;
973 extern __sfr __at (0xFB7) ECCP1DEL;
986 extern volatile __ECCP1DEL_t __at (0xFB7) ECCP1DELbits;
988 extern __sfr __at (0xFB8) BAUDCON;
1001 extern volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
1003 extern __sfr __at (0xFBA) CCP2CON;
1006 unsigned CCP2M0 : 1;
1007 unsigned CCP2M1 : 1;
1008 unsigned CCP2M2 : 1;
1009 unsigned CCP2M3 : 1;
1016 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
1018 extern __sfr __at (0xFBB) CCPR2L;
1020 extern __sfr __at (0xFBC) CCPR2H;
1022 extern __sfr __at (0xFBD) CCP1CON;
1025 unsigned CCP1M0 : 1;
1026 unsigned CCP1M1 : 1;
1027 unsigned CCP1M2 : 1;
1028 unsigned CCP1M3 : 1;
1035 extern volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
1037 extern __sfr __at (0xFBE) CCPR1L;
1039 extern __sfr __at (0xFBF) CCPR1H;
1041 extern __sfr __at (0xFC0) ADCON2;
1054 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
1056 extern __sfr __at (0xFC1) ADCON1;
1069 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
1071 extern __sfr __at (0xFC2) ADCON0;
1084 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
1086 extern __sfr __at (0xFC3) ADRESL;
1088 extern __sfr __at (0xFC4) ADRESH;
1090 extern __sfr __at (0xFC5) SSPCON2;
1099 unsigned ACKSTAT : 1;
1103 extern volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
1105 extern __sfr __at (0xFC6) SSPCON1;
1118 extern volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
1120 extern __sfr __at (0xFC7) SSPSTAT;
1133 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
1135 extern __sfr __at (0xFC8) SSPADD;
1137 extern __sfr __at (0xFC9) SSPBUF;
1139 extern __sfr __at (0xFCA) T2CON;
1142 unsigned T2CKPS0 : 1;
1143 unsigned T2CKPS1 : 1;
1144 unsigned TMR2ON : 1;
1145 unsigned TOUTPS0 : 1;
1146 unsigned TOUTPS1 : 1;
1147 unsigned TOUTPS2 : 1;
1148 unsigned TOUTPS3 : 1;
1152 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
1154 extern __sfr __at (0xFCB) PR2;
1156 extern __sfr __at (0xFCC) TMR2;
1158 extern __sfr __at (0xFCD) T1CON;
1161 unsigned TMR1ON : 1;
1162 unsigned TMR1CS : 1;
1163 unsigned NOT_T1SYNC : 1;
1164 unsigned T1OSCEN : 1;
1165 unsigned T1CKPS0 : 1;
1166 unsigned T1CKPS1 : 1;
1171 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
1173 extern __sfr __at (0xFCE) TMR1L;
1175 extern __sfr __at (0xFCF) TMR1H;
1177 extern __sfr __at (0xFD0) RCON;
1186 unsigned SBOREN : 1;
1190 extern volatile __RCON_t __at (0xFD0) RCONbits;
1192 extern __sfr __at (0xFD1) WDTCON;
1195 unsigned SWDTEN : 1;
1205 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
1207 extern __sfr __at (0xFD2) HLVDCON;
1210 unsigned HLVDL0 : 1;
1211 unsigned HLVDL1 : 1;
1212 unsigned HLVDL2 : 1;
1213 unsigned HLVDL3 : 1;
1214 unsigned HLVDEN : 1;
1217 unsigned VDIRMAG : 1;
1220 extern volatile __HLVDCON_t __at (0xFD2) HLVDCONbits;
1222 extern __sfr __at (0xFD3) OSCCON;
1232 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
1234 extern __sfr __at (0xFD5) T0CON;
1243 unsigned T08BIT : 1;
1244 unsigned TMR0ON : 1;
1247 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
1249 extern __sfr __at (0xFD6) TMR0L;
1251 extern __sfr __at (0xFD7) TMR0H;
1253 extern __sfr __at (0xFD8) STATUS;
1266 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
1268 extern __sfr __at (0xFD9) FSR2L;
1270 extern __sfr __at (0xFDA) FSR2H;
1280 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
1282 extern __sfr __at (0xFDB) PLUSW2;
1284 extern __sfr __at (0xFDC) PREINC2;
1286 extern __sfr __at (0xFDD) POSTDEC2;
1288 extern __sfr __at (0xFDE) POSTINC2;
1290 extern __sfr __at (0xFDF) INDF2;
1292 extern __sfr __at (0xFE0) BSR;
1302 extern volatile __BSR_t __at (0xFE0) BSRbits;
1304 extern __sfr __at (0xFE1) FSR1L;
1306 extern __sfr __at (0xFE2) FSR1H;
1316 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
1318 extern __sfr __at (0xFE3) PLUSW1;
1320 extern __sfr __at (0xFE4) PREINC1;
1322 extern __sfr __at (0xFE5) POSTDEC1;
1324 extern __sfr __at (0xFE6) POSTINC1;
1326 extern __sfr __at (0xFE7) INDF1;
1328 extern __sfr __at (0xFE8) WREG;
1330 extern __sfr __at (0xFE9) FSR0L;
1332 extern __sfr __at (0xFEA) FSR0H;
1342 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
1344 extern __sfr __at (0xFEB) PLUSW0;
1346 extern __sfr __at (0xFEC) PREINC0;
1348 extern __sfr __at (0xFED) POSTDEC0;
1350 extern __sfr __at (0xFEE) POSTINC0;
1352 extern __sfr __at (0xFEF) INDF0;
1354 extern __sfr __at (0xFF0) INTCON3;
1357 unsigned INT1IF : 1;
1358 unsigned INT2IF : 1;
1360 unsigned INT1IE : 1;
1361 unsigned INT2IE : 1;
1363 unsigned INT1IP : 1;
1364 unsigned INT2IP : 1;
1367 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
1369 extern __sfr __at (0xFF1) INTCON2;
1374 unsigned TMR0IP : 1;
1376 unsigned INTEDG2 : 1;
1377 unsigned INTEDG1 : 1;
1378 unsigned INTEDG0 : 1;
1382 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
1384 extern __sfr __at (0xFF2) INTCON;
1388 unsigned INT0IF : 1;
1389 unsigned TMR0IF : 1;
1391 unsigned INT0IE : 1;
1392 unsigned TMR0IE : 1;
1407 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
1409 extern __sfr __at (0xFF3) PRODL;
1411 extern __sfr __at (0xFF4) PRODH;
1413 extern __sfr __at (0xFF5) TABLAT;
1415 extern __sfr __at (0xFF6) TBLPTRL;
1417 extern __sfr __at (0xFF7) TBLPTRH;
1419 extern __sfr __at (0xFF8) TBLPTRU;
1422 unsigned TBLPTRU : 6;
1427 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
1429 extern __sfr __at (0xFF9) PCL;
1431 extern __sfr __at (0xFFA) PCLATH;
1437 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
1439 extern __sfr __at (0xFFB) PCLATU;
1448 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1450 extern __sfr __at (0xFFC) STKPTR;
1453 unsigned STKPTR : 5;
1455 unsigned STKUNF : 1;
1456 unsigned STKFUL : 1;
1459 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1461 extern __sfr __at (0xFFD) TOSL;
1463 extern __sfr __at (0xFFE) TOSH;
1465 extern __sfr __at (0xFFF) TOSU;
1474 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1476 /* Configuration register locations */
1477 #define __CONFIG1L 0x300000
1478 #define __CONFIG1H 0x300001
1479 #define __CONFIG2L 0x300002
1480 #define __CONFIG2H 0x300003
1481 #define __CONFIG3H 0x300005
1482 #define __CONFIG4L 0x300006
1483 #define __CONFIG5L 0x300008
1484 #define __CONFIG5H 0x300009
1485 #define __CONFIG6L 0x30000A
1486 #define __CONFIG6H 0x30000B
1487 #define __CONFIG7L 0x30000C
1488 #define __CONFIG7H 0x30000D
1491 /* Full-Speed USB Clock Source Selection 1L options */
1492 #define _USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2_1L 0xFF /* Clock src from 96MHz PLL/2 */
1493 #define _USBPLL_CLOCK_SRC_FROM_OSC1_OSC2_1L 0xDF /* Clock src from OSC1/OSC2 */
1495 /* CPU System Clock Postscaler 1L options */
1496 #define _CPUDIV__OSC1_OSC2_SRC___4__96MHZ_PLL_SRC___6__1L 0xFF /* [OSC1/OSC2 Src: /4][96MHz PLL Src: /6] */
1497 #define _CPUDIV__OSC1_OSC2_SRC___3__96MHZ_PLL_SRC___4__1L 0xF7 /* [OSC1/OSC2 Src: /3][96MHz PLL Src: /4] */
1498 #define _CPUDIV__OSC1_OSC2_SRC___2__96MHZ_PLL_SRC___3__1L 0xEF /* [OSC1/OSC2 Src: /2][96MHz PLL Src: /3] */
1499 #define _CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2__1L 0xE7 /* [OSC1/OSC2 Src: /1][96MHz PLL Src: /2] */
1501 /* 96MHz PLL Prescaler 1L options */
1502 #define _PLLDIV_DIVIDE_BY_12__48MHZ_INPUT__1L 0xFF /* Divide by 12 (48MHz input) */
1503 #define _PLLDIV_DIVIDE_BY_10__40MHZ_INPUT__1L 0xFE /* Divide by 10 (40MHz input) */
1504 #define _PLLDIV_DIVIDE_BY_6__24MHZ_INPUT__1L 0xFD /* Divide by 6 (24MHz input) */
1505 #define _PLLDIV_DIVIDE_BY_5__20MHZ_INPUT__1L 0xFC /* Divide by 5 (20MHz input) */
1506 #define _PLLDIV_DIVIDE_BY_4__16MHZ_INPUT__1L 0xFB /* Divide by 4 (16MHz input) */
1507 #define _PLLDIV_DIVIDE_BY_3__12MHZ_INPUT__1L 0xFA /* Divide by 3 (12MHz input) */
1508 #define _PLLDIV_DIVIDE_BY_2__8MHZ_INPUT__1L 0xF9 /* Divide by 2 (8MHz input) */
1509 #define _PLLDIV_NO_DIVIDE__4MHZ_INPUT__1L 0xF8 /* No Divide (4MHz input) */
1512 /* Oscillator 1H options */
1513 #define _OSC_HS__HS_PLL__USB_HS_1H 0xFE /* HS: HS+PLL, USB-HS */
1514 #define _OSC_HS__USB_HS_1H 0xFC /* HS: USB-HS */
1515 #define _OSC_INTOSC__USB_HS_1H 0xFB /* INTOSC: USB-HS */
1516 #define _OSC_INTOSC__USB_XT_1H 0xFA /* INTOSC: USB-XT */
1517 #define _OSC_INTOSC__INTOSC_CLK0_RA6___USB_EC_1H 0xF9 /* INTOSC: INTOSC+CLK0{RA6}, USB-EC */
1518 #define _OSC_INTOSC__INTOSC_RA6__USB_EC_1H 0xF8 /* INTOSC: INTOSC+RA6, USB-EC */
1519 #define _OSC_EC__EC_PLL__EC_PLL_CLKO_RA6___USB_EC_1H 0xF7 /* EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC */
1520 #define _OSC_EC__EC_PLL__EC_PLL_RA6__USB_EC_1H 0xF6 /* EC: EC+PLL, EC+PLL+RA6, USB-EC */
1521 #define _OSC_EC__EC_CLKO_RA6___USB_EC_1H 0xF5 /* EC: EC+CLKO{RA6}, USB-EC */
1522 #define _OSC_EC__EC_RA6__USB_EC_1H 0xF4 /* EC: EC+RA6, USB-EC */
1523 #define _OSC_XT__XT_PLL__USB_XT_1H 0xF2 /* XT: XT+PLL, USB-XT */
1524 #define _OSC_XT__USB_XT_1H 0xF0 /* XT: USB-XT */
1526 /* Fail-Safe Clock Monitor Enable 1H options */
1527 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1528 #define _FCMEN_ON_1H 0xFF /* Enabled */
1530 /* Internal External Switch Over Mode 1H options */
1531 #define _IESO_OFF_1H 0x7F /* Disabled */
1532 #define _IESO_ON_1H 0xFF /* Enabled */
1535 /* USB Voltage Regulator 2L options */
1536 #define _VREGEN_ON_2L 0xFF /* Enabled */
1537 #define _VREGEN_OFF_2L 0xDF /* Disabled */
1539 /* Power Up Timer 2L options */
1540 #define _PUT_OFF_2L 0xFF /* Disabled */
1541 #define _PUT_ON_2L 0xFE /* Enabled */
1543 /* Brown Out Detect 2L options */
1544 #define _BODEN_ON_2L 0xFF /* Enabled in hardware, SBOREN disabled */
1545 #define _BODEN_ON_WHILE_ACTIVE_2L 0xFD /* Enabled while active,disabled in SLEEP,SBOREN disabled */
1546 #define _BODEN_CONTROLLED_WITH_SBOREN_BIT_2L 0xFB /* Controlled with SBOREN bit */
1547 #define _BODEN_OFF_2L 0xF9 /* Disabled in hardware, SBOREN disabled */
1549 /* Brown Out Voltage 2L options */
1550 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
1551 #define _BODENV_2_7V_2L 0xF7 /* 2.7V */
1552 #define _BODENV_4_2V_2L 0xEF /* 4.2V */
1553 #define _BODENV_4_5V_2L 0xE7 /* 4.5V */
1556 /* Watchdog Timer 2H options */
1557 #define _WDT_ON_2H 0xFF /* Enabled */
1558 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1560 /* Watchdog Postscaler 2H options */
1561 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1562 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1563 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1564 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1565 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1566 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1567 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1568 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1569 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1570 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1571 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1572 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1573 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1574 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1575 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1576 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1579 /* CCP2 Mux 3H options */
1580 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1581 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1583 /* PortB A/D Enable 3H options */
1584 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
1585 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
1587 /* Low Power Timer1 Osc enable 3H options */
1588 #define _LPT1OSC_ON_3H 0xFF /* Enabled */
1589 #define _LPT1OSC_OFF_3H 0xFB /* Disabled */
1591 /* Master Clear Enable 3H options */
1592 #define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
1593 #define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
1596 /* Stack Overflow Reset 4L options */
1597 #define _STVR_ON_4L 0xFF /* Enabled */
1598 #define _STVR_OFF_4L 0xFE /* Disabled */
1600 /* Low Voltage Program 4L options */
1601 #define _LVP_ON_4L 0xFF /* Enabled */
1602 #define _LVP_OFF_4L 0xFB /* Disabled */
1604 /* Dedicated In-Circuit Port {ICD/ICSP} 4L options */
1605 #define _ENICPORT_OFF_4L 0xDF /* Disabled */
1607 /* Extended CPU Enable 4L options */
1608 #define _ENHCPU_ON_4L 0xFF /* Enabled */
1609 #define _ENHCPU_OFF_4L 0xBF /* Disabled */
1611 /* Background Debug 4L options */
1612 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1613 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1616 /* Code Protect 00800-01FFF 5L options */
1617 #define _CP_0_OFF_5L 0xFF /* Disabled */
1618 #define _CP_0_ON_5L 0xFE /* Enabled */
1620 /* Code Protect 02000-03FFF 5L options */
1621 #define _CP_1_OFF_5L 0xFF /* Disabled */
1622 #define _CP_1_ON_5L 0xFD /* Enabled */
1624 /* Code Protect 04000-05FFF 5L options */
1625 #define _CP_2_OFF_5L 0xFF /* Disabled */
1626 #define _CP_2_ON_5L 0xFB /* Enabled */
1628 /* Code Protect 06000-07FFF 5L options */
1629 #define _CP_3_OFF_5L 0xFF /* Disabled */
1630 #define _CP_3_ON_5L 0xF7 /* Enabled */
1633 /* Data EE Read Protect 5H options */
1634 #define _CPD_OFF_5H 0xFF /* Disabled */
1635 #define _CPD_ON_5H 0x7F /* Enabled */
1637 /* Code Protect Boot 5H options */
1638 #define _CPB_OFF_5H 0xFF /* Disabled */
1639 #define _CPB_ON_5H 0xBF /* Enabled */
1642 /* Table Write Protect 00800-01FFF 6L options */
1643 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1644 #define _WRT_0_ON_6L 0xFE /* Enabled */
1646 /* Table Write Protect 02000-03FFF 6L options */
1647 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1648 #define _WRT_1_ON_6L 0xFD /* Enabled */
1650 /* Table Write Protect 04000-05FFF 6L options */
1651 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1652 #define _WRT_2_ON_6L 0xFB /* Enabled */
1654 /* Table Write Protect 06000-07FFF 6L options */
1655 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1656 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1659 /* Data EE Write Protect 6H options */
1660 #define _WRTD_OFF_6H 0xFF /* Disabled */
1661 #define _WRTD_ON_6H 0x7F /* Enabled */
1663 /* Table Write Protect Boot 6H options */
1664 #define _WRTB_OFF_6H 0xFF /* Disabled */
1665 #define _WRTB_ON_6H 0xBF /* Enabled */
1667 /* Config. Write Protect 6H options */
1668 #define _WRTC_OFF_6H 0xFF /* Disabled */
1669 #define _WRTC_ON_6H 0xDF /* Enabled */
1672 /* Table Read Protect 00800-01FFF 7L options */
1673 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1674 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1676 /* Table Read Protect 02000-03FFF 7L options */
1677 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1678 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1680 /* Table Read Protect 04000-05FFF 7L options */
1681 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1682 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1684 /* Table Read Protect 06000-07FFF 7L options */
1685 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1686 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1689 /* Table Read Protect Boot 7H options */
1690 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1691 #define _EBTRB_ON_7H 0xBF /* Enabled */
1695 /* Location of User ID words */
1696 #define __IDLOC0 0x200000
1697 #define __IDLOC1 0x200001
1698 #define __IDLOC2 0x200002
1699 #define __IDLOC3 0x200003
1700 #define __IDLOC4 0x200004
1701 #define __IDLOC5 0x200005
1702 #define __IDLOC6 0x200006
1703 #define __IDLOC7 0x200007
1705 #endif // __PIC18F2455__