3 * pic18f242.h - PIC18F242 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F242_H__
16 #define __PIC18F242_H__
18 extern sfr at 0xf80 PORTA;
65 extern volatile __PORTAbits_t at 0xf80 PORTAbits;
67 extern sfr at 0xf81 PORTB;
92 extern volatile __PORTBbits_t at 0xf81 PORTBbits;
94 extern sfr at 0xf82 PORTC;
130 extern volatile __PORTCbits_t at 0xf82 PORTCbits;
132 extern sfr at 0xf89 LATA;
146 extern volatile __LATAbits_t at 0xf89 LATAbits;
148 extern sfr at 0xf8a LATB;
162 extern volatile __LATBbits_t at 0xf8a LATBbits;
164 extern sfr at 0xf8b LATC;
178 extern volatile __LATCbits_t at 0xf8b LATCbits;
180 extern sfr at 0xf92 TRISA;
194 extern volatile __TRISAbits_t at 0xf92 TRISAbits;
196 extern sfr at 0xf93 TRISB;
210 extern volatile __TRISBbits_t at 0xf93 TRISBbits;
212 extern sfr at 0xf94 TRISC;
226 extern volatile __TRISCbits_t at 0xf94 TRISCbits;
228 extern sfr at 0xf9d PIE1;
242 extern volatile __PIE1bits_t at 0xf9d PIE1bits;
244 extern sfr at 0xf9e PIR1;
258 extern volatile __PIR1bits_t at 0xf9e PIR1bits;
260 extern sfr at 0xf9f IPR1;
274 extern volatile __IPR1bits_t at 0xf9f IPR1bits;
276 extern sfr at 0xfa0 PIE2;
290 extern volatile __PIE2bits_t at 0xfa0 PIE2bits;
292 extern sfr at 0xfa1 PIR2;
306 extern volatile __PIR2bits_t at 0xfa1 PIR2bits;
308 extern sfr at 0xfa2 IPR2;
322 extern volatile __IPR2bits_t at 0xfa2 IPR2bits;
324 extern sfr at 0xfa6 EECON1;
338 extern volatile __EECON1bits_t at 0xfa6 EECON1bits;
340 extern sfr at 0xfa7 EECON2;
341 extern sfr at 0xfa8 EEDATA;
342 extern sfr at 0xfa9 EEADR;
343 extern sfr at 0xfab RCSTA;
357 extern volatile __RCSTAbits_t at 0xfab RCSTAbits;
359 extern sfr at 0xfac TXSTA;
373 extern volatile __TXSTAbits_t at 0xfac TXSTAbits;
375 extern sfr at 0xfad TXREG;
376 extern sfr at 0xfae RCREG;
377 extern sfr at 0xfaf SPBRG;
378 extern sfr at 0xfb1 T3CON;
392 extern volatile __T3CONbits_t at 0xfb1 T3CONbits;
394 extern sfr at 0xfb2 TMR3L;
395 extern sfr at 0xfb3 TMR3H;
396 extern sfr at 0xfba CCP2CON;
410 extern volatile __CCP2CONbits_t at 0xfba CCP2CONbits;
412 extern sfr at 0xfbb CCPR2L;
413 extern sfr at 0xfbc CCPR2H;
414 extern sfr at 0xfbd CCP1CON;
428 extern volatile __CCP1CONbits_t at 0xfbd CCP1CONbits;
430 extern sfr at 0xfbe CCPR1L;
431 extern sfr at 0xfbf CCPR1H;
432 extern sfr at 0xfc1 ADCON1;
446 extern volatile __ADCON1bits_t at 0xfc1 ADCON1bits;
448 extern sfr at 0xfc2 ADCON0;
462 extern volatile __ADCON0bits_t at 0xfc2 ADCON0bits;
464 extern sfr at 0xfc3 ADRESL;
465 extern sfr at 0xfc4 ADRESH;
466 extern sfr at 0xfc5 SSPCON2;
480 extern volatile __SSPCON2bits_t at 0xfc5 SSPCON2bits;
482 extern sfr at 0xfc6 SSPCON1;
496 extern volatile __SSPCON1bits_t at 0xfc6 SSPCON1bits;
498 extern sfr at 0xfc7 SSPSTAT;
512 extern volatile __SSPSTATbits_t at 0xfc7 SSPSTATbits;
514 extern sfr at 0xfc8 SSPADD;
515 extern sfr at 0xfc9 SSPBUF;
516 extern sfr at 0xfca T2CON;
530 extern volatile __T2CONbits_t at 0xfca T2CONbits;
532 extern sfr at 0xfcb PR2;
533 extern sfr at 0xfcc TMR2;
534 extern sfr at 0xfcd T1CON;
539 unsigned NOT_T1SYNC:1;
548 extern volatile __T1CONbits_t at 0xfcd T1CONbits;
550 extern sfr at 0xfce TMR1L;
551 extern sfr at 0xfcf TMR1H;
552 extern sfr at 0xfd0 RCON;
566 extern volatile __RCONbits_t at 0xfd0 RCONbits;
568 extern sfr at 0xfd1 WDTCON;
593 extern volatile __WDTCONbits_t at 0xfd1 WDTCONbits;
595 extern sfr at 0xfd2 LVDCON;
620 extern volatile __LVDCONbits_t at 0xfd2 LVDCONbits;
622 extern sfr at 0xfd3 OSCCON;
636 extern volatile __OSCCONbits_t at 0xfd3 OSCCONbits;
638 extern sfr at 0xfd5 T0CON;
639 extern sfr at 0xfd6 TMR0L;
640 extern sfr at 0xfd7 TMR0H;
641 extern sfr at 0xfd8 STATUS;
655 extern volatile __STATUSbits_t at 0xfd8 STATUSbits;
657 extern sfr at 0xfd9 FSR2L;
658 extern sfr at 0xfda FSR2H;
659 extern sfr at 0xfdb PLUSW2;
660 extern sfr at 0xfdc PREINC2;
661 extern sfr at 0xfdd POSTDEC2;
662 extern sfr at 0xfde POSTINC2;
663 extern sfr at 0xfdf INDF2;
664 extern sfr at 0xfe0 BSR;
665 extern sfr at 0xfe1 FSR1L;
666 extern sfr at 0xfe2 FSR1H;
667 extern sfr at 0xfe3 PLUSW1;
668 extern sfr at 0xfe4 PREINC1;
669 extern sfr at 0xfe5 POSTDEC1;
670 extern sfr at 0xfe6 POSTINC1;
671 extern sfr at 0xfe7 INDF1;
672 extern sfr at 0xfe8 WREG;
673 extern sfr at 0xfe9 FSR0L;
674 extern sfr at 0xfea FSR0H;
675 extern sfr at 0xfeb PLUSW0;
676 extern sfr at 0xfec PREINC0;
677 extern sfr at 0xfed POSTDEC0;
678 extern sfr at 0xfee POSTINC0;
679 extern sfr at 0xfef INDF0;
680 extern sfr at 0xff0 INTCON3;
705 extern volatile __INTCON3bits_t at 0xff0 INTCON3bits;
707 extern sfr at 0xff1 INTCON2;
721 extern volatile __INTCON2bits_t at 0xff1 INTCON2bits;
723 extern sfr at 0xff2 INTCON;
737 extern volatile __INTCONbits_t at 0xff2 INTCONbits;
739 extern sfr at 0xff3 PRODL;
740 extern sfr at 0xff4 PRODH;
741 extern sfr at 0xff5 TABLAT;
742 extern sfr at 0xff6 TBLPTRL;
743 extern sfr at 0xff7 TBLPTRH;
744 extern sfr at 0xff8 TBLPTRU;
745 extern sfr at 0xff9 PCL;
746 extern sfr at 0xffa PCLATH;
747 extern sfr at 0xffb PCLATU;
748 extern sfr at 0xffc STKPTR;
762 extern volatile __STKPTRbits_t at 0xffc STKPTRbits;
764 extern sfr at 0xffd TOSL;
765 extern sfr at 0xffe TOSH;
766 extern sfr at 0xfff TOSU;
769 /* Configuration registers locations */
770 #define __CONFIG1H 0x300001
771 #define __CONFIG2L 0x300002
772 #define __CONFIG2H 0x300003
773 #define __CONFIG3H 0x300005
774 #define __CONFIG4L 0x300006
775 #define __CONFIG5L 0x300008
776 #define __CONFIG5H 0x300009
777 #define __CONFIG6L 0x30000A
778 #define __CONFIG6H 0x30000B
779 #define __CONFIG7L 0x30000C
780 #define __CONFIG7H 0x30000D
784 /* Oscillator 1H options */
785 #define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */
786 #define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */
787 #define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */
788 #define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */
789 #define _OSC_RC_1H 0xFB /* RC */
790 #define _OSC_HS_1H 0xFA /* HS */
791 #define _OSC_XT_1H 0xF9 /* XT */
792 #define _OSC_LP_1H 0xF8 /* LP */
794 /* Osc. Switch Enable 1H options */
795 #define _OSCS_OFF_1H 0xFF /* Disabled */
796 #define _OSCS_ON_1H 0xDF /* Enabled */
798 /* Power Up Timer 2L options */
799 #define _PUT_OFF_2L 0xFF /* Disabled */
800 #define _PUT_ON_2L 0xFE /* Enabled */
802 /* Brown Out Detect 2L options */
803 #define _BODEN_ON_2L 0xFF /* Enabled */
804 #define _BODEN_OFF_2L 0xFD /* Disabled */
806 /* Brown Out Voltage 2L options */
807 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
808 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
809 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
810 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
812 /* Watchdog Timer 2H options */
813 #define _WDT_ON_2H 0xFF /* Enabled */
814 #define _WDT_OFF_2H 0xFE /* Disabled */
816 /* Watchdog Postscaler 2H options */
817 #define _WDTPS_1_128_2H 0xFF /* 1:128 */
818 #define _WDTPS_1_64_2H 0xFD /* 1:64 */
819 #define _WDTPS_1_32_2H 0xFB /* 1:32 */
820 #define _WDTPS_1_16_2H 0xF9 /* 1:16 */
821 #define _WDTPS_1_8_2H 0xF7 /* 1:8 */
822 #define _WDTPS_1_4_2H 0xF5 /* 1:4 */
823 #define _WDTPS_1_2_2H 0xF3 /* 1:2 */
824 #define _WDTPS_1_1_2H 0xF1 /* 1:1 */
826 /* CCP2 Mux 3H options */
827 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
828 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
830 /* Low Voltage Program 4L options */
831 #define _LVP_ON_4L 0xFF /* Enabled */
832 #define _LVP_OFF_4L 0xFB /* Disabled */
834 /* Background Debug 4L options */
835 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
836 #define _BACKBUG_ON_4L 0x7F /* Enabled */
838 /* Stack Overflow Reset 4L options */
839 #define _STVR_ON_4L 0xFF /* Enabled */
840 #define _STVR_OFF_4L 0xFE /* Disabled */
842 /* Code Protect 00200-01FFF 5L options */
843 #define _CP_0_OFF_5L 0xFF /* Disabled */
844 #define _CP_0_ON_5L 0xFE /* Enabled */
846 /* Code Protect 02000-03FFF 5L options */
847 #define _CP_1_OFF_5L 0xFF /* Disabled */
848 #define _CP_1_ON_5L 0xFD /* Enabled */
850 /* Data EE Read Protect 5H options */
851 #define _CPD_OFF_5H 0xFF /* Disabled */
852 #define _CPD_ON_5H 0x7F /* Enabled */
854 /* Code Protect Boot 5H options */
855 #define _CPB_OFF_5H 0xFF /* Disabled */
856 #define _CPB_ON_5H 0xBF /* Enabled */
858 /* Table Write Protect 00200-01FFF 6L options */
859 #define _WRT_0_OFF_6L 0xFF /* Disabled */
860 #define _WRT_0_ON_6L 0xFE /* Enabled */
862 /* Table Write Protect 02000-03FFF 6L options */
863 #define _WRT_1_OFF_6L 0xFF /* Disabled */
864 #define _WRT_1_ON_6L 0xFD /* Enabled */
866 /* Data EE Write Protect 6H options */
867 #define _WRTD_OFF_6H 0xFF /* Disabled */
868 #define _WRTD_ON_6H 0x7F /* Enabled */
870 /* Table Write Protect Boot 6H options */
871 #define _WRTB_OFF_6H 0xFF /* Disabled */
872 #define _WRTB_ON_6H 0xBF /* Enabled */
874 /* Config. Write Protect 6H options */
875 #define _WRTC_OFF_6H 0xFF /* Disabled */
876 #define _WRTC_ON_6H 0xDF /* Enabled */
878 /* Table Read Protect 00200-01FFF 7L options */
879 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
880 #define _EBTR_0_ON_7L 0xFE /* Enabled */
882 /* Table Read Protect 02000-03FFF 7L options */
883 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
884 #define _EBTR_1_ON_7L 0xFD /* Enabled */
886 /* Table Read Protect Boot 7H options */
887 #define _EBTRB_OFF_7H 0xFF /* Disabled */
888 #define _EBTRB_ON_7H 0xBF /* Enabled */
891 /* Device ID locations */
892 #define __IDLOC0 0x200000
893 #define __IDLOC1 0x200001
894 #define __IDLOC2 0x200002
895 #define __IDLOC3 0x200003
896 #define __IDLOC4 0x200004
897 #define __IDLOC5 0x200005
898 #define __IDLOC6 0x200006
899 #define __IDLOC7 0x200007