3 * pic18f2220.h - PIC18F2220 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F2220_H__
16 #define __PIC18F2220_H__
18 extern __sfr __at (0xf80) PORTA;
65 extern volatile __PORTAbits_t __at (0xf80) PORTAbits;
67 extern __sfr __at (0xf81) PORTB;
103 extern volatile __PORTBbits_t __at (0xf81) PORTBbits;
105 extern __sfr __at (0xf82) PORTC;
141 extern volatile __PORTCbits_t __at (0xf82) PORTCbits;
143 extern __sfr __at (0xf89) LATA;
157 extern volatile __LATAbits_t __at (0xf89) LATAbits;
159 extern __sfr __at (0xf8a) LATB;
173 extern volatile __LATBbits_t __at (0xf8a) LATBbits;
175 extern __sfr __at (0xf8b) LATC;
189 extern volatile __LATCbits_t __at (0xf8b) LATCbits;
191 extern __sfr __at (0xf92) TRISA;
205 extern volatile __TRISAbits_t __at (0xf92) TRISAbits;
207 extern __sfr __at (0xf93) TRISB;
221 extern volatile __TRISBbits_t __at (0xf93) TRISBbits;
223 extern __sfr __at (0xf94) TRISC;
237 extern volatile __TRISCbits_t __at (0xf94) TRISCbits;
239 extern __sfr __at (0xf9b) OSCTUNE;
253 extern volatile __OSCTUNEbits_t __at (0xf9b) OSCTUNEbits;
255 extern __sfr __at (0xf9d) PIE1;
269 extern volatile __PIE1bits_t __at (0xf9d) PIE1bits;
271 extern __sfr __at (0xf9e) PIR1;
285 extern volatile __PIR1bits_t __at (0xf9e) PIR1bits;
287 extern __sfr __at (0xf9f) IPR1;
301 extern volatile __IPR1bits_t __at (0xf9f) IPR1bits;
303 extern __sfr __at (0xfa0) PIE2;
317 extern volatile __PIE2bits_t __at (0xfa0) PIE2bits;
319 extern __sfr __at (0xfa1) PIR2;
333 extern volatile __PIR2bits_t __at (0xfa1) PIR2bits;
335 extern __sfr __at (0xfa2) IPR2;
349 extern volatile __IPR2bits_t __at (0xfa2) IPR2bits;
351 extern __sfr __at (0xfa6) EECON1;
365 extern volatile __EECON1bits_t __at (0xfa6) EECON1bits;
367 extern __sfr __at (0xfa7) EECON2;
368 extern __sfr __at (0xfa8) EEDATA;
369 extern __sfr __at (0xfa9) EEADR;
370 extern __sfr __at (0xfab) RCSTA;
384 extern volatile __RCSTAbits_t __at (0xfab) RCSTAbits;
386 extern __sfr __at (0xfac) TXSTA;
400 extern volatile __TXSTAbits_t __at (0xfac) TXSTAbits;
402 extern __sfr __at (0xfad) TXREG;
403 extern __sfr __at (0xfae) RCREG;
404 extern __sfr __at (0xfaf) SPBRG;
405 extern __sfr __at (0xfb1) T3CON;
419 extern volatile __T3CONbits_t __at (0xfb1) T3CONbits;
421 extern __sfr __at (0xfb2) TMR3L;
422 extern __sfr __at (0xfb3) TMR3H;
423 extern __sfr __at (0xfb4) CMCON;
437 extern volatile __CMCONbits_t __at (0xfb4) CMCONbits;
439 extern __sfr __at (0xfb5) CVRCON;
453 extern volatile __CVRCONbits_t __at (0xfb5) CVRCONbits;
455 extern __sfr __at (0xfba) CCP2CON;
479 extern volatile __CCP2CONbits_t __at (0xfba) CCP2CONbits;
481 extern __sfr __at (0xfbb) CCPR2L;
482 extern __sfr __at (0xfbc) CCPR2H;
483 extern __sfr __at (0xfbd) CCP1CON;
507 extern volatile __CCP1CONbits_t __at (0xfbd) CCP1CONbits;
509 extern __sfr __at (0xfbe) CCPR1L;
510 extern __sfr __at (0xfbf) CCPR1H;
511 extern __sfr __at (0xfc0) ADCON2;
525 extern volatile __ADCON2bits_t __at (0xfc0) ADCON2bits;
527 extern __sfr __at (0xfc1) ADCON1;
541 extern volatile __ADCON1bits_t __at (0xfc1) ADCON1bits;
543 extern __sfr __at (0xfc2) ADCON0;
557 extern volatile __ADCON0bits_t __at (0xfc2) ADCON0bits;
559 extern __sfr __at (0xfc3) ADRESL;
560 extern __sfr __at (0xfc4) ADRESH;
561 extern __sfr __at (0xfc5) SSPCON2;
575 extern volatile __SSPCON2bits_t __at (0xfc5) SSPCON2bits;
577 extern __sfr __at (0xfc6) SSPCON1;
591 extern volatile __SSPCON1bits_t __at (0xfc6) SSPCON1bits;
593 extern __sfr __at (0xfc7) SSPSTAT;
607 extern volatile __SSPSTATbits_t __at (0xfc7) SSPSTATbits;
609 extern __sfr __at (0xfc8) SSPADD;
610 extern __sfr __at (0xfc9) SSPBUF;
611 extern __sfr __at (0xfca) T2CON;
625 extern volatile __T2CONbits_t __at (0xfca) T2CONbits;
627 extern __sfr __at (0xfcb) PR2;
628 extern __sfr __at (0xfcc) TMR2;
629 extern __sfr __at (0xfcd) T1CON;
634 unsigned NOT_T1SYNC:1;
643 extern volatile __T1CONbits_t __at (0xfcd) T1CONbits;
645 extern __sfr __at (0xfce) TMR1L;
646 extern __sfr __at (0xfcf) TMR1H;
647 extern __sfr __at (0xfd0) RCON;
661 extern volatile __RCONbits_t __at (0xfd0) RCONbits;
663 extern __sfr __at (0xfd1) WDTCON;
688 extern volatile __WDTCONbits_t __at (0xfd1) WDTCONbits;
690 extern __sfr __at (0xfd2) LVDCON;
715 extern volatile __LVDCONbits_t __at (0xfd2) LVDCONbits;
717 extern __sfr __at (0xfd3) OSCCON;
731 extern volatile __OSCCONbits_t __at (0xfd3) OSCCONbits;
733 extern __sfr __at (0xfd5) T0CON;
747 extern volatile __T0CONbits_t __at (0xfd5) T0CONbits;
749 extern __sfr __at (0xfd6) TMR0L;
750 extern __sfr __at (0xfd7) TMR0H;
751 extern __sfr __at (0xfd8) STATUS;
765 extern volatile __STATUSbits_t __at (0xfd8) STATUSbits;
767 extern __sfr __at (0xfd9) FSR2L;
768 extern __sfr __at (0xfda) FSR2H;
769 extern __sfr __at (0xfdb) PLUSW2;
770 extern __sfr __at (0xfdc) PREINC2;
771 extern __sfr __at (0xfdd) POSTDEC2;
772 extern __sfr __at (0xfde) POSTINC2;
773 extern __sfr __at (0xfdf) INDF2;
774 extern __sfr __at (0xfe0) BSR;
775 extern __sfr __at (0xfe1) FSR1L;
776 extern __sfr __at (0xfe2) FSR1H;
777 extern __sfr __at (0xfe3) PLUSW1;
778 extern __sfr __at (0xfe4) PREINC1;
779 extern __sfr __at (0xfe5) POSTDEC1;
780 extern __sfr __at (0xfe6) POSTINC1;
781 extern __sfr __at (0xfe7) INDF1;
782 extern __sfr __at (0xfe8) WREG;
783 extern __sfr __at (0xfe9) FSR0L;
784 extern __sfr __at (0xfea) FSR0H;
785 extern __sfr __at (0xfeb) PLUSW0;
786 extern __sfr __at (0xfec) PREINC0;
787 extern __sfr __at (0xfed) POSTDEC0;
788 extern __sfr __at (0xfee) POSTINC0;
789 extern __sfr __at (0xfef) INDF0;
790 extern __sfr __at (0xff0) INTCON3;
815 extern volatile __INTCON3bits_t __at (0xff0) INTCON3bits;
817 extern __sfr __at (0xff1) INTCON2;
831 extern volatile __INTCON2bits_t __at (0xff1) INTCON2bits;
833 extern __sfr __at (0xff2) INTCON;
847 extern volatile __INTCONbits_t __at (0xff2) INTCONbits;
849 extern __sfr __at (0xff3) PRODL;
850 extern __sfr __at (0xff4) PRODH;
851 extern __sfr __at (0xff5) TABLAT;
852 extern __sfr __at (0xff6) TBLPTRL;
853 extern __sfr __at (0xff7) TBLPTRH;
854 extern __sfr __at (0xff8) TBLPTRU;
855 extern __sfr __at (0xff9) PCL;
856 extern __sfr __at (0xffa) PCLATH;
857 extern __sfr __at (0xffb) PCLATU;
858 extern __sfr __at (0xffc) STKPTR;
872 extern volatile __STKPTRbits_t __at (0xffc) STKPTRbits;
874 extern __sfr __at (0xffd) TOSL;
875 extern __sfr __at (0xffe) TOSH;
876 extern __sfr __at (0xfff) TOSU;
879 /* Configuration registers locations */
880 #define __CONFIG1H 0x300001
881 #define __CONFIG2L 0x300002
882 #define __CONFIG2H 0x300003
883 #define __CONFIG3H 0x300005
884 #define __CONFIG4L 0x300006
885 #define __CONFIG5L 0x300008
886 #define __CONFIG5H 0x300009
887 #define __CONFIG6L 0x30000A
888 #define __CONFIG6H 0x30000B
889 #define __CONFIG7L 0x30000C
890 #define __CONFIG7H 0x30000D
894 /* Oscillator 1H options */
895 #define _OSC_11XX_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
896 #define _OSC_101X_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
897 #define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_1H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */
898 #define _OSC_INT_Port_on_RA6_Port_on_RA7_1H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */
899 #define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */
900 #define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
901 #define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */
902 #define _OSC_EC_CLKOUT_1H 0xF4 /* EC-CLKOUT on RA6 */
903 #define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
904 #define _OSC_HS_1H 0xF2 /* HS */
905 #define _OSC_XT_1H 0xF1 /* XT */
906 #define _OSC_LP_1H 0xF0 /* LP */
908 /* Fail Safe Clock Monitor Enable 1H options */
909 #define _FCMEN_OFF_1H 0xBF /* Disabled */
910 #define _FCMEN_ON_1H 0xFF /* Enabled */
912 /* Internal External Switch Over 1H options */
913 #define _IESO_OFF_1H 0x7F /* Disabled */
914 #define _IESO_ON_1H 0xFF /* Enabled */
916 /* Power Up Timer 2L options */
917 #define _PUT_OFF_2L 0xFF /* Disabled */
918 #define _PUT_ON_2L 0xFE /* Enabled */
920 /* Brown Out Detect 2L options */
921 #define _BODEN_ON_2L 0xFF /* Enabled */
922 #define _BODEN_OFF_2L 0xFD /* Disabled */
924 /* Brown Out Voltage 2L options */
925 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
926 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
927 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
928 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
930 /* Watchdog Timer 2H options */
931 #define _WDT_ON_2H 0xFF /* Enabled */
932 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
934 /* Watchdog Postscaler 2H options */
935 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
936 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
937 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
938 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
939 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
940 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
941 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
942 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
943 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
944 #define _WDTPS_1_64_2H 0xED /* 1:64 */
945 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
946 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
947 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
948 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
949 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
950 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
952 /* CCP2 Mux 3H options */
953 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
954 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
956 /* PortB A/D Enable 3H options */
957 #define _PBADEN_PORTB_4_0__analog_inputs_on_RSET_3H 0xFF /* PORTB<4:0> configured as analog_inputs_on_RESET */
958 #define _PBADEN_PORTB_4_0__digital_I_O_on_REST_3H 0xFD /* PORTB<4:0> configured as digital_I_O_on_RESET */
960 /* MCLR enable 3H options */
961 #define _MCLRE_MCLR_Enabled_RE3_Disabled_3H 0xFF /* MCLR Enabled_RE3_Disabled */
962 #define _MCLRE_MCLR_Disabled_RE3_Enabled_3H 0x7F /* MCLR Disabled__RE3_Enabled */
964 /* Stack Overflow Reset 4L options */
965 #define _STVR_ON_4L 0xFF /* Enabled */
966 #define _STVR_OFF_4L 0xFE /* Disabled */
968 /* Low Voltage Program 4L options */
969 #define _LVP_ON_4L 0xFF /* Enabled */
970 #define _LVP_OFF_4L 0xFB /* Disabled */
972 /* Background Debug 4L options */
973 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
974 #define _BACKBUG_ON_4L 0x7F /* Enabled */
976 /* Code Protect 000200-0007FF 5L options */
977 #define _CP_0_OFF_5L 0xFF /* Disabled */
978 #define _CP_0_ON_5L 0xFE /* Enabled */
980 /* Code Protect 000800-000FFF 5L options */
981 #define _CP_1_OFF_5L 0xFF /* Disabled */
982 #define _CP_1_ON_5L 0xFD /* Enabled */
984 /* Data EE Read Protect 5H options */
985 #define _CPD_OFF_5H 0xFF /* Disabled */
986 #define _CPD_ON_5H 0x7F /* Enabled */
988 /* Code Protect Boot 5H options */
989 #define _CPB_OFF_5H 0xFF /* Disabled */
990 #define _CPB_ON_5H 0xBF /* Enabled */
992 /* Table Write Protect 00200-007FF 6L options */
993 #define _WRT_0_OFF_6L 0xFF /* Disabled */
994 #define _WRT_0_ON_6L 0xFE /* Enabled */
996 /* Table Write Protect 00800-00FFF 6L options */
997 #define _WRT_1_OFF_6L 0xFF /* Disabled */
998 #define _WRT_1_ON_6L 0xFD /* Enabled */
1000 /* Data EE Write Protect 6H options */
1001 #define _WRTD_OFF_6H 0xFF /* Disabled */
1002 #define _WRTD_ON_6H 0x7F /* Enabled */
1004 /* Table Write Protect Boot 6H options */
1005 #define _WRTB_OFF_6H 0xFF /* Disabled */
1006 #define _WRTB_ON_6H 0xBF /* Enabled */
1008 /* Config. Write Protect 6H options */
1009 #define _WRTC_OFF_6H 0xFF /* Disabled */
1010 #define _WRTC_ON_6H 0xDF /* Enabled */
1012 /* Table Read Protect 00200-007FF 7L options */
1013 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1014 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1016 /* Table Read Protect 00800-00FFF 7L options */
1017 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1018 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1020 /* Table Read Protect Boot 7H options */
1021 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1022 #define _EBTRB_ON_7H 0xBF /* Enabled */
1025 /* Device ID locations */
1026 #define __IDLOC0 0x200000
1027 #define __IDLOC1 0x200001
1028 #define __IDLOC2 0x200002
1029 #define __IDLOC3 0x200003
1030 #define __IDLOC4 0x200004
1031 #define __IDLOC5 0x200005
1032 #define __IDLOC6 0x200006
1033 #define __IDLOC7 0x200007