3 * pic18f2220.h - PIC18F2220 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F2220_H__
16 #define __PIC18F2220_H__
18 extern __sfr __at 0xf80 PORTA;
65 extern volatile __PORTAbits_t __at 0xf80 PORTAbits;
67 extern __sfr __at 0xf81 PORTB;
92 extern volatile __PORTBbits_t __at 0xf81 PORTBbits;
94 extern __sfr __at 0xf82 PORTC;
130 extern volatile __PORTCbits_t __at 0xf82 PORTCbits;
132 extern __sfr __at 0xf89 LATA;
146 extern volatile __LATAbits_t __at 0xf89 LATAbits;
148 extern __sfr __at 0xf8a LATB;
162 extern volatile __LATBbits_t __at 0xf8a LATBbits;
164 extern __sfr __at 0xf8b LATC;
178 extern volatile __LATCbits_t __at 0xf8b LATCbits;
180 extern __sfr __at 0xf92 TRISA;
194 extern volatile __TRISAbits_t __at 0xf92 TRISAbits;
196 extern __sfr __at 0xf93 TRISB;
210 extern volatile __TRISBbits_t __at 0xf93 TRISBbits;
212 extern __sfr __at 0xf94 TRISC;
226 extern volatile __TRISCbits_t __at 0xf94 TRISCbits;
228 extern __sfr __at 0xf9b OSCTUNE;
242 extern volatile __OSCTUNEbits_t __at 0xf9b OSCTUNEbits;
244 extern __sfr __at 0xf9d PIE1;
258 extern volatile __PIE1bits_t __at 0xf9d PIE1bits;
260 extern __sfr __at 0xf9e PIR1;
274 extern volatile __PIR1bits_t __at 0xf9e PIR1bits;
276 extern __sfr __at 0xf9f IPR1;
290 extern volatile __IPR1bits_t __at 0xf9f IPR1bits;
292 extern __sfr __at 0xfa0 PIE2;
306 extern volatile __PIE2bits_t __at 0xfa0 PIE2bits;
308 extern __sfr __at 0xfa1 PIR2;
322 extern volatile __PIR2bits_t __at 0xfa1 PIR2bits;
324 extern __sfr __at 0xfa2 IPR2;
338 extern volatile __IPR2bits_t __at 0xfa2 IPR2bits;
340 extern __sfr __at 0xfa6 EECON1;
354 extern volatile __EECON1bits_t __at 0xfa6 EECON1bits;
356 extern __sfr __at 0xfa7 EECON2;
357 extern __sfr __at 0xfa8 EEDATA;
358 extern __sfr __at 0xfa9 EEADR;
359 extern __sfr __at 0xfab RCSTA;
373 extern volatile __RCSTAbits_t __at 0xfab RCSTAbits;
375 extern __sfr __at 0xfac TXSTA;
389 extern volatile __TXSTAbits_t __at 0xfac TXSTAbits;
391 extern __sfr __at 0xfad TXREG;
392 extern __sfr __at 0xfae RCREG;
393 extern __sfr __at 0xfaf SPBRG;
394 extern __sfr __at 0xfb1 T3CON;
408 extern volatile __T3CONbits_t __at 0xfb1 T3CONbits;
410 extern __sfr __at 0xfb2 TMR3L;
411 extern __sfr __at 0xfb3 TMR3H;
412 extern __sfr __at 0xfb4 CMCON;
426 extern volatile __CMCONbits_t __at 0xfb4 CMCONbits;
428 extern __sfr __at 0xfb5 CVRCON;
442 extern volatile __CVRCONbits_t __at 0xfb5 CVRCONbits;
444 extern __sfr __at 0xfba CCP2CON;
458 extern volatile __CCP2CONbits_t __at 0xfba CCP2CONbits;
460 extern __sfr __at 0xfbb CCPR2L;
461 extern __sfr __at 0xfbc CCPR2H;
462 extern __sfr __at 0xfbd CCP1CON;
476 extern volatile __CCP1CONbits_t __at 0xfbd CCP1CONbits;
478 extern __sfr __at 0xfbe CCPR1L;
479 extern __sfr __at 0xfbf CCPR1H;
480 extern __sfr __at 0xfc0 ADCON2;
494 extern volatile __ADCON2bits_t __at 0xfc0 ADCON2bits;
496 extern __sfr __at 0xfc1 ADCON1;
510 extern volatile __ADCON1bits_t __at 0xfc1 ADCON1bits;
512 extern __sfr __at 0xfc2 ADCON0;
526 extern volatile __ADCON0bits_t __at 0xfc2 ADCON0bits;
528 extern __sfr __at 0xfc3 ADRESL;
529 extern __sfr __at 0xfc4 ADRESH;
530 extern __sfr __at 0xfc5 SSPCON2;
544 extern volatile __SSPCON2bits_t __at 0xfc5 SSPCON2bits;
546 extern __sfr __at 0xfc6 SSPCON1;
560 extern volatile __SSPCON1bits_t __at 0xfc6 SSPCON1bits;
562 extern __sfr __at 0xfc7 SSPSTAT;
576 extern volatile __SSPSTATbits_t __at 0xfc7 SSPSTATbits;
578 extern __sfr __at 0xfc8 SSPADD;
579 extern __sfr __at 0xfc9 SSPBUF;
580 extern __sfr __at 0xfca T2CON;
594 extern volatile __T2CONbits_t __at 0xfca T2CONbits;
596 extern __sfr __at 0xfcb PR2;
597 extern __sfr __at 0xfcc TMR2;
598 extern __sfr __at 0xfcd T1CON;
603 unsigned NOT_T1SYNC:1;
612 extern volatile __T1CONbits_t __at 0xfcd T1CONbits;
614 extern __sfr __at 0xfce TMR1L;
615 extern __sfr __at 0xfcf TMR1H;
616 extern __sfr __at 0xfd0 RCON;
630 extern volatile __RCONbits_t __at 0xfd0 RCONbits;
632 extern __sfr __at 0xfd1 WDTCON;
657 extern volatile __WDTCONbits_t __at 0xfd1 WDTCONbits;
659 extern __sfr __at 0xfd2 LVDCON;
684 extern volatile __LVDCONbits_t __at 0xfd2 LVDCONbits;
686 extern __sfr __at 0xfd3 OSCCON;
700 extern volatile __OSCCONbits_t __at 0xfd3 OSCCONbits;
702 extern __sfr __at 0xfd5 T0CON;
703 extern __sfr __at 0xfd6 TMR0L;
704 extern __sfr __at 0xfd7 TMR0H;
705 extern __sfr __at 0xfd8 STATUS;
719 extern volatile __STATUSbits_t __at 0xfd8 STATUSbits;
721 extern __sfr __at 0xfd9 FSR2L;
722 extern __sfr __at 0xfda FSR2H;
723 extern __sfr __at 0xfdb PLUSW2;
724 extern __sfr __at 0xfdc PREINC2;
725 extern __sfr __at 0xfdd POSTDEC2;
726 extern __sfr __at 0xfde POSTINC2;
727 extern __sfr __at 0xfdf INDF2;
728 extern __sfr __at 0xfe0 BSR;
729 extern __sfr __at 0xfe1 FSR1L;
730 extern __sfr __at 0xfe2 FSR1H;
731 extern __sfr __at 0xfe3 PLUSW1;
732 extern __sfr __at 0xfe4 PREINC1;
733 extern __sfr __at 0xfe5 POSTDEC1;
734 extern __sfr __at 0xfe6 POSTINC1;
735 extern __sfr __at 0xfe7 INDF1;
736 extern __sfr __at 0xfe8 WREG;
737 extern __sfr __at 0xfe9 FSR0L;
738 extern __sfr __at 0xfea FSR0H;
739 extern __sfr __at 0xfeb PLUSW0;
740 extern __sfr __at 0xfec PREINC0;
741 extern __sfr __at 0xfed POSTDEC0;
742 extern __sfr __at 0xfee POSTINC0;
743 extern __sfr __at 0xfef INDF0;
744 extern __sfr __at 0xff0 INTCON3;
769 extern volatile __INTCON3bits_t __at 0xff0 INTCON3bits;
771 extern __sfr __at 0xff1 INTCON2;
785 extern volatile __INTCON2bits_t __at 0xff1 INTCON2bits;
787 extern __sfr __at 0xff2 INTCON;
801 extern volatile __INTCONbits_t __at 0xff2 INTCONbits;
803 extern __sfr __at 0xff3 PRODL;
804 extern __sfr __at 0xff4 PRODH;
805 extern __sfr __at 0xff5 TABLAT;
806 extern __sfr __at 0xff6 TBLPTRL;
807 extern __sfr __at 0xff7 TBLPTRH;
808 extern __sfr __at 0xff8 TBLPTRU;
809 extern __sfr __at 0xff9 PCL;
810 extern __sfr __at 0xffa PCLATH;
811 extern __sfr __at 0xffb PCLATU;
812 extern __sfr __at 0xffc STKPTR;
826 extern volatile __STKPTRbits_t __at 0xffc STKPTRbits;
828 extern __sfr __at 0xffd TOSL;
829 extern __sfr __at 0xffe TOSH;
830 extern __sfr __at 0xfff TOSU;
833 /* Configuration registers locations */
834 #define __CONFIG1H 0x300001
835 #define __CONFIG2L 0x300002
836 #define __CONFIG2H 0x300003
837 #define __CONFIG3H 0x300005
838 #define __CONFIG4L 0x300006
839 #define __CONFIG5L 0x300008
840 #define __CONFIG5H 0x300009
841 #define __CONFIG6L 0x30000A
842 #define __CONFIG6H 0x30000B
843 #define __CONFIG7L 0x30000C
844 #define __CONFIG7H 0x30000D
848 /* Oscillator 1H options */
849 #define _OSC_11XX_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
850 #define _OSC_101X_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
851 #define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_1H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */
852 #define _OSC_INT_Port_on_RA6_Port_on_RA7_1H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */
853 #define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */
854 #define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
855 #define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */
856 #define _OSC_EC_CLKOUT_1H 0xF4 /* EC-CLKOUT on RA6 */
857 #define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
858 #define _OSC_HS_1H 0xF2 /* HS */
859 #define _OSC_XT_1H 0xF1 /* XT */
860 #define _OSC_LP_1H 0xF0 /* LP */
862 /* Fail Safe Clock Monitor Enable 1H options */
863 #define _FCMEN_OFF_1H 0xBF /* Disabled */
864 #define _FCMEN_ON_1H 0xFF /* Enabled */
866 /* Internal External Switch Over 1H options */
867 #define _IESO_OFF_1H 0x7F /* Disabled */
868 #define _IESO_ON_1H 0xFF /* Enabled */
870 /* Power Up Timer 2L options */
871 #define _PUT_OFF_2L 0xFF /* Disabled */
872 #define _PUT_ON_2L 0xFE /* Enabled */
874 /* Brown Out Detect 2L options */
875 #define _BODEN_ON_2L 0xFF /* Enabled */
876 #define _BODEN_OFF_2L 0xFD /* Disabled */
878 /* Brown Out Voltage 2L options */
879 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
880 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
881 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
882 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
884 /* Watchdog Timer 2H options */
885 #define _WDT_ON_2H 0xFF /* Enabled */
886 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
888 /* Watchdog Postscaler 2H options */
889 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
890 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
891 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
892 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
893 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
894 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
895 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
896 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
897 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
898 #define _WDTPS_1_64_2H 0xED /* 1:64 */
899 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
900 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
901 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
902 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
903 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
904 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
906 /* CCP2 Mux 3H options */
907 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
908 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
910 /* PortB A/D Enable 3H options */
911 #define _PBADEN_PORTB_4_0__analog_inputs_on_RSET_3H 0xFF /* PORTB<4:0> configured as analog_inputs_on_RESET */
912 #define _PBADEN_PORTB_4_0__digital_I_O_on_REST_3H 0xFD /* PORTB<4:0> configured as digital_I_O_on_RESET */
914 /* MCLR enable 3H options */
915 #define _MCLRE_MCLR_Enabled_RE3_Disabled_3H 0xFF /* MCLR Enabled_RE3_Disabled */
916 #define _MCLRE_MCLR_Disabled_RE3_Enabled_3H 0x7F /* MCLR Disabled__RE3_Enabled */
918 /* Stack Overflow Reset 4L options */
919 #define _STVR_ON_4L 0xFF /* Enabled */
920 #define _STVR_OFF_4L 0xFE /* Disabled */
922 /* Low Voltage Program 4L options */
923 #define _LVP_ON_4L 0xFF /* Enabled */
924 #define _LVP_OFF_4L 0xFB /* Disabled */
926 /* Background Debug 4L options */
927 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
928 #define _BACKBUG_ON_4L 0x7F /* Enabled */
930 /* Code Protect 000200-0007FF 5L options */
931 #define _CP_0_OFF_5L 0xFF /* Disabled */
932 #define _CP_0_ON_5L 0xFE /* Enabled */
934 /* Code Protect 000800-000FFF 5L options */
935 #define _CP_1_OFF_5L 0xFF /* Disabled */
936 #define _CP_1_ON_5L 0xFD /* Enabled */
938 /* Data EE Read Protect 5H options */
939 #define _CPD_OFF_5H 0xFF /* Disabled */
940 #define _CPD_ON_5H 0x7F /* Enabled */
942 /* Code Protect Boot 5H options */
943 #define _CPB_OFF_5H 0xFF /* Disabled */
944 #define _CPB_ON_5H 0xBF /* Enabled */
946 /* Table Write Protect 00200-007FF 6L options */
947 #define _WRT_0_OFF_6L 0xFF /* Disabled */
948 #define _WRT_0_ON_6L 0xFE /* Enabled */
950 /* Table Write Protect 00800-00FFF 6L options */
951 #define _WRT_1_OFF_6L 0xFF /* Disabled */
952 #define _WRT_1_ON_6L 0xFD /* Enabled */
954 /* Data EE Write Protect 6H options */
955 #define _WRTD_OFF_6H 0xFF /* Disabled */
956 #define _WRTD_ON_6H 0x7F /* Enabled */
958 /* Table Write Protect Boot 6H options */
959 #define _WRTB_OFF_6H 0xFF /* Disabled */
960 #define _WRTB_ON_6H 0xBF /* Enabled */
962 /* Config. Write Protect 6H options */
963 #define _WRTC_OFF_6H 0xFF /* Disabled */
964 #define _WRTC_ON_6H 0xDF /* Enabled */
966 /* Table Read Protect 00200-007FF 7L options */
967 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
968 #define _EBTR_0_ON_7L 0xFE /* Enabled */
970 /* Table Read Protect 00800-00FFF 7L options */
971 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
972 #define _EBTR_1_ON_7L 0xFD /* Enabled */
974 /* Table Read Protect Boot 7H options */
975 #define _EBTRB_OFF_7H 0xFF /* Disabled */
976 #define _EBTRB_ON_7H 0xBF /* Enabled */
979 /* Device ID locations */
980 #define __IDLOC0 0x200000
981 #define __IDLOC1 0x200001
982 #define __IDLOC2 0x200002
983 #define __IDLOC3 0x200003
984 #define __IDLOC4 0x200004
985 #define __IDLOC5 0x200005
986 #define __IDLOC6 0x200006
987 #define __IDLOC7 0x200007