3 * pic18f1220.h - PIC18F1220 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
11 * $Id: pic18f1220.h 5369 2009-02-09 23:45:54Z tecodev $
15 #ifndef __PIC18F1220_H__
16 #define __PIC18F1220_H__
18 extern __sfr __at (0xf80) PORTA;
65 extern volatile __PORTAbits_t __at (0xf80) PORTAbits;
67 extern __sfr __at (0xf81) PORTB;
92 extern volatile __PORTBbits_t __at (0xf81) PORTBbits;
94 extern __sfr __at (0xf89) LATA;
108 extern volatile __LATAbits_t __at (0xf89) LATAbits;
110 extern __sfr __at (0xf8a) LATB;
124 extern volatile __LATBbits_t __at (0xf8a) LATBbits;
126 extern __sfr __at (0xf92) TRISA;
140 extern volatile __TRISAbits_t __at (0xf92) TRISAbits;
142 extern __sfr __at (0xf93) TRISB;
156 extern volatile __TRISBbits_t __at (0xf93) TRISBbits;
158 extern __sfr __at (0xf9d) PIE1;
172 extern volatile __PIE1bits_t __at (0xf9d) PIE1bits;
174 extern __sfr __at (0xf9e) PIR1;
188 extern volatile __PIR1bits_t __at (0xf9e) PIR1bits;
190 extern __sfr __at (0xf9f) IPR1;
204 extern volatile __IPR1bits_t __at (0xf9f) IPR1bits;
206 extern __sfr __at (0xfa0) PIE2;
220 extern volatile __PIE2bits_t __at (0xfa0) PIE2bits;
222 extern __sfr __at (0xfa1) PIR2;
236 extern volatile __PIR2bits_t __at (0xfa1) PIR2bits;
238 extern __sfr __at (0xfa2) IPR2;
252 extern volatile __IPR2bits_t __at (0xfa2) IPR2bits;
254 extern __sfr __at (0xfa6) EECON1;
268 extern volatile __EECON1bits_t __at (0xfa6) EECON1bits;
270 extern __sfr __at (0xfa7) EECON2;
271 extern __sfr __at (0xfa8) EEDATA;
272 extern __sfr __at (0xfa9) EEADR;
273 extern __sfr __at (0xfaa) BAUDCTL;
274 extern __sfr __at (0xfab) RCSTA;
288 extern volatile __RCSTAbits_t __at (0xfab) RCSTAbits;
290 extern __sfr __at (0xfac) TXSTA;
304 extern volatile __TXSTAbits_t __at (0xfac) TXSTAbits;
306 extern __sfr __at (0xfad) TXREG;
307 extern __sfr __at (0xfae) RCREG;
308 extern __sfr __at (0xfaf) SPBRG;
309 extern __sfr __at (0xfb0) SPBRGH;
310 extern __sfr __at (0xfb1) T3CON;
324 extern volatile __T3CONbits_t __at (0xfb1) T3CONbits;
326 extern __sfr __at (0xfb2) TMR3L;
327 extern __sfr __at (0xfb3) TMR3H;
328 extern __sfr __at (0xfb6) ECCPAS;
342 extern volatile __ECCPASbits_t __at (0xfb6) ECCPASbits;
344 extern __sfr __at (0xfbd) CCP1CON;
358 extern volatile __CCP1CONbits_t __at (0xfbd) CCP1CONbits;
360 extern __sfr __at (0xfbe) CCPR1L;
361 extern __sfr __at (0xfbf) CCPR1H;
362 extern __sfr __at (0xfc0) ADCON2;
376 extern volatile __ADCON2bits_t __at (0xfc0) ADCON2bits;
378 extern __sfr __at (0xfc1) ADCON1;
392 extern volatile __ADCON1bits_t __at (0xfc1) ADCON1bits;
394 extern __sfr __at (0xfc2) ADCON0;
408 extern volatile __ADCON0bits_t __at (0xfc2) ADCON0bits;
410 extern __sfr __at (0xfc3) ADRESL;
411 extern __sfr __at (0xfc4) ADRESH;
412 extern __sfr __at (0xfca) T2CON;
426 extern volatile __T2CONbits_t __at (0xfca) T2CONbits;
428 extern __sfr __at (0xfcb) PR2;
429 extern __sfr __at (0xfcc) TMR2;
430 extern __sfr __at (0xfcd) T1CON;
435 unsigned NOT_T1SYNC:1;
444 extern volatile __T1CONbits_t __at (0xfcd) T1CONbits;
446 extern __sfr __at (0xfce) TMR1L;
447 extern __sfr __at (0xfcf) TMR1H;
448 extern __sfr __at (0xfd0) RCON;
462 extern volatile __RCONbits_t __at (0xfd0) RCONbits;
464 extern __sfr __at (0xfd1) WDTCON;
489 extern volatile __WDTCONbits_t __at (0xfd1) WDTCONbits;
491 extern __sfr __at (0xfd2) LVDCON;
516 extern volatile __LVDCONbits_t __at (0xfd2) LVDCONbits;
518 extern __sfr __at (0xfd3) OSCCON;
532 extern volatile __OSCCONbits_t __at (0xfd3) OSCCONbits;
534 extern __sfr __at (0xfd5) T0CON;
547 extern volatile __T0CONbits_t __at (0xfd5) T0CONbits;
549 extern __sfr __at (0xfd6) TMR0L;
550 extern __sfr __at (0xfd7) TMR0H;
551 extern __sfr __at (0xfd8) STATUS;
565 extern volatile __STATUSbits_t __at (0xfd8) STATUSbits;
567 extern __sfr __at (0xfd9) FSR2L;
568 extern __sfr __at (0xfda) FSR2H;
569 extern __sfr __at (0xfdb) PLUSW2;
570 extern __sfr __at (0xfdc) PREINC2;
571 extern __sfr __at (0xfdd) POSTDEC2;
572 extern __sfr __at (0xfde) POSTINC2;
573 extern __sfr __at (0xfdf) INDF2;
574 extern __sfr __at (0xfe0) BSR;
575 extern __sfr __at (0xfe1) FSR1L;
576 extern __sfr __at (0xfe2) FSR1H;
577 extern __sfr __at (0xfe3) PLUSW1;
578 extern __sfr __at (0xfe4) PREINC1;
579 extern __sfr __at (0xfe5) POSTDEC1;
580 extern __sfr __at (0xfe6) POSTINC1;
581 extern __sfr __at (0xfe7) INDF1;
582 extern __sfr __at (0xfe8) WREG;
583 extern __sfr __at (0xfe9) FSR0L;
584 extern __sfr __at (0xfea) FSR0H;
585 extern __sfr __at (0xfeb) PLUSW0;
586 extern __sfr __at (0xfec) PREINC0;
587 extern __sfr __at (0xfed) POSTDEC0;
588 extern __sfr __at (0xfee) POSTINC0;
589 extern __sfr __at (0xfef) INDF0;
590 extern __sfr __at (0xff0) INTCON3;
615 extern volatile __INTCON3bits_t __at (0xff0) INTCON3bits;
617 extern __sfr __at (0xff1) INTCON2;
631 extern volatile __INTCON2bits_t __at (0xff1) INTCON2bits;
633 extern __sfr __at (0xff2) INTCON;
657 extern volatile __INTCONbits_t __at (0xff2) INTCONbits;
659 extern __sfr __at (0xff3) PRODL;
660 extern __sfr __at (0xff4) PRODH;
661 extern __sfr __at (0xff5) TABLAT;
662 extern __sfr __at (0xff6) TBLPTRL;
663 extern __sfr __at (0xff7) TBLPTRH;
664 extern __sfr __at (0xff8) TBLPTRU;
665 extern __sfr __at (0xff9) PCL;
666 extern __sfr __at (0xffa) PCLATH;
667 extern __sfr __at (0xffb) PCLATU;
668 extern __sfr __at (0xffc) STKPTR;
682 extern volatile __STKPTRbits_t __at (0xffc) STKPTRbits;
684 extern __sfr __at (0xffd) TOSL;
685 extern __sfr __at (0xffe) TOSH;
686 extern __sfr __at (0xfff) TOSU;
689 /* Configuration registers locations */
690 #define __CONFIG1H 0x300001
691 #define __CONFIG2L 0x300002
692 #define __CONFIG2H 0x300003
693 #define __CONFIG3H 0x300005
694 #define __CONFIG4L 0x300006
695 #define __CONFIG5L 0x300008
696 #define __CONFIG5H 0x300009
697 #define __CONFIG6L 0x30000A
698 #define __CONFIG6H 0x30000B
699 #define __CONFIG7L 0x30000C
700 #define __CONFIG7H 0x30000D
704 /* Oscillator 1H options */
705 #define _OSC_11XX_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
706 #define _OSC_101X_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
707 #define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_1H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */
708 #define _OSC_INT_Port_on_RA6_Port_on_RA7_1H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */
709 #define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */
710 #define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
711 #define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */
712 #define _OSC_EC_CLKOUT_1H 0xF4 /* EC-CLKOUT on RA6 */
713 #define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
714 #define _OSC_HS_1H 0xF2 /* HS */
715 #define _OSC_XT_1H 0xF1 /* XT */
716 #define _OSC_LP_1H 0xF0 /* LP */
718 /* Fail Safe Clock Monitor Enable 1H options */
719 #define _FCMEN_OFF_1H 0xBF /* Disabled */
720 #define _FCMEN_ON_1H 0xFF /* Enabled */
722 /* Internal External Switch Over 1H options */
723 #define _IESO_OFF_1H 0x7F /* Disabled */
724 #define _IESO_ON_1H 0xFF /* Enabled */
726 /* Power Up Timer 2L options */
727 #define _PUT_OFF_2L 0xFF /* Disabled */
728 #define _PUT_ON_2L 0xFE /* Enabled */
730 /* Brown Out Detect 2L options */
731 #define _BODEN_ON_2L 0xFF /* Enabled */
732 #define _BODEN_OFF_2L 0xFD /* Disabled */
734 /* Brown Out Voltage 2L options */
735 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
736 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
737 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
738 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
740 /* Watchdog Timer 2H options */
741 #define _WDT_ON_2H 0xFF /* Enabled */
742 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
744 /* Watchdog Postscaler 2H options */
745 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
746 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
747 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
748 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
749 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
750 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
751 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
752 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
753 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
754 #define _WDTPS_1_64_2H 0xED /* 1:64 */
755 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
756 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
757 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
758 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
759 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
760 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
762 /* MCLR enable 3H options */
763 #define _MCLRE_MCLR_enabled_RA5_input_dis_3H 0xFF /* MCLR enabled__RA5_input_disabled */
764 #define _MCLRE_MCLR_disabled_RA5_input_en_3H 0x7F /* MCLR disabled__RA5_input_enabled */
766 /* Stack Overflow Reset 4L options */
767 #define _STVR_ON_4L 0xFF /* Enabled */
768 #define _STVR_OFF_4L 0xFE /* Disabled */
770 /* Low Voltage Program 4L options */
771 #define _LVP_ON_4L 0xFF /* Enabled */
772 #define _LVP_OFF_4L 0xFB /* Disabled */
774 /* Background Debug 4L options */
775 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
776 #define _BACKBUG_ON_4L 0x7F /* Enabled */
778 /* Code Protect 000200-0007FF 5L options */
779 #define _CP_0_OFF_5L 0xFF /* Disabled */
780 #define _CP_0_ON_5L 0xFE /* Enabled */
782 /* Code Protect 000800-000FFF 5L options */
783 #define _CP_1_OFF_5L 0xFF /* Disabled */
784 #define _CP_1_ON_5L 0xFD /* Enabled */
786 /* Data EE Read Protect 5H options */
787 #define _CPD_OFF_5H 0xFF /* Disabled */
788 #define _CPD_ON_5H 0x7F /* Enabled */
790 /* Code Protect Boot 5H options */
791 #define _CPB_OFF_5H 0xFF /* Disabled */
792 #define _CPB_ON_5H 0xBF /* Enabled */
794 /* Table Write Protect 00200-007FF 6L options */
795 #define _WRT_0_OFF_6L 0xFF /* Disabled */
796 #define _WRT_0_ON_6L 0xFE /* Enabled */
798 /* Table Write Protect 00800-00FFF 6L options */
799 #define _WRT_1_OFF_6L 0xFF /* Disabled */
800 #define _WRT_1_ON_6L 0xFD /* Enabled */
802 /* Data EE Write Protect 6H options */
803 #define _WRTD_OFF_6H 0xFF /* Disabled */
804 #define _WRTD_ON_6H 0x7F /* Enabled */
806 /* Table Write Protect Boot 6H options */
807 #define _WRTB_OFF_6H 0xFF /* Disabled */
808 #define _WRTB_ON_6H 0xBF /* Enabled */
810 /* Config. Write Protect 6H options */
811 #define _WRTC_OFF_6H 0xFF /* Disabled */
812 #define _WRTC_ON_6H 0xDF /* Enabled */
814 /* Table Read Protect 00200-007FF 7L options */
815 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
816 #define _EBTR_0_ON_7L 0xFE /* Enabled */
818 /* Table Read Protect 000800-00FFF 7L options */
819 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
820 #define _EBTR_1_ON_7L 0xFD /* Enabled */
822 /* Table Read Protect Boot 7H options */
823 #define _EBTRB_OFF_7H 0xFF /* Disabled */
824 #define _EBTRB_ON_7H 0xBF /* Enabled */
827 /* Device ID locations */
828 #define __IDLOC0 0x200000
829 #define __IDLOC1 0x200001
830 #define __IDLOC2 0x200002
831 #define __IDLOC3 0x200003
832 #define __IDLOC4 0x200004
833 #define __IDLOC5 0x200005
834 #define __IDLOC6 0x200006
835 #define __IDLOC7 0x200007