3 * pic18f1220.h - PIC18F1220 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F1220_H__
16 #define __PIC18F1220_H__
18 extern sfr at 0xf80 PORTA;
65 extern volatile __PORTAbits_t at 0xf80 PORTAbits;
67 extern sfr at 0xf81 PORTB;
92 extern volatile __PORTBbits_t at 0xf81 PORTBbits;
94 extern sfr at 0xf89 LATA;
108 extern volatile __LATAbits_t at 0xf89 LATAbits;
110 extern sfr at 0xf8a LATB;
124 extern volatile __LATBbits_t at 0xf8a LATBbits;
126 extern sfr at 0xf92 TRISA;
140 extern volatile __TRISAbits_t at 0xf92 TRISAbits;
142 extern sfr at 0xf93 TRISB;
156 extern volatile __TRISBbits_t at 0xf93 TRISBbits;
158 extern sfr at 0xf9d PIE1;
172 extern volatile __PIE1bits_t at 0xf9d PIE1bits;
174 extern sfr at 0xf9e PIR1;
188 extern volatile __PIR1bits_t at 0xf9e PIR1bits;
190 extern sfr at 0xf9f IPR1;
204 extern volatile __IPR1bits_t at 0xf9f IPR1bits;
206 extern sfr at 0xfa0 PIE2;
220 extern volatile __PIE2bits_t at 0xfa0 PIE2bits;
222 extern sfr at 0xfa1 PIR2;
236 extern volatile __PIR2bits_t at 0xfa1 PIR2bits;
238 extern sfr at 0xfa2 IPR2;
252 extern volatile __IPR2bits_t at 0xfa2 IPR2bits;
254 extern sfr at 0xfa6 EECON1;
268 extern volatile __EECON1bits_t at 0xfa6 EECON1bits;
270 extern sfr at 0xfa7 EECON2;
271 extern sfr at 0xfa8 EEDATA;
272 extern sfr at 0xfa9 EEADR;
273 extern sfr at 0xfaa BAUDCTL;
274 extern sfr at 0xfab RCSTA;
288 extern volatile __RCSTAbits_t at 0xfab RCSTAbits;
290 extern sfr at 0xfac TXSTA;
304 extern volatile __TXSTAbits_t at 0xfac TXSTAbits;
306 extern sfr at 0xfad TXREG;
307 extern sfr at 0xfae RCREG;
308 extern sfr at 0xfaf SPBRG;
309 extern sfr at 0xfb0 SPBRGH;
310 extern sfr at 0xfb1 T3CON;
324 extern volatile __T3CONbits_t at 0xfb1 T3CONbits;
326 extern sfr at 0xfb2 TMR3L;
327 extern sfr at 0xfb3 TMR3H;
328 extern sfr at 0xfbd CCP1CON;
342 extern volatile __CCP1CONbits_t at 0xfbd CCP1CONbits;
344 extern sfr at 0xfbe CCPR1L;
345 extern sfr at 0xfbf CCPR1H;
346 extern sfr at 0xfc0 ADCON2;
360 extern volatile __ADCON2bits_t at 0xfc0 ADCON2bits;
362 extern sfr at 0xfc1 ADCON1;
376 extern volatile __ADCON1bits_t at 0xfc1 ADCON1bits;
378 extern sfr at 0xfc2 ADCON0;
392 extern volatile __ADCON0bits_t at 0xfc2 ADCON0bits;
394 extern sfr at 0xfc3 ADRESL;
395 extern sfr at 0xfc4 ADRESH;
396 extern sfr at 0xfca T2CON;
410 extern volatile __T2CONbits_t at 0xfca T2CONbits;
412 extern sfr at 0xfcb PR2;
413 extern sfr at 0xfcc TMR2;
414 extern sfr at 0xfcd T1CON;
419 unsigned NOT_T1SYNC:1;
428 extern volatile __T1CONbits_t at 0xfcd T1CONbits;
430 extern sfr at 0xfce TMR1L;
431 extern sfr at 0xfcf TMR1H;
432 extern sfr at 0xfd0 RCON;
446 extern volatile __RCONbits_t at 0xfd0 RCONbits;
448 extern sfr at 0xfd1 WDTCON;
473 extern volatile __WDTCONbits_t at 0xfd1 WDTCONbits;
475 extern sfr at 0xfd2 LVDCON;
500 extern volatile __LVDCONbits_t at 0xfd2 LVDCONbits;
502 extern sfr at 0xfd3 OSCCON;
516 extern volatile __OSCCONbits_t at 0xfd3 OSCCONbits;
518 extern sfr at 0xfd5 T0CON;
519 extern sfr at 0xfd6 TMR0L;
520 extern sfr at 0xfd7 TMR0H;
521 extern sfr at 0xfd8 STATUS;
535 extern volatile __STATUSbits_t at 0xfd8 STATUSbits;
537 extern sfr at 0xfd9 FSR2L;
538 extern sfr at 0xfda FSR2H;
539 extern sfr at 0xfdb PLUSW2;
540 extern sfr at 0xfdc PREINC2;
541 extern sfr at 0xfdd POSTDEC2;
542 extern sfr at 0xfde POSTINC2;
543 extern sfr at 0xfdf INDF2;
544 extern sfr at 0xfe0 BSR;
545 extern sfr at 0xfe1 FSR1L;
546 extern sfr at 0xfe2 FSR1H;
547 extern sfr at 0xfe3 PLUSW1;
548 extern sfr at 0xfe4 PREINC1;
549 extern sfr at 0xfe5 POSTDEC1;
550 extern sfr at 0xfe6 POSTINC1;
551 extern sfr at 0xfe7 INDF1;
552 extern sfr at 0xfe8 WREG;
553 extern sfr at 0xfe9 FSR0L;
554 extern sfr at 0xfea FSR0H;
555 extern sfr at 0xfeb PLUSW0;
556 extern sfr at 0xfec PREINC0;
557 extern sfr at 0xfed POSTDEC0;
558 extern sfr at 0xfee POSTINC0;
559 extern sfr at 0xfef INDF0;
560 extern sfr at 0xff0 INTCON3;
585 extern volatile __INTCON3bits_t at 0xff0 INTCON3bits;
587 extern sfr at 0xff1 INTCON2;
601 extern volatile __INTCON2bits_t at 0xff1 INTCON2bits;
603 extern sfr at 0xff2 INTCON;
617 extern volatile __INTCONbits_t at 0xff2 INTCONbits;
619 extern sfr at 0xff3 PRODL;
620 extern sfr at 0xff4 PRODH;
621 extern sfr at 0xff5 TABLAT;
622 extern sfr at 0xff6 TBLPTRL;
623 extern sfr at 0xff7 TBLPTRH;
624 extern sfr at 0xff8 TBLPTRU;
625 extern sfr at 0xff9 PCL;
626 extern sfr at 0xffa PCLATH;
627 extern sfr at 0xffb PCLATU;
628 extern sfr at 0xffc STKPTR;
642 extern volatile __STKPTRbits_t at 0xffc STKPTRbits;
644 extern sfr at 0xffd TOSL;
645 extern sfr at 0xffe TOSH;
646 extern sfr at 0xfff TOSU;
649 /* Configuration registers locations */
650 #define __CONFIG1H 0x300001
651 #define __CONFIG2L 0x300002
652 #define __CONFIG2H 0x300003
653 #define __CONFIG3H 0x300005
654 #define __CONFIG4L 0x300006
655 #define __CONFIG5L 0x300008
656 #define __CONFIG5H 0x300009
657 #define __CONFIG6L 0x30000A
658 #define __CONFIG6H 0x30000B
659 #define __CONFIG7L 0x30000C
660 #define __CONFIG7H 0x30000D
664 /* Oscillator 1H options */
665 #define _OSC_11XX_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
666 #define _OSC_101X_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
667 #define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_1H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */
668 #define _OSC_INT_Port_on_RA6_Port_on_RA7_1H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */
669 #define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */
670 #define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
671 #define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */
672 #define _OSC_EC_CLKOUT_1H 0xF4 /* EC-CLKOUT on RA6 */
673 #define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
674 #define _OSC_HS_1H 0xF2 /* HS */
675 #define _OSC_XT_1H 0xF1 /* XT */
676 #define _OSC_LP_1H 0xF0 /* LP */
678 /* Fail Safe Clock Monitor Enable 1H options */
679 #define _FCMEN_OFF_1H 0xBF /* Disabled */
680 #define _FCMEN_ON_1H 0xFF /* Enabled */
682 /* Internal External Switch Over 1H options */
683 #define _IESO_OFF_1H 0x7F /* Disabled */
684 #define _IESO_ON_1H 0xFF /* Enabled */
686 /* Power Up Timer 2L options */
687 #define _PUT_OFF_2L 0xFF /* Disabled */
688 #define _PUT_ON_2L 0xFE /* Enabled */
690 /* Brown Out Detect 2L options */
691 #define _BODEN_ON_2L 0xFF /* Enabled */
692 #define _BODEN_OFF_2L 0xFD /* Disabled */
694 /* Brown Out Voltage 2L options */
695 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
696 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
697 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
698 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
700 /* Watchdog Timer 2H options */
701 #define _WDT_ON_2H 0xFF /* Enabled */
702 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
704 /* Watchdog Postscaler 2H options */
705 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
706 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
707 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
708 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
709 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
710 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
711 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
712 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
713 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
714 #define _WDTPS_1_64_2H 0xED /* 1:64 */
715 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
716 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
717 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
718 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
719 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
720 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
722 /* MCLR enable 3H options */
723 #define _MCLRE_MCLR_enabled_RA5_input_dis_3H 0xFF /* MCLR enabled__RA5_input_disabled */
724 #define _MCLRE_MCLR_disabled_RA5_input_en_3H 0x7F /* MCLR disabled__RA5_input_enabled */
726 /* Stack Overflow Reset 4L options */
727 #define _STVR_ON_4L 0xFF /* Enabled */
728 #define _STVR_OFF_4L 0xFE /* Disabled */
730 /* Low Voltage Program 4L options */
731 #define _LVP_ON_4L 0xFF /* Enabled */
732 #define _LVP_OFF_4L 0xFB /* Disabled */
734 /* Background Debug 4L options */
735 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
736 #define _BACKBUG_ON_4L 0x7F /* Enabled */
738 /* Code Protect 000200-0007FF 5L options */
739 #define _CP_0_OFF_5L 0xFF /* Disabled */
740 #define _CP_0_ON_5L 0xFE /* Enabled */
742 /* Code Protect 000800-000FFF 5L options */
743 #define _CP_1_OFF_5L 0xFF /* Disabled */
744 #define _CP_1_ON_5L 0xFD /* Enabled */
746 /* Data EE Read Protect 5H options */
747 #define _CPD_OFF_5H 0xFF /* Disabled */
748 #define _CPD_ON_5H 0x7F /* Enabled */
750 /* Code Protect Boot 5H options */
751 #define _CPB_OFF_5H 0xFF /* Disabled */
752 #define _CPB_ON_5H 0xBF /* Enabled */
754 /* Table Write Protect 00200-007FF 6L options */
755 #define _WRT_0_OFF_6L 0xFF /* Disabled */
756 #define _WRT_0_ON_6L 0xFE /* Enabled */
758 /* Table Write Protect 00800-00FFF 6L options */
759 #define _WRT_1_OFF_6L 0xFF /* Disabled */
760 #define _WRT_1_ON_6L 0xFD /* Enabled */
762 /* Data EE Write Protect 6H options */
763 #define _WRTD_OFF_6H 0xFF /* Disabled */
764 #define _WRTD_ON_6H 0x7F /* Enabled */
766 /* Table Write Protect Boot 6H options */
767 #define _WRTB_OFF_6H 0xFF /* Disabled */
768 #define _WRTB_ON_6H 0xBF /* Enabled */
770 /* Config. Write Protect 6H options */
771 #define _WRTC_OFF_6H 0xFF /* Disabled */
772 #define _WRTC_ON_6H 0xDF /* Enabled */
774 /* Table Read Protect 00200-007FF 7L options */
775 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
776 #define _EBTR_0_ON_7L 0xFE /* Enabled */
778 /* Table Read Protect 000800-00FFF 7L options */
779 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
780 #define _EBTR_1_ON_7L 0xFD /* Enabled */
782 /* Table Read Protect Boot 7H options */
783 #define _EBTRB_OFF_7H 0xFF /* Disabled */
784 #define _EBTRB_ON_7H 0xBF /* Enabled */
787 /* Device ID locations */
788 #define __IDLOC0 0x200000
789 #define __IDLOC1 0x200001
790 #define __IDLOC2 0x200002
791 #define __IDLOC3 0x200003
792 #define __IDLOC4 0x200004
793 #define __IDLOC5 0x200005
794 #define __IDLOC6 0x200006
795 #define __IDLOC7 0x200007