2 // Register Declarations for Microchip 16F916 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTE_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define PIR1_ADDR 0x000C
40 #define PIR2_ADDR 0x000D
41 #define TMR1L_ADDR 0x000E
42 #define TMR1H_ADDR 0x000F
43 #define T1CON_ADDR 0x0010
44 #define TMR2_ADDR 0x0011
45 #define T2CON_ADDR 0x0012
46 #define SSPBUF_ADDR 0x0013
47 #define SSPCON_ADDR 0x0014
48 #define CCPR1L_ADDR 0x0015
49 #define CCPR1H_ADDR 0x0016
50 #define CCP1CON_ADDR 0x0017
51 #define RCSTA_ADDR 0x0018
52 #define TXREG_ADDR 0x0019
53 #define RCREG_ADDR 0x001A
54 #define ADRESH_ADDR 0x001E
55 #define ADCON0_ADDR 0x001F
56 #define OPTION_REG_ADDR 0x0081
57 #define TRISA_ADDR 0x0085
58 #define TRISB_ADDR 0x0086
59 #define TRISC_ADDR 0x0087
60 #define TRISE_ADDR 0x0089
61 #define PIE1_ADDR 0x008C
62 #define PIE2_ADDR 0x008D
63 #define PCON_ADDR 0x008E
64 #define OSCCON_ADDR 0x008F
65 #define OSCTUNE_ADDR 0x0090
66 #define ANSEL_ADDR 0x0091
67 #define PR2_ADDR 0x0092
68 #define SSPADD_ADDR 0x0093
69 #define SSPSTAT_ADDR 0x0094
70 #define WPUB_ADDR 0x0095
71 #define WPU_ADDR 0x0095
72 #define IOCB_ADDR 0x0096
73 #define IOC_ADDR 0x0096
74 #define CMCON1_ADDR 0x0097
75 #define TXSTA_ADDR 0x0098
76 #define SPBRG_ADDR 0x0099
77 #define CMCON0_ADDR 0x009C
78 #define VRCON_ADDR 0x009D
79 #define ADRESL_ADDR 0x009E
80 #define ADCON1_ADDR 0x009F
81 #define WDTCON_ADDR 0x0105
82 #define LCDCON_ADDR 0x0107
83 #define LCDPS_ADDR 0x0108
84 #define LVDCON_ADDR 0x0109
85 #define EEDATL_ADDR 0x010C
86 #define EEADRL_ADDR 0x010D
87 #define EEDATH_ADDR 0x010E
88 #define EEADRH_ADDR 0x010F
89 #define LCDDATA0_ADDR 0x0110
90 #define LCDDATA1_ADDR 0x0111
91 #define LCDDATA3_ADDR 0x0113
92 #define LCDDATA4_ADDR 0x0114
93 #define LCDDATA6_ADDR 0x0116
94 #define LCDDATA7_ADDR 0x0117
95 #define LCDDATA9_ADDR 0x0119
96 #define LCDDATA10_ADDR 0x011A
97 #define LCDSE0_ADDR 0x011C
98 #define LCDSE1_ADDR 0x011D
99 #define EECON1_ADDR 0x018C
100 #define EECON2_ADDR 0x018D
103 // Memory organization.
106 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
107 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
108 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
109 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
110 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
111 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
112 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
113 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
114 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
115 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
116 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
117 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
118 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
119 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
120 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
121 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
122 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
123 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
124 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
125 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
126 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
127 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
128 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
129 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
130 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
131 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
132 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
133 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
134 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
135 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
136 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
137 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
138 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
139 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
140 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
141 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
142 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
143 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
144 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
145 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
146 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
147 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
148 #pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB
149 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
150 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
151 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
152 #pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
153 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
154 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
155 #pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
156 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
157 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
158 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
159 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
160 #pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON
161 #pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS
162 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
163 #pragma memmap EEDATL_ADDR EEDATL_ADDR SFR 0x000 // EEDATL
164 #pragma memmap EEADRL_ADDR EEADRL_ADDR SFR 0x000 // EEADRL
165 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
166 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
167 #pragma memmap LCDDATA0_ADDR LCDDATA0_ADDR SFR 0x000 // LCDDATA0
168 #pragma memmap LCDDATA1_ADDR LCDDATA1_ADDR SFR 0x000 // LCDDATA1
169 #pragma memmap LCDDATA3_ADDR LCDDATA3_ADDR SFR 0x000 // LCDDATA3
170 #pragma memmap LCDDATA4_ADDR LCDDATA4_ADDR SFR 0x000 // LCDDATA4
171 #pragma memmap LCDDATA6_ADDR LCDDATA6_ADDR SFR 0x000 // LCDDATA6
172 #pragma memmap LCDDATA7_ADDR LCDDATA7_ADDR SFR 0x000 // LCDDATA7
173 #pragma memmap LCDDATA9_ADDR LCDDATA9_ADDR SFR 0x000 // LCDDATA9
174 #pragma memmap LCDDATA10_ADDR LCDDATA10_ADDR SFR 0x000 // LCDDATA10
175 #pragma memmap LCDSE0_ADDR LCDSE0_ADDR SFR 0x000 // LCDSE0
176 #pragma memmap LCDSE1_ADDR LCDSE1_ADDR SFR 0x000 // LCDSE1
177 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
178 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
182 // P16F916.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
185 // This header file defines configurations, registers, and other useful bits of
186 // information for the PIC16F916 microcontroller.
187 // These names are taken to match the data sheets as closely as possible.
189 // Note that the processor must be selected before this file is
190 // included. The processor may be selected the following ways:
192 // 1. Command line switch:
193 // C:\ MPASM MYFILE.ASM /PIC16F916
194 // 2. LIST directive in the source file
196 // 3. Processor Type entry in the MPASM full-screen interface
198 //==========================================================================
202 //==========================================================================
205 //1.00 06/11/04 Initial Release
206 //1.01 06/18/04 Corrected typo in 'bad ram' section
207 //1.02 08/16/04 Added EECON2
209 //==========================================================================
213 //==========================================================================
216 // MESSG "Processor-header file mismatch. Verify selected processor."
219 //==========================================================================
221 // Register Definitions
223 //==========================================================================
228 //----- Register Files------------------------------------------------------
230 extern data __at (INDF_ADDR) volatile char INDF;
231 extern sfr __at (TMR0_ADDR) TMR0;
232 extern data __at (PCL_ADDR) volatile char PCL;
233 extern sfr __at (STATUS_ADDR) STATUS;
234 extern sfr __at (FSR_ADDR) FSR;
235 extern sfr __at (PORTA_ADDR) PORTA;
236 extern sfr __at (PORTB_ADDR) PORTB;
237 extern sfr __at (PORTC_ADDR) PORTC;
238 extern sfr __at (PORTE_ADDR) PORTE;
239 extern sfr __at (PCLATH_ADDR) PCLATH;
240 extern sfr __at (INTCON_ADDR) INTCON;
241 extern sfr __at (PIR1_ADDR) PIR1;
242 extern sfr __at (PIR2_ADDR) PIR2;
243 extern sfr __at (TMR1L_ADDR) TMR1L;
244 extern sfr __at (TMR1H_ADDR) TMR1H;
245 extern sfr __at (T1CON_ADDR) T1CON;
246 extern sfr __at (TMR2_ADDR) TMR2;
247 extern sfr __at (T2CON_ADDR) T2CON;
248 extern sfr __at (SSPBUF_ADDR) SSPBUF;
249 extern sfr __at (SSPCON_ADDR) SSPCON;
250 extern sfr __at (CCPR1L_ADDR) CCPR1L;
251 extern sfr __at (CCPR1H_ADDR) CCPR1H;
252 extern sfr __at (CCP1CON_ADDR) CCP1CON;
253 extern sfr __at (RCSTA_ADDR) RCSTA;
254 extern sfr __at (TXREG_ADDR) TXREG;
255 extern sfr __at (RCREG_ADDR) RCREG;
256 extern sfr __at (ADRESH_ADDR) ADRESH;
257 extern sfr __at (ADCON0_ADDR) ADCON0;
259 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
260 extern sfr __at (TRISA_ADDR) TRISA;
261 extern sfr __at (TRISB_ADDR) TRISB;
262 extern sfr __at (TRISC_ADDR) TRISC;
263 extern sfr __at (TRISE_ADDR) TRISE;
264 extern sfr __at (PIE1_ADDR) PIE1;
265 extern sfr __at (PIE2_ADDR) PIE2;
266 extern sfr __at (PCON_ADDR) PCON;
267 extern sfr __at (OSCCON_ADDR) OSCCON;
268 extern sfr __at (OSCTUNE_ADDR) OSCTUNE;
269 extern sfr __at (ANSEL_ADDR) ANSEL;
270 extern sfr __at (PR2_ADDR) PR2;
271 extern sfr __at (SSPADD_ADDR) SSPADD;
272 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
273 extern sfr __at (WPUB_ADDR) WPUB;
274 extern sfr __at (WPU_ADDR) WPU;
275 extern sfr __at (IOCB_ADDR) IOCB;
276 extern sfr __at (IOC_ADDR) IOC;
277 extern sfr __at (CMCON1_ADDR) CMCON1;
278 extern sfr __at (TXSTA_ADDR) TXSTA;
279 extern sfr __at (SPBRG_ADDR) SPBRG;
280 extern sfr __at (CMCON0_ADDR) CMCON0;
281 extern sfr __at (VRCON_ADDR) VRCON;
282 extern sfr __at (ADRESL_ADDR) ADRESL;
283 extern sfr __at (ADCON1_ADDR) ADCON1;
285 extern sfr __at (WDTCON_ADDR) WDTCON;
286 extern sfr __at (LCDCON_ADDR) LCDCON;
287 extern sfr __at (LCDPS_ADDR) LCDPS;
288 extern sfr __at (LVDCON_ADDR) LVDCON;
289 extern sfr __at (EEDATL_ADDR) EEDATL;
290 extern sfr __at (EEADRL_ADDR) EEADRL;
291 extern sfr __at (EEDATH_ADDR) EEDATH;
292 extern sfr __at (EEADRH_ADDR) EEADRH;
293 extern sfr __at (LCDDATA0_ADDR) LCDDATA0;
294 extern sfr __at (LCDDATA1_ADDR) LCDDATA1;
295 extern sfr __at (LCDDATA3_ADDR) LCDDATA3;
296 extern sfr __at (LCDDATA4_ADDR) LCDDATA4;
297 extern sfr __at (LCDDATA6_ADDR) LCDDATA6;
298 extern sfr __at (LCDDATA7_ADDR) LCDDATA7;
299 extern sfr __at (LCDDATA9_ADDR) LCDDATA9;
300 extern sfr __at (LCDDATA10_ADDR) LCDDATA10;
301 extern sfr __at (LCDSE0_ADDR) LCDSE0;
302 extern sfr __at (LCDSE1_ADDR) LCDSE1;
304 extern sfr __at (EECON1_ADDR) EECON1;
305 extern sfr __at (EECON2_ADDR) EECON2;
308 //----- STATUS Bits --------------------------------------------------------
311 //----- INTCON Bits --------------------------------------------------------
314 //----- PIR1 Bits ----------------------------------------------------------
317 //----- PIR2 Bits ----------------------------------------------------------
320 //----- T1CON Bits ---------------------------------------------------------
323 //----- T2CON Bits ---------------------------------------------------------
326 //----- SSPCON Bits --------------------------------------------------------
329 //----- CCP1CON Bits -------------------------------------------------------
332 //----- RCSTA Bits ---------------------------------------------------------
336 //----- ADCON0 Bits --------------------------------------------------------
339 //----- OPTION Bits -----------------------------------------------------
342 //----- PIE1 Bits ----------------------------------------------------------
345 //----- PIE2 Bits ----------------------------------------------------------
348 //----- PCON Bits ----------------------------------------------------------
351 //----- OSCCON Bits -------------------------------------------------------
354 //----- OSCTUNE Bits -------------------------------------------------------
358 //----- ANSEL Bits ---------------------------------------------------------
362 //----- SSPSTAT Bits -------------------------------------------------------
366 //----- WPUB Bits -------------------------------------------------------
369 //----- WPU Bits -------------------------------------------------------
373 //----- IOCB Bits -------------------------------------------------------
377 //----- IOC Bits -------------------------------------------------------
381 //----- CMCON1 Bits --------------------------------------------------------
384 //----- TXSTA Bits ---------------------------------------------------------
388 //----- CMCON0 Bits ---------------------------------------------------------
391 //----- VRCON Bits --------------------------------------------------------
394 //----- ADCON1 Bits --------------------------------------------------------
397 //----- WDTCON Bits --------------------------------------------------------
400 //----- LCDCON Bits --------------------------------------------------------
403 //----- LCDPS Bits ---------------------------------------------------------
406 //----- LVDCON Bits --------------------------------------------------------
409 //----- LCDDATA0 Bits -------------------------------------------------------
413 //----- LCDDATA1 Bits -------------------------------------------------------
418 //----- LCDDATA3 Bits -------------------------------------------------------
422 //----- LCDDATA4 Bits -------------------------------------------------------
427 //----- LCDDATA6 Bits -------------------------------------------------------
431 //----- LCDDATA7 Bits -------------------------------------------------------
436 //----- LCDDATA9 Bits -------------------------------------------------------
440 //----- LCDDATA10 Bits -------------------------------------------------------
445 //----- LCDSE0 Bits --------------------------------------------------------
449 //----- LCDSE1 Bits --------------------------------------------------------
454 //----- EECON1 Bits --------------------------------------------------------
458 //==========================================================================
462 //==========================================================================
465 // __BADRAM H'08', H'1B'-H'1D'
466 // __BADRAM H'88', H'9A'-H'9B'
467 // __BADRAM H'112', H'115', H'118', H'11B',H'11E'-H'11F'
468 // __BADRAM H'185', H'187'-H'189', H'18D'-H'18F'
470 //==========================================================================
472 // Configuration Bits
474 //==========================================================================
476 #define _CONFIG 0x2007
478 //Configuration Byte 1 Options
479 #define _DEBUG_ON 0x2FFF
480 #define _DEBUG_OFF 0x3FFF
481 #define _FCMEN_ON 0x3FFF
482 #define _FCMEN_OFF 0x37FF
483 #define _IESO_ON 0x3FFF
484 #define _IESO_OFF 0x3BFF
485 #define _BOD_ON 0x3FFF
486 #define _BOD_NSLEEP 0x3EFF
487 #define _BOD_SBODEN 0x3DFF
488 #define _BOD_OFF 0x3CFF
489 #define _CPD_ON 0x3F7F
490 #define _CPD_OFF 0x3FFF
491 #define _CP_ON 0x3FBF
492 #define _CP_OFF 0x3FFF
493 #define _MCLRE_ON 0x3FFF
494 #define _MCLRE_OFF 0x3FDF
495 #define _PWRTE_ON 0x3FEF
496 #define _PWRTE_OFF 0x3FFF
497 #define _WDT_ON 0x3FFF
498 #define _WDT_OFF 0x3FF7
499 #define _LP_OSC 0x3FF8
500 #define _XT_OSC 0x3FF9
501 #define _HS_OSC 0x3FFA
502 #define _EC_OSC 0x3FFB
503 #define _INTRC_OSC_NOCLKOUT 0x3FFC
504 #define _INTRC_OSC_CLKOUT 0x3FFD
505 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
506 #define _EXTRC_OSC_CLKOUT 0x3FFF
507 #define _INTOSCIO 0x3FFC
508 #define _INTOSC 0x3FFD
509 #define _EXTRCIO 0x3FFE
510 #define _EXTRC 0x3FFF
515 // ----- ADCON0 bits --------------------
518 unsigned char ADON:1;
519 unsigned char NOT_DONE:1;
520 unsigned char CHS0:1;
521 unsigned char CHS1:1;
522 unsigned char CHS2:1;
523 unsigned char VCFG0:1;
524 unsigned char VCFG1:1;
525 unsigned char ADFM:1;
529 unsigned char GO_DONE:1;
538 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
540 #define ADON ADCON0_bits.ADON
541 #define NOT_DONE ADCON0_bits.NOT_DONE
542 #define GO_DONE ADCON0_bits.GO_DONE
543 #define CHS0 ADCON0_bits.CHS0
544 #define CHS1 ADCON0_bits.CHS1
545 #define CHS2 ADCON0_bits.CHS2
546 #define VCFG0 ADCON0_bits.VCFG0
547 #define VCFG1 ADCON0_bits.VCFG1
548 #define ADFM ADCON0_bits.ADFM
550 // ----- ADCON1 bits --------------------
557 unsigned char ADCS0:1;
558 unsigned char ADCS1:1;
559 unsigned char ADCS2:1;
563 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
565 #define ADCS0 ADCON1_bits.ADCS0
566 #define ADCS1 ADCON1_bits.ADCS1
567 #define ADCS2 ADCON1_bits.ADCS2
569 // ----- ANSEL bits --------------------
582 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
584 #define AN0 ANSEL_bits.AN0
585 #define AN1 ANSEL_bits.AN1
586 #define AN2 ANSEL_bits.AN2
587 #define AN3 ANSEL_bits.AN3
588 #define AN4 ANSEL_bits.AN4
590 // ----- CCP1CON bits --------------------
593 unsigned char CCP1M0:1;
594 unsigned char CCP1M1:1;
595 unsigned char CCP1M2:1;
596 unsigned char CCP1M3:1;
597 unsigned char CCP1Y:1;
598 unsigned char CCP1X:1;
603 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
605 #define CCP1M0 CCP1CON_bits.CCP1M0
606 #define CCP1M1 CCP1CON_bits.CCP1M1
607 #define CCP1M2 CCP1CON_bits.CCP1M2
608 #define CCP1M3 CCP1CON_bits.CCP1M3
609 #define CCP1Y CCP1CON_bits.CCP1Y
610 #define CCP1X CCP1CON_bits.CCP1X
612 // ----- CMCON0 bits --------------------
619 unsigned char C1INV:1;
620 unsigned char C2INV:1;
621 unsigned char C1OUT:1;
622 unsigned char C2OUT:1;
625 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
627 #define CM0 CMCON0_bits.CM0
628 #define CM1 CMCON0_bits.CM1
629 #define CM2 CMCON0_bits.CM2
630 #define CIS CMCON0_bits.CIS
631 #define C1INV CMCON0_bits.C1INV
632 #define C2INV CMCON0_bits.C2INV
633 #define C1OUT CMCON0_bits.C1OUT
634 #define C2OUT CMCON0_bits.C2OUT
636 // ----- CMCON1 bits --------------------
639 unsigned char C2SYNC:1;
640 unsigned char T1GSS:1;
649 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
651 #define C2SYNC CMCON1_bits.C2SYNC
652 #define T1GSS CMCON1_bits.T1GSS
654 // ----- EECON1 bits --------------------
659 unsigned char WREN:1;
660 unsigned char WRERR:1;
664 unsigned char EEPGD:1;
667 unsigned char EERD:1;
668 unsigned char EEWR:1;
677 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
679 #define RD EECON1_bits.RD
680 #define EERD EECON1_bits.EERD
681 #define WR EECON1_bits.WR
682 #define EEWR EECON1_bits.EEWR
683 #define WREN EECON1_bits.WREN
684 #define WRERR EECON1_bits.WRERR
685 #define EEPGD EECON1_bits.EEPGD
687 // ----- INTCON bits --------------------
690 unsigned char RBIF:1;
691 unsigned char INTF:1;
692 unsigned char T0IF:1;
693 unsigned char RBIE:1;
694 unsigned char INTE:1;
695 unsigned char T0IE:1;
696 unsigned char PEIE:1;
702 unsigned char TMR0IF:1;
705 unsigned char TMR0IE:1;
710 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
712 #define RBIF INTCON_bits.RBIF
713 #define INTF INTCON_bits.INTF
714 #define T0IF INTCON_bits.T0IF
715 #define TMR0IF INTCON_bits.TMR0IF
716 #define RBIE INTCON_bits.RBIE
717 #define INTE INTCON_bits.INTE
718 #define T0IE INTCON_bits.T0IE
719 #define TMR0IE INTCON_bits.TMR0IE
720 #define PEIE INTCON_bits.PEIE
721 #define GIE INTCON_bits.GIE
723 // ----- IOC bits --------------------
730 unsigned char IOC4:1;
731 unsigned char IOC5:1;
732 unsigned char IOC6:1;
733 unsigned char IOC7:1;
736 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
738 #define IOC4 IOC_bits.IOC4
739 #define IOC5 IOC_bits.IOC5
740 #define IOC6 IOC_bits.IOC6
741 #define IOC7 IOC_bits.IOC7
743 // ----- IOCB bits --------------------
750 unsigned char IOCB4:1;
751 unsigned char IOCB5:1;
752 unsigned char IOCB6:1;
753 unsigned char IOCB7:1;
756 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
758 #define IOCB4 IOCB_bits.IOCB4
759 #define IOCB5 IOCB_bits.IOCB5
760 #define IOCB6 IOCB_bits.IOCB6
761 #define IOCB7 IOCB_bits.IOCB7
763 // ----- LCDCON bits --------------------
766 unsigned char LMUX0:1;
767 unsigned char LMUX1:1;
770 unsigned char VLCDEN:1;
771 unsigned char WERR:1;
772 unsigned char SLPEN:1;
773 unsigned char LCDEN:1;
776 extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits;
778 #define LMUX0 LCDCON_bits.LMUX0
779 #define LMUX1 LCDCON_bits.LMUX1
780 #define CS0 LCDCON_bits.CS0
781 #define CS1 LCDCON_bits.CS1
782 #define VLCDEN LCDCON_bits.VLCDEN
783 #define WERR LCDCON_bits.WERR
784 #define SLPEN LCDCON_bits.SLPEN
785 #define LCDEN LCDCON_bits.LCDEN
787 // ----- LCDDATA0 bits --------------------
790 unsigned char SEG0COM0:1;
791 unsigned char SEG1COM0:1;
792 unsigned char SEG2COM0:1;
793 unsigned char SEG3COM0:1;
794 unsigned char SEG4COM0:1;
795 unsigned char SEG5COM0:1;
796 unsigned char SEG6COM0:1;
797 unsigned char SEG7COM0:1;
800 unsigned char S0C0:1;
801 unsigned char S1C0:1;
802 unsigned char S2C0:1;
803 unsigned char S3C0:1;
804 unsigned char S4C0:1;
805 unsigned char S5C0:1;
806 unsigned char S6C0:1;
807 unsigned char S7C0:1;
810 extern volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits;
812 #define SEG0COM0 LCDDATA0_bits.SEG0COM0
813 #define S0C0 LCDDATA0_bits.S0C0
814 #define SEG1COM0 LCDDATA0_bits.SEG1COM0
815 #define S1C0 LCDDATA0_bits.S1C0
816 #define SEG2COM0 LCDDATA0_bits.SEG2COM0
817 #define S2C0 LCDDATA0_bits.S2C0
818 #define SEG3COM0 LCDDATA0_bits.SEG3COM0
819 #define S3C0 LCDDATA0_bits.S3C0
820 #define SEG4COM0 LCDDATA0_bits.SEG4COM0
821 #define S4C0 LCDDATA0_bits.S4C0
822 #define SEG5COM0 LCDDATA0_bits.SEG5COM0
823 #define S5C0 LCDDATA0_bits.S5C0
824 #define SEG6COM0 LCDDATA0_bits.SEG6COM0
825 #define S6C0 LCDDATA0_bits.S6C0
826 #define SEG7COM0 LCDDATA0_bits.SEG7COM0
827 #define S7C0 LCDDATA0_bits.S7C0
829 // ----- LCDDATA1 bits --------------------
832 unsigned char SEG8COM0:1;
833 unsigned char SEG9COM0:1;
834 unsigned char SEG10COM0:1;
835 unsigned char SEG11COM0:1;
836 unsigned char SEG12COM0:1;
837 unsigned char SEG13COM0:1;
838 unsigned char SEG14COM0:1;
839 unsigned char SEG15COM0:1;
842 unsigned char S8C0:1;
843 unsigned char S9C0:1;
844 unsigned char S10C0:1;
845 unsigned char S11C0:1;
846 unsigned char S12C0:1;
847 unsigned char S13C0:1;
848 unsigned char S14C0:1;
849 unsigned char S15C0:1;
852 extern volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits;
854 #define SEG8COM0 LCDDATA1_bits.SEG8COM0
855 #define S8C0 LCDDATA1_bits.S8C0
856 #define SEG9COM0 LCDDATA1_bits.SEG9COM0
857 #define S9C0 LCDDATA1_bits.S9C0
858 #define SEG10COM0 LCDDATA1_bits.SEG10COM0
859 #define S10C0 LCDDATA1_bits.S10C0
860 #define SEG11COM0 LCDDATA1_bits.SEG11COM0
861 #define S11C0 LCDDATA1_bits.S11C0
862 #define SEG12COM0 LCDDATA1_bits.SEG12COM0
863 #define S12C0 LCDDATA1_bits.S12C0
864 #define SEG13COM0 LCDDATA1_bits.SEG13COM0
865 #define S13C0 LCDDATA1_bits.S13C0
866 #define SEG14COM0 LCDDATA1_bits.SEG14COM0
867 #define S14C0 LCDDATA1_bits.S14C0
868 #define SEG15COM0 LCDDATA1_bits.SEG15COM0
869 #define S15C0 LCDDATA1_bits.S15C0
871 // ----- LCDDATA10 bits --------------------
874 unsigned char SEG8COM3:1;
875 unsigned char SEG9COM3:1;
876 unsigned char SEG10COM3:1;
877 unsigned char SEG11COM3:1;
878 unsigned char SEG12COM3:1;
879 unsigned char SEG13COM3:1;
880 unsigned char SEG14COM3:1;
881 unsigned char SEG15COM3:1;
884 unsigned char S8C3:1;
885 unsigned char S9C3:1;
886 unsigned char S10C3:1;
887 unsigned char S11C3:1;
888 unsigned char S12C3:1;
889 unsigned char S13C3:1;
890 unsigned char S14C3:1;
891 unsigned char S15C3:1;
893 } __LCDDATA10_bits_t;
894 extern volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits;
896 #define SEG8COM3 LCDDATA10_bits.SEG8COM3
897 #define S8C3 LCDDATA10_bits.S8C3
898 #define SEG9COM3 LCDDATA10_bits.SEG9COM3
899 #define S9C3 LCDDATA10_bits.S9C3
900 #define SEG10COM3 LCDDATA10_bits.SEG10COM3
901 #define S10C3 LCDDATA10_bits.S10C3
902 #define SEG11COM3 LCDDATA10_bits.SEG11COM3
903 #define S11C3 LCDDATA10_bits.S11C3
904 #define SEG12COM3 LCDDATA10_bits.SEG12COM3
905 #define S12C3 LCDDATA10_bits.S12C3
906 #define SEG13COM3 LCDDATA10_bits.SEG13COM3
907 #define S13C3 LCDDATA10_bits.S13C3
908 #define SEG14COM3 LCDDATA10_bits.SEG14COM3
909 #define S14C3 LCDDATA10_bits.S14C3
910 #define SEG15COM3 LCDDATA10_bits.SEG15COM3
911 #define S15C3 LCDDATA10_bits.S15C3
913 // ----- LCDDATA3 bits --------------------
916 unsigned char SEG0COM1:1;
917 unsigned char SEG1COM1:1;
918 unsigned char SEG2COM1:1;
919 unsigned char SEG3COM1:1;
920 unsigned char SEG4COM1:1;
921 unsigned char SEG5COM1:1;
922 unsigned char SEG6COM1:1;
923 unsigned char SEG7COM1:1;
926 unsigned char S0C1:1;
927 unsigned char S1C1:1;
928 unsigned char S2C1:1;
929 unsigned char S3C1:1;
930 unsigned char S4C1:1;
931 unsigned char S5C1:1;
932 unsigned char S6C1:1;
933 unsigned char S7C1:1;
936 extern volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits;
938 #define SEG0COM1 LCDDATA3_bits.SEG0COM1
939 #define S0C1 LCDDATA3_bits.S0C1
940 #define SEG1COM1 LCDDATA3_bits.SEG1COM1
941 #define S1C1 LCDDATA3_bits.S1C1
942 #define SEG2COM1 LCDDATA3_bits.SEG2COM1
943 #define S2C1 LCDDATA3_bits.S2C1
944 #define SEG3COM1 LCDDATA3_bits.SEG3COM1
945 #define S3C1 LCDDATA3_bits.S3C1
946 #define SEG4COM1 LCDDATA3_bits.SEG4COM1
947 #define S4C1 LCDDATA3_bits.S4C1
948 #define SEG5COM1 LCDDATA3_bits.SEG5COM1
949 #define S5C1 LCDDATA3_bits.S5C1
950 #define SEG6COM1 LCDDATA3_bits.SEG6COM1
951 #define S6C1 LCDDATA3_bits.S6C1
952 #define SEG7COM1 LCDDATA3_bits.SEG7COM1
953 #define S7C1 LCDDATA3_bits.S7C1
955 // ----- LCDDATA4 bits --------------------
958 unsigned char SEG8COM1:1;
959 unsigned char SEG9COM1:1;
960 unsigned char SEG10COM1:1;
961 unsigned char SEG11COM1:1;
962 unsigned char SEG12COM1:1;
963 unsigned char SEG13COM1:1;
964 unsigned char SEG14COM1:1;
965 unsigned char SEG15COM1:1;
968 unsigned char S8C1:1;
969 unsigned char S9C1:1;
970 unsigned char S10C1:1;
971 unsigned char S11C1:1;
972 unsigned char S12C1:1;
973 unsigned char S13C1:1;
974 unsigned char S14C1:1;
975 unsigned char S15C1:1;
978 extern volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits;
980 #define SEG8COM1 LCDDATA4_bits.SEG8COM1
981 #define S8C1 LCDDATA4_bits.S8C1
982 #define SEG9COM1 LCDDATA4_bits.SEG9COM1
983 #define S9C1 LCDDATA4_bits.S9C1
984 #define SEG10COM1 LCDDATA4_bits.SEG10COM1
985 #define S10C1 LCDDATA4_bits.S10C1
986 #define SEG11COM1 LCDDATA4_bits.SEG11COM1
987 #define S11C1 LCDDATA4_bits.S11C1
988 #define SEG12COM1 LCDDATA4_bits.SEG12COM1
989 #define S12C1 LCDDATA4_bits.S12C1
990 #define SEG13COM1 LCDDATA4_bits.SEG13COM1
991 #define S13C1 LCDDATA4_bits.S13C1
992 #define SEG14COM1 LCDDATA4_bits.SEG14COM1
993 #define S14C1 LCDDATA4_bits.S14C1
994 #define SEG15COM1 LCDDATA4_bits.SEG15COM1
995 #define S15C1 LCDDATA4_bits.S15C1
997 // ----- LCDDATA6 bits --------------------
1000 unsigned char SEG0COM2:1;
1001 unsigned char SEG1COM2:1;
1002 unsigned char SEG2COM2:1;
1003 unsigned char SEG3COM2:1;
1004 unsigned char SEG4COM2:1;
1005 unsigned char SEG5COM2:1;
1006 unsigned char SEG6COM2:1;
1007 unsigned char SEG7COM2:1;
1010 unsigned char S0C2:1;
1011 unsigned char S1C2:1;
1012 unsigned char S2C2:1;
1013 unsigned char S3C2:1;
1014 unsigned char S4C2:1;
1015 unsigned char S5C2:1;
1016 unsigned char S6C2:1;
1017 unsigned char S7C2:1;
1019 } __LCDDATA6_bits_t;
1020 extern volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits;
1022 #define SEG0COM2 LCDDATA6_bits.SEG0COM2
1023 #define S0C2 LCDDATA6_bits.S0C2
1024 #define SEG1COM2 LCDDATA6_bits.SEG1COM2
1025 #define S1C2 LCDDATA6_bits.S1C2
1026 #define SEG2COM2 LCDDATA6_bits.SEG2COM2
1027 #define S2C2 LCDDATA6_bits.S2C2
1028 #define SEG3COM2 LCDDATA6_bits.SEG3COM2
1029 #define S3C2 LCDDATA6_bits.S3C2
1030 #define SEG4COM2 LCDDATA6_bits.SEG4COM2
1031 #define S4C2 LCDDATA6_bits.S4C2
1032 #define SEG5COM2 LCDDATA6_bits.SEG5COM2
1033 #define S5C2 LCDDATA6_bits.S5C2
1034 #define SEG6COM2 LCDDATA6_bits.SEG6COM2
1035 #define S6C2 LCDDATA6_bits.S6C2
1036 #define SEG7COM2 LCDDATA6_bits.SEG7COM2
1037 #define S7C2 LCDDATA6_bits.S7C2
1039 // ----- LCDDATA7 bits --------------------
1042 unsigned char SEG8COM2:1;
1043 unsigned char SEG9COM2:1;
1044 unsigned char SEG10COM2:1;
1045 unsigned char SEG11COM2:1;
1046 unsigned char SEG12COM2:1;
1047 unsigned char SEG13COM2:1;
1048 unsigned char SEG14COM2:1;
1049 unsigned char SEG15COM2:1;
1052 unsigned char S8C2:1;
1053 unsigned char S9C2:1;
1054 unsigned char S10C2:1;
1055 unsigned char S11C2:1;
1056 unsigned char S12C2:1;
1057 unsigned char S13C2:1;
1058 unsigned char S14C2:1;
1059 unsigned char S15C2:1;
1061 } __LCDDATA7_bits_t;
1062 extern volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits;
1064 #define SEG8COM2 LCDDATA7_bits.SEG8COM2
1065 #define S8C2 LCDDATA7_bits.S8C2
1066 #define SEG9COM2 LCDDATA7_bits.SEG9COM2
1067 #define S9C2 LCDDATA7_bits.S9C2
1068 #define SEG10COM2 LCDDATA7_bits.SEG10COM2
1069 #define S10C2 LCDDATA7_bits.S10C2
1070 #define SEG11COM2 LCDDATA7_bits.SEG11COM2
1071 #define S11C2 LCDDATA7_bits.S11C2
1072 #define SEG12COM2 LCDDATA7_bits.SEG12COM2
1073 #define S12C2 LCDDATA7_bits.S12C2
1074 #define SEG13COM2 LCDDATA7_bits.SEG13COM2
1075 #define S13C2 LCDDATA7_bits.S13C2
1076 #define SEG14COM2 LCDDATA7_bits.SEG14COM2
1077 #define S14C2 LCDDATA7_bits.S14C2
1078 #define SEG15COM2 LCDDATA7_bits.SEG15COM2
1079 #define S15C2 LCDDATA7_bits.S15C2
1081 // ----- LCDDATA9 bits --------------------
1084 unsigned char SEG0COM3:1;
1085 unsigned char SEG1COM3:1;
1086 unsigned char SEG2COM3:1;
1087 unsigned char SEG3COM3:1;
1088 unsigned char SEG4COM3:1;
1089 unsigned char SEG5COM3:1;
1090 unsigned char SEG6COM3:1;
1091 unsigned char SEG7COM3:1;
1094 unsigned char S0C3:1;
1095 unsigned char S1C3:1;
1096 unsigned char S2C3:1;
1097 unsigned char S3C3:1;
1098 unsigned char S4C3:1;
1099 unsigned char S5C3:1;
1100 unsigned char S6C3:1;
1101 unsigned char S7C3:1;
1103 } __LCDDATA9_bits_t;
1104 extern volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits;
1106 #define SEG0COM3 LCDDATA9_bits.SEG0COM3
1107 #define S0C3 LCDDATA9_bits.S0C3
1108 #define SEG1COM3 LCDDATA9_bits.SEG1COM3
1109 #define S1C3 LCDDATA9_bits.S1C3
1110 #define SEG2COM3 LCDDATA9_bits.SEG2COM3
1111 #define S2C3 LCDDATA9_bits.S2C3
1112 #define SEG3COM3 LCDDATA9_bits.SEG3COM3
1113 #define S3C3 LCDDATA9_bits.S3C3
1114 #define SEG4COM3 LCDDATA9_bits.SEG4COM3
1115 #define S4C3 LCDDATA9_bits.S4C3
1116 #define SEG5COM3 LCDDATA9_bits.SEG5COM3
1117 #define S5C3 LCDDATA9_bits.S5C3
1118 #define SEG6COM3 LCDDATA9_bits.SEG6COM3
1119 #define S6C3 LCDDATA9_bits.S6C3
1120 #define SEG7COM3 LCDDATA9_bits.SEG7COM3
1121 #define S7C3 LCDDATA9_bits.S7C3
1123 // ----- LCDPS bits --------------------
1126 unsigned char LP0:1;
1127 unsigned char LP1:1;
1128 unsigned char LP2:1;
1129 unsigned char LP3:1;
1131 unsigned char LCDA:1;
1132 unsigned char BIASMD:1;
1133 unsigned char WFT:1;
1136 extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits;
1138 #define LP0 LCDPS_bits.LP0
1139 #define LP1 LCDPS_bits.LP1
1140 #define LP2 LCDPS_bits.LP2
1141 #define LP3 LCDPS_bits.LP3
1142 #define WA LCDPS_bits.WA
1143 #define LCDA LCDPS_bits.LCDA
1144 #define BIASMD LCDPS_bits.BIASMD
1145 #define WFT LCDPS_bits.WFT
1147 // ----- LCDSE0 bits --------------------
1150 unsigned char SE0:1;
1151 unsigned char SE1:1;
1152 unsigned char SE2:1;
1153 unsigned char SE3:1;
1154 unsigned char SE4:1;
1155 unsigned char SE5:1;
1156 unsigned char SE6:1;
1157 unsigned char SE7:1;
1160 unsigned char SEGEN0:1;
1161 unsigned char SEGEN1:1;
1162 unsigned char SEGEN2:1;
1163 unsigned char SEGEN3:1;
1164 unsigned char SEGEN4:1;
1165 unsigned char SEGEN5:1;
1166 unsigned char SEGEN6:1;
1167 unsigned char SEGEN7:1;
1170 extern volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits;
1172 #define SE0 LCDSE0_bits.SE0
1173 #define SEGEN0 LCDSE0_bits.SEGEN0
1174 #define SE1 LCDSE0_bits.SE1
1175 #define SEGEN1 LCDSE0_bits.SEGEN1
1176 #define SE2 LCDSE0_bits.SE2
1177 #define SEGEN2 LCDSE0_bits.SEGEN2
1178 #define SE3 LCDSE0_bits.SE3
1179 #define SEGEN3 LCDSE0_bits.SEGEN3
1180 #define SE4 LCDSE0_bits.SE4
1181 #define SEGEN4 LCDSE0_bits.SEGEN4
1182 #define SE5 LCDSE0_bits.SE5
1183 #define SEGEN5 LCDSE0_bits.SEGEN5
1184 #define SE6 LCDSE0_bits.SE6
1185 #define SEGEN6 LCDSE0_bits.SEGEN6
1186 #define SE7 LCDSE0_bits.SE7
1187 #define SEGEN7 LCDSE0_bits.SEGEN7
1189 // ----- LCDSE1 bits --------------------
1192 unsigned char SE8:1;
1193 unsigned char SE9:1;
1194 unsigned char SE10:1;
1195 unsigned char SE11:1;
1196 unsigned char SE12:1;
1197 unsigned char SE13:1;
1198 unsigned char SE14:1;
1199 unsigned char SE15:1;
1202 unsigned char SEGEN8:1;
1203 unsigned char SEGEN9:1;
1204 unsigned char SEGEN10:1;
1205 unsigned char SEGEN11:1;
1206 unsigned char SEGEN12:1;
1207 unsigned char SEGEN13:1;
1208 unsigned char SEGEN14:1;
1209 unsigned char SEGEN15:1;
1212 extern volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits;
1214 #define SE8 LCDSE1_bits.SE8
1215 #define SEGEN8 LCDSE1_bits.SEGEN8
1216 #define SE9 LCDSE1_bits.SE9
1217 #define SEGEN9 LCDSE1_bits.SEGEN9
1218 #define SE10 LCDSE1_bits.SE10
1219 #define SEGEN10 LCDSE1_bits.SEGEN10
1220 #define SE11 LCDSE1_bits.SE11
1221 #define SEGEN11 LCDSE1_bits.SEGEN11
1222 #define SE12 LCDSE1_bits.SE12
1223 #define SEGEN12 LCDSE1_bits.SEGEN12
1224 #define SE13 LCDSE1_bits.SE13
1225 #define SEGEN13 LCDSE1_bits.SEGEN13
1226 #define SE14 LCDSE1_bits.SE14
1227 #define SEGEN14 LCDSE1_bits.SEGEN14
1228 #define SE15 LCDSE1_bits.SE15
1229 #define SEGEN15 LCDSE1_bits.SEGEN15
1231 // ----- LVDCON bits --------------------
1234 unsigned char LVDL0:1;
1235 unsigned char LVDL1:1;
1236 unsigned char LVDL2:1;
1238 unsigned char LVDEN:1;
1239 unsigned char IRVST:1;
1244 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
1246 #define LVDL0 LVDCON_bits.LVDL0
1247 #define LVDL1 LVDCON_bits.LVDL1
1248 #define LVDL2 LVDCON_bits.LVDL2
1249 #define LVDEN LVDCON_bits.LVDEN
1250 #define IRVST LVDCON_bits.IRVST
1252 // ----- OPTION_REG bits --------------------
1255 unsigned char PS0:1;
1256 unsigned char PS1:1;
1257 unsigned char PS2:1;
1258 unsigned char PSA:1;
1259 unsigned char T0SE:1;
1260 unsigned char T0CS:1;
1261 unsigned char INTEDG:1;
1262 unsigned char NOT_RBPU:1;
1264 } __OPTION_REG_bits_t;
1265 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
1267 #define PS0 OPTION_REG_bits.PS0
1268 #define PS1 OPTION_REG_bits.PS1
1269 #define PS2 OPTION_REG_bits.PS2
1270 #define PSA OPTION_REG_bits.PSA
1271 #define T0SE OPTION_REG_bits.T0SE
1272 #define T0CS OPTION_REG_bits.T0CS
1273 #define INTEDG OPTION_REG_bits.INTEDG
1274 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
1276 // ----- OSCCON bits --------------------
1279 unsigned char SCS:1;
1280 unsigned char LTS:1;
1281 unsigned char HTS:1;
1282 unsigned char OSTS:1;
1283 unsigned char IRCF0:1;
1284 unsigned char IRCF1:1;
1285 unsigned char IRCF2:1;
1289 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
1291 #define SCS OSCCON_bits.SCS
1292 #define LTS OSCCON_bits.LTS
1293 #define HTS OSCCON_bits.HTS
1294 #define OSTS OSCCON_bits.OSTS
1295 #define IRCF0 OSCCON_bits.IRCF0
1296 #define IRCF1 OSCCON_bits.IRCF1
1297 #define IRCF2 OSCCON_bits.IRCF2
1299 // ----- OSCTUNE bits --------------------
1302 unsigned char TUN0:1;
1303 unsigned char TUN1:1;
1304 unsigned char TUN2:1;
1305 unsigned char TUN3:1;
1306 unsigned char TUN4:1;
1312 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
1314 #define TUN0 OSCTUNE_bits.TUN0
1315 #define TUN1 OSCTUNE_bits.TUN1
1316 #define TUN2 OSCTUNE_bits.TUN2
1317 #define TUN3 OSCTUNE_bits.TUN3
1318 #define TUN4 OSCTUNE_bits.TUN4
1320 // ----- PCON bits --------------------
1323 unsigned char NOT_BO:1;
1324 unsigned char NOT_POR:1;
1327 unsigned char SBOREN:1;
1333 unsigned char NOT_BOR:1;
1343 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
1345 #define NOT_BO PCON_bits.NOT_BO
1346 #define NOT_BOR PCON_bits.NOT_BOR
1347 #define NOT_POR PCON_bits.NOT_POR
1348 #define SBOREN PCON_bits.SBOREN
1350 // ----- PIE1 bits --------------------
1353 unsigned char TMR1IE:1;
1354 unsigned char TMR2IE:1;
1355 unsigned char CCP1IE:1;
1356 unsigned char SSPIE:1;
1357 unsigned char TXIE:1;
1358 unsigned char RCIE:1;
1359 unsigned char ADIE:1;
1360 unsigned char EEIE:1;
1363 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
1365 #define TMR1IE PIE1_bits.TMR1IE
1366 #define TMR2IE PIE1_bits.TMR2IE
1367 #define CCP1IE PIE1_bits.CCP1IE
1368 #define SSPIE PIE1_bits.SSPIE
1369 #define TXIE PIE1_bits.TXIE
1370 #define RCIE PIE1_bits.RCIE
1371 #define ADIE PIE1_bits.ADIE
1372 #define EEIE PIE1_bits.EEIE
1374 // ----- PIE2 bits --------------------
1379 unsigned char LVDIE:1;
1381 unsigned char LCDIE:1;
1382 unsigned char C1IE:1;
1383 unsigned char C2IE:1;
1384 unsigned char OSFIE:1;
1387 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
1389 #define LVDIE PIE2_bits.LVDIE
1390 #define LCDIE PIE2_bits.LCDIE
1391 #define C1IE PIE2_bits.C1IE
1392 #define C2IE PIE2_bits.C2IE
1393 #define OSFIE PIE2_bits.OSFIE
1395 // ----- PIR1 bits --------------------
1398 unsigned char TMR1IF:1;
1399 unsigned char TMR2IF:1;
1400 unsigned char CCP1IF:1;
1401 unsigned char SSPIF:1;
1402 unsigned char TXIF:1;
1403 unsigned char RCIF:1;
1404 unsigned char ADIF:1;
1405 unsigned char EEIF:1;
1408 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
1410 #define TMR1IF PIR1_bits.TMR1IF
1411 #define TMR2IF PIR1_bits.TMR2IF
1412 #define CCP1IF PIR1_bits.CCP1IF
1413 #define SSPIF PIR1_bits.SSPIF
1414 #define TXIF PIR1_bits.TXIF
1415 #define RCIF PIR1_bits.RCIF
1416 #define ADIF PIR1_bits.ADIF
1417 #define EEIF PIR1_bits.EEIF
1419 // ----- PIR2 bits --------------------
1424 unsigned char LVDIF:1;
1426 unsigned char LCDIF:1;
1427 unsigned char C1IF:1;
1428 unsigned char C2IF:1;
1429 unsigned char OSFIF:1;
1432 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
1434 #define LVDIF PIR2_bits.LVDIF
1435 #define LCDIF PIR2_bits.LCDIF
1436 #define C1IF PIR2_bits.C1IF
1437 #define C2IF PIR2_bits.C2IF
1438 #define OSFIF PIR2_bits.OSFIF
1440 // ----- RCSTA bits --------------------
1443 unsigned char RX9D:1;
1444 unsigned char OERR:1;
1445 unsigned char FERR:1;
1446 unsigned char ADDEN:1;
1447 unsigned char CREN:1;
1448 unsigned char SREN:1;
1449 unsigned char RX9:1;
1450 unsigned char SPEN:1;
1453 unsigned char RCD8:1;
1459 unsigned char RC9:1;
1469 unsigned char NOT_RC8:1;
1479 unsigned char RC8_9:1;
1483 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
1485 #define RX9D RCSTA_bits.RX9D
1486 #define RCD8 RCSTA_bits.RCD8
1487 #define OERR RCSTA_bits.OERR
1488 #define FERR RCSTA_bits.FERR
1489 #define ADDEN RCSTA_bits.ADDEN
1490 #define CREN RCSTA_bits.CREN
1491 #define SREN RCSTA_bits.SREN
1492 #define RX9 RCSTA_bits.RX9
1493 #define RC9 RCSTA_bits.RC9
1494 #define NOT_RC8 RCSTA_bits.NOT_RC8
1495 #define RC8_9 RCSTA_bits.RC8_9
1496 #define SPEN RCSTA_bits.SPEN
1498 // ----- SSPCON bits --------------------
1501 unsigned char SSPM0:1;
1502 unsigned char SSPM1:1;
1503 unsigned char SSPM2:1;
1504 unsigned char SSPM3:1;
1505 unsigned char CKP:1;
1506 unsigned char SSPEN:1;
1507 unsigned char SSPOV:1;
1508 unsigned char WCOL:1;
1511 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1513 #define SSPM0 SSPCON_bits.SSPM0
1514 #define SSPM1 SSPCON_bits.SSPM1
1515 #define SSPM2 SSPCON_bits.SSPM2
1516 #define SSPM3 SSPCON_bits.SSPM3
1517 #define CKP SSPCON_bits.CKP
1518 #define SSPEN SSPCON_bits.SSPEN
1519 #define SSPOV SSPCON_bits.SSPOV
1520 #define WCOL SSPCON_bits.WCOL
1522 // ----- SSPSTAT bits --------------------
1531 unsigned char CKE:1;
1532 unsigned char SMP:1;
1537 unsigned char I2C_READ:1;
1538 unsigned char I2C_START:1;
1539 unsigned char I2C_STOP:1;
1540 unsigned char I2C_DATA:1;
1547 unsigned char NOT_W:1;
1550 unsigned char NOT_A:1;
1557 unsigned char NOT_WRITE:1;
1560 unsigned char NOT_ADDRESS:1;
1567 unsigned char R_W:1;
1570 unsigned char D_A:1;
1577 unsigned char READ_WRITE:1;
1580 unsigned char DATA_ADDRESS:1;
1585 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1587 #define BF SSPSTAT_bits.BF
1588 #define UA SSPSTAT_bits.UA
1589 #define R SSPSTAT_bits.R
1590 #define I2C_READ SSPSTAT_bits.I2C_READ
1591 #define NOT_W SSPSTAT_bits.NOT_W
1592 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1593 #define R_W SSPSTAT_bits.R_W
1594 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1595 #define S SSPSTAT_bits.S
1596 #define I2C_START SSPSTAT_bits.I2C_START
1597 #define P SSPSTAT_bits.P
1598 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1599 #define D SSPSTAT_bits.D
1600 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1601 #define NOT_A SSPSTAT_bits.NOT_A
1602 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1603 #define D_A SSPSTAT_bits.D_A
1604 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1605 #define CKE SSPSTAT_bits.CKE
1606 #define SMP SSPSTAT_bits.SMP
1608 // ----- STATUS bits --------------------
1614 unsigned char NOT_PD:1;
1615 unsigned char NOT_TO:1;
1616 unsigned char RP0:1;
1617 unsigned char RP1:1;
1618 unsigned char IRP:1;
1621 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1623 #define C STATUS_bits.C
1624 #define DC STATUS_bits.DC
1625 #define Z STATUS_bits.Z
1626 #define NOT_PD STATUS_bits.NOT_PD
1627 #define NOT_TO STATUS_bits.NOT_TO
1628 #define RP0 STATUS_bits.RP0
1629 #define RP1 STATUS_bits.RP1
1630 #define IRP STATUS_bits.IRP
1632 // ----- T1CON bits --------------------
1635 unsigned char TMR1ON:1;
1636 unsigned char TMR1CS:1;
1637 unsigned char NOT_T1SYNC:1;
1638 unsigned char T1OSCEN:1;
1639 unsigned char T1CKPS0:1;
1640 unsigned char T1CKPS1:1;
1641 unsigned char T1GE:1;
1642 unsigned char T1GINV:1;
1647 unsigned char T1INSYNC:1;
1657 unsigned char T1SYNC:1;
1665 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1667 #define TMR1ON T1CON_bits.TMR1ON
1668 #define TMR1CS T1CON_bits.TMR1CS
1669 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1670 #define T1INSYNC T1CON_bits.T1INSYNC
1671 #define T1SYNC T1CON_bits.T1SYNC
1672 #define T1OSCEN T1CON_bits.T1OSCEN
1673 #define T1CKPS0 T1CON_bits.T1CKPS0
1674 #define T1CKPS1 T1CON_bits.T1CKPS1
1675 #define T1GE T1CON_bits.T1GE
1676 #define T1GINV T1CON_bits.T1GINV
1678 // ----- T2CON bits --------------------
1681 unsigned char T2CKPS0:1;
1682 unsigned char T2CKPS1:1;
1683 unsigned char TMR2ON:1;
1684 unsigned char TOUTPS0:1;
1685 unsigned char TOUTPS1:1;
1686 unsigned char TOUTPS2:1;
1687 unsigned char TOUTPS3:1;
1691 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1693 #define T2CKPS0 T2CON_bits.T2CKPS0
1694 #define T2CKPS1 T2CON_bits.T2CKPS1
1695 #define TMR2ON T2CON_bits.TMR2ON
1696 #define TOUTPS0 T2CON_bits.TOUTPS0
1697 #define TOUTPS1 T2CON_bits.TOUTPS1
1698 #define TOUTPS2 T2CON_bits.TOUTPS2
1699 #define TOUTPS3 T2CON_bits.TOUTPS3
1701 // ----- TXSTA bits --------------------
1704 unsigned char TX9D:1;
1705 unsigned char TRMT:1;
1706 unsigned char BRGH:1;
1708 unsigned char SYNC:1;
1709 unsigned char TXEN:1;
1710 unsigned char TX9:1;
1711 unsigned char CSRC:1;
1714 unsigned char TXD8:1;
1720 unsigned char NOT_TX8:1;
1730 unsigned char TX8_9:1;
1734 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1736 #define TX9D TXSTA_bits.TX9D
1737 #define TXD8 TXSTA_bits.TXD8
1738 #define TRMT TXSTA_bits.TRMT
1739 #define BRGH TXSTA_bits.BRGH
1740 #define SYNC TXSTA_bits.SYNC
1741 #define TXEN TXSTA_bits.TXEN
1742 #define TX9 TXSTA_bits.TX9
1743 #define NOT_TX8 TXSTA_bits.NOT_TX8
1744 #define TX8_9 TXSTA_bits.TX8_9
1745 #define CSRC TXSTA_bits.CSRC
1747 // ----- VRCON bits --------------------
1750 unsigned char VR0:1;
1751 unsigned char VR1:1;
1752 unsigned char VR2:1;
1753 unsigned char VR3:1;
1755 unsigned char VRR:1;
1757 unsigned char VREN:1;
1760 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1762 #define VR0 VRCON_bits.VR0
1763 #define VR1 VRCON_bits.VR1
1764 #define VR2 VRCON_bits.VR2
1765 #define VR3 VRCON_bits.VR3
1766 #define VRR VRCON_bits.VRR
1767 #define VREN VRCON_bits.VREN
1769 // ----- WDTCON bits --------------------
1772 unsigned char SWDTEN:1;
1773 unsigned char WDTPS0:1;
1774 unsigned char WDTPS1:1;
1775 unsigned char WDTPS2:1;
1776 unsigned char WDTPS3:1;
1782 unsigned char SWDTE:1;
1792 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1794 #define SWDTEN WDTCON_bits.SWDTEN
1795 #define SWDTE WDTCON_bits.SWDTE
1796 #define WDTPS0 WDTCON_bits.WDTPS0
1797 #define WDTPS1 WDTCON_bits.WDTPS1
1798 #define WDTPS2 WDTCON_bits.WDTPS2
1799 #define WDTPS3 WDTCON_bits.WDTPS3
1801 // ----- WPU bits --------------------
1804 unsigned char WPU0:1;
1805 unsigned char WPU1:1;
1806 unsigned char WPU2:1;
1807 unsigned char WPU3:1;
1808 unsigned char WPU4:1;
1809 unsigned char WPU5:1;
1810 unsigned char WPU6:1;
1811 unsigned char WPU7:1;
1814 extern volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits;
1816 #define WPU0 WPU_bits.WPU0
1817 #define WPU1 WPU_bits.WPU1
1818 #define WPU2 WPU_bits.WPU2
1819 #define WPU3 WPU_bits.WPU3
1820 #define WPU4 WPU_bits.WPU4
1821 #define WPU5 WPU_bits.WPU5
1822 #define WPU6 WPU_bits.WPU6
1823 #define WPU7 WPU_bits.WPU7
1825 // ----- WPUB bits --------------------
1828 unsigned char WPUB0:1;
1829 unsigned char WPUB1:1;
1830 unsigned char WPUB2:1;
1831 unsigned char WPUB3:1;
1832 unsigned char WPUB4:1;
1833 unsigned char WPUB5:1;
1834 unsigned char WPUB6:1;
1835 unsigned char WPUB7:1;
1838 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1840 #define WPUB0 WPUB_bits.WPUB0
1841 #define WPUB1 WPUB_bits.WPUB1
1842 #define WPUB2 WPUB_bits.WPUB2
1843 #define WPUB3 WPUB_bits.WPUB3
1844 #define WPUB4 WPUB_bits.WPUB4
1845 #define WPUB5 WPUB_bits.WPUB5
1846 #define WPUB6 WPUB_bits.WPUB6
1847 #define WPUB7 WPUB_bits.WPUB7