2 // Register Declarations for Microchip 16F914 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define OSCCON_ADDR 0x008F
70 #define OSCTUNE_ADDR 0x0090
71 #define ANSEL_ADDR 0x0091
72 #define PR2_ADDR 0x0092
73 #define SSPADD_ADDR 0x0093
74 #define SSPSTAT_ADDR 0x0094
75 #define WPUB_ADDR 0x0095
76 #define WPU_ADDR 0x0095
77 #define IOCB_ADDR 0x0096
78 #define IOC_ADDR 0x0096
79 #define CMCON1_ADDR 0x0097
80 #define TXSTA_ADDR 0x0098
81 #define SPBRG_ADDR 0x0099
82 #define CMCON0_ADDR 0x009C
83 #define VRCON_ADDR 0x009D
84 #define ADRESL_ADDR 0x009E
85 #define ADCON1_ADDR 0x009F
86 #define WDTCON_ADDR 0x0105
87 #define LCDCON_ADDR 0x0107
88 #define LCDPS_ADDR 0x0108
89 #define LVDCON_ADDR 0x0109
90 #define EEDATL_ADDR 0x010C
91 #define EEADRL_ADDR 0x010D
92 #define EEDATH_ADDR 0x010E
93 #define EEADRH_ADDR 0x010F
94 #define LCDDATA0_ADDR 0x0110
95 #define LCDDATA1_ADDR 0x0111
96 #define LCDDATA2_ADDR 0x0112
97 #define LCDDATA3_ADDR 0x0113
98 #define LCDDATA4_ADDR 0x0114
99 #define LCDDATA5_ADDR 0x0115
100 #define LCDDATA6_ADDR 0x0116
101 #define LCDDATA7_ADDR 0x0117
102 #define LCDDATA8_ADDR 0x0118
103 #define LCDDATA9_ADDR 0x0119
104 #define LCDDATA10_ADDR 0x011A
105 #define LCDDATA11_ADDR 0x011B
106 #define LCDSE0_ADDR 0x011C
107 #define LCDSE1_ADDR 0x011D
108 #define LCDSE2_ADDR 0x011E
109 #define EECON1_ADDR 0x018C
110 #define EECON2_ADDR 0x018D
113 // Memory organization.
116 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
117 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
118 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
119 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
120 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
121 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
122 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
123 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
124 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
125 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
126 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
127 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
128 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
129 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
130 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
131 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
132 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
133 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
134 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
135 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
136 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
137 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
138 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
139 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
140 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
141 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
142 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
143 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
144 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
145 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
146 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
147 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
148 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
149 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
150 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
151 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
152 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
153 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
154 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
155 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
156 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
157 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
158 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
159 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
160 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
161 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
162 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
163 #pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB
164 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
165 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
166 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
167 #pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
168 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
169 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
170 #pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
171 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
172 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
173 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
174 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
175 #pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON
176 #pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS
177 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
178 #pragma memmap EEDATL_ADDR EEDATL_ADDR SFR 0x000 // EEDATL
179 #pragma memmap EEADRL_ADDR EEADRL_ADDR SFR 0x000 // EEADRL
180 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
181 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
182 #pragma memmap LCDDATA0_ADDR LCDDATA0_ADDR SFR 0x000 // LCDDATA0
183 #pragma memmap LCDDATA1_ADDR LCDDATA1_ADDR SFR 0x000 // LCDDATA1
184 #pragma memmap LCDDATA2_ADDR LCDDATA2_ADDR SFR 0x000 // LCDDATA2
185 #pragma memmap LCDDATA3_ADDR LCDDATA3_ADDR SFR 0x000 // LCDDATA3
186 #pragma memmap LCDDATA4_ADDR LCDDATA4_ADDR SFR 0x000 // LCDDATA4
187 #pragma memmap LCDDATA5_ADDR LCDDATA5_ADDR SFR 0x000 // LCDDATA5
188 #pragma memmap LCDDATA6_ADDR LCDDATA6_ADDR SFR 0x000 // LCDDATA6
189 #pragma memmap LCDDATA7_ADDR LCDDATA7_ADDR SFR 0x000 // LCDDATA7
190 #pragma memmap LCDDATA8_ADDR LCDDATA8_ADDR SFR 0x000 // LCDDATA8
191 #pragma memmap LCDDATA9_ADDR LCDDATA9_ADDR SFR 0x000 // LCDDATA9
192 #pragma memmap LCDDATA10_ADDR LCDDATA10_ADDR SFR 0x000 // LCDDATA10
193 #pragma memmap LCDDATA11_ADDR LCDDATA11_ADDR SFR 0x000 // LCDDATA11
194 #pragma memmap LCDSE0_ADDR LCDSE0_ADDR SFR 0x000 // LCDSE0
195 #pragma memmap LCDSE1_ADDR LCDSE1_ADDR SFR 0x000 // LCDSE1
196 #pragma memmap LCDSE2_ADDR LCDSE2_ADDR SFR 0x000 // LCDSE2
197 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
198 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
202 // P16F914.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
205 // This header file defines configurations, registers, and other useful bits of
206 // information for the PIC16F914 microcontroller.
207 // These names are taken to match the data sheets as closely as possible.
209 // Note that the processor must be selected before this file is
210 // included. The processor may be selected the following ways:
212 // 1. Command line switch:
213 // C:\ MPASM MYFILE.ASM /PIC16F914
214 // 2. LIST directive in the source file
216 // 3. Processor Type entry in the MPASM full-screen interface
218 //==========================================================================
222 //==========================================================================
225 //1.00 06/11/04 Initial Release
226 //1.01 08/16/04 Added EECON2
229 //==========================================================================
233 //==========================================================================
236 // MESSG "Processor-header file mismatch. Verify selected processor."
239 //==========================================================================
241 // Register Definitions
243 //==========================================================================
248 //----- Register Files------------------------------------------------------
250 extern __data __at (INDF_ADDR) volatile char INDF;
251 extern __sfr __at (TMR0_ADDR) TMR0;
252 extern __data __at (PCL_ADDR) volatile char PCL;
253 extern __sfr __at (STATUS_ADDR) STATUS;
254 extern __sfr __at (FSR_ADDR) FSR;
255 extern __sfr __at (PORTA_ADDR) PORTA;
256 extern __sfr __at (PORTB_ADDR) PORTB;
257 extern __sfr __at (PORTC_ADDR) PORTC;
258 extern __sfr __at (PORTD_ADDR) PORTD;
259 extern __sfr __at (PORTE_ADDR) PORTE;
260 extern __sfr __at (PCLATH_ADDR) PCLATH;
261 extern __sfr __at (INTCON_ADDR) INTCON;
262 extern __sfr __at (PIR1_ADDR) PIR1;
263 extern __sfr __at (PIR2_ADDR) PIR2;
264 extern __sfr __at (TMR1L_ADDR) TMR1L;
265 extern __sfr __at (TMR1H_ADDR) TMR1H;
266 extern __sfr __at (T1CON_ADDR) T1CON;
267 extern __sfr __at (TMR2_ADDR) TMR2;
268 extern __sfr __at (T2CON_ADDR) T2CON;
269 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
270 extern __sfr __at (SSPCON_ADDR) SSPCON;
271 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
272 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
273 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
274 extern __sfr __at (RCSTA_ADDR) RCSTA;
275 extern __sfr __at (TXREG_ADDR) TXREG;
276 extern __sfr __at (RCREG_ADDR) RCREG;
277 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
278 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
279 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
280 extern __sfr __at (ADRESH_ADDR) ADRESH;
281 extern __sfr __at (ADCON0_ADDR) ADCON0;
283 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
284 extern __sfr __at (TRISA_ADDR) TRISA;
285 extern __sfr __at (TRISB_ADDR) TRISB;
286 extern __sfr __at (TRISC_ADDR) TRISC;
287 extern __sfr __at (TRISD_ADDR) TRISD;
288 extern __sfr __at (TRISE_ADDR) TRISE;
289 extern __sfr __at (PIE1_ADDR) PIE1;
290 extern __sfr __at (PIE2_ADDR) PIE2;
291 extern __sfr __at (PCON_ADDR) PCON;
292 extern __sfr __at (OSCCON_ADDR) OSCCON;
293 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
294 extern __sfr __at (ANSEL_ADDR) ANSEL;
295 extern __sfr __at (PR2_ADDR) PR2;
296 extern __sfr __at (SSPADD_ADDR) SSPADD;
297 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
298 extern __sfr __at (WPUB_ADDR) WPUB;
299 extern __sfr __at (WPU_ADDR) WPU;
300 extern __sfr __at (IOCB_ADDR) IOCB;
301 extern __sfr __at (IOC_ADDR) IOC;
302 extern __sfr __at (CMCON1_ADDR) CMCON1;
303 extern __sfr __at (TXSTA_ADDR) TXSTA;
304 extern __sfr __at (SPBRG_ADDR) SPBRG;
305 extern __sfr __at (CMCON0_ADDR) CMCON0;
306 extern __sfr __at (VRCON_ADDR) VRCON;
307 extern __sfr __at (ADRESL_ADDR) ADRESL;
308 extern __sfr __at (ADCON1_ADDR) ADCON1;
310 extern __sfr __at (WDTCON_ADDR) WDTCON;
311 extern __sfr __at (LCDCON_ADDR) LCDCON;
312 extern __sfr __at (LCDPS_ADDR) LCDPS;
313 extern __sfr __at (LVDCON_ADDR) LVDCON;
314 extern __sfr __at (EEDATL_ADDR) EEDATL;
315 extern __sfr __at (EEADRL_ADDR) EEADRL;
316 extern __sfr __at (EEDATH_ADDR) EEDATH;
317 extern __sfr __at (EEADRH_ADDR) EEADRH;
318 extern __sfr __at (LCDDATA0_ADDR) LCDDATA0;
319 extern __sfr __at (LCDDATA1_ADDR) LCDDATA1;
320 extern __sfr __at (LCDDATA2_ADDR) LCDDATA2;
321 extern __sfr __at (LCDDATA3_ADDR) LCDDATA3;
322 extern __sfr __at (LCDDATA4_ADDR) LCDDATA4;
323 extern __sfr __at (LCDDATA5_ADDR) LCDDATA5;
324 extern __sfr __at (LCDDATA6_ADDR) LCDDATA6;
325 extern __sfr __at (LCDDATA7_ADDR) LCDDATA7;
326 extern __sfr __at (LCDDATA8_ADDR) LCDDATA8;
327 extern __sfr __at (LCDDATA9_ADDR) LCDDATA9;
328 extern __sfr __at (LCDDATA10_ADDR) LCDDATA10;
329 extern __sfr __at (LCDDATA11_ADDR) LCDDATA11;
330 extern __sfr __at (LCDSE0_ADDR) LCDSE0;
331 extern __sfr __at (LCDSE1_ADDR) LCDSE1;
332 extern __sfr __at (LCDSE2_ADDR) LCDSE2;
334 extern __sfr __at (EECON1_ADDR) EECON1;
335 extern __sfr __at (EECON2_ADDR) EECON2;
338 //----- STATUS Bits --------------------------------------------------------
341 //----- INTCON Bits --------------------------------------------------------
344 //----- PIR1 Bits ----------------------------------------------------------
347 //----- PIR2 Bits ----------------------------------------------------------
350 //----- T1CON Bits ---------------------------------------------------------
353 //----- T2CON Bits ---------------------------------------------------------
356 //----- SSPCON Bits --------------------------------------------------------
359 //----- CCP1CON Bits -------------------------------------------------------
362 //----- RCSTA Bits ---------------------------------------------------------
365 //----- CCP2CON Bits -------------------------------------------------------
368 //----- ADCON0 Bits --------------------------------------------------------
371 //----- OPTION Bits -----------------------------------------------------
374 //----- PIE1 Bits ----------------------------------------------------------
377 //----- PIE2 Bits ----------------------------------------------------------
380 //----- PCON Bits ----------------------------------------------------------
383 //----- OSCCON Bits -------------------------------------------------------
386 //----- OSCTUNE Bits -------------------------------------------------------
390 //----- ANSEL Bits ---------------------------------------------------------
394 //----- SSPSTAT Bits -------------------------------------------------------
398 //----- WPUB Bits -------------------------------------------------------
401 //----- WPU Bits -------------------------------------------------------
405 //----- IOCB Bits -------------------------------------------------------
409 //----- IOC Bits -------------------------------------------------------
413 //----- CMCON1 Bits --------------------------------------------------------
416 //----- TXSTA Bits ---------------------------------------------------------
420 //----- CMCON0 Bits ---------------------------------------------------------
423 //----- VRCON Bits --------------------------------------------------------
426 //----- ADCON1 Bits --------------------------------------------------------
429 //----- WDTCON Bits --------------------------------------------------------
432 //----- LCDCON Bits --------------------------------------------------------
435 //----- LCDPS Bits ---------------------------------------------------------
438 //----- LVDCON Bits --------------------------------------------------------
441 //----- LCDDATA0 Bits -------------------------------------------------------
445 //----- LCDDATA1 Bits -------------------------------------------------------
449 //----- LCDDATA2 Bits -------------------------------------------------------
453 //----- LCDDATA3 Bits -------------------------------------------------------
457 //----- LCDDATA4 Bits -------------------------------------------------------
461 //----- LCDDATA5 Bits -------------------------------------------------------
465 //----- LCDDATA6 Bits -------------------------------------------------------
469 //----- LCDDATA7 Bits -------------------------------------------------------
473 //----- LCDDATA8 Bits -------------------------------------------------------
477 //----- LCDDATA9 Bits -------------------------------------------------------
481 //----- LCDDATA10 Bits -------------------------------------------------------
485 //----- LCDDATA11 Bits -------------------------------------------------------
489 //----- LCDSE0 Bits --------------------------------------------------------
493 //----- LCDSE1 Bits --------------------------------------------------------
497 //----- LCDSE2 Bits --------------------------------------------------------
501 //----- EECON1 Bits --------------------------------------------------------
505 //==========================================================================
509 //==========================================================================
512 // __BADRAM H'9A'-H'9B'
514 // __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF'
516 //==========================================================================
518 // Configuration Bits
520 //==========================================================================
522 #define _CONFIG 0x2007
524 //Configuration Byte 1 Options
525 #define _DEBUG_ON 0x2FFF
526 #define _DEBUG_OFF 0x3FFF
527 #define _FCMEN_ON 0x3FFF
528 #define _FCMEN_OFF 0x37FF
529 #define _IESO_ON 0x3FFF
530 #define _IESO_OFF 0x3BFF
531 #define _BOD_ON 0x3FFF
532 #define _BOD_NSLEEP 0x3EFF
533 #define _BOD_SBODEN 0x3DFF
534 #define _BOD_OFF 0x3CFF
535 #define _CPD_ON 0x3F7F
536 #define _CPD_OFF 0x3FFF
537 #define _CP_ON 0x3FBF
538 #define _CP_OFF 0x3FFF
539 #define _MCLRE_ON 0x3FFF
540 #define _MCLRE_OFF 0x3FDF
541 #define _PWRTE_ON 0x3FEF
542 #define _PWRTE_OFF 0x3FFF
543 #define _WDT_ON 0x3FFF
544 #define _WDT_OFF 0x3FF7
545 #define _LP_OSC 0x3FF8
546 #define _XT_OSC 0x3FF9
547 #define _HS_OSC 0x3FFA
548 #define _EC_OSC 0x3FFB
549 #define _INTRC_OSC_NOCLKOUT 0x3FFC
550 #define _INTRC_OSC_CLKOUT 0x3FFD
551 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
552 #define _EXTRC_OSC_CLKOUT 0x3FFF
553 #define _INTOSCIO 0x3FFC
554 #define _INTOSC 0x3FFD
555 #define _EXTRCIO 0x3FFE
556 #define _EXTRC 0x3FFF
561 // ----- ADCON0 bits --------------------
564 unsigned char ADON:1;
565 unsigned char NOT_DONE:1;
566 unsigned char CHS0:1;
567 unsigned char CHS1:1;
568 unsigned char CHS2:1;
569 unsigned char VCFG0:1;
570 unsigned char VCFG1:1;
571 unsigned char ADFM:1;
575 unsigned char GO_DONE:1;
584 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
586 #define ADON ADCON0_bits.ADON
587 #define NOT_DONE ADCON0_bits.NOT_DONE
588 #define GO_DONE ADCON0_bits.GO_DONE
589 #define CHS0 ADCON0_bits.CHS0
590 #define CHS1 ADCON0_bits.CHS1
591 #define CHS2 ADCON0_bits.CHS2
592 #define VCFG0 ADCON0_bits.VCFG0
593 #define VCFG1 ADCON0_bits.VCFG1
594 #define ADFM ADCON0_bits.ADFM
596 // ----- ADCON1 bits --------------------
603 unsigned char ADCS0:1;
604 unsigned char ADCS1:1;
605 unsigned char ADCS2:1;
609 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
611 #define ADCS0 ADCON1_bits.ADCS0
612 #define ADCS1 ADCON1_bits.ADCS1
613 #define ADCS2 ADCON1_bits.ADCS2
615 // ----- ANSEL bits --------------------
628 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
630 #define AN0 ANSEL_bits.AN0
631 #define AN1 ANSEL_bits.AN1
632 #define AN2 ANSEL_bits.AN2
633 #define AN3 ANSEL_bits.AN3
634 #define AN4 ANSEL_bits.AN4
635 #define AN5 ANSEL_bits.AN5
636 #define AN6 ANSEL_bits.AN6
637 #define AN7 ANSEL_bits.AN7
639 // ----- CCP1CON bits --------------------
642 unsigned char CCP1M0:1;
643 unsigned char CCP1M1:1;
644 unsigned char CCP1M2:1;
645 unsigned char CCP1M3:1;
646 unsigned char CCP1Y:1;
647 unsigned char CCP1X:1;
652 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
654 #define CCP1M0 CCP1CON_bits.CCP1M0
655 #define CCP1M1 CCP1CON_bits.CCP1M1
656 #define CCP1M2 CCP1CON_bits.CCP1M2
657 #define CCP1M3 CCP1CON_bits.CCP1M3
658 #define CCP1Y CCP1CON_bits.CCP1Y
659 #define CCP1X CCP1CON_bits.CCP1X
661 // ----- CCP2CON bits --------------------
664 unsigned char CCP2M0:1;
665 unsigned char CCP2M1:1;
666 unsigned char CCP2M2:1;
667 unsigned char CCP2M3:1;
668 unsigned char CCP2Y:1;
669 unsigned char CCP2X:1;
674 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
676 #define CCP2M0 CCP2CON_bits.CCP2M0
677 #define CCP2M1 CCP2CON_bits.CCP2M1
678 #define CCP2M2 CCP2CON_bits.CCP2M2
679 #define CCP2M3 CCP2CON_bits.CCP2M3
680 #define CCP2Y CCP2CON_bits.CCP2Y
681 #define CCP2X CCP2CON_bits.CCP2X
683 // ----- CMCON0 bits --------------------
690 unsigned char C1INV:1;
691 unsigned char C2INV:1;
692 unsigned char C1OUT:1;
693 unsigned char C2OUT:1;
696 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
698 #define CM0 CMCON0_bits.CM0
699 #define CM1 CMCON0_bits.CM1
700 #define CM2 CMCON0_bits.CM2
701 #define CIS CMCON0_bits.CIS
702 #define C1INV CMCON0_bits.C1INV
703 #define C2INV CMCON0_bits.C2INV
704 #define C1OUT CMCON0_bits.C1OUT
705 #define C2OUT CMCON0_bits.C2OUT
707 // ----- CMCON1 bits --------------------
710 unsigned char C2SYNC:1;
711 unsigned char T1GSS:1;
720 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
722 #define C2SYNC CMCON1_bits.C2SYNC
723 #define T1GSS CMCON1_bits.T1GSS
725 // ----- EECON1 bits --------------------
730 unsigned char WREN:1;
731 unsigned char WRERR:1;
735 unsigned char EEPGD:1;
738 unsigned char EERD:1;
739 unsigned char EEWR:1;
748 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
750 #define RD EECON1_bits.RD
751 #define EERD EECON1_bits.EERD
752 #define WR EECON1_bits.WR
753 #define EEWR EECON1_bits.EEWR
754 #define WREN EECON1_bits.WREN
755 #define WRERR EECON1_bits.WRERR
756 #define EEPGD EECON1_bits.EEPGD
758 // ----- INTCON bits --------------------
761 unsigned char RBIF:1;
762 unsigned char INTF:1;
763 unsigned char T0IF:1;
764 unsigned char RBIE:1;
765 unsigned char INTE:1;
766 unsigned char T0IE:1;
767 unsigned char PEIE:1;
773 unsigned char TMR0IF:1;
776 unsigned char TMR0IE:1;
781 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
783 #define RBIF INTCON_bits.RBIF
784 #define INTF INTCON_bits.INTF
785 #define T0IF INTCON_bits.T0IF
786 #define TMR0IF INTCON_bits.TMR0IF
787 #define RBIE INTCON_bits.RBIE
788 #define INTE INTCON_bits.INTE
789 #define T0IE INTCON_bits.T0IE
790 #define TMR0IE INTCON_bits.TMR0IE
791 #define PEIE INTCON_bits.PEIE
792 #define GIE INTCON_bits.GIE
794 // ----- IOC bits --------------------
801 unsigned char IOC4:1;
802 unsigned char IOC5:1;
803 unsigned char IOC6:1;
804 unsigned char IOC7:1;
807 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
809 #define IOC4 IOC_bits.IOC4
810 #define IOC5 IOC_bits.IOC5
811 #define IOC6 IOC_bits.IOC6
812 #define IOC7 IOC_bits.IOC7
814 // ----- IOCB bits --------------------
821 unsigned char IOCB4:1;
822 unsigned char IOCB5:1;
823 unsigned char IOCB6:1;
824 unsigned char IOCB7:1;
827 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
829 #define IOCB4 IOCB_bits.IOCB4
830 #define IOCB5 IOCB_bits.IOCB5
831 #define IOCB6 IOCB_bits.IOCB6
832 #define IOCB7 IOCB_bits.IOCB7
834 // ----- LCDCON bits --------------------
837 unsigned char LMUX0:1;
838 unsigned char LMUX1:1;
841 unsigned char VLCDEN:1;
842 unsigned char WERR:1;
843 unsigned char SLPEN:1;
844 unsigned char LCDEN:1;
847 extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits;
849 #define LMUX0 LCDCON_bits.LMUX0
850 #define LMUX1 LCDCON_bits.LMUX1
851 #define CS0 LCDCON_bits.CS0
852 #define CS1 LCDCON_bits.CS1
853 #define VLCDEN LCDCON_bits.VLCDEN
854 #define WERR LCDCON_bits.WERR
855 #define SLPEN LCDCON_bits.SLPEN
856 #define LCDEN LCDCON_bits.LCDEN
858 // ----- LCDDATA0 bits --------------------
861 unsigned char SEG0COM0:1;
862 unsigned char SEG1COM0:1;
863 unsigned char SEG2COM0:1;
864 unsigned char SEG3COM0:1;
865 unsigned char SEG4COM0:1;
866 unsigned char SEG5COM0:1;
867 unsigned char SEG6COM0:1;
868 unsigned char SEG7COM0:1;
871 unsigned char S0C0:1;
872 unsigned char S1C0:1;
873 unsigned char S2C0:1;
874 unsigned char S3C0:1;
875 unsigned char S4C0:1;
876 unsigned char S5C0:1;
877 unsigned char S6C0:1;
878 unsigned char S7C0:1;
881 extern volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits;
883 #define SEG0COM0 LCDDATA0_bits.SEG0COM0
884 #define S0C0 LCDDATA0_bits.S0C0
885 #define SEG1COM0 LCDDATA0_bits.SEG1COM0
886 #define S1C0 LCDDATA0_bits.S1C0
887 #define SEG2COM0 LCDDATA0_bits.SEG2COM0
888 #define S2C0 LCDDATA0_bits.S2C0
889 #define SEG3COM0 LCDDATA0_bits.SEG3COM0
890 #define S3C0 LCDDATA0_bits.S3C0
891 #define SEG4COM0 LCDDATA0_bits.SEG4COM0
892 #define S4C0 LCDDATA0_bits.S4C0
893 #define SEG5COM0 LCDDATA0_bits.SEG5COM0
894 #define S5C0 LCDDATA0_bits.S5C0
895 #define SEG6COM0 LCDDATA0_bits.SEG6COM0
896 #define S6C0 LCDDATA0_bits.S6C0
897 #define SEG7COM0 LCDDATA0_bits.SEG7COM0
898 #define S7C0 LCDDATA0_bits.S7C0
900 // ----- LCDDATA1 bits --------------------
903 unsigned char SEG8COM0:1;
904 unsigned char SEG9COM0:1;
905 unsigned char SEG10COM0:1;
906 unsigned char SEG11COM0:1;
907 unsigned char SEG12COM0:1;
908 unsigned char SEG13COM0:1;
909 unsigned char SEG14COM0:1;
910 unsigned char SEG15COM0:1;
913 unsigned char S8C0:1;
914 unsigned char S9C0:1;
915 unsigned char S10C0:1;
916 unsigned char S11C0:1;
917 unsigned char S12C0:1;
918 unsigned char S13C0:1;
919 unsigned char S14C0:1;
920 unsigned char S15C0:1;
923 extern volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits;
925 #define SEG8COM0 LCDDATA1_bits.SEG8COM0
926 #define S8C0 LCDDATA1_bits.S8C0
927 #define SEG9COM0 LCDDATA1_bits.SEG9COM0
928 #define S9C0 LCDDATA1_bits.S9C0
929 #define SEG10COM0 LCDDATA1_bits.SEG10COM0
930 #define S10C0 LCDDATA1_bits.S10C0
931 #define SEG11COM0 LCDDATA1_bits.SEG11COM0
932 #define S11C0 LCDDATA1_bits.S11C0
933 #define SEG12COM0 LCDDATA1_bits.SEG12COM0
934 #define S12C0 LCDDATA1_bits.S12C0
935 #define SEG13COM0 LCDDATA1_bits.SEG13COM0
936 #define S13C0 LCDDATA1_bits.S13C0
937 #define SEG14COM0 LCDDATA1_bits.SEG14COM0
938 #define S14C0 LCDDATA1_bits.S14C0
939 #define SEG15COM0 LCDDATA1_bits.SEG15COM0
940 #define S15C0 LCDDATA1_bits.S15C0
942 // ----- LCDDATA10 bits --------------------
945 unsigned char SEG8COM3:1;
946 unsigned char SEG9COM3:1;
947 unsigned char SEG10COM3:1;
948 unsigned char SEG11COM3:1;
949 unsigned char SEG12COM3:1;
950 unsigned char SEG13COM3:1;
951 unsigned char SEG14COM3:1;
952 unsigned char SEG15COM3:1;
955 unsigned char S8C3:1;
956 unsigned char S9C3:1;
957 unsigned char S10C3:1;
958 unsigned char S11C3:1;
959 unsigned char S12C3:1;
960 unsigned char S13C3:1;
961 unsigned char S14C3:1;
962 unsigned char S15C3:1;
964 } __LCDDATA10_bits_t;
965 extern volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits;
967 #define SEG8COM3 LCDDATA10_bits.SEG8COM3
968 #define S8C3 LCDDATA10_bits.S8C3
969 #define SEG9COM3 LCDDATA10_bits.SEG9COM3
970 #define S9C3 LCDDATA10_bits.S9C3
971 #define SEG10COM3 LCDDATA10_bits.SEG10COM3
972 #define S10C3 LCDDATA10_bits.S10C3
973 #define SEG11COM3 LCDDATA10_bits.SEG11COM3
974 #define S11C3 LCDDATA10_bits.S11C3
975 #define SEG12COM3 LCDDATA10_bits.SEG12COM3
976 #define S12C3 LCDDATA10_bits.S12C3
977 #define SEG13COM3 LCDDATA10_bits.SEG13COM3
978 #define S13C3 LCDDATA10_bits.S13C3
979 #define SEG14COM3 LCDDATA10_bits.SEG14COM3
980 #define S14C3 LCDDATA10_bits.S14C3
981 #define SEG15COM3 LCDDATA10_bits.SEG15COM3
982 #define S15C3 LCDDATA10_bits.S15C3
984 // ----- LCDDATA11 bits --------------------
987 unsigned char SEG16COM3:1;
988 unsigned char SEG17COM3:1;
989 unsigned char SEG18COM3:1;
990 unsigned char SEG19COM3:1;
991 unsigned char SEG20COM3:1;
992 unsigned char SEG21COM3:1;
993 unsigned char SEG22COM3:1;
994 unsigned char SEG23COM3:1;
997 unsigned char S16C3:1;
998 unsigned char S17C3:1;
999 unsigned char S18C3:1;
1000 unsigned char S19C3:1;
1001 unsigned char S20C3:1;
1002 unsigned char S21C3:1;
1003 unsigned char S22C3:1;
1004 unsigned char S23C3:1;
1006 } __LCDDATA11_bits_t;
1007 extern volatile __LCDDATA11_bits_t __at(LCDDATA11_ADDR) LCDDATA11_bits;
1009 #define SEG16COM3 LCDDATA11_bits.SEG16COM3
1010 #define S16C3 LCDDATA11_bits.S16C3
1011 #define SEG17COM3 LCDDATA11_bits.SEG17COM3
1012 #define S17C3 LCDDATA11_bits.S17C3
1013 #define SEG18COM3 LCDDATA11_bits.SEG18COM3
1014 #define S18C3 LCDDATA11_bits.S18C3
1015 #define SEG19COM3 LCDDATA11_bits.SEG19COM3
1016 #define S19C3 LCDDATA11_bits.S19C3
1017 #define SEG20COM3 LCDDATA11_bits.SEG20COM3
1018 #define S20C3 LCDDATA11_bits.S20C3
1019 #define SEG21COM3 LCDDATA11_bits.SEG21COM3
1020 #define S21C3 LCDDATA11_bits.S21C3
1021 #define SEG22COM3 LCDDATA11_bits.SEG22COM3
1022 #define S22C3 LCDDATA11_bits.S22C3
1023 #define SEG23COM3 LCDDATA11_bits.SEG23COM3
1024 #define S23C3 LCDDATA11_bits.S23C3
1026 // ----- LCDDATA2 bits --------------------
1029 unsigned char SEG16COM0:1;
1030 unsigned char SEG17COM0:1;
1031 unsigned char SEG18COM0:1;
1032 unsigned char SEG19COM0:1;
1033 unsigned char SEG20COM0:1;
1034 unsigned char SEG21COM0:1;
1035 unsigned char SEG22COM0:1;
1036 unsigned char SEG23COM0:1;
1039 unsigned char S16C0:1;
1040 unsigned char S17C0:1;
1041 unsigned char S18C0:1;
1042 unsigned char S19C0:1;
1043 unsigned char S20C0:1;
1044 unsigned char S21C0:1;
1045 unsigned char S22C0:1;
1046 unsigned char S23C0:1;
1048 } __LCDDATA2_bits_t;
1049 extern volatile __LCDDATA2_bits_t __at(LCDDATA2_ADDR) LCDDATA2_bits;
1051 #define SEG16COM0 LCDDATA2_bits.SEG16COM0
1052 #define S16C0 LCDDATA2_bits.S16C0
1053 #define SEG17COM0 LCDDATA2_bits.SEG17COM0
1054 #define S17C0 LCDDATA2_bits.S17C0
1055 #define SEG18COM0 LCDDATA2_bits.SEG18COM0
1056 #define S18C0 LCDDATA2_bits.S18C0
1057 #define SEG19COM0 LCDDATA2_bits.SEG19COM0
1058 #define S19C0 LCDDATA2_bits.S19C0
1059 #define SEG20COM0 LCDDATA2_bits.SEG20COM0
1060 #define S20C0 LCDDATA2_bits.S20C0
1061 #define SEG21COM0 LCDDATA2_bits.SEG21COM0
1062 #define S21C0 LCDDATA2_bits.S21C0
1063 #define SEG22COM0 LCDDATA2_bits.SEG22COM0
1064 #define S22C0 LCDDATA2_bits.S22C0
1065 #define SEG23COM0 LCDDATA2_bits.SEG23COM0
1066 #define S23C0 LCDDATA2_bits.S23C0
1068 // ----- LCDDATA3 bits --------------------
1071 unsigned char SEG0COM1:1;
1072 unsigned char SEG1COM1:1;
1073 unsigned char SEG2COM1:1;
1074 unsigned char SEG3COM1:1;
1075 unsigned char SEG4COM1:1;
1076 unsigned char SEG5COM1:1;
1077 unsigned char SEG6COM1:1;
1078 unsigned char SEG7COM1:1;
1081 unsigned char S0C1:1;
1082 unsigned char S1C1:1;
1083 unsigned char S2C1:1;
1084 unsigned char S3C1:1;
1085 unsigned char S4C1:1;
1086 unsigned char S5C1:1;
1087 unsigned char S6C1:1;
1088 unsigned char S7C1:1;
1090 } __LCDDATA3_bits_t;
1091 extern volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits;
1093 #define SEG0COM1 LCDDATA3_bits.SEG0COM1
1094 #define S0C1 LCDDATA3_bits.S0C1
1095 #define SEG1COM1 LCDDATA3_bits.SEG1COM1
1096 #define S1C1 LCDDATA3_bits.S1C1
1097 #define SEG2COM1 LCDDATA3_bits.SEG2COM1
1098 #define S2C1 LCDDATA3_bits.S2C1
1099 #define SEG3COM1 LCDDATA3_bits.SEG3COM1
1100 #define S3C1 LCDDATA3_bits.S3C1
1101 #define SEG4COM1 LCDDATA3_bits.SEG4COM1
1102 #define S4C1 LCDDATA3_bits.S4C1
1103 #define SEG5COM1 LCDDATA3_bits.SEG5COM1
1104 #define S5C1 LCDDATA3_bits.S5C1
1105 #define SEG6COM1 LCDDATA3_bits.SEG6COM1
1106 #define S6C1 LCDDATA3_bits.S6C1
1107 #define SEG7COM1 LCDDATA3_bits.SEG7COM1
1108 #define S7C1 LCDDATA3_bits.S7C1
1110 // ----- LCDDATA4 bits --------------------
1113 unsigned char SEG8COM1:1;
1114 unsigned char SEG9COM1:1;
1115 unsigned char SEG10COM1:1;
1116 unsigned char SEG11COM1:1;
1117 unsigned char SEG12COM1:1;
1118 unsigned char SEG13COM1:1;
1119 unsigned char SEG14COM1:1;
1120 unsigned char SEG15COM1:1;
1123 unsigned char S8C1:1;
1124 unsigned char S9C1:1;
1125 unsigned char S10C1:1;
1126 unsigned char S11C1:1;
1127 unsigned char S12C1:1;
1128 unsigned char S13C1:1;
1129 unsigned char S14C1:1;
1130 unsigned char S15C1:1;
1132 } __LCDDATA4_bits_t;
1133 extern volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits;
1135 #define SEG8COM1 LCDDATA4_bits.SEG8COM1
1136 #define S8C1 LCDDATA4_bits.S8C1
1137 #define SEG9COM1 LCDDATA4_bits.SEG9COM1
1138 #define S9C1 LCDDATA4_bits.S9C1
1139 #define SEG10COM1 LCDDATA4_bits.SEG10COM1
1140 #define S10C1 LCDDATA4_bits.S10C1
1141 #define SEG11COM1 LCDDATA4_bits.SEG11COM1
1142 #define S11C1 LCDDATA4_bits.S11C1
1143 #define SEG12COM1 LCDDATA4_bits.SEG12COM1
1144 #define S12C1 LCDDATA4_bits.S12C1
1145 #define SEG13COM1 LCDDATA4_bits.SEG13COM1
1146 #define S13C1 LCDDATA4_bits.S13C1
1147 #define SEG14COM1 LCDDATA4_bits.SEG14COM1
1148 #define S14C1 LCDDATA4_bits.S14C1
1149 #define SEG15COM1 LCDDATA4_bits.SEG15COM1
1150 #define S15C1 LCDDATA4_bits.S15C1
1152 // ----- LCDDATA5 bits --------------------
1155 unsigned char SEG16COM1:1;
1156 unsigned char SEG17COM1:1;
1157 unsigned char SEG18COM1:1;
1158 unsigned char SEG19COM1:1;
1159 unsigned char SEG20COM1:1;
1160 unsigned char SEG21COM1:1;
1161 unsigned char SEG22COM1:1;
1162 unsigned char SEG23COM1:1;
1165 unsigned char S16C1:1;
1166 unsigned char S17C1:1;
1167 unsigned char S18C1:1;
1168 unsigned char S19C1:1;
1169 unsigned char S20C1:1;
1170 unsigned char S21C1:1;
1171 unsigned char S22C1:1;
1172 unsigned char S23C1:1;
1174 } __LCDDATA5_bits_t;
1175 extern volatile __LCDDATA5_bits_t __at(LCDDATA5_ADDR) LCDDATA5_bits;
1177 #define SEG16COM1 LCDDATA5_bits.SEG16COM1
1178 #define S16C1 LCDDATA5_bits.S16C1
1179 #define SEG17COM1 LCDDATA5_bits.SEG17COM1
1180 #define S17C1 LCDDATA5_bits.S17C1
1181 #define SEG18COM1 LCDDATA5_bits.SEG18COM1
1182 #define S18C1 LCDDATA5_bits.S18C1
1183 #define SEG19COM1 LCDDATA5_bits.SEG19COM1
1184 #define S19C1 LCDDATA5_bits.S19C1
1185 #define SEG20COM1 LCDDATA5_bits.SEG20COM1
1186 #define S20C1 LCDDATA5_bits.S20C1
1187 #define SEG21COM1 LCDDATA5_bits.SEG21COM1
1188 #define S21C1 LCDDATA5_bits.S21C1
1189 #define SEG22COM1 LCDDATA5_bits.SEG22COM1
1190 #define S22C1 LCDDATA5_bits.S22C1
1191 #define SEG23COM1 LCDDATA5_bits.SEG23COM1
1192 #define S23C1 LCDDATA5_bits.S23C1
1194 // ----- LCDDATA6 bits --------------------
1197 unsigned char SEG0COM2:1;
1198 unsigned char SEG1COM2:1;
1199 unsigned char SEG2COM2:1;
1200 unsigned char SEG3COM2:1;
1201 unsigned char SEG4COM2:1;
1202 unsigned char SEG5COM2:1;
1203 unsigned char SEG6COM2:1;
1204 unsigned char SEG7COM2:1;
1207 unsigned char S0C2:1;
1208 unsigned char S1C2:1;
1209 unsigned char S2C2:1;
1210 unsigned char S3C2:1;
1211 unsigned char S4C2:1;
1212 unsigned char S5C2:1;
1213 unsigned char S6C2:1;
1214 unsigned char S7C2:1;
1216 } __LCDDATA6_bits_t;
1217 extern volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits;
1219 #define SEG0COM2 LCDDATA6_bits.SEG0COM2
1220 #define S0C2 LCDDATA6_bits.S0C2
1221 #define SEG1COM2 LCDDATA6_bits.SEG1COM2
1222 #define S1C2 LCDDATA6_bits.S1C2
1223 #define SEG2COM2 LCDDATA6_bits.SEG2COM2
1224 #define S2C2 LCDDATA6_bits.S2C2
1225 #define SEG3COM2 LCDDATA6_bits.SEG3COM2
1226 #define S3C2 LCDDATA6_bits.S3C2
1227 #define SEG4COM2 LCDDATA6_bits.SEG4COM2
1228 #define S4C2 LCDDATA6_bits.S4C2
1229 #define SEG5COM2 LCDDATA6_bits.SEG5COM2
1230 #define S5C2 LCDDATA6_bits.S5C2
1231 #define SEG6COM2 LCDDATA6_bits.SEG6COM2
1232 #define S6C2 LCDDATA6_bits.S6C2
1233 #define SEG7COM2 LCDDATA6_bits.SEG7COM2
1234 #define S7C2 LCDDATA6_bits.S7C2
1236 // ----- LCDDATA7 bits --------------------
1239 unsigned char SEG8COM2:1;
1240 unsigned char SEG9COM2:1;
1241 unsigned char SEG10COM2:1;
1242 unsigned char SEG11COM2:1;
1243 unsigned char SEG12COM2:1;
1244 unsigned char SEG13COM2:1;
1245 unsigned char SEG14COM2:1;
1246 unsigned char SEG15COM2:1;
1249 unsigned char S8C2:1;
1250 unsigned char S9C2:1;
1251 unsigned char S10C2:1;
1252 unsigned char S11C2:1;
1253 unsigned char S12C2:1;
1254 unsigned char S13C2:1;
1255 unsigned char S14C2:1;
1256 unsigned char S15C2:1;
1258 } __LCDDATA7_bits_t;
1259 extern volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits;
1261 #define SEG8COM2 LCDDATA7_bits.SEG8COM2
1262 #define S8C2 LCDDATA7_bits.S8C2
1263 #define SEG9COM2 LCDDATA7_bits.SEG9COM2
1264 #define S9C2 LCDDATA7_bits.S9C2
1265 #define SEG10COM2 LCDDATA7_bits.SEG10COM2
1266 #define S10C2 LCDDATA7_bits.S10C2
1267 #define SEG11COM2 LCDDATA7_bits.SEG11COM2
1268 #define S11C2 LCDDATA7_bits.S11C2
1269 #define SEG12COM2 LCDDATA7_bits.SEG12COM2
1270 #define S12C2 LCDDATA7_bits.S12C2
1271 #define SEG13COM2 LCDDATA7_bits.SEG13COM2
1272 #define S13C2 LCDDATA7_bits.S13C2
1273 #define SEG14COM2 LCDDATA7_bits.SEG14COM2
1274 #define S14C2 LCDDATA7_bits.S14C2
1275 #define SEG15COM2 LCDDATA7_bits.SEG15COM2
1276 #define S15C2 LCDDATA7_bits.S15C2
1278 // ----- LCDDATA8 bits --------------------
1281 unsigned char SEG16COM2:1;
1282 unsigned char SEG17COM2:1;
1283 unsigned char SEG18COM2:1;
1284 unsigned char SEG19COM2:1;
1285 unsigned char SEG20COM2:1;
1286 unsigned char SEG21COM2:1;
1287 unsigned char SEG22COM2:1;
1288 unsigned char SEG23COM2:1;
1291 unsigned char S16C2:1;
1292 unsigned char S17C2:1;
1293 unsigned char S18C2:1;
1294 unsigned char S19C2:1;
1295 unsigned char S20C2:1;
1296 unsigned char S21C2:1;
1297 unsigned char S22C2:1;
1298 unsigned char S23C2:1;
1300 } __LCDDATA8_bits_t;
1301 extern volatile __LCDDATA8_bits_t __at(LCDDATA8_ADDR) LCDDATA8_bits;
1303 #define SEG16COM2 LCDDATA8_bits.SEG16COM2
1304 #define S16C2 LCDDATA8_bits.S16C2
1305 #define SEG17COM2 LCDDATA8_bits.SEG17COM2
1306 #define S17C2 LCDDATA8_bits.S17C2
1307 #define SEG18COM2 LCDDATA8_bits.SEG18COM2
1308 #define S18C2 LCDDATA8_bits.S18C2
1309 #define SEG19COM2 LCDDATA8_bits.SEG19COM2
1310 #define S19C2 LCDDATA8_bits.S19C2
1311 #define SEG20COM2 LCDDATA8_bits.SEG20COM2
1312 #define S20C2 LCDDATA8_bits.S20C2
1313 #define SEG21COM2 LCDDATA8_bits.SEG21COM2
1314 #define S21C2 LCDDATA8_bits.S21C2
1315 #define SEG22COM2 LCDDATA8_bits.SEG22COM2
1316 #define S22C2 LCDDATA8_bits.S22C2
1317 #define SEG23COM2 LCDDATA8_bits.SEG23COM2
1318 #define S23C2 LCDDATA8_bits.S23C2
1320 // ----- LCDDATA9 bits --------------------
1323 unsigned char SEG0COM3:1;
1324 unsigned char SEG1COM3:1;
1325 unsigned char SEG2COM3:1;
1326 unsigned char SEG3COM3:1;
1327 unsigned char SEG4COM3:1;
1328 unsigned char SEG5COM3:1;
1329 unsigned char SEG6COM3:1;
1330 unsigned char SEG7COM3:1;
1333 unsigned char S0C3:1;
1334 unsigned char S1C3:1;
1335 unsigned char S2C3:1;
1336 unsigned char S3C3:1;
1337 unsigned char S4C3:1;
1338 unsigned char S5C3:1;
1339 unsigned char S6C3:1;
1340 unsigned char S7C3:1;
1342 } __LCDDATA9_bits_t;
1343 extern volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits;
1345 #define SEG0COM3 LCDDATA9_bits.SEG0COM3
1346 #define S0C3 LCDDATA9_bits.S0C3
1347 #define SEG1COM3 LCDDATA9_bits.SEG1COM3
1348 #define S1C3 LCDDATA9_bits.S1C3
1349 #define SEG2COM3 LCDDATA9_bits.SEG2COM3
1350 #define S2C3 LCDDATA9_bits.S2C3
1351 #define SEG3COM3 LCDDATA9_bits.SEG3COM3
1352 #define S3C3 LCDDATA9_bits.S3C3
1353 #define SEG4COM3 LCDDATA9_bits.SEG4COM3
1354 #define S4C3 LCDDATA9_bits.S4C3
1355 #define SEG5COM3 LCDDATA9_bits.SEG5COM3
1356 #define S5C3 LCDDATA9_bits.S5C3
1357 #define SEG6COM3 LCDDATA9_bits.SEG6COM3
1358 #define S6C3 LCDDATA9_bits.S6C3
1359 #define SEG7COM3 LCDDATA9_bits.SEG7COM3
1360 #define S7C3 LCDDATA9_bits.S7C3
1362 // ----- LCDPS bits --------------------
1365 unsigned char LP0:1;
1366 unsigned char LP1:1;
1367 unsigned char LP2:1;
1368 unsigned char LP3:1;
1370 unsigned char LCDA:1;
1371 unsigned char BIASMD:1;
1372 unsigned char WFT:1;
1375 extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits;
1377 #define LP0 LCDPS_bits.LP0
1378 #define LP1 LCDPS_bits.LP1
1379 #define LP2 LCDPS_bits.LP2
1380 #define LP3 LCDPS_bits.LP3
1381 #define WA LCDPS_bits.WA
1382 #define LCDA LCDPS_bits.LCDA
1383 #define BIASMD LCDPS_bits.BIASMD
1384 #define WFT LCDPS_bits.WFT
1386 // ----- LCDSE0 bits --------------------
1389 unsigned char SE0:1;
1390 unsigned char SE1:1;
1391 unsigned char SE2:1;
1392 unsigned char SE3:1;
1393 unsigned char SE4:1;
1394 unsigned char SE5:1;
1395 unsigned char SE6:1;
1396 unsigned char SE7:1;
1399 unsigned char SEGEN0:1;
1400 unsigned char SEGEN1:1;
1401 unsigned char SEGEN2:1;
1402 unsigned char SEGEN3:1;
1403 unsigned char SEGEN4:1;
1404 unsigned char SEGEN5:1;
1405 unsigned char SEGEN6:1;
1406 unsigned char SEGEN7:1;
1409 extern volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits;
1411 #define SE0 LCDSE0_bits.SE0
1412 #define SEGEN0 LCDSE0_bits.SEGEN0
1413 #define SE1 LCDSE0_bits.SE1
1414 #define SEGEN1 LCDSE0_bits.SEGEN1
1415 #define SE2 LCDSE0_bits.SE2
1416 #define SEGEN2 LCDSE0_bits.SEGEN2
1417 #define SE3 LCDSE0_bits.SE3
1418 #define SEGEN3 LCDSE0_bits.SEGEN3
1419 #define SE4 LCDSE0_bits.SE4
1420 #define SEGEN4 LCDSE0_bits.SEGEN4
1421 #define SE5 LCDSE0_bits.SE5
1422 #define SEGEN5 LCDSE0_bits.SEGEN5
1423 #define SE6 LCDSE0_bits.SE6
1424 #define SEGEN6 LCDSE0_bits.SEGEN6
1425 #define SE7 LCDSE0_bits.SE7
1426 #define SEGEN7 LCDSE0_bits.SEGEN7
1428 // ----- LCDSE1 bits --------------------
1431 unsigned char SE8:1;
1432 unsigned char SE9:1;
1433 unsigned char SE10:1;
1434 unsigned char SE11:1;
1435 unsigned char SE12:1;
1436 unsigned char SE13:1;
1437 unsigned char SE14:1;
1438 unsigned char SE15:1;
1441 unsigned char SEGEN8:1;
1442 unsigned char SEGEN9:1;
1443 unsigned char SEGEN10:1;
1444 unsigned char SEGEN11:1;
1445 unsigned char SEGEN12:1;
1446 unsigned char SEGEN13:1;
1447 unsigned char SEGEN14:1;
1448 unsigned char SEGEN15:1;
1451 extern volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits;
1453 #define SE8 LCDSE1_bits.SE8
1454 #define SEGEN8 LCDSE1_bits.SEGEN8
1455 #define SE9 LCDSE1_bits.SE9
1456 #define SEGEN9 LCDSE1_bits.SEGEN9
1457 #define SE10 LCDSE1_bits.SE10
1458 #define SEGEN10 LCDSE1_bits.SEGEN10
1459 #define SE11 LCDSE1_bits.SE11
1460 #define SEGEN11 LCDSE1_bits.SEGEN11
1461 #define SE12 LCDSE1_bits.SE12
1462 #define SEGEN12 LCDSE1_bits.SEGEN12
1463 #define SE13 LCDSE1_bits.SE13
1464 #define SEGEN13 LCDSE1_bits.SEGEN13
1465 #define SE14 LCDSE1_bits.SE14
1466 #define SEGEN14 LCDSE1_bits.SEGEN14
1467 #define SE15 LCDSE1_bits.SE15
1468 #define SEGEN15 LCDSE1_bits.SEGEN15
1470 // ----- LCDSE2 bits --------------------
1473 unsigned char SE16:1;
1474 unsigned char SE17:1;
1475 unsigned char SE18:1;
1476 unsigned char SE19:1;
1477 unsigned char SE20:1;
1478 unsigned char SE21:1;
1479 unsigned char SE22:1;
1480 unsigned char SE23:1;
1483 unsigned char SEGEN16:1;
1484 unsigned char SEGEN17:1;
1485 unsigned char SEGEN18:1;
1486 unsigned char SEGEN19:1;
1487 unsigned char SEGEN20:1;
1488 unsigned char SEGEN21:1;
1489 unsigned char SEGEN22:1;
1490 unsigned char SEGEN23:1;
1493 extern volatile __LCDSE2_bits_t __at(LCDSE2_ADDR) LCDSE2_bits;
1495 #define SE16 LCDSE2_bits.SE16
1496 #define SEGEN16 LCDSE2_bits.SEGEN16
1497 #define SE17 LCDSE2_bits.SE17
1498 #define SEGEN17 LCDSE2_bits.SEGEN17
1499 #define SE18 LCDSE2_bits.SE18
1500 #define SEGEN18 LCDSE2_bits.SEGEN18
1501 #define SE19 LCDSE2_bits.SE19
1502 #define SEGEN19 LCDSE2_bits.SEGEN19
1503 #define SE20 LCDSE2_bits.SE20
1504 #define SEGEN20 LCDSE2_bits.SEGEN20
1505 #define SE21 LCDSE2_bits.SE21
1506 #define SEGEN21 LCDSE2_bits.SEGEN21
1507 #define SE22 LCDSE2_bits.SE22
1508 #define SEGEN22 LCDSE2_bits.SEGEN22
1509 #define SE23 LCDSE2_bits.SE23
1510 #define SEGEN23 LCDSE2_bits.SEGEN23
1512 // ----- LVDCON bits --------------------
1515 unsigned char LVDL0:1;
1516 unsigned char LVDL1:1;
1517 unsigned char LVDL2:1;
1519 unsigned char LVDEN:1;
1520 unsigned char IRVST:1;
1525 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
1527 #define LVDL0 LVDCON_bits.LVDL0
1528 #define LVDL1 LVDCON_bits.LVDL1
1529 #define LVDL2 LVDCON_bits.LVDL2
1530 #define LVDEN LVDCON_bits.LVDEN
1531 #define IRVST LVDCON_bits.IRVST
1533 // ----- OPTION_REG bits --------------------
1536 unsigned char PS0:1;
1537 unsigned char PS1:1;
1538 unsigned char PS2:1;
1539 unsigned char PSA:1;
1540 unsigned char T0SE:1;
1541 unsigned char T0CS:1;
1542 unsigned char INTEDG:1;
1543 unsigned char NOT_RBPU:1;
1545 } __OPTION_REG_bits_t;
1546 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
1548 #define PS0 OPTION_REG_bits.PS0
1549 #define PS1 OPTION_REG_bits.PS1
1550 #define PS2 OPTION_REG_bits.PS2
1551 #define PSA OPTION_REG_bits.PSA
1552 #define T0SE OPTION_REG_bits.T0SE
1553 #define T0CS OPTION_REG_bits.T0CS
1554 #define INTEDG OPTION_REG_bits.INTEDG
1555 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
1557 // ----- OSCCON bits --------------------
1560 unsigned char SCS:1;
1561 unsigned char LTS:1;
1562 unsigned char HTS:1;
1563 unsigned char OSTS:1;
1564 unsigned char IRCF0:1;
1565 unsigned char IRCF1:1;
1566 unsigned char IRCF2:1;
1570 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
1572 #define SCS OSCCON_bits.SCS
1573 #define LTS OSCCON_bits.LTS
1574 #define HTS OSCCON_bits.HTS
1575 #define OSTS OSCCON_bits.OSTS
1576 #define IRCF0 OSCCON_bits.IRCF0
1577 #define IRCF1 OSCCON_bits.IRCF1
1578 #define IRCF2 OSCCON_bits.IRCF2
1580 // ----- OSCTUNE bits --------------------
1583 unsigned char TUN0:1;
1584 unsigned char TUN1:1;
1585 unsigned char TUN2:1;
1586 unsigned char TUN3:1;
1587 unsigned char TUN4:1;
1593 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
1595 #define TUN0 OSCTUNE_bits.TUN0
1596 #define TUN1 OSCTUNE_bits.TUN1
1597 #define TUN2 OSCTUNE_bits.TUN2
1598 #define TUN3 OSCTUNE_bits.TUN3
1599 #define TUN4 OSCTUNE_bits.TUN4
1601 // ----- PCON bits --------------------
1604 unsigned char NOT_BO:1;
1605 unsigned char NOT_POR:1;
1608 unsigned char SBOREN:1;
1614 unsigned char NOT_BOR:1;
1624 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
1626 #define NOT_BO PCON_bits.NOT_BO
1627 #define NOT_BOR PCON_bits.NOT_BOR
1628 #define NOT_POR PCON_bits.NOT_POR
1629 #define SBOREN PCON_bits.SBOREN
1631 // ----- PIE1 bits --------------------
1634 unsigned char TMR1IE:1;
1635 unsigned char TMR2IE:1;
1636 unsigned char CCP1IE:1;
1637 unsigned char SSPIE:1;
1638 unsigned char TXIE:1;
1639 unsigned char RCIE:1;
1640 unsigned char ADIE:1;
1641 unsigned char EEIE:1;
1644 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
1646 #define TMR1IE PIE1_bits.TMR1IE
1647 #define TMR2IE PIE1_bits.TMR2IE
1648 #define CCP1IE PIE1_bits.CCP1IE
1649 #define SSPIE PIE1_bits.SSPIE
1650 #define TXIE PIE1_bits.TXIE
1651 #define RCIE PIE1_bits.RCIE
1652 #define ADIE PIE1_bits.ADIE
1653 #define EEIE PIE1_bits.EEIE
1655 // ----- PIE2 bits --------------------
1658 unsigned char CCP2IE:1;
1660 unsigned char LVDIE:1;
1662 unsigned char LCDIE:1;
1663 unsigned char C1IE:1;
1664 unsigned char C2IE:1;
1665 unsigned char OSFIE:1;
1668 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
1670 #define CCP2IE PIE2_bits.CCP2IE
1671 #define LVDIE PIE2_bits.LVDIE
1672 #define LCDIE PIE2_bits.LCDIE
1673 #define C1IE PIE2_bits.C1IE
1674 #define C2IE PIE2_bits.C2IE
1675 #define OSFIE PIE2_bits.OSFIE
1677 // ----- PIR1 bits --------------------
1680 unsigned char TMR1IF:1;
1681 unsigned char TMR2IF:1;
1682 unsigned char CCP1IF:1;
1683 unsigned char SSPIF:1;
1684 unsigned char TXIF:1;
1685 unsigned char RCIF:1;
1686 unsigned char ADIF:1;
1687 unsigned char EEIF:1;
1690 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
1692 #define TMR1IF PIR1_bits.TMR1IF
1693 #define TMR2IF PIR1_bits.TMR2IF
1694 #define CCP1IF PIR1_bits.CCP1IF
1695 #define SSPIF PIR1_bits.SSPIF
1696 #define TXIF PIR1_bits.TXIF
1697 #define RCIF PIR1_bits.RCIF
1698 #define ADIF PIR1_bits.ADIF
1699 #define EEIF PIR1_bits.EEIF
1701 // ----- PIR2 bits --------------------
1704 unsigned char CCP2IF:1;
1706 unsigned char LVDIF:1;
1708 unsigned char LCDIF:1;
1709 unsigned char C1IF:1;
1710 unsigned char C2IF:1;
1711 unsigned char OSFIF:1;
1714 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
1716 #define CCP2IF PIR2_bits.CCP2IF
1717 #define LVDIF PIR2_bits.LVDIF
1718 #define LCDIF PIR2_bits.LCDIF
1719 #define C1IF PIR2_bits.C1IF
1720 #define C2IF PIR2_bits.C2IF
1721 #define OSFIF PIR2_bits.OSFIF
1723 // ----- RCSTA bits --------------------
1726 unsigned char RX9D:1;
1727 unsigned char OERR:1;
1728 unsigned char FERR:1;
1729 unsigned char ADDEN:1;
1730 unsigned char CREN:1;
1731 unsigned char SREN:1;
1732 unsigned char RX9:1;
1733 unsigned char SPEN:1;
1736 unsigned char RCD8:1;
1742 unsigned char RC9:1;
1752 unsigned char NOT_RC8:1;
1762 unsigned char RC8_9:1;
1766 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
1768 #define RX9D RCSTA_bits.RX9D
1769 #define RCD8 RCSTA_bits.RCD8
1770 #define OERR RCSTA_bits.OERR
1771 #define FERR RCSTA_bits.FERR
1772 #define ADDEN RCSTA_bits.ADDEN
1773 #define CREN RCSTA_bits.CREN
1774 #define SREN RCSTA_bits.SREN
1775 #define RX9 RCSTA_bits.RX9
1776 #define RC9 RCSTA_bits.RC9
1777 #define NOT_RC8 RCSTA_bits.NOT_RC8
1778 #define RC8_9 RCSTA_bits.RC8_9
1779 #define SPEN RCSTA_bits.SPEN
1781 // ----- SSPCON bits --------------------
1784 unsigned char SSPM0:1;
1785 unsigned char SSPM1:1;
1786 unsigned char SSPM2:1;
1787 unsigned char SSPM3:1;
1788 unsigned char CKP:1;
1789 unsigned char SSPEN:1;
1790 unsigned char SSPOV:1;
1791 unsigned char WCOL:1;
1794 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1796 #define SSPM0 SSPCON_bits.SSPM0
1797 #define SSPM1 SSPCON_bits.SSPM1
1798 #define SSPM2 SSPCON_bits.SSPM2
1799 #define SSPM3 SSPCON_bits.SSPM3
1800 #define CKP SSPCON_bits.CKP
1801 #define SSPEN SSPCON_bits.SSPEN
1802 #define SSPOV SSPCON_bits.SSPOV
1803 #define WCOL SSPCON_bits.WCOL
1805 // ----- SSPSTAT bits --------------------
1814 unsigned char CKE:1;
1815 unsigned char SMP:1;
1820 unsigned char I2C_READ:1;
1821 unsigned char I2C_START:1;
1822 unsigned char I2C_STOP:1;
1823 unsigned char I2C_DATA:1;
1830 unsigned char NOT_W:1;
1833 unsigned char NOT_A:1;
1840 unsigned char NOT_WRITE:1;
1843 unsigned char NOT_ADDRESS:1;
1850 unsigned char R_W:1;
1853 unsigned char D_A:1;
1860 unsigned char READ_WRITE:1;
1863 unsigned char DATA_ADDRESS:1;
1868 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1870 #define BF SSPSTAT_bits.BF
1871 #define UA SSPSTAT_bits.UA
1872 #define R SSPSTAT_bits.R
1873 #define I2C_READ SSPSTAT_bits.I2C_READ
1874 #define NOT_W SSPSTAT_bits.NOT_W
1875 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1876 #define R_W SSPSTAT_bits.R_W
1877 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1878 #define S SSPSTAT_bits.S
1879 #define I2C_START SSPSTAT_bits.I2C_START
1880 #define P SSPSTAT_bits.P
1881 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1882 #define D SSPSTAT_bits.D
1883 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1884 #define NOT_A SSPSTAT_bits.NOT_A
1885 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1886 #define D_A SSPSTAT_bits.D_A
1887 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1888 #define CKE SSPSTAT_bits.CKE
1889 #define SMP SSPSTAT_bits.SMP
1891 // ----- STATUS bits --------------------
1897 unsigned char NOT_PD:1;
1898 unsigned char NOT_TO:1;
1899 unsigned char RP0:1;
1900 unsigned char RP1:1;
1901 unsigned char IRP:1;
1904 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1906 #define C STATUS_bits.C
1907 #define DC STATUS_bits.DC
1908 #define Z STATUS_bits.Z
1909 #define NOT_PD STATUS_bits.NOT_PD
1910 #define NOT_TO STATUS_bits.NOT_TO
1911 #define RP0 STATUS_bits.RP0
1912 #define RP1 STATUS_bits.RP1
1913 #define IRP STATUS_bits.IRP
1915 // ----- T1CON bits --------------------
1918 unsigned char TMR1ON:1;
1919 unsigned char TMR1CS:1;
1920 unsigned char NOT_T1SYNC:1;
1921 unsigned char T1OSCEN:1;
1922 unsigned char T1CKPS0:1;
1923 unsigned char T1CKPS1:1;
1924 unsigned char T1GE:1;
1925 unsigned char T1GINV:1;
1930 unsigned char T1INSYNC:1;
1940 unsigned char T1SYNC:1;
1948 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1950 #define TMR1ON T1CON_bits.TMR1ON
1951 #define TMR1CS T1CON_bits.TMR1CS
1952 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1953 #define T1INSYNC T1CON_bits.T1INSYNC
1954 #define T1SYNC T1CON_bits.T1SYNC
1955 #define T1OSCEN T1CON_bits.T1OSCEN
1956 #define T1CKPS0 T1CON_bits.T1CKPS0
1957 #define T1CKPS1 T1CON_bits.T1CKPS1
1958 #define T1GE T1CON_bits.T1GE
1959 #define T1GINV T1CON_bits.T1GINV
1961 // ----- T2CON bits --------------------
1964 unsigned char T2CKPS0:1;
1965 unsigned char T2CKPS1:1;
1966 unsigned char TMR2ON:1;
1967 unsigned char TOUTPS0:1;
1968 unsigned char TOUTPS1:1;
1969 unsigned char TOUTPS2:1;
1970 unsigned char TOUTPS3:1;
1974 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1976 #define T2CKPS0 T2CON_bits.T2CKPS0
1977 #define T2CKPS1 T2CON_bits.T2CKPS1
1978 #define TMR2ON T2CON_bits.TMR2ON
1979 #define TOUTPS0 T2CON_bits.TOUTPS0
1980 #define TOUTPS1 T2CON_bits.TOUTPS1
1981 #define TOUTPS2 T2CON_bits.TOUTPS2
1982 #define TOUTPS3 T2CON_bits.TOUTPS3
1984 // ----- TXSTA bits --------------------
1987 unsigned char TX9D:1;
1988 unsigned char TRMT:1;
1989 unsigned char BRGH:1;
1991 unsigned char SYNC:1;
1992 unsigned char TXEN:1;
1993 unsigned char TX9:1;
1994 unsigned char CSRC:1;
1997 unsigned char TXD8:1;
2003 unsigned char NOT_TX8:1;
2013 unsigned char TX8_9:1;
2017 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
2019 #define TX9D TXSTA_bits.TX9D
2020 #define TXD8 TXSTA_bits.TXD8
2021 #define TRMT TXSTA_bits.TRMT
2022 #define BRGH TXSTA_bits.BRGH
2023 #define SYNC TXSTA_bits.SYNC
2024 #define TXEN TXSTA_bits.TXEN
2025 #define TX9 TXSTA_bits.TX9
2026 #define NOT_TX8 TXSTA_bits.NOT_TX8
2027 #define TX8_9 TXSTA_bits.TX8_9
2028 #define CSRC TXSTA_bits.CSRC
2030 // ----- VRCON bits --------------------
2033 unsigned char VR0:1;
2034 unsigned char VR1:1;
2035 unsigned char VR2:1;
2036 unsigned char VR3:1;
2038 unsigned char VRR:1;
2040 unsigned char VREN:1;
2043 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
2045 #define VR0 VRCON_bits.VR0
2046 #define VR1 VRCON_bits.VR1
2047 #define VR2 VRCON_bits.VR2
2048 #define VR3 VRCON_bits.VR3
2049 #define VRR VRCON_bits.VRR
2050 #define VREN VRCON_bits.VREN
2052 // ----- WDTCON bits --------------------
2055 unsigned char SWDTEN:1;
2056 unsigned char WDTPS0:1;
2057 unsigned char WDTPS1:1;
2058 unsigned char WDTPS2:1;
2059 unsigned char WDTPS3:1;
2065 unsigned char SWDTE:1;
2075 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
2077 #define SWDTEN WDTCON_bits.SWDTEN
2078 #define SWDTE WDTCON_bits.SWDTE
2079 #define WDTPS0 WDTCON_bits.WDTPS0
2080 #define WDTPS1 WDTCON_bits.WDTPS1
2081 #define WDTPS2 WDTCON_bits.WDTPS2
2082 #define WDTPS3 WDTCON_bits.WDTPS3
2084 // ----- WPU bits --------------------
2087 unsigned char WPU0:1;
2088 unsigned char WPU1:1;
2089 unsigned char WPU2:1;
2090 unsigned char WPU3:1;
2091 unsigned char WPU4:1;
2092 unsigned char WPU5:1;
2093 unsigned char WPU6:1;
2094 unsigned char WPU7:1;
2097 extern volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits;
2099 #define WPU0 WPU_bits.WPU0
2100 #define WPU1 WPU_bits.WPU1
2101 #define WPU2 WPU_bits.WPU2
2102 #define WPU3 WPU_bits.WPU3
2103 #define WPU4 WPU_bits.WPU4
2104 #define WPU5 WPU_bits.WPU5
2105 #define WPU6 WPU_bits.WPU6
2106 #define WPU7 WPU_bits.WPU7
2108 // ----- WPUB bits --------------------
2111 unsigned char WPUB0:1;
2112 unsigned char WPUB1:1;
2113 unsigned char WPUB2:1;
2114 unsigned char WPUB3:1;
2115 unsigned char WPUB4:1;
2116 unsigned char WPUB5:1;
2117 unsigned char WPUB6:1;
2118 unsigned char WPUB7:1;
2121 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
2123 #define WPUB0 WPUB_bits.WPUB0
2124 #define WPUB1 WPUB_bits.WPUB1
2125 #define WPUB2 WPUB_bits.WPUB2
2126 #define WPUB3 WPUB_bits.WPUB3
2127 #define WPUB4 WPUB_bits.WPUB4
2128 #define WPUB5 WPUB_bits.WPUB5
2129 #define WPUB6 WPUB_bits.WPUB6
2130 #define WPUB7 WPUB_bits.WPUB7