2 // Register Declarations for Microchip 16F887 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define OSCCON_ADDR 0x008F
70 #define OSCTUNE_ADDR 0x0090
71 #define SSPCON2_ADDR 0x0091
72 #define PR2_ADDR 0x0092
73 #define SSPADD_ADDR 0x0093
74 #define SSPSTAT_ADDR 0x0094
75 #define WPUB_ADDR 0x0095
76 #define IOCB_ADDR 0x0096
77 #define VRCON_ADDR 0x0097
78 #define TXSTA_ADDR 0x0098
79 #define SPBRG_ADDR 0x0099
80 #define SPBRGH_ADDR 0x009A
81 #define PWM1CON_ADDR 0x009B
82 #define ECCPAS_ADDR 0x009C
83 #define PSTRCON_ADDR 0x009D
84 #define ADRESL_ADDR 0x009E
85 #define ADCON1_ADDR 0x009F
86 #define WDTCON_ADDR 0x0105
87 #define CM1CON0_ADDR 0x0107
88 #define CM2CON0_ADDR 0x0108
89 #define CM2CON1_ADDR 0x0109
90 #define EEDATA_ADDR 0x010C
91 #define EEADR_ADDR 0x010D
92 #define EEDATH_ADDR 0x010E
93 #define EEADRH_ADDR 0x010F
94 #define SRCON_ADDR 0x0185
95 #define BAUDCTL_ADDR 0x0187
96 #define ANSEL_ADDR 0x0188
97 #define ANSELH_ADDR 0x0189
98 #define EECON1_ADDR 0x018C
99 #define EECON2_ADDR 0x018D
102 // Memory organization.
108 // P16F887.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
111 // This header file defines configurations, registers, and other useful bits of
112 // information for the PIC16F887 microcontroller. These names are taken to match
113 // the data sheets as closely as possible.
115 // Note that the processor must be selected before this file is
116 // included. The processor may be selected the following ways:
118 // 1. Command line switch:
119 // C:\ MPASM MYFILE.ASM /PIC16F887
120 // 2. LIST directive in the source file
122 // 3. Processor Type entry in the MPASM full-screen interface
124 //==========================================================================
128 //==========================================================================
130 //1.00 11/18/05 Original
132 //==========================================================================
136 //==========================================================================
139 // MESSG "Processor-header file mismatch. Verify selected processor."
142 //==========================================================================
144 // Register Definitions
146 //==========================================================================
151 //----- Register Files------------------------------------------------------
153 extern __sfr __at (INDF_ADDR) INDF;
154 extern __sfr __at (TMR0_ADDR) TMR0;
155 extern __sfr __at (PCL_ADDR) PCL;
156 extern __sfr __at (STATUS_ADDR) STATUS;
157 extern __sfr __at (FSR_ADDR) FSR;
158 extern __sfr __at (PORTA_ADDR) PORTA;
159 extern __sfr __at (PORTB_ADDR) PORTB;
160 extern __sfr __at (PORTC_ADDR) PORTC;
161 extern __sfr __at (PORTD_ADDR) PORTD;
162 extern __sfr __at (PORTE_ADDR) PORTE;
163 extern __sfr __at (PCLATH_ADDR) PCLATH;
164 extern __sfr __at (INTCON_ADDR) INTCON;
165 extern __sfr __at (PIR1_ADDR) PIR1;
166 extern __sfr __at (PIR2_ADDR) PIR2;
167 extern __sfr __at (TMR1L_ADDR) TMR1L;
168 extern __sfr __at (TMR1H_ADDR) TMR1H;
169 extern __sfr __at (T1CON_ADDR) T1CON;
170 extern __sfr __at (TMR2_ADDR) TMR2;
171 extern __sfr __at (T2CON_ADDR) T2CON;
172 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
173 extern __sfr __at (SSPCON_ADDR) SSPCON;
174 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
175 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
176 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
177 extern __sfr __at (RCSTA_ADDR) RCSTA;
178 extern __sfr __at (TXREG_ADDR) TXREG;
179 extern __sfr __at (RCREG_ADDR) RCREG;
180 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
181 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
182 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
183 extern __sfr __at (ADRESH_ADDR) ADRESH;
184 extern __sfr __at (ADCON0_ADDR) ADCON0;
186 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
188 extern __sfr __at (TRISA_ADDR) TRISA;
189 extern __sfr __at (TRISB_ADDR) TRISB;
190 extern __sfr __at (TRISC_ADDR) TRISC;
191 extern __sfr __at (TRISD_ADDR) TRISD;
192 extern __sfr __at (TRISE_ADDR) TRISE;
194 extern __sfr __at (PIE1_ADDR) PIE1;
195 extern __sfr __at (PIE2_ADDR) PIE2;
196 extern __sfr __at (PCON_ADDR) PCON;
197 extern __sfr __at (OSCCON_ADDR) OSCCON;
198 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
199 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
200 extern __sfr __at (PR2_ADDR) PR2;
201 extern __sfr __at (SSPADD_ADDR) SSPADD;
202 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
203 extern __sfr __at (WPUB_ADDR) WPUB;
204 extern __sfr __at (IOCB_ADDR) IOCB;
205 extern __sfr __at (VRCON_ADDR) VRCON;
206 extern __sfr __at (TXSTA_ADDR) TXSTA;
207 extern __sfr __at (SPBRG_ADDR) SPBRG;
208 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
209 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
210 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
211 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
212 extern __sfr __at (ADRESL_ADDR) ADRESL;
213 extern __sfr __at (ADCON1_ADDR) ADCON1;
215 extern __sfr __at (WDTCON_ADDR) WDTCON;
217 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
218 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
219 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
221 extern __sfr __at (EEDATA_ADDR) EEDATA;
222 extern __sfr __at (EEADR_ADDR) EEADR;
223 extern __sfr __at (EEDATH_ADDR) EEDATH;
224 extern __sfr __at (EEADRH_ADDR) EEADRH;
226 extern __sfr __at (SRCON_ADDR) SRCON;
228 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
229 extern __sfr __at (ANSEL_ADDR) ANSEL;
230 extern __sfr __at (ANSELH_ADDR) ANSELH;
232 extern __sfr __at (EECON1_ADDR) EECON1;
233 extern __sfr __at (EECON2_ADDR) EECON2;
235 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
236 //----- STATUS Bits --------------------------------------------------------
239 //----- INTCON Bits --------------------------------------------------------
242 //----- PIR1 Bits ----------------------------------------------------------
245 //----- PIR2 Bits ----------------------------------------------------------
248 //----- T1CON Bits ---------------------------------------------------------
251 //----- T2CON Bits ---------------------------------------------------------
254 //----- SSPCON Bits --------------------------------------------------------
257 //----- CCP1CON Bits -------------------------------------------------------
260 //----- RCSTA Bits ---------------------------------------------------------
263 //----- CCP2CON Bits -------------------------------------------------------
266 //----- ADCON0 Bits --------------------------------------------------------
269 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
270 //----- OPTION_REG Bits -----------------------------------------------------
273 //----- PIE1 Bits ----------------------------------------------------------
276 //----- PIE2 Bits ----------------------------------------------------------
279 //----- PCON Bits ----------------------------------------------------------
282 //----- OSCCON Bits --------------------------------------------------------
285 //----- OSCTUNE Bits -------------------------------------------------------
288 //----- SSPCON2 Bits --------------------------------------------------------
291 //----- SSPSTAT Bits -------------------------------------------------------
294 //----- WPUB Bits ----------------------------------------------------------
297 //----- IOCB Bits ----------------------------------------------------------
300 //----- VRCON Bits ---------------------------------------------------------
303 //----- TXSTA Bits ---------------------------------------------------------
306 //----- SPBRG Bits -------------------------------------------------------
309 //----- SPBRGH Bits -------------------------------------------------------
312 //----- PWM1CON Bits -------------------------------------------------------
315 //----- ECCPAS Bits --------------------------------------------------------
318 //----- PSTRCON -------------------------------------------------------------
321 //----- ADCON1 -------------------------------------------------------------
324 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
325 //----- WDTCON Bits --------------------------------------------------------
328 //----- CM1CON0 Bits -------------------------------------------------------
332 //----- CM2CON0 Bits -------------------------------------------------------
336 //----- CM2CON1 Bits -------------------------------------------------------
340 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
341 //----- SRCON ---------------------------------------------------------------
345 //----- BAUDCTL Bits -------------------------------------------------------
350 //----- ANSEL --------------------------------------------------------------
353 //----- ANSELH -------------------------------------------------------------
356 //----- EECON1 Bits --------------------------------------------------------
360 //==========================================================================
364 //==========================================================================
367 // __BADRAM H'18E'-H'18F'
369 //==========================================================================
371 // Configuration Bits
373 //==========================================================================
374 #define _CONFIG1 0x2007
375 #define _CONFIG2 0x2008
377 //----- Configuration Word1 ------------------------------------------------
379 #define _LVP_ON 0x3FFF
380 #define _LVP_OFF 0x2FFF
381 #define _FCMEN_ON 0x3FFF
382 #define _FCMEN_OFF 0x37FF
383 #define _IESO_ON 0x3FFF
384 #define _IESO_OFF 0x3BFF
385 #define _BOR_ON 0x3FFF
386 #define _BOR_NSLEEP 0x3EFF
387 #define _BOR_SBODEN 0x3DFF
388 #define _BOR_OFF 0x3CFF
389 #define _CPD_ON 0x3F7F
390 #define _CPD_OFF 0x3FFF
391 #define _CP_ON 0x3FBF
392 #define _CP_OFF 0x3FFF
393 #define _MCLRE_ON 0x3FFF
394 #define _MCLRE_OFF 0x3FDF
395 #define _PWRTE_ON 0x3FEF
396 #define _PWRTE_OFF 0x3FFF
397 #define _WDT_ON 0x3FFF
398 #define _WDT_OFF 0x3FF7
399 #define _LP_OSC 0x3FF8
400 #define _XT_OSC 0x3FF9
401 #define _HS_OSC 0x3FFA
402 #define _EC_OSC 0x3FFB
403 #define _INTRC_OSC_NOCLKOUT 0x3FFC
404 #define _INTRC_OSC_CLKOUT 0x3FFD
405 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
406 #define _EXTRC_OSC_CLKOUT 0x3FFF
407 #define _INTOSCIO 0x3FFC
408 #define _INTOSC 0x3FFD
409 #define _EXTRCIO 0x3FFE
410 #define _EXTRC 0x3FFF
412 //----- Configuration Word2 ------------------------------------------------
414 #define _WRT_OFF 0x3FFF // No prog memmory write protection
415 #define _WRT_256 0x3DFF // First 256 prog memmory write protected
416 #define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected
417 #define _WRT_HALF 0x39FF // First half memmory write protected
419 #define _BOR21V 0x3EFF
420 #define _BOR40V 0x3FFF
424 // ----- ADCON0 bits --------------------
427 unsigned char ADON:1;
429 unsigned char CHS0:1;
430 unsigned char CHS1:1;
431 unsigned char CHS2:1;
432 unsigned char CHS3:1;
433 unsigned char ADCS0:1;
434 unsigned char ADCS1:1;
438 unsigned char NOT_DONE:1;
448 unsigned char GO_DONE:1;
457 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
459 #define ADON ADCON0_bits.ADON
460 #define GO ADCON0_bits.GO
461 #define NOT_DONE ADCON0_bits.NOT_DONE
462 #define GO_DONE ADCON0_bits.GO_DONE
463 #define CHS0 ADCON0_bits.CHS0
464 #define CHS1 ADCON0_bits.CHS1
465 #define CHS2 ADCON0_bits.CHS2
466 #define CHS3 ADCON0_bits.CHS3
467 #define ADCS0 ADCON0_bits.ADCS0
468 #define ADCS1 ADCON0_bits.ADCS1
470 // ----- ADCON1 bits --------------------
477 unsigned char VCFG1:1;
478 unsigned char VCFG0:1;
480 unsigned char ADFM:1;
483 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
485 #define VCFG1 ADCON1_bits.VCFG1
486 #define VCFG0 ADCON1_bits.VCFG0
487 #define ADFM ADCON1_bits.ADFM
489 // ----- ANSEL bits --------------------
492 unsigned char ANS0:1;
493 unsigned char ANS1:1;
494 unsigned char ANS2:1;
495 unsigned char ANS3:1;
496 unsigned char ANS4:1;
497 unsigned char ANS5:1;
498 unsigned char ANS6:1;
499 unsigned char ANS7:1;
502 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
504 #define ANS0 ANSEL_bits.ANS0
505 #define ANS1 ANSEL_bits.ANS1
506 #define ANS2 ANSEL_bits.ANS2
507 #define ANS3 ANSEL_bits.ANS3
508 #define ANS4 ANSEL_bits.ANS4
509 #define ANS5 ANSEL_bits.ANS5
510 #define ANS6 ANSEL_bits.ANS6
511 #define ANS7 ANSEL_bits.ANS7
513 // ----- ANSELH bits --------------------
516 unsigned char ANS8:1;
517 unsigned char ANS9:1;
518 unsigned char ANS10:1;
519 unsigned char ANS11:1;
520 unsigned char ANS12:1;
521 unsigned char ANS13:1;
526 extern volatile __ANSELH_bits_t __at(ANSELH_ADDR) ANSELH_bits;
528 #define ANS8 ANSELH_bits.ANS8
529 #define ANS9 ANSELH_bits.ANS9
530 #define ANS10 ANSELH_bits.ANS10
531 #define ANS11 ANSELH_bits.ANS11
532 #define ANS12 ANSELH_bits.ANS12
533 #define ANS13 ANSELH_bits.ANS13
535 // ----- BAUDCTL bits --------------------
538 unsigned char ABDEN:1;
541 unsigned char BRG16:1;
542 unsigned char SCKP:1;
544 unsigned char RCIDL:1;
545 unsigned char ABDOVF:1;
548 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
550 #define ABDEN BAUDCTL_bits.ABDEN
551 #define WUE BAUDCTL_bits.WUE
552 #define BRG16 BAUDCTL_bits.BRG16
553 #define SCKP BAUDCTL_bits.SCKP
554 #define RCIDL BAUDCTL_bits.RCIDL
555 #define ABDOVF BAUDCTL_bits.ABDOVF
557 // ----- CCP1CON bits --------------------
560 unsigned char CCP1M0:1;
561 unsigned char CCP1M1:1;
562 unsigned char CCP1M2:1;
563 unsigned char CCP1M3:1;
564 unsigned char DC1B0:1;
565 unsigned char DC1B1:1;
566 unsigned char P1M0:1;
567 unsigned char P1M1:1;
574 unsigned char CCP1Y:1;
575 unsigned char CCP1X:1;
580 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
582 #define CCP1M0 CCP1CON_bits.CCP1M0
583 #define CCP1M1 CCP1CON_bits.CCP1M1
584 #define CCP1M2 CCP1CON_bits.CCP1M2
585 #define CCP1M3 CCP1CON_bits.CCP1M3
586 #define DC1B0 CCP1CON_bits.DC1B0
587 #define CCP1Y CCP1CON_bits.CCP1Y
588 #define DC1B1 CCP1CON_bits.DC1B1
589 #define CCP1X CCP1CON_bits.CCP1X
590 #define P1M0 CCP1CON_bits.P1M0
591 #define P1M1 CCP1CON_bits.P1M1
593 // ----- CCP2CON bits --------------------
596 unsigned char CCP2M0:1;
597 unsigned char CCP2M1:1;
598 unsigned char CCP2M2:1;
599 unsigned char CCP2M3:1;
600 unsigned char CCP2Y:1;
601 unsigned char CCP2X:1;
610 unsigned char DC2B0:1;
611 unsigned char DC2B1:1;
616 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
618 #define CCP2M0 CCP2CON_bits.CCP2M0
619 #define CCP2M1 CCP2CON_bits.CCP2M1
620 #define CCP2M2 CCP2CON_bits.CCP2M2
621 #define CCP2M3 CCP2CON_bits.CCP2M3
622 #define CCP2Y CCP2CON_bits.CCP2Y
623 #define DC2B0 CCP2CON_bits.DC2B0
624 #define CCP2X CCP2CON_bits.CCP2X
625 #define DC2B1 CCP2CON_bits.DC2B1
627 // ----- CM1CON0 bits --------------------
630 unsigned char C1CH0:1;
631 unsigned char C1CH1:1;
634 unsigned char C1POL:1;
635 unsigned char C1OE:1;
636 unsigned char C1OUT:1;
637 unsigned char C1ON:1;
640 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
642 #define C1CH0 CM1CON0_bits.C1CH0
643 #define C1CH1 CM1CON0_bits.C1CH1
644 #define C1R CM1CON0_bits.C1R
645 #define C1POL CM1CON0_bits.C1POL
646 #define C1OE CM1CON0_bits.C1OE
647 #define C1OUT CM1CON0_bits.C1OUT
648 #define C1ON CM1CON0_bits.C1ON
650 // ----- CM2CON0 bits --------------------
653 unsigned char C2CH0:1;
654 unsigned char C2CH1:1;
657 unsigned char C2POL:1;
658 unsigned char C2OE:1;
659 unsigned char C2OUT:1;
660 unsigned char C2ON:1;
663 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
665 #define C2CH0 CM2CON0_bits.C2CH0
666 #define C2CH1 CM2CON0_bits.C2CH1
667 #define C2R CM2CON0_bits.C2R
668 #define C2POL CM2CON0_bits.C2POL
669 #define C2OE CM2CON0_bits.C2OE
670 #define C2OUT CM2CON0_bits.C2OUT
671 #define C2ON CM2CON0_bits.C2ON
673 // ----- CM2CON1 bits --------------------
676 unsigned char C2SYNC:1;
677 unsigned char T1GSS:1;
680 unsigned char C2RSEL:1;
681 unsigned char C1RSEL:1;
682 unsigned char MC2OUT:1;
683 unsigned char MC1OUT:1;
686 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
688 #define C2SYNC CM2CON1_bits.C2SYNC
689 #define T1GSS CM2CON1_bits.T1GSS
690 #define C2RSEL CM2CON1_bits.C2RSEL
691 #define C1RSEL CM2CON1_bits.C1RSEL
692 #define MC2OUT CM2CON1_bits.MC2OUT
693 #define MC1OUT CM2CON1_bits.MC1OUT
695 // ----- ECCPAS bits --------------------
698 unsigned char PSSBD0:1;
699 unsigned char PSSBD1:1;
700 unsigned char PSSAC0:1;
701 unsigned char PSSAC1:1;
702 unsigned char ECCPAS0:1;
703 unsigned char ECCPAS1:1;
704 unsigned char ECCPAS2:1;
705 unsigned char ECCPASE:1;
708 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
710 #define PSSBD0 ECCPAS_bits.PSSBD0
711 #define PSSBD1 ECCPAS_bits.PSSBD1
712 #define PSSAC0 ECCPAS_bits.PSSAC0
713 #define PSSAC1 ECCPAS_bits.PSSAC1
714 #define ECCPAS0 ECCPAS_bits.ECCPAS0
715 #define ECCPAS1 ECCPAS_bits.ECCPAS1
716 #define ECCPAS2 ECCPAS_bits.ECCPAS2
717 #define ECCPASE ECCPAS_bits.ECCPASE
719 // ----- EECON1 bits --------------------
724 unsigned char WREN:1;
725 unsigned char WRERR:1;
729 unsigned char EEPGD:1;
732 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
734 #define RD EECON1_bits.RD
735 #define WR EECON1_bits.WR
736 #define WREN EECON1_bits.WREN
737 #define WRERR EECON1_bits.WRERR
738 #define EEPGD EECON1_bits.EEPGD
740 // ----- INTCON bits --------------------
743 unsigned char RBIF:1;
744 unsigned char INTF:1;
745 unsigned char T0IF:1;
746 unsigned char RBIE:1;
747 unsigned char INTE:1;
748 unsigned char T0IE:1;
749 unsigned char PEIE:1;
755 unsigned char TMR0IF:1;
758 unsigned char TMR0IE:1;
763 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
765 #define RBIF INTCON_bits.RBIF
766 #define INTF INTCON_bits.INTF
767 #define T0IF INTCON_bits.T0IF
768 #define TMR0IF INTCON_bits.TMR0IF
769 #define RBIE INTCON_bits.RBIE
770 #define INTE INTCON_bits.INTE
771 #define T0IE INTCON_bits.T0IE
772 #define TMR0IE INTCON_bits.TMR0IE
773 #define PEIE INTCON_bits.PEIE
774 #define GIE INTCON_bits.GIE
776 // ----- IOCB bits --------------------
779 unsigned char IOCB0:1;
780 unsigned char IOCB1:1;
781 unsigned char IOCB2:1;
782 unsigned char IOCB3:1;
783 unsigned char IOCB4:1;
784 unsigned char IOCB5:1;
785 unsigned char IOCB6:1;
786 unsigned char IOCB7:1;
789 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
791 #define IOCB0 IOCB_bits.IOCB0
792 #define IOCB1 IOCB_bits.IOCB1
793 #define IOCB2 IOCB_bits.IOCB2
794 #define IOCB3 IOCB_bits.IOCB3
795 #define IOCB4 IOCB_bits.IOCB4
796 #define IOCB5 IOCB_bits.IOCB5
797 #define IOCB6 IOCB_bits.IOCB6
798 #define IOCB7 IOCB_bits.IOCB7
800 // ----- OPTION_REG bits --------------------
807 unsigned char T0SE:1;
808 unsigned char T0CS:1;
809 unsigned char INTEDG:1;
810 unsigned char NOT_RBPU:1;
812 } __OPTION_REG_bits_t;
813 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
815 #define PS0 OPTION_REG_bits.PS0
816 #define PS1 OPTION_REG_bits.PS1
817 #define PS2 OPTION_REG_bits.PS2
818 #define PSA OPTION_REG_bits.PSA
819 #define T0SE OPTION_REG_bits.T0SE
820 #define T0CS OPTION_REG_bits.T0CS
821 #define INTEDG OPTION_REG_bits.INTEDG
822 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
824 // ----- OSCCON bits --------------------
830 unsigned char OSTS:1;
831 unsigned char IRCF0:1;
832 unsigned char IRCF1:1;
833 unsigned char IRCF2:1;
837 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
839 #define SCS OSCCON_bits.SCS
840 #define LTS OSCCON_bits.LTS
841 #define HTS OSCCON_bits.HTS
842 #define OSTS OSCCON_bits.OSTS
843 #define IRCF0 OSCCON_bits.IRCF0
844 #define IRCF1 OSCCON_bits.IRCF1
845 #define IRCF2 OSCCON_bits.IRCF2
847 // ----- OSCTUNE bits --------------------
850 unsigned char TUN0:1;
851 unsigned char TUN1:1;
852 unsigned char TUN2:1;
853 unsigned char TUN3:1;
854 unsigned char TUN4:1;
860 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
862 #define TUN0 OSCTUNE_bits.TUN0
863 #define TUN1 OSCTUNE_bits.TUN1
864 #define TUN2 OSCTUNE_bits.TUN2
865 #define TUN3 OSCTUNE_bits.TUN3
866 #define TUN4 OSCTUNE_bits.TUN4
868 // ----- PCON bits --------------------
871 unsigned char NOT_BO:1;
872 unsigned char NOT_POR:1;
875 unsigned char SBOREN:1;
876 unsigned char ULPWUE:1;
881 unsigned char NOT_BOR:1;
891 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
893 #define NOT_BO PCON_bits.NOT_BO
894 #define NOT_BOR PCON_bits.NOT_BOR
895 #define NOT_POR PCON_bits.NOT_POR
896 #define SBOREN PCON_bits.SBOREN
897 #define ULPWUE PCON_bits.ULPWUE
899 // ----- PIE1 bits --------------------
902 unsigned char TMR1IE:1;
903 unsigned char TMR2IE:1;
904 unsigned char CCP1IE:1;
905 unsigned char SSPIE:1;
906 unsigned char TXIE:1;
907 unsigned char RCIE:1;
908 unsigned char ADIE:1;
912 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
914 #define TMR1IE PIE1_bits.TMR1IE
915 #define TMR2IE PIE1_bits.TMR2IE
916 #define CCP1IE PIE1_bits.CCP1IE
917 #define SSPIE PIE1_bits.SSPIE
918 #define TXIE PIE1_bits.TXIE
919 #define RCIE PIE1_bits.RCIE
920 #define ADIE PIE1_bits.ADIE
922 // ----- PIE2 bits --------------------
925 unsigned char CCP2IE:1;
927 unsigned char ULPWUIE:1;
928 unsigned char BCLIE:1;
929 unsigned char EEIE:1;
930 unsigned char C1IE:1;
931 unsigned char C2IE:1;
932 unsigned char OSFIE:1;
935 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
937 #define CCP2IE PIE2_bits.CCP2IE
938 #define ULPWUIE PIE2_bits.ULPWUIE
939 #define BCLIE PIE2_bits.BCLIE
940 #define EEIE PIE2_bits.EEIE
941 #define C1IE PIE2_bits.C1IE
942 #define C2IE PIE2_bits.C2IE
943 #define OSFIE PIE2_bits.OSFIE
945 // ----- PIR1 bits --------------------
948 unsigned char TMR1IF:1;
949 unsigned char TMR2IF:1;
950 unsigned char CCP1IF:1;
951 unsigned char SSPIF:1;
952 unsigned char TXIF:1;
953 unsigned char RCIF:1;
954 unsigned char ADIF:1;
958 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
960 #define TMR1IF PIR1_bits.TMR1IF
961 #define TMR2IF PIR1_bits.TMR2IF
962 #define CCP1IF PIR1_bits.CCP1IF
963 #define SSPIF PIR1_bits.SSPIF
964 #define TXIF PIR1_bits.TXIF
965 #define RCIF PIR1_bits.RCIF
966 #define ADIF PIR1_bits.ADIF
968 // ----- PIR2 bits --------------------
971 unsigned char CCP2IF:1;
973 unsigned char ULPWUIF:1;
974 unsigned char BCLIF:1;
975 unsigned char EEIF:1;
976 unsigned char C1IF:1;
977 unsigned char C2IF:1;
978 unsigned char OSPIF:1;
981 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
983 #define CCP2IF PIR2_bits.CCP2IF
984 #define ULPWUIF PIR2_bits.ULPWUIF
985 #define BCLIF PIR2_bits.BCLIF
986 #define EEIF PIR2_bits.EEIF
987 #define C1IF PIR2_bits.C1IF
988 #define C2IF PIR2_bits.C2IF
989 #define OSPIF PIR2_bits.OSPIF
991 // ----- PORTA bits --------------------
1004 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
1006 #define RA0 PORTA_bits.RA0
1007 #define RA1 PORTA_bits.RA1
1008 #define RA2 PORTA_bits.RA2
1009 #define RA3 PORTA_bits.RA3
1010 #define RA4 PORTA_bits.RA4
1011 #define RA5 PORTA_bits.RA5
1013 // ----- PORTB bits --------------------
1016 unsigned char RB0:1;
1017 unsigned char RB1:1;
1018 unsigned char RB2:1;
1019 unsigned char RB3:1;
1020 unsigned char RB4:1;
1021 unsigned char RB5:1;
1022 unsigned char RB6:1;
1023 unsigned char RB7:1;
1026 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
1028 #define RB0 PORTB_bits.RB0
1029 #define RB1 PORTB_bits.RB1
1030 #define RB2 PORTB_bits.RB2
1031 #define RB3 PORTB_bits.RB3
1032 #define RB4 PORTB_bits.RB4
1033 #define RB5 PORTB_bits.RB5
1034 #define RB6 PORTB_bits.RB6
1035 #define RB7 PORTB_bits.RB7
1037 // ----- PORTC bits --------------------
1040 unsigned char RC0:1;
1041 unsigned char RC1:1;
1042 unsigned char RC2:1;
1043 unsigned char RC3:1;
1044 unsigned char RC4:1;
1045 unsigned char RC5:1;
1046 unsigned char RC6:1;
1047 unsigned char RC7:1;
1050 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
1052 #define RC0 PORTC_bits.RC0
1053 #define RC1 PORTC_bits.RC1
1054 #define RC2 PORTC_bits.RC2
1055 #define RC3 PORTC_bits.RC3
1056 #define RC4 PORTC_bits.RC4
1057 #define RC5 PORTC_bits.RC5
1058 #define RC6 PORTC_bits.RC6
1059 #define RC7 PORTC_bits.RC7
1061 // ----- PORTD bits --------------------
1064 unsigned char RD0:1;
1065 unsigned char RD1:1;
1066 unsigned char RD2:1;
1067 unsigned char RD3:1;
1068 unsigned char RD4:1;
1069 unsigned char RD5:1;
1070 unsigned char RD6:1;
1071 unsigned char RD7:1;
1074 extern volatile __PORTD_bits_t __at(PORTD_ADDR) PORTD_bits;
1076 #define RD0 PORTD_bits.RD0
1077 #define RD1 PORTD_bits.RD1
1078 #define RD2 PORTD_bits.RD2
1079 #define RD3 PORTD_bits.RD3
1080 #define RD4 PORTD_bits.RD4
1081 #define RD5 PORTD_bits.RD5
1082 #define RD6 PORTD_bits.RD6
1083 #define RD7 PORTD_bits.RD7
1085 // ----- PORTE bits --------------------
1088 unsigned char RE0:1;
1089 unsigned char RE1:1;
1090 unsigned char RE2:1;
1098 extern volatile __PORTE_bits_t __at(PORTE_ADDR) PORTE_bits;
1100 #define RE0 PORTE_bits.RE0
1101 #define RE1 PORTE_bits.RE1
1102 #define RE2 PORTE_bits.RE2
1104 // ----- PSTRCON bits --------------------
1107 unsigned char STRA:1;
1108 unsigned char STRB:1;
1109 unsigned char STRC:1;
1110 unsigned char STRD:1;
1111 unsigned char STRSYNC:1;
1117 extern volatile __PSTRCON_bits_t __at(PSTRCON_ADDR) PSTRCON_bits;
1119 #define STRA PSTRCON_bits.STRA
1120 #define STRB PSTRCON_bits.STRB
1121 #define STRC PSTRCON_bits.STRC
1122 #define STRD PSTRCON_bits.STRD
1123 #define STRSYNC PSTRCON_bits.STRSYNC
1125 // ----- PWM1CON bits --------------------
1128 unsigned char PDC0:1;
1129 unsigned char PDC1:1;
1130 unsigned char PDC2:1;
1131 unsigned char PDC3:1;
1132 unsigned char PDC4:1;
1133 unsigned char PDC5:1;
1134 unsigned char PDC6:1;
1135 unsigned char PRSEN:1;
1138 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
1140 #define PDC0 PWM1CON_bits.PDC0
1141 #define PDC1 PWM1CON_bits.PDC1
1142 #define PDC2 PWM1CON_bits.PDC2
1143 #define PDC3 PWM1CON_bits.PDC3
1144 #define PDC4 PWM1CON_bits.PDC4
1145 #define PDC5 PWM1CON_bits.PDC5
1146 #define PDC6 PWM1CON_bits.PDC6
1147 #define PRSEN PWM1CON_bits.PRSEN
1149 // ----- RCSTA bits --------------------
1152 unsigned char RX9D:1;
1153 unsigned char OERR:1;
1154 unsigned char FERR:1;
1155 unsigned char ADDEN:1;
1156 unsigned char CREN:1;
1157 unsigned char SREN:1;
1158 unsigned char RX9:1;
1159 unsigned char SPEN:1;
1162 unsigned char RCD8:1;
1168 unsigned char RC9:1;
1178 unsigned char NOT_RC8:1;
1188 unsigned char RC8_9:1;
1192 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
1194 #define RX9D RCSTA_bits.RX9D
1195 #define RCD8 RCSTA_bits.RCD8
1196 #define OERR RCSTA_bits.OERR
1197 #define FERR RCSTA_bits.FERR
1198 #define ADDEN RCSTA_bits.ADDEN
1199 #define CREN RCSTA_bits.CREN
1200 #define SREN RCSTA_bits.SREN
1201 #define RX9 RCSTA_bits.RX9
1202 #define RC9 RCSTA_bits.RC9
1203 #define NOT_RC8 RCSTA_bits.NOT_RC8
1204 #define RC8_9 RCSTA_bits.RC8_9
1205 #define SPEN RCSTA_bits.SPEN
1207 // ----- SPBRG bits --------------------
1210 unsigned char BRG0:1;
1211 unsigned char BRG1:1;
1212 unsigned char BRG2:1;
1213 unsigned char BRG3:1;
1214 unsigned char BRG4:1;
1215 unsigned char BRG5:1;
1216 unsigned char BRG6:1;
1217 unsigned char BRG7:1;
1220 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
1222 #define BRG0 SPBRG_bits.BRG0
1223 #define BRG1 SPBRG_bits.BRG1
1224 #define BRG2 SPBRG_bits.BRG2
1225 #define BRG3 SPBRG_bits.BRG3
1226 #define BRG4 SPBRG_bits.BRG4
1227 #define BRG5 SPBRG_bits.BRG5
1228 #define BRG6 SPBRG_bits.BRG6
1229 #define BRG7 SPBRG_bits.BRG7
1231 // ----- SPBRGH bits --------------------
1234 unsigned char BRG8:1;
1235 unsigned char BRG9:1;
1236 unsigned char BRG10:1;
1237 unsigned char BRG11:1;
1238 unsigned char BRG12:1;
1239 unsigned char BRG13:1;
1240 unsigned char BRG14:1;
1241 unsigned char BRG15:1;
1244 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
1246 #define BRG8 SPBRGH_bits.BRG8
1247 #define BRG9 SPBRGH_bits.BRG9
1248 #define BRG10 SPBRGH_bits.BRG10
1249 #define BRG11 SPBRGH_bits.BRG11
1250 #define BRG12 SPBRGH_bits.BRG12
1251 #define BRG13 SPBRGH_bits.BRG13
1252 #define BRG14 SPBRGH_bits.BRG14
1253 #define BRG15 SPBRGH_bits.BRG15
1255 // ----- SRCON bits --------------------
1258 unsigned char FVREN:1;
1260 unsigned char PULSR:1;
1261 unsigned char PULSS:1;
1262 unsigned char C2REN:1;
1263 unsigned char C1SEN:1;
1264 unsigned char SR0:1;
1265 unsigned char SR1:1;
1268 extern volatile __SRCON_bits_t __at(SRCON_ADDR) SRCON_bits;
1270 #define FVREN SRCON_bits.FVREN
1271 #define PULSR SRCON_bits.PULSR
1272 #define PULSS SRCON_bits.PULSS
1273 #define C2REN SRCON_bits.C2REN
1274 #define C1SEN SRCON_bits.C1SEN
1275 #define SR0 SRCON_bits.SR0
1276 #define SR1 SRCON_bits.SR1
1278 // ----- SSPCON bits --------------------
1281 unsigned char SSPM0:1;
1282 unsigned char SSPM1:1;
1283 unsigned char SSPM2:1;
1284 unsigned char SSPM3:1;
1285 unsigned char CKP:1;
1286 unsigned char SSPEN:1;
1287 unsigned char SSPOV:1;
1288 unsigned char WCOL:1;
1291 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1293 #define SSPM0 SSPCON_bits.SSPM0
1294 #define SSPM1 SSPCON_bits.SSPM1
1295 #define SSPM2 SSPCON_bits.SSPM2
1296 #define SSPM3 SSPCON_bits.SSPM3
1297 #define CKP SSPCON_bits.CKP
1298 #define SSPEN SSPCON_bits.SSPEN
1299 #define SSPOV SSPCON_bits.SSPOV
1300 #define WCOL SSPCON_bits.WCOL
1302 // ----- SSPCON2 bits --------------------
1305 unsigned char SEN:1;
1306 unsigned char RSEN:1;
1307 unsigned char PEN:1;
1308 unsigned char RCEN:1;
1309 unsigned char ACKEN:1;
1310 unsigned char ACKDT:1;
1311 unsigned char ACKSTAT:1;
1312 unsigned char GCEN:1;
1315 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
1317 #define SEN SSPCON2_bits.SEN
1318 #define RSEN SSPCON2_bits.RSEN
1319 #define PEN SSPCON2_bits.PEN
1320 #define RCEN SSPCON2_bits.RCEN
1321 #define ACKEN SSPCON2_bits.ACKEN
1322 #define ACKDT SSPCON2_bits.ACKDT
1323 #define ACKSTAT SSPCON2_bits.ACKSTAT
1324 #define GCEN SSPCON2_bits.GCEN
1326 // ----- SSPSTAT bits --------------------
1335 unsigned char CKE:1;
1336 unsigned char SMP:1;
1341 unsigned char I2C_READ:1;
1342 unsigned char I2C_START:1;
1343 unsigned char I2C_STOP:1;
1344 unsigned char I2C_DATA:1;
1351 unsigned char NOT_W:1;
1354 unsigned char NOT_A:1;
1361 unsigned char NOT_WRITE:1;
1364 unsigned char NOT_ADDRESS:1;
1371 unsigned char R_W:1;
1374 unsigned char D_A:1;
1381 unsigned char READ_WRITE:1;
1384 unsigned char DATA_ADDRESS:1;
1389 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1391 #define BF SSPSTAT_bits.BF
1392 #define UA SSPSTAT_bits.UA
1393 #define R SSPSTAT_bits.R
1394 #define I2C_READ SSPSTAT_bits.I2C_READ
1395 #define NOT_W SSPSTAT_bits.NOT_W
1396 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1397 #define R_W SSPSTAT_bits.R_W
1398 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1399 #define S SSPSTAT_bits.S
1400 #define I2C_START SSPSTAT_bits.I2C_START
1401 #define P SSPSTAT_bits.P
1402 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1403 #define D SSPSTAT_bits.D
1404 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1405 #define NOT_A SSPSTAT_bits.NOT_A
1406 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1407 #define D_A SSPSTAT_bits.D_A
1408 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1409 #define CKE SSPSTAT_bits.CKE
1410 #define SMP SSPSTAT_bits.SMP
1412 // ----- STATUS bits --------------------
1418 unsigned char NOT_PD:1;
1419 unsigned char NOT_TO:1;
1420 unsigned char RP0:1;
1421 unsigned char RP1:1;
1422 unsigned char IRP:1;
1425 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1427 #define C STATUS_bits.C
1428 #define DC STATUS_bits.DC
1429 #define Z STATUS_bits.Z
1430 #define NOT_PD STATUS_bits.NOT_PD
1431 #define NOT_TO STATUS_bits.NOT_TO
1432 #define RP0 STATUS_bits.RP0
1433 #define RP1 STATUS_bits.RP1
1434 #define IRP STATUS_bits.IRP
1436 // ----- T1CON bits --------------------
1439 unsigned char TMR1ON:1;
1440 unsigned char TMR1CS:1;
1441 unsigned char NOT_T1SYNC:1;
1442 unsigned char T1OSCEN:1;
1443 unsigned char T1CKPS0:1;
1444 unsigned char T1CKPS1:1;
1451 unsigned char T1INSYNC:1;
1461 unsigned char T1SYNC:1;
1469 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1471 #define TMR1ON T1CON_bits.TMR1ON
1472 #define TMR1CS T1CON_bits.TMR1CS
1473 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1474 #define T1INSYNC T1CON_bits.T1INSYNC
1475 #define T1SYNC T1CON_bits.T1SYNC
1476 #define T1OSCEN T1CON_bits.T1OSCEN
1477 #define T1CKPS0 T1CON_bits.T1CKPS0
1478 #define T1CKPS1 T1CON_bits.T1CKPS1
1480 // ----- T2CON bits --------------------
1483 unsigned char T2CKPS0:1;
1484 unsigned char T2CKPS1:1;
1485 unsigned char TMR2ON:1;
1486 unsigned char TOUTPS0:1;
1487 unsigned char TOUTPS1:1;
1488 unsigned char TOUTPS2:1;
1489 unsigned char TOUTPS3:1;
1493 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1495 #define T2CKPS0 T2CON_bits.T2CKPS0
1496 #define T2CKPS1 T2CON_bits.T2CKPS1
1497 #define TMR2ON T2CON_bits.TMR2ON
1498 #define TOUTPS0 T2CON_bits.TOUTPS0
1499 #define TOUTPS1 T2CON_bits.TOUTPS1
1500 #define TOUTPS2 T2CON_bits.TOUTPS2
1501 #define TOUTPS3 T2CON_bits.TOUTPS3
1503 // ----- TRISA bits --------------------
1506 unsigned char TRISA0:1;
1507 unsigned char TRISA1:1;
1508 unsigned char TRISA2:1;
1509 unsigned char TRISA3:1;
1510 unsigned char TRISA4:1;
1511 unsigned char TRISA5:1;
1516 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1518 #define TRISA0 TRISA_bits.TRISA0
1519 #define TRISA1 TRISA_bits.TRISA1
1520 #define TRISA2 TRISA_bits.TRISA2
1521 #define TRISA3 TRISA_bits.TRISA3
1522 #define TRISA4 TRISA_bits.TRISA4
1523 #define TRISA5 TRISA_bits.TRISA5
1525 // ----- TRISB bits --------------------
1528 unsigned char TRISB0:1;
1529 unsigned char TRISB1:1;
1530 unsigned char TRISB2:1;
1531 unsigned char TRISB3:1;
1532 unsigned char TRISB4:1;
1533 unsigned char TRISB5:1;
1534 unsigned char TRISB6:1;
1535 unsigned char TRISB7:1;
1538 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1540 #define TRISB0 TRISB_bits.TRISB0
1541 #define TRISB1 TRISB_bits.TRISB1
1542 #define TRISB2 TRISB_bits.TRISB2
1543 #define TRISB3 TRISB_bits.TRISB3
1544 #define TRISB4 TRISB_bits.TRISB4
1545 #define TRISB5 TRISB_bits.TRISB5
1546 #define TRISB6 TRISB_bits.TRISB6
1547 #define TRISB7 TRISB_bits.TRISB7
1549 // ----- TRISC bits --------------------
1552 unsigned char TRISC0:1;
1553 unsigned char TRISC1:1;
1554 unsigned char TRISC2:1;
1555 unsigned char TRISC3:1;
1556 unsigned char TRISC4:1;
1557 unsigned char TRISC5:1;
1558 unsigned char TRISC6:1;
1559 unsigned char TRISC7:1;
1562 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1564 #define TRISC0 TRISC_bits.TRISC0
1565 #define TRISC1 TRISC_bits.TRISC1
1566 #define TRISC2 TRISC_bits.TRISC2
1567 #define TRISC3 TRISC_bits.TRISC3
1568 #define TRISC4 TRISC_bits.TRISC4
1569 #define TRISC5 TRISC_bits.TRISC5
1570 #define TRISC6 TRISC_bits.TRISC6
1571 #define TRISC7 TRISC_bits.TRISC7
1573 // ----- TRISD bits --------------------
1576 unsigned char TRISD0:1;
1577 unsigned char TRISD1:1;
1578 unsigned char TRISD2:1;
1579 unsigned char TRISD3:1;
1580 unsigned char TRISD4:1;
1581 unsigned char TRISD5:1;
1582 unsigned char TRISD6:1;
1583 unsigned char TRISD7:1;
1586 extern volatile __TRISD_bits_t __at(TRISD_ADDR) TRISD_bits;
1588 #define TRISD0 TRISD_bits.TRISD0
1589 #define TRISD1 TRISD_bits.TRISD1
1590 #define TRISD2 TRISD_bits.TRISD2
1591 #define TRISD3 TRISD_bits.TRISD3
1592 #define TRISD4 TRISD_bits.TRISD4
1593 #define TRISD5 TRISD_bits.TRISD5
1594 #define TRISD6 TRISD_bits.TRISD6
1595 #define TRISD7 TRISD_bits.TRISD7
1597 // ----- TRISE bits --------------------
1600 unsigned char TRISE0:1;
1601 unsigned char TRISE1:1;
1602 unsigned char TRISE2:1;
1610 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1612 #define TRISE0 TRISE_bits.TRISE0
1613 #define TRISE1 TRISE_bits.TRISE1
1614 #define TRISE2 TRISE_bits.TRISE2
1616 // ----- TXSTA bits --------------------
1619 unsigned char TX9D:1;
1620 unsigned char TRMT:1;
1621 unsigned char BRGH:1;
1623 unsigned char SYNC:1;
1624 unsigned char TXEN:1;
1625 unsigned char TX9:1;
1626 unsigned char CSRC:1;
1629 unsigned char TXD8:1;
1635 unsigned char NOT_TX8:1;
1645 unsigned char TX8_9:1;
1649 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1651 #define TX9D TXSTA_bits.TX9D
1652 #define TXD8 TXSTA_bits.TXD8
1653 #define TRMT TXSTA_bits.TRMT
1654 #define BRGH TXSTA_bits.BRGH
1655 #define SYNC TXSTA_bits.SYNC
1656 #define TXEN TXSTA_bits.TXEN
1657 #define TX9 TXSTA_bits.TX9
1658 #define NOT_TX8 TXSTA_bits.NOT_TX8
1659 #define TX8_9 TXSTA_bits.TX8_9
1660 #define CSRC TXSTA_bits.CSRC
1662 // ----- VRCON bits --------------------
1665 unsigned char VR0:1;
1666 unsigned char VR1:1;
1667 unsigned char VR2:1;
1668 unsigned char VR3:1;
1669 unsigned char VRSS:1;
1670 unsigned char VRR:1;
1671 unsigned char VROE:1;
1672 unsigned char VREN:1;
1675 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1677 #define VR0 VRCON_bits.VR0
1678 #define VR1 VRCON_bits.VR1
1679 #define VR2 VRCON_bits.VR2
1680 #define VR3 VRCON_bits.VR3
1681 #define VRSS VRCON_bits.VRSS
1682 #define VRR VRCON_bits.VRR
1683 #define VROE VRCON_bits.VROE
1684 #define VREN VRCON_bits.VREN
1686 // ----- WDTCON bits --------------------
1689 unsigned char SWDTEN:1;
1690 unsigned char WDTPS0:1;
1691 unsigned char WDTPS1:1;
1692 unsigned char WDTPS2:1;
1693 unsigned char WDTPS3:1;
1699 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1701 #define SWDTEN WDTCON_bits.SWDTEN
1702 #define WDTPS0 WDTCON_bits.WDTPS0
1703 #define WDTPS1 WDTCON_bits.WDTPS1
1704 #define WDTPS2 WDTCON_bits.WDTPS2
1705 #define WDTPS3 WDTCON_bits.WDTPS3
1707 // ----- WPUB bits --------------------
1710 unsigned char WPUB0:1;
1711 unsigned char WPUB1:1;
1712 unsigned char WPUB2:1;
1713 unsigned char WPUB3:1;
1714 unsigned char WPUB4:1;
1715 unsigned char WPUB5:1;
1716 unsigned char WPUB6:1;
1717 unsigned char WPUB7:1;
1720 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1722 #define WPUB0 WPUB_bits.WPUB0
1723 #define WPUB1 WPUB_bits.WPUB1
1724 #define WPUB2 WPUB_bits.WPUB2
1725 #define WPUB3 WPUB_bits.WPUB3
1726 #define WPUB4 WPUB_bits.WPUB4
1727 #define WPUB5 WPUB_bits.WPUB5
1728 #define WPUB6 WPUB_bits.WPUB6
1729 #define WPUB7 WPUB_bits.WPUB7