2 // Register Declarations for Microchip 16F88 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define PIR2_ADDR 0x000D
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define RCSTA_ADDR 0x0018
50 #define TXREG_ADDR 0x0019
51 #define RCREG_ADDR 0x001A
52 #define ADRESH_ADDR 0x001E
53 #define ADCON0_ADDR 0x001F
54 #define OPTION_REG_ADDR 0x0081
55 #define TRISA_ADDR 0x0085
56 #define TRISB_ADDR 0x0086
57 #define PIE1_ADDR 0x008C
58 #define PIE2_ADDR 0x008D
59 #define PCON_ADDR 0x008E
60 #define OSCCON_ADDR 0x008F
61 #define OSCTUNE_ADDR 0x0090
62 #define PR2_ADDR 0x0092
63 #define SSPADD_ADDR 0x0093
64 #define SSPSTAT_ADDR 0x0094
65 #define TXSTA_ADDR 0x0098
66 #define SPBRG_ADDR 0x0099
67 #define ANSEL_ADDR 0x009B
68 #define CMCON_ADDR 0x009C
69 #define CVRCON_ADDR 0x009D
70 #define ADRESL_ADDR 0x009E
71 #define ADCON1_ADDR 0x009F
72 #define WDTCON_ADDR 0x0105
73 #define EEDATA_ADDR 0x010C
74 #define EEADR_ADDR 0x010D
75 #define EEDATH_ADDR 0x010E
76 #define EEADRH_ADDR 0x010F
77 #define EECON1_ADDR 0x018C
78 #define EECON2_ADDR 0x018D
81 // Memory organization.
87 // P16F88.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
90 // This header file defines configurations, registers, and other useful bits of
91 // information for the PIC16F88 microcontroller. These names are taken to match
92 // the data sheets as closely as possible.
94 // Note that the processor must be selected before this file is
95 // included. The processor may be selected the following ways:
97 // 1. Command line switch:
98 // C:\ MPASM MYFILE.ASM /PIC16F88
99 // 2. LIST directive in the source file
101 // 3. Processor Type entry in the MPASM full-screen interface
103 //==========================================================================
107 //==========================================================================
111 //1.00 07/29/02 Initial Release
112 //1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS
113 //1.02 01/10/03 Added bit names for TXSTA & RCSTA registers.
114 //1.03 01/24/03 Changed Config bit CCP1_RB2 to CCP1_RB0
115 //1.04 12/02/03 Modified the WRT1:WRT0 bit definition in Config Word 1.
116 //1.05 02/08/04 Changed bit in _CONFIG1 example from CCP1_RB2 to CCP1_RB0.
118 //==========================================================================
122 //==========================================================================
125 // MESSG "Processor-header file mismatch. Verify selected processor."
128 //==========================================================================
130 // Register Definitions
132 //==========================================================================
137 //----- Register Files------------------------------------------------------
139 extern __data __at (INDF_ADDR) volatile char INDF;
140 extern __sfr __at (TMR0_ADDR) TMR0;
141 extern __data __at (PCL_ADDR) volatile char PCL;
142 extern __sfr __at (STATUS_ADDR) STATUS;
143 extern __sfr __at (FSR_ADDR) FSR;
144 extern __sfr __at (PORTA_ADDR) PORTA;
145 extern __sfr __at (PORTB_ADDR) PORTB;
146 extern __sfr __at (PCLATH_ADDR) PCLATH;
147 extern __sfr __at (INTCON_ADDR) INTCON;
148 extern __sfr __at (PIR1_ADDR) PIR1;
149 extern __sfr __at (PIR2_ADDR) PIR2;
150 extern __sfr __at (TMR1L_ADDR) TMR1L;
151 extern __sfr __at (TMR1H_ADDR) TMR1H;
152 extern __sfr __at (T1CON_ADDR) T1CON;
153 extern __sfr __at (TMR2_ADDR) TMR2;
154 extern __sfr __at (T2CON_ADDR) T2CON;
155 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
156 extern __sfr __at (SSPCON_ADDR) SSPCON;
157 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
158 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
159 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
160 extern __sfr __at (RCSTA_ADDR) RCSTA;
161 extern __sfr __at (TXREG_ADDR) TXREG;
162 extern __sfr __at (RCREG_ADDR) RCREG;
163 extern __sfr __at (ADRESH_ADDR) ADRESH;
164 extern __sfr __at (ADCON0_ADDR) ADCON0;
166 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
167 extern __sfr __at (TRISA_ADDR) TRISA;
168 extern __sfr __at (TRISB_ADDR) TRISB;
169 extern __sfr __at (PIE1_ADDR) PIE1;
170 extern __sfr __at (PIE2_ADDR) PIE2;
171 extern __sfr __at (PCON_ADDR) PCON;
172 extern __sfr __at (OSCCON_ADDR) OSCCON;
173 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
174 extern __sfr __at (PR2_ADDR) PR2;
175 extern __sfr __at (SSPADD_ADDR) SSPADD;
176 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
177 extern __sfr __at (TXSTA_ADDR) TXSTA;
178 extern __sfr __at (SPBRG_ADDR) SPBRG;
179 extern __sfr __at (ANSEL_ADDR) ANSEL;
180 extern __sfr __at (CMCON_ADDR) CMCON;
181 extern __sfr __at (CVRCON_ADDR) CVRCON;
182 extern __sfr __at (ADRESL_ADDR) ADRESL;
183 extern __sfr __at (ADCON1_ADDR) ADCON1;
185 extern __sfr __at (WDTCON_ADDR) WDTCON;
186 extern __sfr __at (EEDATA_ADDR) EEDATA;
187 extern __sfr __at (EEADR_ADDR) EEADR;
188 extern __sfr __at (EEDATH_ADDR) EEDATH;
189 extern __sfr __at (EEADRH_ADDR) EEADRH;
191 extern __sfr __at (EECON1_ADDR) EECON1;
192 extern __sfr __at (EECON2_ADDR) EECON2;
194 //----- STATUS Bits --------------------------------------------------------
196 //----- INTCON Bits --------------------------------------------------------
198 //----- PIR1 Bits ----------------------------------------------------------
200 //----- PIR2 Bits ----------------------------------------------------------
202 //----- T1CON Bits ---------------------------------------------------------
204 //----- T2CON Bits ---------------------------------------------------------
206 //----- SSPCON Bits --------------------------------------------------------
208 //----- CCP1CON Bits -------------------------------------------------------
210 //----- RCSTA Bits ---------------------------------------------------------
212 //----- ADCON0 Bits --------------------------------------------------------
214 //----- OPTION_REG Bits -----------------------------------------------------
216 //----- PIE1 Bits ----------------------------------------------------------
218 //----- PIE2 Bits ----------------------------------------------------------
220 //----- PCON Bits ----------------------------------------------------------
222 //----- OSCCON Bits -------------------------------------------------------
224 //----- OSCTUNE Bits -------------------------------------------------------
226 //----- SSPSTAT Bits -------------------------------------------------------
228 //----- TXSTA Bits ---------------------------------------------------------
230 //----- ADCON1 Bits --------------------------------------------------------
232 //----- WDTCON Bits --------------------------------------------------------
234 //----- CMCON Bits ---------------------------------------------------------
236 //----- CVRCON Bits --------------------------------------------------------
238 //----- EECON1 Bits --------------------------------------------------------
240 //==========================================================================
244 //==========================================================================
247 // __BADRAM H'07'-H'09', H'1B'-H'1D'
248 // __BADRAM H'87'-H'89', H'91', H'95'-H'97', H'9A'
249 // __BADRAM H'107'-H'109'
250 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
252 //==========================================================================
254 // Configuration Bits
256 //==========================================================================
258 #define _CONFIG1 0x2007
259 #define _CONFIG2 0x2008
261 //Configuration Byte 1 Options
262 #define _CP_ALL 0x1FFF
263 #define _CP_OFF 0x3FFF
264 #define _CCP1_RB0 0x3FFF
265 #define _CCP1_RB3 0x2FFF
266 #define _DEBUG_OFF 0x3FFF
267 #define _DEBUG_ON 0x37FF
268 #define _WRT_PROTECT_OFF 0x3FFF //No program memory write protection
269 #define _WRT_PROTECT_256 0x3DFF //First 256 program memory protected
270 #define _WRT_PROTECT_2048 0x3BFF //First 2048 program memory protected
271 #define _WRT_PROTECT_ALL 0x39FF //All of program memory protected
272 #define _CPD_ON 0x3EFF
273 #define _CPD_OFF 0x3FFF
274 #define _LVP_ON 0x3FFF
275 #define _LVP_OFF 0x3F7F
276 #define _BODEN_ON 0x3FFF
277 #define _BODEN_OFF 0x3FBF
278 #define _MCLR_ON 0x3FFF
279 #define _MCLR_OFF 0x3FDF
280 #define _PWRTE_OFF 0x3FFF
281 #define _PWRTE_ON 0x3FF7
282 #define _WDT_ON 0x3FFF
283 #define _WDT_OFF 0x3FFB
284 #define _EXTRC_CLKOUT 0x3FFF
285 #define _EXTRC_IO 0x3FFE
286 #define _INTRC_CLKOUT 0x3FFD
287 #define _INTRC_IO 0x3FFC
288 #define _EXTCLK 0x3FEF
289 #define _HS_OSC 0x3FEE
290 #define _XT_OSC 0x3FED
291 #define _LP_OSC 0x3FEC
293 //Configuration Byte 2 Options
294 #define _IESO_ON 0x3FFF
295 #define _IESO_OFF 0x3FFD
296 #define _FCMEN_ON 0x3FFF
297 #define _FCMEN_OFF 0x3FFE
301 // To use the Configuration Bits, place the following lines in your source code
302 // in the following format, and change the configuration value to the desired
303 // setting (such as CP_OFF to CP_ALL). These are currently commented out here
304 // and each __CONFIG line should have the preceding semicolon removed when
305 // pasted into your source code.
307 //Program Configuration Register 1
308 // __CONFIG _CONFIG1, _CP_OFF & _CCP1_RB0 & _DEBUG_OFF & _WRT_PROTECT_OFF & _CPD_OFF & _LVP_OFF & _BODEN_OFF & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
310 //Program Configuration Register 2
311 // __CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF
317 // ----- ADCON0 bits --------------------
320 unsigned char ADON:1;
323 unsigned char CHS0:1;
324 unsigned char CHS1:1;
325 unsigned char CHS2:1;
326 unsigned char ADCS0:1;
327 unsigned char ADCS1:1;
332 unsigned char NOT_DONE:1;
342 unsigned char GO_DONE:1;
350 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
352 #define ADON ADCON0_bits.ADON
353 #define GO ADCON0_bits.GO
354 #define NOT_DONE ADCON0_bits.NOT_DONE
355 #define GO_DONE ADCON0_bits.GO_DONE
356 #define CHS0 ADCON0_bits.CHS0
357 #define CHS1 ADCON0_bits.CHS1
358 #define CHS2 ADCON0_bits.CHS2
359 #define ADCS0 ADCON0_bits.ADCS0
360 #define ADCS1 ADCON0_bits.ADCS1
362 // ----- ADCON1 bits --------------------
369 unsigned char VCFG0:1;
370 unsigned char VCFG1:1;
371 unsigned char ADCS2:1;
372 unsigned char ADFM:1;
375 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
377 #define VCFG0 ADCON1_bits.VCFG0
378 #define VCFG1 ADCON1_bits.VCFG1
379 #define ADCS2 ADCON1_bits.ADCS2
380 #define ADFM ADCON1_bits.ADFM
382 // ----- CCP1CON bits --------------------
385 unsigned char CCP1M0:1;
386 unsigned char CCP1M1:1;
387 unsigned char CCP1M2:1;
388 unsigned char CCP1M3:1;
389 unsigned char CCP1Y:1;
390 unsigned char CCP1X:1;
395 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
397 #define CCP1M0 CCP1CON_bits.CCP1M0
398 #define CCP1M1 CCP1CON_bits.CCP1M1
399 #define CCP1M2 CCP1CON_bits.CCP1M2
400 #define CCP1M3 CCP1CON_bits.CCP1M3
401 #define CCP1Y CCP1CON_bits.CCP1Y
402 #define CCP1X CCP1CON_bits.CCP1X
404 // ----- CMCON bits --------------------
411 unsigned char C1INV:1;
412 unsigned char C2INV:1;
413 unsigned char C1OUT:1;
414 unsigned char C2OUT:1;
417 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
419 #define CM0 CMCON_bits.CM0
420 #define CM1 CMCON_bits.CM1
421 #define CM2 CMCON_bits.CM2
422 #define CIS CMCON_bits.CIS
423 #define C1INV CMCON_bits.C1INV
424 #define C2INV CMCON_bits.C2INV
425 #define C1OUT CMCON_bits.C1OUT
426 #define C2OUT CMCON_bits.C2OUT
428 // ----- CVRCON bits --------------------
431 unsigned char CVR0:1;
432 unsigned char CVR1:1;
433 unsigned char CVR2:1;
434 unsigned char CVR3:1;
436 unsigned char CVRR:1;
437 unsigned char CVROE:1;
438 unsigned char CVREN:1;
441 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
443 #define CVR0 CVRCON_bits.CVR0
444 #define CVR1 CVRCON_bits.CVR1
445 #define CVR2 CVRCON_bits.CVR2
446 #define CVR3 CVRCON_bits.CVR3
447 #define CVRR CVRCON_bits.CVRR
448 #define CVROE CVRCON_bits.CVROE
449 #define CVREN CVRCON_bits.CVREN
451 // ----- EECON1 bits --------------------
456 unsigned char WREN:1;
457 unsigned char WRERR:1;
458 unsigned char FREE:1;
461 unsigned char EEPGD:1;
464 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
466 #define RD EECON1_bits.RD
467 #define WR EECON1_bits.WR
468 #define WREN EECON1_bits.WREN
469 #define WRERR EECON1_bits.WRERR
470 #define FREE EECON1_bits.FREE
471 #define EEPGD EECON1_bits.EEPGD
473 // ----- INTCON bits --------------------
476 unsigned char RBIF:1;
477 unsigned char INTF:1;
478 unsigned char TMR0IF:1;
479 unsigned char RBIE:1;
480 unsigned char INTE:1;
481 unsigned char TMR0IE:1;
482 unsigned char PEIE:1;
486 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
488 #define RBIF INTCON_bits.RBIF
489 #define INTF INTCON_bits.INTF
490 #define TMR0IF INTCON_bits.TMR0IF
491 #define RBIE INTCON_bits.RBIE
492 #define INTE INTCON_bits.INTE
493 #define TMR0IE INTCON_bits.TMR0IE
494 #define PEIE INTCON_bits.PEIE
495 #define GIE INTCON_bits.GIE
497 // ----- OPTION_REG bits --------------------
504 unsigned char T0SE:1;
505 unsigned char T0CS:1;
506 unsigned char INTEDG:1;
507 unsigned char NOT_RBPU:1;
509 } __OPTION_REG_bits_t;
510 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
512 #define PS0 OPTION_REG_bits.PS0
513 #define PS1 OPTION_REG_bits.PS1
514 #define PS2 OPTION_REG_bits.PS2
515 #define PSA OPTION_REG_bits.PSA
516 #define T0SE OPTION_REG_bits.T0SE
517 #define T0CS OPTION_REG_bits.T0CS
518 #define INTEDG OPTION_REG_bits.INTEDG
519 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
521 // ----- OSCCON bits --------------------
524 unsigned char SCS0:1;
525 unsigned char SCS1:1;
526 unsigned char IOFS:1;
527 unsigned char OSTS:1;
528 unsigned char IRCF0:1;
529 unsigned char IRCF1:1;
530 unsigned char IRCF2:1;
534 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
536 #define SCS0 OSCCON_bits.SCS0
537 #define SCS1 OSCCON_bits.SCS1
538 #define IOFS OSCCON_bits.IOFS
539 #define OSTS OSCCON_bits.OSTS
540 #define IRCF0 OSCCON_bits.IRCF0
541 #define IRCF1 OSCCON_bits.IRCF1
542 #define IRCF2 OSCCON_bits.IRCF2
544 // ----- OSCTUNE bits --------------------
547 unsigned char TUN0:1;
548 unsigned char TUN1:1;
549 unsigned char TUN2:1;
550 unsigned char TUN3:1;
551 unsigned char TUN4:1;
552 unsigned char TUN5:1;
557 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
559 #define TUN0 OSCTUNE_bits.TUN0
560 #define TUN1 OSCTUNE_bits.TUN1
561 #define TUN2 OSCTUNE_bits.TUN2
562 #define TUN3 OSCTUNE_bits.TUN3
563 #define TUN4 OSCTUNE_bits.TUN4
564 #define TUN5 OSCTUNE_bits.TUN5
566 // ----- PCON bits --------------------
569 unsigned char NOT_BO:1;
570 unsigned char NOT_POR:1;
579 unsigned char NOT_BOR:1;
589 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
591 #define NOT_BO PCON_bits.NOT_BO
592 #define NOT_BOR PCON_bits.NOT_BOR
593 #define NOT_POR PCON_bits.NOT_POR
595 // ----- PIE1 bits --------------------
598 unsigned char TMR1IE:1;
599 unsigned char TMR2IE:1;
600 unsigned char CCP1IE:1;
601 unsigned char SSPIE:1;
602 unsigned char TXIE:1;
603 unsigned char RCIE:1;
604 unsigned char ADIE:1;
608 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
610 #define TMR1IE PIE1_bits.TMR1IE
611 #define TMR2IE PIE1_bits.TMR2IE
612 #define CCP1IE PIE1_bits.CCP1IE
613 #define SSPIE PIE1_bits.SSPIE
614 #define TXIE PIE1_bits.TXIE
615 #define RCIE PIE1_bits.RCIE
616 #define ADIE PIE1_bits.ADIE
618 // ----- PIE2 bits --------------------
625 unsigned char EEIE:1;
627 unsigned char CMIE:1;
628 unsigned char OSFIE:1;
631 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
633 #define EEIE PIE2_bits.EEIE
634 #define CMIE PIE2_bits.CMIE
635 #define OSFIE PIE2_bits.OSFIE
637 // ----- PIR1 bits --------------------
640 unsigned char TMR1IF:1;
641 unsigned char TMR2IF:1;
642 unsigned char CCP1IF:1;
643 unsigned char SSPIF:1;
644 unsigned char TXIF:1;
645 unsigned char RCIF:1;
646 unsigned char ADIF:1;
650 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
652 #define TMR1IF PIR1_bits.TMR1IF
653 #define TMR2IF PIR1_bits.TMR2IF
654 #define CCP1IF PIR1_bits.CCP1IF
655 #define SSPIF PIR1_bits.SSPIF
656 #define TXIF PIR1_bits.TXIF
657 #define RCIF PIR1_bits.RCIF
658 #define ADIF PIR1_bits.ADIF
660 // ----- PIR2 bits --------------------
667 unsigned char EEIF:1;
669 unsigned char CMIF:1;
670 unsigned char OSFIF:1;
673 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
675 #define EEIF PIR2_bits.EEIF
676 #define CMIF PIR2_bits.CMIF
677 #define OSFIF PIR2_bits.OSFIF
679 // ----- PORTA bits --------------------
692 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
694 #define RA0 PORTA_bits.RA0
695 #define RA1 PORTA_bits.RA1
696 #define RA2 PORTA_bits.RA2
697 #define RA3 PORTA_bits.RA3
698 #define RA4 PORTA_bits.RA4
699 #define RA5 PORTA_bits.RA5
701 // ----- PORTB bits --------------------
714 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
716 #define RB0 PORTB_bits.RB0
717 #define RB1 PORTB_bits.RB1
718 #define RB2 PORTB_bits.RB2
719 #define RB3 PORTB_bits.RB3
720 #define RB4 PORTB_bits.RB4
721 #define RB5 PORTB_bits.RB5
722 #define RB6 PORTB_bits.RB6
723 #define RB7 PORTB_bits.RB7
725 // ----- RCSTA bits --------------------
728 unsigned char RX9D:1;
729 unsigned char OERR:1;
730 unsigned char FERR:1;
731 unsigned char ADDEN:1;
732 unsigned char CREN:1;
733 unsigned char SREN:1;
735 unsigned char SPEN:1;
738 unsigned char RCD8:1;
754 unsigned char NOT_RC8:1;
764 unsigned char RC8_9:1;
768 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
770 #define RX9D RCSTA_bits.RX9D
771 #define RCD8 RCSTA_bits.RCD8
772 #define OERR RCSTA_bits.OERR
773 #define FERR RCSTA_bits.FERR
774 #define ADDEN RCSTA_bits.ADDEN
775 #define CREN RCSTA_bits.CREN
776 #define SREN RCSTA_bits.SREN
777 #define RX9 RCSTA_bits.RX9
778 #define RC9 RCSTA_bits.RC9
779 #define NOT_RC8 RCSTA_bits.NOT_RC8
780 #define RC8_9 RCSTA_bits.RC8_9
781 #define SPEN RCSTA_bits.SPEN
783 // ----- SSPCON bits --------------------
786 unsigned char SSPM0:1;
787 unsigned char SSPM1:1;
788 unsigned char SSPM2:1;
789 unsigned char SSPM3:1;
791 unsigned char SSPEN:1;
792 unsigned char SSPOV:1;
793 unsigned char WCOL:1;
796 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
798 #define SSPM0 SSPCON_bits.SSPM0
799 #define SSPM1 SSPCON_bits.SSPM1
800 #define SSPM2 SSPCON_bits.SSPM2
801 #define SSPM3 SSPCON_bits.SSPM3
802 #define CKP SSPCON_bits.CKP
803 #define SSPEN SSPCON_bits.SSPEN
804 #define SSPOV SSPCON_bits.SSPOV
805 #define WCOL SSPCON_bits.WCOL
807 // ----- SSPSTAT bits --------------------
822 unsigned char I2C_READ:1;
823 unsigned char I2C_START:1;
824 unsigned char I2C_STOP:1;
825 unsigned char I2C_DATA:1;
832 unsigned char NOT_W:1;
835 unsigned char NOT_A:1;
842 unsigned char NOT_WRITE:1;
845 unsigned char NOT_ADDRESS:1;
862 unsigned char READ_WRITE:1;
865 unsigned char DATA_ADDRESS:1;
870 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
872 #define BF SSPSTAT_bits.BF
873 #define UA SSPSTAT_bits.UA
874 #define R SSPSTAT_bits.R
875 #define I2C_READ SSPSTAT_bits.I2C_READ
876 #define NOT_W SSPSTAT_bits.NOT_W
877 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
878 #define R_W SSPSTAT_bits.R_W
879 #define READ_WRITE SSPSTAT_bits.READ_WRITE
880 #define S SSPSTAT_bits.S
881 #define I2C_START SSPSTAT_bits.I2C_START
882 #define P SSPSTAT_bits.P
883 #define I2C_STOP SSPSTAT_bits.I2C_STOP
884 #define D SSPSTAT_bits.D
885 #define I2C_DATA SSPSTAT_bits.I2C_DATA
886 #define NOT_A SSPSTAT_bits.NOT_A
887 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
888 #define D_A SSPSTAT_bits.D_A
889 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
890 #define CKE SSPSTAT_bits.CKE
891 #define SMP SSPSTAT_bits.SMP
893 // ----- STATUS bits --------------------
899 unsigned char NOT_PD:1;
900 unsigned char NOT_TO:1;
906 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
908 #define C STATUS_bits.C
909 #define DC STATUS_bits.DC
910 #define Z STATUS_bits.Z
911 #define NOT_PD STATUS_bits.NOT_PD
912 #define NOT_TO STATUS_bits.NOT_TO
913 #define RP0 STATUS_bits.RP0
914 #define RP1 STATUS_bits.RP1
915 #define IRP STATUS_bits.IRP
917 // ----- T1CON bits --------------------
920 unsigned char TMR1ON:1;
921 unsigned char TMR1CS:1;
922 unsigned char NOT_T1SYNC:1;
923 unsigned char T1OSCEN:1;
924 unsigned char T1CKPS0:1;
925 unsigned char T1CKPS1:1;
926 unsigned char T1RUN:1;
932 unsigned char T1INSYNC:1;
940 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
942 #define TMR1ON T1CON_bits.TMR1ON
943 #define TMR1CS T1CON_bits.TMR1CS
944 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
945 #define T1INSYNC T1CON_bits.T1INSYNC
946 #define T1OSCEN T1CON_bits.T1OSCEN
947 #define T1CKPS0 T1CON_bits.T1CKPS0
948 #define T1CKPS1 T1CON_bits.T1CKPS1
949 #define T1RUN T1CON_bits.T1RUN
951 // ----- T2CON bits --------------------
954 unsigned char T2CKPS0:1;
955 unsigned char T2CKPS1:1;
956 unsigned char TMR2ON:1;
957 unsigned char TOUTPS0:1;
958 unsigned char TOUTPS1:1;
959 unsigned char TOUTPS2:1;
960 unsigned char TOUTPS3:1;
964 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
966 #define T2CKPS0 T2CON_bits.T2CKPS0
967 #define T2CKPS1 T2CON_bits.T2CKPS1
968 #define TMR2ON T2CON_bits.TMR2ON
969 #define TOUTPS0 T2CON_bits.TOUTPS0
970 #define TOUTPS1 T2CON_bits.TOUTPS1
971 #define TOUTPS2 T2CON_bits.TOUTPS2
972 #define TOUTPS3 T2CON_bits.TOUTPS3
974 // ----- TRISA bits --------------------
977 unsigned char TRISA0:1;
978 unsigned char TRISA1:1;
979 unsigned char TRISA2:1;
980 unsigned char TRISA3:1;
981 unsigned char TRISA4:1;
982 unsigned char TRISA5:1;
987 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
989 #define TRISA0 TRISA_bits.TRISA0
990 #define TRISA1 TRISA_bits.TRISA1
991 #define TRISA2 TRISA_bits.TRISA2
992 #define TRISA3 TRISA_bits.TRISA3
993 #define TRISA4 TRISA_bits.TRISA4
994 #define TRISA5 TRISA_bits.TRISA5
996 // ----- TRISB bits --------------------
999 unsigned char TRISB0:1;
1000 unsigned char TRISB1:1;
1001 unsigned char TRISB2:1;
1002 unsigned char TRISB3:1;
1003 unsigned char TRISB4:1;
1004 unsigned char TRISB5:1;
1005 unsigned char TRISB6:1;
1006 unsigned char TRISB7:1;
1009 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1011 #define TRISB0 TRISB_bits.TRISB0
1012 #define TRISB1 TRISB_bits.TRISB1
1013 #define TRISB2 TRISB_bits.TRISB2
1014 #define TRISB3 TRISB_bits.TRISB3
1015 #define TRISB4 TRISB_bits.TRISB4
1016 #define TRISB5 TRISB_bits.TRISB5
1017 #define TRISB6 TRISB_bits.TRISB6
1018 #define TRISB7 TRISB_bits.TRISB7
1020 // ----- TXSTA bits --------------------
1023 unsigned char TX9D:1;
1024 unsigned char TRMT:1;
1025 unsigned char BRGH:1;
1027 unsigned char SYNC:1;
1028 unsigned char TXEN:1;
1029 unsigned char TX9:1;
1030 unsigned char CSRC:1;
1033 unsigned char TXD8:1;
1039 unsigned char NOT_TX8:1;
1049 unsigned char TX8_9:1;
1053 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1055 #define TX9D TXSTA_bits.TX9D
1056 #define TXD8 TXSTA_bits.TXD8
1057 #define TRMT TXSTA_bits.TRMT
1058 #define BRGH TXSTA_bits.BRGH
1059 #define SYNC TXSTA_bits.SYNC
1060 #define TXEN TXSTA_bits.TXEN
1061 #define TX9 TXSTA_bits.TX9
1062 #define NOT_TX8 TXSTA_bits.NOT_TX8
1063 #define TX8_9 TXSTA_bits.TX8_9
1064 #define CSRC TXSTA_bits.CSRC
1066 // ----- WDTCON bits --------------------
1069 unsigned char SWDTEN:1;
1070 unsigned char WDTPS0:1;
1071 unsigned char WDTPS1:1;
1072 unsigned char WDTPS2:1;
1073 unsigned char WDTPS3:1;
1079 unsigned char SWDTE:1;
1089 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1091 #define SWDTEN WDTCON_bits.SWDTEN
1092 #define SWDTE WDTCON_bits.SWDTE
1093 #define WDTPS0 WDTCON_bits.WDTPS0
1094 #define WDTPS1 WDTCON_bits.WDTPS1
1095 #define WDTPS2 WDTCON_bits.WDTPS2
1096 #define WDTPS3 WDTCON_bits.WDTPS3