2 // Register Declarations for Microchip 16F88 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define PIR2_ADDR 0x000D
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define RCSTA_ADDR 0x0018
50 #define TXREG_ADDR 0x0019
51 #define RCREG_ADDR 0x001A
52 #define ADRESH_ADDR 0x001E
53 #define ADCON0_ADDR 0x001F
54 #define OPTION_REG_ADDR 0x0081
55 #define TRISA_ADDR 0x0085
56 #define TRISB_ADDR 0x0086
57 #define PIE1_ADDR 0x008C
58 #define PIE2_ADDR 0x008D
59 #define PCON_ADDR 0x008E
60 #define OSCCON_ADDR 0x008F
61 #define OSCTUNE_ADDR 0x0090
62 #define PR2_ADDR 0x0092
63 #define SSPADD_ADDR 0x0093
64 #define SSPSTAT_ADDR 0x0094
65 #define TXSTA_ADDR 0x0098
66 #define SPBRG_ADDR 0x0099
67 #define ANSEL_ADDR 0x009B
68 #define CMCON_ADDR 0x009C
69 #define CVRCON_ADDR 0x009D
70 #define ADRESL_ADDR 0x009E
71 #define ADCON1_ADDR 0x009F
72 #define WDTCON_ADDR 0x0105
73 #define EEDATA_ADDR 0x010C
74 #define EEADR_ADDR 0x010D
75 #define EEDATH_ADDR 0x010E
76 #define EEADRH_ADDR 0x010F
77 #define EECON1_ADDR 0x018C
78 #define EECON2_ADDR 0x018D
81 // Memory organization.
84 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
85 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
86 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
87 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
88 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
89 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
90 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
91 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
92 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
93 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
94 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
95 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
96 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
97 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
98 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
99 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
100 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
101 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
102 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
103 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
104 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
105 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
106 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
107 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
108 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
109 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
110 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
111 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
112 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
113 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
114 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
115 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
116 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
117 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
118 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
119 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
120 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
121 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
122 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
123 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
124 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
125 #pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON
126 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
127 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
128 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
129 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
130 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
131 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
132 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
133 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
134 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
138 // P16F88.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
141 // This header file defines configurations, registers, and other useful bits of
142 // information for the PIC16F88 microcontroller. These names are taken to match
143 // the data sheets as closely as possible.
145 // Note that the processor must be selected before this file is
146 // included. The processor may be selected the following ways:
148 // 1. Command line switch:
149 // C:\ MPASM MYFILE.ASM /PIC16F88
150 // 2. LIST directive in the source file
152 // 3. Processor Type entry in the MPASM full-screen interface
154 //==========================================================================
158 //==========================================================================
162 //1.00 07/29/02 Initial Release
163 //1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS
164 //1.02 01/10/03 Added bit names for TXSTA & RCSTA registers.
165 //1.03 01/24/03 Changed Config bit CCP1_RB2 to CCP1_RB0
166 //1.04 12/02/03 Modified the WRT1:WRT0 bit definition in Config Word 1.
167 //1.05 02/08/04 Changed bit in _CONFIG1 example from CCP1_RB2 to CCP1_RB0.
169 //==========================================================================
173 //==========================================================================
176 // MESSG "Processor-header file mismatch. Verify selected processor."
179 //==========================================================================
181 // Register Definitions
183 //==========================================================================
188 //----- Register Files------------------------------------------------------
190 extern __data __at (INDF_ADDR) volatile char INDF;
191 extern __sfr __at (TMR0_ADDR) TMR0;
192 extern __data __at (PCL_ADDR) volatile char PCL;
193 extern __sfr __at (STATUS_ADDR) STATUS;
194 extern __sfr __at (FSR_ADDR) FSR;
195 extern __sfr __at (PORTA_ADDR) PORTA;
196 extern __sfr __at (PORTB_ADDR) PORTB;
197 extern __sfr __at (PCLATH_ADDR) PCLATH;
198 extern __sfr __at (INTCON_ADDR) INTCON;
199 extern __sfr __at (PIR1_ADDR) PIR1;
200 extern __sfr __at (PIR2_ADDR) PIR2;
201 extern __sfr __at (TMR1L_ADDR) TMR1L;
202 extern __sfr __at (TMR1H_ADDR) TMR1H;
203 extern __sfr __at (T1CON_ADDR) T1CON;
204 extern __sfr __at (TMR2_ADDR) TMR2;
205 extern __sfr __at (T2CON_ADDR) T2CON;
206 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
207 extern __sfr __at (SSPCON_ADDR) SSPCON;
208 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
209 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
210 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
211 extern __sfr __at (RCSTA_ADDR) RCSTA;
212 extern __sfr __at (TXREG_ADDR) TXREG;
213 extern __sfr __at (RCREG_ADDR) RCREG;
214 extern __sfr __at (ADRESH_ADDR) ADRESH;
215 extern __sfr __at (ADCON0_ADDR) ADCON0;
217 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
218 extern __sfr __at (TRISA_ADDR) TRISA;
219 extern __sfr __at (TRISB_ADDR) TRISB;
220 extern __sfr __at (PIE1_ADDR) PIE1;
221 extern __sfr __at (PIE2_ADDR) PIE2;
222 extern __sfr __at (PCON_ADDR) PCON;
223 extern __sfr __at (OSCCON_ADDR) OSCCON;
224 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
225 extern __sfr __at (PR2_ADDR) PR2;
226 extern __sfr __at (SSPADD_ADDR) SSPADD;
227 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
228 extern __sfr __at (TXSTA_ADDR) TXSTA;
229 extern __sfr __at (SPBRG_ADDR) SPBRG;
230 extern __sfr __at (ANSEL_ADDR) ANSEL;
231 extern __sfr __at (CMCON_ADDR) CMCON;
232 extern __sfr __at (CVRCON_ADDR) CVRCON;
233 extern __sfr __at (ADRESL_ADDR) ADRESL;
234 extern __sfr __at (ADCON1_ADDR) ADCON1;
236 extern __sfr __at (WDTCON_ADDR) WDTCON;
237 extern __sfr __at (EEDATA_ADDR) EEDATA;
238 extern __sfr __at (EEADR_ADDR) EEADR;
239 extern __sfr __at (EEDATH_ADDR) EEDATH;
240 extern __sfr __at (EEADRH_ADDR) EEADRH;
242 extern __sfr __at (EECON1_ADDR) EECON1;
243 extern __sfr __at (EECON2_ADDR) EECON2;
245 //----- STATUS Bits --------------------------------------------------------
247 //----- INTCON Bits --------------------------------------------------------
249 //----- PIR1 Bits ----------------------------------------------------------
251 //----- PIR2 Bits ----------------------------------------------------------
253 //----- T1CON Bits ---------------------------------------------------------
255 //----- T2CON Bits ---------------------------------------------------------
257 //----- SSPCON Bits --------------------------------------------------------
259 //----- CCP1CON Bits -------------------------------------------------------
261 //----- RCSTA Bits ---------------------------------------------------------
263 //----- ADCON0 Bits --------------------------------------------------------
265 //----- OPTION Bits -----------------------------------------------------
267 //----- PIE1 Bits ----------------------------------------------------------
269 //----- PIE2 Bits ----------------------------------------------------------
271 //----- PCON Bits ----------------------------------------------------------
273 //----- OSCCON Bits -------------------------------------------------------
275 //----- OSCTUNE Bits -------------------------------------------------------
277 //----- SSPSTAT Bits -------------------------------------------------------
279 //----- TXSTA Bits ---------------------------------------------------------
281 //----- ADCON1 Bits --------------------------------------------------------
283 //----- WDTCON Bits --------------------------------------------------------
285 //----- CMCON Bits ---------------------------------------------------------
287 //----- CVRCON Bits --------------------------------------------------------
289 //----- EECON1 Bits --------------------------------------------------------
291 //==========================================================================
295 //==========================================================================
298 // __BADRAM H'07'-H'09', H'1B'-H'1D'
299 // __BADRAM H'87'-H'89', H'91', H'95'-H'97', H'9A'
300 // __BADRAM H'107'-H'109'
301 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
303 //==========================================================================
305 // Configuration Bits
307 //==========================================================================
309 #define _CONFIG1 0x2007
310 #define _CONFIG2 0x2008
312 //Configuration Byte 1 Options
313 #define _CP_ALL 0x1FFF
314 #define _CP_OFF 0x3FFF
315 #define _CCP1_RB0 0x3FFF
316 #define _CCP1_RB3 0x2FFF
317 #define _DEBUG_OFF 0x3FFF
318 #define _DEBUG_ON 0x37FF
319 #define _WRT_PROTECT_OFF 0x3FFF //No program memory write protection
320 #define _WRT_PROTECT_256 0x3DFF //First 256 program memory protected
321 #define _WRT_PROTECT_2048 0x3BFF //First 2048 program memory protected
322 #define _WRT_PROTECT_ALL 0x39FF //All of program memory protected
323 #define _CPD_ON 0x3EFF
324 #define _CPD_OFF 0x3FFF
325 #define _LVP_ON 0x3FFF
326 #define _LVP_OFF 0x3F7F
327 #define _BODEN_ON 0x3FFF
328 #define _BODEN_OFF 0x3FBF
329 #define _MCLR_ON 0x3FFF
330 #define _MCLR_OFF 0x3FDF
331 #define _PWRTE_OFF 0x3FFF
332 #define _PWRTE_ON 0x3FF7
333 #define _WDT_ON 0x3FFF
334 #define _WDT_OFF 0x3FFB
335 #define _EXTRC_CLKOUT 0x3FFF
336 #define _EXTRC_IO 0x3FFE
337 #define _INTRC_CLKOUT 0x3FFD
338 #define _INTRC_IO 0x3FFC
339 #define _EXTCLK 0x3FEF
340 #define _HS_OSC 0x3FEE
341 #define _XT_OSC 0x3FED
342 #define _LP_OSC 0x3FEC
344 //Configuration Byte 2 Options
345 #define _IESO_ON 0x3FFF
346 #define _IESO_OFF 0x3FFD
347 #define _FCMEN_ON 0x3FFF
348 #define _FCMEN_OFF 0x3FFE
352 // To use the Configuration Bits, place the following lines in your source code
353 // in the following format, and change the configuration value to the desired
354 // setting (such as CP_OFF to CP_ALL). These are currently commented out here
355 // and each __CONFIG line should have the preceding semicolon removed when
356 // pasted into your source code.
358 //Program Configuration Register 1
359 // __CONFIG _CONFIG1, _CP_OFF & _CCP1_RB0 & _DEBUG_OFF & _WRT_PROTECT_OFF & _CPD_OFF & _LVP_OFF & _BODEN_OFF & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
361 //Program Configuration Register 2
362 // __CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF
368 // ----- ADCON0 bits --------------------
371 unsigned char ADON:1;
374 unsigned char CHS0:1;
375 unsigned char CHS1:1;
376 unsigned char CHS2:1;
377 unsigned char ADCS0:1;
378 unsigned char ADCS1:1;
383 unsigned char NOT_DONE:1;
393 unsigned char GO_DONE:1;
401 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
403 #define ADON ADCON0_bits.ADON
404 #define GO ADCON0_bits.GO
405 #define NOT_DONE ADCON0_bits.NOT_DONE
406 #define GO_DONE ADCON0_bits.GO_DONE
407 #define CHS0 ADCON0_bits.CHS0
408 #define CHS1 ADCON0_bits.CHS1
409 #define CHS2 ADCON0_bits.CHS2
410 #define ADCS0 ADCON0_bits.ADCS0
411 #define ADCS1 ADCON0_bits.ADCS1
413 // ----- ADCON1 bits --------------------
420 unsigned char VCFG0:1;
421 unsigned char VCFG1:1;
422 unsigned char ADCS2:1;
423 unsigned char ADFM:1;
426 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
428 #define VCFG0 ADCON1_bits.VCFG0
429 #define VCFG1 ADCON1_bits.VCFG1
430 #define ADCS2 ADCON1_bits.ADCS2
431 #define ADFM ADCON1_bits.ADFM
433 // ----- CCP1CON bits --------------------
436 unsigned char CCP1M0:1;
437 unsigned char CCP1M1:1;
438 unsigned char CCP1M2:1;
439 unsigned char CCP1M3:1;
440 unsigned char CCP1Y:1;
441 unsigned char CCP1X:1;
446 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
448 #define CCP1M0 CCP1CON_bits.CCP1M0
449 #define CCP1M1 CCP1CON_bits.CCP1M1
450 #define CCP1M2 CCP1CON_bits.CCP1M2
451 #define CCP1M3 CCP1CON_bits.CCP1M3
452 #define CCP1Y CCP1CON_bits.CCP1Y
453 #define CCP1X CCP1CON_bits.CCP1X
455 // ----- CMCON bits --------------------
462 unsigned char C1INV:1;
463 unsigned char C2INV:1;
464 unsigned char C1OUT:1;
465 unsigned char C2OUT:1;
468 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
470 #define CM0 CMCON_bits.CM0
471 #define CM1 CMCON_bits.CM1
472 #define CM2 CMCON_bits.CM2
473 #define CIS CMCON_bits.CIS
474 #define C1INV CMCON_bits.C1INV
475 #define C2INV CMCON_bits.C2INV
476 #define C1OUT CMCON_bits.C1OUT
477 #define C2OUT CMCON_bits.C2OUT
479 // ----- CVRCON bits --------------------
482 unsigned char CVR0:1;
483 unsigned char CVR1:1;
484 unsigned char CVR2:1;
485 unsigned char CVR3:1;
487 unsigned char CVRR:1;
488 unsigned char CVROE:1;
489 unsigned char CVREN:1;
492 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
494 #define CVR0 CVRCON_bits.CVR0
495 #define CVR1 CVRCON_bits.CVR1
496 #define CVR2 CVRCON_bits.CVR2
497 #define CVR3 CVRCON_bits.CVR3
498 #define CVRR CVRCON_bits.CVRR
499 #define CVROE CVRCON_bits.CVROE
500 #define CVREN CVRCON_bits.CVREN
502 // ----- EECON1 bits --------------------
507 unsigned char WREN:1;
508 unsigned char WRERR:1;
509 unsigned char FREE:1;
512 unsigned char EEPGD:1;
515 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
517 #define RD EECON1_bits.RD
518 #define WR EECON1_bits.WR
519 #define WREN EECON1_bits.WREN
520 #define WRERR EECON1_bits.WRERR
521 #define FREE EECON1_bits.FREE
522 #define EEPGD EECON1_bits.EEPGD
524 // ----- INTCON bits --------------------
527 unsigned char RBIF:1;
528 unsigned char INTF:1;
529 unsigned char TMR0IF:1;
530 unsigned char RBIE:1;
531 unsigned char INTE:1;
532 unsigned char TMR0IE:1;
533 unsigned char PEIE:1;
537 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
539 #define RBIF INTCON_bits.RBIF
540 #define INTF INTCON_bits.INTF
541 #define TMR0IF INTCON_bits.TMR0IF
542 #define RBIE INTCON_bits.RBIE
543 #define INTE INTCON_bits.INTE
544 #define TMR0IE INTCON_bits.TMR0IE
545 #define PEIE INTCON_bits.PEIE
546 #define GIE INTCON_bits.GIE
548 // ----- OPTION_REG bits --------------------
555 unsigned char T0SE:1;
556 unsigned char T0CS:1;
557 unsigned char INTEDG:1;
558 unsigned char NOT_RBPU:1;
560 } __OPTION_REG_bits_t;
561 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
563 #define PS0 OPTION_REG_bits.PS0
564 #define PS1 OPTION_REG_bits.PS1
565 #define PS2 OPTION_REG_bits.PS2
566 #define PSA OPTION_REG_bits.PSA
567 #define T0SE OPTION_REG_bits.T0SE
568 #define T0CS OPTION_REG_bits.T0CS
569 #define INTEDG OPTION_REG_bits.INTEDG
570 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
572 // ----- OSCCON bits --------------------
575 unsigned char SCS0:1;
576 unsigned char SCS1:1;
577 unsigned char IOFS:1;
578 unsigned char OSTS:1;
579 unsigned char IRCF0:1;
580 unsigned char IRCF1:1;
581 unsigned char IRCF2:1;
585 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
587 #define SCS0 OSCCON_bits.SCS0
588 #define SCS1 OSCCON_bits.SCS1
589 #define IOFS OSCCON_bits.IOFS
590 #define OSTS OSCCON_bits.OSTS
591 #define IRCF0 OSCCON_bits.IRCF0
592 #define IRCF1 OSCCON_bits.IRCF1
593 #define IRCF2 OSCCON_bits.IRCF2
595 // ----- OSCTUNE bits --------------------
598 unsigned char TUN0:1;
599 unsigned char TUN1:1;
600 unsigned char TUN2:1;
601 unsigned char TUN3:1;
602 unsigned char TUN4:1;
603 unsigned char TUN5:1;
608 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
610 #define TUN0 OSCTUNE_bits.TUN0
611 #define TUN1 OSCTUNE_bits.TUN1
612 #define TUN2 OSCTUNE_bits.TUN2
613 #define TUN3 OSCTUNE_bits.TUN3
614 #define TUN4 OSCTUNE_bits.TUN4
615 #define TUN5 OSCTUNE_bits.TUN5
617 // ----- PCON bits --------------------
620 unsigned char NOT_BO:1;
621 unsigned char NOT_POR:1;
630 unsigned char NOT_BOR:1;
640 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
642 #define NOT_BO PCON_bits.NOT_BO
643 #define NOT_BOR PCON_bits.NOT_BOR
644 #define NOT_POR PCON_bits.NOT_POR
646 // ----- PIE1 bits --------------------
649 unsigned char TMR1IE:1;
650 unsigned char TMR2IE:1;
651 unsigned char CCP1IE:1;
652 unsigned char SSPIE:1;
653 unsigned char TXIE:1;
654 unsigned char RCIE:1;
655 unsigned char ADIE:1;
659 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
661 #define TMR1IE PIE1_bits.TMR1IE
662 #define TMR2IE PIE1_bits.TMR2IE
663 #define CCP1IE PIE1_bits.CCP1IE
664 #define SSPIE PIE1_bits.SSPIE
665 #define TXIE PIE1_bits.TXIE
666 #define RCIE PIE1_bits.RCIE
667 #define ADIE PIE1_bits.ADIE
669 // ----- PIE2 bits --------------------
676 unsigned char EEIE:1;
678 unsigned char CMIE:1;
679 unsigned char OSFIE:1;
682 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
684 #define EEIE PIE2_bits.EEIE
685 #define CMIE PIE2_bits.CMIE
686 #define OSFIE PIE2_bits.OSFIE
688 // ----- PIR1 bits --------------------
691 unsigned char TMR1IF:1;
692 unsigned char TMR2IF:1;
693 unsigned char CCP1IF:1;
694 unsigned char SSPIF:1;
695 unsigned char TXIF:1;
696 unsigned char RCIF:1;
697 unsigned char ADIF:1;
701 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
703 #define TMR1IF PIR1_bits.TMR1IF
704 #define TMR2IF PIR1_bits.TMR2IF
705 #define CCP1IF PIR1_bits.CCP1IF
706 #define SSPIF PIR1_bits.SSPIF
707 #define TXIF PIR1_bits.TXIF
708 #define RCIF PIR1_bits.RCIF
709 #define ADIF PIR1_bits.ADIF
711 // ----- PIR2 bits --------------------
718 unsigned char EEIF:1;
720 unsigned char CMIF:1;
721 unsigned char OSFIF:1;
724 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
726 #define EEIF PIR2_bits.EEIF
727 #define CMIF PIR2_bits.CMIF
728 #define OSFIF PIR2_bits.OSFIF
730 // ----- RCSTA bits --------------------
733 unsigned char RX9D:1;
734 unsigned char OERR:1;
735 unsigned char FERR:1;
736 unsigned char ADDEN:1;
737 unsigned char CREN:1;
738 unsigned char SREN:1;
740 unsigned char SPEN:1;
743 unsigned char RCD8:1;
759 unsigned char NOT_RC8:1;
769 unsigned char RC8_9:1;
773 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
775 #define RX9D RCSTA_bits.RX9D
776 #define RCD8 RCSTA_bits.RCD8
777 #define OERR RCSTA_bits.OERR
778 #define FERR RCSTA_bits.FERR
779 #define ADDEN RCSTA_bits.ADDEN
780 #define CREN RCSTA_bits.CREN
781 #define SREN RCSTA_bits.SREN
782 #define RX9 RCSTA_bits.RX9
783 #define RC9 RCSTA_bits.RC9
784 #define NOT_RC8 RCSTA_bits.NOT_RC8
785 #define RC8_9 RCSTA_bits.RC8_9
786 #define SPEN RCSTA_bits.SPEN
788 // ----- SSPCON bits --------------------
791 unsigned char SSPM0:1;
792 unsigned char SSPM1:1;
793 unsigned char SSPM2:1;
794 unsigned char SSPM3:1;
796 unsigned char SSPEN:1;
797 unsigned char SSPOV:1;
798 unsigned char WCOL:1;
801 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
803 #define SSPM0 SSPCON_bits.SSPM0
804 #define SSPM1 SSPCON_bits.SSPM1
805 #define SSPM2 SSPCON_bits.SSPM2
806 #define SSPM3 SSPCON_bits.SSPM3
807 #define CKP SSPCON_bits.CKP
808 #define SSPEN SSPCON_bits.SSPEN
809 #define SSPOV SSPCON_bits.SSPOV
810 #define WCOL SSPCON_bits.WCOL
812 // ----- SSPSTAT bits --------------------
827 unsigned char I2C_READ:1;
828 unsigned char I2C_START:1;
829 unsigned char I2C_STOP:1;
830 unsigned char I2C_DATA:1;
837 unsigned char NOT_W:1;
840 unsigned char NOT_A:1;
847 unsigned char NOT_WRITE:1;
850 unsigned char NOT_ADDRESS:1;
867 unsigned char READ_WRITE:1;
870 unsigned char DATA_ADDRESS:1;
875 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
877 #define BF SSPSTAT_bits.BF
878 #define UA SSPSTAT_bits.UA
879 #define R SSPSTAT_bits.R
880 #define I2C_READ SSPSTAT_bits.I2C_READ
881 #define NOT_W SSPSTAT_bits.NOT_W
882 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
883 #define R_W SSPSTAT_bits.R_W
884 #define READ_WRITE SSPSTAT_bits.READ_WRITE
885 #define S SSPSTAT_bits.S
886 #define I2C_START SSPSTAT_bits.I2C_START
887 #define P SSPSTAT_bits.P
888 #define I2C_STOP SSPSTAT_bits.I2C_STOP
889 #define D SSPSTAT_bits.D
890 #define I2C_DATA SSPSTAT_bits.I2C_DATA
891 #define NOT_A SSPSTAT_bits.NOT_A
892 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
893 #define D_A SSPSTAT_bits.D_A
894 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
895 #define CKE SSPSTAT_bits.CKE
896 #define SMP SSPSTAT_bits.SMP
898 // ----- STATUS bits --------------------
904 unsigned char NOT_PD:1;
905 unsigned char NOT_TO:1;
911 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
913 #define C STATUS_bits.C
914 #define DC STATUS_bits.DC
915 #define Z STATUS_bits.Z
916 #define NOT_PD STATUS_bits.NOT_PD
917 #define NOT_TO STATUS_bits.NOT_TO
918 #define RP0 STATUS_bits.RP0
919 #define RP1 STATUS_bits.RP1
920 #define IRP STATUS_bits.IRP
922 // ----- T1CON bits --------------------
925 unsigned char TMR1ON:1;
926 unsigned char TMR1CS:1;
927 unsigned char NOT_T1SYNC:1;
928 unsigned char T1OSCEN:1;
929 unsigned char T1CKPS0:1;
930 unsigned char T1CKPS1:1;
931 unsigned char T1RUN:1;
937 unsigned char T1INSYNC:1;
945 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
947 #define TMR1ON T1CON_bits.TMR1ON
948 #define TMR1CS T1CON_bits.TMR1CS
949 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
950 #define T1INSYNC T1CON_bits.T1INSYNC
951 #define T1OSCEN T1CON_bits.T1OSCEN
952 #define T1CKPS0 T1CON_bits.T1CKPS0
953 #define T1CKPS1 T1CON_bits.T1CKPS1
954 #define T1RUN T1CON_bits.T1RUN
956 // ----- T2CON bits --------------------
959 unsigned char T2CKPS0:1;
960 unsigned char T2CKPS1:1;
961 unsigned char TMR2ON:1;
962 unsigned char TOUTPS0:1;
963 unsigned char TOUTPS1:1;
964 unsigned char TOUTPS2:1;
965 unsigned char TOUTPS3:1;
969 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
971 #define T2CKPS0 T2CON_bits.T2CKPS0
972 #define T2CKPS1 T2CON_bits.T2CKPS1
973 #define TMR2ON T2CON_bits.TMR2ON
974 #define TOUTPS0 T2CON_bits.TOUTPS0
975 #define TOUTPS1 T2CON_bits.TOUTPS1
976 #define TOUTPS2 T2CON_bits.TOUTPS2
977 #define TOUTPS3 T2CON_bits.TOUTPS3
979 // ----- TXSTA bits --------------------
982 unsigned char TX9D:1;
983 unsigned char TRMT:1;
984 unsigned char BRGH:1;
986 unsigned char SYNC:1;
987 unsigned char TXEN:1;
989 unsigned char CSRC:1;
992 unsigned char TXD8:1;
998 unsigned char NOT_TX8:1;
1008 unsigned char TX8_9:1;
1012 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1014 #define TX9D TXSTA_bits.TX9D
1015 #define TXD8 TXSTA_bits.TXD8
1016 #define TRMT TXSTA_bits.TRMT
1017 #define BRGH TXSTA_bits.BRGH
1018 #define SYNC TXSTA_bits.SYNC
1019 #define TXEN TXSTA_bits.TXEN
1020 #define TX9 TXSTA_bits.TX9
1021 #define NOT_TX8 TXSTA_bits.NOT_TX8
1022 #define TX8_9 TXSTA_bits.TX8_9
1023 #define CSRC TXSTA_bits.CSRC
1025 // ----- WDTCON bits --------------------
1028 unsigned char SWDTEN:1;
1029 unsigned char WDTPS0:1;
1030 unsigned char WDTPS1:1;
1031 unsigned char WDTPS2:1;
1032 unsigned char WDTPS3:1;
1038 unsigned char SWDTE:1;
1048 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1050 #define SWDTEN WDTCON_bits.SWDTEN
1051 #define SWDTE WDTCON_bits.SWDTE
1052 #define WDTPS0 WDTCON_bits.WDTPS0
1053 #define WDTPS1 WDTCON_bits.WDTPS1
1054 #define WDTPS2 WDTCON_bits.WDTPS2
1055 #define WDTPS3 WDTCON_bits.WDTPS3